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staging:iio:adc: unused header removals.
[deliverable/linux.git] / drivers / staging / iio / adc / max1363_core.c
1 /*
2 * iio/adc/max1363.c
3 * Copyright (C) 2008-2010 Jonathan Cameron
4 *
5 * based on linux/drivers/i2c/chips/max123x
6 * Copyright (C) 2002-2004 Stefan Eletzhofer
7 *
8 * based on linux/drivers/acron/char/pcf8583.c
9 * Copyright (C) 2000 Russell King
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 * max1363.c
16 *
17 * Partial support for max1363 and similar chips.
18 *
19 * Not currently implemented.
20 *
21 * - Control of internal reference.
22 */
23
24 #include <linux/interrupt.h>
25 #include <linux/device.h>
26 #include <linux/kernel.h>
27 #include <linux/sysfs.h>
28 #include <linux/list.h>
29 #include <linux/i2c.h>
30 #include <linux/regulator/consumer.h>
31 #include <linux/slab.h>
32 #include <linux/err.h>
33
34 #include "../iio.h"
35 #include "../sysfs.h"
36 #include "../ring_generic.h"
37
38 #include "max1363.h"
39
40 #define MAX1363_MODE_SINGLE(_num, _mask) { \
41 .conf = MAX1363_CHANNEL_SEL(_num) \
42 | MAX1363_CONFIG_SCAN_SINGLE_1 \
43 | MAX1363_CONFIG_SE, \
44 .modemask = _mask, \
45 }
46
47 #define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) { \
48 .conf = MAX1363_CHANNEL_SEL(_num) \
49 | MAX1363_CONFIG_SCAN_TO_CS \
50 | MAX1363_CONFIG_SE, \
51 .modemask = _mask, \
52 }
53
54 /* note not available for max1363 hence naming */
55 #define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) { \
56 .conf = MAX1363_CHANNEL_SEL(_num) \
57 | MAX1236_SCAN_MID_TO_CHANNEL \
58 | MAX1363_CONFIG_SE, \
59 .modemask = _mask \
60 }
61
62 #define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) { \
63 .conf = MAX1363_CHANNEL_SEL(_nump) \
64 | MAX1363_CONFIG_SCAN_SINGLE_1 \
65 | MAX1363_CONFIG_DE, \
66 .modemask = _mask \
67 }
68
69 /* Can't think how to automate naming so specify for now */
70 #define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) { \
71 .conf = MAX1363_CHANNEL_SEL(_num) \
72 | MAX1363_CONFIG_SCAN_TO_CS \
73 | MAX1363_CONFIG_DE, \
74 .modemask = _mask \
75 }
76
77 /* note only available for max1363 hence naming */
78 #define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) { \
79 .conf = MAX1363_CHANNEL_SEL(_num) \
80 | MAX1236_SCAN_MID_TO_CHANNEL \
81 | MAX1363_CONFIG_SE, \
82 .modemask = _mask \
83 }
84
85 static const struct max1363_mode max1363_mode_table[] = {
86 /* All of the single channel options first */
87 MAX1363_MODE_SINGLE(0, 1 << 0),
88 MAX1363_MODE_SINGLE(1, 1 << 1),
89 MAX1363_MODE_SINGLE(2, 1 << 2),
90 MAX1363_MODE_SINGLE(3, 1 << 3),
91 MAX1363_MODE_SINGLE(4, 1 << 4),
92 MAX1363_MODE_SINGLE(5, 1 << 5),
93 MAX1363_MODE_SINGLE(6, 1 << 6),
94 MAX1363_MODE_SINGLE(7, 1 << 7),
95 MAX1363_MODE_SINGLE(8, 1 << 8),
96 MAX1363_MODE_SINGLE(9, 1 << 9),
97 MAX1363_MODE_SINGLE(10, 1 << 10),
98 MAX1363_MODE_SINGLE(11, 1 << 11),
99
100 MAX1363_MODE_DIFF_SINGLE(0, 1, 1 << 12),
101 MAX1363_MODE_DIFF_SINGLE(2, 3, 1 << 13),
102 MAX1363_MODE_DIFF_SINGLE(4, 5, 1 << 14),
103 MAX1363_MODE_DIFF_SINGLE(6, 7, 1 << 15),
104 MAX1363_MODE_DIFF_SINGLE(8, 9, 1 << 16),
105 MAX1363_MODE_DIFF_SINGLE(10, 11, 1 << 17),
106 MAX1363_MODE_DIFF_SINGLE(1, 0, 1 << 18),
107 MAX1363_MODE_DIFF_SINGLE(3, 2, 1 << 19),
108 MAX1363_MODE_DIFF_SINGLE(5, 4, 1 << 20),
109 MAX1363_MODE_DIFF_SINGLE(7, 6, 1 << 21),
110 MAX1363_MODE_DIFF_SINGLE(9, 8, 1 << 22),
111 MAX1363_MODE_DIFF_SINGLE(11, 10, 1 << 23),
112
113 /* The multichannel scans next */
114 MAX1363_MODE_SCAN_TO_CHANNEL(1, 0x003),
115 MAX1363_MODE_SCAN_TO_CHANNEL(2, 0x007),
116 MAX1236_MODE_SCAN_MID_TO_CHANNEL(2, 3, 0x00C),
117 MAX1363_MODE_SCAN_TO_CHANNEL(3, 0x00F),
118 MAX1363_MODE_SCAN_TO_CHANNEL(4, 0x01F),
119 MAX1363_MODE_SCAN_TO_CHANNEL(5, 0x03F),
120 MAX1363_MODE_SCAN_TO_CHANNEL(6, 0x07F),
121 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 7, 0x0C0),
122 MAX1363_MODE_SCAN_TO_CHANNEL(7, 0x0FF),
123 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 8, 0x1C0),
124 MAX1363_MODE_SCAN_TO_CHANNEL(8, 0x1FF),
125 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 9, 0x3C0),
126 MAX1363_MODE_SCAN_TO_CHANNEL(9, 0x3FF),
127 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 10, 0x7C0),
128 MAX1363_MODE_SCAN_TO_CHANNEL(10, 0x7FF),
129 MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 11, 0xFC0),
130 MAX1363_MODE_SCAN_TO_CHANNEL(11, 0xFFF),
131
132 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(2, 2, 0x003000),
133 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(4, 3, 0x007000),
134 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(6, 4, 0x00F000),
135 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(8, 2, 0x018000),
136 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(8, 5, 0x01F000),
137 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(10, 3, 0x038000),
138 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(10, 6, 0x3F000),
139 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(3, 2, 0x0C0000),
140 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(5, 3, 0x1C0000),
141 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(7, 4, 0x3C0000),
142 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(9, 2, 0x600000),
143 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(9, 5, 0x7C0000),
144 MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(11, 3, 0xE00000),
145 MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(11, 6, 0xFC0000),
146 };
147
148 const struct max1363_mode
149 *max1363_match_mode(u32 mask, const struct max1363_chip_info *ci)
150 {
151 int i;
152 if (mask)
153 for (i = 0; i < ci->num_modes; i++)
154 if (!((~max1363_mode_table[ci->mode_list[i]].modemask) &
155 mask))
156 return &max1363_mode_table[ci->mode_list[i]];
157 return NULL;
158 }
159
160 static int max1363_write_basic_config(struct i2c_client *client,
161 unsigned char d1,
162 unsigned char d2)
163 {
164 u8 tx_buf[2] = {d1, d2};
165
166 return i2c_master_send(client, tx_buf, 2);
167 }
168
169 int max1363_set_scan_mode(struct max1363_state *st)
170 {
171 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
172 | MAX1363_SCAN_MASK
173 | MAX1363_SE_DE_MASK);
174 st->configbyte |= st->current_mode->conf;
175
176 return max1363_write_basic_config(st->client,
177 st->setupbyte,
178 st->configbyte);
179 }
180
181 static int max1363_read_single_chan(struct iio_dev *indio_dev,
182 struct iio_chan_spec const *chan,
183 int *val,
184 long m)
185 {
186 int ret = 0;
187 s32 data;
188 char rxbuf[2];
189 long mask;
190 struct max1363_state *st = iio_priv(indio_dev);
191 struct i2c_client *client = st->client;
192
193 mutex_lock(&indio_dev->mlock);
194 /*
195 * If monitor mode is enabled, the method for reading a single
196 * channel will have to be rather different and has not yet
197 * been implemented.
198 */
199 if (st->monitor_on) {
200 ret = -EBUSY;
201 goto error_ret;
202 }
203
204 /* If ring buffer capture is occurring, query the buffer */
205 if (iio_ring_enabled(indio_dev)) {
206 mask = max1363_mode_table[chan->address].modemask;
207 data = max1363_single_channel_from_ring(mask, st);
208 if (data < 0) {
209 ret = data;
210 goto error_ret;
211 }
212 } else {
213 /* Check to see if current scan mode is correct */
214 if (st->current_mode != &max1363_mode_table[chan->address]) {
215 /* Update scan mode if needed */
216 st->current_mode = &max1363_mode_table[chan->address];
217 ret = max1363_set_scan_mode(st);
218 if (ret < 0)
219 goto error_ret;
220 }
221 if (st->chip_info->bits != 8) {
222 /* Get reading */
223 data = i2c_master_recv(client, rxbuf, 2);
224 if (data < 0) {
225 ret = data;
226 goto error_ret;
227 }
228 data = (s32)(rxbuf[1]) | ((s32)(rxbuf[0] & 0x0F)) << 8;
229 } else {
230 /* Get reading */
231 data = i2c_master_recv(client, rxbuf, 1);
232 if (data < 0) {
233 ret = data;
234 goto error_ret;
235 }
236 data = rxbuf[0];
237 }
238 }
239 *val = data;
240 error_ret:
241 mutex_unlock(&indio_dev->mlock);
242 return ret;
243
244 }
245
246 static int max1363_read_raw(struct iio_dev *indio_dev,
247 struct iio_chan_spec const *chan,
248 int *val,
249 int *val2,
250 long m)
251 {
252 struct max1363_state *st = iio_priv(indio_dev);
253 int ret;
254 switch (m) {
255 case 0:
256 ret = max1363_read_single_chan(indio_dev, chan, val, m);
257 if (ret < 0)
258 return ret;
259 return IIO_VAL_INT;
260 case (1 << IIO_CHAN_INFO_SCALE_SHARED):
261 if ((1 << (st->chip_info->bits + 1)) >
262 st->chip_info->int_vref_mv) {
263 *val = 0;
264 *val2 = 500000;
265 return IIO_VAL_INT_PLUS_MICRO;
266 } else {
267 *val = (st->chip_info->int_vref_mv)
268 >> st->chip_info->bits;
269 return IIO_VAL_INT;
270 }
271 default:
272 return -EINVAL;
273 }
274 return 0;
275 }
276
277 /* Applies to max1363 */
278 static const enum max1363_modes max1363_mode_list[] = {
279 _s0, _s1, _s2, _s3,
280 s0to1, s0to2, s0to3,
281 d0m1, d2m3, d1m0, d3m2,
282 d0m1to2m3, d1m0to3m2,
283 };
284
285 #define MAX1363_EV_M \
286 (IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING) \
287 | IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING))
288 #define MAX1363_INFO_MASK (1 << IIO_CHAN_INFO_SCALE_SHARED)
289
290 static struct iio_chan_spec max1363_channels[] = {
291 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0, MAX1363_INFO_MASK,
292 _s0, 0, IIO_ST('u', 12, 16, 0), MAX1363_EV_M),
293 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0, MAX1363_INFO_MASK,
294 _s1, 1, IIO_ST('u', 12, 16, 0), MAX1363_EV_M),
295 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 2, 0, MAX1363_INFO_MASK,
296 _s2, 2, IIO_ST('u', 12, 16, 0), MAX1363_EV_M),
297 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 3, 0, MAX1363_INFO_MASK,
298 _s3, 3, IIO_ST('u', 12, 16, 0), MAX1363_EV_M),
299 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 0, 1, MAX1363_INFO_MASK,
300 d0m1, 4, IIO_ST('s', 12, 16, 0), MAX1363_EV_M),
301 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 2, 3, MAX1363_INFO_MASK,
302 d2m3, 5, IIO_ST('s', 12, 16, 0), MAX1363_EV_M),
303 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 1, 0, MAX1363_INFO_MASK,
304 d1m0, 6, IIO_ST('s', 12, 16, 0), MAX1363_EV_M),
305 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 3, 2, MAX1363_INFO_MASK,
306 d3m2, 7, IIO_ST('s', 12, 16, 0), MAX1363_EV_M),
307 IIO_CHAN_SOFT_TIMESTAMP(8)
308 };
309
310 static struct iio_chan_spec max1361_channels[] = {
311 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0, MAX1363_INFO_MASK,
312 _s0, 0, IIO_ST('u', 10, 16, 0), MAX1363_EV_M),
313 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0, MAX1363_INFO_MASK,
314 _s1, 1, IIO_ST('u', 10, 16, 0), MAX1363_EV_M),
315 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 2, 0, MAX1363_INFO_MASK,
316 _s2, 2, IIO_ST('u', 10, 16, 0), MAX1363_EV_M),
317 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 3, 0, MAX1363_INFO_MASK,
318 _s3, 3, IIO_ST('u', 10, 16, 0), MAX1363_EV_M),
319 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 0, 1, MAX1363_INFO_MASK,
320 d0m1, 4, IIO_ST('s', 10, 16, 0), MAX1363_EV_M),
321 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 2, 3, MAX1363_INFO_MASK,
322 d2m3, 5, IIO_ST('s', 10, 16, 0), MAX1363_EV_M),
323 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 1, 0, MAX1363_INFO_MASK,
324 d1m0, 6, IIO_ST('s', 10, 16, 0), MAX1363_EV_M),
325 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 3, 2, MAX1363_INFO_MASK,
326 d3m2, 7, IIO_ST('s', 10, 16, 0), MAX1363_EV_M),
327 IIO_CHAN_SOFT_TIMESTAMP(8)
328 };
329
330 #define MAX1363_CHAN_U(num, address, scan_index, bits) \
331 IIO_CHAN(IIO_IN, 0, 1, 0, NULL, num, 0, MAX1363_INFO_MASK, \
332 address, scan_index, IIO_ST('u', bits, \
333 (bits == 8) ? 8 : 16, 0), 0)
334 /* bipolar channel */
335 #define MAX1363_CHAN_B(num, num2, address, scan_index, bits) \
336 IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, num, num2, MAX1363_INFO_MASK,\
337 address, scan_index, IIO_ST('s', bits, \
338 (bits == 8) ? 8 : 16, 0), 0)
339
340 #define MAX1363_4X_CHANS(bits) { \
341 MAX1363_CHAN_U(0, _s0, 0, bits), \
342 MAX1363_CHAN_U(1, _s1, 1, bits), \
343 MAX1363_CHAN_U(2, _s2, 2, bits), \
344 MAX1363_CHAN_U(3, _s3, 3, bits), \
345 MAX1363_CHAN_B(0, 1, d0m1, 4, bits), \
346 MAX1363_CHAN_B(2, 3, d2m3, 5, bits), \
347 MAX1363_CHAN_B(1, 0, d1m0, 6, bits), \
348 MAX1363_CHAN_B(3, 2, d3m2, 7, bits), \
349 IIO_CHAN_SOFT_TIMESTAMP(8) \
350 }
351
352 static struct iio_chan_spec max1036_channels[] = MAX1363_4X_CHANS(8);
353 static struct iio_chan_spec max1136_channels[] = MAX1363_4X_CHANS(10);
354 static struct iio_chan_spec max1236_channels[] = MAX1363_4X_CHANS(12);
355
356 /* Appies to max1236, max1237 */
357 static const enum max1363_modes max1236_mode_list[] = {
358 _s0, _s1, _s2, _s3,
359 s0to1, s0to2, s0to3,
360 d0m1, d2m3, d1m0, d3m2,
361 d0m1to2m3, d1m0to3m2,
362 s2to3,
363 };
364
365 /* Applies to max1238, max1239 */
366 static const enum max1363_modes max1238_mode_list[] = {
367 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
368 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6,
369 s0to7, s0to8, s0to9, s0to10, s0to11,
370 d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
371 d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
372 d0m1to2m3, d0m1to4m5, d0m1to6m7, d0m1to8m9, d0m1to10m11,
373 d1m0to3m2, d1m0to5m4, d1m0to7m6, d1m0to9m8, d1m0to11m10,
374 s6to7, s6to8, s6to9, s6to10, s6to11,
375 d6m7to8m9, d6m7to10m11, d7m6to9m8, d7m6to11m10,
376 };
377
378 #define MAX1363_12X_CHANS(bits) { \
379 MAX1363_CHAN_U(0, _s0, 0, bits), \
380 MAX1363_CHAN_U(1, _s1, 1, bits), \
381 MAX1363_CHAN_U(2, _s2, 2, bits), \
382 MAX1363_CHAN_U(3, _s3, 3, bits), \
383 MAX1363_CHAN_U(4, _s4, 4, bits), \
384 MAX1363_CHAN_U(5, _s5, 5, bits), \
385 MAX1363_CHAN_U(6, _s6, 6, bits), \
386 MAX1363_CHAN_U(7, _s7, 7, bits), \
387 MAX1363_CHAN_U(8, _s8, 8, bits), \
388 MAX1363_CHAN_U(9, _s9, 9, bits), \
389 MAX1363_CHAN_U(10, _s10, 10, bits), \
390 MAX1363_CHAN_U(11, _s11, 11, bits), \
391 MAX1363_CHAN_B(0, 1, d0m1, 12, bits), \
392 MAX1363_CHAN_B(2, 3, d2m3, 13, bits), \
393 MAX1363_CHAN_B(4, 5, d4m5, 14, bits), \
394 MAX1363_CHAN_B(6, 7, d6m7, 15, bits), \
395 MAX1363_CHAN_B(8, 9, d8m9, 16, bits), \
396 MAX1363_CHAN_B(10, 11, d10m11, 17, bits), \
397 MAX1363_CHAN_B(1, 0, d1m0, 18, bits), \
398 MAX1363_CHAN_B(3, 2, d3m2, 19, bits), \
399 MAX1363_CHAN_B(5, 4, d5m4, 20, bits), \
400 MAX1363_CHAN_B(7, 6, d7m6, 21, bits), \
401 MAX1363_CHAN_B(9, 8, d9m8, 22, bits), \
402 MAX1363_CHAN_B(11, 10, d11m10, 23, bits), \
403 IIO_CHAN_SOFT_TIMESTAMP(24) \
404 }
405 static struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8);
406 static struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10);
407 static struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12);
408
409 static const enum max1363_modes max11607_mode_list[] = {
410 _s0, _s1, _s2, _s3,
411 s0to1, s0to2, s0to3,
412 s2to3,
413 d0m1, d2m3, d1m0, d3m2,
414 d0m1to2m3, d1m0to3m2,
415 };
416
417 static const enum max1363_modes max11608_mode_list[] = {
418 _s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7,
419 s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, s0to7,
420 s6to7,
421 d0m1, d2m3, d4m5, d6m7,
422 d1m0, d3m2, d5m4, d7m6,
423 d0m1to2m3, d0m1to4m5, d0m1to6m7,
424 d1m0to3m2, d1m0to5m4, d1m0to7m6,
425 };
426
427 #define MAX1363_8X_CHANS(bits) { \
428 MAX1363_CHAN_U(0, _s0, 0, bits), \
429 MAX1363_CHAN_U(1, _s1, 1, bits), \
430 MAX1363_CHAN_U(2, _s2, 2, bits), \
431 MAX1363_CHAN_U(3, _s3, 3, bits), \
432 MAX1363_CHAN_U(4, _s4, 4, bits), \
433 MAX1363_CHAN_U(5, _s5, 5, bits), \
434 MAX1363_CHAN_U(6, _s6, 6, bits), \
435 MAX1363_CHAN_U(7, _s7, 7, bits), \
436 MAX1363_CHAN_B(0, 1, d0m1, 8, bits), \
437 MAX1363_CHAN_B(2, 3, d2m3, 9, bits), \
438 MAX1363_CHAN_B(4, 5, d4m5, 10, bits), \
439 MAX1363_CHAN_B(6, 7, d6m7, 11, bits), \
440 MAX1363_CHAN_B(1, 0, d1m0, 12, bits), \
441 MAX1363_CHAN_B(3, 2, d3m2, 13, bits), \
442 MAX1363_CHAN_B(5, 4, d5m4, 14, bits), \
443 MAX1363_CHAN_B(7, 6, d7m6, 15, bits), \
444 IIO_CHAN_SOFT_TIMESTAMP(16) \
445 }
446 static struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8);
447 static struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10);
448 static struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12);
449
450 static const enum max1363_modes max11644_mode_list[] = {
451 _s0, _s1, s0to1, d0m1, d1m0,
452 };
453
454 #define MAX1363_2X_CHANS(bits) { \
455 MAX1363_CHAN_U(0, _s0, 0, bits), \
456 MAX1363_CHAN_U(1, _s1, 1, bits), \
457 MAX1363_CHAN_B(0, 1, d0m1, 2, bits), \
458 MAX1363_CHAN_B(1, 0, d1m0, 3, bits), \
459 IIO_CHAN_SOFT_TIMESTAMP(4) \
460 }
461
462 static struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10);
463 static struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12);
464
465 enum { max1361,
466 max1362,
467 max1363,
468 max1364,
469 max1036,
470 max1037,
471 max1038,
472 max1039,
473 max1136,
474 max1137,
475 max1138,
476 max1139,
477 max1236,
478 max1237,
479 max1238,
480 max1239,
481 max11600,
482 max11601,
483 max11602,
484 max11603,
485 max11604,
486 max11605,
487 max11606,
488 max11607,
489 max11608,
490 max11609,
491 max11610,
492 max11611,
493 max11612,
494 max11613,
495 max11614,
496 max11615,
497 max11616,
498 max11617,
499 max11644,
500 max11645,
501 max11646,
502 max11647
503 };
504
505 static const int max1363_monitor_speeds[] = { 133000, 665000, 33300, 16600,
506 8300, 4200, 2000, 1000 };
507
508 static ssize_t max1363_monitor_show_freq(struct device *dev,
509 struct device_attribute *attr,
510 char *buf)
511 {
512 struct max1363_state *st = iio_priv(dev_get_drvdata(dev));
513 return sprintf(buf, "%d\n", max1363_monitor_speeds[st->monitor_speed]);
514 }
515
516 static ssize_t max1363_monitor_store_freq(struct device *dev,
517 struct device_attribute *attr,
518 const char *buf,
519 size_t len)
520 {
521 struct iio_dev *indio_dev = dev_get_drvdata(dev);
522 struct max1363_state *st = iio_priv(indio_dev);
523 int i, ret;
524 unsigned long val;
525 bool found = false;
526
527 ret = strict_strtoul(buf, 10, &val);
528 if (ret)
529 return -EINVAL;
530 for (i = 0; i < ARRAY_SIZE(max1363_monitor_speeds); i++)
531 if (val == max1363_monitor_speeds[i]) {
532 found = true;
533 break;
534 }
535 if (!found)
536 return -EINVAL;
537
538 mutex_lock(&indio_dev->mlock);
539 st->monitor_speed = i;
540 mutex_unlock(&indio_dev->mlock);
541
542 return 0;
543 }
544
545 static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR,
546 max1363_monitor_show_freq,
547 max1363_monitor_store_freq);
548
549 static IIO_CONST_ATTR(sampling_frequency_available,
550 "133000 665000 33300 16600 8300 4200 2000 1000");
551
552 static int max1363_read_thresh(struct iio_dev *indio_dev,
553 int event_code,
554 int *val)
555 {
556 struct max1363_state *st = iio_priv(indio_dev);
557 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING)
558 *val = st->thresh_low[IIO_EVENT_CODE_EXTRACT_NUM(event_code)];
559 else
560 *val = st->thresh_high[IIO_EVENT_CODE_EXTRACT_NUM(event_code)];
561 return 0;
562 }
563
564 static int max1363_write_thresh(struct iio_dev *indio_dev,
565 int event_code,
566 int val)
567 {
568 struct max1363_state *st = iio_priv(indio_dev);
569 /* make it handle signed correctly as well */
570 switch (st->chip_info->bits) {
571 case 10:
572 if (val > 0x3FF)
573 return -EINVAL;
574 break;
575 case 12:
576 if (val > 0xFFF)
577 return -EINVAL;
578 break;
579 }
580
581 switch (IIO_EVENT_CODE_EXTRACT_DIR(event_code)) {
582 case IIO_EV_DIR_FALLING:
583 st->thresh_low[IIO_EVENT_CODE_EXTRACT_NUM(event_code)] = val;
584 break;
585 case IIO_EV_DIR_RISING:
586 st->thresh_high[IIO_EVENT_CODE_EXTRACT_NUM(event_code)] = val;
587 break;
588 }
589
590 return 0;
591 }
592
593 static const int max1363_event_codes[] = {
594 IIO_UNMOD_EVENT_CODE(IIO_EV_CLASS_IN, 0,
595 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
596 IIO_UNMOD_EVENT_CODE(IIO_EV_CLASS_IN, 1,
597 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
598 IIO_UNMOD_EVENT_CODE(IIO_EV_CLASS_IN, 2,
599 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
600 IIO_UNMOD_EVENT_CODE(IIO_EV_CLASS_IN, 3,
601 IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
602 IIO_UNMOD_EVENT_CODE(IIO_EV_CLASS_IN, 0,
603 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
604 IIO_UNMOD_EVENT_CODE(IIO_EV_CLASS_IN, 1,
605 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
606 IIO_UNMOD_EVENT_CODE(IIO_EV_CLASS_IN, 2,
607 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
608 IIO_UNMOD_EVENT_CODE(IIO_EV_CLASS_IN, 3,
609 IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
610 };
611
612 static irqreturn_t max1363_event_handler(int irq, void *private)
613 {
614 struct iio_dev *indio_dev = private;
615 struct max1363_state *st = iio_priv(indio_dev);
616 s64 timestamp = iio_get_time_ns();
617 unsigned long mask, loc;
618 u8 rx;
619 u8 tx[2] = { st->setupbyte,
620 MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0 };
621
622 i2c_master_recv(st->client, &rx, 1);
623 mask = rx;
624 for_each_set_bit(loc, &mask, 8)
625 iio_push_event(indio_dev, 0, max1363_event_codes[loc],
626 timestamp);
627 i2c_master_send(st->client, tx, 2);
628
629 return IRQ_HANDLED;
630 }
631
632 static int max1363_read_event_config(struct iio_dev *indio_dev,
633 int event_code)
634 {
635 struct max1363_state *st = iio_priv(indio_dev);
636
637 int val;
638 int number = IIO_EVENT_CODE_EXTRACT_NUM(event_code);
639 mutex_lock(&indio_dev->mlock);
640 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING)
641 val = (1 << number) & st->mask_low;
642 else
643 val = (1 << number) & st->mask_high;
644 mutex_unlock(&indio_dev->mlock);
645
646 return val;
647 }
648
649 static int max1363_monitor_mode_update(struct max1363_state *st, int enabled)
650 {
651 u8 *tx_buf;
652 int ret, i = 3, j;
653 unsigned long numelements;
654 int len;
655 long modemask;
656
657 if (!enabled) {
658 /* transition to ring capture is not currently supported */
659 st->setupbyte &= ~MAX1363_SETUP_MONITOR_SETUP;
660 st->configbyte &= ~MAX1363_SCAN_MASK;
661 st->monitor_on = false;
662 return max1363_write_basic_config(st->client,
663 st->setupbyte,
664 st->configbyte);
665 }
666
667 /* Ensure we are in the relevant mode */
668 st->setupbyte |= MAX1363_SETUP_MONITOR_SETUP;
669 st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
670 | MAX1363_SCAN_MASK
671 | MAX1363_SE_DE_MASK);
672 st->configbyte |= MAX1363_CONFIG_SCAN_MONITOR_MODE;
673 if ((st->mask_low | st->mask_high) & 0x0F) {
674 st->configbyte |= max1363_mode_table[s0to3].conf;
675 modemask = max1363_mode_table[s0to3].modemask;
676 } else if ((st->mask_low | st->mask_high) & 0x30) {
677 st->configbyte |= max1363_mode_table[d0m1to2m3].conf;
678 modemask = max1363_mode_table[d0m1to2m3].modemask;
679 } else {
680 st->configbyte |= max1363_mode_table[d1m0to3m2].conf;
681 modemask = max1363_mode_table[d1m0to3m2].modemask;
682 }
683 numelements = hweight_long(modemask);
684 len = 3 * numelements + 3;
685 tx_buf = kmalloc(len, GFP_KERNEL);
686 if (!tx_buf) {
687 ret = -ENOMEM;
688 goto error_ret;
689 }
690 tx_buf[0] = st->configbyte;
691 tx_buf[1] = st->setupbyte;
692 tx_buf[2] = (st->monitor_speed << 1);
693
694 /*
695 * So we need to do yet another bit of nefarious scan mode
696 * setup to match what we need.
697 */
698 for (j = 0; j < 8; j++)
699 if (modemask & (1 << j)) {
700 /* Establish the mode is in the scan */
701 if (st->mask_low & (1 << j)) {
702 tx_buf[i] = (st->thresh_low[j] >> 4) & 0xFF;
703 tx_buf[i + 1] = (st->thresh_low[j] << 4) & 0xF0;
704 } else if (j < 4) {
705 tx_buf[i] = 0;
706 tx_buf[i + 1] = 0;
707 } else {
708 tx_buf[i] = 0x80;
709 tx_buf[i + 1] = 0;
710 }
711 if (st->mask_high & (1 << j)) {
712 tx_buf[i + 1] |=
713 (st->thresh_high[j] >> 8) & 0x0F;
714 tx_buf[i + 2] = st->thresh_high[j] & 0xFF;
715 } else if (j < 4) {
716 tx_buf[i + 1] |= 0x0F;
717 tx_buf[i + 2] = 0xFF;
718 } else {
719 tx_buf[i + 1] |= 0x07;
720 tx_buf[i + 2] = 0xFF;
721 }
722 i += 3;
723 }
724
725
726 ret = i2c_master_send(st->client, tx_buf, len);
727 if (ret < 0)
728 goto error_ret;
729 if (ret != len) {
730 ret = -EIO;
731 goto error_ret;
732 }
733
734 /*
735 * Now that we hopefully have sensible thresholds in place it is
736 * time to turn the interrupts on.
737 * It is unclear from the data sheet if this should be necessary
738 * (i.e. whether monitor mode setup is atomic) but it appears to
739 * be in practice.
740 */
741 tx_buf[0] = st->setupbyte;
742 tx_buf[1] = MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0;
743 ret = i2c_master_send(st->client, tx_buf, 2);
744 if (ret < 0)
745 goto error_ret;
746 if (ret != 2) {
747 ret = -EIO;
748 goto error_ret;
749 }
750 ret = 0;
751 st->monitor_on = true;
752 error_ret:
753
754 kfree(tx_buf);
755
756 return ret;
757 }
758
759 /*
760 * To keep this manageable we always use one of 3 scan modes.
761 * Scan 0...3, 0-1,2-3 and 1-0,3-2
762 */
763
764 static inline int __max1363_check_event_mask(int thismask, int checkmask)
765 {
766 int ret = 0;
767 /* Is it unipolar */
768 if (thismask < 4) {
769 if (checkmask & ~0x0F) {
770 ret = -EBUSY;
771 goto error_ret;
772 }
773 } else if (thismask < 6) {
774 if (checkmask & ~0x30) {
775 ret = -EBUSY;
776 goto error_ret;
777 }
778 } else if (checkmask & ~0xC0)
779 ret = -EBUSY;
780 error_ret:
781 return ret;
782 }
783
784 static int max1363_write_event_config(struct iio_dev *indio_dev,
785 int event_code,
786 int state)
787 {
788 int ret = 0;
789 struct max1363_state *st = iio_priv(indio_dev);
790 u16 unifiedmask;
791 int number = IIO_EVENT_CODE_EXTRACT_NUM(event_code);
792
793 mutex_lock(&indio_dev->mlock);
794 unifiedmask = st->mask_low | st->mask_high;
795 if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING) {
796
797 if (state == 0)
798 st->mask_low &= ~(1 << number);
799 else {
800 ret = __max1363_check_event_mask((1 << number),
801 unifiedmask);
802 if (ret)
803 goto error_ret;
804 st->mask_low |= (1 << number);
805 }
806 } else {
807 if (state == 0)
808 st->mask_high &= ~(1 << number);
809 else {
810 ret = __max1363_check_event_mask((1 << number),
811 unifiedmask);
812 if (ret)
813 goto error_ret;
814 st->mask_high |= (1 << number);
815 }
816 }
817
818 max1363_monitor_mode_update(st, !!(st->mask_high | st->mask_low));
819 error_ret:
820 mutex_unlock(&indio_dev->mlock);
821
822 return ret;
823 }
824
825 /*
826 * As with scan_elements, only certain sets of these can
827 * be combined.
828 */
829 static struct attribute *max1363_event_attributes[] = {
830 &iio_dev_attr_sampling_frequency.dev_attr.attr,
831 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
832 NULL,
833 };
834
835 static struct attribute_group max1363_event_attribute_group = {
836 .attrs = max1363_event_attributes,
837 };
838
839 #define MAX1363_EVENT_FUNCS \
840
841
842 static const struct iio_info max1238_info = {
843 .read_raw = &max1363_read_raw,
844 .driver_module = THIS_MODULE,
845 };
846
847 static const struct iio_info max1363_info = {
848 .read_event_value = &max1363_read_thresh,
849 .write_event_value = &max1363_write_thresh,
850 .read_event_config = &max1363_read_event_config,
851 .write_event_config = &max1363_write_event_config,
852 .read_raw = &max1363_read_raw,
853 .driver_module = THIS_MODULE,
854 .num_interrupt_lines = 1,
855 .event_attrs = &max1363_event_attribute_group,
856 };
857
858 /* max1363 and max1368 tested - rest from data sheet */
859 static const struct max1363_chip_info max1363_chip_info_tbl[] = {
860 [max1361] = {
861 .bits = 10,
862 .int_vref_mv = 2048,
863 .mode_list = max1363_mode_list,
864 .num_modes = ARRAY_SIZE(max1363_mode_list),
865 .default_mode = s0to3,
866 .channels = max1361_channels,
867 .num_channels = ARRAY_SIZE(max1361_channels),
868 .info = &max1363_info,
869 },
870 [max1362] = {
871 .bits = 10,
872 .int_vref_mv = 4096,
873 .mode_list = max1363_mode_list,
874 .num_modes = ARRAY_SIZE(max1363_mode_list),
875 .default_mode = s0to3,
876 .channels = max1361_channels,
877 .num_channels = ARRAY_SIZE(max1361_channels),
878 .info = &max1363_info,
879 },
880 [max1363] = {
881 .bits = 12,
882 .int_vref_mv = 2048,
883 .mode_list = max1363_mode_list,
884 .num_modes = ARRAY_SIZE(max1363_mode_list),
885 .default_mode = s0to3,
886 .channels = max1363_channels,
887 .num_channels = ARRAY_SIZE(max1363_channels),
888 .info = &max1363_info,
889 },
890 [max1364] = {
891 .bits = 12,
892 .int_vref_mv = 4096,
893 .mode_list = max1363_mode_list,
894 .num_modes = ARRAY_SIZE(max1363_mode_list),
895 .default_mode = s0to3,
896 .channels = max1363_channels,
897 .num_channels = ARRAY_SIZE(max1363_channels),
898 .info = &max1363_info,
899 },
900 [max1036] = {
901 .bits = 8,
902 .int_vref_mv = 4096,
903 .mode_list = max1236_mode_list,
904 .num_modes = ARRAY_SIZE(max1236_mode_list),
905 .default_mode = s0to3,
906 .info = &max1238_info,
907 .channels = max1036_channels,
908 .num_channels = ARRAY_SIZE(max1036_channels),
909 },
910 [max1037] = {
911 .bits = 8,
912 .int_vref_mv = 2048,
913 .mode_list = max1236_mode_list,
914 .num_modes = ARRAY_SIZE(max1236_mode_list),
915 .default_mode = s0to3,
916 .info = &max1238_info,
917 .channels = max1036_channels,
918 .num_channels = ARRAY_SIZE(max1036_channels),
919 },
920 [max1038] = {
921 .bits = 8,
922 .int_vref_mv = 4096,
923 .mode_list = max1238_mode_list,
924 .num_modes = ARRAY_SIZE(max1238_mode_list),
925 .default_mode = s0to11,
926 .info = &max1238_info,
927 .channels = max1038_channels,
928 .num_channels = ARRAY_SIZE(max1038_channels),
929 },
930 [max1039] = {
931 .bits = 8,
932 .int_vref_mv = 2048,
933 .mode_list = max1238_mode_list,
934 .num_modes = ARRAY_SIZE(max1238_mode_list),
935 .default_mode = s0to11,
936 .info = &max1238_info,
937 .channels = max1038_channels,
938 .num_channels = ARRAY_SIZE(max1038_channels),
939 },
940 [max1136] = {
941 .bits = 10,
942 .int_vref_mv = 4096,
943 .mode_list = max1236_mode_list,
944 .num_modes = ARRAY_SIZE(max1236_mode_list),
945 .default_mode = s0to3,
946 .info = &max1238_info,
947 .channels = max1136_channels,
948 .num_channels = ARRAY_SIZE(max1136_channels),
949 },
950 [max1137] = {
951 .bits = 10,
952 .int_vref_mv = 2048,
953 .mode_list = max1236_mode_list,
954 .num_modes = ARRAY_SIZE(max1236_mode_list),
955 .default_mode = s0to3,
956 .info = &max1238_info,
957 .channels = max1136_channels,
958 .num_channels = ARRAY_SIZE(max1136_channels),
959 },
960 [max1138] = {
961 .bits = 10,
962 .int_vref_mv = 4096,
963 .mode_list = max1238_mode_list,
964 .num_modes = ARRAY_SIZE(max1238_mode_list),
965 .default_mode = s0to11,
966 .info = &max1238_info,
967 .channels = max1138_channels,
968 .num_channels = ARRAY_SIZE(max1138_channels),
969 },
970 [max1139] = {
971 .bits = 10,
972 .int_vref_mv = 2048,
973 .mode_list = max1238_mode_list,
974 .num_modes = ARRAY_SIZE(max1238_mode_list),
975 .default_mode = s0to11,
976 .info = &max1238_info,
977 .channels = max1138_channels,
978 .num_channels = ARRAY_SIZE(max1138_channels),
979 },
980 [max1236] = {
981 .bits = 12,
982 .int_vref_mv = 4096,
983 .mode_list = max1236_mode_list,
984 .num_modes = ARRAY_SIZE(max1236_mode_list),
985 .default_mode = s0to3,
986 .info = &max1238_info,
987 .channels = max1236_channels,
988 .num_channels = ARRAY_SIZE(max1236_channels),
989 },
990 [max1237] = {
991 .bits = 12,
992 .int_vref_mv = 2048,
993 .mode_list = max1236_mode_list,
994 .num_modes = ARRAY_SIZE(max1236_mode_list),
995 .default_mode = s0to3,
996 .info = &max1238_info,
997 .channels = max1236_channels,
998 .num_channels = ARRAY_SIZE(max1236_channels),
999 },
1000 [max1238] = {
1001 .bits = 12,
1002 .int_vref_mv = 4096,
1003 .mode_list = max1238_mode_list,
1004 .num_modes = ARRAY_SIZE(max1238_mode_list),
1005 .default_mode = s0to11,
1006 .info = &max1238_info,
1007 .channels = max1238_channels,
1008 .num_channels = ARRAY_SIZE(max1238_channels),
1009 },
1010 [max1239] = {
1011 .bits = 12,
1012 .int_vref_mv = 2048,
1013 .mode_list = max1238_mode_list,
1014 .num_modes = ARRAY_SIZE(max1238_mode_list),
1015 .default_mode = s0to11,
1016 .info = &max1238_info,
1017 .channels = max1238_channels,
1018 .num_channels = ARRAY_SIZE(max1238_channels),
1019 },
1020 [max11600] = {
1021 .bits = 8,
1022 .int_vref_mv = 4096,
1023 .mode_list = max11607_mode_list,
1024 .num_modes = ARRAY_SIZE(max11607_mode_list),
1025 .default_mode = s0to3,
1026 .info = &max1238_info,
1027 .channels = max1036_channels,
1028 .num_channels = ARRAY_SIZE(max1036_channels),
1029 },
1030 [max11601] = {
1031 .bits = 8,
1032 .int_vref_mv = 2048,
1033 .mode_list = max11607_mode_list,
1034 .num_modes = ARRAY_SIZE(max11607_mode_list),
1035 .default_mode = s0to3,
1036 .info = &max1238_info,
1037 .channels = max1036_channels,
1038 .num_channels = ARRAY_SIZE(max1036_channels),
1039 },
1040 [max11602] = {
1041 .bits = 8,
1042 .int_vref_mv = 4096,
1043 .mode_list = max11608_mode_list,
1044 .num_modes = ARRAY_SIZE(max11608_mode_list),
1045 .default_mode = s0to7,
1046 .info = &max1238_info,
1047 .channels = max11602_channels,
1048 .num_channels = ARRAY_SIZE(max11602_channels),
1049 },
1050 [max11603] = {
1051 .bits = 8,
1052 .int_vref_mv = 2048,
1053 .mode_list = max11608_mode_list,
1054 .num_modes = ARRAY_SIZE(max11608_mode_list),
1055 .default_mode = s0to7,
1056 .info = &max1238_info,
1057 .channels = max11602_channels,
1058 .num_channels = ARRAY_SIZE(max11602_channels),
1059 },
1060 [max11604] = {
1061 .bits = 8,
1062 .int_vref_mv = 4098,
1063 .mode_list = max1238_mode_list,
1064 .num_modes = ARRAY_SIZE(max1238_mode_list),
1065 .default_mode = s0to11,
1066 .info = &max1238_info,
1067 .channels = max1238_channels,
1068 .num_channels = ARRAY_SIZE(max1238_channels),
1069 },
1070 [max11605] = {
1071 .bits = 8,
1072 .int_vref_mv = 2048,
1073 .mode_list = max1238_mode_list,
1074 .num_modes = ARRAY_SIZE(max1238_mode_list),
1075 .default_mode = s0to11,
1076 .info = &max1238_info,
1077 .channels = max1238_channels,
1078 .num_channels = ARRAY_SIZE(max1238_channels),
1079 },
1080 [max11606] = {
1081 .bits = 10,
1082 .int_vref_mv = 4096,
1083 .mode_list = max11607_mode_list,
1084 .num_modes = ARRAY_SIZE(max11607_mode_list),
1085 .default_mode = s0to3,
1086 .info = &max1238_info,
1087 .channels = max1136_channels,
1088 .num_channels = ARRAY_SIZE(max1136_channels),
1089 },
1090 [max11607] = {
1091 .bits = 10,
1092 .int_vref_mv = 2048,
1093 .mode_list = max11607_mode_list,
1094 .num_modes = ARRAY_SIZE(max11607_mode_list),
1095 .default_mode = s0to3,
1096 .info = &max1238_info,
1097 .channels = max1136_channels,
1098 .num_channels = ARRAY_SIZE(max1136_channels),
1099 },
1100 [max11608] = {
1101 .bits = 10,
1102 .int_vref_mv = 4096,
1103 .mode_list = max11608_mode_list,
1104 .num_modes = ARRAY_SIZE(max11608_mode_list),
1105 .default_mode = s0to7,
1106 .info = &max1238_info,
1107 .channels = max11608_channels,
1108 .num_channels = ARRAY_SIZE(max11608_channels),
1109 },
1110 [max11609] = {
1111 .bits = 10,
1112 .int_vref_mv = 2048,
1113 .mode_list = max11608_mode_list,
1114 .num_modes = ARRAY_SIZE(max11608_mode_list),
1115 .default_mode = s0to7,
1116 .info = &max1238_info,
1117 .channels = max11608_channels,
1118 .num_channels = ARRAY_SIZE(max11608_channels),
1119 },
1120 [max11610] = {
1121 .bits = 10,
1122 .int_vref_mv = 4098,
1123 .mode_list = max1238_mode_list,
1124 .num_modes = ARRAY_SIZE(max1238_mode_list),
1125 .default_mode = s0to11,
1126 .info = &max1238_info,
1127 .channels = max1238_channels,
1128 .num_channels = ARRAY_SIZE(max1238_channels),
1129 },
1130 [max11611] = {
1131 .bits = 10,
1132 .int_vref_mv = 2048,
1133 .mode_list = max1238_mode_list,
1134 .num_modes = ARRAY_SIZE(max1238_mode_list),
1135 .default_mode = s0to11,
1136 .info = &max1238_info,
1137 .channels = max1238_channels,
1138 .num_channels = ARRAY_SIZE(max1238_channels),
1139 },
1140 [max11612] = {
1141 .bits = 12,
1142 .int_vref_mv = 4096,
1143 .mode_list = max11607_mode_list,
1144 .num_modes = ARRAY_SIZE(max11607_mode_list),
1145 .default_mode = s0to3,
1146 .info = &max1238_info,
1147 .channels = max1363_channels,
1148 .num_channels = ARRAY_SIZE(max1363_channels),
1149 },
1150 [max11613] = {
1151 .bits = 12,
1152 .int_vref_mv = 2048,
1153 .mode_list = max11607_mode_list,
1154 .num_modes = ARRAY_SIZE(max11607_mode_list),
1155 .default_mode = s0to3,
1156 .info = &max1238_info,
1157 .channels = max1363_channels,
1158 .num_channels = ARRAY_SIZE(max1363_channels),
1159 },
1160 [max11614] = {
1161 .bits = 12,
1162 .int_vref_mv = 4096,
1163 .mode_list = max11608_mode_list,
1164 .num_modes = ARRAY_SIZE(max11608_mode_list),
1165 .default_mode = s0to7,
1166 .info = &max1238_info,
1167 .channels = max11614_channels,
1168 .num_channels = ARRAY_SIZE(max11614_channels),
1169 },
1170 [max11615] = {
1171 .bits = 12,
1172 .int_vref_mv = 2048,
1173 .mode_list = max11608_mode_list,
1174 .num_modes = ARRAY_SIZE(max11608_mode_list),
1175 .default_mode = s0to7,
1176 .info = &max1238_info,
1177 .channels = max11614_channels,
1178 .num_channels = ARRAY_SIZE(max11614_channels),
1179 },
1180 [max11616] = {
1181 .bits = 12,
1182 .int_vref_mv = 4098,
1183 .mode_list = max1238_mode_list,
1184 .num_modes = ARRAY_SIZE(max1238_mode_list),
1185 .default_mode = s0to11,
1186 .info = &max1238_info,
1187 .channels = max1238_channels,
1188 .num_channels = ARRAY_SIZE(max1238_channels),
1189 },
1190 [max11617] = {
1191 .bits = 12,
1192 .int_vref_mv = 2048,
1193 .mode_list = max1238_mode_list,
1194 .num_modes = ARRAY_SIZE(max1238_mode_list),
1195 .default_mode = s0to11,
1196 .info = &max1238_info,
1197 .channels = max1238_channels,
1198 .num_channels = ARRAY_SIZE(max1238_channels),
1199 },
1200 [max11644] = {
1201 .bits = 12,
1202 .int_vref_mv = 2048,
1203 .mode_list = max11644_mode_list,
1204 .num_modes = ARRAY_SIZE(max11644_mode_list),
1205 .default_mode = s0to1,
1206 .info = &max1238_info,
1207 .channels = max11644_channels,
1208 .num_channels = ARRAY_SIZE(max11644_channels),
1209 },
1210 [max11645] = {
1211 .bits = 12,
1212 .int_vref_mv = 4096,
1213 .mode_list = max11644_mode_list,
1214 .num_modes = ARRAY_SIZE(max11644_mode_list),
1215 .default_mode = s0to1,
1216 .info = &max1238_info,
1217 .channels = max11644_channels,
1218 .num_channels = ARRAY_SIZE(max11644_channels),
1219 },
1220 [max11646] = {
1221 .bits = 10,
1222 .int_vref_mv = 2048,
1223 .mode_list = max11644_mode_list,
1224 .num_modes = ARRAY_SIZE(max11644_mode_list),
1225 .default_mode = s0to1,
1226 .info = &max1238_info,
1227 .channels = max11646_channels,
1228 .num_channels = ARRAY_SIZE(max11646_channels),
1229 },
1230 [max11647] = {
1231 .bits = 10,
1232 .int_vref_mv = 4096,
1233 .mode_list = max11644_mode_list,
1234 .num_modes = ARRAY_SIZE(max11644_mode_list),
1235 .default_mode = s0to1,
1236 .info = &max1238_info,
1237 .channels = max11646_channels,
1238 .num_channels = ARRAY_SIZE(max11646_channels),
1239 },
1240 };
1241
1242
1243
1244 static int max1363_initial_setup(struct max1363_state *st)
1245 {
1246 st->setupbyte = MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD
1247 | MAX1363_SETUP_POWER_UP_INT_REF
1248 | MAX1363_SETUP_INT_CLOCK
1249 | MAX1363_SETUP_UNIPOLAR
1250 | MAX1363_SETUP_NORESET;
1251
1252 /* Set scan mode writes the config anyway so wait until then*/
1253 st->setupbyte = MAX1363_SETUP_BYTE(st->setupbyte);
1254 st->current_mode = &max1363_mode_table[st->chip_info->default_mode];
1255 st->configbyte = MAX1363_CONFIG_BYTE(st->configbyte);
1256
1257 return max1363_set_scan_mode(st);
1258 }
1259
1260 static int __devinit max1363_probe(struct i2c_client *client,
1261 const struct i2c_device_id *id)
1262 {
1263 int ret, i, regdone = 0;
1264 struct max1363_state *st;
1265 struct iio_dev *indio_dev;
1266 struct regulator *reg;
1267
1268 reg = regulator_get(&client->dev, "vcc");
1269 if (IS_ERR(reg)) {
1270 ret = PTR_ERR(reg);
1271 goto error_out;
1272 }
1273
1274 ret = regulator_enable(reg);
1275 if (ret)
1276 goto error_put_reg;
1277
1278 indio_dev = iio_allocate_device(sizeof(struct max1363_state));
1279 if (indio_dev == NULL) {
1280 ret = -ENOMEM;
1281 goto error_disable_reg;
1282 }
1283 st = iio_priv(indio_dev);
1284 st->reg = reg;
1285 /* this is only used for device removal purposes */
1286 i2c_set_clientdata(client, indio_dev);
1287
1288 st->chip_info = &max1363_chip_info_tbl[id->driver_data];
1289 st->client = client;
1290
1291 indio_dev->available_scan_masks
1292 = kzalloc(sizeof(*indio_dev->available_scan_masks)*
1293 (st->chip_info->num_modes + 1), GFP_KERNEL);
1294 if (!indio_dev->available_scan_masks) {
1295 ret = -ENOMEM;
1296 goto error_free_device;
1297 }
1298
1299 for (i = 0; i < st->chip_info->num_modes; i++)
1300 indio_dev->available_scan_masks[i] =
1301 max1363_mode_table[st->chip_info->mode_list[i]]
1302 .modemask;
1303 /* Estabilish that the iio_dev is a child of the i2c device */
1304 indio_dev->dev.parent = &client->dev;
1305 indio_dev->name = id->name;
1306
1307 indio_dev->info = st->chip_info->info;
1308 indio_dev->modes = INDIO_DIRECT_MODE;
1309 indio_dev->channels = st->chip_info->channels;
1310 indio_dev->num_channels = st->chip_info->num_channels;
1311 ret = max1363_initial_setup(st);
1312 if (ret < 0)
1313 goto error_free_available_scan_masks;
1314
1315 ret = max1363_register_ring_funcs_and_init(indio_dev);
1316 if (ret)
1317 goto error_free_available_scan_masks;
1318
1319 ret = iio_device_register(indio_dev);
1320 if (ret)
1321 goto error_cleanup_ring;
1322 regdone = 1;
1323 ret = iio_ring_buffer_register_ex(indio_dev->ring, 0,
1324 st->chip_info->channels,
1325 st->chip_info->num_channels);
1326 if (ret)
1327 goto error_cleanup_ring;
1328
1329 if (client->irq) {
1330 ret = request_threaded_irq(st->client->irq,
1331 NULL,
1332 &max1363_event_handler,
1333 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1334 "max1363_event",
1335 indio_dev);
1336
1337 if (ret)
1338 goto error_uninit_ring;
1339 }
1340
1341 return 0;
1342
1343 error_uninit_ring:
1344 iio_ring_buffer_unregister(indio_dev->ring);
1345 error_cleanup_ring:
1346 max1363_ring_cleanup(indio_dev);
1347 error_free_available_scan_masks:
1348 kfree(indio_dev->available_scan_masks);
1349 error_free_device:
1350 if (!regdone)
1351 iio_free_device(indio_dev);
1352 else
1353 iio_device_unregister(indio_dev);
1354 error_disable_reg:
1355 regulator_disable(reg);
1356 error_put_reg:
1357 regulator_put(reg);
1358 error_out:
1359 return ret;
1360 }
1361
1362 static int max1363_remove(struct i2c_client *client)
1363 {
1364 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1365 struct max1363_state *st = iio_priv(indio_dev);
1366 struct regulator *reg = st->reg;
1367
1368 if (client->irq)
1369 free_irq(st->client->irq, indio_dev);
1370 iio_ring_buffer_unregister(indio_dev->ring);
1371 max1363_ring_cleanup(indio_dev);
1372 kfree(indio_dev->available_scan_masks);
1373 if (!IS_ERR(reg)) {
1374 regulator_disable(reg);
1375 regulator_put(reg);
1376 }
1377 iio_device_unregister(indio_dev);
1378
1379 return 0;
1380 }
1381
1382 static const struct i2c_device_id max1363_id[] = {
1383 { "max1361", max1361 },
1384 { "max1362", max1362 },
1385 { "max1363", max1363 },
1386 { "max1364", max1364 },
1387 { "max1036", max1036 },
1388 { "max1037", max1037 },
1389 { "max1038", max1038 },
1390 { "max1039", max1039 },
1391 { "max1136", max1136 },
1392 { "max1137", max1137 },
1393 { "max1138", max1138 },
1394 { "max1139", max1139 },
1395 { "max1236", max1236 },
1396 { "max1237", max1237 },
1397 { "max1238", max1238 },
1398 { "max1239", max1239 },
1399 { "max11600", max11600 },
1400 { "max11601", max11601 },
1401 { "max11602", max11602 },
1402 { "max11603", max11603 },
1403 { "max11604", max11604 },
1404 { "max11605", max11605 },
1405 { "max11606", max11606 },
1406 { "max11607", max11607 },
1407 { "max11608", max11608 },
1408 { "max11609", max11609 },
1409 { "max11610", max11610 },
1410 { "max11611", max11611 },
1411 { "max11612", max11612 },
1412 { "max11613", max11613 },
1413 { "max11614", max11614 },
1414 { "max11615", max11615 },
1415 { "max11616", max11616 },
1416 { "max11617", max11617 },
1417 {}
1418 };
1419
1420 MODULE_DEVICE_TABLE(i2c, max1363_id);
1421
1422 static struct i2c_driver max1363_driver = {
1423 .driver = {
1424 .name = "max1363",
1425 },
1426 .probe = max1363_probe,
1427 .remove = max1363_remove,
1428 .id_table = max1363_id,
1429 };
1430
1431 static __init int max1363_init(void)
1432 {
1433 return i2c_add_driver(&max1363_driver);
1434 }
1435
1436 static __exit void max1363_exit(void)
1437 {
1438 i2c_del_driver(&max1363_driver);
1439 }
1440
1441 MODULE_AUTHOR("Jonathan Cameron <jic23@cam.ac.uk>");
1442 MODULE_DESCRIPTION("Maxim 1363 ADC");
1443 MODULE_LICENSE("GPL v2");
1444
1445 module_init(max1363_init);
1446 module_exit(max1363_exit);
Linux kernel - Deliverables
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