99d1cceaa3de1bc7570132dac142e9bcd004950f
2 * Copyright 2005-2009 Freescale Semiconductor, Inc.
4 * The code contained herein is licensed under the GNU Lesser General
5 * Public License. You may obtain a copy of the GNU Lesser General
6 * Public License Version 2.1 or later at the following locations:
8 * http://www.opensource.org/licenses/lgpl-license.html
9 * http://www.gnu.org/copyleft/lgpl.html
15 #include <linux/types.h>
16 #include <linux/videodev2.h>
17 #include <linux/bitmap.h>
29 * Bitfield of Display Interface signal polarities.
31 struct ipu_di_signal_cfg
{
32 unsigned datamask_en
:1;
33 unsigned interlaced
:1;
34 unsigned odd_field_first
:1;
36 unsigned clkidle_en
:1;
37 unsigned data_pol
:1; /* true = inverted */
38 unsigned clk_pol
:1; /* true = rising edge */
39 unsigned enable_pol
:1;
40 unsigned Hsync_pol
:1; /* true = active high */
53 unsigned long pixelclock
;
54 #define IPU_DI_CLKMODE_SYNC (1 << 0)
55 #define IPU_DI_CLKMODE_EXT (1 << 1)
56 unsigned long clkflags
;
59 enum ipu_color_space
{
62 IPUV3_COLORSPACE_UNKNOWN
,
67 enum ipu_channel_irq
{
70 IPU_IRQ_NFB4EOF
= 128,
74 int ipu_idmac_channel_irq(struct ipu_soc
*ipu
, struct ipuv3_channel
*channel
,
75 enum ipu_channel_irq irq
);
77 #define IPU_IRQ_DP_SF_START (448 + 2)
78 #define IPU_IRQ_DP_SF_END (448 + 3)
79 #define IPU_IRQ_BG_SF_END IPU_IRQ_DP_SF_END,
80 #define IPU_IRQ_DC_FC_0 (448 + 8)
81 #define IPU_IRQ_DC_FC_1 (448 + 9)
82 #define IPU_IRQ_DC_FC_2 (448 + 10)
83 #define IPU_IRQ_DC_FC_3 (448 + 11)
84 #define IPU_IRQ_DC_FC_4 (448 + 12)
85 #define IPU_IRQ_DC_FC_6 (448 + 13)
86 #define IPU_IRQ_VSYNC_PRE_0 (448 + 14)
87 #define IPU_IRQ_VSYNC_PRE_1 (448 + 15)
90 * IPU Image DMA Controller (idmac) functions
92 struct ipuv3_channel
*ipu_idmac_get(struct ipu_soc
*ipu
, unsigned channel
);
93 void ipu_idmac_put(struct ipuv3_channel
*);
95 int ipu_idmac_enable_channel(struct ipuv3_channel
*channel
);
96 int ipu_idmac_disable_channel(struct ipuv3_channel
*channel
);
98 void ipu_idmac_set_double_buffer(struct ipuv3_channel
*channel
,
100 void ipu_idmac_select_buffer(struct ipuv3_channel
*channel
, u32 buf_num
);
103 * IPU Display Controller (dc) functions
107 struct ipu_dc
*ipu_dc_get(struct ipu_soc
*ipu
, int channel
);
108 void ipu_dc_put(struct ipu_dc
*dc
);
109 int ipu_dc_init_sync(struct ipu_dc
*dc
, struct ipu_di
*di
, bool interlaced
,
110 u32 pixel_fmt
, u32 width
);
111 void ipu_dc_enable_channel(struct ipu_dc
*dc
);
112 void ipu_dc_disable_channel(struct ipu_dc
*dc
);
115 * IPU Display Interface (di) functions
117 struct ipu_di
*ipu_di_get(struct ipu_soc
*ipu
, int disp
);
118 void ipu_di_put(struct ipu_di
*);
119 int ipu_di_disable(struct ipu_di
*);
120 int ipu_di_enable(struct ipu_di
*);
121 int ipu_di_get_num(struct ipu_di
*);
122 int ipu_di_init_sync_panel(struct ipu_di
*, struct ipu_di_signal_cfg
*sig
);
125 * IPU Display Multi FIFO Controller (dmfc) functions
128 int ipu_dmfc_enable_channel(struct dmfc_channel
*dmfc
);
129 void ipu_dmfc_disable_channel(struct dmfc_channel
*dmfc
);
130 int ipu_dmfc_alloc_bandwidth(struct dmfc_channel
*dmfc
,
131 unsigned long bandwidth_mbs
, int burstsize
);
132 void ipu_dmfc_free_bandwidth(struct dmfc_channel
*dmfc
);
133 int ipu_dmfc_init_channel(struct dmfc_channel
*dmfc
, int width
);
134 struct dmfc_channel
*ipu_dmfc_get(struct ipu_soc
*ipu
, int ipuv3_channel
);
135 void ipu_dmfc_put(struct dmfc_channel
*dmfc
);
138 * IPU Display Processor (dp) functions
140 #define IPU_DP_FLOW_SYNC_BG 0
141 #define IPU_DP_FLOW_SYNC_FG 1
142 #define IPU_DP_FLOW_ASYNC0_BG 2
143 #define IPU_DP_FLOW_ASYNC0_FG 3
144 #define IPU_DP_FLOW_ASYNC1_BG 4
145 #define IPU_DP_FLOW_ASYNC1_FG 5
147 struct ipu_dp
*ipu_dp_get(struct ipu_soc
*ipu
, unsigned int flow
);
148 void ipu_dp_put(struct ipu_dp
*);
149 int ipu_dp_enable_channel(struct ipu_dp
*dp
);
150 void ipu_dp_disable_channel(struct ipu_dp
*dp
);
151 int ipu_dp_setup_channel(struct ipu_dp
*dp
,
152 enum ipu_color_space in
, enum ipu_color_space out
);
153 int ipu_dp_set_window_pos(struct ipu_dp
*, u16 x_pos
, u16 y_pos
);
154 int ipu_dp_set_global_alpha(struct ipu_dp
*dp
, bool enable
, u8 alpha
,
157 #define IPU_CPMEM_WORD(word, ofs, size) ((((word) * 160 + (ofs)) << 8) | (size))
159 #define IPU_FIELD_UBO IPU_CPMEM_WORD(0, 46, 22)
160 #define IPU_FIELD_VBO IPU_CPMEM_WORD(0, 68, 22)
161 #define IPU_FIELD_IOX IPU_CPMEM_WORD(0, 90, 4)
162 #define IPU_FIELD_RDRW IPU_CPMEM_WORD(0, 94, 1)
163 #define IPU_FIELD_SO IPU_CPMEM_WORD(0, 113, 1)
164 #define IPU_FIELD_SLY IPU_CPMEM_WORD(1, 102, 14)
165 #define IPU_FIELD_SLUV IPU_CPMEM_WORD(1, 128, 14)
167 #define IPU_FIELD_XV IPU_CPMEM_WORD(0, 0, 10)
168 #define IPU_FIELD_YV IPU_CPMEM_WORD(0, 10, 9)
169 #define IPU_FIELD_XB IPU_CPMEM_WORD(0, 19, 13)
170 #define IPU_FIELD_YB IPU_CPMEM_WORD(0, 32, 12)
171 #define IPU_FIELD_NSB_B IPU_CPMEM_WORD(0, 44, 1)
172 #define IPU_FIELD_CF IPU_CPMEM_WORD(0, 45, 1)
173 #define IPU_FIELD_SX IPU_CPMEM_WORD(0, 46, 12)
174 #define IPU_FIELD_SY IPU_CPMEM_WORD(0, 58, 11)
175 #define IPU_FIELD_NS IPU_CPMEM_WORD(0, 69, 10)
176 #define IPU_FIELD_SDX IPU_CPMEM_WORD(0, 79, 7)
177 #define IPU_FIELD_SM IPU_CPMEM_WORD(0, 86, 10)
178 #define IPU_FIELD_SCC IPU_CPMEM_WORD(0, 96, 1)
179 #define IPU_FIELD_SCE IPU_CPMEM_WORD(0, 97, 1)
180 #define IPU_FIELD_SDY IPU_CPMEM_WORD(0, 98, 7)
181 #define IPU_FIELD_SDRX IPU_CPMEM_WORD(0, 105, 1)
182 #define IPU_FIELD_SDRY IPU_CPMEM_WORD(0, 106, 1)
183 #define IPU_FIELD_BPP IPU_CPMEM_WORD(0, 107, 3)
184 #define IPU_FIELD_DEC_SEL IPU_CPMEM_WORD(0, 110, 2)
185 #define IPU_FIELD_DIM IPU_CPMEM_WORD(0, 112, 1)
186 #define IPU_FIELD_BNDM IPU_CPMEM_WORD(0, 114, 3)
187 #define IPU_FIELD_BM IPU_CPMEM_WORD(0, 117, 2)
188 #define IPU_FIELD_ROT IPU_CPMEM_WORD(0, 119, 1)
189 #define IPU_FIELD_HF IPU_CPMEM_WORD(0, 120, 1)
190 #define IPU_FIELD_VF IPU_CPMEM_WORD(0, 121, 1)
191 #define IPU_FIELD_THE IPU_CPMEM_WORD(0, 122, 1)
192 #define IPU_FIELD_CAP IPU_CPMEM_WORD(0, 123, 1)
193 #define IPU_FIELD_CAE IPU_CPMEM_WORD(0, 124, 1)
194 #define IPU_FIELD_FW IPU_CPMEM_WORD(0, 125, 13)
195 #define IPU_FIELD_FH IPU_CPMEM_WORD(0, 138, 12)
196 #define IPU_FIELD_EBA0 IPU_CPMEM_WORD(1, 0, 29)
197 #define IPU_FIELD_EBA1 IPU_CPMEM_WORD(1, 29, 29)
198 #define IPU_FIELD_ILO IPU_CPMEM_WORD(1, 58, 20)
199 #define IPU_FIELD_NPB IPU_CPMEM_WORD(1, 78, 7)
200 #define IPU_FIELD_PFS IPU_CPMEM_WORD(1, 85, 4)
201 #define IPU_FIELD_ALU IPU_CPMEM_WORD(1, 89, 1)
202 #define IPU_FIELD_ALBM IPU_CPMEM_WORD(1, 90, 3)
203 #define IPU_FIELD_ID IPU_CPMEM_WORD(1, 93, 2)
204 #define IPU_FIELD_TH IPU_CPMEM_WORD(1, 95, 7)
205 #define IPU_FIELD_SL IPU_CPMEM_WORD(1, 102, 14)
206 #define IPU_FIELD_WID0 IPU_CPMEM_WORD(1, 116, 3)
207 #define IPU_FIELD_WID1 IPU_CPMEM_WORD(1, 119, 3)
208 #define IPU_FIELD_WID2 IPU_CPMEM_WORD(1, 122, 3)
209 #define IPU_FIELD_WID3 IPU_CPMEM_WORD(1, 125, 3)
210 #define IPU_FIELD_OFS0 IPU_CPMEM_WORD(1, 128, 5)
211 #define IPU_FIELD_OFS1 IPU_CPMEM_WORD(1, 133, 5)
212 #define IPU_FIELD_OFS2 IPU_CPMEM_WORD(1, 138, 5)
213 #define IPU_FIELD_OFS3 IPU_CPMEM_WORD(1, 143, 5)
214 #define IPU_FIELD_SXYS IPU_CPMEM_WORD(1, 148, 1)
215 #define IPU_FIELD_CRE IPU_CPMEM_WORD(1, 149, 1)
216 #define IPU_FIELD_DEC_SEL2 IPU_CPMEM_WORD(1, 150, 1)
218 struct ipu_cpmem_word
{
223 struct ipu_ch_param
{
224 struct ipu_cpmem_word word
[2];
227 void ipu_ch_param_write_field(struct ipu_ch_param __iomem
*base
, u32 wbs
, u32 v
);
228 u32
ipu_ch_param_read_field(struct ipu_ch_param __iomem
*base
, u32 wbs
);
229 struct ipu_ch_param __iomem
*ipu_get_cpmem(struct ipuv3_channel
*channel
);
230 void ipu_ch_param_dump(struct ipu_ch_param __iomem
*p
);
232 static inline void ipu_ch_param_zero(struct ipu_ch_param __iomem
*p
)
235 void __iomem
*base
= p
;
237 for (i
= 0; i
< sizeof(*p
) / sizeof(u32
); i
++)
238 writel(0, base
+ i
* sizeof(u32
));
241 static inline void ipu_cpmem_set_buffer(struct ipu_ch_param __iomem
*p
,
242 int bufnum
, dma_addr_t buf
)
245 ipu_ch_param_write_field(p
, IPU_FIELD_EBA1
, buf
>> 3);
247 ipu_ch_param_write_field(p
, IPU_FIELD_EBA0
, buf
>> 3);
250 static inline void ipu_cpmem_set_resolution(struct ipu_ch_param __iomem
*p
,
253 ipu_ch_param_write_field(p
, IPU_FIELD_FW
, xres
- 1);
254 ipu_ch_param_write_field(p
, IPU_FIELD_FH
, yres
- 1);
257 static inline void ipu_cpmem_set_stride(struct ipu_ch_param __iomem
*p
,
260 ipu_ch_param_write_field(p
, IPU_FIELD_SLY
, stride
- 1);
263 void ipu_cpmem_set_high_priority(struct ipuv3_channel
*channel
);
266 struct fb_bitfield red
;
267 struct fb_bitfield green
;
268 struct fb_bitfield blue
;
269 struct fb_bitfield transp
;
274 struct v4l2_pix_format pix
;
275 struct v4l2_rect rect
;
279 int ipu_cpmem_set_format_passthrough(struct ipu_ch_param __iomem
*p
,
282 int ipu_cpmem_set_format_rgb(struct ipu_ch_param __iomem
*,
283 struct ipu_rgb
*rgb
);
285 static inline void ipu_cpmem_interlaced_scan(struct ipu_ch_param
*p
,
288 ipu_ch_param_write_field(p
, IPU_FIELD_SO
, 1);
289 ipu_ch_param_write_field(p
, IPU_FIELD_ILO
, stride
/ 8);
290 ipu_ch_param_write_field(p
, IPU_FIELD_SLY
, (stride
* 2) - 1);
293 void ipu_cpmem_set_yuv_planar(struct ipu_ch_param __iomem
*p
, u32 pixel_format
,
294 int stride
, int height
);
295 void ipu_cpmem_set_yuv_interleaved(struct ipu_ch_param
*p
, u32 pixel_format
);
296 void ipu_cpmem_set_yuv_planar_full(struct ipu_ch_param __iomem
*p
,
297 u32 pixel_format
, int stride
, int u_offset
, int v_offset
);
298 int ipu_cpmem_set_fmt(struct ipu_ch_param __iomem
*cpmem
, u32 pixelformat
);
299 int ipu_cpmem_set_image(struct ipu_ch_param __iomem
*cpmem
,
300 struct ipu_image
*image
);
302 enum ipu_color_space
ipu_pixelformat_to_colorspace(u32 pixelformat
);
304 static inline void ipu_cpmem_set_burstsize(struct ipu_ch_param __iomem
*p
,
307 ipu_ch_param_write_field(p
, IPU_FIELD_NPB
, burstsize
- 1);
310 struct ipu_client_platformdata
{
318 #endif /* __DRM_IPU_H__ */
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