2 * i.MX IPUv3 DP Overlay Planes
4 * Copyright (C) 2013 Philipp Zabel, Pengutronix
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <drm/drm_fb_cma_helper.h>
18 #include <drm/drm_gem_cma_helper.h>
20 #include "ipu-v3/imx-ipu-v3.h"
21 #include "ipuv3-plane.h"
23 #define to_ipu_plane(x) container_of(x, struct ipu_plane, base)
25 static const uint32_t ipu_plane_formats
[] = {
38 int ipu_plane_irq(struct ipu_plane
*ipu_plane
)
40 return ipu_idmac_channel_irq(ipu_plane
->ipu
, ipu_plane
->ipu_ch
,
44 static int calc_vref(struct drm_display_mode
*mode
)
46 unsigned long htotal
, vtotal
;
48 htotal
= mode
->htotal
;
49 vtotal
= mode
->vtotal
;
51 if (!htotal
|| !vtotal
)
54 return DIV_ROUND_UP(mode
->clock
* 1000, vtotal
* htotal
);
57 static inline int calc_bandwidth(int width
, int height
, unsigned int vref
)
59 return width
* height
* vref
;
62 int ipu_plane_set_base(struct ipu_plane
*ipu_plane
, struct drm_framebuffer
*fb
,
65 struct ipu_ch_param __iomem
*cpmem
;
66 struct drm_gem_cma_object
*cma_obj
;
68 cma_obj
= drm_fb_cma_get_gem_obj(fb
, 0);
70 DRM_LOG_KMS("entry is null.\n");
74 dev_dbg(ipu_plane
->base
.dev
->dev
, "phys = 0x%x, x = %d, y = %d",
75 cma_obj
->paddr
, x
, y
);
77 cpmem
= ipu_get_cpmem(ipu_plane
->ipu_ch
);
78 ipu_cpmem_set_stride(cpmem
, fb
->pitches
[0]);
79 ipu_cpmem_set_buffer(cpmem
, 0, cma_obj
->paddr
+ fb
->offsets
[0] +
80 fb
->pitches
[0] * y
+ x
);
85 int ipu_plane_mode_set(struct ipu_plane
*ipu_plane
, struct drm_crtc
*crtc
,
86 struct drm_display_mode
*mode
,
87 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
88 unsigned int crtc_w
, unsigned int crtc_h
,
89 uint32_t src_x
, uint32_t src_y
,
90 uint32_t src_w
, uint32_t src_h
)
92 struct ipu_ch_param __iomem
*cpmem
;
93 struct device
*dev
= ipu_plane
->base
.dev
->dev
;
97 if (src_w
!= crtc_w
|| src_h
!= crtc_h
)
100 /* clip to crtc bounds */
102 if (-crtc_x
> crtc_w
)
110 if (-crtc_y
> crtc_h
)
117 if (crtc_x
+ crtc_w
> mode
->hdisplay
) {
118 if (crtc_x
> mode
->hdisplay
)
120 crtc_w
= mode
->hdisplay
- crtc_x
;
123 if (crtc_y
+ crtc_h
> mode
->vdisplay
) {
124 if (crtc_y
> mode
->vdisplay
)
126 crtc_h
= mode
->vdisplay
- crtc_y
;
129 /* full plane minimum width is 13 pixels */
130 if (crtc_w
< 13 && (ipu_plane
->dp_flow
!= IPU_DP_FLOW_SYNC_FG
))
135 switch (ipu_plane
->dp_flow
) {
136 case IPU_DP_FLOW_SYNC_BG
:
137 ret
= ipu_dp_setup_channel(ipu_plane
->dp
,
138 IPUV3_COLORSPACE_RGB
,
139 IPUV3_COLORSPACE_RGB
);
142 "initializing display processor failed with %d\n",
146 ipu_dp_set_global_alpha(ipu_plane
->dp
, 1, 0, 1);
148 case IPU_DP_FLOW_SYNC_FG
:
149 ipu_dp_setup_channel(ipu_plane
->dp
,
150 ipu_drm_fourcc_to_colorspace(fb
->pixel_format
),
151 IPUV3_COLORSPACE_UNKNOWN
);
152 ipu_dp_set_window_pos(ipu_plane
->dp
, crtc_x
, crtc_y
);
156 ret
= ipu_dmfc_init_channel(ipu_plane
->dmfc
, crtc_w
);
158 dev_err(dev
, "initializing dmfc channel failed with %d\n", ret
);
162 ret
= ipu_dmfc_alloc_bandwidth(ipu_plane
->dmfc
,
163 calc_bandwidth(crtc_w
, crtc_h
,
164 calc_vref(mode
)), 64);
166 dev_err(dev
, "allocating dmfc bandwidth failed with %d\n", ret
);
170 cpmem
= ipu_get_cpmem(ipu_plane
->ipu_ch
);
171 ipu_ch_param_zero(cpmem
);
172 ipu_cpmem_set_resolution(cpmem
, src_w
, src_h
);
173 ret
= ipu_cpmem_set_fmt(cpmem
, fb
->pixel_format
);
175 dev_err(dev
, "unsupported pixel format 0x%08x\n",
179 ipu_cpmem_set_high_priority(ipu_plane
->ipu_ch
);
181 ret
= ipu_plane_set_base(ipu_plane
, fb
, src_x
, src_y
);
188 void ipu_plane_put_resources(struct ipu_plane
*ipu_plane
)
190 if (!IS_ERR_OR_NULL(ipu_plane
->dp
))
191 ipu_dp_put(ipu_plane
->dp
);
192 if (!IS_ERR_OR_NULL(ipu_plane
->dmfc
))
193 ipu_dmfc_put(ipu_plane
->dmfc
);
194 if (!IS_ERR_OR_NULL(ipu_plane
->ipu_ch
))
195 ipu_idmac_put(ipu_plane
->ipu_ch
);
198 int ipu_plane_get_resources(struct ipu_plane
*ipu_plane
)
202 ipu_plane
->ipu_ch
= ipu_idmac_get(ipu_plane
->ipu
, ipu_plane
->dma
);
203 if (IS_ERR(ipu_plane
->ipu_ch
)) {
204 ret
= PTR_ERR(ipu_plane
->ipu_ch
);
205 DRM_ERROR("failed to get idmac channel: %d\n", ret
);
209 ipu_plane
->dmfc
= ipu_dmfc_get(ipu_plane
->ipu
, ipu_plane
->dma
);
210 if (IS_ERR(ipu_plane
->dmfc
)) {
211 ret
= PTR_ERR(ipu_plane
->dmfc
);
212 DRM_ERROR("failed to get dmfc: ret %d\n", ret
);
216 if (ipu_plane
->dp_flow
>= 0) {
217 ipu_plane
->dp
= ipu_dp_get(ipu_plane
->ipu
, ipu_plane
->dp_flow
);
218 if (IS_ERR(ipu_plane
->dp
)) {
219 ret
= PTR_ERR(ipu_plane
->dp
);
220 DRM_ERROR("failed to get dp flow: %d\n", ret
);
227 ipu_plane_put_resources(ipu_plane
);
232 void ipu_plane_enable(struct ipu_plane
*ipu_plane
)
234 ipu_dmfc_enable_channel(ipu_plane
->dmfc
);
235 ipu_idmac_enable_channel(ipu_plane
->ipu_ch
);
237 ipu_dp_enable_channel(ipu_plane
->dp
);
239 ipu_plane
->enabled
= true;
242 void ipu_plane_disable(struct ipu_plane
*ipu_plane
)
244 ipu_plane
->enabled
= false;
246 ipu_idmac_wait_busy(ipu_plane
->ipu_ch
, 50);
249 ipu_dp_disable_channel(ipu_plane
->dp
);
250 ipu_idmac_disable_channel(ipu_plane
->ipu_ch
);
251 ipu_dmfc_disable_channel(ipu_plane
->dmfc
);
254 static void ipu_plane_dpms(struct ipu_plane
*ipu_plane
, int mode
)
258 DRM_DEBUG_KMS("mode = %d", mode
);
260 enable
= (mode
== DRM_MODE_DPMS_ON
);
262 if (enable
== ipu_plane
->enabled
)
266 ipu_plane_enable(ipu_plane
);
268 ipu_plane_disable(ipu_plane
);
270 ipu_idmac_put(ipu_plane
->ipu_ch
);
271 ipu_dmfc_put(ipu_plane
->dmfc
);
272 ipu_dp_put(ipu_plane
->dp
);
280 static int ipu_update_plane(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
281 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
282 unsigned int crtc_w
, unsigned int crtc_h
,
283 uint32_t src_x
, uint32_t src_y
,
284 uint32_t src_w
, uint32_t src_h
)
286 struct ipu_plane
*ipu_plane
= to_ipu_plane(plane
);
289 DRM_DEBUG_KMS("plane - %p\n", plane
);
291 if (!ipu_plane
->enabled
)
292 ret
= ipu_plane_get_resources(ipu_plane
);
296 ret
= ipu_plane_mode_set(ipu_plane
, crtc
, &crtc
->hwmode
, fb
,
297 crtc_x
, crtc_y
, crtc_w
, crtc_h
,
298 src_x
>> 16, src_y
>> 16, src_w
>> 16, src_h
>> 16);
300 ipu_plane_put_resources(ipu_plane
);
304 if (crtc
!= plane
->crtc
)
305 dev_info(plane
->dev
->dev
, "crtc change: %p -> %p\n",
309 ipu_plane_dpms(ipu_plane
, DRM_MODE_DPMS_ON
);
314 static int ipu_disable_plane(struct drm_plane
*plane
)
316 struct ipu_plane
*ipu_plane
= to_ipu_plane(plane
);
318 DRM_DEBUG_KMS("[%d] %s\n", __LINE__
, __func__
);
320 ipu_plane_dpms(ipu_plane
, DRM_MODE_DPMS_OFF
);
322 ipu_plane_put_resources(ipu_plane
);
327 static void ipu_plane_destroy(struct drm_plane
*plane
)
329 struct ipu_plane
*ipu_plane
= to_ipu_plane(plane
);
331 DRM_DEBUG_KMS("[%d] %s\n", __LINE__
, __func__
);
333 ipu_disable_plane(plane
);
334 drm_plane_cleanup(plane
);
338 static struct drm_plane_funcs ipu_plane_funcs
= {
339 .update_plane
= ipu_update_plane
,
340 .disable_plane
= ipu_disable_plane
,
341 .destroy
= ipu_plane_destroy
,
344 struct ipu_plane
*ipu_plane_init(struct drm_device
*dev
, struct ipu_soc
*ipu
,
345 int dma
, int dp
, unsigned int possible_crtcs
,
348 struct ipu_plane
*ipu_plane
;
351 DRM_DEBUG_KMS("channel %d, dp flow %d, possible_crtcs=0x%x\n",
352 dma
, dp
, possible_crtcs
);
354 ipu_plane
= kzalloc(sizeof(*ipu_plane
), GFP_KERNEL
);
356 DRM_ERROR("failed to allocate plane\n");
357 return ERR_PTR(-ENOMEM
);
360 ipu_plane
->ipu
= ipu
;
361 ipu_plane
->dma
= dma
;
362 ipu_plane
->dp_flow
= dp
;
364 ret
= drm_plane_init(dev
, &ipu_plane
->base
, possible_crtcs
,
365 &ipu_plane_funcs
, ipu_plane_formats
,
366 ARRAY_SIZE(ipu_plane_formats
),
369 DRM_ERROR("failed to initialize plane\n");