2 * dim2_reg.h - Definitions for registers of DIM2
3 * (MediaLB, Device Interface Macro IP, OS62420)
5 * Copyright (C) 2015, Microchip Technology Germany II GmbH & Co. KG
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * This file is licensed under GPLv2.
15 #ifndef DIM2_OS62420_H
16 #define DIM2_OS62420_H
18 #include <linux/types.h>
26 /* 0x01 */ u32 rsvd0
[1];
27 /* 0x02 */ u32 MLBPC0
;
29 /* 0x04 */ u32 rsvd1
[1];
31 /* 0x06 */ u32 rsvd2
[2];
34 /* 0x0A */ u32 rsvd3
[1];
36 /* 0x0C */ u32 rsvd4
[1];
37 /* 0x0D */ u32 MLBPC2
;
38 /* 0x0E */ u32 MLBPC1
;
40 /* 0x10 */ u32 rsvd5
[0x10];
42 /* 0x21 */ u32 rsvd6
[1];
49 /* 0x28 */ u32 rsvd7
[8];
60 /* 0x3A */ u32 rsvd8
[0xB6];
62 /* 0xF1 */ u32 rsvd9
[3];
69 #define DIM2_MASK(n) (~((~(u32)0)<<(n)))
76 MLBC0_MLBCLK_SHIFT
= 2,
77 MLBC0_MLBCLK_VAL_256FS
= 0,
78 MLBC0_MLBCLK_VAL_512FS
= 1,
79 MLBC0_MLBCLK_VAL_1024FS
= 2,
80 MLBC0_MLBCLK_VAL_2048FS
= 3,
82 MLBC0_FCNT_SHIFT
= 15,
84 MLBC0_FCNT_VAL_1FPSB
= 0,
85 MLBC0_FCNT_VAL_2FPSB
= 1,
86 MLBC0_FCNT_VAL_4FPSB
= 2,
87 MLBC0_FCNT_VAL_8FPSB
= 3,
88 MLBC0_FCNT_VAL_16FPSB
= 4,
89 MLBC0_FCNT_VAL_32FPSB
= 5,
90 MLBC0_FCNT_VAL_64FPSB
= 6,
94 MIEN_CTX_BREAK_BIT
= 29,
96 MIEN_CTX_DONE_BIT
= 27,
98 MIEN_CRX_BREAK_BIT
= 26,
100 MIEN_CRX_DONE_BIT
= 24,
102 MIEN_ATX_BREAK_BIT
= 22,
103 MIEN_ATX_PE_BIT
= 21,
104 MIEN_ATX_DONE_BIT
= 20,
106 MIEN_ARX_BREAK_BIT
= 19,
107 MIEN_ARX_PE_BIT
= 18,
108 MIEN_ARX_DONE_BIT
= 17,
110 MIEN_SYNC_PE_BIT
= 16,
112 MIEN_ISOC_BUFO_BIT
= 1,
113 MIEN_ISOC_PE_BIT
= 0,
116 MLBC1_NDA_MASK
= 0xFF,
118 MLBC1_CLKMERR_BIT
= 7,
119 MLBC1_LOCKERR_BIT
= 6,
121 ACTL_DMA_MODE_BIT
= 2,
122 ACTL_DMA_MODE_VAL_DMA_MODE_0
= 0,
123 ACTL_DMA_MODE_VAL_DMA_MODE_1
= 1,
130 CDT1_BS_ISOC_SHIFT
= 0,
131 CDT1_BS_ISOC_MASK
= DIM2_MASK(9),
134 CDT3_BD_MASK
= DIM2_MASK(12),
135 CDT3_BD_ISOC_MASK
= DIM2_MASK(13),
148 ADT1_CTRL_ASYNC_BD_MASK
= DIM2_MASK(11),
149 ADT1_ISOC_SYNC_BD_MASK
= DIM2_MASK(13),
161 CAT_CT_VAL_CONTROL
= 1,
162 CAT_CT_VAL_ASYNC
= 2,
166 CAT_CL_MASK
= DIM2_MASK(6)
173 #endif /* DIM2_OS62420_H */