1 /**********************************************************************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (c) 2003-2007 Cavium Networks
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 **********************************************************************/
27 #include <linux/kernel.h>
28 #include <linux/netdevice.h>
29 #include <linux/mii.h>
32 #include <asm/octeon/octeon.h>
34 #include "ethernet-defines.h"
35 #include "octeon-ethernet.h"
36 #include "ethernet-common.h"
37 #include "ethernet-util.h"
41 #include <asm/octeon/cvmx-npi-defs.h>
42 #include "cvmx-spxx-defs.h"
43 #include "cvmx-stxx-defs.h"
45 static int number_spi_ports
;
46 static int need_retrain
[2] = { 0, 0 };
48 static irqreturn_t
cvm_oct_spi_rml_interrupt(int cpl
, void *dev_id
)
50 irqreturn_t return_status
= IRQ_NONE
;
51 union cvmx_npi_rsl_int_blocks rsl_int_blocks
;
53 /* Check and see if this interrupt was caused by the GMX block */
54 rsl_int_blocks
.u64
= cvmx_read_csr(CVMX_NPI_RSL_INT_BLOCKS
);
55 if (rsl_int_blocks
.s
.spx1
) { /* 19 - SPX1_INT_REG & STX1_INT_REG */
57 union cvmx_spxx_int_reg spx_int_reg
;
58 union cvmx_stxx_int_reg stx_int_reg
;
60 spx_int_reg
.u64
= cvmx_read_csr(CVMX_SPXX_INT_REG(1));
61 cvmx_write_csr(CVMX_SPXX_INT_REG(1), spx_int_reg
.u64
);
62 if (!need_retrain
[1]) {
64 spx_int_reg
.u64
&= cvmx_read_csr(CVMX_SPXX_INT_MSK(1));
65 if (spx_int_reg
.s
.spf
)
66 pr_err("SPI1: SRX Spi4 interface down\n");
67 if (spx_int_reg
.s
.calerr
)
68 pr_err("SPI1: SRX Spi4 Calendar table "
70 if (spx_int_reg
.s
.syncerr
)
71 pr_err("SPI1: SRX Consecutive Spi4 DIP4 "
72 "errors have exceeded "
73 "SPX_ERR_CTL[ERRCNT]\n");
74 if (spx_int_reg
.s
.diperr
)
75 pr_err("SPI1: SRX Spi4 DIP4 error\n");
76 if (spx_int_reg
.s
.tpaovr
)
77 pr_err("SPI1: SRX Selected port has hit "
79 if (spx_int_reg
.s
.rsverr
)
80 pr_err("SPI1: SRX Spi4 reserved control "
82 if (spx_int_reg
.s
.drwnng
)
83 pr_err("SPI1: SRX Spi4 receive FIFO "
84 "drowning/overflow\n");
85 if (spx_int_reg
.s
.clserr
)
86 pr_err("SPI1: SRX Spi4 packet closed on "
87 "non-16B alignment without EOP\n");
88 if (spx_int_reg
.s
.spiovr
)
89 pr_err("SPI1: SRX Spi4 async FIFO overflow\n");
90 if (spx_int_reg
.s
.abnorm
)
91 pr_err("SPI1: SRX Abnormal packet "
92 "termination (ERR bit)\n");
93 if (spx_int_reg
.s
.prtnxa
)
94 pr_err("SPI1: SRX Port out of range\n");
97 stx_int_reg
.u64
= cvmx_read_csr(CVMX_STXX_INT_REG(1));
98 cvmx_write_csr(CVMX_STXX_INT_REG(1), stx_int_reg
.u64
);
99 if (!need_retrain
[1]) {
101 stx_int_reg
.u64
&= cvmx_read_csr(CVMX_STXX_INT_MSK(1));
102 if (stx_int_reg
.s
.syncerr
)
103 pr_err("SPI1: STX Interface encountered a "
105 if (stx_int_reg
.s
.frmerr
)
106 pr_err("SPI1: STX FRMCNT has exceeded "
107 "STX_DIP_CNT[MAXFRM]\n");
108 if (stx_int_reg
.s
.unxfrm
)
109 pr_err("SPI1: STX Unexpected framing "
111 if (stx_int_reg
.s
.nosync
)
112 pr_err("SPI1: STX ERRCNT has exceeded "
113 "STX_DIP_CNT[MAXDIP]\n");
114 if (stx_int_reg
.s
.diperr
)
115 pr_err("SPI1: STX DIP2 error on the Spi4 "
117 if (stx_int_reg
.s
.datovr
)
118 pr_err("SPI1: STX Spi4 FIFO overflow error\n");
119 if (stx_int_reg
.s
.ovrbst
)
120 pr_err("SPI1: STX Transmit packet burst "
122 if (stx_int_reg
.s
.calpar1
)
123 pr_err("SPI1: STX Calendar Table Parity "
125 if (stx_int_reg
.s
.calpar0
)
126 pr_err("SPI1: STX Calendar Table Parity "
130 cvmx_write_csr(CVMX_SPXX_INT_MSK(1), 0);
131 cvmx_write_csr(CVMX_STXX_INT_MSK(1), 0);
133 return_status
= IRQ_HANDLED
;
136 if (rsl_int_blocks
.s
.spx0
) { /* 18 - SPX0_INT_REG & STX0_INT_REG */
137 union cvmx_spxx_int_reg spx_int_reg
;
138 union cvmx_stxx_int_reg stx_int_reg
;
140 spx_int_reg
.u64
= cvmx_read_csr(CVMX_SPXX_INT_REG(0));
141 cvmx_write_csr(CVMX_SPXX_INT_REG(0), spx_int_reg
.u64
);
142 if (!need_retrain
[0]) {
144 spx_int_reg
.u64
&= cvmx_read_csr(CVMX_SPXX_INT_MSK(0));
145 if (spx_int_reg
.s
.spf
)
146 pr_err("SPI0: SRX Spi4 interface down\n");
147 if (spx_int_reg
.s
.calerr
)
148 pr_err("SPI0: SRX Spi4 Calendar table "
150 if (spx_int_reg
.s
.syncerr
)
151 pr_err("SPI0: SRX Consecutive Spi4 DIP4 "
152 "errors have exceeded "
153 "SPX_ERR_CTL[ERRCNT]\n");
154 if (spx_int_reg
.s
.diperr
)
155 pr_err("SPI0: SRX Spi4 DIP4 error\n");
156 if (spx_int_reg
.s
.tpaovr
)
157 pr_err("SPI0: SRX Selected port has hit "
159 if (spx_int_reg
.s
.rsverr
)
160 pr_err("SPI0: SRX Spi4 reserved control "
162 if (spx_int_reg
.s
.drwnng
)
163 pr_err("SPI0: SRX Spi4 receive FIFO "
164 "drowning/overflow\n");
165 if (spx_int_reg
.s
.clserr
)
166 pr_err("SPI0: SRX Spi4 packet closed on "
167 "non-16B alignment without EOP\n");
168 if (spx_int_reg
.s
.spiovr
)
169 pr_err("SPI0: SRX Spi4 async FIFO overflow\n");
170 if (spx_int_reg
.s
.abnorm
)
171 pr_err("SPI0: SRX Abnormal packet "
172 "termination (ERR bit)\n");
173 if (spx_int_reg
.s
.prtnxa
)
174 pr_err("SPI0: SRX Port out of range\n");
177 stx_int_reg
.u64
= cvmx_read_csr(CVMX_STXX_INT_REG(0));
178 cvmx_write_csr(CVMX_STXX_INT_REG(0), stx_int_reg
.u64
);
179 if (!need_retrain
[0]) {
181 stx_int_reg
.u64
&= cvmx_read_csr(CVMX_STXX_INT_MSK(0));
182 if (stx_int_reg
.s
.syncerr
)
183 pr_err("SPI0: STX Interface encountered a "
185 if (stx_int_reg
.s
.frmerr
)
186 pr_err("SPI0: STX FRMCNT has exceeded "
187 "STX_DIP_CNT[MAXFRM]\n");
188 if (stx_int_reg
.s
.unxfrm
)
189 pr_err("SPI0: STX Unexpected framing "
191 if (stx_int_reg
.s
.nosync
)
192 pr_err("SPI0: STX ERRCNT has exceeded "
193 "STX_DIP_CNT[MAXDIP]\n");
194 if (stx_int_reg
.s
.diperr
)
195 pr_err("SPI0: STX DIP2 error on the Spi4 "
197 if (stx_int_reg
.s
.datovr
)
198 pr_err("SPI0: STX Spi4 FIFO overflow error\n");
199 if (stx_int_reg
.s
.ovrbst
)
200 pr_err("SPI0: STX Transmit packet burst "
202 if (stx_int_reg
.s
.calpar1
)
203 pr_err("SPI0: STX Calendar Table Parity "
205 if (stx_int_reg
.s
.calpar0
)
206 pr_err("SPI0: STX Calendar Table Parity "
210 cvmx_write_csr(CVMX_SPXX_INT_MSK(0), 0);
211 cvmx_write_csr(CVMX_STXX_INT_MSK(0), 0);
213 return_status
= IRQ_HANDLED
;
216 return return_status
;
219 static void cvm_oct_spi_enable_error_reporting(int interface
)
221 union cvmx_spxx_int_msk spxx_int_msk
;
222 union cvmx_stxx_int_msk stxx_int_msk
;
224 spxx_int_msk
.u64
= cvmx_read_csr(CVMX_SPXX_INT_MSK(interface
));
225 spxx_int_msk
.s
.calerr
= 1;
226 spxx_int_msk
.s
.syncerr
= 1;
227 spxx_int_msk
.s
.diperr
= 1;
228 spxx_int_msk
.s
.tpaovr
= 1;
229 spxx_int_msk
.s
.rsverr
= 1;
230 spxx_int_msk
.s
.drwnng
= 1;
231 spxx_int_msk
.s
.clserr
= 1;
232 spxx_int_msk
.s
.spiovr
= 1;
233 spxx_int_msk
.s
.abnorm
= 1;
234 spxx_int_msk
.s
.prtnxa
= 1;
235 cvmx_write_csr(CVMX_SPXX_INT_MSK(interface
), spxx_int_msk
.u64
);
237 stxx_int_msk
.u64
= cvmx_read_csr(CVMX_STXX_INT_MSK(interface
));
238 stxx_int_msk
.s
.frmerr
= 1;
239 stxx_int_msk
.s
.unxfrm
= 1;
240 stxx_int_msk
.s
.nosync
= 1;
241 stxx_int_msk
.s
.diperr
= 1;
242 stxx_int_msk
.s
.datovr
= 1;
243 stxx_int_msk
.s
.ovrbst
= 1;
244 stxx_int_msk
.s
.calpar1
= 1;
245 stxx_int_msk
.s
.calpar0
= 1;
246 cvmx_write_csr(CVMX_STXX_INT_MSK(interface
), stxx_int_msk
.u64
);
249 static void cvm_oct_spi_poll(struct net_device
*dev
)
251 static int spi4000_port
;
252 struct octeon_ethernet
*priv
= netdev_priv(dev
);
255 for (interface
= 0; interface
< 2; interface
++) {
257 if ((priv
->port
== interface
* 16) && need_retrain
[interface
]) {
259 if (cvmx_spi_restart_interface
260 (interface
, CVMX_SPI_MODE_DUPLEX
, 10) == 0) {
261 need_retrain
[interface
] = 0;
262 cvm_oct_spi_enable_error_reporting(interface
);
267 * The SPI4000 TWSI interface is very slow. In order
268 * not to bring the system to a crawl, we only poll a
269 * single port every second. This means negotiation
270 * speed changes take up to 10 seconds, but at least
271 * we don't waste absurd amounts of time waiting for
274 if (priv
->port
== spi4000_port
) {
276 * This function does nothing if it is called on an
277 * interface without a SPI4000.
279 cvmx_spi4000_check_speed(interface
, priv
->port
);
281 * Normal ordering increments. By decrementing
282 * we only match once per iteration.
285 if (spi4000_port
< 0)
291 int cvm_oct_spi_init(struct net_device
*dev
)
294 struct octeon_ethernet
*priv
= netdev_priv(dev
);
296 if (number_spi_ports
== 0) {
297 r
= request_irq(OCTEON_IRQ_RML
, cvm_oct_spi_rml_interrupt
,
298 IRQF_SHARED
, "SPI", &number_spi_ports
);
302 if ((priv
->port
== 0) || (priv
->port
== 16)) {
303 cvm_oct_spi_enable_error_reporting(INTERFACE(priv
->port
));
304 priv
->poll
= cvm_oct_spi_poll
;
306 cvm_oct_common_init(dev
);
310 void cvm_oct_spi_uninit(struct net_device
*dev
)
314 cvm_oct_common_uninit(dev
);
316 if (number_spi_ports
== 0) {
317 for (interface
= 0; interface
< 2; interface
++) {
318 cvmx_write_csr(CVMX_SPXX_INT_MSK(interface
), 0);
319 cvmx_write_csr(CVMX_STXX_INT_MSK(interface
), 0);
321 free_irq(8 + 46, &number_spi_ports
);