4cf7b8bc81e1d3b7a3e9ff22f5f991bb8221862c
[deliverable/linux.git] / drivers / staging / octeon-usb / cvmx-usb.c
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39
40
41 /**
42 * @file
43 *
44 * "cvmx-usb.c" defines a set of low level USB functions to help
45 * developers create Octeon USB drivers for various operating
46 * systems. These functions provide a generic API to the Octeon
47 * USB blocks, hiding the internal hardware specific
48 * operations.
49 */
50 #include <linux/delay.h>
51 #include <asm/octeon/cvmx.h>
52 #include <asm/octeon/octeon.h>
53 #include <asm/octeon/cvmx-sysinfo.h>
54 #include "cvmx-usbnx-defs.h"
55 #include "cvmx-usbcx-defs.h"
56 #include "cvmx-usb.h"
57 #include <asm/octeon/cvmx-helper.h>
58 #include <asm/octeon/cvmx-helper-board.h>
59
60 /* Normal prefetch that use the pref instruction. */
61 #define CVMX_PREFETCH(address, offset) asm volatile ("pref %[type], %[off](%[rbase])" : : [rbase] "d" (address), [off] "I" (offset), [type] "n" (0))
62
63 #define MAX_RETRIES 3 /* Maximum number of times to retry failed transactions */
64 #define MAX_PIPES 32 /* Maximum number of pipes that can be open at once */
65 #define MAX_TRANSACTIONS 256 /* Maximum number of outstanding transactions across all pipes */
66 #define MAX_CHANNELS 8 /* Maximum number of hardware channels supported by the USB block */
67 #define MAX_USB_ADDRESS 127 /* The highest valid USB device address */
68 #define MAX_USB_ENDPOINT 15 /* The highest valid USB endpoint number */
69 #define MAX_USB_HUB_PORT 15 /* The highest valid port number on a hub */
70 #define MAX_TRANSFER_BYTES ((1<<19)-1) /* The low level hardware can transfer a maximum of this number of bytes in each transfer. The field is 19 bits wide */
71 #define MAX_TRANSFER_PACKETS ((1<<10)-1) /* The low level hardware can transfer a maximum of this number of packets in each transfer. The field is 10 bits wide */
72
73 enum cvmx_usb_transaction_flags {
74 __CVMX_USB_TRANSACTION_FLAGS_IN_USE = 1<<16,
75 };
76
77 enum {
78 USB_CLOCK_TYPE_REF_12,
79 USB_CLOCK_TYPE_REF_24,
80 USB_CLOCK_TYPE_REF_48,
81 USB_CLOCK_TYPE_CRYSTAL_12,
82 };
83
84 /**
85 * Logical transactions may take numerous low level
86 * transactions, especially when splits are concerned. This
87 * enum represents all of the possible stages a transaction can
88 * be in. Note that split completes are always even. This is so
89 * the NAK handler can backup to the previous low level
90 * transaction with a simple clearing of bit 0.
91 */
92 enum cvmx_usb_stage {
93 CVMX_USB_STAGE_NON_CONTROL,
94 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE,
95 CVMX_USB_STAGE_SETUP,
96 CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE,
97 CVMX_USB_STAGE_DATA,
98 CVMX_USB_STAGE_DATA_SPLIT_COMPLETE,
99 CVMX_USB_STAGE_STATUS,
100 CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE,
101 };
102
103 /**
104 * struct cvmx_usb_transaction - describes each pending USB transaction
105 * regardless of type. These are linked together
106 * to form a list of pending requests for a pipe.
107 *
108 * @prev: Transaction before this one in the pipe.
109 * @next: Transaction after this one in the pipe.
110 * @type: Type of transaction, duplicated of the pipe.
111 * @flags: State flags for this transaction.
112 * @buffer: User's physical buffer address to read/write.
113 * @buffer_length: Size of the user's buffer in bytes.
114 * @control_header: For control transactions, physical address of the 8
115 * byte standard header.
116 * @iso_start_frame: For ISO transactions, the starting frame number.
117 * @iso_number_packets: For ISO transactions, the number of packets in the
118 * request.
119 * @iso_packets: For ISO transactions, the sub packets in the request.
120 * @actual_bytes: Actual bytes transfer for this transaction.
121 * @stage: For control transactions, the current stage.
122 * @callback: User's callback function when complete.
123 * @callback_data: User's data.
124 */
125 struct cvmx_usb_transaction {
126 struct cvmx_usb_transaction *prev;
127 struct cvmx_usb_transaction *next;
128 enum cvmx_usb_transfer type;
129 enum cvmx_usb_transaction_flags flags;
130 uint64_t buffer;
131 int buffer_length;
132 uint64_t control_header;
133 int iso_start_frame;
134 int iso_number_packets;
135 struct cvmx_usb_iso_packet *iso_packets;
136 int xfersize;
137 int pktcnt;
138 int retries;
139 int actual_bytes;
140 enum cvmx_usb_stage stage;
141 cvmx_usb_callback_func_t callback;
142 void *callback_data;
143 };
144
145 /**
146 * struct cvmx_usb_pipe - a pipe represents a virtual connection between Octeon
147 * and some USB device. It contains a list of pending
148 * request to the device.
149 *
150 * @prev: Pipe before this one in the list
151 * @next: Pipe after this one in the list
152 * @head: The first pending transaction
153 * @tail: The last pending transaction
154 * @interval: For periodic pipes, the interval between packets in
155 * frames
156 * @next_tx_frame: The next frame this pipe is allowed to transmit on
157 * @flags: State flags for this pipe
158 * @device_speed: Speed of device connected to this pipe
159 * @transfer_type: Type of transaction supported by this pipe
160 * @transfer_dir: IN or OUT. Ignored for Control
161 * @multi_count: Max packet in a row for the device
162 * @max_packet: The device's maximum packet size in bytes
163 * @device_addr: USB device address at other end of pipe
164 * @endpoint_num: USB endpoint number at other end of pipe
165 * @hub_device_addr: Hub address this device is connected to
166 * @hub_port: Hub port this device is connected to
167 * @pid_toggle: This toggles between 0/1 on every packet send to track
168 * the data pid needed
169 * @channel: Hardware DMA channel for this pipe
170 * @split_sc_frame: The low order bits of the frame number the split
171 * complete should be sent on
172 */
173 struct cvmx_usb_pipe {
174 struct cvmx_usb_pipe *prev;
175 struct cvmx_usb_pipe *next;
176 struct cvmx_usb_transaction *head;
177 struct cvmx_usb_transaction *tail;
178 uint64_t interval;
179 uint64_t next_tx_frame;
180 enum cvmx_usb_pipe_flags flags;
181 enum cvmx_usb_speed device_speed;
182 enum cvmx_usb_transfer transfer_type;
183 enum cvmx_usb_direction transfer_dir;
184 int multi_count;
185 uint16_t max_packet;
186 uint8_t device_addr;
187 uint8_t endpoint_num;
188 uint8_t hub_device_addr;
189 uint8_t hub_port;
190 uint8_t pid_toggle;
191 uint8_t channel;
192 int8_t split_sc_frame;
193 };
194
195 /**
196 * struct cvmx_usb_pipe_list
197 *
198 * @head: Head of the list, or NULL if empty.
199 * @tail: Tail if the list, or NULL if empty.
200 */
201 struct cvmx_usb_pipe_list {
202 struct cvmx_usb_pipe *head;
203 struct cvmx_usb_pipe *tail;
204 };
205
206 struct cvmx_usb_tx_fifo {
207 struct {
208 int channel;
209 int size;
210 uint64_t address;
211 } entry[MAX_CHANNELS+1];
212 int head;
213 int tail;
214 };
215
216 /**
217 * struct cvmx_usb_internal_state - the state of the USB block
218 *
219 * init_flags: Flags passed to initialize.
220 * index: Which USB block this is for.
221 * idle_hardware_channels: Bit set for every idle hardware channel.
222 * usbcx_hprt: Stored port status so we don't need to read a CSR to
223 * determine splits.
224 * pipe_for_channel: Map channels to pipes.
225 * free_transaction_head: List of free transactions head.
226 * free_transaction_tail: List of free transactions tail.
227 * pipe: Storage for pipes.
228 * transaction: Storage for transactions.
229 * callback: User global callbacks.
230 * callback_data: User data for each callback.
231 * indent: Used by debug output to indent functions.
232 * port_status: Last port status used for change notification.
233 * free_pipes: List of all pipes that are currently closed.
234 * idle_pipes: List of open pipes that have no transactions.
235 * active_pipes: Active pipes indexed by transfer type.
236 * frame_number: Increments every SOF interrupt for time keeping.
237 * active_split: Points to the current active split, or NULL.
238 */
239 struct cvmx_usb_internal_state {
240 int init_flags;
241 int index;
242 int idle_hardware_channels;
243 union cvmx_usbcx_hprt usbcx_hprt;
244 struct cvmx_usb_pipe *pipe_for_channel[MAX_CHANNELS];
245 struct cvmx_usb_transaction *free_transaction_head;
246 struct cvmx_usb_transaction *free_transaction_tail;
247 struct cvmx_usb_pipe pipe[MAX_PIPES];
248 struct cvmx_usb_transaction transaction[MAX_TRANSACTIONS];
249 cvmx_usb_callback_func_t callback[__CVMX_USB_CALLBACK_END];
250 void *callback_data[__CVMX_USB_CALLBACK_END];
251 int indent;
252 struct cvmx_usb_port_status port_status;
253 struct cvmx_usb_pipe_list free_pipes;
254 struct cvmx_usb_pipe_list idle_pipes;
255 struct cvmx_usb_pipe_list active_pipes[4];
256 uint64_t frame_number;
257 struct cvmx_usb_transaction *active_split;
258 struct cvmx_usb_tx_fifo periodic;
259 struct cvmx_usb_tx_fifo nonperiodic;
260 };
261
262 /* This macro spins on a field waiting for it to reach a value */
263 #define CVMX_WAIT_FOR_FIELD32(address, type, field, op, value, timeout_usec)\
264 ({int result; \
265 do { \
266 uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec * \
267 octeon_get_clock_rate() / 1000000; \
268 type c; \
269 while (1) { \
270 c.u32 = __cvmx_usb_read_csr32(usb, address); \
271 if (c.s.field op (value)) { \
272 result = 0; \
273 break; \
274 } else if (cvmx_get_cycle() > done) { \
275 result = -1; \
276 break; \
277 } else \
278 cvmx_wait(100); \
279 } \
280 } while (0); \
281 result; })
282
283 /*
284 * This macro logically sets a single field in a CSR. It does the sequence
285 * read, modify, and write
286 */
287 #define USB_SET_FIELD32(address, type, field, value) \
288 do { \
289 type c; \
290 c.u32 = __cvmx_usb_read_csr32(usb, address); \
291 c.s.field = value; \
292 __cvmx_usb_write_csr32(usb, address, c.u32); \
293 } while (0)
294
295 /* Returns the IO address to push/pop stuff data from the FIFOs */
296 #define USB_FIFO_ADDRESS(channel, usb_index) (CVMX_USBCX_GOTGCTL(usb_index) + ((channel)+1)*0x1000)
297
298 static int octeon_usb_get_clock_type(void)
299 {
300 switch (cvmx_sysinfo_get()->board_type) {
301 case CVMX_BOARD_TYPE_BBGW_REF:
302 case CVMX_BOARD_TYPE_LANAI2_A:
303 case CVMX_BOARD_TYPE_LANAI2_U:
304 case CVMX_BOARD_TYPE_LANAI2_G:
305 case CVMX_BOARD_TYPE_UBNT_E100:
306 return USB_CLOCK_TYPE_CRYSTAL_12;
307 }
308 return USB_CLOCK_TYPE_REF_48;
309 }
310
311 /**
312 * Read a USB 32bit CSR. It performs the necessary address swizzle
313 * for 32bit CSRs and logs the value in a readable format if
314 * debugging is on.
315 *
316 * @usb: USB block this access is for
317 * @address: 64bit address to read
318 *
319 * Returns: Result of the read
320 */
321 static inline uint32_t __cvmx_usb_read_csr32(struct cvmx_usb_internal_state *usb,
322 uint64_t address)
323 {
324 uint32_t result = cvmx_read64_uint32(address ^ 4);
325 return result;
326 }
327
328
329 /**
330 * Write a USB 32bit CSR. It performs the necessary address
331 * swizzle for 32bit CSRs and logs the value in a readable format
332 * if debugging is on.
333 *
334 * @usb: USB block this access is for
335 * @address: 64bit address to write
336 * @value: Value to write
337 */
338 static inline void __cvmx_usb_write_csr32(struct cvmx_usb_internal_state *usb,
339 uint64_t address, uint32_t value)
340 {
341 cvmx_write64_uint32(address ^ 4, value);
342 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
343 }
344
345
346 /**
347 * Read a USB 64bit CSR. It logs the value in a readable format if
348 * debugging is on.
349 *
350 * @usb: USB block this access is for
351 * @address: 64bit address to read
352 *
353 * Returns: Result of the read
354 */
355 static inline uint64_t __cvmx_usb_read_csr64(struct cvmx_usb_internal_state *usb,
356 uint64_t address)
357 {
358 uint64_t result = cvmx_read64_uint64(address);
359 return result;
360 }
361
362
363 /**
364 * Write a USB 64bit CSR. It logs the value in a readable format
365 * if debugging is on.
366 *
367 * @usb: USB block this access is for
368 * @address: 64bit address to write
369 * @value: Value to write
370 */
371 static inline void __cvmx_usb_write_csr64(struct cvmx_usb_internal_state *usb,
372 uint64_t address, uint64_t value)
373 {
374 cvmx_write64_uint64(address, value);
375 }
376
377 /**
378 * Return non zero if this pipe connects to a non HIGH speed
379 * device through a high speed hub.
380 *
381 * @usb: USB block this access is for
382 * @pipe: Pipe to check
383 *
384 * Returns: Non zero if we need to do split transactions
385 */
386 static inline int __cvmx_usb_pipe_needs_split(struct cvmx_usb_internal_state *usb, struct cvmx_usb_pipe *pipe)
387 {
388 return ((pipe->device_speed != CVMX_USB_SPEED_HIGH) && (usb->usbcx_hprt.s.prtspd == CVMX_USB_SPEED_HIGH));
389 }
390
391
392 /**
393 * Trivial utility function to return the correct PID for a pipe
394 *
395 * @pipe: pipe to check
396 *
397 * Returns: PID for pipe
398 */
399 static inline int __cvmx_usb_get_data_pid(struct cvmx_usb_pipe *pipe)
400 {
401 if (pipe->pid_toggle)
402 return 2; /* Data1 */
403 else
404 return 0; /* Data0 */
405 }
406
407
408 /**
409 * Return the number of USB ports supported by this Octeon
410 * chip. If the chip doesn't support USB, or is not supported
411 * by this API, a zero will be returned. Most Octeon chips
412 * support one usb port, but some support two ports.
413 * cvmx_usb_initialize() must be called on independent
414 * struct cvmx_usb_state.
415 *
416 * Returns: Number of port, zero if usb isn't supported
417 */
418 int cvmx_usb_get_num_ports(void)
419 {
420 int arch_ports = 0;
421
422 if (OCTEON_IS_MODEL(OCTEON_CN56XX))
423 arch_ports = 1;
424 else if (OCTEON_IS_MODEL(OCTEON_CN52XX))
425 arch_ports = 2;
426 else if (OCTEON_IS_MODEL(OCTEON_CN50XX))
427 arch_ports = 1;
428 else if (OCTEON_IS_MODEL(OCTEON_CN31XX))
429 arch_ports = 1;
430 else if (OCTEON_IS_MODEL(OCTEON_CN30XX))
431 arch_ports = 1;
432 else
433 arch_ports = 0;
434
435 return arch_ports;
436 }
437
438
439 /**
440 * Allocate a usb transaction for use
441 *
442 * @usb: USB device state populated by
443 * cvmx_usb_initialize().
444 *
445 * Returns: Transaction or NULL
446 */
447 static inline struct cvmx_usb_transaction *__cvmx_usb_alloc_transaction(struct cvmx_usb_internal_state *usb)
448 {
449 struct cvmx_usb_transaction *t;
450 t = usb->free_transaction_head;
451 if (t) {
452 usb->free_transaction_head = t->next;
453 if (!usb->free_transaction_head)
454 usb->free_transaction_tail = NULL;
455 }
456 if (t) {
457 memset(t, 0, sizeof(*t));
458 t->flags = __CVMX_USB_TRANSACTION_FLAGS_IN_USE;
459 }
460 return t;
461 }
462
463
464 /**
465 * Free a usb transaction
466 *
467 * @usb: USB device state populated by
468 * cvmx_usb_initialize().
469 * @transaction:
470 * Transaction to free
471 */
472 static inline void __cvmx_usb_free_transaction(struct cvmx_usb_internal_state *usb,
473 struct cvmx_usb_transaction *transaction)
474 {
475 transaction->flags = 0;
476 transaction->prev = NULL;
477 transaction->next = NULL;
478 if (usb->free_transaction_tail)
479 usb->free_transaction_tail->next = transaction;
480 else
481 usb->free_transaction_head = transaction;
482 usb->free_transaction_tail = transaction;
483 }
484
485
486 /**
487 * Add a pipe to the tail of a list
488 * @list: List to add pipe to
489 * @pipe: Pipe to add
490 */
491 static inline void __cvmx_usb_append_pipe(struct cvmx_usb_pipe_list *list, struct cvmx_usb_pipe *pipe)
492 {
493 pipe->next = NULL;
494 pipe->prev = list->tail;
495 if (list->tail)
496 list->tail->next = pipe;
497 else
498 list->head = pipe;
499 list->tail = pipe;
500 }
501
502
503 /**
504 * Remove a pipe from a list
505 * @list: List to remove pipe from
506 * @pipe: Pipe to remove
507 */
508 static inline void __cvmx_usb_remove_pipe(struct cvmx_usb_pipe_list *list, struct cvmx_usb_pipe *pipe)
509 {
510 if (list->head == pipe) {
511 list->head = pipe->next;
512 pipe->next = NULL;
513 if (list->head)
514 list->head->prev = NULL;
515 else
516 list->tail = NULL;
517 } else if (list->tail == pipe) {
518 list->tail = pipe->prev;
519 list->tail->next = NULL;
520 pipe->prev = NULL;
521 } else {
522 pipe->prev->next = pipe->next;
523 pipe->next->prev = pipe->prev;
524 pipe->prev = NULL;
525 pipe->next = NULL;
526 }
527 }
528
529
530 /**
531 * Initialize a USB port for use. This must be called before any
532 * other access to the Octeon USB port is made. The port starts
533 * off in the disabled state.
534 *
535 * @state: Pointer to an empty struct cvmx_usb_state
536 * that will be populated by the initialize call.
537 * This structure is then passed to all other USB
538 * functions.
539 * @usb_port_number:
540 * Which Octeon USB port to initialize.
541 *
542 * Returns: 0 or a negative error code.
543 */
544 int cvmx_usb_initialize(struct cvmx_usb_state *state, int usb_port_number)
545 {
546 union cvmx_usbnx_clk_ctl usbn_clk_ctl;
547 union cvmx_usbnx_usbp_ctl_status usbn_usbp_ctl_status;
548 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
549 enum cvmx_usb_initialize_flags flags = 0;
550
551 /* Make sure that state is large enough to store the internal state */
552 if (sizeof(*state) < sizeof(*usb))
553 return -EINVAL;
554 /* At first allow 0-1 for the usb port number */
555 if ((usb_port_number < 0) || (usb_port_number > 1))
556 return -EINVAL;
557 /* For all chips except 52XX there is only one port */
558 if (!OCTEON_IS_MODEL(OCTEON_CN52XX) && (usb_port_number > 0))
559 return -EINVAL;
560 /* Try to determine clock type automatically */
561 if (octeon_usb_get_clock_type() == USB_CLOCK_TYPE_CRYSTAL_12) {
562 /* Only 12 MHZ crystals are supported */
563 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI;
564 } else {
565 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND;
566
567 switch (octeon_usb_get_clock_type()) {
568 case USB_CLOCK_TYPE_REF_12:
569 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ;
570 break;
571 case USB_CLOCK_TYPE_REF_24:
572 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ;
573 break;
574 case USB_CLOCK_TYPE_REF_48:
575 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ;
576 break;
577 default:
578 return -EINVAL;
579 break;
580 }
581 }
582
583 memset(usb, 0, sizeof(*usb));
584 usb->init_flags = flags;
585
586 /* Initialize the USB state structure */
587 {
588 int i;
589 usb->index = usb_port_number;
590
591 /* Initialize the transaction double linked list */
592 usb->free_transaction_head = NULL;
593 usb->free_transaction_tail = NULL;
594 for (i = 0; i < MAX_TRANSACTIONS; i++)
595 __cvmx_usb_free_transaction(usb, usb->transaction + i);
596 for (i = 0; i < MAX_PIPES; i++)
597 __cvmx_usb_append_pipe(&usb->free_pipes, usb->pipe + i);
598 }
599
600 /*
601 * Power On Reset and PHY Initialization
602 *
603 * 1. Wait for DCOK to assert (nothing to do)
604 *
605 * 2a. Write USBN0/1_CLK_CTL[POR] = 1 and
606 * USBN0/1_CLK_CTL[HRST,PRST,HCLK_RST] = 0
607 */
608 usbn_clk_ctl.u64 = __cvmx_usb_read_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index));
609 usbn_clk_ctl.s.por = 1;
610 usbn_clk_ctl.s.hrst = 0;
611 usbn_clk_ctl.s.prst = 0;
612 usbn_clk_ctl.s.hclk_rst = 0;
613 usbn_clk_ctl.s.enable = 0;
614 /*
615 * 2b. Select the USB reference clock/crystal parameters by writing
616 * appropriate values to USBN0/1_CLK_CTL[P_C_SEL, P_RTYPE, P_COM_ON]
617 */
618 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND) {
619 /*
620 * The USB port uses 12/24/48MHz 2.5V board clock
621 * source at USB_XO. USB_XI should be tied to GND.
622 * Most Octeon evaluation boards require this setting
623 */
624 if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
625 usbn_clk_ctl.cn31xx.p_rclk = 1; /* From CN31XX,CN30XX manual */
626 usbn_clk_ctl.cn31xx.p_xenbn = 0;
627 } else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))
628 usbn_clk_ctl.cn56xx.p_rtype = 2; /* From CN56XX,CN50XX manual */
629 else
630 usbn_clk_ctl.cn52xx.p_rtype = 1; /* From CN52XX manual */
631
632 switch (flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK) {
633 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ:
634 usbn_clk_ctl.s.p_c_sel = 0;
635 break;
636 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ:
637 usbn_clk_ctl.s.p_c_sel = 1;
638 break;
639 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ:
640 usbn_clk_ctl.s.p_c_sel = 2;
641 break;
642 }
643 } else {
644 /*
645 * The USB port uses a 12MHz crystal as clock source
646 * at USB_XO and USB_XI
647 */
648 if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
649 usbn_clk_ctl.cn31xx.p_rclk = 1; /* From CN31XX,CN30XX manual */
650 usbn_clk_ctl.cn31xx.p_xenbn = 1;
651 } else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))
652 usbn_clk_ctl.cn56xx.p_rtype = 0; /* From CN56XX,CN50XX manual */
653 else
654 usbn_clk_ctl.cn52xx.p_rtype = 0; /* From CN52XX manual */
655
656 usbn_clk_ctl.s.p_c_sel = 0;
657 }
658 /*
659 * 2c. Select the HCLK via writing USBN0/1_CLK_CTL[DIVIDE, DIVIDE2] and
660 * setting USBN0/1_CLK_CTL[ENABLE] = 1. Divide the core clock down
661 * such that USB is as close as possible to 125Mhz
662 */
663 {
664 int divisor = (octeon_get_clock_rate()+125000000-1)/125000000;
665 if (divisor < 4) /* Lower than 4 doesn't seem to work properly */
666 divisor = 4;
667 usbn_clk_ctl.s.divide = divisor;
668 usbn_clk_ctl.s.divide2 = 0;
669 }
670 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
671 usbn_clk_ctl.u64);
672 /* 2d. Write USBN0/1_CLK_CTL[HCLK_RST] = 1 */
673 usbn_clk_ctl.s.hclk_rst = 1;
674 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
675 usbn_clk_ctl.u64);
676 /* 2e. Wait 64 core-clock cycles for HCLK to stabilize */
677 cvmx_wait(64);
678 /*
679 * 3. Program the power-on reset field in the USBN clock-control
680 * register:
681 * USBN_CLK_CTL[POR] = 0
682 */
683 usbn_clk_ctl.s.por = 0;
684 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
685 usbn_clk_ctl.u64);
686 /* 4. Wait 1 ms for PHY clock to start */
687 mdelay(1);
688 /*
689 * 5. Program the Reset input from automatic test equipment field in the
690 * USBP control and status register:
691 * USBN_USBP_CTL_STATUS[ATE_RESET] = 1
692 */
693 usbn_usbp_ctl_status.u64 = __cvmx_usb_read_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index));
694 usbn_usbp_ctl_status.s.ate_reset = 1;
695 __cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
696 usbn_usbp_ctl_status.u64);
697 /* 6. Wait 10 cycles */
698 cvmx_wait(10);
699 /*
700 * 7. Clear ATE_RESET field in the USBN clock-control register:
701 * USBN_USBP_CTL_STATUS[ATE_RESET] = 0
702 */
703 usbn_usbp_ctl_status.s.ate_reset = 0;
704 __cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
705 usbn_usbp_ctl_status.u64);
706 /*
707 * 8. Program the PHY reset field in the USBN clock-control register:
708 * USBN_CLK_CTL[PRST] = 1
709 */
710 usbn_clk_ctl.s.prst = 1;
711 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
712 usbn_clk_ctl.u64);
713 /*
714 * 9. Program the USBP control and status register to select host or
715 * device mode. USBN_USBP_CTL_STATUS[HST_MODE] = 0 for host, = 1 for
716 * device
717 */
718 usbn_usbp_ctl_status.s.hst_mode = 0;
719 __cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
720 usbn_usbp_ctl_status.u64);
721 /* 10. Wait 1 us */
722 udelay(1);
723 /*
724 * 11. Program the hreset_n field in the USBN clock-control register:
725 * USBN_CLK_CTL[HRST] = 1
726 */
727 usbn_clk_ctl.s.hrst = 1;
728 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
729 usbn_clk_ctl.u64);
730 /* 12. Proceed to USB core initialization */
731 usbn_clk_ctl.s.enable = 1;
732 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
733 usbn_clk_ctl.u64);
734 udelay(1);
735
736 /*
737 * USB Core Initialization
738 *
739 * 1. Read USBC_GHWCFG1, USBC_GHWCFG2, USBC_GHWCFG3, USBC_GHWCFG4 to
740 * determine USB core configuration parameters.
741 *
742 * Nothing needed
743 *
744 * 2. Program the following fields in the global AHB configuration
745 * register (USBC_GAHBCFG)
746 * DMA mode, USBC_GAHBCFG[DMAEn]: 1 = DMA mode, 0 = slave mode
747 * Burst length, USBC_GAHBCFG[HBSTLEN] = 0
748 * Nonperiodic TxFIFO empty level (slave mode only),
749 * USBC_GAHBCFG[NPTXFEMPLVL]
750 * Periodic TxFIFO empty level (slave mode only),
751 * USBC_GAHBCFG[PTXFEMPLVL]
752 * Global interrupt mask, USBC_GAHBCFG[GLBLINTRMSK] = 1
753 */
754 {
755 union cvmx_usbcx_gahbcfg usbcx_gahbcfg;
756 /* Due to an errata, CN31XX doesn't support DMA */
757 if (OCTEON_IS_MODEL(OCTEON_CN31XX))
758 usb->init_flags |= CVMX_USB_INITIALIZE_FLAGS_NO_DMA;
759 usbcx_gahbcfg.u32 = 0;
760 usbcx_gahbcfg.s.dmaen = !(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA);
761 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
762 usb->idle_hardware_channels = 0x1; /* Only use one channel with non DMA */
763 else if (OCTEON_IS_MODEL(OCTEON_CN5XXX))
764 usb->idle_hardware_channels = 0xf7; /* CN5XXX have an errata with channel 3 */
765 else
766 usb->idle_hardware_channels = 0xff;
767 usbcx_gahbcfg.s.hbstlen = 0;
768 usbcx_gahbcfg.s.nptxfemplvl = 1;
769 usbcx_gahbcfg.s.ptxfemplvl = 1;
770 usbcx_gahbcfg.s.glblintrmsk = 1;
771 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GAHBCFG(usb->index),
772 usbcx_gahbcfg.u32);
773 }
774 /*
775 * 3. Program the following fields in USBC_GUSBCFG register.
776 * HS/FS timeout calibration, USBC_GUSBCFG[TOUTCAL] = 0
777 * ULPI DDR select, USBC_GUSBCFG[DDRSEL] = 0
778 * USB turnaround time, USBC_GUSBCFG[USBTRDTIM] = 0x5
779 * PHY low-power clock select, USBC_GUSBCFG[PHYLPWRCLKSEL] = 0
780 */
781 {
782 union cvmx_usbcx_gusbcfg usbcx_gusbcfg;
783 usbcx_gusbcfg.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GUSBCFG(usb->index));
784 usbcx_gusbcfg.s.toutcal = 0;
785 usbcx_gusbcfg.s.ddrsel = 0;
786 usbcx_gusbcfg.s.usbtrdtim = 0x5;
787 usbcx_gusbcfg.s.phylpwrclksel = 0;
788 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GUSBCFG(usb->index),
789 usbcx_gusbcfg.u32);
790 }
791 /*
792 * 4. The software must unmask the following bits in the USBC_GINTMSK
793 * register.
794 * OTG interrupt mask, USBC_GINTMSK[OTGINTMSK] = 1
795 * Mode mismatch interrupt mask, USBC_GINTMSK[MODEMISMSK] = 1
796 */
797 {
798 union cvmx_usbcx_gintmsk usbcx_gintmsk;
799 int channel;
800
801 usbcx_gintmsk.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GINTMSK(usb->index));
802 usbcx_gintmsk.s.otgintmsk = 1;
803 usbcx_gintmsk.s.modemismsk = 1;
804 usbcx_gintmsk.s.hchintmsk = 1;
805 usbcx_gintmsk.s.sofmsk = 0;
806 /* We need RX FIFO interrupts if we don't have DMA */
807 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
808 usbcx_gintmsk.s.rxflvlmsk = 1;
809 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTMSK(usb->index),
810 usbcx_gintmsk.u32);
811
812 /* Disable all channel interrupts. We'll enable them per channel later */
813 for (channel = 0; channel < 8; channel++)
814 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), 0);
815 }
816
817 {
818 /*
819 * Host Port Initialization
820 *
821 * 1. Program the host-port interrupt-mask field to unmask,
822 * USBC_GINTMSK[PRTINT] = 1
823 */
824 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk,
825 prtintmsk, 1);
826 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk,
827 disconnintmsk, 1);
828 /*
829 * 2. Program the USBC_HCFG register to select full-speed host
830 * or high-speed host.
831 */
832 {
833 union cvmx_usbcx_hcfg usbcx_hcfg;
834 usbcx_hcfg.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCFG(usb->index));
835 usbcx_hcfg.s.fslssupp = 0;
836 usbcx_hcfg.s.fslspclksel = 0;
837 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCFG(usb->index), usbcx_hcfg.u32);
838 }
839 /*
840 * 3. Program the port power bit to drive VBUS on the USB,
841 * USBC_HPRT[PRTPWR] = 1
842 */
843 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt, prtpwr, 1);
844
845 /*
846 * Steps 4-15 from the manual are done later in the port enable
847 */
848 }
849
850 return 0;
851 }
852
853
854 /**
855 * Shutdown a USB port after a call to cvmx_usb_initialize().
856 * The port should be disabled with all pipes closed when this
857 * function is called.
858 *
859 * @state: USB device state populated by
860 * cvmx_usb_initialize().
861 *
862 * Returns: 0 or a negative error code.
863 */
864 int cvmx_usb_shutdown(struct cvmx_usb_state *state)
865 {
866 union cvmx_usbnx_clk_ctl usbn_clk_ctl;
867 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
868
869 /* Make sure all pipes are closed */
870 if (usb->idle_pipes.head ||
871 usb->active_pipes[CVMX_USB_TRANSFER_ISOCHRONOUS].head ||
872 usb->active_pipes[CVMX_USB_TRANSFER_INTERRUPT].head ||
873 usb->active_pipes[CVMX_USB_TRANSFER_CONTROL].head ||
874 usb->active_pipes[CVMX_USB_TRANSFER_BULK].head)
875 return -EBUSY;
876
877 /* Disable the clocks and put them in power on reset */
878 usbn_clk_ctl.u64 = __cvmx_usb_read_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index));
879 usbn_clk_ctl.s.enable = 1;
880 usbn_clk_ctl.s.por = 1;
881 usbn_clk_ctl.s.hclk_rst = 1;
882 usbn_clk_ctl.s.prst = 0;
883 usbn_clk_ctl.s.hrst = 0;
884 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
885 usbn_clk_ctl.u64);
886 return 0;
887 }
888
889
890 /**
891 * Enable a USB port. After this call succeeds, the USB port is
892 * online and servicing requests.
893 *
894 * @state: USB device state populated by
895 * cvmx_usb_initialize().
896 *
897 * Returns: 0 or a negative error code.
898 */
899 int cvmx_usb_enable(struct cvmx_usb_state *state)
900 {
901 union cvmx_usbcx_ghwcfg3 usbcx_ghwcfg3;
902 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
903
904 usb->usbcx_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
905
906 /*
907 * If the port is already enabled the just return. We don't need to do
908 * anything
909 */
910 if (usb->usbcx_hprt.s.prtena)
911 return 0;
912
913 /* If there is nothing plugged into the port then fail immediately */
914 if (!usb->usbcx_hprt.s.prtconnsts) {
915 return -ETIMEDOUT;
916 }
917
918 /* Program the port reset bit to start the reset process */
919 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt, prtrst, 1);
920
921 /*
922 * Wait at least 50ms (high speed), or 10ms (full speed) for the reset
923 * process to complete.
924 */
925 mdelay(50);
926
927 /* Program the port reset bit to 0, USBC_HPRT[PRTRST] = 0 */
928 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt, prtrst, 0);
929
930 /* Wait for the USBC_HPRT[PRTENA]. */
931 if (CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt,
932 prtena, ==, 1, 100000))
933 return -ETIMEDOUT;
934
935 /* Read the port speed field to get the enumerated speed, USBC_HPRT[PRTSPD]. */
936 usb->usbcx_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
937 usbcx_ghwcfg3.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GHWCFG3(usb->index));
938
939 /*
940 * 13. Program the USBC_GRXFSIZ register to select the size of the
941 * receive FIFO (25%).
942 */
943 USB_SET_FIELD32(CVMX_USBCX_GRXFSIZ(usb->index), union cvmx_usbcx_grxfsiz,
944 rxfdep, usbcx_ghwcfg3.s.dfifodepth / 4);
945 /*
946 * 14. Program the USBC_GNPTXFSIZ register to select the size and the
947 * start address of the non- periodic transmit FIFO for nonperiodic
948 * transactions (50%).
949 */
950 {
951 union cvmx_usbcx_gnptxfsiz siz;
952 siz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index));
953 siz.s.nptxfdep = usbcx_ghwcfg3.s.dfifodepth / 2;
954 siz.s.nptxfstaddr = usbcx_ghwcfg3.s.dfifodepth / 4;
955 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index), siz.u32);
956 }
957 /*
958 * 15. Program the USBC_HPTXFSIZ register to select the size and start
959 * address of the periodic transmit FIFO for periodic transactions
960 * (25%).
961 */
962 {
963 union cvmx_usbcx_hptxfsiz siz;
964 siz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPTXFSIZ(usb->index));
965 siz.s.ptxfsize = usbcx_ghwcfg3.s.dfifodepth / 4;
966 siz.s.ptxfstaddr = 3 * usbcx_ghwcfg3.s.dfifodepth / 4;
967 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HPTXFSIZ(usb->index), siz.u32);
968 }
969 /* Flush all FIFOs */
970 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), union cvmx_usbcx_grstctl, txfnum, 0x10);
971 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), union cvmx_usbcx_grstctl, txfflsh, 1);
972 CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), union cvmx_usbcx_grstctl,
973 txfflsh, ==, 0, 100);
974 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), union cvmx_usbcx_grstctl, rxfflsh, 1);
975 CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), union cvmx_usbcx_grstctl,
976 rxfflsh, ==, 0, 100);
977
978 return 0;
979 }
980
981
982 /**
983 * Disable a USB port. After this call the USB port will not
984 * generate data transfers and will not generate events.
985 * Transactions in process will fail and call their
986 * associated callbacks.
987 *
988 * @state: USB device state populated by
989 * cvmx_usb_initialize().
990 *
991 * Returns: 0 or a negative error code.
992 */
993 int cvmx_usb_disable(struct cvmx_usb_state *state)
994 {
995 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
996
997 /* Disable the port */
998 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt, prtena, 1);
999 return 0;
1000 }
1001
1002
1003 /**
1004 * Get the current state of the USB port. Use this call to
1005 * determine if the usb port has anything connected, is enabled,
1006 * or has some sort of error condition. The return value of this
1007 * call has "changed" bits to signal of the value of some fields
1008 * have changed between calls. These "changed" fields are based
1009 * on the last call to cvmx_usb_set_status(). In order to clear
1010 * them, you must update the status through cvmx_usb_set_status().
1011 *
1012 * @state: USB device state populated by
1013 * cvmx_usb_initialize().
1014 *
1015 * Returns: Port status information
1016 */
1017 struct cvmx_usb_port_status cvmx_usb_get_status(struct cvmx_usb_state *state)
1018 {
1019 union cvmx_usbcx_hprt usbc_hprt;
1020 struct cvmx_usb_port_status result;
1021 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
1022
1023 memset(&result, 0, sizeof(result));
1024
1025 usbc_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
1026 result.port_enabled = usbc_hprt.s.prtena;
1027 result.port_over_current = usbc_hprt.s.prtovrcurract;
1028 result.port_powered = usbc_hprt.s.prtpwr;
1029 result.port_speed = usbc_hprt.s.prtspd;
1030 result.connected = usbc_hprt.s.prtconnsts;
1031 result.connect_change = (result.connected != usb->port_status.connected);
1032
1033 return result;
1034 }
1035
1036
1037 /**
1038 * Set the current state of the USB port. The status is used as
1039 * a reference for the "changed" bits returned by
1040 * cvmx_usb_get_status(). Other than serving as a reference, the
1041 * status passed to this function is not used. No fields can be
1042 * changed through this call.
1043 *
1044 * @state: USB device state populated by
1045 * cvmx_usb_initialize().
1046 * @port_status:
1047 * Port status to set, most like returned by cvmx_usb_get_status()
1048 */
1049 void cvmx_usb_set_status(struct cvmx_usb_state *state, struct cvmx_usb_port_status port_status)
1050 {
1051 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
1052 usb->port_status = port_status;
1053 return;
1054 }
1055
1056
1057 /**
1058 * Convert a USB transaction into a handle
1059 *
1060 * @usb: USB device state populated by
1061 * cvmx_usb_initialize().
1062 * @transaction:
1063 * Transaction to get handle for
1064 *
1065 * Returns: Handle
1066 */
1067 static inline int __cvmx_usb_get_submit_handle(struct cvmx_usb_internal_state *usb,
1068 struct cvmx_usb_transaction *transaction)
1069 {
1070 return ((unsigned long)transaction - (unsigned long)usb->transaction) /
1071 sizeof(*transaction);
1072 }
1073
1074
1075 /**
1076 * Convert a USB pipe into a handle
1077 *
1078 * @usb: USB device state populated by
1079 * cvmx_usb_initialize().
1080 * @pipe: Pipe to get handle for
1081 *
1082 * Returns: Handle
1083 */
1084 static inline int __cvmx_usb_get_pipe_handle(struct cvmx_usb_internal_state *usb,
1085 struct cvmx_usb_pipe *pipe)
1086 {
1087 return ((unsigned long)pipe - (unsigned long)usb->pipe) / sizeof(*pipe);
1088 }
1089
1090
1091 /**
1092 * Open a virtual pipe between the host and a USB device. A pipe
1093 * must be opened before data can be transferred between a device
1094 * and Octeon.
1095 *
1096 * @state: USB device state populated by
1097 * cvmx_usb_initialize().
1098 * @device_addr:
1099 * USB device address to open the pipe to
1100 * (0-127).
1101 * @endpoint_num:
1102 * USB endpoint number to open the pipe to
1103 * (0-15).
1104 * @device_speed:
1105 * The speed of the device the pipe is going
1106 * to. This must match the device's speed,
1107 * which may be different than the port speed.
1108 * @max_packet: The maximum packet length the device can
1109 * transmit/receive (low speed=0-8, full
1110 * speed=0-1023, high speed=0-1024). This value
1111 * comes from the standard endpoint descriptor
1112 * field wMaxPacketSize bits <10:0>.
1113 * @transfer_type:
1114 * The type of transfer this pipe is for.
1115 * @transfer_dir:
1116 * The direction the pipe is in. This is not
1117 * used for control pipes.
1118 * @interval: For ISOCHRONOUS and INTERRUPT transfers,
1119 * this is how often the transfer is scheduled
1120 * for. All other transfers should specify
1121 * zero. The units are in frames (8000/sec at
1122 * high speed, 1000/sec for full speed).
1123 * @multi_count:
1124 * For high speed devices, this is the maximum
1125 * allowed number of packet per microframe.
1126 * Specify zero for non high speed devices. This
1127 * value comes from the standard endpoint descriptor
1128 * field wMaxPacketSize bits <12:11>.
1129 * @hub_device_addr:
1130 * Hub device address this device is connected
1131 * to. Devices connected directly to Octeon
1132 * use zero. This is only used when the device
1133 * is full/low speed behind a high speed hub.
1134 * The address will be of the high speed hub,
1135 * not and full speed hubs after it.
1136 * @hub_port: Which port on the hub the device is
1137 * connected. Use zero for devices connected
1138 * directly to Octeon. Like hub_device_addr,
1139 * this is only used for full/low speed
1140 * devices behind a high speed hub.
1141 *
1142 * Returns: A non negative value is a pipe handle. Negative
1143 * values are error codes.
1144 */
1145 int cvmx_usb_open_pipe(struct cvmx_usb_state *state,
1146 int device_addr, int endpoint_num,
1147 enum cvmx_usb_speed device_speed, int max_packet,
1148 enum cvmx_usb_transfer transfer_type,
1149 enum cvmx_usb_direction transfer_dir, int interval,
1150 int multi_count, int hub_device_addr, int hub_port)
1151 {
1152 struct cvmx_usb_pipe *pipe;
1153 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
1154
1155 if (unlikely((device_addr < 0) || (device_addr > MAX_USB_ADDRESS)))
1156 return -EINVAL;
1157 if (unlikely((endpoint_num < 0) || (endpoint_num > MAX_USB_ENDPOINT)))
1158 return -EINVAL;
1159 if (unlikely(device_speed > CVMX_USB_SPEED_LOW))
1160 return -EINVAL;
1161 if (unlikely((max_packet <= 0) || (max_packet > 1024)))
1162 return -EINVAL;
1163 if (unlikely(transfer_type > CVMX_USB_TRANSFER_INTERRUPT))
1164 return -EINVAL;
1165 if (unlikely((transfer_dir != CVMX_USB_DIRECTION_OUT) &&
1166 (transfer_dir != CVMX_USB_DIRECTION_IN)))
1167 return -EINVAL;
1168 if (unlikely(interval < 0))
1169 return -EINVAL;
1170 if (unlikely((transfer_type == CVMX_USB_TRANSFER_CONTROL) && interval))
1171 return -EINVAL;
1172 if (unlikely(multi_count < 0))
1173 return -EINVAL;
1174 if (unlikely((device_speed != CVMX_USB_SPEED_HIGH) &&
1175 (multi_count != 0)))
1176 return -EINVAL;
1177 if (unlikely((hub_device_addr < 0) || (hub_device_addr > MAX_USB_ADDRESS)))
1178 return -EINVAL;
1179 if (unlikely((hub_port < 0) || (hub_port > MAX_USB_HUB_PORT)))
1180 return -EINVAL;
1181
1182 /* Find a free pipe */
1183 pipe = usb->free_pipes.head;
1184 if (!pipe)
1185 return -ENOMEM;
1186 __cvmx_usb_remove_pipe(&usb->free_pipes, pipe);
1187 pipe->flags = __CVMX_USB_PIPE_FLAGS_OPEN;
1188 if ((device_speed == CVMX_USB_SPEED_HIGH) &&
1189 (transfer_dir == CVMX_USB_DIRECTION_OUT) &&
1190 (transfer_type == CVMX_USB_TRANSFER_BULK))
1191 pipe->flags |= __CVMX_USB_PIPE_FLAGS_NEED_PING;
1192 pipe->device_addr = device_addr;
1193 pipe->endpoint_num = endpoint_num;
1194 pipe->device_speed = device_speed;
1195 pipe->max_packet = max_packet;
1196 pipe->transfer_type = transfer_type;
1197 pipe->transfer_dir = transfer_dir;
1198 /*
1199 * All pipes use interval to rate limit NAK processing. Force an
1200 * interval if one wasn't supplied
1201 */
1202 if (!interval)
1203 interval = 1;
1204 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1205 pipe->interval = interval*8;
1206 /* Force start splits to be schedule on uFrame 0 */
1207 pipe->next_tx_frame = ((usb->frame_number+7)&~7) + pipe->interval;
1208 } else {
1209 pipe->interval = interval;
1210 pipe->next_tx_frame = usb->frame_number + pipe->interval;
1211 }
1212 pipe->multi_count = multi_count;
1213 pipe->hub_device_addr = hub_device_addr;
1214 pipe->hub_port = hub_port;
1215 pipe->pid_toggle = 0;
1216 pipe->split_sc_frame = -1;
1217 __cvmx_usb_append_pipe(&usb->idle_pipes, pipe);
1218
1219 /*
1220 * We don't need to tell the hardware about this pipe yet since
1221 * it doesn't have any submitted requests
1222 */
1223
1224 return __cvmx_usb_get_pipe_handle(usb, pipe);
1225 }
1226
1227
1228 /**
1229 * Poll the RX FIFOs and remove data as needed. This function is only used
1230 * in non DMA mode. It is very important that this function be called quickly
1231 * enough to prevent FIFO overflow.
1232 *
1233 * @usb: USB device state populated by
1234 * cvmx_usb_initialize().
1235 */
1236 static void __cvmx_usb_poll_rx_fifo(struct cvmx_usb_internal_state *usb)
1237 {
1238 union cvmx_usbcx_grxstsph rx_status;
1239 int channel;
1240 int bytes;
1241 uint64_t address;
1242 uint32_t *ptr;
1243
1244 rx_status.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GRXSTSPH(usb->index));
1245 /* Only read data if IN data is there */
1246 if (rx_status.s.pktsts != 2)
1247 return;
1248 /* Check if no data is available */
1249 if (!rx_status.s.bcnt)
1250 return;
1251
1252 channel = rx_status.s.chnum;
1253 bytes = rx_status.s.bcnt;
1254 if (!bytes)
1255 return;
1256
1257 /* Get where the DMA engine would have written this data */
1258 address = __cvmx_usb_read_csr64(usb, CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8);
1259 ptr = cvmx_phys_to_ptr(address);
1260 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8, address + bytes);
1261
1262 /* Loop writing the FIFO data for this packet into memory */
1263 while (bytes > 0) {
1264 *ptr++ = __cvmx_usb_read_csr32(usb, USB_FIFO_ADDRESS(channel, usb->index));
1265 bytes -= 4;
1266 }
1267 CVMX_SYNCW;
1268
1269 return;
1270 }
1271
1272
1273 /**
1274 * Fill the TX hardware fifo with data out of the software
1275 * fifos
1276 *
1277 * @usb: USB device state populated by
1278 * cvmx_usb_initialize().
1279 * @fifo: Software fifo to use
1280 * @available: Amount of space in the hardware fifo
1281 *
1282 * Returns: Non zero if the hardware fifo was too small and needs
1283 * to be serviced again.
1284 */
1285 static int __cvmx_usb_fill_tx_hw(struct cvmx_usb_internal_state *usb, struct cvmx_usb_tx_fifo *fifo, int available)
1286 {
1287 /*
1288 * We're done either when there isn't anymore space or the software FIFO
1289 * is empty
1290 */
1291 while (available && (fifo->head != fifo->tail)) {
1292 int i = fifo->tail;
1293 const uint32_t *ptr = cvmx_phys_to_ptr(fifo->entry[i].address);
1294 uint64_t csr_address = USB_FIFO_ADDRESS(fifo->entry[i].channel, usb->index) ^ 4;
1295 int words = available;
1296
1297 /* Limit the amount of data to waht the SW fifo has */
1298 if (fifo->entry[i].size <= available) {
1299 words = fifo->entry[i].size;
1300 fifo->tail++;
1301 if (fifo->tail > MAX_CHANNELS)
1302 fifo->tail = 0;
1303 }
1304
1305 /* Update the next locations and counts */
1306 available -= words;
1307 fifo->entry[i].address += words * 4;
1308 fifo->entry[i].size -= words;
1309
1310 /*
1311 * Write the HW fifo data. The read every three writes is due
1312 * to an errata on CN3XXX chips
1313 */
1314 while (words > 3) {
1315 cvmx_write64_uint32(csr_address, *ptr++);
1316 cvmx_write64_uint32(csr_address, *ptr++);
1317 cvmx_write64_uint32(csr_address, *ptr++);
1318 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
1319 words -= 3;
1320 }
1321 cvmx_write64_uint32(csr_address, *ptr++);
1322 if (--words) {
1323 cvmx_write64_uint32(csr_address, *ptr++);
1324 if (--words)
1325 cvmx_write64_uint32(csr_address, *ptr++);
1326 }
1327 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
1328 }
1329 return fifo->head != fifo->tail;
1330 }
1331
1332
1333 /**
1334 * Check the hardware FIFOs and fill them as needed
1335 *
1336 * @usb: USB device state populated by
1337 * cvmx_usb_initialize().
1338 */
1339 static void __cvmx_usb_poll_tx_fifo(struct cvmx_usb_internal_state *usb)
1340 {
1341 if (usb->periodic.head != usb->periodic.tail) {
1342 union cvmx_usbcx_hptxsts tx_status;
1343 tx_status.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPTXSTS(usb->index));
1344 if (__cvmx_usb_fill_tx_hw(usb, &usb->periodic, tx_status.s.ptxfspcavail))
1345 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk, ptxfempmsk, 1);
1346 else
1347 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk, ptxfempmsk, 0);
1348 }
1349
1350 if (usb->nonperiodic.head != usb->nonperiodic.tail) {
1351 union cvmx_usbcx_gnptxsts tx_status;
1352 tx_status.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GNPTXSTS(usb->index));
1353 if (__cvmx_usb_fill_tx_hw(usb, &usb->nonperiodic, tx_status.s.nptxfspcavail))
1354 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk, nptxfempmsk, 1);
1355 else
1356 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk, nptxfempmsk, 0);
1357 }
1358
1359 return;
1360 }
1361
1362
1363 /**
1364 * Fill the TX FIFO with an outgoing packet
1365 *
1366 * @usb: USB device state populated by
1367 * cvmx_usb_initialize().
1368 * @channel: Channel number to get packet from
1369 */
1370 static void __cvmx_usb_fill_tx_fifo(struct cvmx_usb_internal_state *usb, int channel)
1371 {
1372 union cvmx_usbcx_hccharx hcchar;
1373 union cvmx_usbcx_hcspltx usbc_hcsplt;
1374 union cvmx_usbcx_hctsizx usbc_hctsiz;
1375 struct cvmx_usb_tx_fifo *fifo;
1376
1377 /* We only need to fill data on outbound channels */
1378 hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index));
1379 if (hcchar.s.epdir != CVMX_USB_DIRECTION_OUT)
1380 return;
1381
1382 /* OUT Splits only have data on the start and not the complete */
1383 usbc_hcsplt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCSPLTX(channel, usb->index));
1384 if (usbc_hcsplt.s.spltena && usbc_hcsplt.s.compsplt)
1385 return;
1386
1387 /* Find out how many bytes we need to fill and convert it into 32bit words */
1388 usbc_hctsiz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index));
1389 if (!usbc_hctsiz.s.xfersize)
1390 return;
1391
1392 if ((hcchar.s.eptype == CVMX_USB_TRANSFER_INTERRUPT) ||
1393 (hcchar.s.eptype == CVMX_USB_TRANSFER_ISOCHRONOUS))
1394 fifo = &usb->periodic;
1395 else
1396 fifo = &usb->nonperiodic;
1397
1398 fifo->entry[fifo->head].channel = channel;
1399 fifo->entry[fifo->head].address = __cvmx_usb_read_csr64(usb, CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8);
1400 fifo->entry[fifo->head].size = (usbc_hctsiz.s.xfersize+3)>>2;
1401 fifo->head++;
1402 if (fifo->head > MAX_CHANNELS)
1403 fifo->head = 0;
1404
1405 __cvmx_usb_poll_tx_fifo(usb);
1406
1407 return;
1408 }
1409
1410 /**
1411 * Perform channel specific setup for Control transactions. All
1412 * the generic stuff will already have been done in
1413 * __cvmx_usb_start_channel()
1414 *
1415 * @usb: USB device state populated by
1416 * cvmx_usb_initialize().
1417 * @channel: Channel to setup
1418 * @pipe: Pipe for control transaction
1419 */
1420 static void __cvmx_usb_start_channel_control(struct cvmx_usb_internal_state *usb,
1421 int channel,
1422 struct cvmx_usb_pipe *pipe)
1423 {
1424 struct cvmx_usb_transaction *transaction = pipe->head;
1425 union cvmx_usb_control_header *header =
1426 cvmx_phys_to_ptr(transaction->control_header);
1427 int bytes_to_transfer = transaction->buffer_length - transaction->actual_bytes;
1428 int packets_to_transfer;
1429 union cvmx_usbcx_hctsizx usbc_hctsiz;
1430
1431 usbc_hctsiz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index));
1432
1433 switch (transaction->stage) {
1434 case CVMX_USB_STAGE_NON_CONTROL:
1435 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE:
1436 cvmx_dprintf("%s: ERROR - Non control stage\n", __FUNCTION__);
1437 break;
1438 case CVMX_USB_STAGE_SETUP:
1439 usbc_hctsiz.s.pid = 3; /* Setup */
1440 bytes_to_transfer = sizeof(*header);
1441 /* All Control operations start with a setup going OUT */
1442 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), union cvmx_usbcx_hccharx, epdir, CVMX_USB_DIRECTION_OUT);
1443 /*
1444 * Setup send the control header instead of the buffer data. The
1445 * buffer data will be used in the next stage
1446 */
1447 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8, transaction->control_header);
1448 break;
1449 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE:
1450 usbc_hctsiz.s.pid = 3; /* Setup */
1451 bytes_to_transfer = 0;
1452 /* All Control operations start with a setup going OUT */
1453 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), union cvmx_usbcx_hccharx, epdir, CVMX_USB_DIRECTION_OUT);
1454 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), union cvmx_usbcx_hcspltx, compsplt, 1);
1455 break;
1456 case CVMX_USB_STAGE_DATA:
1457 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1458 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1459 if (header->s.request_type & 0x80)
1460 bytes_to_transfer = 0;
1461 else if (bytes_to_transfer > pipe->max_packet)
1462 bytes_to_transfer = pipe->max_packet;
1463 }
1464 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1465 union cvmx_usbcx_hccharx, epdir,
1466 ((header->s.request_type & 0x80) ?
1467 CVMX_USB_DIRECTION_IN :
1468 CVMX_USB_DIRECTION_OUT));
1469 break;
1470 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE:
1471 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1472 if (!(header->s.request_type & 0x80))
1473 bytes_to_transfer = 0;
1474 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1475 union cvmx_usbcx_hccharx, epdir,
1476 ((header->s.request_type & 0x80) ?
1477 CVMX_USB_DIRECTION_IN :
1478 CVMX_USB_DIRECTION_OUT));
1479 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), union cvmx_usbcx_hcspltx, compsplt, 1);
1480 break;
1481 case CVMX_USB_STAGE_STATUS:
1482 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1483 bytes_to_transfer = 0;
1484 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), union cvmx_usbcx_hccharx, epdir,
1485 ((header->s.request_type & 0x80) ?
1486 CVMX_USB_DIRECTION_OUT :
1487 CVMX_USB_DIRECTION_IN));
1488 break;
1489 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE:
1490 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1491 bytes_to_transfer = 0;
1492 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), union cvmx_usbcx_hccharx, epdir,
1493 ((header->s.request_type & 0x80) ?
1494 CVMX_USB_DIRECTION_OUT :
1495 CVMX_USB_DIRECTION_IN));
1496 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), union cvmx_usbcx_hcspltx, compsplt, 1);
1497 break;
1498 }
1499
1500 /*
1501 * Make sure the transfer never exceeds the byte limit of the hardware.
1502 * Further bytes will be sent as continued transactions
1503 */
1504 if (bytes_to_transfer > MAX_TRANSFER_BYTES) {
1505 /* Round MAX_TRANSFER_BYTES to a multiple of out packet size */
1506 bytes_to_transfer = MAX_TRANSFER_BYTES / pipe->max_packet;
1507 bytes_to_transfer *= pipe->max_packet;
1508 }
1509
1510 /*
1511 * Calculate the number of packets to transfer. If the length is zero
1512 * we still need to transfer one packet
1513 */
1514 packets_to_transfer = (bytes_to_transfer + pipe->max_packet - 1) / pipe->max_packet;
1515 if (packets_to_transfer == 0)
1516 packets_to_transfer = 1;
1517 else if ((packets_to_transfer > 1) && (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)) {
1518 /*
1519 * Limit to one packet when not using DMA. Channels must be
1520 * restarted between every packet for IN transactions, so there
1521 * is no reason to do multiple packets in a row
1522 */
1523 packets_to_transfer = 1;
1524 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1525 } else if (packets_to_transfer > MAX_TRANSFER_PACKETS) {
1526 /*
1527 * Limit the number of packet and data transferred to what the
1528 * hardware can handle
1529 */
1530 packets_to_transfer = MAX_TRANSFER_PACKETS;
1531 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1532 }
1533
1534 usbc_hctsiz.s.xfersize = bytes_to_transfer;
1535 usbc_hctsiz.s.pktcnt = packets_to_transfer;
1536
1537 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index), usbc_hctsiz.u32);
1538 return;
1539 }
1540
1541
1542 /**
1543 * Start a channel to perform the pipe's head transaction
1544 *
1545 * @usb: USB device state populated by
1546 * cvmx_usb_initialize().
1547 * @channel: Channel to setup
1548 * @pipe: Pipe to start
1549 */
1550 static void __cvmx_usb_start_channel(struct cvmx_usb_internal_state *usb,
1551 int channel,
1552 struct cvmx_usb_pipe *pipe)
1553 {
1554 struct cvmx_usb_transaction *transaction = pipe->head;
1555
1556 /* Make sure all writes to the DMA region get flushed */
1557 CVMX_SYNCW;
1558
1559 /* Attach the channel to the pipe */
1560 usb->pipe_for_channel[channel] = pipe;
1561 pipe->channel = channel;
1562 pipe->flags |= __CVMX_USB_PIPE_FLAGS_SCHEDULED;
1563
1564 /* Mark this channel as in use */
1565 usb->idle_hardware_channels &= ~(1<<channel);
1566
1567 /* Enable the channel interrupt bits */
1568 {
1569 union cvmx_usbcx_hcintx usbc_hcint;
1570 union cvmx_usbcx_hcintmskx usbc_hcintmsk;
1571 union cvmx_usbcx_haintmsk usbc_haintmsk;
1572
1573 /* Clear all channel status bits */
1574 usbc_hcint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCINTX(channel, usb->index));
1575 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTX(channel, usb->index), usbc_hcint.u32);
1576
1577 usbc_hcintmsk.u32 = 0;
1578 usbc_hcintmsk.s.chhltdmsk = 1;
1579 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) {
1580 /* Channels need these extra interrupts when we aren't in DMA mode */
1581 usbc_hcintmsk.s.datatglerrmsk = 1;
1582 usbc_hcintmsk.s.frmovrunmsk = 1;
1583 usbc_hcintmsk.s.bblerrmsk = 1;
1584 usbc_hcintmsk.s.xacterrmsk = 1;
1585 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1586 /* Splits don't generate xfercompl, so we need ACK and NYET */
1587 usbc_hcintmsk.s.nyetmsk = 1;
1588 usbc_hcintmsk.s.ackmsk = 1;
1589 }
1590 usbc_hcintmsk.s.nakmsk = 1;
1591 usbc_hcintmsk.s.stallmsk = 1;
1592 usbc_hcintmsk.s.xfercomplmsk = 1;
1593 }
1594 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), usbc_hcintmsk.u32);
1595
1596 /* Enable the channel interrupt to propagate */
1597 usbc_haintmsk.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HAINTMSK(usb->index));
1598 usbc_haintmsk.s.haintmsk |= 1<<channel;
1599 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HAINTMSK(usb->index), usbc_haintmsk.u32);
1600 }
1601
1602 /* Setup the locations the DMA engines use */
1603 {
1604 uint64_t dma_address = transaction->buffer + transaction->actual_bytes;
1605 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
1606 dma_address = transaction->buffer + transaction->iso_packets[0].offset + transaction->actual_bytes;
1607 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8, dma_address);
1608 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8, dma_address);
1609 }
1610
1611 /* Setup both the size of the transfer and the SPLIT characteristics */
1612 {
1613 union cvmx_usbcx_hcspltx usbc_hcsplt = {.u32 = 0};
1614 union cvmx_usbcx_hctsizx usbc_hctsiz = {.u32 = 0};
1615 int packets_to_transfer;
1616 int bytes_to_transfer = transaction->buffer_length - transaction->actual_bytes;
1617
1618 /*
1619 * ISOCHRONOUS transactions store each individual transfer size
1620 * in the packet structure, not the global buffer_length
1621 */
1622 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
1623 bytes_to_transfer = transaction->iso_packets[0].length - transaction->actual_bytes;
1624
1625 /*
1626 * We need to do split transactions when we are talking to non
1627 * high speed devices that are behind a high speed hub
1628 */
1629 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1630 /*
1631 * On the start split phase (stage is even) record the
1632 * frame number we will need to send the split complete.
1633 * We only store the lower two bits since the time ahead
1634 * can only be two frames
1635 */
1636 if ((transaction->stage&1) == 0) {
1637 if (transaction->type == CVMX_USB_TRANSFER_BULK)
1638 pipe->split_sc_frame = (usb->frame_number + 1) & 0x7f;
1639 else
1640 pipe->split_sc_frame = (usb->frame_number + 2) & 0x7f;
1641 } else
1642 pipe->split_sc_frame = -1;
1643
1644 usbc_hcsplt.s.spltena = 1;
1645 usbc_hcsplt.s.hubaddr = pipe->hub_device_addr;
1646 usbc_hcsplt.s.prtaddr = pipe->hub_port;
1647 usbc_hcsplt.s.compsplt = (transaction->stage == CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE);
1648
1649 /*
1650 * SPLIT transactions can only ever transmit one data
1651 * packet so limit the transfer size to the max packet
1652 * size
1653 */
1654 if (bytes_to_transfer > pipe->max_packet)
1655 bytes_to_transfer = pipe->max_packet;
1656
1657 /*
1658 * ISOCHRONOUS OUT splits are unique in that they limit
1659 * data transfers to 188 byte chunks representing the
1660 * begin/middle/end of the data or all
1661 */
1662 if (!usbc_hcsplt.s.compsplt &&
1663 (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) &&
1664 (pipe->transfer_type == CVMX_USB_TRANSFER_ISOCHRONOUS)) {
1665 /*
1666 * Clear the split complete frame number as
1667 * there isn't going to be a split complete
1668 */
1669 pipe->split_sc_frame = -1;
1670 /*
1671 * See if we've started this transfer and sent
1672 * data
1673 */
1674 if (transaction->actual_bytes == 0) {
1675 /*
1676 * Nothing sent yet, this is either a
1677 * begin or the entire payload
1678 */
1679 if (bytes_to_transfer <= 188)
1680 usbc_hcsplt.s.xactpos = 3; /* Entire payload in one go */
1681 else
1682 usbc_hcsplt.s.xactpos = 2; /* First part of payload */
1683 } else {
1684 /*
1685 * Continuing the previous data, we must
1686 * either be in the middle or at the end
1687 */
1688 if (bytes_to_transfer <= 188)
1689 usbc_hcsplt.s.xactpos = 1; /* End of payload */
1690 else
1691 usbc_hcsplt.s.xactpos = 0; /* Middle of payload */
1692 }
1693 /*
1694 * Again, the transfer size is limited to 188
1695 * bytes
1696 */
1697 if (bytes_to_transfer > 188)
1698 bytes_to_transfer = 188;
1699 }
1700 }
1701
1702 /*
1703 * Make sure the transfer never exceeds the byte limit of the
1704 * hardware. Further bytes will be sent as continued
1705 * transactions
1706 */
1707 if (bytes_to_transfer > MAX_TRANSFER_BYTES) {
1708 /*
1709 * Round MAX_TRANSFER_BYTES to a multiple of out packet
1710 * size
1711 */
1712 bytes_to_transfer = MAX_TRANSFER_BYTES / pipe->max_packet;
1713 bytes_to_transfer *= pipe->max_packet;
1714 }
1715
1716 /*
1717 * Calculate the number of packets to transfer. If the length is
1718 * zero we still need to transfer one packet
1719 */
1720 packets_to_transfer = (bytes_to_transfer + pipe->max_packet - 1) / pipe->max_packet;
1721 if (packets_to_transfer == 0)
1722 packets_to_transfer = 1;
1723 else if ((packets_to_transfer > 1) && (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)) {
1724 /*
1725 * Limit to one packet when not using DMA. Channels must
1726 * be restarted between every packet for IN
1727 * transactions, so there is no reason to do multiple
1728 * packets in a row
1729 */
1730 packets_to_transfer = 1;
1731 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1732 } else if (packets_to_transfer > MAX_TRANSFER_PACKETS) {
1733 /*
1734 * Limit the number of packet and data transferred to
1735 * what the hardware can handle
1736 */
1737 packets_to_transfer = MAX_TRANSFER_PACKETS;
1738 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1739 }
1740
1741 usbc_hctsiz.s.xfersize = bytes_to_transfer;
1742 usbc_hctsiz.s.pktcnt = packets_to_transfer;
1743
1744 /* Update the DATA0/DATA1 toggle */
1745 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1746 /*
1747 * High speed pipes may need a hardware ping before they start
1748 */
1749 if (pipe->flags & __CVMX_USB_PIPE_FLAGS_NEED_PING)
1750 usbc_hctsiz.s.dopng = 1;
1751
1752 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCSPLTX(channel, usb->index), usbc_hcsplt.u32);
1753 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index), usbc_hctsiz.u32);
1754 }
1755
1756 /* Setup the Host Channel Characteristics Register */
1757 {
1758 union cvmx_usbcx_hccharx usbc_hcchar = {.u32 = 0};
1759
1760 /*
1761 * Set the startframe odd/even properly. This is only used for
1762 * periodic
1763 */
1764 usbc_hcchar.s.oddfrm = usb->frame_number&1;
1765
1766 /*
1767 * Set the number of back to back packets allowed by this
1768 * endpoint. Split transactions interpret "ec" as the number of
1769 * immediate retries of failure. These retries happen too
1770 * quickly, so we disable these entirely for splits
1771 */
1772 if (__cvmx_usb_pipe_needs_split(usb, pipe))
1773 usbc_hcchar.s.ec = 1;
1774 else if (pipe->multi_count < 1)
1775 usbc_hcchar.s.ec = 1;
1776 else if (pipe->multi_count > 3)
1777 usbc_hcchar.s.ec = 3;
1778 else
1779 usbc_hcchar.s.ec = pipe->multi_count;
1780
1781 /* Set the rest of the endpoint specific settings */
1782 usbc_hcchar.s.devaddr = pipe->device_addr;
1783 usbc_hcchar.s.eptype = transaction->type;
1784 usbc_hcchar.s.lspddev = (pipe->device_speed == CVMX_USB_SPEED_LOW);
1785 usbc_hcchar.s.epdir = pipe->transfer_dir;
1786 usbc_hcchar.s.epnum = pipe->endpoint_num;
1787 usbc_hcchar.s.mps = pipe->max_packet;
1788 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index), usbc_hcchar.u32);
1789 }
1790
1791 /* Do transaction type specific fixups as needed */
1792 switch (transaction->type) {
1793 case CVMX_USB_TRANSFER_CONTROL:
1794 __cvmx_usb_start_channel_control(usb, channel, pipe);
1795 break;
1796 case CVMX_USB_TRANSFER_BULK:
1797 case CVMX_USB_TRANSFER_INTERRUPT:
1798 break;
1799 case CVMX_USB_TRANSFER_ISOCHRONOUS:
1800 if (!__cvmx_usb_pipe_needs_split(usb, pipe)) {
1801 /*
1802 * ISO transactions require different PIDs depending on
1803 * direction and how many packets are needed
1804 */
1805 if (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) {
1806 if (pipe->multi_count < 2) /* Need DATA0 */
1807 USB_SET_FIELD32(CVMX_USBCX_HCTSIZX(channel, usb->index), union cvmx_usbcx_hctsizx, pid, 0);
1808 else /* Need MDATA */
1809 USB_SET_FIELD32(CVMX_USBCX_HCTSIZX(channel, usb->index), union cvmx_usbcx_hctsizx, pid, 3);
1810 }
1811 }
1812 break;
1813 }
1814 {
1815 union cvmx_usbcx_hctsizx usbc_hctsiz = {.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index))};
1816 transaction->xfersize = usbc_hctsiz.s.xfersize;
1817 transaction->pktcnt = usbc_hctsiz.s.pktcnt;
1818 }
1819 /* Remeber when we start a split transaction */
1820 if (__cvmx_usb_pipe_needs_split(usb, pipe))
1821 usb->active_split = transaction;
1822 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), union cvmx_usbcx_hccharx, chena, 1);
1823 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
1824 __cvmx_usb_fill_tx_fifo(usb, channel);
1825 return;
1826 }
1827
1828
1829 /**
1830 * Find a pipe that is ready to be scheduled to hardware.
1831 * @usb: USB device state populated by
1832 * cvmx_usb_initialize().
1833 * @list: Pipe list to search
1834 * @current_frame:
1835 * Frame counter to use as a time reference.
1836 *
1837 * Returns: Pipe or NULL if none are ready
1838 */
1839 static struct cvmx_usb_pipe *__cvmx_usb_find_ready_pipe(struct cvmx_usb_internal_state *usb, struct cvmx_usb_pipe_list *list, uint64_t current_frame)
1840 {
1841 struct cvmx_usb_pipe *pipe = list->head;
1842 while (pipe) {
1843 if (!(pipe->flags & __CVMX_USB_PIPE_FLAGS_SCHEDULED) && pipe->head &&
1844 (pipe->next_tx_frame <= current_frame) &&
1845 ((pipe->split_sc_frame == -1) || ((((int)current_frame - (int)pipe->split_sc_frame) & 0x7f) < 0x40)) &&
1846 (!usb->active_split || (usb->active_split == pipe->head))) {
1847 CVMX_PREFETCH(pipe, 128);
1848 CVMX_PREFETCH(pipe->head, 0);
1849 return pipe;
1850 }
1851 pipe = pipe->next;
1852 }
1853 return NULL;
1854 }
1855
1856
1857 /**
1858 * Called whenever a pipe might need to be scheduled to the
1859 * hardware.
1860 *
1861 * @usb: USB device state populated by
1862 * cvmx_usb_initialize().
1863 * @is_sof: True if this schedule was called on a SOF interrupt.
1864 */
1865 static void __cvmx_usb_schedule(struct cvmx_usb_internal_state *usb, int is_sof)
1866 {
1867 int channel;
1868 struct cvmx_usb_pipe *pipe;
1869 int need_sof;
1870 enum cvmx_usb_transfer ttype;
1871
1872 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) {
1873 /* Without DMA we need to be careful to not schedule something at the end of a frame and cause an overrun */
1874 union cvmx_usbcx_hfnum hfnum = {.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index))};
1875 union cvmx_usbcx_hfir hfir = {.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFIR(usb->index))};
1876 if (hfnum.s.frrem < hfir.s.frint/4)
1877 goto done;
1878 }
1879
1880 while (usb->idle_hardware_channels) {
1881 /* Find an idle channel */
1882 channel = __fls(usb->idle_hardware_channels);
1883 if (unlikely(channel > 7))
1884 break;
1885
1886 /* Find a pipe needing service */
1887 pipe = NULL;
1888 if (is_sof) {
1889 /*
1890 * Only process periodic pipes on SOF interrupts. This
1891 * way we are sure that the periodic data is sent in the
1892 * beginning of the frame
1893 */
1894 pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_ISOCHRONOUS, usb->frame_number);
1895 if (likely(!pipe))
1896 pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_INTERRUPT, usb->frame_number);
1897 }
1898 if (likely(!pipe)) {
1899 pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_CONTROL, usb->frame_number);
1900 if (likely(!pipe))
1901 pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_BULK, usb->frame_number);
1902 }
1903 if (!pipe)
1904 break;
1905
1906 __cvmx_usb_start_channel(usb, channel, pipe);
1907 }
1908
1909 done:
1910 /*
1911 * Only enable SOF interrupts when we have transactions pending in the
1912 * future that might need to be scheduled
1913 */
1914 need_sof = 0;
1915 for (ttype = CVMX_USB_TRANSFER_CONTROL; ttype <= CVMX_USB_TRANSFER_INTERRUPT; ttype++) {
1916 pipe = usb->active_pipes[ttype].head;
1917 while (pipe) {
1918 if (pipe->next_tx_frame > usb->frame_number) {
1919 need_sof = 1;
1920 break;
1921 }
1922 pipe = pipe->next;
1923 }
1924 }
1925 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk, sofmsk, need_sof);
1926 return;
1927 }
1928
1929
1930 /**
1931 * Call a user's callback for a specific reason.
1932 *
1933 * @usb: USB device state populated by
1934 * cvmx_usb_initialize().
1935 * @pipe: Pipe the callback is for or NULL
1936 * @transaction:
1937 * Transaction the callback is for or NULL
1938 * @reason: Reason this callback is being called
1939 * @complete_code:
1940 * Completion code for the transaction, if any
1941 */
1942 static void __cvmx_usb_perform_callback(struct cvmx_usb_internal_state *usb,
1943 struct cvmx_usb_pipe *pipe,
1944 struct cvmx_usb_transaction *transaction,
1945 enum cvmx_usb_callback reason,
1946 enum cvmx_usb_complete complete_code)
1947 {
1948 cvmx_usb_callback_func_t callback = usb->callback[reason];
1949 void *user_data = usb->callback_data[reason];
1950 int submit_handle = -1;
1951 int pipe_handle = -1;
1952 int bytes_transferred = 0;
1953
1954 if (pipe)
1955 pipe_handle = __cvmx_usb_get_pipe_handle(usb, pipe);
1956
1957 if (transaction) {
1958 submit_handle = __cvmx_usb_get_submit_handle(usb, transaction);
1959 bytes_transferred = transaction->actual_bytes;
1960 /* Transactions are allowed to override the default callback */
1961 if ((reason == CVMX_USB_CALLBACK_TRANSFER_COMPLETE) && transaction->callback) {
1962 callback = transaction->callback;
1963 user_data = transaction->callback_data;
1964 }
1965 }
1966
1967 if (!callback)
1968 return;
1969
1970 callback((struct cvmx_usb_state *)usb, reason, complete_code, pipe_handle, submit_handle,
1971 bytes_transferred, user_data);
1972 }
1973
1974
1975 /**
1976 * Signal the completion of a transaction and free it. The
1977 * transaction will be removed from the pipe transaction list.
1978 *
1979 * @usb: USB device state populated by
1980 * cvmx_usb_initialize().
1981 * @pipe: Pipe the transaction is on
1982 * @transaction:
1983 * Transaction that completed
1984 * @complete_code:
1985 * Completion code
1986 */
1987 static void __cvmx_usb_perform_complete(struct cvmx_usb_internal_state *usb,
1988 struct cvmx_usb_pipe *pipe,
1989 struct cvmx_usb_transaction *transaction,
1990 enum cvmx_usb_complete complete_code)
1991 {
1992 /* If this was a split then clear our split in progress marker */
1993 if (usb->active_split == transaction)
1994 usb->active_split = NULL;
1995
1996 /*
1997 * Isochronous transactions need extra processing as they might not be
1998 * done after a single data transfer
1999 */
2000 if (unlikely(transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)) {
2001 /* Update the number of bytes transferred in this ISO packet */
2002 transaction->iso_packets[0].length = transaction->actual_bytes;
2003 transaction->iso_packets[0].status = complete_code;
2004
2005 /*
2006 * If there are more ISOs pending and we succeeded, schedule the
2007 * next one
2008 */
2009 if ((transaction->iso_number_packets > 1) && (complete_code == CVMX_USB_COMPLETE_SUCCESS)) {
2010 transaction->actual_bytes = 0; /* No bytes transferred for this packet as of yet */
2011 transaction->iso_number_packets--; /* One less ISO waiting to transfer */
2012 transaction->iso_packets++; /* Increment to the next location in our packet array */
2013 transaction->stage = CVMX_USB_STAGE_NON_CONTROL;
2014 goto done;
2015 }
2016 }
2017
2018 /* Remove the transaction from the pipe list */
2019 if (transaction->next)
2020 transaction->next->prev = transaction->prev;
2021 else
2022 pipe->tail = transaction->prev;
2023 if (transaction->prev)
2024 transaction->prev->next = transaction->next;
2025 else
2026 pipe->head = transaction->next;
2027 if (!pipe->head) {
2028 __cvmx_usb_remove_pipe(usb->active_pipes + pipe->transfer_type, pipe);
2029 __cvmx_usb_append_pipe(&usb->idle_pipes, pipe);
2030
2031 }
2032 __cvmx_usb_perform_callback(usb, pipe, transaction,
2033 CVMX_USB_CALLBACK_TRANSFER_COMPLETE,
2034 complete_code);
2035 __cvmx_usb_free_transaction(usb, transaction);
2036 done:
2037 return;
2038 }
2039
2040
2041 /**
2042 * Submit a usb transaction to a pipe. Called for all types
2043 * of transactions.
2044 *
2045 * @usb:
2046 * @pipe_handle:
2047 * Which pipe to submit to. Will be validated in this function.
2048 * @type: Transaction type
2049 * @buffer: User buffer for the transaction
2050 * @buffer_length:
2051 * User buffer's length in bytes
2052 * @control_header:
2053 * For control transactions, the 8 byte standard header
2054 * @iso_start_frame:
2055 * For ISO transactions, the start frame
2056 * @iso_number_packets:
2057 * For ISO, the number of packet in the transaction.
2058 * @iso_packets:
2059 * A description of each ISO packet
2060 * @callback: User callback to call when the transaction completes
2061 * @user_data: User's data for the callback
2062 *
2063 * Returns: Submit handle or negative on failure. Matches the result
2064 * in the external API.
2065 */
2066 static int __cvmx_usb_submit_transaction(struct cvmx_usb_internal_state *usb,
2067 int pipe_handle,
2068 enum cvmx_usb_transfer type,
2069 uint64_t buffer,
2070 int buffer_length,
2071 uint64_t control_header,
2072 int iso_start_frame,
2073 int iso_number_packets,
2074 struct cvmx_usb_iso_packet *iso_packets,
2075 cvmx_usb_callback_func_t callback,
2076 void *user_data)
2077 {
2078 int submit_handle;
2079 struct cvmx_usb_transaction *transaction;
2080 struct cvmx_usb_pipe *pipe = usb->pipe + pipe_handle;
2081
2082 if (unlikely((pipe_handle < 0) || (pipe_handle >= MAX_PIPES)))
2083 return -EINVAL;
2084 /* Fail if the pipe isn't open */
2085 if (unlikely((pipe->flags & __CVMX_USB_PIPE_FLAGS_OPEN) == 0))
2086 return -EINVAL;
2087 if (unlikely(pipe->transfer_type != type))
2088 return -EINVAL;
2089
2090 transaction = __cvmx_usb_alloc_transaction(usb);
2091 if (unlikely(!transaction))
2092 return -ENOMEM;
2093
2094 transaction->type = type;
2095 transaction->buffer = buffer;
2096 transaction->buffer_length = buffer_length;
2097 transaction->control_header = control_header;
2098 transaction->iso_start_frame = iso_start_frame; // FIXME: This is not used, implement it
2099 transaction->iso_number_packets = iso_number_packets;
2100 transaction->iso_packets = iso_packets;
2101 transaction->callback = callback;
2102 transaction->callback_data = user_data;
2103 if (transaction->type == CVMX_USB_TRANSFER_CONTROL)
2104 transaction->stage = CVMX_USB_STAGE_SETUP;
2105 else
2106 transaction->stage = CVMX_USB_STAGE_NON_CONTROL;
2107
2108 transaction->next = NULL;
2109 if (pipe->tail) {
2110 transaction->prev = pipe->tail;
2111 transaction->prev->next = transaction;
2112 } else {
2113 if (pipe->next_tx_frame < usb->frame_number)
2114 pipe->next_tx_frame = usb->frame_number + pipe->interval -
2115 (usb->frame_number - pipe->next_tx_frame) % pipe->interval;
2116 transaction->prev = NULL;
2117 pipe->head = transaction;
2118 __cvmx_usb_remove_pipe(&usb->idle_pipes, pipe);
2119 __cvmx_usb_append_pipe(usb->active_pipes + pipe->transfer_type, pipe);
2120 }
2121 pipe->tail = transaction;
2122
2123 submit_handle = __cvmx_usb_get_submit_handle(usb, transaction);
2124
2125 /* We may need to schedule the pipe if this was the head of the pipe */
2126 if (!transaction->prev)
2127 __cvmx_usb_schedule(usb, 0);
2128
2129 return submit_handle;
2130 }
2131
2132
2133 /**
2134 * Call to submit a USB Bulk transfer to a pipe.
2135 *
2136 * @state: USB device state populated by
2137 * cvmx_usb_initialize().
2138 * @pipe_handle:
2139 * Handle to the pipe for the transfer.
2140 * @buffer: Physical address of the data buffer in
2141 * memory. Note that this is NOT A POINTER, but
2142 * the full 64bit physical address of the
2143 * buffer. This may be zero if buffer_length is
2144 * zero.
2145 * @buffer_length:
2146 * Length of buffer in bytes.
2147 * @callback: Function to call when this transaction
2148 * completes. If the return value of this
2149 * function isn't an error, then this function
2150 * is guaranteed to be called when the
2151 * transaction completes. If this parameter is
2152 * NULL, then the generic callback registered
2153 * through cvmx_usb_register_callback is
2154 * called. If both are NULL, then there is no
2155 * way to know when a transaction completes.
2156 * @user_data: User supplied data returned when the
2157 * callback is called. This is only used if
2158 * callback in not NULL.
2159 *
2160 * Returns: A submitted transaction handle or negative on
2161 * failure. Negative values are error codes.
2162 */
2163 int cvmx_usb_submit_bulk(struct cvmx_usb_state *state, int pipe_handle,
2164 uint64_t buffer, int buffer_length,
2165 cvmx_usb_callback_func_t callback,
2166 void *user_data)
2167 {
2168 int submit_handle;
2169 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
2170
2171 /* Pipe handle checking is done later in a common place */
2172 if (unlikely(!buffer))
2173 return -EINVAL;
2174 if (unlikely(buffer_length < 0))
2175 return -EINVAL;
2176
2177 submit_handle = __cvmx_usb_submit_transaction(usb, pipe_handle,
2178 CVMX_USB_TRANSFER_BULK,
2179 buffer,
2180 buffer_length,
2181 0, /* control_header */
2182 0, /* iso_start_frame */
2183 0, /* iso_number_packets */
2184 NULL, /* iso_packets */
2185 callback,
2186 user_data);
2187 return submit_handle;
2188 }
2189
2190
2191 /**
2192 * Call to submit a USB Interrupt transfer to a pipe.
2193 *
2194 * @state: USB device state populated by
2195 * cvmx_usb_initialize().
2196 * @pipe_handle:
2197 * Handle to the pipe for the transfer.
2198 * @buffer: Physical address of the data buffer in
2199 * memory. Note that this is NOT A POINTER, but
2200 * the full 64bit physical address of the
2201 * buffer. This may be zero if buffer_length is
2202 * zero.
2203 * @buffer_length:
2204 * Length of buffer in bytes.
2205 * @callback: Function to call when this transaction
2206 * completes. If the return value of this
2207 * function isn't an error, then this function
2208 * is guaranteed to be called when the
2209 * transaction completes. If this parameter is
2210 * NULL, then the generic callback registered
2211 * through cvmx_usb_register_callback is
2212 * called. If both are NULL, then there is no
2213 * way to know when a transaction completes.
2214 * @user_data: User supplied data returned when the
2215 * callback is called. This is only used if
2216 * callback in not NULL.
2217 *
2218 * Returns: A submitted transaction handle or negative on
2219 * failure. Negative values are error codes.
2220 */
2221 int cvmx_usb_submit_interrupt(struct cvmx_usb_state *state, int pipe_handle,
2222 uint64_t buffer, int buffer_length,
2223 cvmx_usb_callback_func_t callback,
2224 void *user_data)
2225 {
2226 int submit_handle;
2227 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
2228
2229 /* Pipe handle checking is done later in a common place */
2230 if (unlikely(!buffer))
2231 return -EINVAL;
2232 if (unlikely(buffer_length < 0))
2233 return -EINVAL;
2234
2235 submit_handle = __cvmx_usb_submit_transaction(usb, pipe_handle,
2236 CVMX_USB_TRANSFER_INTERRUPT,
2237 buffer,
2238 buffer_length,
2239 0, /* control_header */
2240 0, /* iso_start_frame */
2241 0, /* iso_number_packets */
2242 NULL, /* iso_packets */
2243 callback,
2244 user_data);
2245 return submit_handle;
2246 }
2247
2248
2249 /**
2250 * Call to submit a USB Control transfer to a pipe.
2251 *
2252 * @state: USB device state populated by
2253 * cvmx_usb_initialize().
2254 * @pipe_handle:
2255 * Handle to the pipe for the transfer.
2256 * @control_header:
2257 * USB 8 byte control header physical address.
2258 * Note that this is NOT A POINTER, but the
2259 * full 64bit physical address of the buffer.
2260 * @buffer: Physical address of the data buffer in
2261 * memory. Note that this is NOT A POINTER, but
2262 * the full 64bit physical address of the
2263 * buffer. This may be zero if buffer_length is
2264 * zero.
2265 * @buffer_length:
2266 * Length of buffer in bytes.
2267 * @callback: Function to call when this transaction
2268 * completes. If the return value of this
2269 * function isn't an error, then this function
2270 * is guaranteed to be called when the
2271 * transaction completes. If this parameter is
2272 * NULL, then the generic callback registered
2273 * through cvmx_usb_register_callback is
2274 * called. If both are NULL, then there is no
2275 * way to know when a transaction completes.
2276 * @user_data: User supplied data returned when the
2277 * callback is called. This is only used if
2278 * callback in not NULL.
2279 *
2280 * Returns: A submitted transaction handle or negative on
2281 * failure. Negative values are error codes.
2282 */
2283 int cvmx_usb_submit_control(struct cvmx_usb_state *state, int pipe_handle,
2284 uint64_t control_header,
2285 uint64_t buffer, int buffer_length,
2286 cvmx_usb_callback_func_t callback,
2287 void *user_data)
2288 {
2289 int submit_handle;
2290 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
2291 union cvmx_usb_control_header *header =
2292 cvmx_phys_to_ptr(control_header);
2293
2294 /* Pipe handle checking is done later in a common place */
2295 if (unlikely(!control_header))
2296 return -EINVAL;
2297 /* Some drivers send a buffer with a zero length. God only knows why */
2298 if (unlikely(buffer && (buffer_length < 0)))
2299 return -EINVAL;
2300 if (unlikely(!buffer && (buffer_length != 0)))
2301 return -EINVAL;
2302 if ((header->s.request_type & 0x80) == 0)
2303 buffer_length = le16_to_cpu(header->s.length);
2304
2305 submit_handle = __cvmx_usb_submit_transaction(usb, pipe_handle,
2306 CVMX_USB_TRANSFER_CONTROL,
2307 buffer,
2308 buffer_length,
2309 control_header,
2310 0, /* iso_start_frame */
2311 0, /* iso_number_packets */
2312 NULL, /* iso_packets */
2313 callback,
2314 user_data);
2315 return submit_handle;
2316 }
2317
2318
2319 /**
2320 * Call to submit a USB Isochronous transfer to a pipe.
2321 *
2322 * @state: USB device state populated by
2323 * cvmx_usb_initialize().
2324 * @pipe_handle:
2325 * Handle to the pipe for the transfer.
2326 * @start_frame:
2327 * Number of frames into the future to schedule
2328 * this transaction.
2329 * @number_packets:
2330 * Number of sequential packets to transfer.
2331 * "packets" is a pointer to an array of this
2332 * many packet structures.
2333 * @packets: Description of each transfer packet as
2334 * defined by struct cvmx_usb_iso_packet. The array
2335 * pointed to here must stay valid until the
2336 * complete callback is called.
2337 * @buffer: Physical address of the data buffer in
2338 * memory. Note that this is NOT A POINTER, but
2339 * the full 64bit physical address of the
2340 * buffer. This may be zero if buffer_length is
2341 * zero.
2342 * @buffer_length:
2343 * Length of buffer in bytes.
2344 * @callback: Function to call when this transaction
2345 * completes. If the return value of this
2346 * function isn't an error, then this function
2347 * is guaranteed to be called when the
2348 * transaction completes. If this parameter is
2349 * NULL, then the generic callback registered
2350 * through cvmx_usb_register_callback is
2351 * called. If both are NULL, then there is no
2352 * way to know when a transaction completes.
2353 * @user_data: User supplied data returned when the
2354 * callback is called. This is only used if
2355 * callback in not NULL.
2356 *
2357 * Returns: A submitted transaction handle or negative on
2358 * failure. Negative values are error codes.
2359 */
2360 int cvmx_usb_submit_isochronous(struct cvmx_usb_state *state, int pipe_handle,
2361 int start_frame,
2362 int number_packets,
2363 struct cvmx_usb_iso_packet packets[],
2364 uint64_t buffer, int buffer_length,
2365 cvmx_usb_callback_func_t callback,
2366 void *user_data)
2367 {
2368 int submit_handle;
2369 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
2370
2371 /* Pipe handle checking is done later in a common place */
2372 if (unlikely(start_frame < 0))
2373 return -EINVAL;
2374 if (unlikely(number_packets < 1))
2375 return -EINVAL;
2376 if (unlikely(!packets))
2377 return -EINVAL;
2378 if (unlikely(!buffer))
2379 return -EINVAL;
2380 if (unlikely(buffer_length < 0))
2381 return -EINVAL;
2382
2383 submit_handle = __cvmx_usb_submit_transaction(usb, pipe_handle,
2384 CVMX_USB_TRANSFER_ISOCHRONOUS,
2385 buffer,
2386 buffer_length,
2387 0, /* control_header */
2388 start_frame,
2389 number_packets,
2390 packets,
2391 callback,
2392 user_data);
2393 return submit_handle;
2394 }
2395
2396
2397 /**
2398 * Cancel one outstanding request in a pipe. Canceling a request
2399 * can fail if the transaction has already completed before cancel
2400 * is called. Even after a successful cancel call, it may take
2401 * a frame or two for the cvmx_usb_poll() function to call the
2402 * associated callback.
2403 *
2404 * @state: USB device state populated by
2405 * cvmx_usb_initialize().
2406 * @pipe_handle:
2407 * Pipe handle to cancel requests in.
2408 * @submit_handle:
2409 * Handle to transaction to cancel, returned by the submit function.
2410 *
2411 * Returns: 0 or a negative error code.
2412 */
2413 int cvmx_usb_cancel(struct cvmx_usb_state *state, int pipe_handle, int submit_handle)
2414 {
2415 struct cvmx_usb_transaction *transaction;
2416 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
2417 struct cvmx_usb_pipe *pipe = usb->pipe + pipe_handle;
2418
2419 if (unlikely((pipe_handle < 0) || (pipe_handle >= MAX_PIPES)))
2420 return -EINVAL;
2421 if (unlikely((submit_handle < 0) || (submit_handle >= MAX_TRANSACTIONS)))
2422 return -EINVAL;
2423
2424 /* Fail if the pipe isn't open */
2425 if (unlikely((pipe->flags & __CVMX_USB_PIPE_FLAGS_OPEN) == 0))
2426 return -EINVAL;
2427
2428 transaction = usb->transaction + submit_handle;
2429
2430 /* Fail if this transaction already completed */
2431 if (unlikely((transaction->flags & __CVMX_USB_TRANSACTION_FLAGS_IN_USE) == 0))
2432 return -EINVAL;
2433
2434 /*
2435 * If the transaction is the HEAD of the queue and scheduled. We need to
2436 * treat it special
2437 */
2438 if ((pipe->head == transaction) &&
2439 (pipe->flags & __CVMX_USB_PIPE_FLAGS_SCHEDULED)) {
2440 union cvmx_usbcx_hccharx usbc_hcchar;
2441
2442 usb->pipe_for_channel[pipe->channel] = NULL;
2443 pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_SCHEDULED;
2444
2445 CVMX_SYNCW;
2446
2447 usbc_hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(pipe->channel, usb->index));
2448 /* If the channel isn't enabled then the transaction already completed */
2449 if (usbc_hcchar.s.chena) {
2450 usbc_hcchar.s.chdis = 1;
2451 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(pipe->channel, usb->index), usbc_hcchar.u32);
2452 }
2453 }
2454 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_CANCEL);
2455 return 0;
2456 }
2457
2458
2459 /**
2460 * Cancel all outstanding requests in a pipe. Logically all this
2461 * does is call cvmx_usb_cancel() in a loop.
2462 *
2463 * @state: USB device state populated by
2464 * cvmx_usb_initialize().
2465 * @pipe_handle:
2466 * Pipe handle to cancel requests in.
2467 *
2468 * Returns: 0 or a negative error code.
2469 */
2470 int cvmx_usb_cancel_all(struct cvmx_usb_state *state, int pipe_handle)
2471 {
2472 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
2473 struct cvmx_usb_pipe *pipe = usb->pipe + pipe_handle;
2474
2475 if (unlikely((pipe_handle < 0) || (pipe_handle >= MAX_PIPES)))
2476 return -EINVAL;
2477
2478 /* Fail if the pipe isn't open */
2479 if (unlikely((pipe->flags & __CVMX_USB_PIPE_FLAGS_OPEN) == 0))
2480 return -EINVAL;
2481
2482 /* Simply loop through and attempt to cancel each transaction */
2483 while (pipe->head) {
2484 int result = cvmx_usb_cancel(state, pipe_handle,
2485 __cvmx_usb_get_submit_handle(usb, pipe->head));
2486 if (unlikely(result != 0))
2487 return result;
2488 }
2489 return 0;
2490 }
2491
2492
2493 /**
2494 * Close a pipe created with cvmx_usb_open_pipe().
2495 *
2496 * @state: USB device state populated by
2497 * cvmx_usb_initialize().
2498 * @pipe_handle:
2499 * Pipe handle to close.
2500 *
2501 * Returns: 0 or a negative error code. EBUSY is returned if the pipe has
2502 * outstanding transfers.
2503 */
2504 int cvmx_usb_close_pipe(struct cvmx_usb_state *state, int pipe_handle)
2505 {
2506 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
2507 struct cvmx_usb_pipe *pipe = usb->pipe + pipe_handle;
2508
2509 if (unlikely((pipe_handle < 0) || (pipe_handle >= MAX_PIPES)))
2510 return -EINVAL;
2511
2512 /* Fail if the pipe isn't open */
2513 if (unlikely((pipe->flags & __CVMX_USB_PIPE_FLAGS_OPEN) == 0))
2514 return -EINVAL;
2515
2516 /* Fail if the pipe has pending transactions */
2517 if (unlikely(pipe->head))
2518 return -EBUSY;
2519
2520 pipe->flags = 0;
2521 __cvmx_usb_remove_pipe(&usb->idle_pipes, pipe);
2522 __cvmx_usb_append_pipe(&usb->free_pipes, pipe);
2523
2524 return 0;
2525 }
2526
2527
2528 /**
2529 * Register a function to be called when various USB events occur.
2530 *
2531 * @state: USB device state populated by
2532 * cvmx_usb_initialize().
2533 * @reason: Which event to register for.
2534 * @callback: Function to call when the event occurs.
2535 * @user_data: User data parameter to the function.
2536 *
2537 * Returns: 0 or a negative error code.
2538 */
2539 int cvmx_usb_register_callback(struct cvmx_usb_state *state,
2540 enum cvmx_usb_callback reason,
2541 cvmx_usb_callback_func_t callback,
2542 void *user_data)
2543 {
2544 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
2545
2546 if (unlikely(reason >= __CVMX_USB_CALLBACK_END))
2547 return -EINVAL;
2548 if (unlikely(!callback))
2549 return -EINVAL;
2550
2551 usb->callback[reason] = callback;
2552 usb->callback_data[reason] = user_data;
2553
2554 return 0;
2555 }
2556
2557
2558 /**
2559 * Get the current USB protocol level frame number. The frame
2560 * number is always in the range of 0-0x7ff.
2561 *
2562 * @state: USB device state populated by
2563 * cvmx_usb_initialize().
2564 *
2565 * Returns: USB frame number
2566 */
2567 int cvmx_usb_get_frame_number(struct cvmx_usb_state *state)
2568 {
2569 int frame_number;
2570 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
2571 union cvmx_usbcx_hfnum usbc_hfnum;
2572
2573 usbc_hfnum.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index));
2574 frame_number = usbc_hfnum.s.frnum;
2575
2576 return frame_number;
2577 }
2578
2579
2580 /**
2581 * Poll a channel for status
2582 *
2583 * @usb: USB device
2584 * @channel: Channel to poll
2585 *
2586 * Returns: Zero on success
2587 */
2588 static int __cvmx_usb_poll_channel(struct cvmx_usb_internal_state *usb, int channel)
2589 {
2590 union cvmx_usbcx_hcintx usbc_hcint;
2591 union cvmx_usbcx_hctsizx usbc_hctsiz;
2592 union cvmx_usbcx_hccharx usbc_hcchar;
2593 struct cvmx_usb_pipe *pipe;
2594 struct cvmx_usb_transaction *transaction;
2595 int bytes_this_transfer;
2596 int bytes_in_last_packet;
2597 int packets_processed;
2598 int buffer_space_left;
2599
2600 /* Read the interrupt status bits for the channel */
2601 usbc_hcint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCINTX(channel, usb->index));
2602
2603 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) {
2604 usbc_hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index));
2605
2606 if (usbc_hcchar.s.chena && usbc_hcchar.s.chdis) {
2607 /*
2608 * There seems to be a bug in CN31XX which can cause
2609 * interrupt IN transfers to get stuck until we do a
2610 * write of HCCHARX without changing things
2611 */
2612 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index), usbc_hcchar.u32);
2613 return 0;
2614 }
2615
2616 /*
2617 * In non DMA mode the channels don't halt themselves. We need
2618 * to manually disable channels that are left running
2619 */
2620 if (!usbc_hcint.s.chhltd) {
2621 if (usbc_hcchar.s.chena) {
2622 union cvmx_usbcx_hcintmskx hcintmsk;
2623 /* Disable all interrupts except CHHLTD */
2624 hcintmsk.u32 = 0;
2625 hcintmsk.s.chhltdmsk = 1;
2626 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), hcintmsk.u32);
2627 usbc_hcchar.s.chdis = 1;
2628 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index), usbc_hcchar.u32);
2629 return 0;
2630 } else if (usbc_hcint.s.xfercompl) {
2631 /* Successful IN/OUT with transfer complete. Channel halt isn't needed */
2632 } else {
2633 cvmx_dprintf("USB%d: Channel %d interrupt without halt\n", usb->index, channel);
2634 return 0;
2635 }
2636 }
2637 } else {
2638 /*
2639 * There is are no interrupts that we need to process when the
2640 * channel is still running
2641 */
2642 if (!usbc_hcint.s.chhltd)
2643 return 0;
2644 }
2645
2646 /* Disable the channel interrupts now that it is done */
2647 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), 0);
2648 usb->idle_hardware_channels |= (1<<channel);
2649
2650 /* Make sure this channel is tied to a valid pipe */
2651 pipe = usb->pipe_for_channel[channel];
2652 CVMX_PREFETCH(pipe, 0);
2653 CVMX_PREFETCH(pipe, 128);
2654 if (!pipe)
2655 return 0;
2656 transaction = pipe->head;
2657 CVMX_PREFETCH(transaction, 0);
2658
2659 /*
2660 * Disconnect this pipe from the HW channel. Later the schedule
2661 * function will figure out which pipe needs to go
2662 */
2663 usb->pipe_for_channel[channel] = NULL;
2664 pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_SCHEDULED;
2665
2666 /*
2667 * Read the channel config info so we can figure out how much data
2668 * transfered
2669 */
2670 usbc_hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index));
2671 usbc_hctsiz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index));
2672
2673 /*
2674 * Calculating the number of bytes successfully transferred is dependent
2675 * on the transfer direction
2676 */
2677 packets_processed = transaction->pktcnt - usbc_hctsiz.s.pktcnt;
2678 if (usbc_hcchar.s.epdir) {
2679 /*
2680 * IN transactions are easy. For every byte received the
2681 * hardware decrements xfersize. All we need to do is subtract
2682 * the current value of xfersize from its starting value and we
2683 * know how many bytes were written to the buffer
2684 */
2685 bytes_this_transfer = transaction->xfersize - usbc_hctsiz.s.xfersize;
2686 } else {
2687 /*
2688 * OUT transaction don't decrement xfersize. Instead pktcnt is
2689 * decremented on every successful packet send. The hardware
2690 * does this when it receives an ACK, or NYET. If it doesn't
2691 * receive one of these responses pktcnt doesn't change
2692 */
2693 bytes_this_transfer = packets_processed * usbc_hcchar.s.mps;
2694 /*
2695 * The last packet may not be a full transfer if we didn't have
2696 * enough data
2697 */
2698 if (bytes_this_transfer > transaction->xfersize)
2699 bytes_this_transfer = transaction->xfersize;
2700 }
2701 /* Figure out how many bytes were in the last packet of the transfer */
2702 if (packets_processed)
2703 bytes_in_last_packet = bytes_this_transfer - (packets_processed-1) * usbc_hcchar.s.mps;
2704 else
2705 bytes_in_last_packet = bytes_this_transfer;
2706
2707 /*
2708 * As a special case, setup transactions output the setup header, not
2709 * the user's data. For this reason we don't count setup data as bytes
2710 * transferred
2711 */
2712 if ((transaction->stage == CVMX_USB_STAGE_SETUP) ||
2713 (transaction->stage == CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE))
2714 bytes_this_transfer = 0;
2715
2716 /*
2717 * Add the bytes transferred to the running total. It is important that
2718 * bytes_this_transfer doesn't count any data that needs to be
2719 * retransmitted
2720 */
2721 transaction->actual_bytes += bytes_this_transfer;
2722 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
2723 buffer_space_left = transaction->iso_packets[0].length - transaction->actual_bytes;
2724 else
2725 buffer_space_left = transaction->buffer_length - transaction->actual_bytes;
2726
2727 /*
2728 * We need to remember the PID toggle state for the next transaction.
2729 * The hardware already updated it for the next transaction
2730 */
2731 pipe->pid_toggle = !(usbc_hctsiz.s.pid == 0);
2732
2733 /*
2734 * For high speed bulk out, assume the next transaction will need to do
2735 * a ping before proceeding. If this isn't true the ACK processing below
2736 * will clear this flag
2737 */
2738 if ((pipe->device_speed == CVMX_USB_SPEED_HIGH) &&
2739 (pipe->transfer_type == CVMX_USB_TRANSFER_BULK) &&
2740 (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT))
2741 pipe->flags |= __CVMX_USB_PIPE_FLAGS_NEED_PING;
2742
2743 if (usbc_hcint.s.stall) {
2744 /*
2745 * STALL as a response means this transaction cannot be
2746 * completed because the device can't process transactions. Tell
2747 * the user. Any data that was transferred will be counted on
2748 * the actual bytes transferred
2749 */
2750 pipe->pid_toggle = 0;
2751 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_STALL);
2752 } else if (usbc_hcint.s.xacterr) {
2753 /*
2754 * We know at least one packet worked if we get a ACK or NAK.
2755 * Reset the retry counter
2756 */
2757 if (usbc_hcint.s.nak || usbc_hcint.s.ack)
2758 transaction->retries = 0;
2759 transaction->retries++;
2760 if (transaction->retries > MAX_RETRIES) {
2761 /*
2762 * XactErr as a response means the device signaled
2763 * something wrong with the transfer. For example, PID
2764 * toggle errors cause these
2765 */
2766 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_XACTERR);
2767 } else {
2768 /*
2769 * If this was a split then clear our split in progress
2770 * marker
2771 */
2772 if (usb->active_split == transaction)
2773 usb->active_split = NULL;
2774 /*
2775 * Rewind to the beginning of the transaction by anding
2776 * off the split complete bit
2777 */
2778 transaction->stage &= ~1;
2779 pipe->split_sc_frame = -1;
2780 pipe->next_tx_frame += pipe->interval;
2781 if (pipe->next_tx_frame < usb->frame_number)
2782 pipe->next_tx_frame = usb->frame_number + pipe->interval -
2783 (usb->frame_number - pipe->next_tx_frame) % pipe->interval;
2784 }
2785 } else if (usbc_hcint.s.bblerr) {
2786 /* Babble Error (BblErr) */
2787 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_BABBLEERR);
2788 } else if (usbc_hcint.s.datatglerr) {
2789 /* We'll retry the exact same transaction again */
2790 transaction->retries++;
2791 } else if (usbc_hcint.s.nyet) {
2792 /*
2793 * NYET as a response is only allowed in three cases: as a
2794 * response to a ping, as a response to a split transaction, and
2795 * as a response to a bulk out. The ping case is handled by
2796 * hardware, so we only have splits and bulk out
2797 */
2798 if (!__cvmx_usb_pipe_needs_split(usb, pipe)) {
2799 transaction->retries = 0;
2800 /*
2801 * If there is more data to go then we need to try
2802 * again. Otherwise this transaction is complete
2803 */
2804 if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet))
2805 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2806 } else {
2807 /*
2808 * Split transactions retry the split complete 4 times
2809 * then rewind to the start split and do the entire
2810 * transactions again
2811 */
2812 transaction->retries++;
2813 if ((transaction->retries & 0x3) == 0) {
2814 /*
2815 * Rewind to the beginning of the transaction by
2816 * anding off the split complete bit
2817 */
2818 transaction->stage &= ~1;
2819 pipe->split_sc_frame = -1;
2820 }
2821 }
2822 } else if (usbc_hcint.s.ack) {
2823 transaction->retries = 0;
2824 /*
2825 * The ACK bit can only be checked after the other error bits.
2826 * This is because a multi packet transfer may succeed in a
2827 * number of packets and then get a different response on the
2828 * last packet. In this case both ACK and the last response bit
2829 * will be set. If none of the other response bits is set, then
2830 * the last packet must have been an ACK
2831 *
2832 * Since we got an ACK, we know we don't need to do a ping on
2833 * this pipe
2834 */
2835 pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_NEED_PING;
2836
2837 switch (transaction->type) {
2838 case CVMX_USB_TRANSFER_CONTROL:
2839 switch (transaction->stage) {
2840 case CVMX_USB_STAGE_NON_CONTROL:
2841 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE:
2842 /* This should be impossible */
2843 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_ERROR);
2844 break;
2845 case CVMX_USB_STAGE_SETUP:
2846 pipe->pid_toggle = 1;
2847 if (__cvmx_usb_pipe_needs_split(usb, pipe))
2848 transaction->stage = CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE;
2849 else {
2850 union cvmx_usb_control_header *header =
2851 cvmx_phys_to_ptr(transaction->control_header);
2852 if (header->s.length)
2853 transaction->stage = CVMX_USB_STAGE_DATA;
2854 else
2855 transaction->stage = CVMX_USB_STAGE_STATUS;
2856 }
2857 break;
2858 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE:
2859 {
2860 union cvmx_usb_control_header *header =
2861 cvmx_phys_to_ptr(transaction->control_header);
2862 if (header->s.length)
2863 transaction->stage = CVMX_USB_STAGE_DATA;
2864 else
2865 transaction->stage = CVMX_USB_STAGE_STATUS;
2866 }
2867 break;
2868 case CVMX_USB_STAGE_DATA:
2869 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
2870 transaction->stage = CVMX_USB_STAGE_DATA_SPLIT_COMPLETE;
2871 /*
2872 * For setup OUT data that are splits,
2873 * the hardware doesn't appear to count
2874 * transferred data. Here we manually
2875 * update the data transferred
2876 */
2877 if (!usbc_hcchar.s.epdir) {
2878 if (buffer_space_left < pipe->max_packet)
2879 transaction->actual_bytes += buffer_space_left;
2880 else
2881 transaction->actual_bytes += pipe->max_packet;
2882 }
2883 } else if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet)) {
2884 pipe->pid_toggle = 1;
2885 transaction->stage = CVMX_USB_STAGE_STATUS;
2886 }
2887 break;
2888 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE:
2889 if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet)) {
2890 pipe->pid_toggle = 1;
2891 transaction->stage = CVMX_USB_STAGE_STATUS;
2892 } else {
2893 transaction->stage = CVMX_USB_STAGE_DATA;
2894 }
2895 break;
2896 case CVMX_USB_STAGE_STATUS:
2897 if (__cvmx_usb_pipe_needs_split(usb, pipe))
2898 transaction->stage = CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE;
2899 else
2900 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2901 break;
2902 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE:
2903 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2904 break;
2905 }
2906 break;
2907 case CVMX_USB_TRANSFER_BULK:
2908 case CVMX_USB_TRANSFER_INTERRUPT:
2909 /*
2910 * The only time a bulk transfer isn't complete when it
2911 * finishes with an ACK is during a split transaction.
2912 * For splits we need to continue the transfer if more
2913 * data is needed
2914 */
2915 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
2916 if (transaction->stage == CVMX_USB_STAGE_NON_CONTROL)
2917 transaction->stage = CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE;
2918 else {
2919 if (buffer_space_left && (bytes_in_last_packet == pipe->max_packet))
2920 transaction->stage = CVMX_USB_STAGE_NON_CONTROL;
2921 else {
2922 if (transaction->type == CVMX_USB_TRANSFER_INTERRUPT)
2923 pipe->next_tx_frame += pipe->interval;
2924 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2925 }
2926 }
2927 } else {
2928 if ((pipe->device_speed == CVMX_USB_SPEED_HIGH) &&
2929 (pipe->transfer_type == CVMX_USB_TRANSFER_BULK) &&
2930 (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) &&
2931 (usbc_hcint.s.nak))
2932 pipe->flags |= __CVMX_USB_PIPE_FLAGS_NEED_PING;
2933 if (!buffer_space_left || (bytes_in_last_packet < pipe->max_packet)) {
2934 if (transaction->type == CVMX_USB_TRANSFER_INTERRUPT)
2935 pipe->next_tx_frame += pipe->interval;
2936 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2937 }
2938 }
2939 break;
2940 case CVMX_USB_TRANSFER_ISOCHRONOUS:
2941 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
2942 /*
2943 * ISOCHRONOUS OUT splits don't require a
2944 * complete split stage. Instead they use a
2945 * sequence of begin OUT splits to transfer the
2946 * data 188 bytes at a time. Once the transfer
2947 * is complete, the pipe sleeps until the next
2948 * schedule interval
2949 */
2950 if (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) {
2951 /*
2952 * If no space left or this wasn't a max
2953 * size packet then this transfer is
2954 * complete. Otherwise start it again to
2955 * send the next 188 bytes
2956 */
2957 if (!buffer_space_left || (bytes_this_transfer < 188)) {
2958 pipe->next_tx_frame += pipe->interval;
2959 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2960 }
2961 } else {
2962 if (transaction->stage == CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE) {
2963 /*
2964 * We are in the incoming data
2965 * phase. Keep getting data
2966 * until we run out of space or
2967 * get a small packet
2968 */
2969 if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet)) {
2970 pipe->next_tx_frame += pipe->interval;
2971 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2972 }
2973 } else
2974 transaction->stage = CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE;
2975 }
2976 } else {
2977 pipe->next_tx_frame += pipe->interval;
2978 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2979 }
2980 break;
2981 }
2982 } else if (usbc_hcint.s.nak) {
2983 /* If this was a split then clear our split in progress marker */
2984 if (usb->active_split == transaction)
2985 usb->active_split = NULL;
2986 /*
2987 * NAK as a response means the device couldn't accept the
2988 * transaction, but it should be retried in the future. Rewind
2989 * to the beginning of the transaction by anding off the split
2990 * complete bit. Retry in the next interval
2991 */
2992 transaction->retries = 0;
2993 transaction->stage &= ~1;
2994 pipe->next_tx_frame += pipe->interval;
2995 if (pipe->next_tx_frame < usb->frame_number)
2996 pipe->next_tx_frame = usb->frame_number + pipe->interval -
2997 (usb->frame_number - pipe->next_tx_frame) % pipe->interval;
2998 } else {
2999 struct cvmx_usb_port_status port;
3000 port = cvmx_usb_get_status((struct cvmx_usb_state *)usb);
3001 if (port.port_enabled) {
3002 /* We'll retry the exact same transaction again */
3003 transaction->retries++;
3004 } else {
3005 /*
3006 * We get channel halted interrupts with no result bits
3007 * sets when the cable is unplugged
3008 */
3009 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_ERROR);
3010 }
3011 }
3012 return 0;
3013 }
3014
3015
3016 /**
3017 * Poll the USB block for status and call all needed callback
3018 * handlers. This function is meant to be called in the interrupt
3019 * handler for the USB controller. It can also be called
3020 * periodically in a loop for non-interrupt based operation.
3021 *
3022 * @state: USB device state populated by
3023 * cvmx_usb_initialize().
3024 *
3025 * Returns: 0 or a negative error code.
3026 */
3027 int cvmx_usb_poll(struct cvmx_usb_state *state)
3028 {
3029 union cvmx_usbcx_hfnum usbc_hfnum;
3030 union cvmx_usbcx_gintsts usbc_gintsts;
3031 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
3032
3033 CVMX_PREFETCH(usb, 0);
3034 CVMX_PREFETCH(usb, 1*128);
3035 CVMX_PREFETCH(usb, 2*128);
3036 CVMX_PREFETCH(usb, 3*128);
3037 CVMX_PREFETCH(usb, 4*128);
3038
3039 /* Update the frame counter */
3040 usbc_hfnum.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index));
3041 if ((usb->frame_number&0x3fff) > usbc_hfnum.s.frnum)
3042 usb->frame_number += 0x4000;
3043 usb->frame_number &= ~0x3fffull;
3044 usb->frame_number |= usbc_hfnum.s.frnum;
3045
3046 /* Read the pending interrupts */
3047 usbc_gintsts.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GINTSTS(usb->index));
3048
3049 /* Clear the interrupts now that we know about them */
3050 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTSTS(usb->index), usbc_gintsts.u32);
3051
3052 if (usbc_gintsts.s.rxflvl) {
3053 /*
3054 * RxFIFO Non-Empty (RxFLvl)
3055 * Indicates that there is at least one packet pending to be
3056 * read from the RxFIFO.
3057 *
3058 * In DMA mode this is handled by hardware
3059 */
3060 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
3061 __cvmx_usb_poll_rx_fifo(usb);
3062 }
3063 if (usbc_gintsts.s.ptxfemp || usbc_gintsts.s.nptxfemp) {
3064 /* Fill the Tx FIFOs when not in DMA mode */
3065 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
3066 __cvmx_usb_poll_tx_fifo(usb);
3067 }
3068 if (usbc_gintsts.s.disconnint || usbc_gintsts.s.prtint) {
3069 union cvmx_usbcx_hprt usbc_hprt;
3070 /*
3071 * Disconnect Detected Interrupt (DisconnInt)
3072 * Asserted when a device disconnect is detected.
3073 *
3074 * Host Port Interrupt (PrtInt)
3075 * The core sets this bit to indicate a change in port status of
3076 * one of the O2P USB core ports in Host mode. The application
3077 * must read the Host Port Control and Status (HPRT) register to
3078 * determine the exact event that caused this interrupt. The
3079 * application must clear the appropriate status bit in the Host
3080 * Port Control and Status register to clear this bit.
3081 *
3082 * Call the user's port callback
3083 */
3084 __cvmx_usb_perform_callback(usb, NULL, NULL,
3085 CVMX_USB_CALLBACK_PORT_CHANGED,
3086 CVMX_USB_COMPLETE_SUCCESS);
3087 /* Clear the port change bits */
3088 usbc_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
3089 usbc_hprt.s.prtena = 0;
3090 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HPRT(usb->index), usbc_hprt.u32);
3091 }
3092 if (usbc_gintsts.s.hchint) {
3093 /*
3094 * Host Channels Interrupt (HChInt)
3095 * The core sets this bit to indicate that an interrupt is
3096 * pending on one of the channels of the core (in Host mode).
3097 * The application must read the Host All Channels Interrupt
3098 * (HAINT) register to determine the exact number of the channel
3099 * on which the interrupt occurred, and then read the
3100 * corresponding Host Channel-n Interrupt (HCINTn) register to
3101 * determine the exact cause of the interrupt. The application
3102 * must clear the appropriate status bit in the HCINTn register
3103 * to clear this bit.
3104 */
3105 union cvmx_usbcx_haint usbc_haint;
3106 usbc_haint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HAINT(usb->index));
3107 while (usbc_haint.u32) {
3108 int channel;
3109
3110 channel = __fls(usbc_haint.u32);
3111 __cvmx_usb_poll_channel(usb, channel);
3112 usbc_haint.u32 ^= 1<<channel;
3113 }
3114 }
3115
3116 __cvmx_usb_schedule(usb, usbc_gintsts.s.sof);
3117
3118 return 0;
3119 }
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