staging: octeon-usb: cvmx-usb.c: make comments to fit into 80 columns
[deliverable/linux.git] / drivers / staging / octeon-usb / cvmx-usb.c
1 /***********************license start***************
2 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
3 * reserved.
4 *
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met:
9 *
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 *
13 * * Redistributions in binary form must reproduce the above
14 * copyright notice, this list of conditions and the following
15 * disclaimer in the documentation and/or other materials provided
16 * with the distribution.
17
18 * * Neither the name of Cavium Networks nor the names of
19 * its contributors may be used to endorse or promote products
20 * derived from this software without specific prior written
21 * permission.
22
23 * This Software, including technical data, may be subject to U.S. export
24 * control laws, including the U.S. Export Administration Act and its associated
25 * regulations, and may be subject to export or import regulations in other
26 * countries.
27
28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
29 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION
32 * OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
38 ***********************license end**************************************/
39
40
41 /**
42 * @file
43 *
44 * "cvmx-usb.c" defines a set of low level USB functions to help
45 * developers create Octeon USB drivers for various operating
46 * systems. These functions provide a generic API to the Octeon
47 * USB blocks, hiding the internal hardware specific
48 * operations.
49 */
50 #include <linux/delay.h>
51 #include <asm/octeon/cvmx.h>
52 #include <asm/octeon/octeon.h>
53 #include <asm/octeon/cvmx-sysinfo.h>
54 #include "cvmx-usbnx-defs.h"
55 #include "cvmx-usbcx-defs.h"
56 #include "cvmx-usb.h"
57 #include <asm/octeon/cvmx-helper.h>
58 #include <asm/octeon/cvmx-helper-board.h>
59
60 /* Normal prefetch that use the pref instruction. */
61 #define CVMX_PREFETCH(address, offset) asm volatile ("pref %[type], %[off](%[rbase])" : : [rbase] "d" (address), [off] "I" (offset), [type] "n" (0))
62
63 /* Maximum number of times to retry failed transactions */
64 #define MAX_RETRIES 3
65
66 /* Maximum number of pipes that can be open at once */
67 #define MAX_PIPES 32
68
69 /* Maximum number of outstanding transactions across all pipes */
70 #define MAX_TRANSACTIONS 256
71
72 /* Maximum number of hardware channels supported by the USB block */
73 #define MAX_CHANNELS 8
74
75 /* The highest valid USB device address */
76 #define MAX_USB_ADDRESS 127
77
78 /* The highest valid USB endpoint number */
79 #define MAX_USB_ENDPOINT 15
80
81 /* The highest valid port number on a hub */
82 #define MAX_USB_HUB_PORT 15
83
84 /*
85 * The low level hardware can transfer a maximum of this number of bytes in each
86 * transfer. The field is 19 bits wide
87 */
88 #define MAX_TRANSFER_BYTES ((1<<19)-1)
89
90 /*
91 * The low level hardware can transfer a maximum of this number of packets in
92 * each transfer. The field is 10 bits wide
93 */
94 #define MAX_TRANSFER_PACKETS ((1<<10)-1)
95
96 enum cvmx_usb_transaction_flags {
97 __CVMX_USB_TRANSACTION_FLAGS_IN_USE = 1<<16,
98 };
99
100 enum {
101 USB_CLOCK_TYPE_REF_12,
102 USB_CLOCK_TYPE_REF_24,
103 USB_CLOCK_TYPE_REF_48,
104 USB_CLOCK_TYPE_CRYSTAL_12,
105 };
106
107 /**
108 * Logical transactions may take numerous low level
109 * transactions, especially when splits are concerned. This
110 * enum represents all of the possible stages a transaction can
111 * be in. Note that split completes are always even. This is so
112 * the NAK handler can backup to the previous low level
113 * transaction with a simple clearing of bit 0.
114 */
115 enum cvmx_usb_stage {
116 CVMX_USB_STAGE_NON_CONTROL,
117 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE,
118 CVMX_USB_STAGE_SETUP,
119 CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE,
120 CVMX_USB_STAGE_DATA,
121 CVMX_USB_STAGE_DATA_SPLIT_COMPLETE,
122 CVMX_USB_STAGE_STATUS,
123 CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE,
124 };
125
126 /**
127 * struct cvmx_usb_transaction - describes each pending USB transaction
128 * regardless of type. These are linked together
129 * to form a list of pending requests for a pipe.
130 *
131 * @prev: Transaction before this one in the pipe.
132 * @next: Transaction after this one in the pipe.
133 * @type: Type of transaction, duplicated of the pipe.
134 * @flags: State flags for this transaction.
135 * @buffer: User's physical buffer address to read/write.
136 * @buffer_length: Size of the user's buffer in bytes.
137 * @control_header: For control transactions, physical address of the 8
138 * byte standard header.
139 * @iso_start_frame: For ISO transactions, the starting frame number.
140 * @iso_number_packets: For ISO transactions, the number of packets in the
141 * request.
142 * @iso_packets: For ISO transactions, the sub packets in the request.
143 * @actual_bytes: Actual bytes transfer for this transaction.
144 * @stage: For control transactions, the current stage.
145 * @callback: User's callback function when complete.
146 * @callback_data: User's data.
147 */
148 struct cvmx_usb_transaction {
149 struct cvmx_usb_transaction *prev;
150 struct cvmx_usb_transaction *next;
151 enum cvmx_usb_transfer type;
152 enum cvmx_usb_transaction_flags flags;
153 uint64_t buffer;
154 int buffer_length;
155 uint64_t control_header;
156 int iso_start_frame;
157 int iso_number_packets;
158 struct cvmx_usb_iso_packet *iso_packets;
159 int xfersize;
160 int pktcnt;
161 int retries;
162 int actual_bytes;
163 enum cvmx_usb_stage stage;
164 cvmx_usb_callback_func_t callback;
165 void *callback_data;
166 };
167
168 /**
169 * struct cvmx_usb_pipe - a pipe represents a virtual connection between Octeon
170 * and some USB device. It contains a list of pending
171 * request to the device.
172 *
173 * @prev: Pipe before this one in the list
174 * @next: Pipe after this one in the list
175 * @head: The first pending transaction
176 * @tail: The last pending transaction
177 * @interval: For periodic pipes, the interval between packets in
178 * frames
179 * @next_tx_frame: The next frame this pipe is allowed to transmit on
180 * @flags: State flags for this pipe
181 * @device_speed: Speed of device connected to this pipe
182 * @transfer_type: Type of transaction supported by this pipe
183 * @transfer_dir: IN or OUT. Ignored for Control
184 * @multi_count: Max packet in a row for the device
185 * @max_packet: The device's maximum packet size in bytes
186 * @device_addr: USB device address at other end of pipe
187 * @endpoint_num: USB endpoint number at other end of pipe
188 * @hub_device_addr: Hub address this device is connected to
189 * @hub_port: Hub port this device is connected to
190 * @pid_toggle: This toggles between 0/1 on every packet send to track
191 * the data pid needed
192 * @channel: Hardware DMA channel for this pipe
193 * @split_sc_frame: The low order bits of the frame number the split
194 * complete should be sent on
195 */
196 struct cvmx_usb_pipe {
197 struct cvmx_usb_pipe *prev;
198 struct cvmx_usb_pipe *next;
199 struct cvmx_usb_transaction *head;
200 struct cvmx_usb_transaction *tail;
201 uint64_t interval;
202 uint64_t next_tx_frame;
203 enum cvmx_usb_pipe_flags flags;
204 enum cvmx_usb_speed device_speed;
205 enum cvmx_usb_transfer transfer_type;
206 enum cvmx_usb_direction transfer_dir;
207 int multi_count;
208 uint16_t max_packet;
209 uint8_t device_addr;
210 uint8_t endpoint_num;
211 uint8_t hub_device_addr;
212 uint8_t hub_port;
213 uint8_t pid_toggle;
214 uint8_t channel;
215 int8_t split_sc_frame;
216 };
217
218 /**
219 * struct cvmx_usb_pipe_list
220 *
221 * @head: Head of the list, or NULL if empty.
222 * @tail: Tail if the list, or NULL if empty.
223 */
224 struct cvmx_usb_pipe_list {
225 struct cvmx_usb_pipe *head;
226 struct cvmx_usb_pipe *tail;
227 };
228
229 struct cvmx_usb_tx_fifo {
230 struct {
231 int channel;
232 int size;
233 uint64_t address;
234 } entry[MAX_CHANNELS+1];
235 int head;
236 int tail;
237 };
238
239 /**
240 * struct cvmx_usb_internal_state - the state of the USB block
241 *
242 * init_flags: Flags passed to initialize.
243 * index: Which USB block this is for.
244 * idle_hardware_channels: Bit set for every idle hardware channel.
245 * usbcx_hprt: Stored port status so we don't need to read a CSR to
246 * determine splits.
247 * pipe_for_channel: Map channels to pipes.
248 * free_transaction_head: List of free transactions head.
249 * free_transaction_tail: List of free transactions tail.
250 * pipe: Storage for pipes.
251 * transaction: Storage for transactions.
252 * callback: User global callbacks.
253 * callback_data: User data for each callback.
254 * indent: Used by debug output to indent functions.
255 * port_status: Last port status used for change notification.
256 * free_pipes: List of all pipes that are currently closed.
257 * idle_pipes: List of open pipes that have no transactions.
258 * active_pipes: Active pipes indexed by transfer type.
259 * frame_number: Increments every SOF interrupt for time keeping.
260 * active_split: Points to the current active split, or NULL.
261 */
262 struct cvmx_usb_internal_state {
263 int init_flags;
264 int index;
265 int idle_hardware_channels;
266 union cvmx_usbcx_hprt usbcx_hprt;
267 struct cvmx_usb_pipe *pipe_for_channel[MAX_CHANNELS];
268 struct cvmx_usb_transaction *free_transaction_head;
269 struct cvmx_usb_transaction *free_transaction_tail;
270 struct cvmx_usb_pipe pipe[MAX_PIPES];
271 struct cvmx_usb_transaction transaction[MAX_TRANSACTIONS];
272 cvmx_usb_callback_func_t callback[__CVMX_USB_CALLBACK_END];
273 void *callback_data[__CVMX_USB_CALLBACK_END];
274 int indent;
275 struct cvmx_usb_port_status port_status;
276 struct cvmx_usb_pipe_list free_pipes;
277 struct cvmx_usb_pipe_list idle_pipes;
278 struct cvmx_usb_pipe_list active_pipes[4];
279 uint64_t frame_number;
280 struct cvmx_usb_transaction *active_split;
281 struct cvmx_usb_tx_fifo periodic;
282 struct cvmx_usb_tx_fifo nonperiodic;
283 };
284
285 /* This macro spins on a field waiting for it to reach a value */
286 #define CVMX_WAIT_FOR_FIELD32(address, type, field, op, value, timeout_usec)\
287 ({int result; \
288 do { \
289 uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec * \
290 octeon_get_clock_rate() / 1000000; \
291 type c; \
292 while (1) { \
293 c.u32 = __cvmx_usb_read_csr32(usb, address); \
294 if (c.s.field op (value)) { \
295 result = 0; \
296 break; \
297 } else if (cvmx_get_cycle() > done) { \
298 result = -1; \
299 break; \
300 } else \
301 cvmx_wait(100); \
302 } \
303 } while (0); \
304 result; })
305
306 /*
307 * This macro logically sets a single field in a CSR. It does the sequence
308 * read, modify, and write
309 */
310 #define USB_SET_FIELD32(address, type, field, value) \
311 do { \
312 type c; \
313 c.u32 = __cvmx_usb_read_csr32(usb, address); \
314 c.s.field = value; \
315 __cvmx_usb_write_csr32(usb, address, c.u32); \
316 } while (0)
317
318 /* Returns the IO address to push/pop stuff data from the FIFOs */
319 #define USB_FIFO_ADDRESS(channel, usb_index) (CVMX_USBCX_GOTGCTL(usb_index) + ((channel)+1)*0x1000)
320
321 static int octeon_usb_get_clock_type(void)
322 {
323 switch (cvmx_sysinfo_get()->board_type) {
324 case CVMX_BOARD_TYPE_BBGW_REF:
325 case CVMX_BOARD_TYPE_LANAI2_A:
326 case CVMX_BOARD_TYPE_LANAI2_U:
327 case CVMX_BOARD_TYPE_LANAI2_G:
328 case CVMX_BOARD_TYPE_UBNT_E100:
329 return USB_CLOCK_TYPE_CRYSTAL_12;
330 }
331 return USB_CLOCK_TYPE_REF_48;
332 }
333
334 /**
335 * Read a USB 32bit CSR. It performs the necessary address swizzle
336 * for 32bit CSRs and logs the value in a readable format if
337 * debugging is on.
338 *
339 * @usb: USB block this access is for
340 * @address: 64bit address to read
341 *
342 * Returns: Result of the read
343 */
344 static inline uint32_t __cvmx_usb_read_csr32(struct cvmx_usb_internal_state *usb,
345 uint64_t address)
346 {
347 uint32_t result = cvmx_read64_uint32(address ^ 4);
348 return result;
349 }
350
351
352 /**
353 * Write a USB 32bit CSR. It performs the necessary address
354 * swizzle for 32bit CSRs and logs the value in a readable format
355 * if debugging is on.
356 *
357 * @usb: USB block this access is for
358 * @address: 64bit address to write
359 * @value: Value to write
360 */
361 static inline void __cvmx_usb_write_csr32(struct cvmx_usb_internal_state *usb,
362 uint64_t address, uint32_t value)
363 {
364 cvmx_write64_uint32(address ^ 4, value);
365 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
366 }
367
368
369 /**
370 * Read a USB 64bit CSR. It logs the value in a readable format if
371 * debugging is on.
372 *
373 * @usb: USB block this access is for
374 * @address: 64bit address to read
375 *
376 * Returns: Result of the read
377 */
378 static inline uint64_t __cvmx_usb_read_csr64(struct cvmx_usb_internal_state *usb,
379 uint64_t address)
380 {
381 uint64_t result = cvmx_read64_uint64(address);
382 return result;
383 }
384
385
386 /**
387 * Write a USB 64bit CSR. It logs the value in a readable format
388 * if debugging is on.
389 *
390 * @usb: USB block this access is for
391 * @address: 64bit address to write
392 * @value: Value to write
393 */
394 static inline void __cvmx_usb_write_csr64(struct cvmx_usb_internal_state *usb,
395 uint64_t address, uint64_t value)
396 {
397 cvmx_write64_uint64(address, value);
398 }
399
400 /**
401 * Return non zero if this pipe connects to a non HIGH speed
402 * device through a high speed hub.
403 *
404 * @usb: USB block this access is for
405 * @pipe: Pipe to check
406 *
407 * Returns: Non zero if we need to do split transactions
408 */
409 static inline int __cvmx_usb_pipe_needs_split(struct cvmx_usb_internal_state *usb, struct cvmx_usb_pipe *pipe)
410 {
411 return ((pipe->device_speed != CVMX_USB_SPEED_HIGH) && (usb->usbcx_hprt.s.prtspd == CVMX_USB_SPEED_HIGH));
412 }
413
414
415 /**
416 * Trivial utility function to return the correct PID for a pipe
417 *
418 * @pipe: pipe to check
419 *
420 * Returns: PID for pipe
421 */
422 static inline int __cvmx_usb_get_data_pid(struct cvmx_usb_pipe *pipe)
423 {
424 if (pipe->pid_toggle)
425 return 2; /* Data1 */
426 else
427 return 0; /* Data0 */
428 }
429
430
431 /**
432 * Return the number of USB ports supported by this Octeon
433 * chip. If the chip doesn't support USB, or is not supported
434 * by this API, a zero will be returned. Most Octeon chips
435 * support one usb port, but some support two ports.
436 * cvmx_usb_initialize() must be called on independent
437 * struct cvmx_usb_state.
438 *
439 * Returns: Number of port, zero if usb isn't supported
440 */
441 int cvmx_usb_get_num_ports(void)
442 {
443 int arch_ports = 0;
444
445 if (OCTEON_IS_MODEL(OCTEON_CN56XX))
446 arch_ports = 1;
447 else if (OCTEON_IS_MODEL(OCTEON_CN52XX))
448 arch_ports = 2;
449 else if (OCTEON_IS_MODEL(OCTEON_CN50XX))
450 arch_ports = 1;
451 else if (OCTEON_IS_MODEL(OCTEON_CN31XX))
452 arch_ports = 1;
453 else if (OCTEON_IS_MODEL(OCTEON_CN30XX))
454 arch_ports = 1;
455 else
456 arch_ports = 0;
457
458 return arch_ports;
459 }
460
461
462 /**
463 * Allocate a usb transaction for use
464 *
465 * @usb: USB device state populated by
466 * cvmx_usb_initialize().
467 *
468 * Returns: Transaction or NULL
469 */
470 static inline struct cvmx_usb_transaction *__cvmx_usb_alloc_transaction(struct cvmx_usb_internal_state *usb)
471 {
472 struct cvmx_usb_transaction *t;
473 t = usb->free_transaction_head;
474 if (t) {
475 usb->free_transaction_head = t->next;
476 if (!usb->free_transaction_head)
477 usb->free_transaction_tail = NULL;
478 }
479 if (t) {
480 memset(t, 0, sizeof(*t));
481 t->flags = __CVMX_USB_TRANSACTION_FLAGS_IN_USE;
482 }
483 return t;
484 }
485
486
487 /**
488 * Free a usb transaction
489 *
490 * @usb: USB device state populated by
491 * cvmx_usb_initialize().
492 * @transaction:
493 * Transaction to free
494 */
495 static inline void __cvmx_usb_free_transaction(struct cvmx_usb_internal_state *usb,
496 struct cvmx_usb_transaction *transaction)
497 {
498 transaction->flags = 0;
499 transaction->prev = NULL;
500 transaction->next = NULL;
501 if (usb->free_transaction_tail)
502 usb->free_transaction_tail->next = transaction;
503 else
504 usb->free_transaction_head = transaction;
505 usb->free_transaction_tail = transaction;
506 }
507
508
509 /**
510 * Add a pipe to the tail of a list
511 * @list: List to add pipe to
512 * @pipe: Pipe to add
513 */
514 static inline void __cvmx_usb_append_pipe(struct cvmx_usb_pipe_list *list, struct cvmx_usb_pipe *pipe)
515 {
516 pipe->next = NULL;
517 pipe->prev = list->tail;
518 if (list->tail)
519 list->tail->next = pipe;
520 else
521 list->head = pipe;
522 list->tail = pipe;
523 }
524
525
526 /**
527 * Remove a pipe from a list
528 * @list: List to remove pipe from
529 * @pipe: Pipe to remove
530 */
531 static inline void __cvmx_usb_remove_pipe(struct cvmx_usb_pipe_list *list, struct cvmx_usb_pipe *pipe)
532 {
533 if (list->head == pipe) {
534 list->head = pipe->next;
535 pipe->next = NULL;
536 if (list->head)
537 list->head->prev = NULL;
538 else
539 list->tail = NULL;
540 } else if (list->tail == pipe) {
541 list->tail = pipe->prev;
542 list->tail->next = NULL;
543 pipe->prev = NULL;
544 } else {
545 pipe->prev->next = pipe->next;
546 pipe->next->prev = pipe->prev;
547 pipe->prev = NULL;
548 pipe->next = NULL;
549 }
550 }
551
552
553 /**
554 * Initialize a USB port for use. This must be called before any
555 * other access to the Octeon USB port is made. The port starts
556 * off in the disabled state.
557 *
558 * @state: Pointer to an empty struct cvmx_usb_state
559 * that will be populated by the initialize call.
560 * This structure is then passed to all other USB
561 * functions.
562 * @usb_port_number:
563 * Which Octeon USB port to initialize.
564 *
565 * Returns: 0 or a negative error code.
566 */
567 int cvmx_usb_initialize(struct cvmx_usb_state *state, int usb_port_number)
568 {
569 union cvmx_usbnx_clk_ctl usbn_clk_ctl;
570 union cvmx_usbnx_usbp_ctl_status usbn_usbp_ctl_status;
571 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
572 enum cvmx_usb_initialize_flags flags = 0;
573
574 /* Make sure that state is large enough to store the internal state */
575 if (sizeof(*state) < sizeof(*usb))
576 return -EINVAL;
577 /* At first allow 0-1 for the usb port number */
578 if ((usb_port_number < 0) || (usb_port_number > 1))
579 return -EINVAL;
580 /* For all chips except 52XX there is only one port */
581 if (!OCTEON_IS_MODEL(OCTEON_CN52XX) && (usb_port_number > 0))
582 return -EINVAL;
583 /* Try to determine clock type automatically */
584 if (octeon_usb_get_clock_type() == USB_CLOCK_TYPE_CRYSTAL_12) {
585 /* Only 12 MHZ crystals are supported */
586 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI;
587 } else {
588 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND;
589
590 switch (octeon_usb_get_clock_type()) {
591 case USB_CLOCK_TYPE_REF_12:
592 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ;
593 break;
594 case USB_CLOCK_TYPE_REF_24:
595 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ;
596 break;
597 case USB_CLOCK_TYPE_REF_48:
598 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ;
599 break;
600 default:
601 return -EINVAL;
602 break;
603 }
604 }
605
606 memset(usb, 0, sizeof(*usb));
607 usb->init_flags = flags;
608
609 /* Initialize the USB state structure */
610 {
611 int i;
612 usb->index = usb_port_number;
613
614 /* Initialize the transaction double linked list */
615 usb->free_transaction_head = NULL;
616 usb->free_transaction_tail = NULL;
617 for (i = 0; i < MAX_TRANSACTIONS; i++)
618 __cvmx_usb_free_transaction(usb, usb->transaction + i);
619 for (i = 0; i < MAX_PIPES; i++)
620 __cvmx_usb_append_pipe(&usb->free_pipes, usb->pipe + i);
621 }
622
623 /*
624 * Power On Reset and PHY Initialization
625 *
626 * 1. Wait for DCOK to assert (nothing to do)
627 *
628 * 2a. Write USBN0/1_CLK_CTL[POR] = 1 and
629 * USBN0/1_CLK_CTL[HRST,PRST,HCLK_RST] = 0
630 */
631 usbn_clk_ctl.u64 = __cvmx_usb_read_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index));
632 usbn_clk_ctl.s.por = 1;
633 usbn_clk_ctl.s.hrst = 0;
634 usbn_clk_ctl.s.prst = 0;
635 usbn_clk_ctl.s.hclk_rst = 0;
636 usbn_clk_ctl.s.enable = 0;
637 /*
638 * 2b. Select the USB reference clock/crystal parameters by writing
639 * appropriate values to USBN0/1_CLK_CTL[P_C_SEL, P_RTYPE, P_COM_ON]
640 */
641 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND) {
642 /*
643 * The USB port uses 12/24/48MHz 2.5V board clock
644 * source at USB_XO. USB_XI should be tied to GND.
645 * Most Octeon evaluation boards require this setting
646 */
647 if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
648 /* From CN31XX,CN30XX manual */
649 usbn_clk_ctl.cn31xx.p_rclk = 1;
650 usbn_clk_ctl.cn31xx.p_xenbn = 0;
651 } else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))
652 /* From CN56XX,CN50XX manual */
653 usbn_clk_ctl.cn56xx.p_rtype = 2;
654 else
655 /* From CN52XX manual */
656 usbn_clk_ctl.cn52xx.p_rtype = 1;
657
658 switch (flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK) {
659 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ:
660 usbn_clk_ctl.s.p_c_sel = 0;
661 break;
662 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ:
663 usbn_clk_ctl.s.p_c_sel = 1;
664 break;
665 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ:
666 usbn_clk_ctl.s.p_c_sel = 2;
667 break;
668 }
669 } else {
670 /*
671 * The USB port uses a 12MHz crystal as clock source
672 * at USB_XO and USB_XI
673 */
674 if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
675 /* From CN31XX,CN30XX manual */
676 usbn_clk_ctl.cn31xx.p_rclk = 1;
677 usbn_clk_ctl.cn31xx.p_xenbn = 1;
678 } else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))
679 /* From CN56XX,CN50XX manual */
680 usbn_clk_ctl.cn56xx.p_rtype = 0;
681 else
682 /* From CN52XX manual */
683 usbn_clk_ctl.cn52xx.p_rtype = 0;
684
685 usbn_clk_ctl.s.p_c_sel = 0;
686 }
687 /*
688 * 2c. Select the HCLK via writing USBN0/1_CLK_CTL[DIVIDE, DIVIDE2] and
689 * setting USBN0/1_CLK_CTL[ENABLE] = 1. Divide the core clock down
690 * such that USB is as close as possible to 125Mhz
691 */
692 {
693 int divisor = (octeon_get_clock_rate()+125000000-1)/125000000;
694 /* Lower than 4 doesn't seem to work properly */
695 if (divisor < 4)
696 divisor = 4;
697 usbn_clk_ctl.s.divide = divisor;
698 usbn_clk_ctl.s.divide2 = 0;
699 }
700 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
701 usbn_clk_ctl.u64);
702 /* 2d. Write USBN0/1_CLK_CTL[HCLK_RST] = 1 */
703 usbn_clk_ctl.s.hclk_rst = 1;
704 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
705 usbn_clk_ctl.u64);
706 /* 2e. Wait 64 core-clock cycles for HCLK to stabilize */
707 cvmx_wait(64);
708 /*
709 * 3. Program the power-on reset field in the USBN clock-control
710 * register:
711 * USBN_CLK_CTL[POR] = 0
712 */
713 usbn_clk_ctl.s.por = 0;
714 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
715 usbn_clk_ctl.u64);
716 /* 4. Wait 1 ms for PHY clock to start */
717 mdelay(1);
718 /*
719 * 5. Program the Reset input from automatic test equipment field in the
720 * USBP control and status register:
721 * USBN_USBP_CTL_STATUS[ATE_RESET] = 1
722 */
723 usbn_usbp_ctl_status.u64 = __cvmx_usb_read_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index));
724 usbn_usbp_ctl_status.s.ate_reset = 1;
725 __cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
726 usbn_usbp_ctl_status.u64);
727 /* 6. Wait 10 cycles */
728 cvmx_wait(10);
729 /*
730 * 7. Clear ATE_RESET field in the USBN clock-control register:
731 * USBN_USBP_CTL_STATUS[ATE_RESET] = 0
732 */
733 usbn_usbp_ctl_status.s.ate_reset = 0;
734 __cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
735 usbn_usbp_ctl_status.u64);
736 /*
737 * 8. Program the PHY reset field in the USBN clock-control register:
738 * USBN_CLK_CTL[PRST] = 1
739 */
740 usbn_clk_ctl.s.prst = 1;
741 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
742 usbn_clk_ctl.u64);
743 /*
744 * 9. Program the USBP control and status register to select host or
745 * device mode. USBN_USBP_CTL_STATUS[HST_MODE] = 0 for host, = 1 for
746 * device
747 */
748 usbn_usbp_ctl_status.s.hst_mode = 0;
749 __cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
750 usbn_usbp_ctl_status.u64);
751 /* 10. Wait 1 us */
752 udelay(1);
753 /*
754 * 11. Program the hreset_n field in the USBN clock-control register:
755 * USBN_CLK_CTL[HRST] = 1
756 */
757 usbn_clk_ctl.s.hrst = 1;
758 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
759 usbn_clk_ctl.u64);
760 /* 12. Proceed to USB core initialization */
761 usbn_clk_ctl.s.enable = 1;
762 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
763 usbn_clk_ctl.u64);
764 udelay(1);
765
766 /*
767 * USB Core Initialization
768 *
769 * 1. Read USBC_GHWCFG1, USBC_GHWCFG2, USBC_GHWCFG3, USBC_GHWCFG4 to
770 * determine USB core configuration parameters.
771 *
772 * Nothing needed
773 *
774 * 2. Program the following fields in the global AHB configuration
775 * register (USBC_GAHBCFG)
776 * DMA mode, USBC_GAHBCFG[DMAEn]: 1 = DMA mode, 0 = slave mode
777 * Burst length, USBC_GAHBCFG[HBSTLEN] = 0
778 * Nonperiodic TxFIFO empty level (slave mode only),
779 * USBC_GAHBCFG[NPTXFEMPLVL]
780 * Periodic TxFIFO empty level (slave mode only),
781 * USBC_GAHBCFG[PTXFEMPLVL]
782 * Global interrupt mask, USBC_GAHBCFG[GLBLINTRMSK] = 1
783 */
784 {
785 union cvmx_usbcx_gahbcfg usbcx_gahbcfg;
786 /* Due to an errata, CN31XX doesn't support DMA */
787 if (OCTEON_IS_MODEL(OCTEON_CN31XX))
788 usb->init_flags |= CVMX_USB_INITIALIZE_FLAGS_NO_DMA;
789 usbcx_gahbcfg.u32 = 0;
790 usbcx_gahbcfg.s.dmaen = !(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA);
791 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
792 /* Only use one channel with non DMA */
793 usb->idle_hardware_channels = 0x1;
794 else if (OCTEON_IS_MODEL(OCTEON_CN5XXX))
795 /* CN5XXX have an errata with channel 3 */
796 usb->idle_hardware_channels = 0xf7;
797 else
798 usb->idle_hardware_channels = 0xff;
799 usbcx_gahbcfg.s.hbstlen = 0;
800 usbcx_gahbcfg.s.nptxfemplvl = 1;
801 usbcx_gahbcfg.s.ptxfemplvl = 1;
802 usbcx_gahbcfg.s.glblintrmsk = 1;
803 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GAHBCFG(usb->index),
804 usbcx_gahbcfg.u32);
805 }
806 /*
807 * 3. Program the following fields in USBC_GUSBCFG register.
808 * HS/FS timeout calibration, USBC_GUSBCFG[TOUTCAL] = 0
809 * ULPI DDR select, USBC_GUSBCFG[DDRSEL] = 0
810 * USB turnaround time, USBC_GUSBCFG[USBTRDTIM] = 0x5
811 * PHY low-power clock select, USBC_GUSBCFG[PHYLPWRCLKSEL] = 0
812 */
813 {
814 union cvmx_usbcx_gusbcfg usbcx_gusbcfg;
815 usbcx_gusbcfg.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GUSBCFG(usb->index));
816 usbcx_gusbcfg.s.toutcal = 0;
817 usbcx_gusbcfg.s.ddrsel = 0;
818 usbcx_gusbcfg.s.usbtrdtim = 0x5;
819 usbcx_gusbcfg.s.phylpwrclksel = 0;
820 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GUSBCFG(usb->index),
821 usbcx_gusbcfg.u32);
822 }
823 /*
824 * 4. The software must unmask the following bits in the USBC_GINTMSK
825 * register.
826 * OTG interrupt mask, USBC_GINTMSK[OTGINTMSK] = 1
827 * Mode mismatch interrupt mask, USBC_GINTMSK[MODEMISMSK] = 1
828 */
829 {
830 union cvmx_usbcx_gintmsk usbcx_gintmsk;
831 int channel;
832
833 usbcx_gintmsk.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GINTMSK(usb->index));
834 usbcx_gintmsk.s.otgintmsk = 1;
835 usbcx_gintmsk.s.modemismsk = 1;
836 usbcx_gintmsk.s.hchintmsk = 1;
837 usbcx_gintmsk.s.sofmsk = 0;
838 /* We need RX FIFO interrupts if we don't have DMA */
839 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
840 usbcx_gintmsk.s.rxflvlmsk = 1;
841 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTMSK(usb->index),
842 usbcx_gintmsk.u32);
843
844 /*
845 * Disable all channel interrupts. We'll enable them per channel
846 * later.
847 */
848 for (channel = 0; channel < 8; channel++)
849 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), 0);
850 }
851
852 {
853 /*
854 * Host Port Initialization
855 *
856 * 1. Program the host-port interrupt-mask field to unmask,
857 * USBC_GINTMSK[PRTINT] = 1
858 */
859 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk,
860 prtintmsk, 1);
861 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk,
862 disconnintmsk, 1);
863 /*
864 * 2. Program the USBC_HCFG register to select full-speed host
865 * or high-speed host.
866 */
867 {
868 union cvmx_usbcx_hcfg usbcx_hcfg;
869 usbcx_hcfg.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCFG(usb->index));
870 usbcx_hcfg.s.fslssupp = 0;
871 usbcx_hcfg.s.fslspclksel = 0;
872 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCFG(usb->index), usbcx_hcfg.u32);
873 }
874 /*
875 * 3. Program the port power bit to drive VBUS on the USB,
876 * USBC_HPRT[PRTPWR] = 1
877 */
878 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt, prtpwr, 1);
879
880 /*
881 * Steps 4-15 from the manual are done later in the port enable
882 */
883 }
884
885 return 0;
886 }
887
888
889 /**
890 * Shutdown a USB port after a call to cvmx_usb_initialize().
891 * The port should be disabled with all pipes closed when this
892 * function is called.
893 *
894 * @state: USB device state populated by
895 * cvmx_usb_initialize().
896 *
897 * Returns: 0 or a negative error code.
898 */
899 int cvmx_usb_shutdown(struct cvmx_usb_state *state)
900 {
901 union cvmx_usbnx_clk_ctl usbn_clk_ctl;
902 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
903
904 /* Make sure all pipes are closed */
905 if (usb->idle_pipes.head ||
906 usb->active_pipes[CVMX_USB_TRANSFER_ISOCHRONOUS].head ||
907 usb->active_pipes[CVMX_USB_TRANSFER_INTERRUPT].head ||
908 usb->active_pipes[CVMX_USB_TRANSFER_CONTROL].head ||
909 usb->active_pipes[CVMX_USB_TRANSFER_BULK].head)
910 return -EBUSY;
911
912 /* Disable the clocks and put them in power on reset */
913 usbn_clk_ctl.u64 = __cvmx_usb_read_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index));
914 usbn_clk_ctl.s.enable = 1;
915 usbn_clk_ctl.s.por = 1;
916 usbn_clk_ctl.s.hclk_rst = 1;
917 usbn_clk_ctl.s.prst = 0;
918 usbn_clk_ctl.s.hrst = 0;
919 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
920 usbn_clk_ctl.u64);
921 return 0;
922 }
923
924
925 /**
926 * Enable a USB port. After this call succeeds, the USB port is
927 * online and servicing requests.
928 *
929 * @state: USB device state populated by
930 * cvmx_usb_initialize().
931 *
932 * Returns: 0 or a negative error code.
933 */
934 int cvmx_usb_enable(struct cvmx_usb_state *state)
935 {
936 union cvmx_usbcx_ghwcfg3 usbcx_ghwcfg3;
937 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
938
939 usb->usbcx_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
940
941 /*
942 * If the port is already enabled the just return. We don't need to do
943 * anything
944 */
945 if (usb->usbcx_hprt.s.prtena)
946 return 0;
947
948 /* If there is nothing plugged into the port then fail immediately */
949 if (!usb->usbcx_hprt.s.prtconnsts) {
950 return -ETIMEDOUT;
951 }
952
953 /* Program the port reset bit to start the reset process */
954 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt, prtrst, 1);
955
956 /*
957 * Wait at least 50ms (high speed), or 10ms (full speed) for the reset
958 * process to complete.
959 */
960 mdelay(50);
961
962 /* Program the port reset bit to 0, USBC_HPRT[PRTRST] = 0 */
963 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt, prtrst, 0);
964
965 /* Wait for the USBC_HPRT[PRTENA]. */
966 if (CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt,
967 prtena, ==, 1, 100000))
968 return -ETIMEDOUT;
969
970 /*
971 * Read the port speed field to get the enumerated speed,
972 * USBC_HPRT[PRTSPD].
973 */
974 usb->usbcx_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
975 usbcx_ghwcfg3.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GHWCFG3(usb->index));
976
977 /*
978 * 13. Program the USBC_GRXFSIZ register to select the size of the
979 * receive FIFO (25%).
980 */
981 USB_SET_FIELD32(CVMX_USBCX_GRXFSIZ(usb->index), union cvmx_usbcx_grxfsiz,
982 rxfdep, usbcx_ghwcfg3.s.dfifodepth / 4);
983 /*
984 * 14. Program the USBC_GNPTXFSIZ register to select the size and the
985 * start address of the non- periodic transmit FIFO for nonperiodic
986 * transactions (50%).
987 */
988 {
989 union cvmx_usbcx_gnptxfsiz siz;
990 siz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index));
991 siz.s.nptxfdep = usbcx_ghwcfg3.s.dfifodepth / 2;
992 siz.s.nptxfstaddr = usbcx_ghwcfg3.s.dfifodepth / 4;
993 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index), siz.u32);
994 }
995 /*
996 * 15. Program the USBC_HPTXFSIZ register to select the size and start
997 * address of the periodic transmit FIFO for periodic transactions
998 * (25%).
999 */
1000 {
1001 union cvmx_usbcx_hptxfsiz siz;
1002 siz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPTXFSIZ(usb->index));
1003 siz.s.ptxfsize = usbcx_ghwcfg3.s.dfifodepth / 4;
1004 siz.s.ptxfstaddr = 3 * usbcx_ghwcfg3.s.dfifodepth / 4;
1005 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HPTXFSIZ(usb->index), siz.u32);
1006 }
1007 /* Flush all FIFOs */
1008 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), union cvmx_usbcx_grstctl, txfnum, 0x10);
1009 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), union cvmx_usbcx_grstctl, txfflsh, 1);
1010 CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), union cvmx_usbcx_grstctl,
1011 txfflsh, ==, 0, 100);
1012 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), union cvmx_usbcx_grstctl, rxfflsh, 1);
1013 CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), union cvmx_usbcx_grstctl,
1014 rxfflsh, ==, 0, 100);
1015
1016 return 0;
1017 }
1018
1019
1020 /**
1021 * Disable a USB port. After this call the USB port will not
1022 * generate data transfers and will not generate events.
1023 * Transactions in process will fail and call their
1024 * associated callbacks.
1025 *
1026 * @state: USB device state populated by
1027 * cvmx_usb_initialize().
1028 *
1029 * Returns: 0 or a negative error code.
1030 */
1031 int cvmx_usb_disable(struct cvmx_usb_state *state)
1032 {
1033 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
1034
1035 /* Disable the port */
1036 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt, prtena, 1);
1037 return 0;
1038 }
1039
1040
1041 /**
1042 * Get the current state of the USB port. Use this call to
1043 * determine if the usb port has anything connected, is enabled,
1044 * or has some sort of error condition. The return value of this
1045 * call has "changed" bits to signal of the value of some fields
1046 * have changed between calls. These "changed" fields are based
1047 * on the last call to cvmx_usb_set_status(). In order to clear
1048 * them, you must update the status through cvmx_usb_set_status().
1049 *
1050 * @state: USB device state populated by
1051 * cvmx_usb_initialize().
1052 *
1053 * Returns: Port status information
1054 */
1055 struct cvmx_usb_port_status cvmx_usb_get_status(struct cvmx_usb_state *state)
1056 {
1057 union cvmx_usbcx_hprt usbc_hprt;
1058 struct cvmx_usb_port_status result;
1059 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
1060
1061 memset(&result, 0, sizeof(result));
1062
1063 usbc_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
1064 result.port_enabled = usbc_hprt.s.prtena;
1065 result.port_over_current = usbc_hprt.s.prtovrcurract;
1066 result.port_powered = usbc_hprt.s.prtpwr;
1067 result.port_speed = usbc_hprt.s.prtspd;
1068 result.connected = usbc_hprt.s.prtconnsts;
1069 result.connect_change = (result.connected != usb->port_status.connected);
1070
1071 return result;
1072 }
1073
1074
1075 /**
1076 * Set the current state of the USB port. The status is used as
1077 * a reference for the "changed" bits returned by
1078 * cvmx_usb_get_status(). Other than serving as a reference, the
1079 * status passed to this function is not used. No fields can be
1080 * changed through this call.
1081 *
1082 * @state: USB device state populated by
1083 * cvmx_usb_initialize().
1084 * @port_status:
1085 * Port status to set, most like returned by cvmx_usb_get_status()
1086 */
1087 void cvmx_usb_set_status(struct cvmx_usb_state *state, struct cvmx_usb_port_status port_status)
1088 {
1089 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
1090 usb->port_status = port_status;
1091 return;
1092 }
1093
1094
1095 /**
1096 * Convert a USB transaction into a handle
1097 *
1098 * @usb: USB device state populated by
1099 * cvmx_usb_initialize().
1100 * @transaction:
1101 * Transaction to get handle for
1102 *
1103 * Returns: Handle
1104 */
1105 static inline int __cvmx_usb_get_submit_handle(struct cvmx_usb_internal_state *usb,
1106 struct cvmx_usb_transaction *transaction)
1107 {
1108 return ((unsigned long)transaction - (unsigned long)usb->transaction) /
1109 sizeof(*transaction);
1110 }
1111
1112
1113 /**
1114 * Convert a USB pipe into a handle
1115 *
1116 * @usb: USB device state populated by
1117 * cvmx_usb_initialize().
1118 * @pipe: Pipe to get handle for
1119 *
1120 * Returns: Handle
1121 */
1122 static inline int __cvmx_usb_get_pipe_handle(struct cvmx_usb_internal_state *usb,
1123 struct cvmx_usb_pipe *pipe)
1124 {
1125 return ((unsigned long)pipe - (unsigned long)usb->pipe) / sizeof(*pipe);
1126 }
1127
1128
1129 /**
1130 * Open a virtual pipe between the host and a USB device. A pipe
1131 * must be opened before data can be transferred between a device
1132 * and Octeon.
1133 *
1134 * @state: USB device state populated by
1135 * cvmx_usb_initialize().
1136 * @device_addr:
1137 * USB device address to open the pipe to
1138 * (0-127).
1139 * @endpoint_num:
1140 * USB endpoint number to open the pipe to
1141 * (0-15).
1142 * @device_speed:
1143 * The speed of the device the pipe is going
1144 * to. This must match the device's speed,
1145 * which may be different than the port speed.
1146 * @max_packet: The maximum packet length the device can
1147 * transmit/receive (low speed=0-8, full
1148 * speed=0-1023, high speed=0-1024). This value
1149 * comes from the standard endpoint descriptor
1150 * field wMaxPacketSize bits <10:0>.
1151 * @transfer_type:
1152 * The type of transfer this pipe is for.
1153 * @transfer_dir:
1154 * The direction the pipe is in. This is not
1155 * used for control pipes.
1156 * @interval: For ISOCHRONOUS and INTERRUPT transfers,
1157 * this is how often the transfer is scheduled
1158 * for. All other transfers should specify
1159 * zero. The units are in frames (8000/sec at
1160 * high speed, 1000/sec for full speed).
1161 * @multi_count:
1162 * For high speed devices, this is the maximum
1163 * allowed number of packet per microframe.
1164 * Specify zero for non high speed devices. This
1165 * value comes from the standard endpoint descriptor
1166 * field wMaxPacketSize bits <12:11>.
1167 * @hub_device_addr:
1168 * Hub device address this device is connected
1169 * to. Devices connected directly to Octeon
1170 * use zero. This is only used when the device
1171 * is full/low speed behind a high speed hub.
1172 * The address will be of the high speed hub,
1173 * not and full speed hubs after it.
1174 * @hub_port: Which port on the hub the device is
1175 * connected. Use zero for devices connected
1176 * directly to Octeon. Like hub_device_addr,
1177 * this is only used for full/low speed
1178 * devices behind a high speed hub.
1179 *
1180 * Returns: A non negative value is a pipe handle. Negative
1181 * values are error codes.
1182 */
1183 int cvmx_usb_open_pipe(struct cvmx_usb_state *state,
1184 int device_addr, int endpoint_num,
1185 enum cvmx_usb_speed device_speed, int max_packet,
1186 enum cvmx_usb_transfer transfer_type,
1187 enum cvmx_usb_direction transfer_dir, int interval,
1188 int multi_count, int hub_device_addr, int hub_port)
1189 {
1190 struct cvmx_usb_pipe *pipe;
1191 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
1192
1193 if (unlikely((device_addr < 0) || (device_addr > MAX_USB_ADDRESS)))
1194 return -EINVAL;
1195 if (unlikely((endpoint_num < 0) || (endpoint_num > MAX_USB_ENDPOINT)))
1196 return -EINVAL;
1197 if (unlikely(device_speed > CVMX_USB_SPEED_LOW))
1198 return -EINVAL;
1199 if (unlikely((max_packet <= 0) || (max_packet > 1024)))
1200 return -EINVAL;
1201 if (unlikely(transfer_type > CVMX_USB_TRANSFER_INTERRUPT))
1202 return -EINVAL;
1203 if (unlikely((transfer_dir != CVMX_USB_DIRECTION_OUT) &&
1204 (transfer_dir != CVMX_USB_DIRECTION_IN)))
1205 return -EINVAL;
1206 if (unlikely(interval < 0))
1207 return -EINVAL;
1208 if (unlikely((transfer_type == CVMX_USB_TRANSFER_CONTROL) && interval))
1209 return -EINVAL;
1210 if (unlikely(multi_count < 0))
1211 return -EINVAL;
1212 if (unlikely((device_speed != CVMX_USB_SPEED_HIGH) &&
1213 (multi_count != 0)))
1214 return -EINVAL;
1215 if (unlikely((hub_device_addr < 0) || (hub_device_addr > MAX_USB_ADDRESS)))
1216 return -EINVAL;
1217 if (unlikely((hub_port < 0) || (hub_port > MAX_USB_HUB_PORT)))
1218 return -EINVAL;
1219
1220 /* Find a free pipe */
1221 pipe = usb->free_pipes.head;
1222 if (!pipe)
1223 return -ENOMEM;
1224 __cvmx_usb_remove_pipe(&usb->free_pipes, pipe);
1225 pipe->flags = __CVMX_USB_PIPE_FLAGS_OPEN;
1226 if ((device_speed == CVMX_USB_SPEED_HIGH) &&
1227 (transfer_dir == CVMX_USB_DIRECTION_OUT) &&
1228 (transfer_type == CVMX_USB_TRANSFER_BULK))
1229 pipe->flags |= __CVMX_USB_PIPE_FLAGS_NEED_PING;
1230 pipe->device_addr = device_addr;
1231 pipe->endpoint_num = endpoint_num;
1232 pipe->device_speed = device_speed;
1233 pipe->max_packet = max_packet;
1234 pipe->transfer_type = transfer_type;
1235 pipe->transfer_dir = transfer_dir;
1236 /*
1237 * All pipes use interval to rate limit NAK processing. Force an
1238 * interval if one wasn't supplied
1239 */
1240 if (!interval)
1241 interval = 1;
1242 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1243 pipe->interval = interval*8;
1244 /* Force start splits to be schedule on uFrame 0 */
1245 pipe->next_tx_frame = ((usb->frame_number+7)&~7) + pipe->interval;
1246 } else {
1247 pipe->interval = interval;
1248 pipe->next_tx_frame = usb->frame_number + pipe->interval;
1249 }
1250 pipe->multi_count = multi_count;
1251 pipe->hub_device_addr = hub_device_addr;
1252 pipe->hub_port = hub_port;
1253 pipe->pid_toggle = 0;
1254 pipe->split_sc_frame = -1;
1255 __cvmx_usb_append_pipe(&usb->idle_pipes, pipe);
1256
1257 /*
1258 * We don't need to tell the hardware about this pipe yet since
1259 * it doesn't have any submitted requests
1260 */
1261
1262 return __cvmx_usb_get_pipe_handle(usb, pipe);
1263 }
1264
1265
1266 /**
1267 * Poll the RX FIFOs and remove data as needed. This function is only used
1268 * in non DMA mode. It is very important that this function be called quickly
1269 * enough to prevent FIFO overflow.
1270 *
1271 * @usb: USB device state populated by
1272 * cvmx_usb_initialize().
1273 */
1274 static void __cvmx_usb_poll_rx_fifo(struct cvmx_usb_internal_state *usb)
1275 {
1276 union cvmx_usbcx_grxstsph rx_status;
1277 int channel;
1278 int bytes;
1279 uint64_t address;
1280 uint32_t *ptr;
1281
1282 rx_status.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GRXSTSPH(usb->index));
1283 /* Only read data if IN data is there */
1284 if (rx_status.s.pktsts != 2)
1285 return;
1286 /* Check if no data is available */
1287 if (!rx_status.s.bcnt)
1288 return;
1289
1290 channel = rx_status.s.chnum;
1291 bytes = rx_status.s.bcnt;
1292 if (!bytes)
1293 return;
1294
1295 /* Get where the DMA engine would have written this data */
1296 address = __cvmx_usb_read_csr64(usb, CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8);
1297 ptr = cvmx_phys_to_ptr(address);
1298 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8, address + bytes);
1299
1300 /* Loop writing the FIFO data for this packet into memory */
1301 while (bytes > 0) {
1302 *ptr++ = __cvmx_usb_read_csr32(usb, USB_FIFO_ADDRESS(channel, usb->index));
1303 bytes -= 4;
1304 }
1305 CVMX_SYNCW;
1306
1307 return;
1308 }
1309
1310
1311 /**
1312 * Fill the TX hardware fifo with data out of the software
1313 * fifos
1314 *
1315 * @usb: USB device state populated by
1316 * cvmx_usb_initialize().
1317 * @fifo: Software fifo to use
1318 * @available: Amount of space in the hardware fifo
1319 *
1320 * Returns: Non zero if the hardware fifo was too small and needs
1321 * to be serviced again.
1322 */
1323 static int __cvmx_usb_fill_tx_hw(struct cvmx_usb_internal_state *usb, struct cvmx_usb_tx_fifo *fifo, int available)
1324 {
1325 /*
1326 * We're done either when there isn't anymore space or the software FIFO
1327 * is empty
1328 */
1329 while (available && (fifo->head != fifo->tail)) {
1330 int i = fifo->tail;
1331 const uint32_t *ptr = cvmx_phys_to_ptr(fifo->entry[i].address);
1332 uint64_t csr_address = USB_FIFO_ADDRESS(fifo->entry[i].channel, usb->index) ^ 4;
1333 int words = available;
1334
1335 /* Limit the amount of data to waht the SW fifo has */
1336 if (fifo->entry[i].size <= available) {
1337 words = fifo->entry[i].size;
1338 fifo->tail++;
1339 if (fifo->tail > MAX_CHANNELS)
1340 fifo->tail = 0;
1341 }
1342
1343 /* Update the next locations and counts */
1344 available -= words;
1345 fifo->entry[i].address += words * 4;
1346 fifo->entry[i].size -= words;
1347
1348 /*
1349 * Write the HW fifo data. The read every three writes is due
1350 * to an errata on CN3XXX chips
1351 */
1352 while (words > 3) {
1353 cvmx_write64_uint32(csr_address, *ptr++);
1354 cvmx_write64_uint32(csr_address, *ptr++);
1355 cvmx_write64_uint32(csr_address, *ptr++);
1356 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
1357 words -= 3;
1358 }
1359 cvmx_write64_uint32(csr_address, *ptr++);
1360 if (--words) {
1361 cvmx_write64_uint32(csr_address, *ptr++);
1362 if (--words)
1363 cvmx_write64_uint32(csr_address, *ptr++);
1364 }
1365 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
1366 }
1367 return fifo->head != fifo->tail;
1368 }
1369
1370
1371 /**
1372 * Check the hardware FIFOs and fill them as needed
1373 *
1374 * @usb: USB device state populated by
1375 * cvmx_usb_initialize().
1376 */
1377 static void __cvmx_usb_poll_tx_fifo(struct cvmx_usb_internal_state *usb)
1378 {
1379 if (usb->periodic.head != usb->periodic.tail) {
1380 union cvmx_usbcx_hptxsts tx_status;
1381 tx_status.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPTXSTS(usb->index));
1382 if (__cvmx_usb_fill_tx_hw(usb, &usb->periodic, tx_status.s.ptxfspcavail))
1383 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk, ptxfempmsk, 1);
1384 else
1385 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk, ptxfempmsk, 0);
1386 }
1387
1388 if (usb->nonperiodic.head != usb->nonperiodic.tail) {
1389 union cvmx_usbcx_gnptxsts tx_status;
1390 tx_status.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GNPTXSTS(usb->index));
1391 if (__cvmx_usb_fill_tx_hw(usb, &usb->nonperiodic, tx_status.s.nptxfspcavail))
1392 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk, nptxfempmsk, 1);
1393 else
1394 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk, nptxfempmsk, 0);
1395 }
1396
1397 return;
1398 }
1399
1400
1401 /**
1402 * Fill the TX FIFO with an outgoing packet
1403 *
1404 * @usb: USB device state populated by
1405 * cvmx_usb_initialize().
1406 * @channel: Channel number to get packet from
1407 */
1408 static void __cvmx_usb_fill_tx_fifo(struct cvmx_usb_internal_state *usb, int channel)
1409 {
1410 union cvmx_usbcx_hccharx hcchar;
1411 union cvmx_usbcx_hcspltx usbc_hcsplt;
1412 union cvmx_usbcx_hctsizx usbc_hctsiz;
1413 struct cvmx_usb_tx_fifo *fifo;
1414
1415 /* We only need to fill data on outbound channels */
1416 hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index));
1417 if (hcchar.s.epdir != CVMX_USB_DIRECTION_OUT)
1418 return;
1419
1420 /* OUT Splits only have data on the start and not the complete */
1421 usbc_hcsplt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCSPLTX(channel, usb->index));
1422 if (usbc_hcsplt.s.spltena && usbc_hcsplt.s.compsplt)
1423 return;
1424
1425 /*
1426 * Find out how many bytes we need to fill and convert it into 32bit
1427 * words.
1428 */
1429 usbc_hctsiz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index));
1430 if (!usbc_hctsiz.s.xfersize)
1431 return;
1432
1433 if ((hcchar.s.eptype == CVMX_USB_TRANSFER_INTERRUPT) ||
1434 (hcchar.s.eptype == CVMX_USB_TRANSFER_ISOCHRONOUS))
1435 fifo = &usb->periodic;
1436 else
1437 fifo = &usb->nonperiodic;
1438
1439 fifo->entry[fifo->head].channel = channel;
1440 fifo->entry[fifo->head].address = __cvmx_usb_read_csr64(usb, CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8);
1441 fifo->entry[fifo->head].size = (usbc_hctsiz.s.xfersize+3)>>2;
1442 fifo->head++;
1443 if (fifo->head > MAX_CHANNELS)
1444 fifo->head = 0;
1445
1446 __cvmx_usb_poll_tx_fifo(usb);
1447
1448 return;
1449 }
1450
1451 /**
1452 * Perform channel specific setup for Control transactions. All
1453 * the generic stuff will already have been done in
1454 * __cvmx_usb_start_channel()
1455 *
1456 * @usb: USB device state populated by
1457 * cvmx_usb_initialize().
1458 * @channel: Channel to setup
1459 * @pipe: Pipe for control transaction
1460 */
1461 static void __cvmx_usb_start_channel_control(struct cvmx_usb_internal_state *usb,
1462 int channel,
1463 struct cvmx_usb_pipe *pipe)
1464 {
1465 struct cvmx_usb_transaction *transaction = pipe->head;
1466 union cvmx_usb_control_header *header =
1467 cvmx_phys_to_ptr(transaction->control_header);
1468 int bytes_to_transfer = transaction->buffer_length - transaction->actual_bytes;
1469 int packets_to_transfer;
1470 union cvmx_usbcx_hctsizx usbc_hctsiz;
1471
1472 usbc_hctsiz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index));
1473
1474 switch (transaction->stage) {
1475 case CVMX_USB_STAGE_NON_CONTROL:
1476 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE:
1477 cvmx_dprintf("%s: ERROR - Non control stage\n", __FUNCTION__);
1478 break;
1479 case CVMX_USB_STAGE_SETUP:
1480 usbc_hctsiz.s.pid = 3; /* Setup */
1481 bytes_to_transfer = sizeof(*header);
1482 /* All Control operations start with a setup going OUT */
1483 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), union cvmx_usbcx_hccharx, epdir, CVMX_USB_DIRECTION_OUT);
1484 /*
1485 * Setup send the control header instead of the buffer data. The
1486 * buffer data will be used in the next stage
1487 */
1488 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8, transaction->control_header);
1489 break;
1490 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE:
1491 usbc_hctsiz.s.pid = 3; /* Setup */
1492 bytes_to_transfer = 0;
1493 /* All Control operations start with a setup going OUT */
1494 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), union cvmx_usbcx_hccharx, epdir, CVMX_USB_DIRECTION_OUT);
1495 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), union cvmx_usbcx_hcspltx, compsplt, 1);
1496 break;
1497 case CVMX_USB_STAGE_DATA:
1498 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1499 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1500 if (header->s.request_type & 0x80)
1501 bytes_to_transfer = 0;
1502 else if (bytes_to_transfer > pipe->max_packet)
1503 bytes_to_transfer = pipe->max_packet;
1504 }
1505 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1506 union cvmx_usbcx_hccharx, epdir,
1507 ((header->s.request_type & 0x80) ?
1508 CVMX_USB_DIRECTION_IN :
1509 CVMX_USB_DIRECTION_OUT));
1510 break;
1511 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE:
1512 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1513 if (!(header->s.request_type & 0x80))
1514 bytes_to_transfer = 0;
1515 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1516 union cvmx_usbcx_hccharx, epdir,
1517 ((header->s.request_type & 0x80) ?
1518 CVMX_USB_DIRECTION_IN :
1519 CVMX_USB_DIRECTION_OUT));
1520 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), union cvmx_usbcx_hcspltx, compsplt, 1);
1521 break;
1522 case CVMX_USB_STAGE_STATUS:
1523 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1524 bytes_to_transfer = 0;
1525 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), union cvmx_usbcx_hccharx, epdir,
1526 ((header->s.request_type & 0x80) ?
1527 CVMX_USB_DIRECTION_OUT :
1528 CVMX_USB_DIRECTION_IN));
1529 break;
1530 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE:
1531 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1532 bytes_to_transfer = 0;
1533 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), union cvmx_usbcx_hccharx, epdir,
1534 ((header->s.request_type & 0x80) ?
1535 CVMX_USB_DIRECTION_OUT :
1536 CVMX_USB_DIRECTION_IN));
1537 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), union cvmx_usbcx_hcspltx, compsplt, 1);
1538 break;
1539 }
1540
1541 /*
1542 * Make sure the transfer never exceeds the byte limit of the hardware.
1543 * Further bytes will be sent as continued transactions
1544 */
1545 if (bytes_to_transfer > MAX_TRANSFER_BYTES) {
1546 /* Round MAX_TRANSFER_BYTES to a multiple of out packet size */
1547 bytes_to_transfer = MAX_TRANSFER_BYTES / pipe->max_packet;
1548 bytes_to_transfer *= pipe->max_packet;
1549 }
1550
1551 /*
1552 * Calculate the number of packets to transfer. If the length is zero
1553 * we still need to transfer one packet
1554 */
1555 packets_to_transfer = (bytes_to_transfer + pipe->max_packet - 1) / pipe->max_packet;
1556 if (packets_to_transfer == 0)
1557 packets_to_transfer = 1;
1558 else if ((packets_to_transfer > 1) && (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)) {
1559 /*
1560 * Limit to one packet when not using DMA. Channels must be
1561 * restarted between every packet for IN transactions, so there
1562 * is no reason to do multiple packets in a row
1563 */
1564 packets_to_transfer = 1;
1565 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1566 } else if (packets_to_transfer > MAX_TRANSFER_PACKETS) {
1567 /*
1568 * Limit the number of packet and data transferred to what the
1569 * hardware can handle
1570 */
1571 packets_to_transfer = MAX_TRANSFER_PACKETS;
1572 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1573 }
1574
1575 usbc_hctsiz.s.xfersize = bytes_to_transfer;
1576 usbc_hctsiz.s.pktcnt = packets_to_transfer;
1577
1578 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index), usbc_hctsiz.u32);
1579 return;
1580 }
1581
1582
1583 /**
1584 * Start a channel to perform the pipe's head transaction
1585 *
1586 * @usb: USB device state populated by
1587 * cvmx_usb_initialize().
1588 * @channel: Channel to setup
1589 * @pipe: Pipe to start
1590 */
1591 static void __cvmx_usb_start_channel(struct cvmx_usb_internal_state *usb,
1592 int channel,
1593 struct cvmx_usb_pipe *pipe)
1594 {
1595 struct cvmx_usb_transaction *transaction = pipe->head;
1596
1597 /* Make sure all writes to the DMA region get flushed */
1598 CVMX_SYNCW;
1599
1600 /* Attach the channel to the pipe */
1601 usb->pipe_for_channel[channel] = pipe;
1602 pipe->channel = channel;
1603 pipe->flags |= __CVMX_USB_PIPE_FLAGS_SCHEDULED;
1604
1605 /* Mark this channel as in use */
1606 usb->idle_hardware_channels &= ~(1<<channel);
1607
1608 /* Enable the channel interrupt bits */
1609 {
1610 union cvmx_usbcx_hcintx usbc_hcint;
1611 union cvmx_usbcx_hcintmskx usbc_hcintmsk;
1612 union cvmx_usbcx_haintmsk usbc_haintmsk;
1613
1614 /* Clear all channel status bits */
1615 usbc_hcint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCINTX(channel, usb->index));
1616 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTX(channel, usb->index), usbc_hcint.u32);
1617
1618 usbc_hcintmsk.u32 = 0;
1619 usbc_hcintmsk.s.chhltdmsk = 1;
1620 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) {
1621 /*
1622 * Channels need these extra interrupts when we aren't
1623 * in DMA mode.
1624 */
1625 usbc_hcintmsk.s.datatglerrmsk = 1;
1626 usbc_hcintmsk.s.frmovrunmsk = 1;
1627 usbc_hcintmsk.s.bblerrmsk = 1;
1628 usbc_hcintmsk.s.xacterrmsk = 1;
1629 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1630 /*
1631 * Splits don't generate xfercompl, so we need
1632 * ACK and NYET.
1633 */
1634 usbc_hcintmsk.s.nyetmsk = 1;
1635 usbc_hcintmsk.s.ackmsk = 1;
1636 }
1637 usbc_hcintmsk.s.nakmsk = 1;
1638 usbc_hcintmsk.s.stallmsk = 1;
1639 usbc_hcintmsk.s.xfercomplmsk = 1;
1640 }
1641 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), usbc_hcintmsk.u32);
1642
1643 /* Enable the channel interrupt to propagate */
1644 usbc_haintmsk.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HAINTMSK(usb->index));
1645 usbc_haintmsk.s.haintmsk |= 1<<channel;
1646 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HAINTMSK(usb->index), usbc_haintmsk.u32);
1647 }
1648
1649 /* Setup the locations the DMA engines use */
1650 {
1651 uint64_t dma_address = transaction->buffer + transaction->actual_bytes;
1652 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
1653 dma_address = transaction->buffer + transaction->iso_packets[0].offset + transaction->actual_bytes;
1654 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8, dma_address);
1655 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8, dma_address);
1656 }
1657
1658 /* Setup both the size of the transfer and the SPLIT characteristics */
1659 {
1660 union cvmx_usbcx_hcspltx usbc_hcsplt = {.u32 = 0};
1661 union cvmx_usbcx_hctsizx usbc_hctsiz = {.u32 = 0};
1662 int packets_to_transfer;
1663 int bytes_to_transfer = transaction->buffer_length - transaction->actual_bytes;
1664
1665 /*
1666 * ISOCHRONOUS transactions store each individual transfer size
1667 * in the packet structure, not the global buffer_length
1668 */
1669 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
1670 bytes_to_transfer = transaction->iso_packets[0].length - transaction->actual_bytes;
1671
1672 /*
1673 * We need to do split transactions when we are talking to non
1674 * high speed devices that are behind a high speed hub
1675 */
1676 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1677 /*
1678 * On the start split phase (stage is even) record the
1679 * frame number we will need to send the split complete.
1680 * We only store the lower two bits since the time ahead
1681 * can only be two frames
1682 */
1683 if ((transaction->stage&1) == 0) {
1684 if (transaction->type == CVMX_USB_TRANSFER_BULK)
1685 pipe->split_sc_frame = (usb->frame_number + 1) & 0x7f;
1686 else
1687 pipe->split_sc_frame = (usb->frame_number + 2) & 0x7f;
1688 } else
1689 pipe->split_sc_frame = -1;
1690
1691 usbc_hcsplt.s.spltena = 1;
1692 usbc_hcsplt.s.hubaddr = pipe->hub_device_addr;
1693 usbc_hcsplt.s.prtaddr = pipe->hub_port;
1694 usbc_hcsplt.s.compsplt = (transaction->stage == CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE);
1695
1696 /*
1697 * SPLIT transactions can only ever transmit one data
1698 * packet so limit the transfer size to the max packet
1699 * size
1700 */
1701 if (bytes_to_transfer > pipe->max_packet)
1702 bytes_to_transfer = pipe->max_packet;
1703
1704 /*
1705 * ISOCHRONOUS OUT splits are unique in that they limit
1706 * data transfers to 188 byte chunks representing the
1707 * begin/middle/end of the data or all
1708 */
1709 if (!usbc_hcsplt.s.compsplt &&
1710 (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) &&
1711 (pipe->transfer_type == CVMX_USB_TRANSFER_ISOCHRONOUS)) {
1712 /*
1713 * Clear the split complete frame number as
1714 * there isn't going to be a split complete
1715 */
1716 pipe->split_sc_frame = -1;
1717 /*
1718 * See if we've started this transfer and sent
1719 * data
1720 */
1721 if (transaction->actual_bytes == 0) {
1722 /*
1723 * Nothing sent yet, this is either a
1724 * begin or the entire payload
1725 */
1726 if (bytes_to_transfer <= 188)
1727 /* Entire payload in one go */
1728 usbc_hcsplt.s.xactpos = 3;
1729 else
1730 /* First part of payload */
1731 usbc_hcsplt.s.xactpos = 2;
1732 } else {
1733 /*
1734 * Continuing the previous data, we must
1735 * either be in the middle or at the end
1736 */
1737 if (bytes_to_transfer <= 188)
1738 /* End of payload */
1739 usbc_hcsplt.s.xactpos = 1;
1740 else
1741 /* Middle of payload */
1742 usbc_hcsplt.s.xactpos = 0;
1743 }
1744 /*
1745 * Again, the transfer size is limited to 188
1746 * bytes
1747 */
1748 if (bytes_to_transfer > 188)
1749 bytes_to_transfer = 188;
1750 }
1751 }
1752
1753 /*
1754 * Make sure the transfer never exceeds the byte limit of the
1755 * hardware. Further bytes will be sent as continued
1756 * transactions
1757 */
1758 if (bytes_to_transfer > MAX_TRANSFER_BYTES) {
1759 /*
1760 * Round MAX_TRANSFER_BYTES to a multiple of out packet
1761 * size
1762 */
1763 bytes_to_transfer = MAX_TRANSFER_BYTES / pipe->max_packet;
1764 bytes_to_transfer *= pipe->max_packet;
1765 }
1766
1767 /*
1768 * Calculate the number of packets to transfer. If the length is
1769 * zero we still need to transfer one packet
1770 */
1771 packets_to_transfer = (bytes_to_transfer + pipe->max_packet - 1) / pipe->max_packet;
1772 if (packets_to_transfer == 0)
1773 packets_to_transfer = 1;
1774 else if ((packets_to_transfer > 1) && (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)) {
1775 /*
1776 * Limit to one packet when not using DMA. Channels must
1777 * be restarted between every packet for IN
1778 * transactions, so there is no reason to do multiple
1779 * packets in a row
1780 */
1781 packets_to_transfer = 1;
1782 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1783 } else if (packets_to_transfer > MAX_TRANSFER_PACKETS) {
1784 /*
1785 * Limit the number of packet and data transferred to
1786 * what the hardware can handle
1787 */
1788 packets_to_transfer = MAX_TRANSFER_PACKETS;
1789 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1790 }
1791
1792 usbc_hctsiz.s.xfersize = bytes_to_transfer;
1793 usbc_hctsiz.s.pktcnt = packets_to_transfer;
1794
1795 /* Update the DATA0/DATA1 toggle */
1796 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1797 /*
1798 * High speed pipes may need a hardware ping before they start
1799 */
1800 if (pipe->flags & __CVMX_USB_PIPE_FLAGS_NEED_PING)
1801 usbc_hctsiz.s.dopng = 1;
1802
1803 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCSPLTX(channel, usb->index), usbc_hcsplt.u32);
1804 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index), usbc_hctsiz.u32);
1805 }
1806
1807 /* Setup the Host Channel Characteristics Register */
1808 {
1809 union cvmx_usbcx_hccharx usbc_hcchar = {.u32 = 0};
1810
1811 /*
1812 * Set the startframe odd/even properly. This is only used for
1813 * periodic
1814 */
1815 usbc_hcchar.s.oddfrm = usb->frame_number&1;
1816
1817 /*
1818 * Set the number of back to back packets allowed by this
1819 * endpoint. Split transactions interpret "ec" as the number of
1820 * immediate retries of failure. These retries happen too
1821 * quickly, so we disable these entirely for splits
1822 */
1823 if (__cvmx_usb_pipe_needs_split(usb, pipe))
1824 usbc_hcchar.s.ec = 1;
1825 else if (pipe->multi_count < 1)
1826 usbc_hcchar.s.ec = 1;
1827 else if (pipe->multi_count > 3)
1828 usbc_hcchar.s.ec = 3;
1829 else
1830 usbc_hcchar.s.ec = pipe->multi_count;
1831
1832 /* Set the rest of the endpoint specific settings */
1833 usbc_hcchar.s.devaddr = pipe->device_addr;
1834 usbc_hcchar.s.eptype = transaction->type;
1835 usbc_hcchar.s.lspddev = (pipe->device_speed == CVMX_USB_SPEED_LOW);
1836 usbc_hcchar.s.epdir = pipe->transfer_dir;
1837 usbc_hcchar.s.epnum = pipe->endpoint_num;
1838 usbc_hcchar.s.mps = pipe->max_packet;
1839 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index), usbc_hcchar.u32);
1840 }
1841
1842 /* Do transaction type specific fixups as needed */
1843 switch (transaction->type) {
1844 case CVMX_USB_TRANSFER_CONTROL:
1845 __cvmx_usb_start_channel_control(usb, channel, pipe);
1846 break;
1847 case CVMX_USB_TRANSFER_BULK:
1848 case CVMX_USB_TRANSFER_INTERRUPT:
1849 break;
1850 case CVMX_USB_TRANSFER_ISOCHRONOUS:
1851 if (!__cvmx_usb_pipe_needs_split(usb, pipe)) {
1852 /*
1853 * ISO transactions require different PIDs depending on
1854 * direction and how many packets are needed
1855 */
1856 if (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) {
1857 if (pipe->multi_count < 2) /* Need DATA0 */
1858 USB_SET_FIELD32(CVMX_USBCX_HCTSIZX(channel, usb->index), union cvmx_usbcx_hctsizx, pid, 0);
1859 else /* Need MDATA */
1860 USB_SET_FIELD32(CVMX_USBCX_HCTSIZX(channel, usb->index), union cvmx_usbcx_hctsizx, pid, 3);
1861 }
1862 }
1863 break;
1864 }
1865 {
1866 union cvmx_usbcx_hctsizx usbc_hctsiz = {.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index))};
1867 transaction->xfersize = usbc_hctsiz.s.xfersize;
1868 transaction->pktcnt = usbc_hctsiz.s.pktcnt;
1869 }
1870 /* Remeber when we start a split transaction */
1871 if (__cvmx_usb_pipe_needs_split(usb, pipe))
1872 usb->active_split = transaction;
1873 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), union cvmx_usbcx_hccharx, chena, 1);
1874 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
1875 __cvmx_usb_fill_tx_fifo(usb, channel);
1876 return;
1877 }
1878
1879
1880 /**
1881 * Find a pipe that is ready to be scheduled to hardware.
1882 * @usb: USB device state populated by
1883 * cvmx_usb_initialize().
1884 * @list: Pipe list to search
1885 * @current_frame:
1886 * Frame counter to use as a time reference.
1887 *
1888 * Returns: Pipe or NULL if none are ready
1889 */
1890 static struct cvmx_usb_pipe *__cvmx_usb_find_ready_pipe(struct cvmx_usb_internal_state *usb, struct cvmx_usb_pipe_list *list, uint64_t current_frame)
1891 {
1892 struct cvmx_usb_pipe *pipe = list->head;
1893 while (pipe) {
1894 if (!(pipe->flags & __CVMX_USB_PIPE_FLAGS_SCHEDULED) && pipe->head &&
1895 (pipe->next_tx_frame <= current_frame) &&
1896 ((pipe->split_sc_frame == -1) || ((((int)current_frame - (int)pipe->split_sc_frame) & 0x7f) < 0x40)) &&
1897 (!usb->active_split || (usb->active_split == pipe->head))) {
1898 CVMX_PREFETCH(pipe, 128);
1899 CVMX_PREFETCH(pipe->head, 0);
1900 return pipe;
1901 }
1902 pipe = pipe->next;
1903 }
1904 return NULL;
1905 }
1906
1907
1908 /**
1909 * Called whenever a pipe might need to be scheduled to the
1910 * hardware.
1911 *
1912 * @usb: USB device state populated by
1913 * cvmx_usb_initialize().
1914 * @is_sof: True if this schedule was called on a SOF interrupt.
1915 */
1916 static void __cvmx_usb_schedule(struct cvmx_usb_internal_state *usb, int is_sof)
1917 {
1918 int channel;
1919 struct cvmx_usb_pipe *pipe;
1920 int need_sof;
1921 enum cvmx_usb_transfer ttype;
1922
1923 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) {
1924 /*
1925 * Without DMA we need to be careful to not schedule something
1926 * at the end of a frame and cause an overrun.
1927 */
1928 union cvmx_usbcx_hfnum hfnum = {.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index))};
1929 union cvmx_usbcx_hfir hfir = {.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFIR(usb->index))};
1930 if (hfnum.s.frrem < hfir.s.frint/4)
1931 goto done;
1932 }
1933
1934 while (usb->idle_hardware_channels) {
1935 /* Find an idle channel */
1936 channel = __fls(usb->idle_hardware_channels);
1937 if (unlikely(channel > 7))
1938 break;
1939
1940 /* Find a pipe needing service */
1941 pipe = NULL;
1942 if (is_sof) {
1943 /*
1944 * Only process periodic pipes on SOF interrupts. This
1945 * way we are sure that the periodic data is sent in the
1946 * beginning of the frame
1947 */
1948 pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_ISOCHRONOUS, usb->frame_number);
1949 if (likely(!pipe))
1950 pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_INTERRUPT, usb->frame_number);
1951 }
1952 if (likely(!pipe)) {
1953 pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_CONTROL, usb->frame_number);
1954 if (likely(!pipe))
1955 pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_BULK, usb->frame_number);
1956 }
1957 if (!pipe)
1958 break;
1959
1960 __cvmx_usb_start_channel(usb, channel, pipe);
1961 }
1962
1963 done:
1964 /*
1965 * Only enable SOF interrupts when we have transactions pending in the
1966 * future that might need to be scheduled
1967 */
1968 need_sof = 0;
1969 for (ttype = CVMX_USB_TRANSFER_CONTROL; ttype <= CVMX_USB_TRANSFER_INTERRUPT; ttype++) {
1970 pipe = usb->active_pipes[ttype].head;
1971 while (pipe) {
1972 if (pipe->next_tx_frame > usb->frame_number) {
1973 need_sof = 1;
1974 break;
1975 }
1976 pipe = pipe->next;
1977 }
1978 }
1979 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk, sofmsk, need_sof);
1980 return;
1981 }
1982
1983
1984 /**
1985 * Call a user's callback for a specific reason.
1986 *
1987 * @usb: USB device state populated by
1988 * cvmx_usb_initialize().
1989 * @pipe: Pipe the callback is for or NULL
1990 * @transaction:
1991 * Transaction the callback is for or NULL
1992 * @reason: Reason this callback is being called
1993 * @complete_code:
1994 * Completion code for the transaction, if any
1995 */
1996 static void __cvmx_usb_perform_callback(struct cvmx_usb_internal_state *usb,
1997 struct cvmx_usb_pipe *pipe,
1998 struct cvmx_usb_transaction *transaction,
1999 enum cvmx_usb_callback reason,
2000 enum cvmx_usb_complete complete_code)
2001 {
2002 cvmx_usb_callback_func_t callback = usb->callback[reason];
2003 void *user_data = usb->callback_data[reason];
2004 int submit_handle = -1;
2005 int pipe_handle = -1;
2006 int bytes_transferred = 0;
2007
2008 if (pipe)
2009 pipe_handle = __cvmx_usb_get_pipe_handle(usb, pipe);
2010
2011 if (transaction) {
2012 submit_handle = __cvmx_usb_get_submit_handle(usb, transaction);
2013 bytes_transferred = transaction->actual_bytes;
2014 /* Transactions are allowed to override the default callback */
2015 if ((reason == CVMX_USB_CALLBACK_TRANSFER_COMPLETE) && transaction->callback) {
2016 callback = transaction->callback;
2017 user_data = transaction->callback_data;
2018 }
2019 }
2020
2021 if (!callback)
2022 return;
2023
2024 callback((struct cvmx_usb_state *)usb, reason, complete_code, pipe_handle, submit_handle,
2025 bytes_transferred, user_data);
2026 }
2027
2028
2029 /**
2030 * Signal the completion of a transaction and free it. The
2031 * transaction will be removed from the pipe transaction list.
2032 *
2033 * @usb: USB device state populated by
2034 * cvmx_usb_initialize().
2035 * @pipe: Pipe the transaction is on
2036 * @transaction:
2037 * Transaction that completed
2038 * @complete_code:
2039 * Completion code
2040 */
2041 static void __cvmx_usb_perform_complete(struct cvmx_usb_internal_state *usb,
2042 struct cvmx_usb_pipe *pipe,
2043 struct cvmx_usb_transaction *transaction,
2044 enum cvmx_usb_complete complete_code)
2045 {
2046 /* If this was a split then clear our split in progress marker */
2047 if (usb->active_split == transaction)
2048 usb->active_split = NULL;
2049
2050 /*
2051 * Isochronous transactions need extra processing as they might not be
2052 * done after a single data transfer
2053 */
2054 if (unlikely(transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)) {
2055 /* Update the number of bytes transferred in this ISO packet */
2056 transaction->iso_packets[0].length = transaction->actual_bytes;
2057 transaction->iso_packets[0].status = complete_code;
2058
2059 /*
2060 * If there are more ISOs pending and we succeeded, schedule the
2061 * next one
2062 */
2063 if ((transaction->iso_number_packets > 1) && (complete_code == CVMX_USB_COMPLETE_SUCCESS)) {
2064 /* No bytes transferred for this packet as of yet */
2065 transaction->actual_bytes = 0;
2066 /* One less ISO waiting to transfer */
2067 transaction->iso_number_packets--;
2068 /* Increment to the next location in our packet array */
2069 transaction->iso_packets++;
2070 transaction->stage = CVMX_USB_STAGE_NON_CONTROL;
2071 goto done;
2072 }
2073 }
2074
2075 /* Remove the transaction from the pipe list */
2076 if (transaction->next)
2077 transaction->next->prev = transaction->prev;
2078 else
2079 pipe->tail = transaction->prev;
2080 if (transaction->prev)
2081 transaction->prev->next = transaction->next;
2082 else
2083 pipe->head = transaction->next;
2084 if (!pipe->head) {
2085 __cvmx_usb_remove_pipe(usb->active_pipes + pipe->transfer_type, pipe);
2086 __cvmx_usb_append_pipe(&usb->idle_pipes, pipe);
2087
2088 }
2089 __cvmx_usb_perform_callback(usb, pipe, transaction,
2090 CVMX_USB_CALLBACK_TRANSFER_COMPLETE,
2091 complete_code);
2092 __cvmx_usb_free_transaction(usb, transaction);
2093 done:
2094 return;
2095 }
2096
2097
2098 /**
2099 * Submit a usb transaction to a pipe. Called for all types
2100 * of transactions.
2101 *
2102 * @usb:
2103 * @pipe_handle:
2104 * Which pipe to submit to. Will be validated in this function.
2105 * @type: Transaction type
2106 * @buffer: User buffer for the transaction
2107 * @buffer_length:
2108 * User buffer's length in bytes
2109 * @control_header:
2110 * For control transactions, the 8 byte standard header
2111 * @iso_start_frame:
2112 * For ISO transactions, the start frame
2113 * @iso_number_packets:
2114 * For ISO, the number of packet in the transaction.
2115 * @iso_packets:
2116 * A description of each ISO packet
2117 * @callback: User callback to call when the transaction completes
2118 * @user_data: User's data for the callback
2119 *
2120 * Returns: Submit handle or negative on failure. Matches the result
2121 * in the external API.
2122 */
2123 static int __cvmx_usb_submit_transaction(struct cvmx_usb_internal_state *usb,
2124 int pipe_handle,
2125 enum cvmx_usb_transfer type,
2126 uint64_t buffer,
2127 int buffer_length,
2128 uint64_t control_header,
2129 int iso_start_frame,
2130 int iso_number_packets,
2131 struct cvmx_usb_iso_packet *iso_packets,
2132 cvmx_usb_callback_func_t callback,
2133 void *user_data)
2134 {
2135 int submit_handle;
2136 struct cvmx_usb_transaction *transaction;
2137 struct cvmx_usb_pipe *pipe = usb->pipe + pipe_handle;
2138
2139 if (unlikely((pipe_handle < 0) || (pipe_handle >= MAX_PIPES)))
2140 return -EINVAL;
2141 /* Fail if the pipe isn't open */
2142 if (unlikely((pipe->flags & __CVMX_USB_PIPE_FLAGS_OPEN) == 0))
2143 return -EINVAL;
2144 if (unlikely(pipe->transfer_type != type))
2145 return -EINVAL;
2146
2147 transaction = __cvmx_usb_alloc_transaction(usb);
2148 if (unlikely(!transaction))
2149 return -ENOMEM;
2150
2151 transaction->type = type;
2152 transaction->buffer = buffer;
2153 transaction->buffer_length = buffer_length;
2154 transaction->control_header = control_header;
2155 /* FIXME: This is not used, implement it. */
2156 transaction->iso_start_frame = iso_start_frame;
2157 transaction->iso_number_packets = iso_number_packets;
2158 transaction->iso_packets = iso_packets;
2159 transaction->callback = callback;
2160 transaction->callback_data = user_data;
2161 if (transaction->type == CVMX_USB_TRANSFER_CONTROL)
2162 transaction->stage = CVMX_USB_STAGE_SETUP;
2163 else
2164 transaction->stage = CVMX_USB_STAGE_NON_CONTROL;
2165
2166 transaction->next = NULL;
2167 if (pipe->tail) {
2168 transaction->prev = pipe->tail;
2169 transaction->prev->next = transaction;
2170 } else {
2171 if (pipe->next_tx_frame < usb->frame_number)
2172 pipe->next_tx_frame = usb->frame_number + pipe->interval -
2173 (usb->frame_number - pipe->next_tx_frame) % pipe->interval;
2174 transaction->prev = NULL;
2175 pipe->head = transaction;
2176 __cvmx_usb_remove_pipe(&usb->idle_pipes, pipe);
2177 __cvmx_usb_append_pipe(usb->active_pipes + pipe->transfer_type, pipe);
2178 }
2179 pipe->tail = transaction;
2180
2181 submit_handle = __cvmx_usb_get_submit_handle(usb, transaction);
2182
2183 /* We may need to schedule the pipe if this was the head of the pipe */
2184 if (!transaction->prev)
2185 __cvmx_usb_schedule(usb, 0);
2186
2187 return submit_handle;
2188 }
2189
2190
2191 /**
2192 * Call to submit a USB Bulk transfer to a pipe.
2193 *
2194 * @state: USB device state populated by
2195 * cvmx_usb_initialize().
2196 * @pipe_handle:
2197 * Handle to the pipe for the transfer.
2198 * @buffer: Physical address of the data buffer in
2199 * memory. Note that this is NOT A POINTER, but
2200 * the full 64bit physical address of the
2201 * buffer. This may be zero if buffer_length is
2202 * zero.
2203 * @buffer_length:
2204 * Length of buffer in bytes.
2205 * @callback: Function to call when this transaction
2206 * completes. If the return value of this
2207 * function isn't an error, then this function
2208 * is guaranteed to be called when the
2209 * transaction completes. If this parameter is
2210 * NULL, then the generic callback registered
2211 * through cvmx_usb_register_callback is
2212 * called. If both are NULL, then there is no
2213 * way to know when a transaction completes.
2214 * @user_data: User supplied data returned when the
2215 * callback is called. This is only used if
2216 * callback in not NULL.
2217 *
2218 * Returns: A submitted transaction handle or negative on
2219 * failure. Negative values are error codes.
2220 */
2221 int cvmx_usb_submit_bulk(struct cvmx_usb_state *state, int pipe_handle,
2222 uint64_t buffer, int buffer_length,
2223 cvmx_usb_callback_func_t callback,
2224 void *user_data)
2225 {
2226 int submit_handle;
2227 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
2228
2229 /* Pipe handle checking is done later in a common place */
2230 if (unlikely(!buffer))
2231 return -EINVAL;
2232 if (unlikely(buffer_length < 0))
2233 return -EINVAL;
2234
2235 submit_handle = __cvmx_usb_submit_transaction(usb, pipe_handle,
2236 CVMX_USB_TRANSFER_BULK,
2237 buffer,
2238 buffer_length,
2239 0, /* control_header */
2240 0, /* iso_start_frame */
2241 0, /* iso_number_packets */
2242 NULL, /* iso_packets */
2243 callback,
2244 user_data);
2245 return submit_handle;
2246 }
2247
2248
2249 /**
2250 * Call to submit a USB Interrupt transfer to a pipe.
2251 *
2252 * @state: USB device state populated by
2253 * cvmx_usb_initialize().
2254 * @pipe_handle:
2255 * Handle to the pipe for the transfer.
2256 * @buffer: Physical address of the data buffer in
2257 * memory. Note that this is NOT A POINTER, but
2258 * the full 64bit physical address of the
2259 * buffer. This may be zero if buffer_length is
2260 * zero.
2261 * @buffer_length:
2262 * Length of buffer in bytes.
2263 * @callback: Function to call when this transaction
2264 * completes. If the return value of this
2265 * function isn't an error, then this function
2266 * is guaranteed to be called when the
2267 * transaction completes. If this parameter is
2268 * NULL, then the generic callback registered
2269 * through cvmx_usb_register_callback is
2270 * called. If both are NULL, then there is no
2271 * way to know when a transaction completes.
2272 * @user_data: User supplied data returned when the
2273 * callback is called. This is only used if
2274 * callback in not NULL.
2275 *
2276 * Returns: A submitted transaction handle or negative on
2277 * failure. Negative values are error codes.
2278 */
2279 int cvmx_usb_submit_interrupt(struct cvmx_usb_state *state, int pipe_handle,
2280 uint64_t buffer, int buffer_length,
2281 cvmx_usb_callback_func_t callback,
2282 void *user_data)
2283 {
2284 int submit_handle;
2285 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
2286
2287 /* Pipe handle checking is done later in a common place */
2288 if (unlikely(!buffer))
2289 return -EINVAL;
2290 if (unlikely(buffer_length < 0))
2291 return -EINVAL;
2292
2293 submit_handle = __cvmx_usb_submit_transaction(usb, pipe_handle,
2294 CVMX_USB_TRANSFER_INTERRUPT,
2295 buffer,
2296 buffer_length,
2297 0, /* control_header */
2298 0, /* iso_start_frame */
2299 0, /* iso_number_packets */
2300 NULL, /* iso_packets */
2301 callback,
2302 user_data);
2303 return submit_handle;
2304 }
2305
2306
2307 /**
2308 * Call to submit a USB Control transfer to a pipe.
2309 *
2310 * @state: USB device state populated by
2311 * cvmx_usb_initialize().
2312 * @pipe_handle:
2313 * Handle to the pipe for the transfer.
2314 * @control_header:
2315 * USB 8 byte control header physical address.
2316 * Note that this is NOT A POINTER, but the
2317 * full 64bit physical address of the buffer.
2318 * @buffer: Physical address of the data buffer in
2319 * memory. Note that this is NOT A POINTER, but
2320 * the full 64bit physical address of the
2321 * buffer. This may be zero if buffer_length is
2322 * zero.
2323 * @buffer_length:
2324 * Length of buffer in bytes.
2325 * @callback: Function to call when this transaction
2326 * completes. If the return value of this
2327 * function isn't an error, then this function
2328 * is guaranteed to be called when the
2329 * transaction completes. If this parameter is
2330 * NULL, then the generic callback registered
2331 * through cvmx_usb_register_callback is
2332 * called. If both are NULL, then there is no
2333 * way to know when a transaction completes.
2334 * @user_data: User supplied data returned when the
2335 * callback is called. This is only used if
2336 * callback in not NULL.
2337 *
2338 * Returns: A submitted transaction handle or negative on
2339 * failure. Negative values are error codes.
2340 */
2341 int cvmx_usb_submit_control(struct cvmx_usb_state *state, int pipe_handle,
2342 uint64_t control_header,
2343 uint64_t buffer, int buffer_length,
2344 cvmx_usb_callback_func_t callback,
2345 void *user_data)
2346 {
2347 int submit_handle;
2348 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
2349 union cvmx_usb_control_header *header =
2350 cvmx_phys_to_ptr(control_header);
2351
2352 /* Pipe handle checking is done later in a common place */
2353 if (unlikely(!control_header))
2354 return -EINVAL;
2355 /* Some drivers send a buffer with a zero length. God only knows why */
2356 if (unlikely(buffer && (buffer_length < 0)))
2357 return -EINVAL;
2358 if (unlikely(!buffer && (buffer_length != 0)))
2359 return -EINVAL;
2360 if ((header->s.request_type & 0x80) == 0)
2361 buffer_length = le16_to_cpu(header->s.length);
2362
2363 submit_handle = __cvmx_usb_submit_transaction(usb, pipe_handle,
2364 CVMX_USB_TRANSFER_CONTROL,
2365 buffer,
2366 buffer_length,
2367 control_header,
2368 0, /* iso_start_frame */
2369 0, /* iso_number_packets */
2370 NULL, /* iso_packets */
2371 callback,
2372 user_data);
2373 return submit_handle;
2374 }
2375
2376
2377 /**
2378 * Call to submit a USB Isochronous transfer to a pipe.
2379 *
2380 * @state: USB device state populated by
2381 * cvmx_usb_initialize().
2382 * @pipe_handle:
2383 * Handle to the pipe for the transfer.
2384 * @start_frame:
2385 * Number of frames into the future to schedule
2386 * this transaction.
2387 * @number_packets:
2388 * Number of sequential packets to transfer.
2389 * "packets" is a pointer to an array of this
2390 * many packet structures.
2391 * @packets: Description of each transfer packet as
2392 * defined by struct cvmx_usb_iso_packet. The array
2393 * pointed to here must stay valid until the
2394 * complete callback is called.
2395 * @buffer: Physical address of the data buffer in
2396 * memory. Note that this is NOT A POINTER, but
2397 * the full 64bit physical address of the
2398 * buffer. This may be zero if buffer_length is
2399 * zero.
2400 * @buffer_length:
2401 * Length of buffer in bytes.
2402 * @callback: Function to call when this transaction
2403 * completes. If the return value of this
2404 * function isn't an error, then this function
2405 * is guaranteed to be called when the
2406 * transaction completes. If this parameter is
2407 * NULL, then the generic callback registered
2408 * through cvmx_usb_register_callback is
2409 * called. If both are NULL, then there is no
2410 * way to know when a transaction completes.
2411 * @user_data: User supplied data returned when the
2412 * callback is called. This is only used if
2413 * callback in not NULL.
2414 *
2415 * Returns: A submitted transaction handle or negative on
2416 * failure. Negative values are error codes.
2417 */
2418 int cvmx_usb_submit_isochronous(struct cvmx_usb_state *state, int pipe_handle,
2419 int start_frame,
2420 int number_packets,
2421 struct cvmx_usb_iso_packet packets[],
2422 uint64_t buffer, int buffer_length,
2423 cvmx_usb_callback_func_t callback,
2424 void *user_data)
2425 {
2426 int submit_handle;
2427 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
2428
2429 /* Pipe handle checking is done later in a common place */
2430 if (unlikely(start_frame < 0))
2431 return -EINVAL;
2432 if (unlikely(number_packets < 1))
2433 return -EINVAL;
2434 if (unlikely(!packets))
2435 return -EINVAL;
2436 if (unlikely(!buffer))
2437 return -EINVAL;
2438 if (unlikely(buffer_length < 0))
2439 return -EINVAL;
2440
2441 submit_handle = __cvmx_usb_submit_transaction(usb, pipe_handle,
2442 CVMX_USB_TRANSFER_ISOCHRONOUS,
2443 buffer,
2444 buffer_length,
2445 0, /* control_header */
2446 start_frame,
2447 number_packets,
2448 packets,
2449 callback,
2450 user_data);
2451 return submit_handle;
2452 }
2453
2454
2455 /**
2456 * Cancel one outstanding request in a pipe. Canceling a request
2457 * can fail if the transaction has already completed before cancel
2458 * is called. Even after a successful cancel call, it may take
2459 * a frame or two for the cvmx_usb_poll() function to call the
2460 * associated callback.
2461 *
2462 * @state: USB device state populated by
2463 * cvmx_usb_initialize().
2464 * @pipe_handle:
2465 * Pipe handle to cancel requests in.
2466 * @submit_handle:
2467 * Handle to transaction to cancel, returned by the submit
2468 * function.
2469 *
2470 * Returns: 0 or a negative error code.
2471 */
2472 int cvmx_usb_cancel(struct cvmx_usb_state *state, int pipe_handle, int submit_handle)
2473 {
2474 struct cvmx_usb_transaction *transaction;
2475 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
2476 struct cvmx_usb_pipe *pipe = usb->pipe + pipe_handle;
2477
2478 if (unlikely((pipe_handle < 0) || (pipe_handle >= MAX_PIPES)))
2479 return -EINVAL;
2480 if (unlikely((submit_handle < 0) || (submit_handle >= MAX_TRANSACTIONS)))
2481 return -EINVAL;
2482
2483 /* Fail if the pipe isn't open */
2484 if (unlikely((pipe->flags & __CVMX_USB_PIPE_FLAGS_OPEN) == 0))
2485 return -EINVAL;
2486
2487 transaction = usb->transaction + submit_handle;
2488
2489 /* Fail if this transaction already completed */
2490 if (unlikely((transaction->flags & __CVMX_USB_TRANSACTION_FLAGS_IN_USE) == 0))
2491 return -EINVAL;
2492
2493 /*
2494 * If the transaction is the HEAD of the queue and scheduled. We need to
2495 * treat it special
2496 */
2497 if ((pipe->head == transaction) &&
2498 (pipe->flags & __CVMX_USB_PIPE_FLAGS_SCHEDULED)) {
2499 union cvmx_usbcx_hccharx usbc_hcchar;
2500
2501 usb->pipe_for_channel[pipe->channel] = NULL;
2502 pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_SCHEDULED;
2503
2504 CVMX_SYNCW;
2505
2506 usbc_hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(pipe->channel, usb->index));
2507 /*
2508 * If the channel isn't enabled then the transaction already
2509 * completed.
2510 */
2511 if (usbc_hcchar.s.chena) {
2512 usbc_hcchar.s.chdis = 1;
2513 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(pipe->channel, usb->index), usbc_hcchar.u32);
2514 }
2515 }
2516 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_CANCEL);
2517 return 0;
2518 }
2519
2520
2521 /**
2522 * Cancel all outstanding requests in a pipe. Logically all this
2523 * does is call cvmx_usb_cancel() in a loop.
2524 *
2525 * @state: USB device state populated by
2526 * cvmx_usb_initialize().
2527 * @pipe_handle:
2528 * Pipe handle to cancel requests in.
2529 *
2530 * Returns: 0 or a negative error code.
2531 */
2532 int cvmx_usb_cancel_all(struct cvmx_usb_state *state, int pipe_handle)
2533 {
2534 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
2535 struct cvmx_usb_pipe *pipe = usb->pipe + pipe_handle;
2536
2537 if (unlikely((pipe_handle < 0) || (pipe_handle >= MAX_PIPES)))
2538 return -EINVAL;
2539
2540 /* Fail if the pipe isn't open */
2541 if (unlikely((pipe->flags & __CVMX_USB_PIPE_FLAGS_OPEN) == 0))
2542 return -EINVAL;
2543
2544 /* Simply loop through and attempt to cancel each transaction */
2545 while (pipe->head) {
2546 int result = cvmx_usb_cancel(state, pipe_handle,
2547 __cvmx_usb_get_submit_handle(usb, pipe->head));
2548 if (unlikely(result != 0))
2549 return result;
2550 }
2551 return 0;
2552 }
2553
2554
2555 /**
2556 * Close a pipe created with cvmx_usb_open_pipe().
2557 *
2558 * @state: USB device state populated by
2559 * cvmx_usb_initialize().
2560 * @pipe_handle:
2561 * Pipe handle to close.
2562 *
2563 * Returns: 0 or a negative error code. EBUSY is returned if the pipe has
2564 * outstanding transfers.
2565 */
2566 int cvmx_usb_close_pipe(struct cvmx_usb_state *state, int pipe_handle)
2567 {
2568 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
2569 struct cvmx_usb_pipe *pipe = usb->pipe + pipe_handle;
2570
2571 if (unlikely((pipe_handle < 0) || (pipe_handle >= MAX_PIPES)))
2572 return -EINVAL;
2573
2574 /* Fail if the pipe isn't open */
2575 if (unlikely((pipe->flags & __CVMX_USB_PIPE_FLAGS_OPEN) == 0))
2576 return -EINVAL;
2577
2578 /* Fail if the pipe has pending transactions */
2579 if (unlikely(pipe->head))
2580 return -EBUSY;
2581
2582 pipe->flags = 0;
2583 __cvmx_usb_remove_pipe(&usb->idle_pipes, pipe);
2584 __cvmx_usb_append_pipe(&usb->free_pipes, pipe);
2585
2586 return 0;
2587 }
2588
2589
2590 /**
2591 * Register a function to be called when various USB events occur.
2592 *
2593 * @state: USB device state populated by
2594 * cvmx_usb_initialize().
2595 * @reason: Which event to register for.
2596 * @callback: Function to call when the event occurs.
2597 * @user_data: User data parameter to the function.
2598 *
2599 * Returns: 0 or a negative error code.
2600 */
2601 int cvmx_usb_register_callback(struct cvmx_usb_state *state,
2602 enum cvmx_usb_callback reason,
2603 cvmx_usb_callback_func_t callback,
2604 void *user_data)
2605 {
2606 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
2607
2608 if (unlikely(reason >= __CVMX_USB_CALLBACK_END))
2609 return -EINVAL;
2610 if (unlikely(!callback))
2611 return -EINVAL;
2612
2613 usb->callback[reason] = callback;
2614 usb->callback_data[reason] = user_data;
2615
2616 return 0;
2617 }
2618
2619
2620 /**
2621 * Get the current USB protocol level frame number. The frame
2622 * number is always in the range of 0-0x7ff.
2623 *
2624 * @state: USB device state populated by
2625 * cvmx_usb_initialize().
2626 *
2627 * Returns: USB frame number
2628 */
2629 int cvmx_usb_get_frame_number(struct cvmx_usb_state *state)
2630 {
2631 int frame_number;
2632 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
2633 union cvmx_usbcx_hfnum usbc_hfnum;
2634
2635 usbc_hfnum.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index));
2636 frame_number = usbc_hfnum.s.frnum;
2637
2638 return frame_number;
2639 }
2640
2641
2642 /**
2643 * Poll a channel for status
2644 *
2645 * @usb: USB device
2646 * @channel: Channel to poll
2647 *
2648 * Returns: Zero on success
2649 */
2650 static int __cvmx_usb_poll_channel(struct cvmx_usb_internal_state *usb, int channel)
2651 {
2652 union cvmx_usbcx_hcintx usbc_hcint;
2653 union cvmx_usbcx_hctsizx usbc_hctsiz;
2654 union cvmx_usbcx_hccharx usbc_hcchar;
2655 struct cvmx_usb_pipe *pipe;
2656 struct cvmx_usb_transaction *transaction;
2657 int bytes_this_transfer;
2658 int bytes_in_last_packet;
2659 int packets_processed;
2660 int buffer_space_left;
2661
2662 /* Read the interrupt status bits for the channel */
2663 usbc_hcint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCINTX(channel, usb->index));
2664
2665 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) {
2666 usbc_hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index));
2667
2668 if (usbc_hcchar.s.chena && usbc_hcchar.s.chdis) {
2669 /*
2670 * There seems to be a bug in CN31XX which can cause
2671 * interrupt IN transfers to get stuck until we do a
2672 * write of HCCHARX without changing things
2673 */
2674 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index), usbc_hcchar.u32);
2675 return 0;
2676 }
2677
2678 /*
2679 * In non DMA mode the channels don't halt themselves. We need
2680 * to manually disable channels that are left running
2681 */
2682 if (!usbc_hcint.s.chhltd) {
2683 if (usbc_hcchar.s.chena) {
2684 union cvmx_usbcx_hcintmskx hcintmsk;
2685 /* Disable all interrupts except CHHLTD */
2686 hcintmsk.u32 = 0;
2687 hcintmsk.s.chhltdmsk = 1;
2688 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), hcintmsk.u32);
2689 usbc_hcchar.s.chdis = 1;
2690 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index), usbc_hcchar.u32);
2691 return 0;
2692 } else if (usbc_hcint.s.xfercompl) {
2693 /*
2694 * Successful IN/OUT with transfer complete.
2695 * Channel halt isn't needed.
2696 */
2697 } else {
2698 cvmx_dprintf("USB%d: Channel %d interrupt without halt\n", usb->index, channel);
2699 return 0;
2700 }
2701 }
2702 } else {
2703 /*
2704 * There is are no interrupts that we need to process when the
2705 * channel is still running
2706 */
2707 if (!usbc_hcint.s.chhltd)
2708 return 0;
2709 }
2710
2711 /* Disable the channel interrupts now that it is done */
2712 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), 0);
2713 usb->idle_hardware_channels |= (1<<channel);
2714
2715 /* Make sure this channel is tied to a valid pipe */
2716 pipe = usb->pipe_for_channel[channel];
2717 CVMX_PREFETCH(pipe, 0);
2718 CVMX_PREFETCH(pipe, 128);
2719 if (!pipe)
2720 return 0;
2721 transaction = pipe->head;
2722 CVMX_PREFETCH(transaction, 0);
2723
2724 /*
2725 * Disconnect this pipe from the HW channel. Later the schedule
2726 * function will figure out which pipe needs to go
2727 */
2728 usb->pipe_for_channel[channel] = NULL;
2729 pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_SCHEDULED;
2730
2731 /*
2732 * Read the channel config info so we can figure out how much data
2733 * transfered
2734 */
2735 usbc_hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index));
2736 usbc_hctsiz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index));
2737
2738 /*
2739 * Calculating the number of bytes successfully transferred is dependent
2740 * on the transfer direction
2741 */
2742 packets_processed = transaction->pktcnt - usbc_hctsiz.s.pktcnt;
2743 if (usbc_hcchar.s.epdir) {
2744 /*
2745 * IN transactions are easy. For every byte received the
2746 * hardware decrements xfersize. All we need to do is subtract
2747 * the current value of xfersize from its starting value and we
2748 * know how many bytes were written to the buffer
2749 */
2750 bytes_this_transfer = transaction->xfersize - usbc_hctsiz.s.xfersize;
2751 } else {
2752 /*
2753 * OUT transaction don't decrement xfersize. Instead pktcnt is
2754 * decremented on every successful packet send. The hardware
2755 * does this when it receives an ACK, or NYET. If it doesn't
2756 * receive one of these responses pktcnt doesn't change
2757 */
2758 bytes_this_transfer = packets_processed * usbc_hcchar.s.mps;
2759 /*
2760 * The last packet may not be a full transfer if we didn't have
2761 * enough data
2762 */
2763 if (bytes_this_transfer > transaction->xfersize)
2764 bytes_this_transfer = transaction->xfersize;
2765 }
2766 /* Figure out how many bytes were in the last packet of the transfer */
2767 if (packets_processed)
2768 bytes_in_last_packet = bytes_this_transfer - (packets_processed-1) * usbc_hcchar.s.mps;
2769 else
2770 bytes_in_last_packet = bytes_this_transfer;
2771
2772 /*
2773 * As a special case, setup transactions output the setup header, not
2774 * the user's data. For this reason we don't count setup data as bytes
2775 * transferred
2776 */
2777 if ((transaction->stage == CVMX_USB_STAGE_SETUP) ||
2778 (transaction->stage == CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE))
2779 bytes_this_transfer = 0;
2780
2781 /*
2782 * Add the bytes transferred to the running total. It is important that
2783 * bytes_this_transfer doesn't count any data that needs to be
2784 * retransmitted
2785 */
2786 transaction->actual_bytes += bytes_this_transfer;
2787 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
2788 buffer_space_left = transaction->iso_packets[0].length - transaction->actual_bytes;
2789 else
2790 buffer_space_left = transaction->buffer_length - transaction->actual_bytes;
2791
2792 /*
2793 * We need to remember the PID toggle state for the next transaction.
2794 * The hardware already updated it for the next transaction
2795 */
2796 pipe->pid_toggle = !(usbc_hctsiz.s.pid == 0);
2797
2798 /*
2799 * For high speed bulk out, assume the next transaction will need to do
2800 * a ping before proceeding. If this isn't true the ACK processing below
2801 * will clear this flag
2802 */
2803 if ((pipe->device_speed == CVMX_USB_SPEED_HIGH) &&
2804 (pipe->transfer_type == CVMX_USB_TRANSFER_BULK) &&
2805 (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT))
2806 pipe->flags |= __CVMX_USB_PIPE_FLAGS_NEED_PING;
2807
2808 if (usbc_hcint.s.stall) {
2809 /*
2810 * STALL as a response means this transaction cannot be
2811 * completed because the device can't process transactions. Tell
2812 * the user. Any data that was transferred will be counted on
2813 * the actual bytes transferred
2814 */
2815 pipe->pid_toggle = 0;
2816 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_STALL);
2817 } else if (usbc_hcint.s.xacterr) {
2818 /*
2819 * We know at least one packet worked if we get a ACK or NAK.
2820 * Reset the retry counter
2821 */
2822 if (usbc_hcint.s.nak || usbc_hcint.s.ack)
2823 transaction->retries = 0;
2824 transaction->retries++;
2825 if (transaction->retries > MAX_RETRIES) {
2826 /*
2827 * XactErr as a response means the device signaled
2828 * something wrong with the transfer. For example, PID
2829 * toggle errors cause these
2830 */
2831 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_XACTERR);
2832 } else {
2833 /*
2834 * If this was a split then clear our split in progress
2835 * marker
2836 */
2837 if (usb->active_split == transaction)
2838 usb->active_split = NULL;
2839 /*
2840 * Rewind to the beginning of the transaction by anding
2841 * off the split complete bit
2842 */
2843 transaction->stage &= ~1;
2844 pipe->split_sc_frame = -1;
2845 pipe->next_tx_frame += pipe->interval;
2846 if (pipe->next_tx_frame < usb->frame_number)
2847 pipe->next_tx_frame = usb->frame_number + pipe->interval -
2848 (usb->frame_number - pipe->next_tx_frame) % pipe->interval;
2849 }
2850 } else if (usbc_hcint.s.bblerr) {
2851 /* Babble Error (BblErr) */
2852 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_BABBLEERR);
2853 } else if (usbc_hcint.s.datatglerr) {
2854 /* We'll retry the exact same transaction again */
2855 transaction->retries++;
2856 } else if (usbc_hcint.s.nyet) {
2857 /*
2858 * NYET as a response is only allowed in three cases: as a
2859 * response to a ping, as a response to a split transaction, and
2860 * as a response to a bulk out. The ping case is handled by
2861 * hardware, so we only have splits and bulk out
2862 */
2863 if (!__cvmx_usb_pipe_needs_split(usb, pipe)) {
2864 transaction->retries = 0;
2865 /*
2866 * If there is more data to go then we need to try
2867 * again. Otherwise this transaction is complete
2868 */
2869 if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet))
2870 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2871 } else {
2872 /*
2873 * Split transactions retry the split complete 4 times
2874 * then rewind to the start split and do the entire
2875 * transactions again
2876 */
2877 transaction->retries++;
2878 if ((transaction->retries & 0x3) == 0) {
2879 /*
2880 * Rewind to the beginning of the transaction by
2881 * anding off the split complete bit
2882 */
2883 transaction->stage &= ~1;
2884 pipe->split_sc_frame = -1;
2885 }
2886 }
2887 } else if (usbc_hcint.s.ack) {
2888 transaction->retries = 0;
2889 /*
2890 * The ACK bit can only be checked after the other error bits.
2891 * This is because a multi packet transfer may succeed in a
2892 * number of packets and then get a different response on the
2893 * last packet. In this case both ACK and the last response bit
2894 * will be set. If none of the other response bits is set, then
2895 * the last packet must have been an ACK
2896 *
2897 * Since we got an ACK, we know we don't need to do a ping on
2898 * this pipe
2899 */
2900 pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_NEED_PING;
2901
2902 switch (transaction->type) {
2903 case CVMX_USB_TRANSFER_CONTROL:
2904 switch (transaction->stage) {
2905 case CVMX_USB_STAGE_NON_CONTROL:
2906 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE:
2907 /* This should be impossible */
2908 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_ERROR);
2909 break;
2910 case CVMX_USB_STAGE_SETUP:
2911 pipe->pid_toggle = 1;
2912 if (__cvmx_usb_pipe_needs_split(usb, pipe))
2913 transaction->stage = CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE;
2914 else {
2915 union cvmx_usb_control_header *header =
2916 cvmx_phys_to_ptr(transaction->control_header);
2917 if (header->s.length)
2918 transaction->stage = CVMX_USB_STAGE_DATA;
2919 else
2920 transaction->stage = CVMX_USB_STAGE_STATUS;
2921 }
2922 break;
2923 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE:
2924 {
2925 union cvmx_usb_control_header *header =
2926 cvmx_phys_to_ptr(transaction->control_header);
2927 if (header->s.length)
2928 transaction->stage = CVMX_USB_STAGE_DATA;
2929 else
2930 transaction->stage = CVMX_USB_STAGE_STATUS;
2931 }
2932 break;
2933 case CVMX_USB_STAGE_DATA:
2934 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
2935 transaction->stage = CVMX_USB_STAGE_DATA_SPLIT_COMPLETE;
2936 /*
2937 * For setup OUT data that are splits,
2938 * the hardware doesn't appear to count
2939 * transferred data. Here we manually
2940 * update the data transferred
2941 */
2942 if (!usbc_hcchar.s.epdir) {
2943 if (buffer_space_left < pipe->max_packet)
2944 transaction->actual_bytes += buffer_space_left;
2945 else
2946 transaction->actual_bytes += pipe->max_packet;
2947 }
2948 } else if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet)) {
2949 pipe->pid_toggle = 1;
2950 transaction->stage = CVMX_USB_STAGE_STATUS;
2951 }
2952 break;
2953 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE:
2954 if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet)) {
2955 pipe->pid_toggle = 1;
2956 transaction->stage = CVMX_USB_STAGE_STATUS;
2957 } else {
2958 transaction->stage = CVMX_USB_STAGE_DATA;
2959 }
2960 break;
2961 case CVMX_USB_STAGE_STATUS:
2962 if (__cvmx_usb_pipe_needs_split(usb, pipe))
2963 transaction->stage = CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE;
2964 else
2965 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2966 break;
2967 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE:
2968 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2969 break;
2970 }
2971 break;
2972 case CVMX_USB_TRANSFER_BULK:
2973 case CVMX_USB_TRANSFER_INTERRUPT:
2974 /*
2975 * The only time a bulk transfer isn't complete when it
2976 * finishes with an ACK is during a split transaction.
2977 * For splits we need to continue the transfer if more
2978 * data is needed
2979 */
2980 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
2981 if (transaction->stage == CVMX_USB_STAGE_NON_CONTROL)
2982 transaction->stage = CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE;
2983 else {
2984 if (buffer_space_left && (bytes_in_last_packet == pipe->max_packet))
2985 transaction->stage = CVMX_USB_STAGE_NON_CONTROL;
2986 else {
2987 if (transaction->type == CVMX_USB_TRANSFER_INTERRUPT)
2988 pipe->next_tx_frame += pipe->interval;
2989 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2990 }
2991 }
2992 } else {
2993 if ((pipe->device_speed == CVMX_USB_SPEED_HIGH) &&
2994 (pipe->transfer_type == CVMX_USB_TRANSFER_BULK) &&
2995 (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) &&
2996 (usbc_hcint.s.nak))
2997 pipe->flags |= __CVMX_USB_PIPE_FLAGS_NEED_PING;
2998 if (!buffer_space_left || (bytes_in_last_packet < pipe->max_packet)) {
2999 if (transaction->type == CVMX_USB_TRANSFER_INTERRUPT)
3000 pipe->next_tx_frame += pipe->interval;
3001 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
3002 }
3003 }
3004 break;
3005 case CVMX_USB_TRANSFER_ISOCHRONOUS:
3006 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
3007 /*
3008 * ISOCHRONOUS OUT splits don't require a
3009 * complete split stage. Instead they use a
3010 * sequence of begin OUT splits to transfer the
3011 * data 188 bytes at a time. Once the transfer
3012 * is complete, the pipe sleeps until the next
3013 * schedule interval
3014 */
3015 if (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) {
3016 /*
3017 * If no space left or this wasn't a max
3018 * size packet then this transfer is
3019 * complete. Otherwise start it again to
3020 * send the next 188 bytes
3021 */
3022 if (!buffer_space_left || (bytes_this_transfer < 188)) {
3023 pipe->next_tx_frame += pipe->interval;
3024 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
3025 }
3026 } else {
3027 if (transaction->stage == CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE) {
3028 /*
3029 * We are in the incoming data
3030 * phase. Keep getting data
3031 * until we run out of space or
3032 * get a small packet
3033 */
3034 if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet)) {
3035 pipe->next_tx_frame += pipe->interval;
3036 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
3037 }
3038 } else
3039 transaction->stage = CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE;
3040 }
3041 } else {
3042 pipe->next_tx_frame += pipe->interval;
3043 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
3044 }
3045 break;
3046 }
3047 } else if (usbc_hcint.s.nak) {
3048 /*
3049 * If this was a split then clear our split in progress marker.
3050 */
3051 if (usb->active_split == transaction)
3052 usb->active_split = NULL;
3053 /*
3054 * NAK as a response means the device couldn't accept the
3055 * transaction, but it should be retried in the future. Rewind
3056 * to the beginning of the transaction by anding off the split
3057 * complete bit. Retry in the next interval
3058 */
3059 transaction->retries = 0;
3060 transaction->stage &= ~1;
3061 pipe->next_tx_frame += pipe->interval;
3062 if (pipe->next_tx_frame < usb->frame_number)
3063 pipe->next_tx_frame = usb->frame_number + pipe->interval -
3064 (usb->frame_number - pipe->next_tx_frame) % pipe->interval;
3065 } else {
3066 struct cvmx_usb_port_status port;
3067 port = cvmx_usb_get_status((struct cvmx_usb_state *)usb);
3068 if (port.port_enabled) {
3069 /* We'll retry the exact same transaction again */
3070 transaction->retries++;
3071 } else {
3072 /*
3073 * We get channel halted interrupts with no result bits
3074 * sets when the cable is unplugged
3075 */
3076 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_ERROR);
3077 }
3078 }
3079 return 0;
3080 }
3081
3082
3083 /**
3084 * Poll the USB block for status and call all needed callback
3085 * handlers. This function is meant to be called in the interrupt
3086 * handler for the USB controller. It can also be called
3087 * periodically in a loop for non-interrupt based operation.
3088 *
3089 * @state: USB device state populated by
3090 * cvmx_usb_initialize().
3091 *
3092 * Returns: 0 or a negative error code.
3093 */
3094 int cvmx_usb_poll(struct cvmx_usb_state *state)
3095 {
3096 union cvmx_usbcx_hfnum usbc_hfnum;
3097 union cvmx_usbcx_gintsts usbc_gintsts;
3098 struct cvmx_usb_internal_state *usb = (struct cvmx_usb_internal_state *)state;
3099
3100 CVMX_PREFETCH(usb, 0);
3101 CVMX_PREFETCH(usb, 1*128);
3102 CVMX_PREFETCH(usb, 2*128);
3103 CVMX_PREFETCH(usb, 3*128);
3104 CVMX_PREFETCH(usb, 4*128);
3105
3106 /* Update the frame counter */
3107 usbc_hfnum.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index));
3108 if ((usb->frame_number&0x3fff) > usbc_hfnum.s.frnum)
3109 usb->frame_number += 0x4000;
3110 usb->frame_number &= ~0x3fffull;
3111 usb->frame_number |= usbc_hfnum.s.frnum;
3112
3113 /* Read the pending interrupts */
3114 usbc_gintsts.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GINTSTS(usb->index));
3115
3116 /* Clear the interrupts now that we know about them */
3117 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTSTS(usb->index), usbc_gintsts.u32);
3118
3119 if (usbc_gintsts.s.rxflvl) {
3120 /*
3121 * RxFIFO Non-Empty (RxFLvl)
3122 * Indicates that there is at least one packet pending to be
3123 * read from the RxFIFO.
3124 *
3125 * In DMA mode this is handled by hardware
3126 */
3127 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
3128 __cvmx_usb_poll_rx_fifo(usb);
3129 }
3130 if (usbc_gintsts.s.ptxfemp || usbc_gintsts.s.nptxfemp) {
3131 /* Fill the Tx FIFOs when not in DMA mode */
3132 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
3133 __cvmx_usb_poll_tx_fifo(usb);
3134 }
3135 if (usbc_gintsts.s.disconnint || usbc_gintsts.s.prtint) {
3136 union cvmx_usbcx_hprt usbc_hprt;
3137 /*
3138 * Disconnect Detected Interrupt (DisconnInt)
3139 * Asserted when a device disconnect is detected.
3140 *
3141 * Host Port Interrupt (PrtInt)
3142 * The core sets this bit to indicate a change in port status of
3143 * one of the O2P USB core ports in Host mode. The application
3144 * must read the Host Port Control and Status (HPRT) register to
3145 * determine the exact event that caused this interrupt. The
3146 * application must clear the appropriate status bit in the Host
3147 * Port Control and Status register to clear this bit.
3148 *
3149 * Call the user's port callback
3150 */
3151 __cvmx_usb_perform_callback(usb, NULL, NULL,
3152 CVMX_USB_CALLBACK_PORT_CHANGED,
3153 CVMX_USB_COMPLETE_SUCCESS);
3154 /* Clear the port change bits */
3155 usbc_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
3156 usbc_hprt.s.prtena = 0;
3157 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HPRT(usb->index), usbc_hprt.u32);
3158 }
3159 if (usbc_gintsts.s.hchint) {
3160 /*
3161 * Host Channels Interrupt (HChInt)
3162 * The core sets this bit to indicate that an interrupt is
3163 * pending on one of the channels of the core (in Host mode).
3164 * The application must read the Host All Channels Interrupt
3165 * (HAINT) register to determine the exact number of the channel
3166 * on which the interrupt occurred, and then read the
3167 * corresponding Host Channel-n Interrupt (HCINTn) register to
3168 * determine the exact cause of the interrupt. The application
3169 * must clear the appropriate status bit in the HCINTn register
3170 * to clear this bit.
3171 */
3172 union cvmx_usbcx_haint usbc_haint;
3173 usbc_haint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HAINT(usb->index));
3174 while (usbc_haint.u32) {
3175 int channel;
3176
3177 channel = __fls(usbc_haint.u32);
3178 __cvmx_usb_poll_channel(usb, channel);
3179 usbc_haint.u32 ^= 1<<channel;
3180 }
3181 }
3182
3183 __cvmx_usb_schedule(usb, usbc_gintsts.s.sof);
3184
3185 return 0;
3186 }
This page took 0.170814 seconds and 5 git commands to generate.