staging: octeon-usb: cvmx-usb: delete __cvmx_usb_complete_to_string()
[deliverable/linux.git] / drivers / staging / octeon-usb / cvmx-usb.c
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40
41 /**
42 * @file
43 *
44 * "cvmx-usb.c" defines a set of low level USB functions to help
45 * developers create Octeon USB drivers for various operating
46 * systems. These functions provide a generic API to the Octeon
47 * USB blocks, hiding the internal hardware specific
48 * operations.
49 *
50 * <hr>$Revision: 32636 $<hr>
51 */
52 #include <linux/delay.h>
53 #include <asm/octeon/cvmx.h>
54 #include <asm/octeon/octeon.h>
55 #include <asm/octeon/cvmx-sysinfo.h>
56 #include "cvmx-usbnx-defs.h"
57 #include "cvmx-usbcx-defs.h"
58 #include "cvmx-usb.h"
59 #include <asm/octeon/cvmx-helper.h>
60 #include <asm/octeon/cvmx-helper-board.h>
61
62 #define CVMX_PREFETCH0(address) CVMX_PREFETCH(address, 0)
63 #define CVMX_PREFETCH128(address) CVMX_PREFETCH(address, 128)
64 // a normal prefetch
65 #define CVMX_PREFETCH(address, offset) CVMX_PREFETCH_PREF0(address, offset)
66 // normal prefetches that use the pref instruction
67 #define CVMX_PREFETCH_PREFX(X, address, offset) asm volatile ("pref %[type], %[off](%[rbase])" : : [rbase] "d" (address), [off] "I" (offset), [type] "n" (X))
68 #define CVMX_PREFETCH_PREF0(address, offset) CVMX_PREFETCH_PREFX(0, address, offset)
69 #define CVMX_CLZ(result, input) asm ("clz %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
70
71 #define MAX_RETRIES 3 /* Maximum number of times to retry failed transactions */
72 #define MAX_PIPES 32 /* Maximum number of pipes that can be open at once */
73 #define MAX_TRANSACTIONS 256 /* Maximum number of outstanding transactions across all pipes */
74 #define MAX_CHANNELS 8 /* Maximum number of hardware channels supported by the USB block */
75 #define MAX_USB_ADDRESS 127 /* The highest valid USB device address */
76 #define MAX_USB_ENDPOINT 15 /* The highest valid USB endpoint number */
77 #define MAX_USB_HUB_PORT 15 /* The highest valid port number on a hub */
78 #define MAX_TRANSFER_BYTES ((1<<19)-1) /* The low level hardware can transfer a maximum of this number of bytes in each transfer. The field is 19 bits wide */
79 #define MAX_TRANSFER_PACKETS ((1<<10)-1) /* The low level hardware can transfer a maximum of this number of packets in each transfer. The field is 10 bits wide */
80
81 /* These defines disable the normal read and write csr. This is so I can add
82 extra debug stuff to the usb specific version and I won't use the normal
83 version by mistake */
84 #define cvmx_read_csr use_cvmx_usb_read_csr64_instead_of_cvmx_read_csr
85 #define cvmx_write_csr use_cvmx_usb_write_csr64_instead_of_cvmx_write_csr
86
87 typedef enum {
88 __CVMX_USB_TRANSACTION_FLAGS_IN_USE = 1<<16,
89 } cvmx_usb_transaction_flags_t;
90
91 enum {
92 USB_CLOCK_TYPE_REF_12,
93 USB_CLOCK_TYPE_REF_24,
94 USB_CLOCK_TYPE_REF_48,
95 USB_CLOCK_TYPE_CRYSTAL_12,
96 };
97
98 /**
99 * Logical transactions may take numerous low level
100 * transactions, especially when splits are concerned. This
101 * enum represents all of the possible stages a transaction can
102 * be in. Note that split completes are always even. This is so
103 * the NAK handler can backup to the previous low level
104 * transaction with a simple clearing of bit 0.
105 */
106 typedef enum {
107 CVMX_USB_STAGE_NON_CONTROL,
108 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE,
109 CVMX_USB_STAGE_SETUP,
110 CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE,
111 CVMX_USB_STAGE_DATA,
112 CVMX_USB_STAGE_DATA_SPLIT_COMPLETE,
113 CVMX_USB_STAGE_STATUS,
114 CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE,
115 } cvmx_usb_stage_t;
116
117 /**
118 * This structure describes each pending USB transaction
119 * regardless of type. These are linked together to form a list
120 * of pending requests for a pipe.
121 */
122 typedef struct cvmx_usb_transaction {
123 struct cvmx_usb_transaction *prev; /**< Transaction before this one in the pipe */
124 struct cvmx_usb_transaction *next; /**< Transaction after this one in the pipe */
125 cvmx_usb_transfer_t type; /**< Type of transaction, duplicated of the pipe */
126 cvmx_usb_transaction_flags_t flags; /**< State flags for this transaction */
127 uint64_t buffer; /**< User's physical buffer address to read/write */
128 int buffer_length; /**< Size of the user's buffer in bytes */
129 uint64_t control_header; /**< For control transactions, physical address of the 8 byte standard header */
130 int iso_start_frame; /**< For ISO transactions, the starting frame number */
131 int iso_number_packets; /**< For ISO transactions, the number of packets in the request */
132 cvmx_usb_iso_packet_t *iso_packets; /**< For ISO transactions, the sub packets in the request */
133 int xfersize;
134 int pktcnt;
135 int retries;
136 int actual_bytes; /**< Actual bytes transfer for this transaction */
137 cvmx_usb_stage_t stage; /**< For control transactions, the current stage */
138 cvmx_usb_callback_func_t callback; /**< User's callback function when complete */
139 void *callback_data; /**< User's data */
140 } cvmx_usb_transaction_t;
141
142 /**
143 * A pipe represents a virtual connection between Octeon and some
144 * USB device. It contains a list of pending request to the device.
145 */
146 typedef struct cvmx_usb_pipe {
147 struct cvmx_usb_pipe *prev; /**< Pipe before this one in the list */
148 struct cvmx_usb_pipe *next; /**< Pipe after this one in the list */
149 cvmx_usb_transaction_t *head; /**< The first pending transaction */
150 cvmx_usb_transaction_t *tail; /**< The last pending transaction */
151 uint64_t interval; /**< For periodic pipes, the interval between packets in frames */
152 uint64_t next_tx_frame; /**< The next frame this pipe is allowed to transmit on */
153 cvmx_usb_pipe_flags_t flags; /**< State flags for this pipe */
154 cvmx_usb_speed_t device_speed; /**< Speed of device connected to this pipe */
155 cvmx_usb_transfer_t transfer_type; /**< Type of transaction supported by this pipe */
156 cvmx_usb_direction_t transfer_dir; /**< IN or OUT. Ignored for Control */
157 int multi_count; /**< Max packet in a row for the device */
158 uint16_t max_packet; /**< The device's maximum packet size in bytes */
159 uint8_t device_addr; /**< USB device address at other end of pipe */
160 uint8_t endpoint_num; /**< USB endpoint number at other end of pipe */
161 uint8_t hub_device_addr; /**< Hub address this device is connected to */
162 uint8_t hub_port; /**< Hub port this device is connected to */
163 uint8_t pid_toggle; /**< This toggles between 0/1 on every packet send to track the data pid needed */
164 uint8_t channel; /**< Hardware DMA channel for this pipe */
165 int8_t split_sc_frame; /**< The low order bits of the frame number the split complete should be sent on */
166 } cvmx_usb_pipe_t;
167
168 typedef struct {
169 cvmx_usb_pipe_t *head; /**< Head of the list, or NULL if empty */
170 cvmx_usb_pipe_t *tail; /**< Tail if the list, or NULL if empty */
171 } cvmx_usb_pipe_list_t;
172
173 typedef struct {
174 struct {
175 int channel;
176 int size;
177 uint64_t address;
178 } entry[MAX_CHANNELS+1];
179 int head;
180 int tail;
181 } cvmx_usb_tx_fifo_t;
182
183 /**
184 * The state of the USB block is stored in this structure
185 */
186 typedef struct {
187 int init_flags; /**< Flags passed to initialize */
188 int index; /**< Which USB block this is for */
189 int idle_hardware_channels; /**< Bit set for every idle hardware channel */
190 cvmx_usbcx_hprt_t usbcx_hprt; /**< Stored port status so we don't need to read a CSR to determine splits */
191 cvmx_usb_pipe_t *pipe_for_channel[MAX_CHANNELS]; /**< Map channels to pipes */
192 cvmx_usb_transaction_t *free_transaction_head; /**< List of free transactions head */
193 cvmx_usb_transaction_t *free_transaction_tail; /**< List of free transactions tail */
194 cvmx_usb_pipe_t pipe[MAX_PIPES]; /**< Storage for pipes */
195 cvmx_usb_transaction_t transaction[MAX_TRANSACTIONS]; /**< Storage for transactions */
196 cvmx_usb_callback_func_t callback[__CVMX_USB_CALLBACK_END]; /**< User global callbacks */
197 void *callback_data[__CVMX_USB_CALLBACK_END]; /**< User data for each callback */
198 int indent; /**< Used by debug output to indent functions */
199 cvmx_usb_port_status_t port_status; /**< Last port status used for change notification */
200 cvmx_usb_pipe_list_t free_pipes; /**< List of all pipes that are currently closed */
201 cvmx_usb_pipe_list_t idle_pipes; /**< List of open pipes that have no transactions */
202 cvmx_usb_pipe_list_t active_pipes[4]; /**< Active pipes indexed by transfer type */
203 uint64_t frame_number; /**< Increments every SOF interrupt for time keeping */
204 cvmx_usb_transaction_t *active_split; /**< Points to the current active split, or NULL */
205 cvmx_usb_tx_fifo_t periodic;
206 cvmx_usb_tx_fifo_t nonperiodic;
207 } cvmx_usb_internal_state_t;
208
209 /* This macro spins on a field waiting for it to reach a value */
210 #define CVMX_WAIT_FOR_FIELD32(address, type, field, op, value, timeout_usec)\
211 ({int result; \
212 do { \
213 uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec * \
214 octeon_get_clock_rate() / 1000000; \
215 type c; \
216 while (1) \
217 { \
218 c.u32 = __cvmx_usb_read_csr32(usb, address); \
219 if (c.s.field op (value)) { \
220 result = 0; \
221 break; \
222 } else if (cvmx_get_cycle() > done) { \
223 result = -1; \
224 break; \
225 } else \
226 cvmx_wait(100); \
227 } \
228 } while (0); \
229 result;})
230
231 /* This macro logically sets a single field in a CSR. It does the sequence
232 read, modify, and write */
233 #define USB_SET_FIELD32(address, type, field, value)\
234 do { \
235 type c; \
236 c.u32 = __cvmx_usb_read_csr32(usb, address);\
237 c.s.field = value; \
238 __cvmx_usb_write_csr32(usb, address, c.u32);\
239 } while (0)
240
241 /* Returns the IO address to push/pop stuff data from the FIFOs */
242 #define USB_FIFO_ADDRESS(channel, usb_index) (CVMX_USBCX_GOTGCTL(usb_index) + ((channel)+1)*0x1000)
243
244 static int octeon_usb_get_clock_type(void)
245 {
246 switch (cvmx_sysinfo_get()->board_type) {
247 case CVMX_BOARD_TYPE_BBGW_REF:
248 case CVMX_BOARD_TYPE_LANAI2_A:
249 case CVMX_BOARD_TYPE_LANAI2_U:
250 case CVMX_BOARD_TYPE_LANAI2_G:
251 case CVMX_BOARD_TYPE_UBNT_E100:
252 return USB_CLOCK_TYPE_CRYSTAL_12;
253 }
254 return USB_CLOCK_TYPE_REF_48;
255 }
256
257 /**
258 * @INTERNAL
259 * Read a USB 32bit CSR. It performs the necessary address swizzle
260 * for 32bit CSRs and logs the value in a readable format if
261 * debugging is on.
262 *
263 * @param usb USB block this access is for
264 * @param address 64bit address to read
265 *
266 * @return Result of the read
267 */
268 static inline uint32_t __cvmx_usb_read_csr32(cvmx_usb_internal_state_t *usb,
269 uint64_t address)
270 {
271 uint32_t result = cvmx_read64_uint32(address ^ 4);
272 return result;
273 }
274
275
276 /**
277 * @INTERNAL
278 * Write a USB 32bit CSR. It performs the necessary address
279 * swizzle for 32bit CSRs and logs the value in a readable format
280 * if debugging is on.
281 *
282 * @param usb USB block this access is for
283 * @param address 64bit address to write
284 * @param value Value to write
285 */
286 static inline void __cvmx_usb_write_csr32(cvmx_usb_internal_state_t *usb,
287 uint64_t address, uint32_t value)
288 {
289 cvmx_write64_uint32(address ^ 4, value);
290 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
291 }
292
293
294 /**
295 * @INTERNAL
296 * Read a USB 64bit CSR. It logs the value in a readable format if
297 * debugging is on.
298 *
299 * @param usb USB block this access is for
300 * @param address 64bit address to read
301 *
302 * @return Result of the read
303 */
304 static inline uint64_t __cvmx_usb_read_csr64(cvmx_usb_internal_state_t *usb,
305 uint64_t address)
306 {
307 uint64_t result = cvmx_read64_uint64(address);
308 return result;
309 }
310
311
312 /**
313 * @INTERNAL
314 * Write a USB 64bit CSR. It logs the value in a readable format
315 * if debugging is on.
316 *
317 * @param usb USB block this access is for
318 * @param address 64bit address to write
319 * @param value Value to write
320 */
321 static inline void __cvmx_usb_write_csr64(cvmx_usb_internal_state_t *usb,
322 uint64_t address, uint64_t value)
323 {
324 cvmx_write64_uint64(address, value);
325 }
326
327 /**
328 * @INTERNAL
329 * Return non zero if this pipe connects to a non HIGH speed
330 * device through a high speed hub.
331 *
332 * @param usb USB block this access is for
333 * @param pipe Pipe to check
334 *
335 * @return Non zero if we need to do split transactions
336 */
337 static inline int __cvmx_usb_pipe_needs_split(cvmx_usb_internal_state_t *usb, cvmx_usb_pipe_t *pipe)
338 {
339 return ((pipe->device_speed != CVMX_USB_SPEED_HIGH) && (usb->usbcx_hprt.s.prtspd == CVMX_USB_SPEED_HIGH));
340 }
341
342
343 /**
344 * @INTERNAL
345 * Trivial utility function to return the correct PID for a pipe
346 *
347 * @param pipe pipe to check
348 *
349 * @return PID for pipe
350 */
351 static inline int __cvmx_usb_get_data_pid(cvmx_usb_pipe_t *pipe)
352 {
353 if (pipe->pid_toggle)
354 return 2; /* Data1 */
355 else
356 return 0; /* Data0 */
357 }
358
359
360 /**
361 * Return the number of USB ports supported by this Octeon
362 * chip. If the chip doesn't support USB, or is not supported
363 * by this API, a zero will be returned. Most Octeon chips
364 * support one usb port, but some support two ports.
365 * cvmx_usb_initialize() must be called on independent
366 * cvmx_usb_state_t structures.
367 *
368 * @return Number of port, zero if usb isn't supported
369 */
370 int cvmx_usb_get_num_ports(void)
371 {
372 int arch_ports = 0;
373
374 if (OCTEON_IS_MODEL(OCTEON_CN56XX))
375 arch_ports = 1;
376 else if (OCTEON_IS_MODEL(OCTEON_CN52XX))
377 arch_ports = 2;
378 else if (OCTEON_IS_MODEL(OCTEON_CN50XX))
379 arch_ports = 1;
380 else if (OCTEON_IS_MODEL(OCTEON_CN31XX))
381 arch_ports = 1;
382 else if (OCTEON_IS_MODEL(OCTEON_CN30XX))
383 arch_ports = 1;
384 else
385 arch_ports = 0;
386
387 return arch_ports;
388 }
389
390
391 /**
392 * @INTERNAL
393 * Allocate a usb transaction for use
394 *
395 * @param usb USB device state populated by
396 * cvmx_usb_initialize().
397 *
398 * @return Transaction or NULL
399 */
400 static inline cvmx_usb_transaction_t *__cvmx_usb_alloc_transaction(cvmx_usb_internal_state_t *usb)
401 {
402 cvmx_usb_transaction_t *t;
403 t = usb->free_transaction_head;
404 if (t) {
405 usb->free_transaction_head = t->next;
406 if (!usb->free_transaction_head)
407 usb->free_transaction_tail = NULL;
408 }
409 if (t) {
410 memset(t, 0, sizeof(*t));
411 t->flags = __CVMX_USB_TRANSACTION_FLAGS_IN_USE;
412 }
413 return t;
414 }
415
416
417 /**
418 * @INTERNAL
419 * Free a usb transaction
420 *
421 * @param usb USB device state populated by
422 * cvmx_usb_initialize().
423 * @param transaction
424 * Transaction to free
425 */
426 static inline void __cvmx_usb_free_transaction(cvmx_usb_internal_state_t *usb,
427 cvmx_usb_transaction_t *transaction)
428 {
429 transaction->flags = 0;
430 transaction->prev = NULL;
431 transaction->next = NULL;
432 if (usb->free_transaction_tail)
433 usb->free_transaction_tail->next = transaction;
434 else
435 usb->free_transaction_head = transaction;
436 usb->free_transaction_tail = transaction;
437 }
438
439
440 /**
441 * @INTERNAL
442 * Add a pipe to the tail of a list
443 * @param list List to add pipe to
444 * @param pipe Pipe to add
445 */
446 static inline void __cvmx_usb_append_pipe(cvmx_usb_pipe_list_t *list, cvmx_usb_pipe_t *pipe)
447 {
448 pipe->next = NULL;
449 pipe->prev = list->tail;
450 if (list->tail)
451 list->tail->next = pipe;
452 else
453 list->head = pipe;
454 list->tail = pipe;
455 }
456
457
458 /**
459 * @INTERNAL
460 * Remove a pipe from a list
461 * @param list List to remove pipe from
462 * @param pipe Pipe to remove
463 */
464 static inline void __cvmx_usb_remove_pipe(cvmx_usb_pipe_list_t *list, cvmx_usb_pipe_t *pipe)
465 {
466 if (list->head == pipe) {
467 list->head = pipe->next;
468 pipe->next = NULL;
469 if (list->head)
470 list->head->prev = NULL;
471 else
472 list->tail = NULL;
473 }
474 else if (list->tail == pipe) {
475 list->tail = pipe->prev;
476 list->tail->next = NULL;
477 pipe->prev = NULL;
478 }
479 else {
480 pipe->prev->next = pipe->next;
481 pipe->next->prev = pipe->prev;
482 pipe->prev = NULL;
483 pipe->next = NULL;
484 }
485 }
486
487
488 /**
489 * Initialize a USB port for use. This must be called before any
490 * other access to the Octeon USB port is made. The port starts
491 * off in the disabled state.
492 *
493 * @param state Pointer to an empty cvmx_usb_state_t structure
494 * that will be populated by the initialize call.
495 * This structure is then passed to all other USB
496 * functions.
497 * @param usb_port_number
498 * Which Octeon USB port to initialize.
499 * @param flags Flags to control hardware initialization. See
500 * cvmx_usb_initialize_flags_t for the flag
501 * definitions. Some flags are mandatory.
502 *
503 * @return 0 or a negative error code.
504 */
505 int cvmx_usb_initialize(cvmx_usb_state_t *state, int usb_port_number,
506 cvmx_usb_initialize_flags_t flags)
507 {
508 cvmx_usbnx_clk_ctl_t usbn_clk_ctl;
509 cvmx_usbnx_usbp_ctl_status_t usbn_usbp_ctl_status;
510 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
511
512 usb->init_flags = flags;
513
514 /* Make sure that state is large enough to store the internal state */
515 if (sizeof(*state) < sizeof(*usb))
516 return -EINVAL;
517 /* At first allow 0-1 for the usb port number */
518 if ((usb_port_number < 0) || (usb_port_number > 1))
519 return -EINVAL;
520 /* For all chips except 52XX there is only one port */
521 if (!OCTEON_IS_MODEL(OCTEON_CN52XX) && (usb_port_number > 0))
522 return -EINVAL;
523 /* Try to determine clock type automatically */
524 if ((flags & (CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI |
525 CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND)) == 0) {
526 if (octeon_usb_get_clock_type() == USB_CLOCK_TYPE_CRYSTAL_12)
527 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI; /* Only 12 MHZ crystals are supported */
528 else
529 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND;
530 }
531
532 if (flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND) {
533 /* Check for auto ref clock frequency */
534 if (!(flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK))
535 switch (octeon_usb_get_clock_type()) {
536 case USB_CLOCK_TYPE_REF_12:
537 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ;
538 break;
539 case USB_CLOCK_TYPE_REF_24:
540 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ;
541 break;
542 case USB_CLOCK_TYPE_REF_48:
543 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ;
544 break;
545 default:
546 return -EINVAL;
547 break;
548 }
549 }
550
551 memset(usb, 0, sizeof(usb));
552 usb->init_flags = flags;
553
554 /* Initialize the USB state structure */
555 {
556 int i;
557 usb->index = usb_port_number;
558
559 /* Initialize the transaction double linked list */
560 usb->free_transaction_head = NULL;
561 usb->free_transaction_tail = NULL;
562 for (i=0; i<MAX_TRANSACTIONS; i++)
563 __cvmx_usb_free_transaction(usb, usb->transaction + i);
564 for (i=0; i<MAX_PIPES; i++)
565 __cvmx_usb_append_pipe(&usb->free_pipes, usb->pipe + i);
566 }
567
568 /* Power On Reset and PHY Initialization */
569
570 /* 1. Wait for DCOK to assert (nothing to do) */
571 /* 2a. Write USBN0/1_CLK_CTL[POR] = 1 and
572 USBN0/1_CLK_CTL[HRST,PRST,HCLK_RST] = 0 */
573 usbn_clk_ctl.u64 = __cvmx_usb_read_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index));
574 usbn_clk_ctl.s.por = 1;
575 usbn_clk_ctl.s.hrst = 0;
576 usbn_clk_ctl.s.prst = 0;
577 usbn_clk_ctl.s.hclk_rst = 0;
578 usbn_clk_ctl.s.enable = 0;
579 /* 2b. Select the USB reference clock/crystal parameters by writing
580 appropriate values to USBN0/1_CLK_CTL[P_C_SEL, P_RTYPE, P_COM_ON] */
581 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND) {
582 /* The USB port uses 12/24/48MHz 2.5V board clock
583 source at USB_XO. USB_XI should be tied to GND.
584 Most Octeon evaluation boards require this setting */
585 if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
586 usbn_clk_ctl.cn31xx.p_rclk = 1; /* From CN31XX,CN30XX manual */
587 usbn_clk_ctl.cn31xx.p_xenbn = 0;
588 }
589 else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))
590 usbn_clk_ctl.cn56xx.p_rtype = 2; /* From CN56XX,CN50XX manual */
591 else
592 usbn_clk_ctl.cn52xx.p_rtype = 1; /* From CN52XX manual */
593
594 switch (flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK) {
595 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ:
596 usbn_clk_ctl.s.p_c_sel = 0;
597 break;
598 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ:
599 usbn_clk_ctl.s.p_c_sel = 1;
600 break;
601 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ:
602 usbn_clk_ctl.s.p_c_sel = 2;
603 break;
604 }
605 }
606 else {
607 /* The USB port uses a 12MHz crystal as clock source
608 at USB_XO and USB_XI */
609 if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
610 usbn_clk_ctl.cn31xx.p_rclk = 1; /* From CN31XX,CN30XX manual */
611 usbn_clk_ctl.cn31xx.p_xenbn = 1;
612 }
613 else if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN50XX))
614 usbn_clk_ctl.cn56xx.p_rtype = 0; /* From CN56XX,CN50XX manual */
615 else
616 usbn_clk_ctl.cn52xx.p_rtype = 0; /* From CN52XX manual */
617
618 usbn_clk_ctl.s.p_c_sel = 0;
619 }
620 /* 2c. Select the HCLK via writing USBN0/1_CLK_CTL[DIVIDE, DIVIDE2] and
621 setting USBN0/1_CLK_CTL[ENABLE] = 1. Divide the core clock down such
622 that USB is as close as possible to 125Mhz */
623 {
624 int divisor = (octeon_get_clock_rate()+125000000-1)/125000000;
625 if (divisor < 4) /* Lower than 4 doesn't seem to work properly */
626 divisor = 4;
627 usbn_clk_ctl.s.divide = divisor;
628 usbn_clk_ctl.s.divide2 = 0;
629 }
630 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
631 usbn_clk_ctl.u64);
632 /* 2d. Write USBN0/1_CLK_CTL[HCLK_RST] = 1 */
633 usbn_clk_ctl.s.hclk_rst = 1;
634 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
635 usbn_clk_ctl.u64);
636 /* 2e. Wait 64 core-clock cycles for HCLK to stabilize */
637 cvmx_wait(64);
638 /* 3. Program the power-on reset field in the USBN clock-control register:
639 USBN_CLK_CTL[POR] = 0 */
640 usbn_clk_ctl.s.por = 0;
641 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
642 usbn_clk_ctl.u64);
643 /* 4. Wait 1 ms for PHY clock to start */
644 mdelay(1);
645 /* 5. Program the Reset input from automatic test equipment field in the
646 USBP control and status register: USBN_USBP_CTL_STATUS[ATE_RESET] = 1 */
647 usbn_usbp_ctl_status.u64 = __cvmx_usb_read_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index));
648 usbn_usbp_ctl_status.s.ate_reset = 1;
649 __cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
650 usbn_usbp_ctl_status.u64);
651 /* 6. Wait 10 cycles */
652 cvmx_wait(10);
653 /* 7. Clear ATE_RESET field in the USBN clock-control register:
654 USBN_USBP_CTL_STATUS[ATE_RESET] = 0 */
655 usbn_usbp_ctl_status.s.ate_reset = 0;
656 __cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
657 usbn_usbp_ctl_status.u64);
658 /* 8. Program the PHY reset field in the USBN clock-control register:
659 USBN_CLK_CTL[PRST] = 1 */
660 usbn_clk_ctl.s.prst = 1;
661 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
662 usbn_clk_ctl.u64);
663 /* 9. Program the USBP control and status register to select host or
664 device mode. USBN_USBP_CTL_STATUS[HST_MODE] = 0 for host, = 1 for
665 device */
666 usbn_usbp_ctl_status.s.hst_mode = 0;
667 __cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
668 usbn_usbp_ctl_status.u64);
669 /* 10. Wait 1 us */
670 udelay(1);
671 /* 11. Program the hreset_n field in the USBN clock-control register:
672 USBN_CLK_CTL[HRST] = 1 */
673 usbn_clk_ctl.s.hrst = 1;
674 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
675 usbn_clk_ctl.u64);
676 /* 12. Proceed to USB core initialization */
677 usbn_clk_ctl.s.enable = 1;
678 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
679 usbn_clk_ctl.u64);
680 udelay(1);
681
682 /* USB Core Initialization */
683
684 /* 1. Read USBC_GHWCFG1, USBC_GHWCFG2, USBC_GHWCFG3, USBC_GHWCFG4 to
685 determine USB core configuration parameters. */
686 /* Nothing needed */
687 /* 2. Program the following fields in the global AHB configuration
688 register (USBC_GAHBCFG)
689 DMA mode, USBC_GAHBCFG[DMAEn]: 1 = DMA mode, 0 = slave mode
690 Burst length, USBC_GAHBCFG[HBSTLEN] = 0
691 Nonperiodic TxFIFO empty level (slave mode only),
692 USBC_GAHBCFG[NPTXFEMPLVL]
693 Periodic TxFIFO empty level (slave mode only),
694 USBC_GAHBCFG[PTXFEMPLVL]
695 Global interrupt mask, USBC_GAHBCFG[GLBLINTRMSK] = 1 */
696 {
697 cvmx_usbcx_gahbcfg_t usbcx_gahbcfg;
698 /* Due to an errata, CN31XX doesn't support DMA */
699 if (OCTEON_IS_MODEL(OCTEON_CN31XX))
700 usb->init_flags |= CVMX_USB_INITIALIZE_FLAGS_NO_DMA;
701 usbcx_gahbcfg.u32 = 0;
702 usbcx_gahbcfg.s.dmaen = !(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA);
703 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
704 usb->idle_hardware_channels = 0x1; /* Only use one channel with non DMA */
705 else if (OCTEON_IS_MODEL(OCTEON_CN5XXX))
706 usb->idle_hardware_channels = 0xf7; /* CN5XXX have an errata with channel 3 */
707 else
708 usb->idle_hardware_channels = 0xff;
709 usbcx_gahbcfg.s.hbstlen = 0;
710 usbcx_gahbcfg.s.nptxfemplvl = 1;
711 usbcx_gahbcfg.s.ptxfemplvl = 1;
712 usbcx_gahbcfg.s.glblintrmsk = 1;
713 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GAHBCFG(usb->index),
714 usbcx_gahbcfg.u32);
715 }
716 /* 3. Program the following fields in USBC_GUSBCFG register.
717 HS/FS timeout calibration, USBC_GUSBCFG[TOUTCAL] = 0
718 ULPI DDR select, USBC_GUSBCFG[DDRSEL] = 0
719 USB turnaround time, USBC_GUSBCFG[USBTRDTIM] = 0x5
720 PHY low-power clock select, USBC_GUSBCFG[PHYLPWRCLKSEL] = 0 */
721 {
722 cvmx_usbcx_gusbcfg_t usbcx_gusbcfg;
723 usbcx_gusbcfg.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GUSBCFG(usb->index));
724 usbcx_gusbcfg.s.toutcal = 0;
725 usbcx_gusbcfg.s.ddrsel = 0;
726 usbcx_gusbcfg.s.usbtrdtim = 0x5;
727 usbcx_gusbcfg.s.phylpwrclksel = 0;
728 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GUSBCFG(usb->index),
729 usbcx_gusbcfg.u32);
730 }
731 /* 4. The software must unmask the following bits in the USBC_GINTMSK
732 register.
733 OTG interrupt mask, USBC_GINTMSK[OTGINTMSK] = 1
734 Mode mismatch interrupt mask, USBC_GINTMSK[MODEMISMSK] = 1 */
735 {
736 cvmx_usbcx_gintmsk_t usbcx_gintmsk;
737 int channel;
738
739 usbcx_gintmsk.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GINTMSK(usb->index));
740 usbcx_gintmsk.s.otgintmsk = 1;
741 usbcx_gintmsk.s.modemismsk = 1;
742 usbcx_gintmsk.s.hchintmsk = 1;
743 usbcx_gintmsk.s.sofmsk = 0;
744 /* We need RX FIFO interrupts if we don't have DMA */
745 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
746 usbcx_gintmsk.s.rxflvlmsk = 1;
747 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTMSK(usb->index),
748 usbcx_gintmsk.u32);
749
750 /* Disable all channel interrupts. We'll enable them per channel later */
751 for (channel=0; channel<8; channel++)
752 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), 0);
753 }
754
755 {
756 /* Host Port Initialization */
757
758 /* 1. Program the host-port interrupt-mask field to unmask,
759 USBC_GINTMSK[PRTINT] = 1 */
760 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), cvmx_usbcx_gintmsk_t,
761 prtintmsk, 1);
762 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), cvmx_usbcx_gintmsk_t,
763 disconnintmsk, 1);
764 /* 2. Program the USBC_HCFG register to select full-speed host or
765 high-speed host. */
766 {
767 cvmx_usbcx_hcfg_t usbcx_hcfg;
768 usbcx_hcfg.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCFG(usb->index));
769 usbcx_hcfg.s.fslssupp = 0;
770 usbcx_hcfg.s.fslspclksel = 0;
771 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCFG(usb->index), usbcx_hcfg.u32);
772 }
773 /* 3. Program the port power bit to drive VBUS on the USB,
774 USBC_HPRT[PRTPWR] = 1 */
775 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), cvmx_usbcx_hprt_t, prtpwr, 1);
776
777 /* Steps 4-15 from the manual are done later in the port enable */
778 }
779
780 return 0;
781 }
782
783
784 /**
785 * Shutdown a USB port after a call to cvmx_usb_initialize().
786 * The port should be disabled with all pipes closed when this
787 * function is called.
788 *
789 * @param state USB device state populated by
790 * cvmx_usb_initialize().
791 *
792 * @return 0 or a negative error code.
793 */
794 int cvmx_usb_shutdown(cvmx_usb_state_t *state)
795 {
796 cvmx_usbnx_clk_ctl_t usbn_clk_ctl;
797 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
798
799 /* Make sure all pipes are closed */
800 if (usb->idle_pipes.head ||
801 usb->active_pipes[CVMX_USB_TRANSFER_ISOCHRONOUS].head ||
802 usb->active_pipes[CVMX_USB_TRANSFER_INTERRUPT].head ||
803 usb->active_pipes[CVMX_USB_TRANSFER_CONTROL].head ||
804 usb->active_pipes[CVMX_USB_TRANSFER_BULK].head)
805 return -EBUSY;
806
807 /* Disable the clocks and put them in power on reset */
808 usbn_clk_ctl.u64 = __cvmx_usb_read_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index));
809 usbn_clk_ctl.s.enable = 1;
810 usbn_clk_ctl.s.por = 1;
811 usbn_clk_ctl.s.hclk_rst = 1;
812 usbn_clk_ctl.s.prst = 0;
813 usbn_clk_ctl.s.hrst = 0;
814 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
815 usbn_clk_ctl.u64);
816 return 0;
817 }
818
819
820 /**
821 * Enable a USB port. After this call succeeds, the USB port is
822 * online and servicing requests.
823 *
824 * @param state USB device state populated by
825 * cvmx_usb_initialize().
826 *
827 * @return 0 or a negative error code.
828 */
829 int cvmx_usb_enable(cvmx_usb_state_t *state)
830 {
831 cvmx_usbcx_ghwcfg3_t usbcx_ghwcfg3;
832 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
833
834 usb->usbcx_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
835
836 /* If the port is already enabled the just return. We don't need to do
837 anything */
838 if (usb->usbcx_hprt.s.prtena)
839 return 0;
840
841 /* If there is nothing plugged into the port then fail immediately */
842 if (!usb->usbcx_hprt.s.prtconnsts) {
843 return -ETIMEDOUT;
844 }
845
846 /* Program the port reset bit to start the reset process */
847 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), cvmx_usbcx_hprt_t, prtrst, 1);
848
849 /* Wait at least 50ms (high speed), or 10ms (full speed) for the reset
850 process to complete. */
851 mdelay(50);
852
853 /* Program the port reset bit to 0, USBC_HPRT[PRTRST] = 0 */
854 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), cvmx_usbcx_hprt_t, prtrst, 0);
855
856 /* Wait for the USBC_HPRT[PRTENA]. */
857 if (CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_HPRT(usb->index), cvmx_usbcx_hprt_t,
858 prtena, ==, 1, 100000))
859 return -ETIMEDOUT;
860
861 /* Read the port speed field to get the enumerated speed, USBC_HPRT[PRTSPD]. */
862 usb->usbcx_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
863 usbcx_ghwcfg3.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GHWCFG3(usb->index));
864
865 /* 13. Program the USBC_GRXFSIZ register to select the size of the receive
866 FIFO (25%). */
867 USB_SET_FIELD32(CVMX_USBCX_GRXFSIZ(usb->index), cvmx_usbcx_grxfsiz_t,
868 rxfdep, usbcx_ghwcfg3.s.dfifodepth / 4);
869 /* 14. Program the USBC_GNPTXFSIZ register to select the size and the
870 start address of the non- periodic transmit FIFO for nonperiodic
871 transactions (50%). */
872 {
873 cvmx_usbcx_gnptxfsiz_t siz;
874 siz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index));
875 siz.s.nptxfdep = usbcx_ghwcfg3.s.dfifodepth / 2;
876 siz.s.nptxfstaddr = usbcx_ghwcfg3.s.dfifodepth / 4;
877 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index), siz.u32);
878 }
879 /* 15. Program the USBC_HPTXFSIZ register to select the size and start
880 address of the periodic transmit FIFO for periodic transactions (25%). */
881 {
882 cvmx_usbcx_hptxfsiz_t siz;
883 siz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPTXFSIZ(usb->index));
884 siz.s.ptxfsize = usbcx_ghwcfg3.s.dfifodepth / 4;
885 siz.s.ptxfstaddr = 3 * usbcx_ghwcfg3.s.dfifodepth / 4;
886 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HPTXFSIZ(usb->index), siz.u32);
887 }
888 /* Flush all FIFOs */
889 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), cvmx_usbcx_grstctl_t, txfnum, 0x10);
890 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), cvmx_usbcx_grstctl_t, txfflsh, 1);
891 CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), cvmx_usbcx_grstctl_t,
892 txfflsh, ==, 0, 100);
893 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), cvmx_usbcx_grstctl_t, rxfflsh, 1);
894 CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), cvmx_usbcx_grstctl_t,
895 rxfflsh, ==, 0, 100);
896
897 return 0;
898 }
899
900
901 /**
902 * Disable a USB port. After this call the USB port will not
903 * generate data transfers and will not generate events.
904 * Transactions in process will fail and call their
905 * associated callbacks.
906 *
907 * @param state USB device state populated by
908 * cvmx_usb_initialize().
909 *
910 * @return 0 or a negative error code.
911 */
912 int cvmx_usb_disable(cvmx_usb_state_t *state)
913 {
914 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
915
916 /* Disable the port */
917 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), cvmx_usbcx_hprt_t, prtena, 1);
918 return 0;
919 }
920
921
922 /**
923 * Get the current state of the USB port. Use this call to
924 * determine if the usb port has anything connected, is enabled,
925 * or has some sort of error condition. The return value of this
926 * call has "changed" bits to signal of the value of some fields
927 * have changed between calls. These "changed" fields are based
928 * on the last call to cvmx_usb_set_status(). In order to clear
929 * them, you must update the status through cvmx_usb_set_status().
930 *
931 * @param state USB device state populated by
932 * cvmx_usb_initialize().
933 *
934 * @return Port status information
935 */
936 cvmx_usb_port_status_t cvmx_usb_get_status(cvmx_usb_state_t *state)
937 {
938 cvmx_usbcx_hprt_t usbc_hprt;
939 cvmx_usb_port_status_t result;
940 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
941
942 memset(&result, 0, sizeof(result));
943
944 usbc_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
945 result.port_enabled = usbc_hprt.s.prtena;
946 result.port_over_current = usbc_hprt.s.prtovrcurract;
947 result.port_powered = usbc_hprt.s.prtpwr;
948 result.port_speed = usbc_hprt.s.prtspd;
949 result.connected = usbc_hprt.s.prtconnsts;
950 result.connect_change = (result.connected != usb->port_status.connected);
951
952 return result;
953 }
954
955
956 /**
957 * Set the current state of the USB port. The status is used as
958 * a reference for the "changed" bits returned by
959 * cvmx_usb_get_status(). Other than serving as a reference, the
960 * status passed to this function is not used. No fields can be
961 * changed through this call.
962 *
963 * @param state USB device state populated by
964 * cvmx_usb_initialize().
965 * @param port_status
966 * Port status to set, most like returned by cvmx_usb_get_status()
967 */
968 void cvmx_usb_set_status(cvmx_usb_state_t *state, cvmx_usb_port_status_t port_status)
969 {
970 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
971 usb->port_status = port_status;
972 return;
973 }
974
975
976 /**
977 * @INTERNAL
978 * Convert a USB transaction into a handle
979 *
980 * @param usb USB device state populated by
981 * cvmx_usb_initialize().
982 * @param transaction
983 * Transaction to get handle for
984 *
985 * @return Handle
986 */
987 static inline int __cvmx_usb_get_submit_handle(cvmx_usb_internal_state_t *usb,
988 cvmx_usb_transaction_t *transaction)
989 {
990 return ((unsigned long)transaction - (unsigned long)usb->transaction) /
991 sizeof(*transaction);
992 }
993
994
995 /**
996 * @INTERNAL
997 * Convert a USB pipe into a handle
998 *
999 * @param usb USB device state populated by
1000 * cvmx_usb_initialize().
1001 * @param pipe Pipe to get handle for
1002 *
1003 * @return Handle
1004 */
1005 static inline int __cvmx_usb_get_pipe_handle(cvmx_usb_internal_state_t *usb,
1006 cvmx_usb_pipe_t *pipe)
1007 {
1008 return ((unsigned long)pipe - (unsigned long)usb->pipe) / sizeof(*pipe);
1009 }
1010
1011
1012 /**
1013 * Open a virtual pipe between the host and a USB device. A pipe
1014 * must be opened before data can be transferred between a device
1015 * and Octeon.
1016 *
1017 * @param state USB device state populated by
1018 * cvmx_usb_initialize().
1019 * @param flags Optional pipe flags defined in
1020 * cvmx_usb_pipe_flags_t.
1021 * @param device_addr
1022 * USB device address to open the pipe to
1023 * (0-127).
1024 * @param endpoint_num
1025 * USB endpoint number to open the pipe to
1026 * (0-15).
1027 * @param device_speed
1028 * The speed of the device the pipe is going
1029 * to. This must match the device's speed,
1030 * which may be different than the port speed.
1031 * @param max_packet The maximum packet length the device can
1032 * transmit/receive (low speed=0-8, full
1033 * speed=0-1023, high speed=0-1024). This value
1034 * comes from the standard endpoint descriptor
1035 * field wMaxPacketSize bits <10:0>.
1036 * @param transfer_type
1037 * The type of transfer this pipe is for.
1038 * @param transfer_dir
1039 * The direction the pipe is in. This is not
1040 * used for control pipes.
1041 * @param interval For ISOCHRONOUS and INTERRUPT transfers,
1042 * this is how often the transfer is scheduled
1043 * for. All other transfers should specify
1044 * zero. The units are in frames (8000/sec at
1045 * high speed, 1000/sec for full speed).
1046 * @param multi_count
1047 * For high speed devices, this is the maximum
1048 * allowed number of packet per microframe.
1049 * Specify zero for non high speed devices. This
1050 * value comes from the standard endpoint descriptor
1051 * field wMaxPacketSize bits <12:11>.
1052 * @param hub_device_addr
1053 * Hub device address this device is connected
1054 * to. Devices connected directly to Octeon
1055 * use zero. This is only used when the device
1056 * is full/low speed behind a high speed hub.
1057 * The address will be of the high speed hub,
1058 * not and full speed hubs after it.
1059 * @param hub_port Which port on the hub the device is
1060 * connected. Use zero for devices connected
1061 * directly to Octeon. Like hub_device_addr,
1062 * this is only used for full/low speed
1063 * devices behind a high speed hub.
1064 *
1065 * @return A non negative value is a pipe handle. Negative
1066 * values are error codes.
1067 */
1068 int cvmx_usb_open_pipe(cvmx_usb_state_t *state, cvmx_usb_pipe_flags_t flags,
1069 int device_addr, int endpoint_num,
1070 cvmx_usb_speed_t device_speed, int max_packet,
1071 cvmx_usb_transfer_t transfer_type,
1072 cvmx_usb_direction_t transfer_dir, int interval,
1073 int multi_count, int hub_device_addr, int hub_port)
1074 {
1075 cvmx_usb_pipe_t *pipe;
1076 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
1077
1078 if (unlikely((device_addr < 0) || (device_addr > MAX_USB_ADDRESS)))
1079 return -EINVAL;
1080 if (unlikely((endpoint_num < 0) || (endpoint_num > MAX_USB_ENDPOINT)))
1081 return -EINVAL;
1082 if (unlikely(device_speed > CVMX_USB_SPEED_LOW))
1083 return -EINVAL;
1084 if (unlikely((max_packet <= 0) || (max_packet > 1024)))
1085 return -EINVAL;
1086 if (unlikely(transfer_type > CVMX_USB_TRANSFER_INTERRUPT))
1087 return -EINVAL;
1088 if (unlikely((transfer_dir != CVMX_USB_DIRECTION_OUT) &&
1089 (transfer_dir != CVMX_USB_DIRECTION_IN)))
1090 return -EINVAL;
1091 if (unlikely(interval < 0))
1092 return -EINVAL;
1093 if (unlikely((transfer_type == CVMX_USB_TRANSFER_CONTROL) && interval))
1094 return -EINVAL;
1095 if (unlikely(multi_count < 0))
1096 return -EINVAL;
1097 if (unlikely((device_speed != CVMX_USB_SPEED_HIGH) &&
1098 (multi_count != 0)))
1099 return -EINVAL;
1100 if (unlikely((hub_device_addr < 0) || (hub_device_addr > MAX_USB_ADDRESS)))
1101 return -EINVAL;
1102 if (unlikely((hub_port < 0) || (hub_port > MAX_USB_HUB_PORT)))
1103 return -EINVAL;
1104
1105 /* Find a free pipe */
1106 pipe = usb->free_pipes.head;
1107 if (!pipe)
1108 return -ENOMEM;
1109 __cvmx_usb_remove_pipe(&usb->free_pipes, pipe);
1110 pipe->flags = flags | __CVMX_USB_PIPE_FLAGS_OPEN;
1111 if ((device_speed == CVMX_USB_SPEED_HIGH) &&
1112 (transfer_dir == CVMX_USB_DIRECTION_OUT) &&
1113 (transfer_type == CVMX_USB_TRANSFER_BULK))
1114 pipe->flags |= __CVMX_USB_PIPE_FLAGS_NEED_PING;
1115 pipe->device_addr = device_addr;
1116 pipe->endpoint_num = endpoint_num;
1117 pipe->device_speed = device_speed;
1118 pipe->max_packet = max_packet;
1119 pipe->transfer_type = transfer_type;
1120 pipe->transfer_dir = transfer_dir;
1121 /* All pipes use interval to rate limit NAK processing. Force an interval
1122 if one wasn't supplied */
1123 if (!interval)
1124 interval = 1;
1125 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1126 pipe->interval = interval*8;
1127 /* Force start splits to be schedule on uFrame 0 */
1128 pipe->next_tx_frame = ((usb->frame_number+7)&~7) + pipe->interval;
1129 }
1130 else {
1131 pipe->interval = interval;
1132 pipe->next_tx_frame = usb->frame_number + pipe->interval;
1133 }
1134 pipe->multi_count = multi_count;
1135 pipe->hub_device_addr = hub_device_addr;
1136 pipe->hub_port = hub_port;
1137 pipe->pid_toggle = 0;
1138 pipe->split_sc_frame = -1;
1139 __cvmx_usb_append_pipe(&usb->idle_pipes, pipe);
1140
1141 /* We don't need to tell the hardware about this pipe yet since
1142 it doesn't have any submitted requests */
1143
1144 return __cvmx_usb_get_pipe_handle(usb, pipe);
1145 }
1146
1147
1148 /**
1149 * @INTERNAL
1150 * Poll the RX FIFOs and remove data as needed. This function is only used
1151 * in non DMA mode. It is very important that this function be called quickly
1152 * enough to prevent FIFO overflow.
1153 *
1154 * @param usb USB device state populated by
1155 * cvmx_usb_initialize().
1156 */
1157 static void __cvmx_usb_poll_rx_fifo(cvmx_usb_internal_state_t *usb)
1158 {
1159 cvmx_usbcx_grxstsph_t rx_status;
1160 int channel;
1161 int bytes;
1162 uint64_t address;
1163 uint32_t *ptr;
1164
1165 rx_status.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GRXSTSPH(usb->index));
1166 /* Only read data if IN data is there */
1167 if (rx_status.s.pktsts != 2)
1168 return;
1169 /* Check if no data is available */
1170 if (!rx_status.s.bcnt)
1171 return;
1172
1173 channel = rx_status.s.chnum;
1174 bytes = rx_status.s.bcnt;
1175 if (!bytes)
1176 return;
1177
1178 /* Get where the DMA engine would have written this data */
1179 address = __cvmx_usb_read_csr64(usb, CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8);
1180 ptr = cvmx_phys_to_ptr(address);
1181 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8, address + bytes);
1182
1183 /* Loop writing the FIFO data for this packet into memory */
1184 while (bytes > 0) {
1185 *ptr++ = __cvmx_usb_read_csr32(usb, USB_FIFO_ADDRESS(channel, usb->index));
1186 bytes -= 4;
1187 }
1188 CVMX_SYNCW;
1189
1190 return;
1191 }
1192
1193
1194 /**
1195 * Fill the TX hardware fifo with data out of the software
1196 * fifos
1197 *
1198 * @param usb USB device state populated by
1199 * cvmx_usb_initialize().
1200 * @param fifo Software fifo to use
1201 * @param available Amount of space in the hardware fifo
1202 *
1203 * @return Non zero if the hardware fifo was too small and needs
1204 * to be serviced again.
1205 */
1206 static int __cvmx_usb_fill_tx_hw(cvmx_usb_internal_state_t *usb, cvmx_usb_tx_fifo_t *fifo, int available)
1207 {
1208 /* We're done either when there isn't anymore space or the software FIFO
1209 is empty */
1210 while (available && (fifo->head != fifo->tail)) {
1211 int i = fifo->tail;
1212 const uint32_t *ptr = cvmx_phys_to_ptr(fifo->entry[i].address);
1213 uint64_t csr_address = USB_FIFO_ADDRESS(fifo->entry[i].channel, usb->index) ^ 4;
1214 int words = available;
1215
1216 /* Limit the amount of data to waht the SW fifo has */
1217 if (fifo->entry[i].size <= available) {
1218 words = fifo->entry[i].size;
1219 fifo->tail++;
1220 if (fifo->tail > MAX_CHANNELS)
1221 fifo->tail = 0;
1222 }
1223
1224 /* Update the next locations and counts */
1225 available -= words;
1226 fifo->entry[i].address += words * 4;
1227 fifo->entry[i].size -= words;
1228
1229 /* Write the HW fifo data. The read every three writes is due
1230 to an errata on CN3XXX chips */
1231 while (words > 3) {
1232 cvmx_write64_uint32(csr_address, *ptr++);
1233 cvmx_write64_uint32(csr_address, *ptr++);
1234 cvmx_write64_uint32(csr_address, *ptr++);
1235 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
1236 words -= 3;
1237 }
1238 cvmx_write64_uint32(csr_address, *ptr++);
1239 if (--words) {
1240 cvmx_write64_uint32(csr_address, *ptr++);
1241 if (--words)
1242 cvmx_write64_uint32(csr_address, *ptr++);
1243 }
1244 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
1245 }
1246 return fifo->head != fifo->tail;
1247 }
1248
1249
1250 /**
1251 * Check the hardware FIFOs and fill them as needed
1252 *
1253 * @param usb USB device state populated by
1254 * cvmx_usb_initialize().
1255 */
1256 static void __cvmx_usb_poll_tx_fifo(cvmx_usb_internal_state_t *usb)
1257 {
1258 if (usb->periodic.head != usb->periodic.tail) {
1259 cvmx_usbcx_hptxsts_t tx_status;
1260 tx_status.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPTXSTS(usb->index));
1261 if (__cvmx_usb_fill_tx_hw(usb, &usb->periodic, tx_status.s.ptxfspcavail))
1262 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), cvmx_usbcx_gintmsk_t, ptxfempmsk, 1);
1263 else
1264 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), cvmx_usbcx_gintmsk_t, ptxfempmsk, 0);
1265 }
1266
1267 if (usb->nonperiodic.head != usb->nonperiodic.tail) {
1268 cvmx_usbcx_gnptxsts_t tx_status;
1269 tx_status.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GNPTXSTS(usb->index));
1270 if (__cvmx_usb_fill_tx_hw(usb, &usb->nonperiodic, tx_status.s.nptxfspcavail))
1271 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), cvmx_usbcx_gintmsk_t, nptxfempmsk, 1);
1272 else
1273 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), cvmx_usbcx_gintmsk_t, nptxfempmsk, 0);
1274 }
1275
1276 return;
1277 }
1278
1279
1280 /**
1281 * @INTERNAL
1282 * Fill the TX FIFO with an outgoing packet
1283 *
1284 * @param usb USB device state populated by
1285 * cvmx_usb_initialize().
1286 * @param channel Channel number to get packet from
1287 */
1288 static void __cvmx_usb_fill_tx_fifo(cvmx_usb_internal_state_t *usb, int channel)
1289 {
1290 cvmx_usbcx_hccharx_t hcchar;
1291 cvmx_usbcx_hcspltx_t usbc_hcsplt;
1292 cvmx_usbcx_hctsizx_t usbc_hctsiz;
1293 cvmx_usb_tx_fifo_t *fifo;
1294
1295 /* We only need to fill data on outbound channels */
1296 hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index));
1297 if (hcchar.s.epdir != CVMX_USB_DIRECTION_OUT)
1298 return;
1299
1300 /* OUT Splits only have data on the start and not the complete */
1301 usbc_hcsplt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCSPLTX(channel, usb->index));
1302 if (usbc_hcsplt.s.spltena && usbc_hcsplt.s.compsplt)
1303 return;
1304
1305 /* Find out how many bytes we need to fill and convert it into 32bit words */
1306 usbc_hctsiz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index));
1307 if (!usbc_hctsiz.s.xfersize)
1308 return;
1309
1310 if ((hcchar.s.eptype == CVMX_USB_TRANSFER_INTERRUPT) ||
1311 (hcchar.s.eptype == CVMX_USB_TRANSFER_ISOCHRONOUS))
1312 fifo = &usb->periodic;
1313 else
1314 fifo = &usb->nonperiodic;
1315
1316 fifo->entry[fifo->head].channel = channel;
1317 fifo->entry[fifo->head].address = __cvmx_usb_read_csr64(usb, CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8);
1318 fifo->entry[fifo->head].size = (usbc_hctsiz.s.xfersize+3)>>2;
1319 fifo->head++;
1320 if (fifo->head > MAX_CHANNELS)
1321 fifo->head = 0;
1322
1323 __cvmx_usb_poll_tx_fifo(usb);
1324
1325 return;
1326 }
1327
1328 /**
1329 * @INTERNAL
1330 * Perform channel specific setup for Control transactions. All
1331 * the generic stuff will already have been done in
1332 * __cvmx_usb_start_channel()
1333 *
1334 * @param usb USB device state populated by
1335 * cvmx_usb_initialize().
1336 * @param channel Channel to setup
1337 * @param pipe Pipe for control transaction
1338 */
1339 static void __cvmx_usb_start_channel_control(cvmx_usb_internal_state_t *usb,
1340 int channel,
1341 cvmx_usb_pipe_t *pipe)
1342 {
1343 cvmx_usb_transaction_t *transaction = pipe->head;
1344 cvmx_usb_control_header_t *header = cvmx_phys_to_ptr(transaction->control_header);
1345 int bytes_to_transfer = transaction->buffer_length - transaction->actual_bytes;
1346 int packets_to_transfer;
1347 cvmx_usbcx_hctsizx_t usbc_hctsiz;
1348
1349 usbc_hctsiz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index));
1350
1351 switch (transaction->stage) {
1352 case CVMX_USB_STAGE_NON_CONTROL:
1353 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE:
1354 cvmx_dprintf("%s: ERROR - Non control stage\n", __FUNCTION__);
1355 break;
1356 case CVMX_USB_STAGE_SETUP:
1357 usbc_hctsiz.s.pid = 3; /* Setup */
1358 bytes_to_transfer = sizeof(*header);
1359 /* All Control operations start with a setup going OUT */
1360 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), cvmx_usbcx_hccharx_t, epdir, CVMX_USB_DIRECTION_OUT);
1361 /* Setup send the control header instead of the buffer data. The
1362 buffer data will be used in the next stage */
1363 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8, transaction->control_header);
1364 break;
1365 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE:
1366 usbc_hctsiz.s.pid = 3; /* Setup */
1367 bytes_to_transfer = 0;
1368 /* All Control operations start with a setup going OUT */
1369 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), cvmx_usbcx_hccharx_t, epdir, CVMX_USB_DIRECTION_OUT);
1370 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), cvmx_usbcx_hcspltx_t, compsplt, 1);
1371 break;
1372 case CVMX_USB_STAGE_DATA:
1373 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1374 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1375 if (header->s.request_type & 0x80)
1376 bytes_to_transfer = 0;
1377 else if (bytes_to_transfer > pipe->max_packet)
1378 bytes_to_transfer = pipe->max_packet;
1379 }
1380 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1381 cvmx_usbcx_hccharx_t, epdir,
1382 ((header->s.request_type & 0x80) ?
1383 CVMX_USB_DIRECTION_IN :
1384 CVMX_USB_DIRECTION_OUT));
1385 break;
1386 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE:
1387 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1388 if (!(header->s.request_type & 0x80))
1389 bytes_to_transfer = 0;
1390 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1391 cvmx_usbcx_hccharx_t, epdir,
1392 ((header->s.request_type & 0x80) ?
1393 CVMX_USB_DIRECTION_IN :
1394 CVMX_USB_DIRECTION_OUT));
1395 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), cvmx_usbcx_hcspltx_t, compsplt, 1);
1396 break;
1397 case CVMX_USB_STAGE_STATUS:
1398 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1399 bytes_to_transfer = 0;
1400 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), cvmx_usbcx_hccharx_t, epdir,
1401 ((header->s.request_type & 0x80) ?
1402 CVMX_USB_DIRECTION_OUT :
1403 CVMX_USB_DIRECTION_IN));
1404 break;
1405 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE:
1406 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1407 bytes_to_transfer = 0;
1408 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), cvmx_usbcx_hccharx_t, epdir,
1409 ((header->s.request_type & 0x80) ?
1410 CVMX_USB_DIRECTION_OUT :
1411 CVMX_USB_DIRECTION_IN));
1412 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), cvmx_usbcx_hcspltx_t, compsplt, 1);
1413 break;
1414 }
1415
1416 /* Make sure the transfer never exceeds the byte limit of the hardware.
1417 Further bytes will be sent as continued transactions */
1418 if (bytes_to_transfer > MAX_TRANSFER_BYTES) {
1419 /* Round MAX_TRANSFER_BYTES to a multiple of out packet size */
1420 bytes_to_transfer = MAX_TRANSFER_BYTES / pipe->max_packet;
1421 bytes_to_transfer *= pipe->max_packet;
1422 }
1423
1424 /* Calculate the number of packets to transfer. If the length is zero
1425 we still need to transfer one packet */
1426 packets_to_transfer = (bytes_to_transfer + pipe->max_packet - 1) / pipe->max_packet;
1427 if (packets_to_transfer == 0)
1428 packets_to_transfer = 1;
1429 else if ((packets_to_transfer>1) && (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)) {
1430 /* Limit to one packet when not using DMA. Channels must be restarted
1431 between every packet for IN transactions, so there is no reason to
1432 do multiple packets in a row */
1433 packets_to_transfer = 1;
1434 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1435 }
1436 else if (packets_to_transfer > MAX_TRANSFER_PACKETS) {
1437 /* Limit the number of packet and data transferred to what the
1438 hardware can handle */
1439 packets_to_transfer = MAX_TRANSFER_PACKETS;
1440 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1441 }
1442
1443 usbc_hctsiz.s.xfersize = bytes_to_transfer;
1444 usbc_hctsiz.s.pktcnt = packets_to_transfer;
1445
1446 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index), usbc_hctsiz.u32);
1447 return;
1448 }
1449
1450
1451 /**
1452 * @INTERNAL
1453 * Start a channel to perform the pipe's head transaction
1454 *
1455 * @param usb USB device state populated by
1456 * cvmx_usb_initialize().
1457 * @param channel Channel to setup
1458 * @param pipe Pipe to start
1459 */
1460 static void __cvmx_usb_start_channel(cvmx_usb_internal_state_t *usb,
1461 int channel,
1462 cvmx_usb_pipe_t *pipe)
1463 {
1464 cvmx_usb_transaction_t *transaction = pipe->head;
1465
1466 /* Make sure all writes to the DMA region get flushed */
1467 CVMX_SYNCW;
1468
1469 /* Attach the channel to the pipe */
1470 usb->pipe_for_channel[channel] = pipe;
1471 pipe->channel = channel;
1472 pipe->flags |= __CVMX_USB_PIPE_FLAGS_SCHEDULED;
1473
1474 /* Mark this channel as in use */
1475 usb->idle_hardware_channels &= ~(1<<channel);
1476
1477 /* Enable the channel interrupt bits */
1478 {
1479 cvmx_usbcx_hcintx_t usbc_hcint;
1480 cvmx_usbcx_hcintmskx_t usbc_hcintmsk;
1481 cvmx_usbcx_haintmsk_t usbc_haintmsk;
1482
1483 /* Clear all channel status bits */
1484 usbc_hcint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCINTX(channel, usb->index));
1485 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTX(channel, usb->index), usbc_hcint.u32);
1486
1487 usbc_hcintmsk.u32 = 0;
1488 usbc_hcintmsk.s.chhltdmsk = 1;
1489 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) {
1490 /* Channels need these extra interrupts when we aren't in DMA mode */
1491 usbc_hcintmsk.s.datatglerrmsk = 1;
1492 usbc_hcintmsk.s.frmovrunmsk = 1;
1493 usbc_hcintmsk.s.bblerrmsk = 1;
1494 usbc_hcintmsk.s.xacterrmsk = 1;
1495 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1496 /* Splits don't generate xfercompl, so we need ACK and NYET */
1497 usbc_hcintmsk.s.nyetmsk = 1;
1498 usbc_hcintmsk.s.ackmsk = 1;
1499 }
1500 usbc_hcintmsk.s.nakmsk = 1;
1501 usbc_hcintmsk.s.stallmsk = 1;
1502 usbc_hcintmsk.s.xfercomplmsk = 1;
1503 }
1504 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), usbc_hcintmsk.u32);
1505
1506 /* Enable the channel interrupt to propagate */
1507 usbc_haintmsk.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HAINTMSK(usb->index));
1508 usbc_haintmsk.s.haintmsk |= 1<<channel;
1509 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HAINTMSK(usb->index), usbc_haintmsk.u32);
1510 }
1511
1512 /* Setup the locations the DMA engines use */
1513 {
1514 uint64_t dma_address = transaction->buffer + transaction->actual_bytes;
1515 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
1516 dma_address = transaction->buffer + transaction->iso_packets[0].offset + transaction->actual_bytes;
1517 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8, dma_address);
1518 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8, dma_address);
1519 }
1520
1521 /* Setup both the size of the transfer and the SPLIT characteristics */
1522 {
1523 cvmx_usbcx_hcspltx_t usbc_hcsplt = {.u32 = 0};
1524 cvmx_usbcx_hctsizx_t usbc_hctsiz = {.u32 = 0};
1525 int packets_to_transfer;
1526 int bytes_to_transfer = transaction->buffer_length - transaction->actual_bytes;
1527
1528 /* ISOCHRONOUS transactions store each individual transfer size in the
1529 packet structure, not the global buffer_length */
1530 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
1531 bytes_to_transfer = transaction->iso_packets[0].length - transaction->actual_bytes;
1532
1533 /* We need to do split transactions when we are talking to non high
1534 speed devices that are behind a high speed hub */
1535 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1536 /* On the start split phase (stage is even) record the frame number we
1537 will need to send the split complete. We only store the lower two bits
1538 since the time ahead can only be two frames */
1539 if ((transaction->stage&1) == 0) {
1540 if (transaction->type == CVMX_USB_TRANSFER_BULK)
1541 pipe->split_sc_frame = (usb->frame_number + 1) & 0x7f;
1542 else
1543 pipe->split_sc_frame = (usb->frame_number + 2) & 0x7f;
1544 }
1545 else
1546 pipe->split_sc_frame = -1;
1547
1548 usbc_hcsplt.s.spltena = 1;
1549 usbc_hcsplt.s.hubaddr = pipe->hub_device_addr;
1550 usbc_hcsplt.s.prtaddr = pipe->hub_port;
1551 usbc_hcsplt.s.compsplt = (transaction->stage == CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE);
1552
1553 /* SPLIT transactions can only ever transmit one data packet so
1554 limit the transfer size to the max packet size */
1555 if (bytes_to_transfer > pipe->max_packet)
1556 bytes_to_transfer = pipe->max_packet;
1557
1558 /* ISOCHRONOUS OUT splits are unique in that they limit
1559 data transfers to 188 byte chunks representing the
1560 begin/middle/end of the data or all */
1561 if (!usbc_hcsplt.s.compsplt &&
1562 (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) &&
1563 (pipe->transfer_type == CVMX_USB_TRANSFER_ISOCHRONOUS)) {
1564 /* Clear the split complete frame number as there isn't going
1565 to be a split complete */
1566 pipe->split_sc_frame = -1;
1567 /* See if we've started this transfer and sent data */
1568 if (transaction->actual_bytes == 0) {
1569 /* Nothing sent yet, this is either a begin or the
1570 entire payload */
1571 if (bytes_to_transfer <= 188)
1572 usbc_hcsplt.s.xactpos = 3; /* Entire payload in one go */
1573 else
1574 usbc_hcsplt.s.xactpos = 2; /* First part of payload */
1575 }
1576 else {
1577 /* Continuing the previous data, we must either be
1578 in the middle or at the end */
1579 if (bytes_to_transfer <= 188)
1580 usbc_hcsplt.s.xactpos = 1; /* End of payload */
1581 else
1582 usbc_hcsplt.s.xactpos = 0; /* Middle of payload */
1583 }
1584 /* Again, the transfer size is limited to 188 bytes */
1585 if (bytes_to_transfer > 188)
1586 bytes_to_transfer = 188;
1587 }
1588 }
1589
1590 /* Make sure the transfer never exceeds the byte limit of the hardware.
1591 Further bytes will be sent as continued transactions */
1592 if (bytes_to_transfer > MAX_TRANSFER_BYTES) {
1593 /* Round MAX_TRANSFER_BYTES to a multiple of out packet size */
1594 bytes_to_transfer = MAX_TRANSFER_BYTES / pipe->max_packet;
1595 bytes_to_transfer *= pipe->max_packet;
1596 }
1597
1598 /* Calculate the number of packets to transfer. If the length is zero
1599 we still need to transfer one packet */
1600 packets_to_transfer = (bytes_to_transfer + pipe->max_packet - 1) / pipe->max_packet;
1601 if (packets_to_transfer == 0)
1602 packets_to_transfer = 1;
1603 else if ((packets_to_transfer>1) && (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)) {
1604 /* Limit to one packet when not using DMA. Channels must be restarted
1605 between every packet for IN transactions, so there is no reason to
1606 do multiple packets in a row */
1607 packets_to_transfer = 1;
1608 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1609 }
1610 else if (packets_to_transfer > MAX_TRANSFER_PACKETS) {
1611 /* Limit the number of packet and data transferred to what the
1612 hardware can handle */
1613 packets_to_transfer = MAX_TRANSFER_PACKETS;
1614 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1615 }
1616
1617 usbc_hctsiz.s.xfersize = bytes_to_transfer;
1618 usbc_hctsiz.s.pktcnt = packets_to_transfer;
1619
1620 /* Update the DATA0/DATA1 toggle */
1621 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1622 /* High speed pipes may need a hardware ping before they start */
1623 if (pipe->flags & __CVMX_USB_PIPE_FLAGS_NEED_PING)
1624 usbc_hctsiz.s.dopng = 1;
1625
1626 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCSPLTX(channel, usb->index), usbc_hcsplt.u32);
1627 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index), usbc_hctsiz.u32);
1628 }
1629
1630 /* Setup the Host Channel Characteristics Register */
1631 {
1632 cvmx_usbcx_hccharx_t usbc_hcchar = {.u32 = 0};
1633
1634 /* Set the startframe odd/even properly. This is only used for periodic */
1635 usbc_hcchar.s.oddfrm = usb->frame_number&1;
1636
1637 /* Set the number of back to back packets allowed by this endpoint.
1638 Split transactions interpret "ec" as the number of immediate
1639 retries of failure. These retries happen too quickly, so we
1640 disable these entirely for splits */
1641 if (__cvmx_usb_pipe_needs_split(usb, pipe))
1642 usbc_hcchar.s.ec = 1;
1643 else if (pipe->multi_count < 1)
1644 usbc_hcchar.s.ec = 1;
1645 else if (pipe->multi_count > 3)
1646 usbc_hcchar.s.ec = 3;
1647 else
1648 usbc_hcchar.s.ec = pipe->multi_count;
1649
1650 /* Set the rest of the endpoint specific settings */
1651 usbc_hcchar.s.devaddr = pipe->device_addr;
1652 usbc_hcchar.s.eptype = transaction->type;
1653 usbc_hcchar.s.lspddev = (pipe->device_speed == CVMX_USB_SPEED_LOW);
1654 usbc_hcchar.s.epdir = pipe->transfer_dir;
1655 usbc_hcchar.s.epnum = pipe->endpoint_num;
1656 usbc_hcchar.s.mps = pipe->max_packet;
1657 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index), usbc_hcchar.u32);
1658 }
1659
1660 /* Do transaction type specific fixups as needed */
1661 switch (transaction->type) {
1662 case CVMX_USB_TRANSFER_CONTROL:
1663 __cvmx_usb_start_channel_control(usb, channel, pipe);
1664 break;
1665 case CVMX_USB_TRANSFER_BULK:
1666 case CVMX_USB_TRANSFER_INTERRUPT:
1667 break;
1668 case CVMX_USB_TRANSFER_ISOCHRONOUS:
1669 if (!__cvmx_usb_pipe_needs_split(usb, pipe)) {
1670 /* ISO transactions require different PIDs depending on direction
1671 and how many packets are needed */
1672 if (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) {
1673 if (pipe->multi_count < 2) /* Need DATA0 */
1674 USB_SET_FIELD32(CVMX_USBCX_HCTSIZX(channel, usb->index), cvmx_usbcx_hctsizx_t, pid, 0);
1675 else /* Need MDATA */
1676 USB_SET_FIELD32(CVMX_USBCX_HCTSIZX(channel, usb->index), cvmx_usbcx_hctsizx_t, pid, 3);
1677 }
1678 }
1679 break;
1680 }
1681 {
1682 cvmx_usbcx_hctsizx_t usbc_hctsiz = {.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index))};
1683 transaction->xfersize = usbc_hctsiz.s.xfersize;
1684 transaction->pktcnt = usbc_hctsiz.s.pktcnt;
1685 }
1686 /* Remeber when we start a split transaction */
1687 if (__cvmx_usb_pipe_needs_split(usb, pipe))
1688 usb->active_split = transaction;
1689 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), cvmx_usbcx_hccharx_t, chena, 1);
1690 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
1691 __cvmx_usb_fill_tx_fifo(usb, channel);
1692 return;
1693 }
1694
1695
1696 /**
1697 * @INTERNAL
1698 * Find a pipe that is ready to be scheduled to hardware.
1699 * @param usb USB device state populated by
1700 * cvmx_usb_initialize().
1701 * @param list Pipe list to search
1702 * @param current_frame
1703 * Frame counter to use as a time reference.
1704 *
1705 * @return Pipe or NULL if none are ready
1706 */
1707 static cvmx_usb_pipe_t *__cvmx_usb_find_ready_pipe(cvmx_usb_internal_state_t *usb, cvmx_usb_pipe_list_t *list, uint64_t current_frame)
1708 {
1709 cvmx_usb_pipe_t *pipe = list->head;
1710 while (pipe) {
1711 if (!(pipe->flags & __CVMX_USB_PIPE_FLAGS_SCHEDULED) && pipe->head &&
1712 (pipe->next_tx_frame <= current_frame) &&
1713 ((pipe->split_sc_frame == -1) || ((((int)current_frame - (int)pipe->split_sc_frame) & 0x7f) < 0x40)) &&
1714 (!usb->active_split || (usb->active_split == pipe->head))) {
1715 CVMX_PREFETCH(pipe, 128);
1716 CVMX_PREFETCH(pipe->head, 0);
1717 return pipe;
1718 }
1719 pipe = pipe->next;
1720 }
1721 return NULL;
1722 }
1723
1724
1725 /**
1726 * @INTERNAL
1727 * Called whenever a pipe might need to be scheduled to the
1728 * hardware.
1729 *
1730 * @param usb USB device state populated by
1731 * cvmx_usb_initialize().
1732 * @param is_sof True if this schedule was called on a SOF interrupt.
1733 */
1734 static void __cvmx_usb_schedule(cvmx_usb_internal_state_t *usb, int is_sof)
1735 {
1736 int channel;
1737 cvmx_usb_pipe_t *pipe;
1738 int need_sof;
1739 cvmx_usb_transfer_t ttype;
1740
1741 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) {
1742 /* Without DMA we need to be careful to not schedule something at the end of a frame and cause an overrun */
1743 cvmx_usbcx_hfnum_t hfnum = {.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index))};
1744 cvmx_usbcx_hfir_t hfir = {.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFIR(usb->index))};
1745 if (hfnum.s.frrem < hfir.s.frint/4)
1746 goto done;
1747 }
1748
1749 while (usb->idle_hardware_channels) {
1750 /* Find an idle channel */
1751 CVMX_CLZ(channel, usb->idle_hardware_channels);
1752 channel = 31 - channel;
1753 if (unlikely(channel > 7))
1754 break;
1755
1756 /* Find a pipe needing service */
1757 pipe = NULL;
1758 if (is_sof) {
1759 /* Only process periodic pipes on SOF interrupts. This way we are
1760 sure that the periodic data is sent in the beginning of the
1761 frame */
1762 pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_ISOCHRONOUS, usb->frame_number);
1763 if (likely(!pipe))
1764 pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_INTERRUPT, usb->frame_number);
1765 }
1766 if (likely(!pipe)) {
1767 pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_CONTROL, usb->frame_number);
1768 if (likely(!pipe))
1769 pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_BULK, usb->frame_number);
1770 }
1771 if (!pipe)
1772 break;
1773
1774 __cvmx_usb_start_channel(usb, channel, pipe);
1775 }
1776
1777 done:
1778 /* Only enable SOF interrupts when we have transactions pending in the
1779 future that might need to be scheduled */
1780 need_sof = 0;
1781 for (ttype=CVMX_USB_TRANSFER_CONTROL; ttype<=CVMX_USB_TRANSFER_INTERRUPT; ttype++) {
1782 pipe = usb->active_pipes[ttype].head;
1783 while (pipe) {
1784 if (pipe->next_tx_frame > usb->frame_number) {
1785 need_sof = 1;
1786 break;
1787 }
1788 pipe=pipe->next;
1789 }
1790 }
1791 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), cvmx_usbcx_gintmsk_t, sofmsk, need_sof);
1792 return;
1793 }
1794
1795
1796 /**
1797 * @INTERNAL
1798 * Call a user's callback for a specific reason.
1799 *
1800 * @param usb USB device state populated by
1801 * cvmx_usb_initialize().
1802 * @param pipe Pipe the callback is for or NULL
1803 * @param transaction
1804 * Transaction the callback is for or NULL
1805 * @param reason Reason this callback is being called
1806 * @param complete_code
1807 * Completion code for the transaction, if any
1808 */
1809 static void __cvmx_usb_perform_callback(cvmx_usb_internal_state_t *usb,
1810 cvmx_usb_pipe_t *pipe,
1811 cvmx_usb_transaction_t *transaction,
1812 cvmx_usb_callback_t reason,
1813 cvmx_usb_complete_t complete_code)
1814 {
1815 cvmx_usb_callback_func_t callback = usb->callback[reason];
1816 void *user_data = usb->callback_data[reason];
1817 int submit_handle = -1;
1818 int pipe_handle = -1;
1819 int bytes_transferred = 0;
1820
1821 if (pipe)
1822 pipe_handle = __cvmx_usb_get_pipe_handle(usb, pipe);
1823
1824 if (transaction) {
1825 submit_handle = __cvmx_usb_get_submit_handle(usb, transaction);
1826 bytes_transferred = transaction->actual_bytes;
1827 /* Transactions are allowed to override the default callback */
1828 if ((reason == CVMX_USB_CALLBACK_TRANSFER_COMPLETE) && transaction->callback) {
1829 callback = transaction->callback;
1830 user_data = transaction->callback_data;
1831 }
1832 }
1833
1834 if (!callback)
1835 return;
1836
1837 callback((cvmx_usb_state_t *)usb, reason, complete_code, pipe_handle, submit_handle,
1838 bytes_transferred, user_data);
1839 }
1840
1841
1842 /**
1843 * @INTERNAL
1844 * Signal the completion of a transaction and free it. The
1845 * transaction will be removed from the pipe transaction list.
1846 *
1847 * @param usb USB device state populated by
1848 * cvmx_usb_initialize().
1849 * @param pipe Pipe the transaction is on
1850 * @param transaction
1851 * Transaction that completed
1852 * @param complete_code
1853 * Completion code
1854 */
1855 static void __cvmx_usb_perform_complete(cvmx_usb_internal_state_t * usb,
1856 cvmx_usb_pipe_t *pipe,
1857 cvmx_usb_transaction_t *transaction,
1858 cvmx_usb_complete_t complete_code)
1859 {
1860 /* If this was a split then clear our split in progress marker */
1861 if (usb->active_split == transaction)
1862 usb->active_split = NULL;
1863
1864 /* Isochronous transactions need extra processing as they might not be done
1865 after a single data transfer */
1866 if (unlikely(transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)) {
1867 /* Update the number of bytes transferred in this ISO packet */
1868 transaction->iso_packets[0].length = transaction->actual_bytes;
1869 transaction->iso_packets[0].status = complete_code;
1870
1871 /* If there are more ISOs pending and we succeeded, schedule the next
1872 one */
1873 if ((transaction->iso_number_packets > 1) && (complete_code == CVMX_USB_COMPLETE_SUCCESS)) {
1874 transaction->actual_bytes = 0; /* No bytes transferred for this packet as of yet */
1875 transaction->iso_number_packets--; /* One less ISO waiting to transfer */
1876 transaction->iso_packets++; /* Increment to the next location in our packet array */
1877 transaction->stage = CVMX_USB_STAGE_NON_CONTROL;
1878 goto done;
1879 }
1880 }
1881
1882 /* Remove the transaction from the pipe list */
1883 if (transaction->next)
1884 transaction->next->prev = transaction->prev;
1885 else
1886 pipe->tail = transaction->prev;
1887 if (transaction->prev)
1888 transaction->prev->next = transaction->next;
1889 else
1890 pipe->head = transaction->next;
1891 if (!pipe->head) {
1892 __cvmx_usb_remove_pipe(usb->active_pipes + pipe->transfer_type, pipe);
1893 __cvmx_usb_append_pipe(&usb->idle_pipes, pipe);
1894
1895 }
1896 __cvmx_usb_perform_callback(usb, pipe, transaction,
1897 CVMX_USB_CALLBACK_TRANSFER_COMPLETE,
1898 complete_code);
1899 __cvmx_usb_free_transaction(usb, transaction);
1900 done:
1901 return;
1902 }
1903
1904
1905 /**
1906 * @INTERNAL
1907 * Submit a usb transaction to a pipe. Called for all types
1908 * of transactions.
1909 *
1910 * @param usb
1911 * @param pipe_handle
1912 * Which pipe to submit to. Will be validated in this function.
1913 * @param type Transaction type
1914 * @param flags Flags for the transaction
1915 * @param buffer User buffer for the transaction
1916 * @param buffer_length
1917 * User buffer's length in bytes
1918 * @param control_header
1919 * For control transactions, the 8 byte standard header
1920 * @param iso_start_frame
1921 * For ISO transactions, the start frame
1922 * @param iso_number_packets
1923 * For ISO, the number of packet in the transaction.
1924 * @param iso_packets
1925 * A description of each ISO packet
1926 * @param callback User callback to call when the transaction completes
1927 * @param user_data User's data for the callback
1928 *
1929 * @return Submit handle or negative on failure. Matches the result
1930 * in the external API.
1931 */
1932 static int __cvmx_usb_submit_transaction(cvmx_usb_internal_state_t *usb,
1933 int pipe_handle,
1934 cvmx_usb_transfer_t type,
1935 int flags,
1936 uint64_t buffer,
1937 int buffer_length,
1938 uint64_t control_header,
1939 int iso_start_frame,
1940 int iso_number_packets,
1941 cvmx_usb_iso_packet_t *iso_packets,
1942 cvmx_usb_callback_func_t callback,
1943 void *user_data)
1944 {
1945 int submit_handle;
1946 cvmx_usb_transaction_t *transaction;
1947 cvmx_usb_pipe_t *pipe = usb->pipe + pipe_handle;
1948
1949 if (unlikely((pipe_handle < 0) || (pipe_handle >= MAX_PIPES)))
1950 return -EINVAL;
1951 /* Fail if the pipe isn't open */
1952 if (unlikely((pipe->flags & __CVMX_USB_PIPE_FLAGS_OPEN) == 0))
1953 return -EINVAL;
1954 if (unlikely(pipe->transfer_type != type))
1955 return -EINVAL;
1956
1957 transaction = __cvmx_usb_alloc_transaction(usb);
1958 if (unlikely(!transaction))
1959 return -ENOMEM;
1960
1961 transaction->type = type;
1962 transaction->flags |= flags;
1963 transaction->buffer = buffer;
1964 transaction->buffer_length = buffer_length;
1965 transaction->control_header = control_header;
1966 transaction->iso_start_frame = iso_start_frame; // FIXME: This is not used, implement it
1967 transaction->iso_number_packets = iso_number_packets;
1968 transaction->iso_packets = iso_packets;
1969 transaction->callback = callback;
1970 transaction->callback_data = user_data;
1971 if (transaction->type == CVMX_USB_TRANSFER_CONTROL)
1972 transaction->stage = CVMX_USB_STAGE_SETUP;
1973 else
1974 transaction->stage = CVMX_USB_STAGE_NON_CONTROL;
1975
1976 transaction->next = NULL;
1977 if (pipe->tail) {
1978 transaction->prev = pipe->tail;
1979 transaction->prev->next = transaction;
1980 }
1981 else {
1982 if (pipe->next_tx_frame < usb->frame_number)
1983 pipe->next_tx_frame = usb->frame_number + pipe->interval -
1984 (usb->frame_number - pipe->next_tx_frame) % pipe->interval;
1985 transaction->prev = NULL;
1986 pipe->head = transaction;
1987 __cvmx_usb_remove_pipe(&usb->idle_pipes, pipe);
1988 __cvmx_usb_append_pipe(usb->active_pipes + pipe->transfer_type, pipe);
1989 }
1990 pipe->tail = transaction;
1991
1992 submit_handle = __cvmx_usb_get_submit_handle(usb, transaction);
1993
1994 /* We may need to schedule the pipe if this was the head of the pipe */
1995 if (!transaction->prev)
1996 __cvmx_usb_schedule(usb, 0);
1997
1998 return submit_handle;
1999 }
2000
2001
2002 /**
2003 * Call to submit a USB Bulk transfer to a pipe.
2004 *
2005 * @param state USB device state populated by
2006 * cvmx_usb_initialize().
2007 * @param pipe_handle
2008 * Handle to the pipe for the transfer.
2009 * @param buffer Physical address of the data buffer in
2010 * memory. Note that this is NOT A POINTER, but
2011 * the full 64bit physical address of the
2012 * buffer. This may be zero if buffer_length is
2013 * zero.
2014 * @param buffer_length
2015 * Length of buffer in bytes.
2016 * @param callback Function to call when this transaction
2017 * completes. If the return value of this
2018 * function isn't an error, then this function
2019 * is guaranteed to be called when the
2020 * transaction completes. If this parameter is
2021 * NULL, then the generic callback registered
2022 * through cvmx_usb_register_callback is
2023 * called. If both are NULL, then there is no
2024 * way to know when a transaction completes.
2025 * @param user_data User supplied data returned when the
2026 * callback is called. This is only used if
2027 * callback in not NULL.
2028 *
2029 * @return A submitted transaction handle or negative on
2030 * failure. Negative values are error codes.
2031 */
2032 int cvmx_usb_submit_bulk(cvmx_usb_state_t *state, int pipe_handle,
2033 uint64_t buffer, int buffer_length,
2034 cvmx_usb_callback_func_t callback,
2035 void *user_data)
2036 {
2037 int submit_handle;
2038 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
2039
2040 /* Pipe handle checking is done later in a common place */
2041 if (unlikely(!buffer))
2042 return -EINVAL;
2043 if (unlikely(buffer_length < 0))
2044 return -EINVAL;
2045
2046 submit_handle = __cvmx_usb_submit_transaction(usb, pipe_handle,
2047 CVMX_USB_TRANSFER_BULK,
2048 0, /* flags */
2049 buffer,
2050 buffer_length,
2051 0, /* control_header */
2052 0, /* iso_start_frame */
2053 0, /* iso_number_packets */
2054 NULL, /* iso_packets */
2055 callback,
2056 user_data);
2057 return submit_handle;
2058 }
2059
2060
2061 /**
2062 * Call to submit a USB Interrupt transfer to a pipe.
2063 *
2064 * @param state USB device state populated by
2065 * cvmx_usb_initialize().
2066 * @param pipe_handle
2067 * Handle to the pipe for the transfer.
2068 * @param buffer Physical address of the data buffer in
2069 * memory. Note that this is NOT A POINTER, but
2070 * the full 64bit physical address of the
2071 * buffer. This may be zero if buffer_length is
2072 * zero.
2073 * @param buffer_length
2074 * Length of buffer in bytes.
2075 * @param callback Function to call when this transaction
2076 * completes. If the return value of this
2077 * function isn't an error, then this function
2078 * is guaranteed to be called when the
2079 * transaction completes. If this parameter is
2080 * NULL, then the generic callback registered
2081 * through cvmx_usb_register_callback is
2082 * called. If both are NULL, then there is no
2083 * way to know when a transaction completes.
2084 * @param user_data User supplied data returned when the
2085 * callback is called. This is only used if
2086 * callback in not NULL.
2087 *
2088 * @return A submitted transaction handle or negative on
2089 * failure. Negative values are error codes.
2090 */
2091 int cvmx_usb_submit_interrupt(cvmx_usb_state_t *state, int pipe_handle,
2092 uint64_t buffer, int buffer_length,
2093 cvmx_usb_callback_func_t callback,
2094 void *user_data)
2095 {
2096 int submit_handle;
2097 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
2098
2099 /* Pipe handle checking is done later in a common place */
2100 if (unlikely(!buffer))
2101 return -EINVAL;
2102 if (unlikely(buffer_length < 0))
2103 return -EINVAL;
2104
2105 submit_handle = __cvmx_usb_submit_transaction(usb, pipe_handle,
2106 CVMX_USB_TRANSFER_INTERRUPT,
2107 0, /* flags */
2108 buffer,
2109 buffer_length,
2110 0, /* control_header */
2111 0, /* iso_start_frame */
2112 0, /* iso_number_packets */
2113 NULL, /* iso_packets */
2114 callback,
2115 user_data);
2116 return submit_handle;
2117 }
2118
2119
2120 /**
2121 * Call to submit a USB Control transfer to a pipe.
2122 *
2123 * @param state USB device state populated by
2124 * cvmx_usb_initialize().
2125 * @param pipe_handle
2126 * Handle to the pipe for the transfer.
2127 * @param control_header
2128 * USB 8 byte control header physical address.
2129 * Note that this is NOT A POINTER, but the
2130 * full 64bit physical address of the buffer.
2131 * @param buffer Physical address of the data buffer in
2132 * memory. Note that this is NOT A POINTER, but
2133 * the full 64bit physical address of the
2134 * buffer. This may be zero if buffer_length is
2135 * zero.
2136 * @param buffer_length
2137 * Length of buffer in bytes.
2138 * @param callback Function to call when this transaction
2139 * completes. If the return value of this
2140 * function isn't an error, then this function
2141 * is guaranteed to be called when the
2142 * transaction completes. If this parameter is
2143 * NULL, then the generic callback registered
2144 * through cvmx_usb_register_callback is
2145 * called. If both are NULL, then there is no
2146 * way to know when a transaction completes.
2147 * @param user_data User supplied data returned when the
2148 * callback is called. This is only used if
2149 * callback in not NULL.
2150 *
2151 * @return A submitted transaction handle or negative on
2152 * failure. Negative values are error codes.
2153 */
2154 int cvmx_usb_submit_control(cvmx_usb_state_t *state, int pipe_handle,
2155 uint64_t control_header,
2156 uint64_t buffer, int buffer_length,
2157 cvmx_usb_callback_func_t callback,
2158 void *user_data)
2159 {
2160 int submit_handle;
2161 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
2162 cvmx_usb_control_header_t *header = cvmx_phys_to_ptr(control_header);
2163
2164 /* Pipe handle checking is done later in a common place */
2165 if (unlikely(!control_header))
2166 return -EINVAL;
2167 /* Some drivers send a buffer with a zero length. God only knows why */
2168 if (unlikely(buffer && (buffer_length < 0)))
2169 return -EINVAL;
2170 if (unlikely(!buffer && (buffer_length != 0)))
2171 return -EINVAL;
2172 if ((header->s.request_type & 0x80) == 0)
2173 buffer_length = le16_to_cpu(header->s.length);
2174
2175 submit_handle = __cvmx_usb_submit_transaction(usb, pipe_handle,
2176 CVMX_USB_TRANSFER_CONTROL,
2177 0, /* flags */
2178 buffer,
2179 buffer_length,
2180 control_header,
2181 0, /* iso_start_frame */
2182 0, /* iso_number_packets */
2183 NULL, /* iso_packets */
2184 callback,
2185 user_data);
2186 return submit_handle;
2187 }
2188
2189
2190 /**
2191 * Call to submit a USB Isochronous transfer to a pipe.
2192 *
2193 * @param state USB device state populated by
2194 * cvmx_usb_initialize().
2195 * @param pipe_handle
2196 * Handle to the pipe for the transfer.
2197 * @param start_frame
2198 * Number of frames into the future to schedule
2199 * this transaction.
2200 * @param flags Flags to control the transfer. See
2201 * cvmx_usb_isochronous_flags_t for the flag
2202 * definitions.
2203 * @param number_packets
2204 * Number of sequential packets to transfer.
2205 * "packets" is a pointer to an array of this
2206 * many packet structures.
2207 * @param packets Description of each transfer packet as
2208 * defined by cvmx_usb_iso_packet_t. The array
2209 * pointed to here must stay valid until the
2210 * complete callback is called.
2211 * @param buffer Physical address of the data buffer in
2212 * memory. Note that this is NOT A POINTER, but
2213 * the full 64bit physical address of the
2214 * buffer. This may be zero if buffer_length is
2215 * zero.
2216 * @param buffer_length
2217 * Length of buffer in bytes.
2218 * @param callback Function to call when this transaction
2219 * completes. If the return value of this
2220 * function isn't an error, then this function
2221 * is guaranteed to be called when the
2222 * transaction completes. If this parameter is
2223 * NULL, then the generic callback registered
2224 * through cvmx_usb_register_callback is
2225 * called. If both are NULL, then there is no
2226 * way to know when a transaction completes.
2227 * @param user_data User supplied data returned when the
2228 * callback is called. This is only used if
2229 * callback in not NULL.
2230 *
2231 * @return A submitted transaction handle or negative on
2232 * failure. Negative values are error codes.
2233 */
2234 int cvmx_usb_submit_isochronous(cvmx_usb_state_t *state, int pipe_handle,
2235 int start_frame, int flags,
2236 int number_packets,
2237 cvmx_usb_iso_packet_t packets[],
2238 uint64_t buffer, int buffer_length,
2239 cvmx_usb_callback_func_t callback,
2240 void *user_data)
2241 {
2242 int submit_handle;
2243 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
2244
2245 /* Pipe handle checking is done later in a common place */
2246 if (unlikely(start_frame < 0))
2247 return -EINVAL;
2248 if (unlikely(flags & ~(CVMX_USB_ISOCHRONOUS_FLAGS_ALLOW_SHORT | CVMX_USB_ISOCHRONOUS_FLAGS_ASAP)))
2249 return -EINVAL;
2250 if (unlikely(number_packets < 1))
2251 return -EINVAL;
2252 if (unlikely(!packets))
2253 return -EINVAL;
2254 if (unlikely(!buffer))
2255 return -EINVAL;
2256 if (unlikely(buffer_length < 0))
2257 return -EINVAL;
2258
2259 submit_handle = __cvmx_usb_submit_transaction(usb, pipe_handle,
2260 CVMX_USB_TRANSFER_ISOCHRONOUS,
2261 flags,
2262 buffer,
2263 buffer_length,
2264 0, /* control_header */
2265 start_frame,
2266 number_packets,
2267 packets,
2268 callback,
2269 user_data);
2270 return submit_handle;
2271 }
2272
2273
2274 /**
2275 * Cancel one outstanding request in a pipe. Canceling a request
2276 * can fail if the transaction has already completed before cancel
2277 * is called. Even after a successful cancel call, it may take
2278 * a frame or two for the cvmx_usb_poll() function to call the
2279 * associated callback.
2280 *
2281 * @param state USB device state populated by
2282 * cvmx_usb_initialize().
2283 * @param pipe_handle
2284 * Pipe handle to cancel requests in.
2285 * @param submit_handle
2286 * Handle to transaction to cancel, returned by the submit function.
2287 *
2288 * @return 0 or a negative error code.
2289 */
2290 int cvmx_usb_cancel(cvmx_usb_state_t *state, int pipe_handle, int submit_handle)
2291 {
2292 cvmx_usb_transaction_t *transaction;
2293 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
2294 cvmx_usb_pipe_t *pipe = usb->pipe + pipe_handle;
2295
2296 if (unlikely((pipe_handle < 0) || (pipe_handle >= MAX_PIPES)))
2297 return -EINVAL;
2298 if (unlikely((submit_handle < 0) || (submit_handle >= MAX_TRANSACTIONS)))
2299 return -EINVAL;
2300
2301 /* Fail if the pipe isn't open */
2302 if (unlikely((pipe->flags & __CVMX_USB_PIPE_FLAGS_OPEN) == 0))
2303 return -EINVAL;
2304
2305 transaction = usb->transaction + submit_handle;
2306
2307 /* Fail if this transaction already completed */
2308 if (unlikely((transaction->flags & __CVMX_USB_TRANSACTION_FLAGS_IN_USE) == 0))
2309 return -EINVAL;
2310
2311 /* If the transaction is the HEAD of the queue and scheduled. We need to
2312 treat it special */
2313 if ((pipe->head == transaction) &&
2314 (pipe->flags & __CVMX_USB_PIPE_FLAGS_SCHEDULED)) {
2315 cvmx_usbcx_hccharx_t usbc_hcchar;
2316
2317 usb->pipe_for_channel[pipe->channel] = NULL;
2318 pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_SCHEDULED;
2319
2320 CVMX_SYNCW;
2321
2322 usbc_hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(pipe->channel, usb->index));
2323 /* If the channel isn't enabled then the transaction already completed */
2324 if (usbc_hcchar.s.chena) {
2325 usbc_hcchar.s.chdis = 1;
2326 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(pipe->channel, usb->index), usbc_hcchar.u32);
2327 }
2328 }
2329 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_CANCEL);
2330 return 0;
2331 }
2332
2333
2334 /**
2335 * Cancel all outstanding requests in a pipe. Logically all this
2336 * does is call cvmx_usb_cancel() in a loop.
2337 *
2338 * @param state USB device state populated by
2339 * cvmx_usb_initialize().
2340 * @param pipe_handle
2341 * Pipe handle to cancel requests in.
2342 *
2343 * @return 0 or a negative error code.
2344 */
2345 int cvmx_usb_cancel_all(cvmx_usb_state_t *state, int pipe_handle)
2346 {
2347 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
2348 cvmx_usb_pipe_t *pipe = usb->pipe + pipe_handle;
2349
2350 if (unlikely((pipe_handle < 0) || (pipe_handle >= MAX_PIPES)))
2351 return -EINVAL;
2352
2353 /* Fail if the pipe isn't open */
2354 if (unlikely((pipe->flags & __CVMX_USB_PIPE_FLAGS_OPEN) == 0))
2355 return -EINVAL;
2356
2357 /* Simply loop through and attempt to cancel each transaction */
2358 while (pipe->head) {
2359 int result = cvmx_usb_cancel(state, pipe_handle,
2360 __cvmx_usb_get_submit_handle(usb, pipe->head));
2361 if (unlikely(result != 0))
2362 return result;
2363 }
2364 return 0;
2365 }
2366
2367
2368 /**
2369 * Close a pipe created with cvmx_usb_open_pipe().
2370 *
2371 * @param state USB device state populated by
2372 * cvmx_usb_initialize().
2373 * @param pipe_handle
2374 * Pipe handle to close.
2375 *
2376 * @return 0 or a negative error code. EBUSY is returned if the pipe has
2377 * outstanding transfers.
2378 */
2379 int cvmx_usb_close_pipe(cvmx_usb_state_t *state, int pipe_handle)
2380 {
2381 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
2382 cvmx_usb_pipe_t *pipe = usb->pipe + pipe_handle;
2383
2384 if (unlikely((pipe_handle < 0) || (pipe_handle >= MAX_PIPES)))
2385 return -EINVAL;
2386
2387 /* Fail if the pipe isn't open */
2388 if (unlikely((pipe->flags & __CVMX_USB_PIPE_FLAGS_OPEN) == 0))
2389 return -EINVAL;
2390
2391 /* Fail if the pipe has pending transactions */
2392 if (unlikely(pipe->head))
2393 return -EBUSY;
2394
2395 pipe->flags = 0;
2396 __cvmx_usb_remove_pipe(&usb->idle_pipes, pipe);
2397 __cvmx_usb_append_pipe(&usb->free_pipes, pipe);
2398
2399 return 0;
2400 }
2401
2402
2403 /**
2404 * Register a function to be called when various USB events occur.
2405 *
2406 * @param state USB device state populated by
2407 * cvmx_usb_initialize().
2408 * @param reason Which event to register for.
2409 * @param callback Function to call when the event occurs.
2410 * @param user_data User data parameter to the function.
2411 *
2412 * @return 0 or a negative error code.
2413 */
2414 int cvmx_usb_register_callback(cvmx_usb_state_t *state,
2415 cvmx_usb_callback_t reason,
2416 cvmx_usb_callback_func_t callback,
2417 void *user_data)
2418 {
2419 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
2420
2421 if (unlikely(reason >= __CVMX_USB_CALLBACK_END))
2422 return -EINVAL;
2423 if (unlikely(!callback))
2424 return -EINVAL;
2425
2426 usb->callback[reason] = callback;
2427 usb->callback_data[reason] = user_data;
2428
2429 return 0;
2430 }
2431
2432
2433 /**
2434 * Get the current USB protocol level frame number. The frame
2435 * number is always in the range of 0-0x7ff.
2436 *
2437 * @param state USB device state populated by
2438 * cvmx_usb_initialize().
2439 *
2440 * @return USB frame number
2441 */
2442 int cvmx_usb_get_frame_number(cvmx_usb_state_t *state)
2443 {
2444 int frame_number;
2445 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
2446 cvmx_usbcx_hfnum_t usbc_hfnum;
2447
2448 usbc_hfnum.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index));
2449 frame_number = usbc_hfnum.s.frnum;
2450
2451 return frame_number;
2452 }
2453
2454
2455 /**
2456 * @INTERNAL
2457 * Poll a channel for status
2458 *
2459 * @param usb USB device
2460 * @param channel Channel to poll
2461 *
2462 * @return Zero on success
2463 */
2464 static int __cvmx_usb_poll_channel(cvmx_usb_internal_state_t *usb, int channel)
2465 {
2466 cvmx_usbcx_hcintx_t usbc_hcint;
2467 cvmx_usbcx_hctsizx_t usbc_hctsiz;
2468 cvmx_usbcx_hccharx_t usbc_hcchar;
2469 cvmx_usb_pipe_t *pipe;
2470 cvmx_usb_transaction_t *transaction;
2471 int bytes_this_transfer;
2472 int bytes_in_last_packet;
2473 int packets_processed;
2474 int buffer_space_left;
2475
2476 /* Read the interrupt status bits for the channel */
2477 usbc_hcint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCINTX(channel, usb->index));
2478
2479 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) {
2480 usbc_hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index));
2481
2482 if (usbc_hcchar.s.chena && usbc_hcchar.s.chdis) {
2483 /* There seems to be a bug in CN31XX which can cause interrupt
2484 IN transfers to get stuck until we do a write of HCCHARX
2485 without changing things */
2486 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index), usbc_hcchar.u32);
2487 return 0;
2488 }
2489
2490 /* In non DMA mode the channels don't halt themselves. We need to
2491 manually disable channels that are left running */
2492 if (!usbc_hcint.s.chhltd) {
2493 if (usbc_hcchar.s.chena) {
2494 cvmx_usbcx_hcintmskx_t hcintmsk;
2495 /* Disable all interrupts except CHHLTD */
2496 hcintmsk.u32 = 0;
2497 hcintmsk.s.chhltdmsk = 1;
2498 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), hcintmsk.u32);
2499 usbc_hcchar.s.chdis = 1;
2500 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index), usbc_hcchar.u32);
2501 return 0;
2502 }
2503 else if (usbc_hcint.s.xfercompl) {
2504 /* Successful IN/OUT with transfer complete. Channel halt isn't needed */
2505 }
2506 else {
2507 cvmx_dprintf("USB%d: Channel %d interrupt without halt\n", usb->index, channel);
2508 return 0;
2509 }
2510 }
2511 }
2512 else {
2513 /* There is are no interrupts that we need to process when the channel is
2514 still running */
2515 if (!usbc_hcint.s.chhltd)
2516 return 0;
2517 }
2518
2519 /* Disable the channel interrupts now that it is done */
2520 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), 0);
2521 usb->idle_hardware_channels |= (1<<channel);
2522
2523 /* Make sure this channel is tied to a valid pipe */
2524 pipe = usb->pipe_for_channel[channel];
2525 CVMX_PREFETCH(pipe, 0);
2526 CVMX_PREFETCH(pipe, 128);
2527 if (!pipe)
2528 return 0;
2529 transaction = pipe->head;
2530 CVMX_PREFETCH0(transaction);
2531
2532 /* Disconnect this pipe from the HW channel. Later the schedule function will
2533 figure out which pipe needs to go */
2534 usb->pipe_for_channel[channel] = NULL;
2535 pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_SCHEDULED;
2536
2537 /* Read the channel config info so we can figure out how much data
2538 transfered */
2539 usbc_hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index));
2540 usbc_hctsiz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index));
2541
2542 /* Calculating the number of bytes successfully transferred is dependent on
2543 the transfer direction */
2544 packets_processed = transaction->pktcnt - usbc_hctsiz.s.pktcnt;
2545 if (usbc_hcchar.s.epdir) {
2546 /* IN transactions are easy. For every byte received the hardware
2547 decrements xfersize. All we need to do is subtract the current
2548 value of xfersize from its starting value and we know how many
2549 bytes were written to the buffer */
2550 bytes_this_transfer = transaction->xfersize - usbc_hctsiz.s.xfersize;
2551 }
2552 else {
2553 /* OUT transaction don't decrement xfersize. Instead pktcnt is
2554 decremented on every successful packet send. The hardware does
2555 this when it receives an ACK, or NYET. If it doesn't
2556 receive one of these responses pktcnt doesn't change */
2557 bytes_this_transfer = packets_processed * usbc_hcchar.s.mps;
2558 /* The last packet may not be a full transfer if we didn't have
2559 enough data */
2560 if (bytes_this_transfer > transaction->xfersize)
2561 bytes_this_transfer = transaction->xfersize;
2562 }
2563 /* Figure out how many bytes were in the last packet of the transfer */
2564 if (packets_processed)
2565 bytes_in_last_packet = bytes_this_transfer - (packets_processed-1) * usbc_hcchar.s.mps;
2566 else
2567 bytes_in_last_packet = bytes_this_transfer;
2568
2569 /* As a special case, setup transactions output the setup header, not
2570 the user's data. For this reason we don't count setup data as bytes
2571 transferred */
2572 if ((transaction->stage == CVMX_USB_STAGE_SETUP) ||
2573 (transaction->stage == CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE))
2574 bytes_this_transfer = 0;
2575
2576 /* Add the bytes transferred to the running total. It is important that
2577 bytes_this_transfer doesn't count any data that needs to be
2578 retransmitted */
2579 transaction->actual_bytes += bytes_this_transfer;
2580 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
2581 buffer_space_left = transaction->iso_packets[0].length - transaction->actual_bytes;
2582 else
2583 buffer_space_left = transaction->buffer_length - transaction->actual_bytes;
2584
2585 /* We need to remember the PID toggle state for the next transaction. The
2586 hardware already updated it for the next transaction */
2587 pipe->pid_toggle = !(usbc_hctsiz.s.pid == 0);
2588
2589 /* For high speed bulk out, assume the next transaction will need to do a
2590 ping before proceeding. If this isn't true the ACK processing below
2591 will clear this flag */
2592 if ((pipe->device_speed == CVMX_USB_SPEED_HIGH) &&
2593 (pipe->transfer_type == CVMX_USB_TRANSFER_BULK) &&
2594 (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT))
2595 pipe->flags |= __CVMX_USB_PIPE_FLAGS_NEED_PING;
2596
2597 if (usbc_hcint.s.stall) {
2598 /* STALL as a response means this transaction cannot be completed
2599 because the device can't process transactions. Tell the user. Any
2600 data that was transferred will be counted on the actual bytes
2601 transferred */
2602 pipe->pid_toggle = 0;
2603 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_STALL);
2604 }
2605 else if (usbc_hcint.s.xacterr) {
2606 /* We know at least one packet worked if we get a ACK or NAK. Reset the retry counter */
2607 if (usbc_hcint.s.nak || usbc_hcint.s.ack)
2608 transaction->retries = 0;
2609 transaction->retries++;
2610 if (transaction->retries > MAX_RETRIES) {
2611 /* XactErr as a response means the device signaled something wrong with
2612 the transfer. For example, PID toggle errors cause these */
2613 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_XACTERR);
2614 }
2615 else {
2616 /* If this was a split then clear our split in progress marker */
2617 if (usb->active_split == transaction)
2618 usb->active_split = NULL;
2619 /* Rewind to the beginning of the transaction by anding off the
2620 split complete bit */
2621 transaction->stage &= ~1;
2622 pipe->split_sc_frame = -1;
2623 pipe->next_tx_frame += pipe->interval;
2624 if (pipe->next_tx_frame < usb->frame_number)
2625 pipe->next_tx_frame = usb->frame_number + pipe->interval -
2626 (usb->frame_number - pipe->next_tx_frame) % pipe->interval;
2627 }
2628 }
2629 else if (usbc_hcint.s.bblerr)
2630 {
2631 /* Babble Error (BblErr) */
2632 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_BABBLEERR);
2633 }
2634 else if (usbc_hcint.s.datatglerr)
2635 {
2636 /* We'll retry the exact same transaction again */
2637 transaction->retries++;
2638 }
2639 else if (usbc_hcint.s.nyet) {
2640 /* NYET as a response is only allowed in three cases: as a response to
2641 a ping, as a response to a split transaction, and as a response to
2642 a bulk out. The ping case is handled by hardware, so we only have
2643 splits and bulk out */
2644 if (!__cvmx_usb_pipe_needs_split(usb, pipe)) {
2645 transaction->retries = 0;
2646 /* If there is more data to go then we need to try again. Otherwise
2647 this transaction is complete */
2648 if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet))
2649 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2650 }
2651 else {
2652 /* Split transactions retry the split complete 4 times then rewind
2653 to the start split and do the entire transactions again */
2654 transaction->retries++;
2655 if ((transaction->retries & 0x3) == 0) {
2656 /* Rewind to the beginning of the transaction by anding off the
2657 split complete bit */
2658 transaction->stage &= ~1;
2659 pipe->split_sc_frame = -1;
2660 }
2661 }
2662 }
2663 else if (usbc_hcint.s.ack) {
2664 transaction->retries = 0;
2665 /* The ACK bit can only be checked after the other error bits. This is
2666 because a multi packet transfer may succeed in a number of packets
2667 and then get a different response on the last packet. In this case
2668 both ACK and the last response bit will be set. If none of the
2669 other response bits is set, then the last packet must have been an
2670 ACK */
2671
2672 /* Since we got an ACK, we know we don't need to do a ping on this
2673 pipe */
2674 pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_NEED_PING;
2675
2676 switch (transaction->type)
2677 {
2678 case CVMX_USB_TRANSFER_CONTROL:
2679 switch (transaction->stage)
2680 {
2681 case CVMX_USB_STAGE_NON_CONTROL:
2682 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE:
2683 /* This should be impossible */
2684 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_ERROR);
2685 break;
2686 case CVMX_USB_STAGE_SETUP:
2687 pipe->pid_toggle = 1;
2688 if (__cvmx_usb_pipe_needs_split(usb, pipe))
2689 transaction->stage = CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE;
2690 else {
2691 cvmx_usb_control_header_t *header = cvmx_phys_to_ptr(transaction->control_header);
2692 if (header->s.length)
2693 transaction->stage = CVMX_USB_STAGE_DATA;
2694 else
2695 transaction->stage = CVMX_USB_STAGE_STATUS;
2696 }
2697 break;
2698 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE:
2699 {
2700 cvmx_usb_control_header_t *header = cvmx_phys_to_ptr(transaction->control_header);
2701 if (header->s.length)
2702 transaction->stage = CVMX_USB_STAGE_DATA;
2703 else
2704 transaction->stage = CVMX_USB_STAGE_STATUS;
2705 }
2706 break;
2707 case CVMX_USB_STAGE_DATA:
2708 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
2709 transaction->stage = CVMX_USB_STAGE_DATA_SPLIT_COMPLETE;
2710 /* For setup OUT data that are splits, the hardware
2711 doesn't appear to count transferred data. Here
2712 we manually update the data transferred */
2713 if (!usbc_hcchar.s.epdir) {
2714 if (buffer_space_left < pipe->max_packet)
2715 transaction->actual_bytes += buffer_space_left;
2716 else
2717 transaction->actual_bytes += pipe->max_packet;
2718 }
2719 }
2720 else if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet)) {
2721 pipe->pid_toggle = 1;
2722 transaction->stage = CVMX_USB_STAGE_STATUS;
2723 }
2724 break;
2725 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE:
2726 if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet)) {
2727 pipe->pid_toggle = 1;
2728 transaction->stage = CVMX_USB_STAGE_STATUS;
2729 }
2730 else {
2731 transaction->stage = CVMX_USB_STAGE_DATA;
2732 }
2733 break;
2734 case CVMX_USB_STAGE_STATUS:
2735 if (__cvmx_usb_pipe_needs_split(usb, pipe))
2736 transaction->stage = CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE;
2737 else
2738 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2739 break;
2740 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE:
2741 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2742 break;
2743 }
2744 break;
2745 case CVMX_USB_TRANSFER_BULK:
2746 case CVMX_USB_TRANSFER_INTERRUPT:
2747 /* The only time a bulk transfer isn't complete when
2748 it finishes with an ACK is during a split transaction. For
2749 splits we need to continue the transfer if more data is
2750 needed */
2751 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
2752 if (transaction->stage == CVMX_USB_STAGE_NON_CONTROL)
2753 transaction->stage = CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE;
2754 else {
2755 if (buffer_space_left && (bytes_in_last_packet == pipe->max_packet))
2756 transaction->stage = CVMX_USB_STAGE_NON_CONTROL;
2757 else {
2758 if (transaction->type == CVMX_USB_TRANSFER_INTERRUPT)
2759 pipe->next_tx_frame += pipe->interval;
2760 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2761 }
2762 }
2763 }
2764 else {
2765 if ((pipe->device_speed == CVMX_USB_SPEED_HIGH) &&
2766 (pipe->transfer_type == CVMX_USB_TRANSFER_BULK) &&
2767 (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) &&
2768 (usbc_hcint.s.nak))
2769 pipe->flags |= __CVMX_USB_PIPE_FLAGS_NEED_PING;
2770 if (!buffer_space_left || (bytes_in_last_packet < pipe->max_packet)) {
2771 if (transaction->type == CVMX_USB_TRANSFER_INTERRUPT)
2772 pipe->next_tx_frame += pipe->interval;
2773 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2774 }
2775 }
2776 break;
2777 case CVMX_USB_TRANSFER_ISOCHRONOUS:
2778 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
2779 /* ISOCHRONOUS OUT splits don't require a complete split stage.
2780 Instead they use a sequence of begin OUT splits to transfer
2781 the data 188 bytes at a time. Once the transfer is complete,
2782 the pipe sleeps until the next schedule interval */
2783 if (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) {
2784 /* If no space left or this wasn't a max size packet then
2785 this transfer is complete. Otherwise start it again
2786 to send the next 188 bytes */
2787 if (!buffer_space_left || (bytes_this_transfer < 188)) {
2788 pipe->next_tx_frame += pipe->interval;
2789 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2790 }
2791 }
2792 else {
2793 if (transaction->stage == CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE) {
2794 /* We are in the incoming data phase. Keep getting
2795 data until we run out of space or get a small
2796 packet */
2797 if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet)) {
2798 pipe->next_tx_frame += pipe->interval;
2799 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2800 }
2801 }
2802 else
2803 transaction->stage = CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE;
2804 }
2805 }
2806 else {
2807 pipe->next_tx_frame += pipe->interval;
2808 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2809 }
2810 break;
2811 }
2812 }
2813 else if (usbc_hcint.s.nak) {
2814 /* If this was a split then clear our split in progress marker */
2815 if (usb->active_split == transaction)
2816 usb->active_split = NULL;
2817 /* NAK as a response means the device couldn't accept the transaction,
2818 but it should be retried in the future. Rewind to the beginning of
2819 the transaction by anding off the split complete bit. Retry in the
2820 next interval */
2821 transaction->retries = 0;
2822 transaction->stage &= ~1;
2823 pipe->next_tx_frame += pipe->interval;
2824 if (pipe->next_tx_frame < usb->frame_number)
2825 pipe->next_tx_frame = usb->frame_number + pipe->interval -
2826 (usb->frame_number - pipe->next_tx_frame) % pipe->interval;
2827 }
2828 else {
2829 cvmx_usb_port_status_t port;
2830 port = cvmx_usb_get_status((cvmx_usb_state_t *)usb);
2831 if (port.port_enabled)
2832 {
2833 /* We'll retry the exact same transaction again */
2834 transaction->retries++;
2835 }
2836 else
2837 {
2838 /* We get channel halted interrupts with no result bits sets when the
2839 cable is unplugged */
2840 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_ERROR);
2841 }
2842 }
2843 return 0;
2844 }
2845
2846
2847 /**
2848 * Poll the USB block for status and call all needed callback
2849 * handlers. This function is meant to be called in the interrupt
2850 * handler for the USB controller. It can also be called
2851 * periodically in a loop for non-interrupt based operation.
2852 *
2853 * @param state USB device state populated by
2854 * cvmx_usb_initialize().
2855 *
2856 * @return 0 or a negative error code.
2857 */
2858 int cvmx_usb_poll(cvmx_usb_state_t *state)
2859 {
2860 cvmx_usbcx_hfnum_t usbc_hfnum;
2861 cvmx_usbcx_gintsts_t usbc_gintsts;
2862 cvmx_usb_internal_state_t *usb = (cvmx_usb_internal_state_t*)state;
2863
2864 CVMX_PREFETCH(usb, 0);
2865 CVMX_PREFETCH(usb, 1*128);
2866 CVMX_PREFETCH(usb, 2*128);
2867 CVMX_PREFETCH(usb, 3*128);
2868 CVMX_PREFETCH(usb, 4*128);
2869
2870 /* Update the frame counter */
2871 usbc_hfnum.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index));
2872 if ((usb->frame_number&0x3fff) > usbc_hfnum.s.frnum)
2873 usb->frame_number += 0x4000;
2874 usb->frame_number &= ~0x3fffull;
2875 usb->frame_number |= usbc_hfnum.s.frnum;
2876
2877 /* Read the pending interrupts */
2878 usbc_gintsts.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GINTSTS(usb->index));
2879
2880 /* Clear the interrupts now that we know about them */
2881 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTSTS(usb->index), usbc_gintsts.u32);
2882
2883 if (usbc_gintsts.s.rxflvl) {
2884 /* RxFIFO Non-Empty (RxFLvl)
2885 Indicates that there is at least one packet pending to be read
2886 from the RxFIFO. */
2887 /* In DMA mode this is handled by hardware */
2888 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
2889 __cvmx_usb_poll_rx_fifo(usb);
2890 }
2891 if (usbc_gintsts.s.ptxfemp || usbc_gintsts.s.nptxfemp) {
2892 /* Fill the Tx FIFOs when not in DMA mode */
2893 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
2894 __cvmx_usb_poll_tx_fifo(usb);
2895 }
2896 if (usbc_gintsts.s.disconnint || usbc_gintsts.s.prtint) {
2897 cvmx_usbcx_hprt_t usbc_hprt;
2898 /* Disconnect Detected Interrupt (DisconnInt)
2899 Asserted when a device disconnect is detected. */
2900
2901 /* Host Port Interrupt (PrtInt)
2902 The core sets this bit to indicate a change in port status of one
2903 of the O2P USB core ports in Host mode. The application must
2904 read the Host Port Control and Status (HPRT) register to
2905 determine the exact event that caused this interrupt. The
2906 application must clear the appropriate status bit in the Host Port
2907 Control and Status register to clear this bit. */
2908
2909 /* Call the user's port callback */
2910 __cvmx_usb_perform_callback(usb, NULL, NULL,
2911 CVMX_USB_CALLBACK_PORT_CHANGED,
2912 CVMX_USB_COMPLETE_SUCCESS);
2913 /* Clear the port change bits */
2914 usbc_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
2915 usbc_hprt.s.prtena = 0;
2916 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HPRT(usb->index), usbc_hprt.u32);
2917 }
2918 if (usbc_gintsts.s.hchint) {
2919 /* Host Channels Interrupt (HChInt)
2920 The core sets this bit to indicate that an interrupt is pending on
2921 one of the channels of the core (in Host mode). The application
2922 must read the Host All Channels Interrupt (HAINT) register to
2923 determine the exact number of the channel on which the
2924 interrupt occurred, and then read the corresponding Host
2925 Channel-n Interrupt (HCINTn) register to determine the exact
2926 cause of the interrupt. The application must clear the
2927 appropriate status bit in the HCINTn register to clear this bit. */
2928 cvmx_usbcx_haint_t usbc_haint;
2929 usbc_haint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HAINT(usb->index));
2930 while (usbc_haint.u32) {
2931 int channel;
2932 CVMX_CLZ(channel, usbc_haint.u32);
2933 channel = 31 - channel;
2934 __cvmx_usb_poll_channel(usb, channel);
2935 usbc_haint.u32 ^= 1<<channel;
2936 }
2937 }
2938
2939 __cvmx_usb_schedule(usb, usbc_gintsts.s.sof);
2940
2941 return 0;
2942 }
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