2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2008 Cavium Networks
8 * Some parts of the code were originally released under BSD license:
10 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions are
17 * * Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
20 * * Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials provided
23 * with the distribution.
25 * * Neither the name of Cavium Networks nor the names of
26 * its contributors may be used to endorse or promote products
27 * derived from this software without specific prior written
30 * This Software, including technical data, may be subject to U.S. export
31 * control laws, including the U.S. Export Administration Act and its associated
32 * regulations, and may be subject to export or import regulations in other
35 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
36 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
37 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
38 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION
39 * OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
40 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
41 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
42 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
43 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
44 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
46 #include <linux/kernel.h>
47 #include <linux/module.h>
48 #include <linux/init.h>
49 #include <linux/pci.h>
50 #include <linux/prefetch.h>
51 #include <linux/interrupt.h>
52 #include <linux/platform_device.h>
53 #include <linux/usb.h>
55 #include <linux/time.h>
56 #include <linux/delay.h>
58 #include <asm/octeon/cvmx.h>
59 #include <asm/octeon/cvmx-iob-defs.h>
61 #include <linux/usb/hcd.h>
63 #include <linux/err.h>
65 #include <asm/octeon/octeon.h>
66 #include <asm/octeon/cvmx-helper.h>
67 #include <asm/octeon/cvmx-sysinfo.h>
68 #include <asm/octeon/cvmx-helper-board.h>
70 #include "octeon-hcd.h"
73 * enum cvmx_usb_speed - the possible USB device speeds
75 * @CVMX_USB_SPEED_HIGH: Device is operation at 480Mbps
76 * @CVMX_USB_SPEED_FULL: Device is operation at 12Mbps
77 * @CVMX_USB_SPEED_LOW: Device is operation at 1.5Mbps
80 CVMX_USB_SPEED_HIGH
= 0,
81 CVMX_USB_SPEED_FULL
= 1,
82 CVMX_USB_SPEED_LOW
= 2,
86 * enum cvmx_usb_transfer - the possible USB transfer types
88 * @CVMX_USB_TRANSFER_CONTROL: USB transfer type control for hub and status
90 * @CVMX_USB_TRANSFER_ISOCHRONOUS: USB transfer type isochronous for low
91 * priority periodic transfers
92 * @CVMX_USB_TRANSFER_BULK: USB transfer type bulk for large low priority
94 * @CVMX_USB_TRANSFER_INTERRUPT: USB transfer type interrupt for high priority
97 enum cvmx_usb_transfer
{
98 CVMX_USB_TRANSFER_CONTROL
= 0,
99 CVMX_USB_TRANSFER_ISOCHRONOUS
= 1,
100 CVMX_USB_TRANSFER_BULK
= 2,
101 CVMX_USB_TRANSFER_INTERRUPT
= 3,
105 * enum cvmx_usb_direction - the transfer directions
107 * @CVMX_USB_DIRECTION_OUT: Data is transferring from Octeon to the device/host
108 * @CVMX_USB_DIRECTION_IN: Data is transferring from the device/host to Octeon
110 enum cvmx_usb_direction
{
111 CVMX_USB_DIRECTION_OUT
,
112 CVMX_USB_DIRECTION_IN
,
116 * enum cvmx_usb_complete - possible callback function status codes
118 * @CVMX_USB_COMPLETE_SUCCESS: The transaction / operation finished without
120 * @CVMX_USB_COMPLETE_SHORT: FIXME: This is currently not implemented
121 * @CVMX_USB_COMPLETE_CANCEL: The transaction was canceled while in flight
122 * by a user call to cvmx_usb_cancel
123 * @CVMX_USB_COMPLETE_ERROR: The transaction aborted with an unexpected
125 * @CVMX_USB_COMPLETE_STALL: The transaction received a USB STALL response
127 * @CVMX_USB_COMPLETE_XACTERR: The transaction failed with an error from the
128 * device even after a number of retries
129 * @CVMX_USB_COMPLETE_DATATGLERR: The transaction failed with a data toggle
130 * error even after a number of retries
131 * @CVMX_USB_COMPLETE_BABBLEERR: The transaction failed with a babble error
132 * @CVMX_USB_COMPLETE_FRAMEERR: The transaction failed with a frame error
133 * even after a number of retries
135 enum cvmx_usb_complete
{
136 CVMX_USB_COMPLETE_SUCCESS
,
137 CVMX_USB_COMPLETE_SHORT
,
138 CVMX_USB_COMPLETE_CANCEL
,
139 CVMX_USB_COMPLETE_ERROR
,
140 CVMX_USB_COMPLETE_STALL
,
141 CVMX_USB_COMPLETE_XACTERR
,
142 CVMX_USB_COMPLETE_DATATGLERR
,
143 CVMX_USB_COMPLETE_BABBLEERR
,
144 CVMX_USB_COMPLETE_FRAMEERR
,
148 * struct cvmx_usb_port_status - the USB port status information
150 * @port_enabled: 1 = Usb port is enabled, 0 = disabled
151 * @port_over_current: 1 = Over current detected, 0 = Over current not
152 * detected. Octeon doesn't support over current detection.
153 * @port_powered: 1 = Port power is being supplied to the device, 0 =
154 * power is off. Octeon doesn't support turning port power
156 * @port_speed: Current port speed.
157 * @connected: 1 = A device is connected to the port, 0 = No device is
159 * @connect_change: 1 = Device connected state changed since the last set
162 struct cvmx_usb_port_status
{
163 uint32_t reserved
: 25;
164 uint32_t port_enabled
: 1;
165 uint32_t port_over_current
: 1;
166 uint32_t port_powered
: 1;
167 enum cvmx_usb_speed port_speed
: 2;
168 uint32_t connected
: 1;
169 uint32_t connect_change
: 1;
173 * struct cvmx_usb_iso_packet - descriptor for Isochronous packets
175 * @offset: This is the offset in bytes into the main buffer where this data
177 * @length: This is the length in bytes of the data.
178 * @status: This is the status of this individual packet transfer.
180 struct cvmx_usb_iso_packet
{
183 enum cvmx_usb_complete status
;
187 * enum cvmx_usb_initialize_flags - flags used by the initialization function
189 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI: The USB port uses a 12MHz crystal
190 * as clock source at USB_XO and
192 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND: The USB port uses 12/24/48MHz 2.5V
193 * board clock source at USB_XO.
194 * USB_XI should be tied to GND.
195 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK: Mask for clock speed field
196 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ: Speed of reference clock or
198 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ: Speed of reference clock
199 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ: Speed of reference clock
200 * @CVMX_USB_INITIALIZE_FLAGS_NO_DMA: Disable DMA and used polled IO for
201 * data transfer use for the USB
203 enum cvmx_usb_initialize_flags
{
204 CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI
= 1 << 0,
205 CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND
= 1 << 1,
206 CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK
= 3 << 3,
207 CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ
= 1 << 3,
208 CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ
= 2 << 3,
209 CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ
= 3 << 3,
210 /* Bits 3-4 used to encode the clock frequency */
211 CVMX_USB_INITIALIZE_FLAGS_NO_DMA
= 1 << 5,
215 * enum cvmx_usb_pipe_flags - internal flags for a pipe.
217 * @__CVMX_USB_PIPE_FLAGS_SCHEDULED: Used internally to determine if a pipe is
218 * actively using hardware. Do not use.
219 * @__CVMX_USB_PIPE_FLAGS_NEED_PING: Used internally to determine if a high
220 * speed pipe is in the ping state. Do not
223 enum cvmx_usb_pipe_flags
{
224 __CVMX_USB_PIPE_FLAGS_SCHEDULED
= 1 << 17,
225 __CVMX_USB_PIPE_FLAGS_NEED_PING
= 1 << 18,
228 /* Maximum number of times to retry failed transactions */
229 #define MAX_RETRIES 3
231 /* Maximum number of hardware channels supported by the USB block */
232 #define MAX_CHANNELS 8
235 * The low level hardware can transfer a maximum of this number of bytes in each
236 * transfer. The field is 19 bits wide
238 #define MAX_TRANSFER_BYTES ((1<<19)-1)
241 * The low level hardware can transfer a maximum of this number of packets in
242 * each transfer. The field is 10 bits wide
244 #define MAX_TRANSFER_PACKETS ((1<<10)-1)
247 * Logical transactions may take numerous low level
248 * transactions, especially when splits are concerned. This
249 * enum represents all of the possible stages a transaction can
250 * be in. Note that split completes are always even. This is so
251 * the NAK handler can backup to the previous low level
252 * transaction with a simple clearing of bit 0.
254 enum cvmx_usb_stage
{
255 CVMX_USB_STAGE_NON_CONTROL
,
256 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
,
257 CVMX_USB_STAGE_SETUP
,
258 CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE
,
260 CVMX_USB_STAGE_DATA_SPLIT_COMPLETE
,
261 CVMX_USB_STAGE_STATUS
,
262 CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE
,
266 * struct cvmx_usb_transaction - describes each pending USB transaction
267 * regardless of type. These are linked together
268 * to form a list of pending requests for a pipe.
270 * @node: List node for transactions in the pipe.
271 * @type: Type of transaction, duplicated of the pipe.
272 * @flags: State flags for this transaction.
273 * @buffer: User's physical buffer address to read/write.
274 * @buffer_length: Size of the user's buffer in bytes.
275 * @control_header: For control transactions, physical address of the 8
276 * byte standard header.
277 * @iso_start_frame: For ISO transactions, the starting frame number.
278 * @iso_number_packets: For ISO transactions, the number of packets in the
280 * @iso_packets: For ISO transactions, the sub packets in the request.
281 * @actual_bytes: Actual bytes transfer for this transaction.
282 * @stage: For control transactions, the current stage.
285 struct cvmx_usb_transaction
{
286 struct list_head node
;
287 enum cvmx_usb_transfer type
;
290 uint64_t control_header
;
292 int iso_number_packets
;
293 struct cvmx_usb_iso_packet
*iso_packets
;
298 enum cvmx_usb_stage stage
;
303 * struct cvmx_usb_pipe - a pipe represents a virtual connection between Octeon
304 * and some USB device. It contains a list of pending
305 * request to the device.
307 * @node: List node for pipe list
308 * @next: Pipe after this one in the list
309 * @transactions: List of pending transactions
310 * @interval: For periodic pipes, the interval between packets in
312 * @next_tx_frame: The next frame this pipe is allowed to transmit on
313 * @flags: State flags for this pipe
314 * @device_speed: Speed of device connected to this pipe
315 * @transfer_type: Type of transaction supported by this pipe
316 * @transfer_dir: IN or OUT. Ignored for Control
317 * @multi_count: Max packet in a row for the device
318 * @max_packet: The device's maximum packet size in bytes
319 * @device_addr: USB device address at other end of pipe
320 * @endpoint_num: USB endpoint number at other end of pipe
321 * @hub_device_addr: Hub address this device is connected to
322 * @hub_port: Hub port this device is connected to
323 * @pid_toggle: This toggles between 0/1 on every packet send to track
324 * the data pid needed
325 * @channel: Hardware DMA channel for this pipe
326 * @split_sc_frame: The low order bits of the frame number the split
327 * complete should be sent on
329 struct cvmx_usb_pipe
{
330 struct list_head node
;
331 struct list_head transactions
;
333 uint64_t next_tx_frame
;
334 enum cvmx_usb_pipe_flags flags
;
335 enum cvmx_usb_speed device_speed
;
336 enum cvmx_usb_transfer transfer_type
;
337 enum cvmx_usb_direction transfer_dir
;
341 uint8_t endpoint_num
;
342 uint8_t hub_device_addr
;
346 int8_t split_sc_frame
;
349 struct cvmx_usb_tx_fifo
{
354 } entry
[MAX_CHANNELS
+1];
360 * struct cvmx_usb_state - the state of the USB block
362 * init_flags: Flags passed to initialize.
363 * index: Which USB block this is for.
364 * idle_hardware_channels: Bit set for every idle hardware channel.
365 * usbcx_hprt: Stored port status so we don't need to read a CSR to
367 * pipe_for_channel: Map channels to pipes.
368 * pipe: Storage for pipes.
369 * indent: Used by debug output to indent functions.
370 * port_status: Last port status used for change notification.
371 * idle_pipes: List of open pipes that have no transactions.
372 * active_pipes: Active pipes indexed by transfer type.
373 * frame_number: Increments every SOF interrupt for time keeping.
374 * active_split: Points to the current active split, or NULL.
376 struct cvmx_usb_state
{
379 int idle_hardware_channels
;
380 union cvmx_usbcx_hprt usbcx_hprt
;
381 struct cvmx_usb_pipe
*pipe_for_channel
[MAX_CHANNELS
];
383 struct cvmx_usb_port_status port_status
;
384 struct list_head idle_pipes
;
385 struct list_head active_pipes
[4];
386 uint64_t frame_number
;
387 struct cvmx_usb_transaction
*active_split
;
388 struct cvmx_usb_tx_fifo periodic
;
389 struct cvmx_usb_tx_fifo nonperiodic
;
394 struct cvmx_usb_state usb
;
397 /* This macro spins on a field waiting for it to reach a value */
398 #define CVMX_WAIT_FOR_FIELD32(address, type, field, op, value, timeout_usec)\
401 uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec * \
402 octeon_get_clock_rate() / 1000000; \
405 c.u32 = cvmx_usb_read_csr32(usb, address); \
406 if (c.s.field op (value)) { \
409 } else if (cvmx_get_cycle() > done) { \
419 * This macro logically sets a single field in a CSR. It does the sequence
420 * read, modify, and write
422 #define USB_SET_FIELD32(address, type, field, value) \
425 c.u32 = cvmx_usb_read_csr32(usb, address); \
427 cvmx_usb_write_csr32(usb, address, c.u32); \
430 /* Returns the IO address to push/pop stuff data from the FIFOs */
431 #define USB_FIFO_ADDRESS(channel, usb_index) \
432 (CVMX_USBCX_GOTGCTL(usb_index) + ((channel)+1)*0x1000)
435 * struct octeon_temp_buffer - a bounce buffer for USB transfers
436 * @temp_buffer: the newly allocated temporary buffer (including meta-data)
437 * @orig_buffer: the original buffer passed by the USB stack
438 * @data: the newly allocated temporary buffer (excluding meta-data)
440 * Both the DMA engine and FIFO mode will always transfer full 32-bit words. If
441 * the buffer is too short, we need to allocate a temporary one, and this struct
444 struct octeon_temp_buffer
{
450 static inline struct octeon_hcd
*cvmx_usb_to_octeon(struct cvmx_usb_state
*p
)
452 return container_of(p
, struct octeon_hcd
, usb
);
455 static inline struct usb_hcd
*octeon_to_hcd(struct octeon_hcd
*p
)
457 return container_of((void *)p
, struct usb_hcd
, hcd_priv
);
461 * octeon_alloc_temp_buffer - allocate a temporary buffer for USB transfer
464 * @mem_flags: Memory allocation flags.
466 * This function allocates a temporary bounce buffer whenever it's needed
467 * due to HW limitations.
469 static int octeon_alloc_temp_buffer(struct urb
*urb
, gfp_t mem_flags
)
471 struct octeon_temp_buffer
*temp
;
473 if (urb
->num_sgs
|| urb
->sg
||
474 (urb
->transfer_flags
& URB_NO_TRANSFER_DMA_MAP
) ||
475 !(urb
->transfer_buffer_length
% sizeof(u32
)))
478 temp
= kmalloc(ALIGN(urb
->transfer_buffer_length
, sizeof(u32
)) +
479 sizeof(*temp
), mem_flags
);
483 temp
->temp_buffer
= temp
;
484 temp
->orig_buffer
= urb
->transfer_buffer
;
485 if (usb_urb_dir_out(urb
))
486 memcpy(temp
->data
, urb
->transfer_buffer
,
487 urb
->transfer_buffer_length
);
488 urb
->transfer_buffer
= temp
->data
;
489 urb
->transfer_flags
|= URB_ALIGNED_TEMP_BUFFER
;
495 * octeon_free_temp_buffer - free a temporary buffer used by USB transfers.
498 * Frees a buffer allocated by octeon_alloc_temp_buffer().
500 static void octeon_free_temp_buffer(struct urb
*urb
)
502 struct octeon_temp_buffer
*temp
;
504 if (!(urb
->transfer_flags
& URB_ALIGNED_TEMP_BUFFER
))
507 temp
= container_of(urb
->transfer_buffer
, struct octeon_temp_buffer
,
509 if (usb_urb_dir_in(urb
))
510 memcpy(temp
->orig_buffer
, urb
->transfer_buffer
,
512 urb
->transfer_buffer
= temp
->orig_buffer
;
513 urb
->transfer_flags
&= ~URB_ALIGNED_TEMP_BUFFER
;
514 kfree(temp
->temp_buffer
);
518 * octeon_map_urb_for_dma - Octeon-specific map_urb_for_dma().
519 * @hcd: USB HCD structure.
521 * @mem_flags: Memory allocation flags.
523 static int octeon_map_urb_for_dma(struct usb_hcd
*hcd
, struct urb
*urb
,
528 ret
= octeon_alloc_temp_buffer(urb
, mem_flags
);
532 ret
= usb_hcd_map_urb_for_dma(hcd
, urb
, mem_flags
);
534 octeon_free_temp_buffer(urb
);
540 * octeon_unmap_urb_for_dma - Octeon-specific unmap_urb_for_dma()
541 * @hcd: USB HCD structure.
544 static void octeon_unmap_urb_for_dma(struct usb_hcd
*hcd
, struct urb
*urb
)
546 usb_hcd_unmap_urb_for_dma(hcd
, urb
);
547 octeon_free_temp_buffer(urb
);
551 * Read a USB 32bit CSR. It performs the necessary address swizzle
552 * for 32bit CSRs and logs the value in a readable format if
555 * @usb: USB block this access is for
556 * @address: 64bit address to read
558 * Returns: Result of the read
560 static inline uint32_t cvmx_usb_read_csr32(struct cvmx_usb_state
*usb
,
563 uint32_t result
= cvmx_read64_uint32(address
^ 4);
569 * Write a USB 32bit CSR. It performs the necessary address
570 * swizzle for 32bit CSRs and logs the value in a readable format
571 * if debugging is on.
573 * @usb: USB block this access is for
574 * @address: 64bit address to write
575 * @value: Value to write
577 static inline void cvmx_usb_write_csr32(struct cvmx_usb_state
*usb
,
578 uint64_t address
, uint32_t value
)
580 cvmx_write64_uint32(address
^ 4, value
);
581 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb
->index
));
585 * Return non zero if this pipe connects to a non HIGH speed
586 * device through a high speed hub.
588 * @usb: USB block this access is for
589 * @pipe: Pipe to check
591 * Returns: Non zero if we need to do split transactions
593 static inline int cvmx_usb_pipe_needs_split(struct cvmx_usb_state
*usb
,
594 struct cvmx_usb_pipe
*pipe
)
596 return pipe
->device_speed
!= CVMX_USB_SPEED_HIGH
&&
597 usb
->usbcx_hprt
.s
.prtspd
== CVMX_USB_SPEED_HIGH
;
602 * Trivial utility function to return the correct PID for a pipe
604 * @pipe: pipe to check
606 * Returns: PID for pipe
608 static inline int cvmx_usb_get_data_pid(struct cvmx_usb_pipe
*pipe
)
610 if (pipe
->pid_toggle
)
611 return 2; /* Data1 */
612 return 0; /* Data0 */
616 * Initialize a USB port for use. This must be called before any
617 * other access to the Octeon USB port is made. The port starts
618 * off in the disabled state.
620 * @usb: Pointer to an empty struct cvmx_usb_state
621 * that will be populated by the initialize call.
622 * This structure is then passed to all other USB
625 * Which Octeon USB port to initialize.
627 * Returns: 0 or a negative error code.
629 static int cvmx_usb_initialize(struct cvmx_usb_state
*usb
,
631 enum cvmx_usb_initialize_flags flags
)
633 union cvmx_usbnx_clk_ctl usbn_clk_ctl
;
634 union cvmx_usbnx_usbp_ctl_status usbn_usbp_ctl_status
;
637 memset(usb
, 0, sizeof(*usb
));
638 usb
->init_flags
= flags
;
640 /* Initialize the USB state structure */
641 usb
->index
= usb_port_number
;
642 INIT_LIST_HEAD(&usb
->idle_pipes
);
643 for (i
= 0; i
< ARRAY_SIZE(usb
->active_pipes
); i
++)
644 INIT_LIST_HEAD(&usb
->active_pipes
[i
]);
647 * Power On Reset and PHY Initialization
649 * 1. Wait for DCOK to assert (nothing to do)
651 * 2a. Write USBN0/1_CLK_CTL[POR] = 1 and
652 * USBN0/1_CLK_CTL[HRST,PRST,HCLK_RST] = 0
654 usbn_clk_ctl
.u64
= cvmx_read64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
));
655 usbn_clk_ctl
.s
.por
= 1;
656 usbn_clk_ctl
.s
.hrst
= 0;
657 usbn_clk_ctl
.s
.prst
= 0;
658 usbn_clk_ctl
.s
.hclk_rst
= 0;
659 usbn_clk_ctl
.s
.enable
= 0;
661 * 2b. Select the USB reference clock/crystal parameters by writing
662 * appropriate values to USBN0/1_CLK_CTL[P_C_SEL, P_RTYPE, P_COM_ON]
664 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND
) {
666 * The USB port uses 12/24/48MHz 2.5V board clock
667 * source at USB_XO. USB_XI should be tied to GND.
668 * Most Octeon evaluation boards require this setting
670 if (OCTEON_IS_MODEL(OCTEON_CN3XXX
) ||
671 OCTEON_IS_MODEL(OCTEON_CN56XX
) ||
672 OCTEON_IS_MODEL(OCTEON_CN50XX
))
673 /* From CN56XX,CN50XX,CN31XX,CN30XX manuals */
674 usbn_clk_ctl
.s
.p_rtype
= 2; /* p_rclk=1 & p_xenbn=0 */
676 /* From CN52XX manual */
677 usbn_clk_ctl
.s
.p_rtype
= 1;
679 switch (flags
& CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK
) {
680 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ
:
681 usbn_clk_ctl
.s
.p_c_sel
= 0;
683 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ
:
684 usbn_clk_ctl
.s
.p_c_sel
= 1;
686 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ
:
687 usbn_clk_ctl
.s
.p_c_sel
= 2;
692 * The USB port uses a 12MHz crystal as clock source
693 * at USB_XO and USB_XI
695 if (OCTEON_IS_MODEL(OCTEON_CN3XXX
))
696 /* From CN31XX,CN30XX manual */
697 usbn_clk_ctl
.s
.p_rtype
= 3; /* p_rclk=1 & p_xenbn=1 */
699 /* From CN56XX,CN52XX,CN50XX manuals. */
700 usbn_clk_ctl
.s
.p_rtype
= 0;
702 usbn_clk_ctl
.s
.p_c_sel
= 0;
705 * 2c. Select the HCLK via writing USBN0/1_CLK_CTL[DIVIDE, DIVIDE2] and
706 * setting USBN0/1_CLK_CTL[ENABLE] = 1. Divide the core clock down
707 * such that USB is as close as possible to 125Mhz
710 int divisor
= DIV_ROUND_UP(octeon_get_clock_rate(), 125000000);
711 /* Lower than 4 doesn't seem to work properly */
714 usbn_clk_ctl
.s
.divide
= divisor
;
715 usbn_clk_ctl
.s
.divide2
= 0;
717 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
), usbn_clk_ctl
.u64
);
718 /* 2d. Write USBN0/1_CLK_CTL[HCLK_RST] = 1 */
719 usbn_clk_ctl
.s
.hclk_rst
= 1;
720 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
), usbn_clk_ctl
.u64
);
721 /* 2e. Wait 64 core-clock cycles for HCLK to stabilize */
724 * 3. Program the power-on reset field in the USBN clock-control
726 * USBN_CLK_CTL[POR] = 0
728 usbn_clk_ctl
.s
.por
= 0;
729 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
), usbn_clk_ctl
.u64
);
730 /* 4. Wait 1 ms for PHY clock to start */
733 * 5. Program the Reset input from automatic test equipment field in the
734 * USBP control and status register:
735 * USBN_USBP_CTL_STATUS[ATE_RESET] = 1
737 usbn_usbp_ctl_status
.u64
=
738 cvmx_read64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb
->index
));
739 usbn_usbp_ctl_status
.s
.ate_reset
= 1;
740 cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb
->index
),
741 usbn_usbp_ctl_status
.u64
);
742 /* 6. Wait 10 cycles */
745 * 7. Clear ATE_RESET field in the USBN clock-control register:
746 * USBN_USBP_CTL_STATUS[ATE_RESET] = 0
748 usbn_usbp_ctl_status
.s
.ate_reset
= 0;
749 cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb
->index
),
750 usbn_usbp_ctl_status
.u64
);
752 * 8. Program the PHY reset field in the USBN clock-control register:
753 * USBN_CLK_CTL[PRST] = 1
755 usbn_clk_ctl
.s
.prst
= 1;
756 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
), usbn_clk_ctl
.u64
);
758 * 9. Program the USBP control and status register to select host or
759 * device mode. USBN_USBP_CTL_STATUS[HST_MODE] = 0 for host, = 1 for
762 usbn_usbp_ctl_status
.s
.hst_mode
= 0;
763 cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb
->index
),
764 usbn_usbp_ctl_status
.u64
);
768 * 11. Program the hreset_n field in the USBN clock-control register:
769 * USBN_CLK_CTL[HRST] = 1
771 usbn_clk_ctl
.s
.hrst
= 1;
772 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
), usbn_clk_ctl
.u64
);
773 /* 12. Proceed to USB core initialization */
774 usbn_clk_ctl
.s
.enable
= 1;
775 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
), usbn_clk_ctl
.u64
);
779 * USB Core Initialization
781 * 1. Read USBC_GHWCFG1, USBC_GHWCFG2, USBC_GHWCFG3, USBC_GHWCFG4 to
782 * determine USB core configuration parameters.
786 * 2. Program the following fields in the global AHB configuration
787 * register (USBC_GAHBCFG)
788 * DMA mode, USBC_GAHBCFG[DMAEn]: 1 = DMA mode, 0 = slave mode
789 * Burst length, USBC_GAHBCFG[HBSTLEN] = 0
790 * Nonperiodic TxFIFO empty level (slave mode only),
791 * USBC_GAHBCFG[NPTXFEMPLVL]
792 * Periodic TxFIFO empty level (slave mode only),
793 * USBC_GAHBCFG[PTXFEMPLVL]
794 * Global interrupt mask, USBC_GAHBCFG[GLBLINTRMSK] = 1
797 union cvmx_usbcx_gahbcfg usbcx_gahbcfg
;
798 /* Due to an errata, CN31XX doesn't support DMA */
799 if (OCTEON_IS_MODEL(OCTEON_CN31XX
))
800 usb
->init_flags
|= CVMX_USB_INITIALIZE_FLAGS_NO_DMA
;
801 usbcx_gahbcfg
.u32
= 0;
802 usbcx_gahbcfg
.s
.dmaen
= !(usb
->init_flags
&
803 CVMX_USB_INITIALIZE_FLAGS_NO_DMA
);
804 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)
805 /* Only use one channel with non DMA */
806 usb
->idle_hardware_channels
= 0x1;
807 else if (OCTEON_IS_MODEL(OCTEON_CN5XXX
))
808 /* CN5XXX have an errata with channel 3 */
809 usb
->idle_hardware_channels
= 0xf7;
811 usb
->idle_hardware_channels
= 0xff;
812 usbcx_gahbcfg
.s
.hbstlen
= 0;
813 usbcx_gahbcfg
.s
.nptxfemplvl
= 1;
814 usbcx_gahbcfg
.s
.ptxfemplvl
= 1;
815 usbcx_gahbcfg
.s
.glblintrmsk
= 1;
816 cvmx_usb_write_csr32(usb
, CVMX_USBCX_GAHBCFG(usb
->index
),
820 * 3. Program the following fields in USBC_GUSBCFG register.
821 * HS/FS timeout calibration, USBC_GUSBCFG[TOUTCAL] = 0
822 * ULPI DDR select, USBC_GUSBCFG[DDRSEL] = 0
823 * USB turnaround time, USBC_GUSBCFG[USBTRDTIM] = 0x5
824 * PHY low-power clock select, USBC_GUSBCFG[PHYLPWRCLKSEL] = 0
827 union cvmx_usbcx_gusbcfg usbcx_gusbcfg
;
829 usbcx_gusbcfg
.u32
= cvmx_usb_read_csr32(usb
,
830 CVMX_USBCX_GUSBCFG(usb
->index
));
831 usbcx_gusbcfg
.s
.toutcal
= 0;
832 usbcx_gusbcfg
.s
.ddrsel
= 0;
833 usbcx_gusbcfg
.s
.usbtrdtim
= 0x5;
834 usbcx_gusbcfg
.s
.phylpwrclksel
= 0;
835 cvmx_usb_write_csr32(usb
, CVMX_USBCX_GUSBCFG(usb
->index
),
839 * 4. The software must unmask the following bits in the USBC_GINTMSK
841 * OTG interrupt mask, USBC_GINTMSK[OTGINTMSK] = 1
842 * Mode mismatch interrupt mask, USBC_GINTMSK[MODEMISMSK] = 1
845 union cvmx_usbcx_gintmsk usbcx_gintmsk
;
848 usbcx_gintmsk
.u32
= cvmx_usb_read_csr32(usb
,
849 CVMX_USBCX_GINTMSK(usb
->index
));
850 usbcx_gintmsk
.s
.otgintmsk
= 1;
851 usbcx_gintmsk
.s
.modemismsk
= 1;
852 usbcx_gintmsk
.s
.hchintmsk
= 1;
853 usbcx_gintmsk
.s
.sofmsk
= 0;
854 /* We need RX FIFO interrupts if we don't have DMA */
855 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)
856 usbcx_gintmsk
.s
.rxflvlmsk
= 1;
857 cvmx_usb_write_csr32(usb
, CVMX_USBCX_GINTMSK(usb
->index
),
861 * Disable all channel interrupts. We'll enable them per channel
864 for (channel
= 0; channel
< 8; channel
++)
865 cvmx_usb_write_csr32(usb
,
866 CVMX_USBCX_HCINTMSKX(channel
, usb
->index
), 0);
871 * Host Port Initialization
873 * 1. Program the host-port interrupt-mask field to unmask,
874 * USBC_GINTMSK[PRTINT] = 1
876 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
),
877 union cvmx_usbcx_gintmsk
, prtintmsk
, 1);
878 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
),
879 union cvmx_usbcx_gintmsk
, disconnintmsk
, 1);
881 * 2. Program the USBC_HCFG register to select full-speed host
882 * or high-speed host.
885 union cvmx_usbcx_hcfg usbcx_hcfg
;
887 usbcx_hcfg
.u32
= cvmx_usb_read_csr32(usb
,
888 CVMX_USBCX_HCFG(usb
->index
));
889 usbcx_hcfg
.s
.fslssupp
= 0;
890 usbcx_hcfg
.s
.fslspclksel
= 0;
891 cvmx_usb_write_csr32(usb
, CVMX_USBCX_HCFG(usb
->index
),
895 * 3. Program the port power bit to drive VBUS on the USB,
896 * USBC_HPRT[PRTPWR] = 1
898 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb
->index
),
899 union cvmx_usbcx_hprt
, prtpwr
, 1);
902 * Steps 4-15 from the manual are done later in the port enable
911 * Shutdown a USB port after a call to cvmx_usb_initialize().
912 * The port should be disabled with all pipes closed when this
913 * function is called.
915 * @usb: USB device state populated by cvmx_usb_initialize().
917 * Returns: 0 or a negative error code.
919 static int cvmx_usb_shutdown(struct cvmx_usb_state
*usb
)
921 union cvmx_usbnx_clk_ctl usbn_clk_ctl
;
923 /* Make sure all pipes are closed */
924 if (!list_empty(&usb
->idle_pipes
) ||
925 !list_empty(&usb
->active_pipes
[CVMX_USB_TRANSFER_ISOCHRONOUS
]) ||
926 !list_empty(&usb
->active_pipes
[CVMX_USB_TRANSFER_INTERRUPT
]) ||
927 !list_empty(&usb
->active_pipes
[CVMX_USB_TRANSFER_CONTROL
]) ||
928 !list_empty(&usb
->active_pipes
[CVMX_USB_TRANSFER_BULK
]))
931 /* Disable the clocks and put them in power on reset */
932 usbn_clk_ctl
.u64
= cvmx_read64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
));
933 usbn_clk_ctl
.s
.enable
= 1;
934 usbn_clk_ctl
.s
.por
= 1;
935 usbn_clk_ctl
.s
.hclk_rst
= 1;
936 usbn_clk_ctl
.s
.prst
= 0;
937 usbn_clk_ctl
.s
.hrst
= 0;
938 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
), usbn_clk_ctl
.u64
);
944 * Enable a USB port. After this call succeeds, the USB port is
945 * online and servicing requests.
947 * @usb: USB device state populated by cvmx_usb_initialize().
949 * Returns: 0 or a negative error code.
951 static int cvmx_usb_enable(struct cvmx_usb_state
*usb
)
953 union cvmx_usbcx_ghwcfg3 usbcx_ghwcfg3
;
955 usb
->usbcx_hprt
.u32
= cvmx_usb_read_csr32(usb
,
956 CVMX_USBCX_HPRT(usb
->index
));
959 * If the port is already enabled the just return. We don't need to do
962 if (usb
->usbcx_hprt
.s
.prtena
)
965 /* If there is nothing plugged into the port then fail immediately */
966 if (!usb
->usbcx_hprt
.s
.prtconnsts
)
969 /* Program the port reset bit to start the reset process */
970 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb
->index
), union cvmx_usbcx_hprt
,
974 * Wait at least 50ms (high speed), or 10ms (full speed) for the reset
975 * process to complete.
979 /* Program the port reset bit to 0, USBC_HPRT[PRTRST] = 0 */
980 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb
->index
), union cvmx_usbcx_hprt
,
983 /* Wait for the USBC_HPRT[PRTENA]. */
984 if (CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_HPRT(usb
->index
),
985 union cvmx_usbcx_hprt
, prtena
, ==, 1, 100000))
989 * Read the port speed field to get the enumerated speed,
992 usb
->usbcx_hprt
.u32
= cvmx_usb_read_csr32(usb
,
993 CVMX_USBCX_HPRT(usb
->index
));
994 usbcx_ghwcfg3
.u32
= cvmx_usb_read_csr32(usb
,
995 CVMX_USBCX_GHWCFG3(usb
->index
));
998 * 13. Program the USBC_GRXFSIZ register to select the size of the
999 * receive FIFO (25%).
1001 USB_SET_FIELD32(CVMX_USBCX_GRXFSIZ(usb
->index
),
1002 union cvmx_usbcx_grxfsiz
, rxfdep
,
1003 usbcx_ghwcfg3
.s
.dfifodepth
/ 4);
1005 * 14. Program the USBC_GNPTXFSIZ register to select the size and the
1006 * start address of the non- periodic transmit FIFO for nonperiodic
1007 * transactions (50%).
1010 union cvmx_usbcx_gnptxfsiz siz
;
1012 siz
.u32
= cvmx_usb_read_csr32(usb
,
1013 CVMX_USBCX_GNPTXFSIZ(usb
->index
));
1014 siz
.s
.nptxfdep
= usbcx_ghwcfg3
.s
.dfifodepth
/ 2;
1015 siz
.s
.nptxfstaddr
= usbcx_ghwcfg3
.s
.dfifodepth
/ 4;
1016 cvmx_usb_write_csr32(usb
, CVMX_USBCX_GNPTXFSIZ(usb
->index
),
1020 * 15. Program the USBC_HPTXFSIZ register to select the size and start
1021 * address of the periodic transmit FIFO for periodic transactions
1025 union cvmx_usbcx_hptxfsiz siz
;
1027 siz
.u32
= cvmx_usb_read_csr32(usb
,
1028 CVMX_USBCX_HPTXFSIZ(usb
->index
));
1029 siz
.s
.ptxfsize
= usbcx_ghwcfg3
.s
.dfifodepth
/ 4;
1030 siz
.s
.ptxfstaddr
= 3 * usbcx_ghwcfg3
.s
.dfifodepth
/ 4;
1031 cvmx_usb_write_csr32(usb
, CVMX_USBCX_HPTXFSIZ(usb
->index
),
1034 /* Flush all FIFOs */
1035 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb
->index
),
1036 union cvmx_usbcx_grstctl
, txfnum
, 0x10);
1037 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb
->index
),
1038 union cvmx_usbcx_grstctl
, txfflsh
, 1);
1039 CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb
->index
),
1040 union cvmx_usbcx_grstctl
,
1041 txfflsh
, ==, 0, 100);
1042 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb
->index
),
1043 union cvmx_usbcx_grstctl
, rxfflsh
, 1);
1044 CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb
->index
),
1045 union cvmx_usbcx_grstctl
,
1046 rxfflsh
, ==, 0, 100);
1053 * Disable a USB port. After this call the USB port will not
1054 * generate data transfers and will not generate events.
1055 * Transactions in process will fail and call their
1056 * associated callbacks.
1058 * @usb: USB device state populated by cvmx_usb_initialize().
1060 * Returns: 0 or a negative error code.
1062 static int cvmx_usb_disable(struct cvmx_usb_state
*usb
)
1064 /* Disable the port */
1065 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb
->index
), union cvmx_usbcx_hprt
,
1072 * Get the current state of the USB port. Use this call to
1073 * determine if the usb port has anything connected, is enabled,
1074 * or has some sort of error condition. The return value of this
1075 * call has "changed" bits to signal of the value of some fields
1076 * have changed between calls.
1078 * @usb: USB device state populated by cvmx_usb_initialize().
1080 * Returns: Port status information
1082 static struct cvmx_usb_port_status
cvmx_usb_get_status(
1083 struct cvmx_usb_state
*usb
)
1085 union cvmx_usbcx_hprt usbc_hprt
;
1086 struct cvmx_usb_port_status result
;
1088 memset(&result
, 0, sizeof(result
));
1090 usbc_hprt
.u32
= cvmx_usb_read_csr32(usb
, CVMX_USBCX_HPRT(usb
->index
));
1091 result
.port_enabled
= usbc_hprt
.s
.prtena
;
1092 result
.port_over_current
= usbc_hprt
.s
.prtovrcurract
;
1093 result
.port_powered
= usbc_hprt
.s
.prtpwr
;
1094 result
.port_speed
= usbc_hprt
.s
.prtspd
;
1095 result
.connected
= usbc_hprt
.s
.prtconnsts
;
1096 result
.connect_change
=
1097 (result
.connected
!= usb
->port_status
.connected
);
1103 * Open a virtual pipe between the host and a USB device. A pipe
1104 * must be opened before data can be transferred between a device
1107 * @usb: USB device state populated by cvmx_usb_initialize().
1109 * USB device address to open the pipe to
1112 * USB endpoint number to open the pipe to
1115 * The speed of the device the pipe is going
1116 * to. This must match the device's speed,
1117 * which may be different than the port speed.
1118 * @max_packet: The maximum packet length the device can
1119 * transmit/receive (low speed=0-8, full
1120 * speed=0-1023, high speed=0-1024). This value
1121 * comes from the standard endpoint descriptor
1122 * field wMaxPacketSize bits <10:0>.
1124 * The type of transfer this pipe is for.
1126 * The direction the pipe is in. This is not
1127 * used for control pipes.
1128 * @interval: For ISOCHRONOUS and INTERRUPT transfers,
1129 * this is how often the transfer is scheduled
1130 * for. All other transfers should specify
1131 * zero. The units are in frames (8000/sec at
1132 * high speed, 1000/sec for full speed).
1134 * For high speed devices, this is the maximum
1135 * allowed number of packet per microframe.
1136 * Specify zero for non high speed devices. This
1137 * value comes from the standard endpoint descriptor
1138 * field wMaxPacketSize bits <12:11>.
1140 * Hub device address this device is connected
1141 * to. Devices connected directly to Octeon
1142 * use zero. This is only used when the device
1143 * is full/low speed behind a high speed hub.
1144 * The address will be of the high speed hub,
1145 * not and full speed hubs after it.
1146 * @hub_port: Which port on the hub the device is
1147 * connected. Use zero for devices connected
1148 * directly to Octeon. Like hub_device_addr,
1149 * this is only used for full/low speed
1150 * devices behind a high speed hub.
1152 * Returns: A non-NULL value is a pipe. NULL means an error.
1154 static struct cvmx_usb_pipe
*cvmx_usb_open_pipe(struct cvmx_usb_state
*usb
,
1160 enum cvmx_usb_transfer
1162 enum cvmx_usb_direction
1164 int interval
, int multi_count
,
1165 int hub_device_addr
,
1168 struct cvmx_usb_pipe
*pipe
;
1170 pipe
= kzalloc(sizeof(*pipe
), GFP_ATOMIC
);
1173 if ((device_speed
== CVMX_USB_SPEED_HIGH
) &&
1174 (transfer_dir
== CVMX_USB_DIRECTION_OUT
) &&
1175 (transfer_type
== CVMX_USB_TRANSFER_BULK
))
1176 pipe
->flags
|= __CVMX_USB_PIPE_FLAGS_NEED_PING
;
1177 pipe
->device_addr
= device_addr
;
1178 pipe
->endpoint_num
= endpoint_num
;
1179 pipe
->device_speed
= device_speed
;
1180 pipe
->max_packet
= max_packet
;
1181 pipe
->transfer_type
= transfer_type
;
1182 pipe
->transfer_dir
= transfer_dir
;
1183 INIT_LIST_HEAD(&pipe
->transactions
);
1186 * All pipes use interval to rate limit NAK processing. Force an
1187 * interval if one wasn't supplied
1191 if (cvmx_usb_pipe_needs_split(usb
, pipe
)) {
1192 pipe
->interval
= interval
*8;
1193 /* Force start splits to be schedule on uFrame 0 */
1194 pipe
->next_tx_frame
= ((usb
->frame_number
+7)&~7) +
1197 pipe
->interval
= interval
;
1198 pipe
->next_tx_frame
= usb
->frame_number
+ pipe
->interval
;
1200 pipe
->multi_count
= multi_count
;
1201 pipe
->hub_device_addr
= hub_device_addr
;
1202 pipe
->hub_port
= hub_port
;
1203 pipe
->pid_toggle
= 0;
1204 pipe
->split_sc_frame
= -1;
1205 list_add_tail(&pipe
->node
, &usb
->idle_pipes
);
1208 * We don't need to tell the hardware about this pipe yet since
1209 * it doesn't have any submitted requests
1217 * Poll the RX FIFOs and remove data as needed. This function is only used
1218 * in non DMA mode. It is very important that this function be called quickly
1219 * enough to prevent FIFO overflow.
1221 * @usb: USB device state populated by cvmx_usb_initialize().
1223 static void cvmx_usb_poll_rx_fifo(struct cvmx_usb_state
*usb
)
1225 union cvmx_usbcx_grxstsph rx_status
;
1231 rx_status
.u32
= cvmx_usb_read_csr32(usb
,
1232 CVMX_USBCX_GRXSTSPH(usb
->index
));
1233 /* Only read data if IN data is there */
1234 if (rx_status
.s
.pktsts
!= 2)
1236 /* Check if no data is available */
1237 if (!rx_status
.s
.bcnt
)
1240 channel
= rx_status
.s
.chnum
;
1241 bytes
= rx_status
.s
.bcnt
;
1245 /* Get where the DMA engine would have written this data */
1246 address
= cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb
->index
) +
1249 ptr
= cvmx_phys_to_ptr(address
);
1250 cvmx_write64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb
->index
) + channel
* 8,
1253 /* Loop writing the FIFO data for this packet into memory */
1255 *ptr
++ = cvmx_usb_read_csr32(usb
,
1256 USB_FIFO_ADDRESS(channel
, usb
->index
));
1264 * Fill the TX hardware fifo with data out of the software
1267 * @usb: USB device state populated by cvmx_usb_initialize().
1268 * @fifo: Software fifo to use
1269 * @available: Amount of space in the hardware fifo
1271 * Returns: Non zero if the hardware fifo was too small and needs
1272 * to be serviced again.
1274 static int cvmx_usb_fill_tx_hw(struct cvmx_usb_state
*usb
,
1275 struct cvmx_usb_tx_fifo
*fifo
, int available
)
1278 * We're done either when there isn't anymore space or the software FIFO
1281 while (available
&& (fifo
->head
!= fifo
->tail
)) {
1283 const uint32_t *ptr
= cvmx_phys_to_ptr(fifo
->entry
[i
].address
);
1284 uint64_t csr_address
= USB_FIFO_ADDRESS(fifo
->entry
[i
].channel
,
1286 int words
= available
;
1288 /* Limit the amount of data to waht the SW fifo has */
1289 if (fifo
->entry
[i
].size
<= available
) {
1290 words
= fifo
->entry
[i
].size
;
1292 if (fifo
->tail
> MAX_CHANNELS
)
1296 /* Update the next locations and counts */
1298 fifo
->entry
[i
].address
+= words
* 4;
1299 fifo
->entry
[i
].size
-= words
;
1302 * Write the HW fifo data. The read every three writes is due
1303 * to an errata on CN3XXX chips
1306 cvmx_write64_uint32(csr_address
, *ptr
++);
1307 cvmx_write64_uint32(csr_address
, *ptr
++);
1308 cvmx_write64_uint32(csr_address
, *ptr
++);
1310 CVMX_USBNX_DMA0_INB_CHN0(usb
->index
));
1313 cvmx_write64_uint32(csr_address
, *ptr
++);
1315 cvmx_write64_uint32(csr_address
, *ptr
++);
1317 cvmx_write64_uint32(csr_address
, *ptr
++);
1319 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb
->index
));
1321 return fifo
->head
!= fifo
->tail
;
1326 * Check the hardware FIFOs and fill them as needed
1328 * @usb: USB device state populated by cvmx_usb_initialize().
1330 static void cvmx_usb_poll_tx_fifo(struct cvmx_usb_state
*usb
)
1332 if (usb
->periodic
.head
!= usb
->periodic
.tail
) {
1333 union cvmx_usbcx_hptxsts tx_status
;
1335 tx_status
.u32
= cvmx_usb_read_csr32(usb
,
1336 CVMX_USBCX_HPTXSTS(usb
->index
));
1337 if (cvmx_usb_fill_tx_hw(usb
, &usb
->periodic
,
1338 tx_status
.s
.ptxfspcavail
))
1339 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
),
1340 union cvmx_usbcx_gintmsk
,
1343 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
),
1344 union cvmx_usbcx_gintmsk
,
1348 if (usb
->nonperiodic
.head
!= usb
->nonperiodic
.tail
) {
1349 union cvmx_usbcx_gnptxsts tx_status
;
1351 tx_status
.u32
= cvmx_usb_read_csr32(usb
,
1352 CVMX_USBCX_GNPTXSTS(usb
->index
));
1353 if (cvmx_usb_fill_tx_hw(usb
, &usb
->nonperiodic
,
1354 tx_status
.s
.nptxfspcavail
))
1355 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
),
1356 union cvmx_usbcx_gintmsk
,
1359 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
),
1360 union cvmx_usbcx_gintmsk
,
1367 * Fill the TX FIFO with an outgoing packet
1369 * @usb: USB device state populated by cvmx_usb_initialize().
1370 * @channel: Channel number to get packet from
1372 static void cvmx_usb_fill_tx_fifo(struct cvmx_usb_state
*usb
, int channel
)
1374 union cvmx_usbcx_hccharx hcchar
;
1375 union cvmx_usbcx_hcspltx usbc_hcsplt
;
1376 union cvmx_usbcx_hctsizx usbc_hctsiz
;
1377 struct cvmx_usb_tx_fifo
*fifo
;
1379 /* We only need to fill data on outbound channels */
1380 hcchar
.u32
= cvmx_usb_read_csr32(usb
,
1381 CVMX_USBCX_HCCHARX(channel
, usb
->index
));
1382 if (hcchar
.s
.epdir
!= CVMX_USB_DIRECTION_OUT
)
1385 /* OUT Splits only have data on the start and not the complete */
1386 usbc_hcsplt
.u32
= cvmx_usb_read_csr32(usb
,
1387 CVMX_USBCX_HCSPLTX(channel
, usb
->index
));
1388 if (usbc_hcsplt
.s
.spltena
&& usbc_hcsplt
.s
.compsplt
)
1392 * Find out how many bytes we need to fill and convert it into 32bit
1395 usbc_hctsiz
.u32
= cvmx_usb_read_csr32(usb
,
1396 CVMX_USBCX_HCTSIZX(channel
, usb
->index
));
1397 if (!usbc_hctsiz
.s
.xfersize
)
1400 if ((hcchar
.s
.eptype
== CVMX_USB_TRANSFER_INTERRUPT
) ||
1401 (hcchar
.s
.eptype
== CVMX_USB_TRANSFER_ISOCHRONOUS
))
1402 fifo
= &usb
->periodic
;
1404 fifo
= &usb
->nonperiodic
;
1406 fifo
->entry
[fifo
->head
].channel
= channel
;
1407 fifo
->entry
[fifo
->head
].address
=
1408 cvmx_read64_uint64(CVMX_USBNX_DMA0_OUTB_CHN0(usb
->index
) +
1410 fifo
->entry
[fifo
->head
].size
= (usbc_hctsiz
.s
.xfersize
+3)>>2;
1412 if (fifo
->head
> MAX_CHANNELS
)
1415 cvmx_usb_poll_tx_fifo(usb
);
1419 * Perform channel specific setup for Control transactions. All
1420 * the generic stuff will already have been done in cvmx_usb_start_channel().
1422 * @usb: USB device state populated by cvmx_usb_initialize().
1423 * @channel: Channel to setup
1424 * @pipe: Pipe for control transaction
1426 static void cvmx_usb_start_channel_control(struct cvmx_usb_state
*usb
,
1428 struct cvmx_usb_pipe
*pipe
)
1430 struct octeon_hcd
*priv
= cvmx_usb_to_octeon(usb
);
1431 struct usb_hcd
*hcd
= octeon_to_hcd(priv
);
1432 struct device
*dev
= hcd
->self
.controller
;
1433 struct cvmx_usb_transaction
*transaction
=
1434 list_first_entry(&pipe
->transactions
, typeof(*transaction
),
1436 struct usb_ctrlrequest
*header
=
1437 cvmx_phys_to_ptr(transaction
->control_header
);
1438 int bytes_to_transfer
= transaction
->buffer_length
-
1439 transaction
->actual_bytes
;
1440 int packets_to_transfer
;
1441 union cvmx_usbcx_hctsizx usbc_hctsiz
;
1443 usbc_hctsiz
.u32
= cvmx_usb_read_csr32(usb
,
1444 CVMX_USBCX_HCTSIZX(channel
, usb
->index
));
1446 switch (transaction
->stage
) {
1447 case CVMX_USB_STAGE_NON_CONTROL
:
1448 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
:
1449 dev_err(dev
, "%s: ERROR - Non control stage\n", __func__
);
1451 case CVMX_USB_STAGE_SETUP
:
1452 usbc_hctsiz
.s
.pid
= 3; /* Setup */
1453 bytes_to_transfer
= sizeof(*header
);
1454 /* All Control operations start with a setup going OUT */
1455 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1456 union cvmx_usbcx_hccharx
, epdir
,
1457 CVMX_USB_DIRECTION_OUT
);
1459 * Setup send the control header instead of the buffer data. The
1460 * buffer data will be used in the next stage
1462 cvmx_write64_uint64(CVMX_USBNX_DMA0_OUTB_CHN0(usb
->index
) +
1464 transaction
->control_header
);
1466 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE
:
1467 usbc_hctsiz
.s
.pid
= 3; /* Setup */
1468 bytes_to_transfer
= 0;
1469 /* All Control operations start with a setup going OUT */
1470 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1471 union cvmx_usbcx_hccharx
, epdir
,
1472 CVMX_USB_DIRECTION_OUT
);
1474 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel
, usb
->index
),
1475 union cvmx_usbcx_hcspltx
, compsplt
, 1);
1477 case CVMX_USB_STAGE_DATA
:
1478 usbc_hctsiz
.s
.pid
= cvmx_usb_get_data_pid(pipe
);
1479 if (cvmx_usb_pipe_needs_split(usb
, pipe
)) {
1480 if (header
->bRequestType
& USB_DIR_IN
)
1481 bytes_to_transfer
= 0;
1482 else if (bytes_to_transfer
> pipe
->max_packet
)
1483 bytes_to_transfer
= pipe
->max_packet
;
1485 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1486 union cvmx_usbcx_hccharx
, epdir
,
1487 ((header
->bRequestType
& USB_DIR_IN
) ?
1488 CVMX_USB_DIRECTION_IN
:
1489 CVMX_USB_DIRECTION_OUT
));
1491 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE
:
1492 usbc_hctsiz
.s
.pid
= cvmx_usb_get_data_pid(pipe
);
1493 if (!(header
->bRequestType
& USB_DIR_IN
))
1494 bytes_to_transfer
= 0;
1495 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1496 union cvmx_usbcx_hccharx
, epdir
,
1497 ((header
->bRequestType
& USB_DIR_IN
) ?
1498 CVMX_USB_DIRECTION_IN
:
1499 CVMX_USB_DIRECTION_OUT
));
1500 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel
, usb
->index
),
1501 union cvmx_usbcx_hcspltx
, compsplt
, 1);
1503 case CVMX_USB_STAGE_STATUS
:
1504 usbc_hctsiz
.s
.pid
= cvmx_usb_get_data_pid(pipe
);
1505 bytes_to_transfer
= 0;
1506 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1507 union cvmx_usbcx_hccharx
, epdir
,
1508 ((header
->bRequestType
& USB_DIR_IN
) ?
1509 CVMX_USB_DIRECTION_OUT
:
1510 CVMX_USB_DIRECTION_IN
));
1512 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE
:
1513 usbc_hctsiz
.s
.pid
= cvmx_usb_get_data_pid(pipe
);
1514 bytes_to_transfer
= 0;
1515 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1516 union cvmx_usbcx_hccharx
, epdir
,
1517 ((header
->bRequestType
& USB_DIR_IN
) ?
1518 CVMX_USB_DIRECTION_OUT
:
1519 CVMX_USB_DIRECTION_IN
));
1520 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel
, usb
->index
),
1521 union cvmx_usbcx_hcspltx
, compsplt
, 1);
1526 * Make sure the transfer never exceeds the byte limit of the hardware.
1527 * Further bytes will be sent as continued transactions
1529 if (bytes_to_transfer
> MAX_TRANSFER_BYTES
) {
1530 /* Round MAX_TRANSFER_BYTES to a multiple of out packet size */
1531 bytes_to_transfer
= MAX_TRANSFER_BYTES
/ pipe
->max_packet
;
1532 bytes_to_transfer
*= pipe
->max_packet
;
1536 * Calculate the number of packets to transfer. If the length is zero
1537 * we still need to transfer one packet
1539 packets_to_transfer
= DIV_ROUND_UP(bytes_to_transfer
,
1541 if (packets_to_transfer
== 0)
1542 packets_to_transfer
= 1;
1543 else if ((packets_to_transfer
> 1) &&
1544 (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)) {
1546 * Limit to one packet when not using DMA. Channels must be
1547 * restarted between every packet for IN transactions, so there
1548 * is no reason to do multiple packets in a row
1550 packets_to_transfer
= 1;
1551 bytes_to_transfer
= packets_to_transfer
* pipe
->max_packet
;
1552 } else if (packets_to_transfer
> MAX_TRANSFER_PACKETS
) {
1554 * Limit the number of packet and data transferred to what the
1555 * hardware can handle
1557 packets_to_transfer
= MAX_TRANSFER_PACKETS
;
1558 bytes_to_transfer
= packets_to_transfer
* pipe
->max_packet
;
1561 usbc_hctsiz
.s
.xfersize
= bytes_to_transfer
;
1562 usbc_hctsiz
.s
.pktcnt
= packets_to_transfer
;
1564 cvmx_usb_write_csr32(usb
, CVMX_USBCX_HCTSIZX(channel
, usb
->index
),
1570 * Start a channel to perform the pipe's head transaction
1572 * @usb: USB device state populated by cvmx_usb_initialize().
1573 * @channel: Channel to setup
1574 * @pipe: Pipe to start
1576 static void cvmx_usb_start_channel(struct cvmx_usb_state
*usb
, int channel
,
1577 struct cvmx_usb_pipe
*pipe
)
1579 struct cvmx_usb_transaction
*transaction
=
1580 list_first_entry(&pipe
->transactions
, typeof(*transaction
),
1583 /* Make sure all writes to the DMA region get flushed */
1586 /* Attach the channel to the pipe */
1587 usb
->pipe_for_channel
[channel
] = pipe
;
1588 pipe
->channel
= channel
;
1589 pipe
->flags
|= __CVMX_USB_PIPE_FLAGS_SCHEDULED
;
1591 /* Mark this channel as in use */
1592 usb
->idle_hardware_channels
&= ~(1<<channel
);
1594 /* Enable the channel interrupt bits */
1596 union cvmx_usbcx_hcintx usbc_hcint
;
1597 union cvmx_usbcx_hcintmskx usbc_hcintmsk
;
1598 union cvmx_usbcx_haintmsk usbc_haintmsk
;
1600 /* Clear all channel status bits */
1601 usbc_hcint
.u32
= cvmx_usb_read_csr32(usb
,
1602 CVMX_USBCX_HCINTX(channel
, usb
->index
));
1604 cvmx_usb_write_csr32(usb
,
1605 CVMX_USBCX_HCINTX(channel
, usb
->index
),
1608 usbc_hcintmsk
.u32
= 0;
1609 usbc_hcintmsk
.s
.chhltdmsk
= 1;
1610 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
) {
1612 * Channels need these extra interrupts when we aren't
1615 usbc_hcintmsk
.s
.datatglerrmsk
= 1;
1616 usbc_hcintmsk
.s
.frmovrunmsk
= 1;
1617 usbc_hcintmsk
.s
.bblerrmsk
= 1;
1618 usbc_hcintmsk
.s
.xacterrmsk
= 1;
1619 if (cvmx_usb_pipe_needs_split(usb
, pipe
)) {
1621 * Splits don't generate xfercompl, so we need
1624 usbc_hcintmsk
.s
.nyetmsk
= 1;
1625 usbc_hcintmsk
.s
.ackmsk
= 1;
1627 usbc_hcintmsk
.s
.nakmsk
= 1;
1628 usbc_hcintmsk
.s
.stallmsk
= 1;
1629 usbc_hcintmsk
.s
.xfercomplmsk
= 1;
1631 cvmx_usb_write_csr32(usb
,
1632 CVMX_USBCX_HCINTMSKX(channel
, usb
->index
),
1635 /* Enable the channel interrupt to propagate */
1636 usbc_haintmsk
.u32
= cvmx_usb_read_csr32(usb
,
1637 CVMX_USBCX_HAINTMSK(usb
->index
));
1638 usbc_haintmsk
.s
.haintmsk
|= 1<<channel
;
1639 cvmx_usb_write_csr32(usb
, CVMX_USBCX_HAINTMSK(usb
->index
),
1643 /* Setup the locations the DMA engines use */
1645 uint64_t dma_address
= transaction
->buffer
+
1646 transaction
->actual_bytes
;
1648 if (transaction
->type
== CVMX_USB_TRANSFER_ISOCHRONOUS
)
1649 dma_address
= transaction
->buffer
+
1650 transaction
->iso_packets
[0].offset
+
1651 transaction
->actual_bytes
;
1653 cvmx_write64_uint64(CVMX_USBNX_DMA0_OUTB_CHN0(usb
->index
) +
1656 cvmx_write64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb
->index
) +
1661 /* Setup both the size of the transfer and the SPLIT characteristics */
1663 union cvmx_usbcx_hcspltx usbc_hcsplt
= {.u32
= 0};
1664 union cvmx_usbcx_hctsizx usbc_hctsiz
= {.u32
= 0};
1665 int packets_to_transfer
;
1666 int bytes_to_transfer
= transaction
->buffer_length
-
1667 transaction
->actual_bytes
;
1670 * ISOCHRONOUS transactions store each individual transfer size
1671 * in the packet structure, not the global buffer_length
1673 if (transaction
->type
== CVMX_USB_TRANSFER_ISOCHRONOUS
)
1675 transaction
->iso_packets
[0].length
-
1676 transaction
->actual_bytes
;
1679 * We need to do split transactions when we are talking to non
1680 * high speed devices that are behind a high speed hub
1682 if (cvmx_usb_pipe_needs_split(usb
, pipe
)) {
1684 * On the start split phase (stage is even) record the
1685 * frame number we will need to send the split complete.
1686 * We only store the lower two bits since the time ahead
1687 * can only be two frames
1689 if ((transaction
->stage
&1) == 0) {
1690 if (transaction
->type
== CVMX_USB_TRANSFER_BULK
)
1691 pipe
->split_sc_frame
=
1692 (usb
->frame_number
+ 1) & 0x7f;
1694 pipe
->split_sc_frame
=
1695 (usb
->frame_number
+ 2) & 0x7f;
1697 pipe
->split_sc_frame
= -1;
1699 usbc_hcsplt
.s
.spltena
= 1;
1700 usbc_hcsplt
.s
.hubaddr
= pipe
->hub_device_addr
;
1701 usbc_hcsplt
.s
.prtaddr
= pipe
->hub_port
;
1702 usbc_hcsplt
.s
.compsplt
= (transaction
->stage
==
1703 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
);
1706 * SPLIT transactions can only ever transmit one data
1707 * packet so limit the transfer size to the max packet
1710 if (bytes_to_transfer
> pipe
->max_packet
)
1711 bytes_to_transfer
= pipe
->max_packet
;
1714 * ISOCHRONOUS OUT splits are unique in that they limit
1715 * data transfers to 188 byte chunks representing the
1716 * begin/middle/end of the data or all
1718 if (!usbc_hcsplt
.s
.compsplt
&&
1719 (pipe
->transfer_dir
==
1720 CVMX_USB_DIRECTION_OUT
) &&
1721 (pipe
->transfer_type
==
1722 CVMX_USB_TRANSFER_ISOCHRONOUS
)) {
1724 * Clear the split complete frame number as
1725 * there isn't going to be a split complete
1727 pipe
->split_sc_frame
= -1;
1729 * See if we've started this transfer and sent
1732 if (transaction
->actual_bytes
== 0) {
1734 * Nothing sent yet, this is either a
1735 * begin or the entire payload
1737 if (bytes_to_transfer
<= 188)
1738 /* Entire payload in one go */
1739 usbc_hcsplt
.s
.xactpos
= 3;
1741 /* First part of payload */
1742 usbc_hcsplt
.s
.xactpos
= 2;
1745 * Continuing the previous data, we must
1746 * either be in the middle or at the end
1748 if (bytes_to_transfer
<= 188)
1749 /* End of payload */
1750 usbc_hcsplt
.s
.xactpos
= 1;
1752 /* Middle of payload */
1753 usbc_hcsplt
.s
.xactpos
= 0;
1756 * Again, the transfer size is limited to 188
1759 if (bytes_to_transfer
> 188)
1760 bytes_to_transfer
= 188;
1765 * Make sure the transfer never exceeds the byte limit of the
1766 * hardware. Further bytes will be sent as continued
1769 if (bytes_to_transfer
> MAX_TRANSFER_BYTES
) {
1771 * Round MAX_TRANSFER_BYTES to a multiple of out packet
1774 bytes_to_transfer
= MAX_TRANSFER_BYTES
/
1776 bytes_to_transfer
*= pipe
->max_packet
;
1780 * Calculate the number of packets to transfer. If the length is
1781 * zero we still need to transfer one packet
1783 packets_to_transfer
=
1784 DIV_ROUND_UP(bytes_to_transfer
, pipe
->max_packet
);
1785 if (packets_to_transfer
== 0)
1786 packets_to_transfer
= 1;
1787 else if ((packets_to_transfer
> 1) &&
1789 CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)) {
1791 * Limit to one packet when not using DMA. Channels must
1792 * be restarted between every packet for IN
1793 * transactions, so there is no reason to do multiple
1796 packets_to_transfer
= 1;
1797 bytes_to_transfer
= packets_to_transfer
*
1799 } else if (packets_to_transfer
> MAX_TRANSFER_PACKETS
) {
1801 * Limit the number of packet and data transferred to
1802 * what the hardware can handle
1804 packets_to_transfer
= MAX_TRANSFER_PACKETS
;
1805 bytes_to_transfer
= packets_to_transfer
*
1809 usbc_hctsiz
.s
.xfersize
= bytes_to_transfer
;
1810 usbc_hctsiz
.s
.pktcnt
= packets_to_transfer
;
1812 /* Update the DATA0/DATA1 toggle */
1813 usbc_hctsiz
.s
.pid
= cvmx_usb_get_data_pid(pipe
);
1815 * High speed pipes may need a hardware ping before they start
1817 if (pipe
->flags
& __CVMX_USB_PIPE_FLAGS_NEED_PING
)
1818 usbc_hctsiz
.s
.dopng
= 1;
1820 cvmx_usb_write_csr32(usb
,
1821 CVMX_USBCX_HCSPLTX(channel
, usb
->index
),
1823 cvmx_usb_write_csr32(usb
,
1824 CVMX_USBCX_HCTSIZX(channel
, usb
->index
),
1828 /* Setup the Host Channel Characteristics Register */
1830 union cvmx_usbcx_hccharx usbc_hcchar
= {.u32
= 0};
1833 * Set the startframe odd/even properly. This is only used for
1836 usbc_hcchar
.s
.oddfrm
= usb
->frame_number
&1;
1839 * Set the number of back to back packets allowed by this
1840 * endpoint. Split transactions interpret "ec" as the number of
1841 * immediate retries of failure. These retries happen too
1842 * quickly, so we disable these entirely for splits
1844 if (cvmx_usb_pipe_needs_split(usb
, pipe
))
1845 usbc_hcchar
.s
.ec
= 1;
1846 else if (pipe
->multi_count
< 1)
1847 usbc_hcchar
.s
.ec
= 1;
1848 else if (pipe
->multi_count
> 3)
1849 usbc_hcchar
.s
.ec
= 3;
1851 usbc_hcchar
.s
.ec
= pipe
->multi_count
;
1853 /* Set the rest of the endpoint specific settings */
1854 usbc_hcchar
.s
.devaddr
= pipe
->device_addr
;
1855 usbc_hcchar
.s
.eptype
= transaction
->type
;
1856 usbc_hcchar
.s
.lspddev
=
1857 (pipe
->device_speed
== CVMX_USB_SPEED_LOW
);
1858 usbc_hcchar
.s
.epdir
= pipe
->transfer_dir
;
1859 usbc_hcchar
.s
.epnum
= pipe
->endpoint_num
;
1860 usbc_hcchar
.s
.mps
= pipe
->max_packet
;
1861 cvmx_usb_write_csr32(usb
,
1862 CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1866 /* Do transaction type specific fixups as needed */
1867 switch (transaction
->type
) {
1868 case CVMX_USB_TRANSFER_CONTROL
:
1869 cvmx_usb_start_channel_control(usb
, channel
, pipe
);
1871 case CVMX_USB_TRANSFER_BULK
:
1872 case CVMX_USB_TRANSFER_INTERRUPT
:
1874 case CVMX_USB_TRANSFER_ISOCHRONOUS
:
1875 if (!cvmx_usb_pipe_needs_split(usb
, pipe
)) {
1877 * ISO transactions require different PIDs depending on
1878 * direction and how many packets are needed
1880 if (pipe
->transfer_dir
== CVMX_USB_DIRECTION_OUT
) {
1881 if (pipe
->multi_count
< 2) /* Need DATA0 */
1883 CVMX_USBCX_HCTSIZX(channel
,
1885 union cvmx_usbcx_hctsizx
,
1887 else /* Need MDATA */
1889 CVMX_USBCX_HCTSIZX(channel
,
1891 union cvmx_usbcx_hctsizx
,
1898 union cvmx_usbcx_hctsizx usbc_hctsiz
= {.u32
=
1899 cvmx_usb_read_csr32(usb
,
1900 CVMX_USBCX_HCTSIZX(channel
, usb
->index
))};
1901 transaction
->xfersize
= usbc_hctsiz
.s
.xfersize
;
1902 transaction
->pktcnt
= usbc_hctsiz
.s
.pktcnt
;
1904 /* Remeber when we start a split transaction */
1905 if (cvmx_usb_pipe_needs_split(usb
, pipe
))
1906 usb
->active_split
= transaction
;
1907 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1908 union cvmx_usbcx_hccharx
, chena
, 1);
1909 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)
1910 cvmx_usb_fill_tx_fifo(usb
, channel
);
1915 * Find a pipe that is ready to be scheduled to hardware.
1916 * @usb: USB device state populated by cvmx_usb_initialize().
1917 * @list: Pipe list to search
1919 * Frame counter to use as a time reference.
1921 * Returns: Pipe or NULL if none are ready
1923 static struct cvmx_usb_pipe
*cvmx_usb_find_ready_pipe(
1924 struct cvmx_usb_state
*usb
,
1925 struct list_head
*list
,
1926 uint64_t current_frame
)
1928 struct cvmx_usb_pipe
*pipe
;
1930 list_for_each_entry(pipe
, list
, node
) {
1931 struct cvmx_usb_transaction
*t
=
1932 list_first_entry(&pipe
->transactions
, typeof(*t
),
1934 if (!(pipe
->flags
& __CVMX_USB_PIPE_FLAGS_SCHEDULED
) && t
&&
1935 (pipe
->next_tx_frame
<= current_frame
) &&
1936 ((pipe
->split_sc_frame
== -1) ||
1937 ((((int)current_frame
- (int)pipe
->split_sc_frame
)
1939 (!usb
->active_split
|| (usb
->active_split
== t
))) {
1949 * Called whenever a pipe might need to be scheduled to the
1952 * @usb: USB device state populated by cvmx_usb_initialize().
1953 * @is_sof: True if this schedule was called on a SOF interrupt.
1955 static void cvmx_usb_schedule(struct cvmx_usb_state
*usb
, int is_sof
)
1958 struct cvmx_usb_pipe
*pipe
;
1960 enum cvmx_usb_transfer ttype
;
1962 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
) {
1964 * Without DMA we need to be careful to not schedule something
1965 * at the end of a frame and cause an overrun.
1967 union cvmx_usbcx_hfnum hfnum
= {
1968 .u32
= cvmx_usb_read_csr32(usb
,
1969 CVMX_USBCX_HFNUM(usb
->index
))
1972 union cvmx_usbcx_hfir hfir
= {
1973 .u32
= cvmx_usb_read_csr32(usb
,
1974 CVMX_USBCX_HFIR(usb
->index
))
1977 if (hfnum
.s
.frrem
< hfir
.s
.frint
/4)
1981 while (usb
->idle_hardware_channels
) {
1982 /* Find an idle channel */
1983 channel
= __fls(usb
->idle_hardware_channels
);
1984 if (unlikely(channel
> 7))
1987 /* Find a pipe needing service */
1991 * Only process periodic pipes on SOF interrupts. This
1992 * way we are sure that the periodic data is sent in the
1993 * beginning of the frame
1995 pipe
= cvmx_usb_find_ready_pipe(usb
,
1997 CVMX_USB_TRANSFER_ISOCHRONOUS
,
2000 pipe
= cvmx_usb_find_ready_pipe(usb
,
2002 CVMX_USB_TRANSFER_INTERRUPT
,
2005 if (likely(!pipe
)) {
2006 pipe
= cvmx_usb_find_ready_pipe(usb
,
2008 CVMX_USB_TRANSFER_CONTROL
,
2011 pipe
= cvmx_usb_find_ready_pipe(usb
,
2013 CVMX_USB_TRANSFER_BULK
,
2019 cvmx_usb_start_channel(usb
, channel
, pipe
);
2024 * Only enable SOF interrupts when we have transactions pending in the
2025 * future that might need to be scheduled
2028 for (ttype
= CVMX_USB_TRANSFER_CONTROL
;
2029 ttype
<= CVMX_USB_TRANSFER_INTERRUPT
; ttype
++) {
2030 list_for_each_entry(pipe
, &usb
->active_pipes
[ttype
], node
) {
2031 if (pipe
->next_tx_frame
> usb
->frame_number
) {
2037 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
),
2038 union cvmx_usbcx_gintmsk
, sofmsk
, need_sof
);
2041 static void octeon_usb_urb_complete_callback(struct cvmx_usb_state
*usb
,
2042 enum cvmx_usb_complete status
,
2043 struct cvmx_usb_pipe
*pipe
,
2044 struct cvmx_usb_transaction
2046 int bytes_transferred
,
2049 struct octeon_hcd
*priv
= cvmx_usb_to_octeon(usb
);
2050 struct usb_hcd
*hcd
= octeon_to_hcd(priv
);
2051 struct device
*dev
= hcd
->self
.controller
;
2053 if (likely(status
== CVMX_USB_COMPLETE_SUCCESS
))
2054 urb
->actual_length
= bytes_transferred
;
2056 urb
->actual_length
= 0;
2060 /* For Isochronous transactions we need to update the URB packet status
2061 list from data in our private copy */
2062 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
2065 * The pointer to the private list is stored in the setup_packet
2068 struct cvmx_usb_iso_packet
*iso_packet
=
2069 (struct cvmx_usb_iso_packet
*) urb
->setup_packet
;
2070 /* Recalculate the transfer size by adding up each packet */
2071 urb
->actual_length
= 0;
2072 for (i
= 0; i
< urb
->number_of_packets
; i
++) {
2073 if (iso_packet
[i
].status
==
2074 CVMX_USB_COMPLETE_SUCCESS
) {
2075 urb
->iso_frame_desc
[i
].status
= 0;
2076 urb
->iso_frame_desc
[i
].actual_length
=
2077 iso_packet
[i
].length
;
2078 urb
->actual_length
+=
2079 urb
->iso_frame_desc
[i
].actual_length
;
2081 dev_dbg(dev
, "ISOCHRONOUS packet=%d of %d status=%d pipe=%p transaction=%p size=%d\n",
2082 i
, urb
->number_of_packets
,
2083 iso_packet
[i
].status
, pipe
,
2084 transaction
, iso_packet
[i
].length
);
2085 urb
->iso_frame_desc
[i
].status
= -EREMOTEIO
;
2088 /* Free the private list now that we don't need it anymore */
2090 urb
->setup_packet
= NULL
;
2094 case CVMX_USB_COMPLETE_SUCCESS
:
2097 case CVMX_USB_COMPLETE_CANCEL
:
2098 if (urb
->status
== 0)
2099 urb
->status
= -ENOENT
;
2101 case CVMX_USB_COMPLETE_STALL
:
2102 dev_dbg(dev
, "status=stall pipe=%p transaction=%p size=%d\n",
2103 pipe
, transaction
, bytes_transferred
);
2104 urb
->status
= -EPIPE
;
2106 case CVMX_USB_COMPLETE_BABBLEERR
:
2107 dev_dbg(dev
, "status=babble pipe=%p transaction=%p size=%d\n",
2108 pipe
, transaction
, bytes_transferred
);
2109 urb
->status
= -EPIPE
;
2111 case CVMX_USB_COMPLETE_SHORT
:
2112 dev_dbg(dev
, "status=short pipe=%p transaction=%p size=%d\n",
2113 pipe
, transaction
, bytes_transferred
);
2114 urb
->status
= -EREMOTEIO
;
2116 case CVMX_USB_COMPLETE_ERROR
:
2117 case CVMX_USB_COMPLETE_XACTERR
:
2118 case CVMX_USB_COMPLETE_DATATGLERR
:
2119 case CVMX_USB_COMPLETE_FRAMEERR
:
2120 dev_dbg(dev
, "status=%d pipe=%p transaction=%p size=%d\n",
2121 status
, pipe
, transaction
, bytes_transferred
);
2122 urb
->status
= -EPROTO
;
2125 usb_hcd_unlink_urb_from_ep(octeon_to_hcd(priv
), urb
);
2126 spin_unlock(&priv
->lock
);
2127 usb_hcd_giveback_urb(octeon_to_hcd(priv
), urb
, urb
->status
);
2128 spin_lock(&priv
->lock
);
2132 * Signal the completion of a transaction and free it. The
2133 * transaction will be removed from the pipe transaction list.
2135 * @usb: USB device state populated by cvmx_usb_initialize().
2136 * @pipe: Pipe the transaction is on
2138 * Transaction that completed
2142 static void cvmx_usb_perform_complete(struct cvmx_usb_state
*usb
,
2143 struct cvmx_usb_pipe
*pipe
,
2144 struct cvmx_usb_transaction
*transaction
,
2145 enum cvmx_usb_complete complete_code
)
2147 /* If this was a split then clear our split in progress marker */
2148 if (usb
->active_split
== transaction
)
2149 usb
->active_split
= NULL
;
2152 * Isochronous transactions need extra processing as they might not be
2153 * done after a single data transfer
2155 if (unlikely(transaction
->type
== CVMX_USB_TRANSFER_ISOCHRONOUS
)) {
2156 /* Update the number of bytes transferred in this ISO packet */
2157 transaction
->iso_packets
[0].length
= transaction
->actual_bytes
;
2158 transaction
->iso_packets
[0].status
= complete_code
;
2161 * If there are more ISOs pending and we succeeded, schedule the
2164 if ((transaction
->iso_number_packets
> 1) &&
2165 (complete_code
== CVMX_USB_COMPLETE_SUCCESS
)) {
2166 /* No bytes transferred for this packet as of yet */
2167 transaction
->actual_bytes
= 0;
2168 /* One less ISO waiting to transfer */
2169 transaction
->iso_number_packets
--;
2170 /* Increment to the next location in our packet array */
2171 transaction
->iso_packets
++;
2172 transaction
->stage
= CVMX_USB_STAGE_NON_CONTROL
;
2177 /* Remove the transaction from the pipe list */
2178 list_del(&transaction
->node
);
2179 if (list_empty(&pipe
->transactions
))
2180 list_move_tail(&pipe
->node
, &usb
->idle_pipes
);
2181 octeon_usb_urb_complete_callback(usb
, complete_code
, pipe
,
2183 transaction
->actual_bytes
,
2190 * Submit a usb transaction to a pipe. Called for all types
2194 * @pipe: Which pipe to submit to.
2195 * @type: Transaction type
2196 * @buffer: User buffer for the transaction
2198 * User buffer's length in bytes
2200 * For control transactions, the 8 byte standard header
2202 * For ISO transactions, the start frame
2203 * @iso_number_packets:
2204 * For ISO, the number of packet in the transaction.
2206 * A description of each ISO packet
2207 * @urb: URB for the callback
2209 * Returns: Transaction or NULL on failure.
2211 static struct cvmx_usb_transaction
*cvmx_usb_submit_transaction(
2212 struct cvmx_usb_state
*usb
,
2213 struct cvmx_usb_pipe
*pipe
,
2214 enum cvmx_usb_transfer type
,
2217 uint64_t control_header
,
2218 int iso_start_frame
,
2219 int iso_number_packets
,
2220 struct cvmx_usb_iso_packet
*iso_packets
,
2223 struct cvmx_usb_transaction
*transaction
;
2225 if (unlikely(pipe
->transfer_type
!= type
))
2228 transaction
= kzalloc(sizeof(*transaction
), GFP_ATOMIC
);
2229 if (unlikely(!transaction
))
2232 transaction
->type
= type
;
2233 transaction
->buffer
= buffer
;
2234 transaction
->buffer_length
= buffer_length
;
2235 transaction
->control_header
= control_header
;
2236 /* FIXME: This is not used, implement it. */
2237 transaction
->iso_start_frame
= iso_start_frame
;
2238 transaction
->iso_number_packets
= iso_number_packets
;
2239 transaction
->iso_packets
= iso_packets
;
2240 transaction
->urb
= urb
;
2241 if (transaction
->type
== CVMX_USB_TRANSFER_CONTROL
)
2242 transaction
->stage
= CVMX_USB_STAGE_SETUP
;
2244 transaction
->stage
= CVMX_USB_STAGE_NON_CONTROL
;
2246 if (!list_empty(&pipe
->transactions
)) {
2247 list_add_tail(&transaction
->node
, &pipe
->transactions
);
2249 list_add_tail(&transaction
->node
, &pipe
->transactions
);
2250 list_move_tail(&pipe
->node
,
2251 &usb
->active_pipes
[pipe
->transfer_type
]);
2254 * We may need to schedule the pipe if this was the head of the
2257 cvmx_usb_schedule(usb
, 0);
2265 * Call to submit a USB Bulk transfer to a pipe.
2267 * @usb: USB device state populated by cvmx_usb_initialize().
2268 * @pipe: Handle to the pipe for the transfer.
2271 * Returns: A submitted transaction or NULL on failure.
2273 static struct cvmx_usb_transaction
*cvmx_usb_submit_bulk(
2274 struct cvmx_usb_state
*usb
,
2275 struct cvmx_usb_pipe
*pipe
,
2278 return cvmx_usb_submit_transaction(usb
, pipe
, CVMX_USB_TRANSFER_BULK
,
2280 urb
->transfer_buffer_length
,
2281 0, /* control_header */
2282 0, /* iso_start_frame */
2283 0, /* iso_number_packets */
2284 NULL
, /* iso_packets */
2290 * Call to submit a USB Interrupt transfer to a pipe.
2292 * @usb: USB device state populated by cvmx_usb_initialize().
2293 * @pipe: Handle to the pipe for the transfer.
2294 * @urb: URB returned when the callback is called.
2296 * Returns: A submitted transaction or NULL on failure.
2298 static struct cvmx_usb_transaction
*cvmx_usb_submit_interrupt(
2299 struct cvmx_usb_state
*usb
,
2300 struct cvmx_usb_pipe
*pipe
,
2303 return cvmx_usb_submit_transaction(usb
, pipe
,
2304 CVMX_USB_TRANSFER_INTERRUPT
,
2306 urb
->transfer_buffer_length
,
2307 0, /* control_header */
2308 0, /* iso_start_frame */
2309 0, /* iso_number_packets */
2310 NULL
, /* iso_packets */
2316 * Call to submit a USB Control transfer to a pipe.
2318 * @usb: USB device state populated by cvmx_usb_initialize().
2319 * @pipe: Handle to the pipe for the transfer.
2322 * Returns: A submitted transaction or NULL on failure.
2324 static struct cvmx_usb_transaction
*cvmx_usb_submit_control(
2325 struct cvmx_usb_state
*usb
,
2326 struct cvmx_usb_pipe
*pipe
,
2329 int buffer_length
= urb
->transfer_buffer_length
;
2330 uint64_t control_header
= urb
->setup_dma
;
2331 struct usb_ctrlrequest
*header
= cvmx_phys_to_ptr(control_header
);
2333 if ((header
->bRequestType
& USB_DIR_IN
) == 0)
2334 buffer_length
= le16_to_cpu(header
->wLength
);
2336 return cvmx_usb_submit_transaction(usb
, pipe
,
2337 CVMX_USB_TRANSFER_CONTROL
,
2338 urb
->transfer_dma
, buffer_length
,
2340 0, /* iso_start_frame */
2341 0, /* iso_number_packets */
2342 NULL
, /* iso_packets */
2348 * Call to submit a USB Isochronous transfer to a pipe.
2350 * @usb: USB device state populated by cvmx_usb_initialize().
2351 * @pipe: Handle to the pipe for the transfer.
2352 * @urb: URB returned when the callback is called.
2354 * Returns: A submitted transaction or NULL on failure.
2356 static struct cvmx_usb_transaction
*cvmx_usb_submit_isochronous(
2357 struct cvmx_usb_state
*usb
,
2358 struct cvmx_usb_pipe
*pipe
,
2361 struct cvmx_usb_iso_packet
*packets
;
2363 packets
= (struct cvmx_usb_iso_packet
*) urb
->setup_packet
;
2364 return cvmx_usb_submit_transaction(usb
, pipe
,
2365 CVMX_USB_TRANSFER_ISOCHRONOUS
,
2367 urb
->transfer_buffer_length
,
2368 0, /* control_header */
2370 urb
->number_of_packets
,
2376 * Cancel one outstanding request in a pipe. Canceling a request
2377 * can fail if the transaction has already completed before cancel
2378 * is called. Even after a successful cancel call, it may take
2379 * a frame or two for the cvmx_usb_poll() function to call the
2380 * associated callback.
2382 * @usb: USB device state populated by cvmx_usb_initialize().
2383 * @pipe: Pipe to cancel requests in.
2384 * @transaction: Transaction to cancel, returned by the submit function.
2386 * Returns: 0 or a negative error code.
2388 static int cvmx_usb_cancel(struct cvmx_usb_state
*usb
,
2389 struct cvmx_usb_pipe
*pipe
,
2390 struct cvmx_usb_transaction
*transaction
)
2393 * If the transaction is the HEAD of the queue and scheduled. We need to
2396 if (list_first_entry(&pipe
->transactions
, typeof(*transaction
), node
) ==
2397 transaction
&& (pipe
->flags
& __CVMX_USB_PIPE_FLAGS_SCHEDULED
)) {
2398 union cvmx_usbcx_hccharx usbc_hcchar
;
2400 usb
->pipe_for_channel
[pipe
->channel
] = NULL
;
2401 pipe
->flags
&= ~__CVMX_USB_PIPE_FLAGS_SCHEDULED
;
2405 usbc_hcchar
.u32
= cvmx_usb_read_csr32(usb
,
2406 CVMX_USBCX_HCCHARX(pipe
->channel
, usb
->index
));
2408 * If the channel isn't enabled then the transaction already
2411 if (usbc_hcchar
.s
.chena
) {
2412 usbc_hcchar
.s
.chdis
= 1;
2413 cvmx_usb_write_csr32(usb
,
2414 CVMX_USBCX_HCCHARX(pipe
->channel
,
2419 cvmx_usb_perform_complete(usb
, pipe
, transaction
,
2420 CVMX_USB_COMPLETE_CANCEL
);
2426 * Cancel all outstanding requests in a pipe. Logically all this
2427 * does is call cvmx_usb_cancel() in a loop.
2429 * @usb: USB device state populated by cvmx_usb_initialize().
2430 * @pipe: Pipe to cancel requests in.
2432 * Returns: 0 or a negative error code.
2434 static int cvmx_usb_cancel_all(struct cvmx_usb_state
*usb
,
2435 struct cvmx_usb_pipe
*pipe
)
2437 struct cvmx_usb_transaction
*transaction
, *next
;
2439 /* Simply loop through and attempt to cancel each transaction */
2440 list_for_each_entry_safe(transaction
, next
, &pipe
->transactions
, node
) {
2441 int result
= cvmx_usb_cancel(usb
, pipe
, transaction
);
2443 if (unlikely(result
!= 0))
2451 * Close a pipe created with cvmx_usb_open_pipe().
2453 * @usb: USB device state populated by cvmx_usb_initialize().
2454 * @pipe: Pipe to close.
2456 * Returns: 0 or a negative error code. EBUSY is returned if the pipe has
2457 * outstanding transfers.
2459 static int cvmx_usb_close_pipe(struct cvmx_usb_state
*usb
,
2460 struct cvmx_usb_pipe
*pipe
)
2462 /* Fail if the pipe has pending transactions */
2463 if (!list_empty(&pipe
->transactions
))
2466 list_del(&pipe
->node
);
2473 * Get the current USB protocol level frame number. The frame
2474 * number is always in the range of 0-0x7ff.
2476 * @usb: USB device state populated by cvmx_usb_initialize().
2478 * Returns: USB frame number
2480 static int cvmx_usb_get_frame_number(struct cvmx_usb_state
*usb
)
2483 union cvmx_usbcx_hfnum usbc_hfnum
;
2485 usbc_hfnum
.u32
= cvmx_usb_read_csr32(usb
, CVMX_USBCX_HFNUM(usb
->index
));
2486 frame_number
= usbc_hfnum
.s
.frnum
;
2488 return frame_number
;
2493 * Poll a channel for status
2496 * @channel: Channel to poll
2498 * Returns: Zero on success
2500 static int cvmx_usb_poll_channel(struct cvmx_usb_state
*usb
, int channel
)
2502 struct octeon_hcd
*priv
= cvmx_usb_to_octeon(usb
);
2503 struct usb_hcd
*hcd
= octeon_to_hcd(priv
);
2504 struct device
*dev
= hcd
->self
.controller
;
2505 union cvmx_usbcx_hcintx usbc_hcint
;
2506 union cvmx_usbcx_hctsizx usbc_hctsiz
;
2507 union cvmx_usbcx_hccharx usbc_hcchar
;
2508 struct cvmx_usb_pipe
*pipe
;
2509 struct cvmx_usb_transaction
*transaction
;
2510 int bytes_this_transfer
;
2511 int bytes_in_last_packet
;
2512 int packets_processed
;
2513 int buffer_space_left
;
2515 /* Read the interrupt status bits for the channel */
2516 usbc_hcint
.u32
= cvmx_usb_read_csr32(usb
,
2517 CVMX_USBCX_HCINTX(channel
, usb
->index
));
2519 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
) {
2520 usbc_hcchar
.u32
= cvmx_usb_read_csr32(usb
,
2521 CVMX_USBCX_HCCHARX(channel
, usb
->index
));
2523 if (usbc_hcchar
.s
.chena
&& usbc_hcchar
.s
.chdis
) {
2525 * There seems to be a bug in CN31XX which can cause
2526 * interrupt IN transfers to get stuck until we do a
2527 * write of HCCHARX without changing things
2529 cvmx_usb_write_csr32(usb
,
2530 CVMX_USBCX_HCCHARX(channel
,
2537 * In non DMA mode the channels don't halt themselves. We need
2538 * to manually disable channels that are left running
2540 if (!usbc_hcint
.s
.chhltd
) {
2541 if (usbc_hcchar
.s
.chena
) {
2542 union cvmx_usbcx_hcintmskx hcintmsk
;
2543 /* Disable all interrupts except CHHLTD */
2545 hcintmsk
.s
.chhltdmsk
= 1;
2546 cvmx_usb_write_csr32(usb
,
2547 CVMX_USBCX_HCINTMSKX(channel
,
2550 usbc_hcchar
.s
.chdis
= 1;
2551 cvmx_usb_write_csr32(usb
,
2552 CVMX_USBCX_HCCHARX(channel
,
2556 } else if (usbc_hcint
.s
.xfercompl
) {
2558 * Successful IN/OUT with transfer complete.
2559 * Channel halt isn't needed.
2562 dev_err(dev
, "USB%d: Channel %d interrupt without halt\n",
2563 usb
->index
, channel
);
2569 * There is are no interrupts that we need to process when the
2570 * channel is still running
2572 if (!usbc_hcint
.s
.chhltd
)
2576 /* Disable the channel interrupts now that it is done */
2577 cvmx_usb_write_csr32(usb
, CVMX_USBCX_HCINTMSKX(channel
, usb
->index
), 0);
2578 usb
->idle_hardware_channels
|= (1<<channel
);
2580 /* Make sure this channel is tied to a valid pipe */
2581 pipe
= usb
->pipe_for_channel
[channel
];
2585 transaction
= list_first_entry(&pipe
->transactions
,
2586 typeof(*transaction
),
2588 prefetch(transaction
);
2591 * Disconnect this pipe from the HW channel. Later the schedule
2592 * function will figure out which pipe needs to go
2594 usb
->pipe_for_channel
[channel
] = NULL
;
2595 pipe
->flags
&= ~__CVMX_USB_PIPE_FLAGS_SCHEDULED
;
2598 * Read the channel config info so we can figure out how much data
2601 usbc_hcchar
.u32
= cvmx_usb_read_csr32(usb
,
2602 CVMX_USBCX_HCCHARX(channel
, usb
->index
));
2603 usbc_hctsiz
.u32
= cvmx_usb_read_csr32(usb
,
2604 CVMX_USBCX_HCTSIZX(channel
, usb
->index
));
2607 * Calculating the number of bytes successfully transferred is dependent
2608 * on the transfer direction
2610 packets_processed
= transaction
->pktcnt
- usbc_hctsiz
.s
.pktcnt
;
2611 if (usbc_hcchar
.s
.epdir
) {
2613 * IN transactions are easy. For every byte received the
2614 * hardware decrements xfersize. All we need to do is subtract
2615 * the current value of xfersize from its starting value and we
2616 * know how many bytes were written to the buffer
2618 bytes_this_transfer
= transaction
->xfersize
-
2619 usbc_hctsiz
.s
.xfersize
;
2622 * OUT transaction don't decrement xfersize. Instead pktcnt is
2623 * decremented on every successful packet send. The hardware
2624 * does this when it receives an ACK, or NYET. If it doesn't
2625 * receive one of these responses pktcnt doesn't change
2627 bytes_this_transfer
= packets_processed
* usbc_hcchar
.s
.mps
;
2629 * The last packet may not be a full transfer if we didn't have
2632 if (bytes_this_transfer
> transaction
->xfersize
)
2633 bytes_this_transfer
= transaction
->xfersize
;
2635 /* Figure out how many bytes were in the last packet of the transfer */
2636 if (packets_processed
)
2637 bytes_in_last_packet
= bytes_this_transfer
-
2638 (packets_processed
- 1) * usbc_hcchar
.s
.mps
;
2640 bytes_in_last_packet
= bytes_this_transfer
;
2643 * As a special case, setup transactions output the setup header, not
2644 * the user's data. For this reason we don't count setup data as bytes
2647 if ((transaction
->stage
== CVMX_USB_STAGE_SETUP
) ||
2648 (transaction
->stage
== CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE
))
2649 bytes_this_transfer
= 0;
2652 * Add the bytes transferred to the running total. It is important that
2653 * bytes_this_transfer doesn't count any data that needs to be
2656 transaction
->actual_bytes
+= bytes_this_transfer
;
2657 if (transaction
->type
== CVMX_USB_TRANSFER_ISOCHRONOUS
)
2658 buffer_space_left
= transaction
->iso_packets
[0].length
-
2659 transaction
->actual_bytes
;
2661 buffer_space_left
= transaction
->buffer_length
-
2662 transaction
->actual_bytes
;
2665 * We need to remember the PID toggle state for the next transaction.
2666 * The hardware already updated it for the next transaction
2668 pipe
->pid_toggle
= !(usbc_hctsiz
.s
.pid
== 0);
2671 * For high speed bulk out, assume the next transaction will need to do
2672 * a ping before proceeding. If this isn't true the ACK processing below
2673 * will clear this flag
2675 if ((pipe
->device_speed
== CVMX_USB_SPEED_HIGH
) &&
2676 (pipe
->transfer_type
== CVMX_USB_TRANSFER_BULK
) &&
2677 (pipe
->transfer_dir
== CVMX_USB_DIRECTION_OUT
))
2678 pipe
->flags
|= __CVMX_USB_PIPE_FLAGS_NEED_PING
;
2680 if (usbc_hcint
.s
.stall
) {
2682 * STALL as a response means this transaction cannot be
2683 * completed because the device can't process transactions. Tell
2684 * the user. Any data that was transferred will be counted on
2685 * the actual bytes transferred
2687 pipe
->pid_toggle
= 0;
2688 cvmx_usb_perform_complete(usb
, pipe
, transaction
,
2689 CVMX_USB_COMPLETE_STALL
);
2690 } else if (usbc_hcint
.s
.xacterr
) {
2692 * We know at least one packet worked if we get a ACK or NAK.
2693 * Reset the retry counter
2695 if (usbc_hcint
.s
.nak
|| usbc_hcint
.s
.ack
)
2696 transaction
->retries
= 0;
2697 transaction
->retries
++;
2698 if (transaction
->retries
> MAX_RETRIES
) {
2700 * XactErr as a response means the device signaled
2701 * something wrong with the transfer. For example, PID
2702 * toggle errors cause these
2704 cvmx_usb_perform_complete(usb
, pipe
, transaction
,
2705 CVMX_USB_COMPLETE_XACTERR
);
2708 * If this was a split then clear our split in progress
2711 if (usb
->active_split
== transaction
)
2712 usb
->active_split
= NULL
;
2714 * Rewind to the beginning of the transaction by anding
2715 * off the split complete bit
2717 transaction
->stage
&= ~1;
2718 pipe
->split_sc_frame
= -1;
2719 pipe
->next_tx_frame
+= pipe
->interval
;
2720 if (pipe
->next_tx_frame
< usb
->frame_number
)
2721 pipe
->next_tx_frame
=
2722 usb
->frame_number
+ pipe
->interval
-
2723 (usb
->frame_number
-
2724 pipe
->next_tx_frame
) % pipe
->interval
;
2726 } else if (usbc_hcint
.s
.bblerr
) {
2727 /* Babble Error (BblErr) */
2728 cvmx_usb_perform_complete(usb
, pipe
, transaction
,
2729 CVMX_USB_COMPLETE_BABBLEERR
);
2730 } else if (usbc_hcint
.s
.datatglerr
) {
2731 /* Data toggle error */
2732 cvmx_usb_perform_complete(usb
, pipe
, transaction
,
2733 CVMX_USB_COMPLETE_DATATGLERR
);
2734 } else if (usbc_hcint
.s
.nyet
) {
2736 * NYET as a response is only allowed in three cases: as a
2737 * response to a ping, as a response to a split transaction, and
2738 * as a response to a bulk out. The ping case is handled by
2739 * hardware, so we only have splits and bulk out
2741 if (!cvmx_usb_pipe_needs_split(usb
, pipe
)) {
2742 transaction
->retries
= 0;
2744 * If there is more data to go then we need to try
2745 * again. Otherwise this transaction is complete
2747 if ((buffer_space_left
== 0) ||
2748 (bytes_in_last_packet
< pipe
->max_packet
))
2749 cvmx_usb_perform_complete(usb
, pipe
,
2751 CVMX_USB_COMPLETE_SUCCESS
);
2754 * Split transactions retry the split complete 4 times
2755 * then rewind to the start split and do the entire
2756 * transactions again
2758 transaction
->retries
++;
2759 if ((transaction
->retries
& 0x3) == 0) {
2761 * Rewind to the beginning of the transaction by
2762 * anding off the split complete bit
2764 transaction
->stage
&= ~1;
2765 pipe
->split_sc_frame
= -1;
2768 } else if (usbc_hcint
.s
.ack
) {
2769 transaction
->retries
= 0;
2771 * The ACK bit can only be checked after the other error bits.
2772 * This is because a multi packet transfer may succeed in a
2773 * number of packets and then get a different response on the
2774 * last packet. In this case both ACK and the last response bit
2775 * will be set. If none of the other response bits is set, then
2776 * the last packet must have been an ACK
2778 * Since we got an ACK, we know we don't need to do a ping on
2781 pipe
->flags
&= ~__CVMX_USB_PIPE_FLAGS_NEED_PING
;
2783 switch (transaction
->type
) {
2784 case CVMX_USB_TRANSFER_CONTROL
:
2785 switch (transaction
->stage
) {
2786 case CVMX_USB_STAGE_NON_CONTROL
:
2787 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
:
2788 /* This should be impossible */
2789 cvmx_usb_perform_complete(usb
, pipe
,
2790 transaction
, CVMX_USB_COMPLETE_ERROR
);
2792 case CVMX_USB_STAGE_SETUP
:
2793 pipe
->pid_toggle
= 1;
2794 if (cvmx_usb_pipe_needs_split(usb
, pipe
))
2795 transaction
->stage
=
2796 CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE
;
2798 struct usb_ctrlrequest
*header
=
2799 cvmx_phys_to_ptr(transaction
->control_header
);
2800 if (header
->wLength
)
2801 transaction
->stage
=
2802 CVMX_USB_STAGE_DATA
;
2804 transaction
->stage
=
2805 CVMX_USB_STAGE_STATUS
;
2808 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE
:
2810 struct usb_ctrlrequest
*header
=
2811 cvmx_phys_to_ptr(transaction
->control_header
);
2812 if (header
->wLength
)
2813 transaction
->stage
=
2814 CVMX_USB_STAGE_DATA
;
2816 transaction
->stage
=
2817 CVMX_USB_STAGE_STATUS
;
2820 case CVMX_USB_STAGE_DATA
:
2821 if (cvmx_usb_pipe_needs_split(usb
, pipe
)) {
2822 transaction
->stage
=
2823 CVMX_USB_STAGE_DATA_SPLIT_COMPLETE
;
2825 * For setup OUT data that are splits,
2826 * the hardware doesn't appear to count
2827 * transferred data. Here we manually
2828 * update the data transferred
2830 if (!usbc_hcchar
.s
.epdir
) {
2831 if (buffer_space_left
< pipe
->max_packet
)
2832 transaction
->actual_bytes
+=
2835 transaction
->actual_bytes
+=
2838 } else if ((buffer_space_left
== 0) ||
2839 (bytes_in_last_packet
<
2840 pipe
->max_packet
)) {
2841 pipe
->pid_toggle
= 1;
2842 transaction
->stage
=
2843 CVMX_USB_STAGE_STATUS
;
2846 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE
:
2847 if ((buffer_space_left
== 0) ||
2848 (bytes_in_last_packet
<
2849 pipe
->max_packet
)) {
2850 pipe
->pid_toggle
= 1;
2851 transaction
->stage
=
2852 CVMX_USB_STAGE_STATUS
;
2854 transaction
->stage
=
2855 CVMX_USB_STAGE_DATA
;
2858 case CVMX_USB_STAGE_STATUS
:
2859 if (cvmx_usb_pipe_needs_split(usb
, pipe
))
2860 transaction
->stage
=
2861 CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE
;
2863 cvmx_usb_perform_complete(usb
, pipe
,
2865 CVMX_USB_COMPLETE_SUCCESS
);
2867 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE
:
2868 cvmx_usb_perform_complete(usb
, pipe
,
2870 CVMX_USB_COMPLETE_SUCCESS
);
2874 case CVMX_USB_TRANSFER_BULK
:
2875 case CVMX_USB_TRANSFER_INTERRUPT
:
2877 * The only time a bulk transfer isn't complete when it
2878 * finishes with an ACK is during a split transaction.
2879 * For splits we need to continue the transfer if more
2882 if (cvmx_usb_pipe_needs_split(usb
, pipe
)) {
2883 if (transaction
->stage
==
2884 CVMX_USB_STAGE_NON_CONTROL
)
2885 transaction
->stage
=
2886 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
;
2888 if (buffer_space_left
&&
2889 (bytes_in_last_packet
==
2891 transaction
->stage
=
2892 CVMX_USB_STAGE_NON_CONTROL
;
2894 if (transaction
->type
==
2895 CVMX_USB_TRANSFER_INTERRUPT
)
2896 pipe
->next_tx_frame
+=
2898 cvmx_usb_perform_complete(
2902 CVMX_USB_COMPLETE_SUCCESS
);
2906 if ((pipe
->device_speed
==
2907 CVMX_USB_SPEED_HIGH
) &&
2908 (pipe
->transfer_type
==
2909 CVMX_USB_TRANSFER_BULK
) &&
2910 (pipe
->transfer_dir
==
2911 CVMX_USB_DIRECTION_OUT
) &&
2914 __CVMX_USB_PIPE_FLAGS_NEED_PING
;
2915 if (!buffer_space_left
||
2916 (bytes_in_last_packet
<
2917 pipe
->max_packet
)) {
2918 if (transaction
->type
==
2919 CVMX_USB_TRANSFER_INTERRUPT
)
2920 pipe
->next_tx_frame
+=
2922 cvmx_usb_perform_complete(usb
, pipe
,
2924 CVMX_USB_COMPLETE_SUCCESS
);
2928 case CVMX_USB_TRANSFER_ISOCHRONOUS
:
2929 if (cvmx_usb_pipe_needs_split(usb
, pipe
)) {
2931 * ISOCHRONOUS OUT splits don't require a
2932 * complete split stage. Instead they use a
2933 * sequence of begin OUT splits to transfer the
2934 * data 188 bytes at a time. Once the transfer
2935 * is complete, the pipe sleeps until the next
2938 if (pipe
->transfer_dir
==
2939 CVMX_USB_DIRECTION_OUT
) {
2941 * If no space left or this wasn't a max
2942 * size packet then this transfer is
2943 * complete. Otherwise start it again to
2944 * send the next 188 bytes
2946 if (!buffer_space_left
||
2947 (bytes_this_transfer
< 188)) {
2948 pipe
->next_tx_frame
+=
2950 cvmx_usb_perform_complete(usb
,
2952 CVMX_USB_COMPLETE_SUCCESS
);
2955 if (transaction
->stage
==
2956 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
) {
2958 * We are in the incoming data
2959 * phase. Keep getting data
2960 * until we run out of space or
2961 * get a small packet
2963 if ((buffer_space_left
== 0) ||
2964 (bytes_in_last_packet
<
2965 pipe
->max_packet
)) {
2966 pipe
->next_tx_frame
+=
2968 cvmx_usb_perform_complete(
2972 CVMX_USB_COMPLETE_SUCCESS
);
2975 transaction
->stage
=
2976 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
;
2979 pipe
->next_tx_frame
+= pipe
->interval
;
2980 cvmx_usb_perform_complete(usb
, pipe
,
2982 CVMX_USB_COMPLETE_SUCCESS
);
2986 } else if (usbc_hcint
.s
.nak
) {
2988 * If this was a split then clear our split in progress marker.
2990 if (usb
->active_split
== transaction
)
2991 usb
->active_split
= NULL
;
2993 * NAK as a response means the device couldn't accept the
2994 * transaction, but it should be retried in the future. Rewind
2995 * to the beginning of the transaction by anding off the split
2996 * complete bit. Retry in the next interval
2998 transaction
->retries
= 0;
2999 transaction
->stage
&= ~1;
3000 pipe
->next_tx_frame
+= pipe
->interval
;
3001 if (pipe
->next_tx_frame
< usb
->frame_number
)
3002 pipe
->next_tx_frame
= usb
->frame_number
+
3004 (usb
->frame_number
- pipe
->next_tx_frame
) %
3007 struct cvmx_usb_port_status port
;
3009 port
= cvmx_usb_get_status(usb
);
3010 if (port
.port_enabled
) {
3011 /* We'll retry the exact same transaction again */
3012 transaction
->retries
++;
3015 * We get channel halted interrupts with no result bits
3016 * sets when the cable is unplugged
3018 cvmx_usb_perform_complete(usb
, pipe
, transaction
,
3019 CVMX_USB_COMPLETE_ERROR
);
3025 static void octeon_usb_port_callback(struct cvmx_usb_state
*usb
)
3027 struct octeon_hcd
*priv
= cvmx_usb_to_octeon(usb
);
3029 spin_unlock(&priv
->lock
);
3030 usb_hcd_poll_rh_status(octeon_to_hcd(priv
));
3031 spin_lock(&priv
->lock
);
3035 * Poll the USB block for status and call all needed callback
3036 * handlers. This function is meant to be called in the interrupt
3037 * handler for the USB controller. It can also be called
3038 * periodically in a loop for non-interrupt based operation.
3040 * @usb: USB device state populated by cvmx_usb_initialize().
3042 * Returns: 0 or a negative error code.
3044 static int cvmx_usb_poll(struct cvmx_usb_state
*usb
)
3046 union cvmx_usbcx_hfnum usbc_hfnum
;
3047 union cvmx_usbcx_gintsts usbc_gintsts
;
3049 prefetch_range(usb
, sizeof(*usb
));
3051 /* Update the frame counter */
3052 usbc_hfnum
.u32
= cvmx_usb_read_csr32(usb
, CVMX_USBCX_HFNUM(usb
->index
));
3053 if ((usb
->frame_number
&0x3fff) > usbc_hfnum
.s
.frnum
)
3054 usb
->frame_number
+= 0x4000;
3055 usb
->frame_number
&= ~0x3fffull
;
3056 usb
->frame_number
|= usbc_hfnum
.s
.frnum
;
3058 /* Read the pending interrupts */
3059 usbc_gintsts
.u32
= cvmx_usb_read_csr32(usb
,
3060 CVMX_USBCX_GINTSTS(usb
->index
));
3062 /* Clear the interrupts now that we know about them */
3063 cvmx_usb_write_csr32(usb
, CVMX_USBCX_GINTSTS(usb
->index
),
3066 if (usbc_gintsts
.s
.rxflvl
) {
3068 * RxFIFO Non-Empty (RxFLvl)
3069 * Indicates that there is at least one packet pending to be
3070 * read from the RxFIFO.
3072 * In DMA mode this is handled by hardware
3074 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)
3075 cvmx_usb_poll_rx_fifo(usb
);
3077 if (usbc_gintsts
.s
.ptxfemp
|| usbc_gintsts
.s
.nptxfemp
) {
3078 /* Fill the Tx FIFOs when not in DMA mode */
3079 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)
3080 cvmx_usb_poll_tx_fifo(usb
);
3082 if (usbc_gintsts
.s
.disconnint
|| usbc_gintsts
.s
.prtint
) {
3083 union cvmx_usbcx_hprt usbc_hprt
;
3085 * Disconnect Detected Interrupt (DisconnInt)
3086 * Asserted when a device disconnect is detected.
3088 * Host Port Interrupt (PrtInt)
3089 * The core sets this bit to indicate a change in port status of
3090 * one of the O2P USB core ports in Host mode. The application
3091 * must read the Host Port Control and Status (HPRT) register to
3092 * determine the exact event that caused this interrupt. The
3093 * application must clear the appropriate status bit in the Host
3094 * Port Control and Status register to clear this bit.
3096 * Call the user's port callback
3098 octeon_usb_port_callback(usb
);
3099 /* Clear the port change bits */
3100 usbc_hprt
.u32
= cvmx_usb_read_csr32(usb
,
3101 CVMX_USBCX_HPRT(usb
->index
));
3102 usbc_hprt
.s
.prtena
= 0;
3103 cvmx_usb_write_csr32(usb
, CVMX_USBCX_HPRT(usb
->index
),
3106 if (usbc_gintsts
.s
.hchint
) {
3108 * Host Channels Interrupt (HChInt)
3109 * The core sets this bit to indicate that an interrupt is
3110 * pending on one of the channels of the core (in Host mode).
3111 * The application must read the Host All Channels Interrupt
3112 * (HAINT) register to determine the exact number of the channel
3113 * on which the interrupt occurred, and then read the
3114 * corresponding Host Channel-n Interrupt (HCINTn) register to
3115 * determine the exact cause of the interrupt. The application
3116 * must clear the appropriate status bit in the HCINTn register
3117 * to clear this bit.
3119 union cvmx_usbcx_haint usbc_haint
;
3121 usbc_haint
.u32
= cvmx_usb_read_csr32(usb
,
3122 CVMX_USBCX_HAINT(usb
->index
));
3123 while (usbc_haint
.u32
) {
3126 channel
= __fls(usbc_haint
.u32
);
3127 cvmx_usb_poll_channel(usb
, channel
);
3128 usbc_haint
.u32
^= 1<<channel
;
3132 cvmx_usb_schedule(usb
, usbc_gintsts
.s
.sof
);
3137 /* convert between an HCD pointer and the corresponding struct octeon_hcd */
3138 static inline struct octeon_hcd
*hcd_to_octeon(struct usb_hcd
*hcd
)
3140 return (struct octeon_hcd
*)(hcd
->hcd_priv
);
3143 static irqreturn_t
octeon_usb_irq(struct usb_hcd
*hcd
)
3145 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3146 unsigned long flags
;
3148 spin_lock_irqsave(&priv
->lock
, flags
);
3149 cvmx_usb_poll(&priv
->usb
);
3150 spin_unlock_irqrestore(&priv
->lock
, flags
);
3154 static int octeon_usb_start(struct usb_hcd
*hcd
)
3156 hcd
->state
= HC_STATE_RUNNING
;
3160 static void octeon_usb_stop(struct usb_hcd
*hcd
)
3162 hcd
->state
= HC_STATE_HALT
;
3165 static int octeon_usb_get_frame_number(struct usb_hcd
*hcd
)
3167 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3169 return cvmx_usb_get_frame_number(&priv
->usb
);
3172 static int octeon_usb_urb_enqueue(struct usb_hcd
*hcd
,
3176 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3177 struct device
*dev
= hcd
->self
.controller
;
3178 struct cvmx_usb_transaction
*transaction
= NULL
;
3179 struct cvmx_usb_pipe
*pipe
;
3180 unsigned long flags
;
3181 struct cvmx_usb_iso_packet
*iso_packet
;
3182 struct usb_host_endpoint
*ep
= urb
->ep
;
3186 spin_lock_irqsave(&priv
->lock
, flags
);
3188 rc
= usb_hcd_link_urb_to_ep(hcd
, urb
);
3190 spin_unlock_irqrestore(&priv
->lock
, flags
);
3195 enum cvmx_usb_transfer transfer_type
;
3196 enum cvmx_usb_speed speed
;
3197 int split_device
= 0;
3200 switch (usb_pipetype(urb
->pipe
)) {
3201 case PIPE_ISOCHRONOUS
:
3202 transfer_type
= CVMX_USB_TRANSFER_ISOCHRONOUS
;
3204 case PIPE_INTERRUPT
:
3205 transfer_type
= CVMX_USB_TRANSFER_INTERRUPT
;
3208 transfer_type
= CVMX_USB_TRANSFER_CONTROL
;
3211 transfer_type
= CVMX_USB_TRANSFER_BULK
;
3214 switch (urb
->dev
->speed
) {
3216 speed
= CVMX_USB_SPEED_LOW
;
3218 case USB_SPEED_FULL
:
3219 speed
= CVMX_USB_SPEED_FULL
;
3222 speed
= CVMX_USB_SPEED_HIGH
;
3226 * For slow devices on high speed ports we need to find the hub
3227 * that does the speed translation so we know where to send the
3228 * split transactions.
3230 if (speed
!= CVMX_USB_SPEED_HIGH
) {
3232 * Start at this device and work our way up the usb
3235 struct usb_device
*dev
= urb
->dev
;
3237 while (dev
->parent
) {
3239 * If our parent is high speed then he'll
3240 * receive the splits.
3242 if (dev
->parent
->speed
== USB_SPEED_HIGH
) {
3243 split_device
= dev
->parent
->devnum
;
3244 split_port
= dev
->portnum
;
3248 * Move up the tree one level. If we make it all
3249 * the way up the tree, then the port must not
3250 * be in high speed mode and we don't need a
3256 pipe
= cvmx_usb_open_pipe(&priv
->usb
, usb_pipedevice(urb
->pipe
),
3257 usb_pipeendpoint(urb
->pipe
), speed
,
3258 le16_to_cpu(ep
->desc
.wMaxPacketSize
)
3261 usb_pipein(urb
->pipe
) ?
3262 CVMX_USB_DIRECTION_IN
:
3263 CVMX_USB_DIRECTION_OUT
,
3265 (le16_to_cpu(ep
->desc
.wMaxPacketSize
)
3267 split_device
, split_port
);
3269 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
3270 spin_unlock_irqrestore(&priv
->lock
, flags
);
3271 dev_dbg(dev
, "Failed to create pipe\n");
3279 switch (usb_pipetype(urb
->pipe
)) {
3280 case PIPE_ISOCHRONOUS
:
3281 dev_dbg(dev
, "Submit isochronous to %d.%d\n",
3282 usb_pipedevice(urb
->pipe
),
3283 usb_pipeendpoint(urb
->pipe
));
3285 * Allocate a structure to use for our private list of
3286 * isochronous packets.
3288 iso_packet
= kmalloc(urb
->number_of_packets
*
3289 sizeof(struct cvmx_usb_iso_packet
),
3293 /* Fill the list with the data from the URB */
3294 for (i
= 0; i
< urb
->number_of_packets
; i
++) {
3295 iso_packet
[i
].offset
=
3296 urb
->iso_frame_desc
[i
].offset
;
3297 iso_packet
[i
].length
=
3298 urb
->iso_frame_desc
[i
].length
;
3299 iso_packet
[i
].status
=
3300 CVMX_USB_COMPLETE_ERROR
;
3303 * Store a pointer to the list in the URB setup_packet
3304 * field. We know this currently isn't being used and
3305 * this saves us a bunch of logic.
3307 urb
->setup_packet
= (char *)iso_packet
;
3308 transaction
= cvmx_usb_submit_isochronous(&priv
->usb
,
3311 * If submit failed we need to free our private packet
3315 urb
->setup_packet
= NULL
;
3320 case PIPE_INTERRUPT
:
3321 dev_dbg(dev
, "Submit interrupt to %d.%d\n",
3322 usb_pipedevice(urb
->pipe
),
3323 usb_pipeendpoint(urb
->pipe
));
3324 transaction
= cvmx_usb_submit_interrupt(&priv
->usb
, pipe
, urb
);
3327 dev_dbg(dev
, "Submit control to %d.%d\n",
3328 usb_pipedevice(urb
->pipe
),
3329 usb_pipeendpoint(urb
->pipe
));
3330 transaction
= cvmx_usb_submit_control(&priv
->usb
, pipe
, urb
);
3333 dev_dbg(dev
, "Submit bulk to %d.%d\n",
3334 usb_pipedevice(urb
->pipe
),
3335 usb_pipeendpoint(urb
->pipe
));
3336 transaction
= cvmx_usb_submit_bulk(&priv
->usb
, pipe
, urb
);
3340 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
3341 spin_unlock_irqrestore(&priv
->lock
, flags
);
3342 dev_dbg(dev
, "Failed to submit\n");
3345 urb
->hcpriv
= transaction
;
3346 spin_unlock_irqrestore(&priv
->lock
, flags
);
3350 static int octeon_usb_urb_dequeue(struct usb_hcd
*hcd
,
3354 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3355 unsigned long flags
;
3361 spin_lock_irqsave(&priv
->lock
, flags
);
3363 rc
= usb_hcd_check_unlink_urb(hcd
, urb
, status
);
3367 urb
->status
= status
;
3368 cvmx_usb_cancel(&priv
->usb
, urb
->ep
->hcpriv
, urb
->hcpriv
);
3371 spin_unlock_irqrestore(&priv
->lock
, flags
);
3376 static void octeon_usb_endpoint_disable(struct usb_hcd
*hcd
,
3377 struct usb_host_endpoint
*ep
)
3379 struct device
*dev
= hcd
->self
.controller
;
3382 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3383 struct cvmx_usb_pipe
*pipe
= ep
->hcpriv
;
3384 unsigned long flags
;
3386 spin_lock_irqsave(&priv
->lock
, flags
);
3387 cvmx_usb_cancel_all(&priv
->usb
, pipe
);
3388 if (cvmx_usb_close_pipe(&priv
->usb
, pipe
))
3389 dev_dbg(dev
, "Closing pipe %p failed\n", pipe
);
3390 spin_unlock_irqrestore(&priv
->lock
, flags
);
3395 static int octeon_usb_hub_status_data(struct usb_hcd
*hcd
, char *buf
)
3397 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3398 struct cvmx_usb_port_status port_status
;
3399 unsigned long flags
;
3401 spin_lock_irqsave(&priv
->lock
, flags
);
3402 port_status
= cvmx_usb_get_status(&priv
->usb
);
3403 spin_unlock_irqrestore(&priv
->lock
, flags
);
3405 buf
[0] = port_status
.connect_change
<< 1;
3410 static int octeon_usb_hub_control(struct usb_hcd
*hcd
, u16 typeReq
, u16 wValue
,
3411 u16 wIndex
, char *buf
, u16 wLength
)
3413 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3414 struct device
*dev
= hcd
->self
.controller
;
3415 struct cvmx_usb_port_status usb_port_status
;
3417 struct usb_hub_descriptor
*desc
;
3418 unsigned long flags
;
3421 case ClearHubFeature
:
3422 dev_dbg(dev
, "ClearHubFeature\n");
3424 case C_HUB_LOCAL_POWER
:
3425 case C_HUB_OVER_CURRENT
:
3426 /* Nothing required here */
3432 case ClearPortFeature
:
3433 dev_dbg(dev
, "ClearPortFeature\n");
3435 dev_dbg(dev
, " INVALID\n");
3440 case USB_PORT_FEAT_ENABLE
:
3441 dev_dbg(dev
, " ENABLE\n");
3442 spin_lock_irqsave(&priv
->lock
, flags
);
3443 cvmx_usb_disable(&priv
->usb
);
3444 spin_unlock_irqrestore(&priv
->lock
, flags
);
3446 case USB_PORT_FEAT_SUSPEND
:
3447 dev_dbg(dev
, " SUSPEND\n");
3448 /* Not supported on Octeon */
3450 case USB_PORT_FEAT_POWER
:
3451 dev_dbg(dev
, " POWER\n");
3452 /* Not supported on Octeon */
3454 case USB_PORT_FEAT_INDICATOR
:
3455 dev_dbg(dev
, " INDICATOR\n");
3456 /* Port inidicator not supported */
3458 case USB_PORT_FEAT_C_CONNECTION
:
3459 dev_dbg(dev
, " C_CONNECTION\n");
3460 /* Clears drivers internal connect status change flag */
3461 spin_lock_irqsave(&priv
->lock
, flags
);
3462 priv
->usb
.port_status
=
3463 cvmx_usb_get_status(&priv
->usb
);
3464 spin_unlock_irqrestore(&priv
->lock
, flags
);
3466 case USB_PORT_FEAT_C_RESET
:
3467 dev_dbg(dev
, " C_RESET\n");
3469 * Clears the driver's internal Port Reset Change flag.
3471 spin_lock_irqsave(&priv
->lock
, flags
);
3472 priv
->usb
.port_status
=
3473 cvmx_usb_get_status(&priv
->usb
);
3474 spin_unlock_irqrestore(&priv
->lock
, flags
);
3476 case USB_PORT_FEAT_C_ENABLE
:
3477 dev_dbg(dev
, " C_ENABLE\n");
3479 * Clears the driver's internal Port Enable/Disable
3482 spin_lock_irqsave(&priv
->lock
, flags
);
3483 priv
->usb
.port_status
=
3484 cvmx_usb_get_status(&priv
->usb
);
3485 spin_unlock_irqrestore(&priv
->lock
, flags
);
3487 case USB_PORT_FEAT_C_SUSPEND
:
3488 dev_dbg(dev
, " C_SUSPEND\n");
3490 * Clears the driver's internal Port Suspend Change
3491 * flag, which is set when resume signaling on the host
3495 case USB_PORT_FEAT_C_OVER_CURRENT
:
3496 dev_dbg(dev
, " C_OVER_CURRENT\n");
3497 /* Clears the driver's overcurrent Change flag */
3498 spin_lock_irqsave(&priv
->lock
, flags
);
3499 priv
->usb
.port_status
=
3500 cvmx_usb_get_status(&priv
->usb
);
3501 spin_unlock_irqrestore(&priv
->lock
, flags
);
3504 dev_dbg(dev
, " UNKNOWN\n");
3508 case GetHubDescriptor
:
3509 dev_dbg(dev
, "GetHubDescriptor\n");
3510 desc
= (struct usb_hub_descriptor
*)buf
;
3511 desc
->bDescLength
= 9;
3512 desc
->bDescriptorType
= 0x29;
3513 desc
->bNbrPorts
= 1;
3514 desc
->wHubCharacteristics
= cpu_to_le16(0x08);
3515 desc
->bPwrOn2PwrGood
= 1;
3516 desc
->bHubContrCurrent
= 0;
3517 desc
->u
.hs
.DeviceRemovable
[0] = 0;
3518 desc
->u
.hs
.DeviceRemovable
[1] = 0xff;
3521 dev_dbg(dev
, "GetHubStatus\n");
3522 *(__le32
*) buf
= 0;
3525 dev_dbg(dev
, "GetPortStatus\n");
3527 dev_dbg(dev
, " INVALID\n");
3531 spin_lock_irqsave(&priv
->lock
, flags
);
3532 usb_port_status
= cvmx_usb_get_status(&priv
->usb
);
3533 spin_unlock_irqrestore(&priv
->lock
, flags
);
3536 if (usb_port_status
.connect_change
) {
3537 port_status
|= (1 << USB_PORT_FEAT_C_CONNECTION
);
3538 dev_dbg(dev
, " C_CONNECTION\n");
3541 if (usb_port_status
.port_enabled
) {
3542 port_status
|= (1 << USB_PORT_FEAT_C_ENABLE
);
3543 dev_dbg(dev
, " C_ENABLE\n");
3546 if (usb_port_status
.connected
) {
3547 port_status
|= (1 << USB_PORT_FEAT_CONNECTION
);
3548 dev_dbg(dev
, " CONNECTION\n");
3551 if (usb_port_status
.port_enabled
) {
3552 port_status
|= (1 << USB_PORT_FEAT_ENABLE
);
3553 dev_dbg(dev
, " ENABLE\n");
3556 if (usb_port_status
.port_over_current
) {
3557 port_status
|= (1 << USB_PORT_FEAT_OVER_CURRENT
);
3558 dev_dbg(dev
, " OVER_CURRENT\n");
3561 if (usb_port_status
.port_powered
) {
3562 port_status
|= (1 << USB_PORT_FEAT_POWER
);
3563 dev_dbg(dev
, " POWER\n");
3566 if (usb_port_status
.port_speed
== CVMX_USB_SPEED_HIGH
) {
3567 port_status
|= USB_PORT_STAT_HIGH_SPEED
;
3568 dev_dbg(dev
, " HIGHSPEED\n");
3569 } else if (usb_port_status
.port_speed
== CVMX_USB_SPEED_LOW
) {
3570 port_status
|= (1 << USB_PORT_FEAT_LOWSPEED
);
3571 dev_dbg(dev
, " LOWSPEED\n");
3574 *((__le32
*) buf
) = cpu_to_le32(port_status
);
3577 dev_dbg(dev
, "SetHubFeature\n");
3578 /* No HUB features supported */
3580 case SetPortFeature
:
3581 dev_dbg(dev
, "SetPortFeature\n");
3583 dev_dbg(dev
, " INVALID\n");
3588 case USB_PORT_FEAT_SUSPEND
:
3589 dev_dbg(dev
, " SUSPEND\n");
3591 case USB_PORT_FEAT_POWER
:
3592 dev_dbg(dev
, " POWER\n");
3594 case USB_PORT_FEAT_RESET
:
3595 dev_dbg(dev
, " RESET\n");
3596 spin_lock_irqsave(&priv
->lock
, flags
);
3597 cvmx_usb_disable(&priv
->usb
);
3598 if (cvmx_usb_enable(&priv
->usb
))
3599 dev_dbg(dev
, "Failed to enable the port\n");
3600 spin_unlock_irqrestore(&priv
->lock
, flags
);
3602 case USB_PORT_FEAT_INDICATOR
:
3603 dev_dbg(dev
, " INDICATOR\n");
3607 dev_dbg(dev
, " UNKNOWN\n");
3612 dev_dbg(dev
, "Unknown root hub request\n");
3618 static const struct hc_driver octeon_hc_driver
= {
3619 .description
= "Octeon USB",
3620 .product_desc
= "Octeon Host Controller",
3621 .hcd_priv_size
= sizeof(struct octeon_hcd
),
3622 .irq
= octeon_usb_irq
,
3623 .flags
= HCD_MEMORY
| HCD_USB2
,
3624 .start
= octeon_usb_start
,
3625 .stop
= octeon_usb_stop
,
3626 .urb_enqueue
= octeon_usb_urb_enqueue
,
3627 .urb_dequeue
= octeon_usb_urb_dequeue
,
3628 .endpoint_disable
= octeon_usb_endpoint_disable
,
3629 .get_frame_number
= octeon_usb_get_frame_number
,
3630 .hub_status_data
= octeon_usb_hub_status_data
,
3631 .hub_control
= octeon_usb_hub_control
,
3632 .map_urb_for_dma
= octeon_map_urb_for_dma
,
3633 .unmap_urb_for_dma
= octeon_unmap_urb_for_dma
,
3636 static int octeon_usb_probe(struct platform_device
*pdev
)
3639 int initialize_flags
;
3641 struct resource
*res_mem
;
3642 struct device_node
*usbn_node
;
3643 int irq
= platform_get_irq(pdev
, 0);
3644 struct device
*dev
= &pdev
->dev
;
3645 struct octeon_hcd
*priv
;
3646 struct usb_hcd
*hcd
;
3647 unsigned long flags
;
3648 u32 clock_rate
= 48000000;
3649 bool is_crystal_clock
= false;
3650 const char *clock_type
;
3653 if (dev
->of_node
== NULL
) {
3654 dev_err(dev
, "Error: empty of_node\n");
3657 usbn_node
= dev
->of_node
->parent
;
3659 i
= of_property_read_u32(usbn_node
,
3660 "refclk-frequency", &clock_rate
);
3662 dev_err(dev
, "No USBN \"refclk-frequency\"\n");
3665 switch (clock_rate
) {
3667 initialize_flags
= CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ
;
3670 initialize_flags
= CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ
;
3673 initialize_flags
= CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ
;
3676 dev_err(dev
, "Illebal USBN \"refclk-frequency\" %u\n",
3682 i
= of_property_read_string(usbn_node
,
3683 "refclk-type", &clock_type
);
3685 if (!i
&& strcmp("crystal", clock_type
) == 0)
3686 is_crystal_clock
= true;
3688 if (is_crystal_clock
)
3689 initialize_flags
|= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI
;
3691 initialize_flags
|= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND
;
3693 res_mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
3694 if (res_mem
== NULL
) {
3695 dev_err(dev
, "found no memory resource\n");
3698 usb_num
= (res_mem
->start
>> 44) & 1;
3701 /* Defective device tree, but we know how to fix it. */
3702 irq_hw_number_t hwirq
= usb_num
? (1 << 6) + 17 : 56;
3704 irq
= irq_create_mapping(NULL
, hwirq
);
3708 * Set the DMA mask to 64bits so we get buffers already translated for
3711 dev
->coherent_dma_mask
= ~0;
3712 dev
->dma_mask
= &dev
->coherent_dma_mask
;
3715 * Only cn52XX and cn56XX have DWC_OTG USB hardware and the
3716 * IOB priority registers. Under heavy network load USB
3717 * hardware can be starved by the IOB causing a crash. Give
3718 * it a priority boost if it has been waiting more than 400
3719 * cycles to avoid this situation.
3721 * Testing indicates that a cnt_val of 8192 is not sufficient,
3722 * but no failures are seen with 4096. We choose a value of
3723 * 400 to give a safety factor of 10.
3725 if (OCTEON_IS_MODEL(OCTEON_CN52XX
) || OCTEON_IS_MODEL(OCTEON_CN56XX
)) {
3726 union cvmx_iob_n2c_l2c_pri_cnt pri_cnt
;
3729 pri_cnt
.s
.cnt_enb
= 1;
3730 pri_cnt
.s
.cnt_val
= 400;
3731 cvmx_write_csr(CVMX_IOB_N2C_L2C_PRI_CNT
, pri_cnt
.u64
);
3734 hcd
= usb_create_hcd(&octeon_hc_driver
, dev
, dev_name(dev
));
3736 dev_dbg(dev
, "Failed to allocate memory for HCD\n");
3739 hcd
->uses_new_polling
= 1;
3740 priv
= (struct octeon_hcd
*)hcd
->hcd_priv
;
3742 spin_lock_init(&priv
->lock
);
3744 status
= cvmx_usb_initialize(&priv
->usb
, usb_num
, initialize_flags
);
3746 dev_dbg(dev
, "USB initialization failed with %d\n", status
);
3751 /* This delay is needed for CN3010, but I don't know why... */
3754 spin_lock_irqsave(&priv
->lock
, flags
);
3755 cvmx_usb_poll(&priv
->usb
);
3756 spin_unlock_irqrestore(&priv
->lock
, flags
);
3758 status
= usb_add_hcd(hcd
, irq
, 0);
3760 dev_dbg(dev
, "USB add HCD failed with %d\n", status
);
3764 device_wakeup_enable(hcd
->self
.controller
);
3766 dev_info(dev
, "Registered HCD for port %d on irq %d\n", usb_num
, irq
);
3771 static int octeon_usb_remove(struct platform_device
*pdev
)
3774 struct device
*dev
= &pdev
->dev
;
3775 struct usb_hcd
*hcd
= dev_get_drvdata(dev
);
3776 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3777 unsigned long flags
;
3779 usb_remove_hcd(hcd
);
3780 spin_lock_irqsave(&priv
->lock
, flags
);
3781 status
= cvmx_usb_shutdown(&priv
->usb
);
3782 spin_unlock_irqrestore(&priv
->lock
, flags
);
3784 dev_dbg(dev
, "USB shutdown failed with %d\n", status
);
3791 static const struct of_device_id octeon_usb_match
[] = {
3793 .compatible
= "cavium,octeon-5750-usbc",
3798 static struct platform_driver octeon_usb_driver
= {
3800 .name
= "OcteonUSB",
3801 .of_match_table
= octeon_usb_match
,
3803 .probe
= octeon_usb_probe
,
3804 .remove
= octeon_usb_remove
,
3807 static int __init
octeon_usb_driver_init(void)
3812 return platform_driver_register(&octeon_usb_driver
);
3814 module_init(octeon_usb_driver_init
);
3816 static void __exit
octeon_usb_driver_exit(void)
3821 platform_driver_unregister(&octeon_usb_driver
);
3823 module_exit(octeon_usb_driver_exit
);
3825 MODULE_LICENSE("GPL");
3826 MODULE_AUTHOR("Cavium, Inc. <support@cavium.com>");
3827 MODULE_DESCRIPTION("Cavium Inc. OCTEON USB Host driver.");