staging: octeon-usb: don't retry on data toggle error
[deliverable/linux.git] / drivers / staging / octeon-usb / octeon-hcd.c
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Cavium Networks
7 *
8 * Some parts of the code were originally released under BSD license:
9 *
10 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
11 * reserved.
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions are
15 * met:
16 *
17 * * Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 *
20 * * Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials provided
23 * with the distribution.
24 *
25 * * Neither the name of Cavium Networks nor the names of
26 * its contributors may be used to endorse or promote products
27 * derived from this software without specific prior written
28 * permission.
29 *
30 * This Software, including technical data, may be subject to U.S. export
31 * control laws, including the U.S. Export Administration Act and its associated
32 * regulations, and may be subject to export or import regulations in other
33 * countries.
34 *
35 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
36 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
37 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
38 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION
39 * OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
40 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
41 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
42 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
43 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
44 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
45 */
46 #include <linux/kernel.h>
47 #include <linux/module.h>
48 #include <linux/init.h>
49 #include <linux/pci.h>
50 #include <linux/prefetch.h>
51 #include <linux/interrupt.h>
52 #include <linux/platform_device.h>
53 #include <linux/usb.h>
54
55 #include <linux/time.h>
56 #include <linux/delay.h>
57
58 #include <asm/octeon/cvmx.h>
59 #include <asm/octeon/cvmx-iob-defs.h>
60
61 #include <linux/usb/hcd.h>
62
63 #include <linux/err.h>
64
65 #include <asm/octeon/octeon.h>
66 #include <asm/octeon/cvmx-helper.h>
67 #include <asm/octeon/cvmx-sysinfo.h>
68 #include <asm/octeon/cvmx-helper-board.h>
69
70 #include "octeon-hcd.h"
71
72 /**
73 * enum cvmx_usb_speed - the possible USB device speeds
74 *
75 * @CVMX_USB_SPEED_HIGH: Device is operation at 480Mbps
76 * @CVMX_USB_SPEED_FULL: Device is operation at 12Mbps
77 * @CVMX_USB_SPEED_LOW: Device is operation at 1.5Mbps
78 */
79 enum cvmx_usb_speed {
80 CVMX_USB_SPEED_HIGH = 0,
81 CVMX_USB_SPEED_FULL = 1,
82 CVMX_USB_SPEED_LOW = 2,
83 };
84
85 /**
86 * enum cvmx_usb_transfer - the possible USB transfer types
87 *
88 * @CVMX_USB_TRANSFER_CONTROL: USB transfer type control for hub and status
89 * transfers
90 * @CVMX_USB_TRANSFER_ISOCHRONOUS: USB transfer type isochronous for low
91 * priority periodic transfers
92 * @CVMX_USB_TRANSFER_BULK: USB transfer type bulk for large low priority
93 * transfers
94 * @CVMX_USB_TRANSFER_INTERRUPT: USB transfer type interrupt for high priority
95 * periodic transfers
96 */
97 enum cvmx_usb_transfer {
98 CVMX_USB_TRANSFER_CONTROL = 0,
99 CVMX_USB_TRANSFER_ISOCHRONOUS = 1,
100 CVMX_USB_TRANSFER_BULK = 2,
101 CVMX_USB_TRANSFER_INTERRUPT = 3,
102 };
103
104 /**
105 * enum cvmx_usb_direction - the transfer directions
106 *
107 * @CVMX_USB_DIRECTION_OUT: Data is transferring from Octeon to the device/host
108 * @CVMX_USB_DIRECTION_IN: Data is transferring from the device/host to Octeon
109 */
110 enum cvmx_usb_direction {
111 CVMX_USB_DIRECTION_OUT,
112 CVMX_USB_DIRECTION_IN,
113 };
114
115 /**
116 * enum cvmx_usb_complete - possible callback function status codes
117 *
118 * @CVMX_USB_COMPLETE_SUCCESS: The transaction / operation finished without
119 * any errors
120 * @CVMX_USB_COMPLETE_SHORT: FIXME: This is currently not implemented
121 * @CVMX_USB_COMPLETE_CANCEL: The transaction was canceled while in flight
122 * by a user call to cvmx_usb_cancel
123 * @CVMX_USB_COMPLETE_ERROR: The transaction aborted with an unexpected
124 * error status
125 * @CVMX_USB_COMPLETE_STALL: The transaction received a USB STALL response
126 * from the device
127 * @CVMX_USB_COMPLETE_XACTERR: The transaction failed with an error from the
128 * device even after a number of retries
129 * @CVMX_USB_COMPLETE_DATATGLERR: The transaction failed with a data toggle
130 * error even after a number of retries
131 * @CVMX_USB_COMPLETE_BABBLEERR: The transaction failed with a babble error
132 * @CVMX_USB_COMPLETE_FRAMEERR: The transaction failed with a frame error
133 * even after a number of retries
134 */
135 enum cvmx_usb_complete {
136 CVMX_USB_COMPLETE_SUCCESS,
137 CVMX_USB_COMPLETE_SHORT,
138 CVMX_USB_COMPLETE_CANCEL,
139 CVMX_USB_COMPLETE_ERROR,
140 CVMX_USB_COMPLETE_STALL,
141 CVMX_USB_COMPLETE_XACTERR,
142 CVMX_USB_COMPLETE_DATATGLERR,
143 CVMX_USB_COMPLETE_BABBLEERR,
144 CVMX_USB_COMPLETE_FRAMEERR,
145 };
146
147 /**
148 * struct cvmx_usb_port_status - the USB port status information
149 *
150 * @port_enabled: 1 = Usb port is enabled, 0 = disabled
151 * @port_over_current: 1 = Over current detected, 0 = Over current not
152 * detected. Octeon doesn't support over current detection.
153 * @port_powered: 1 = Port power is being supplied to the device, 0 =
154 * power is off. Octeon doesn't support turning port power
155 * off.
156 * @port_speed: Current port speed.
157 * @connected: 1 = A device is connected to the port, 0 = No device is
158 * connected.
159 * @connect_change: 1 = Device connected state changed since the last set
160 * status call.
161 */
162 struct cvmx_usb_port_status {
163 uint32_t reserved : 25;
164 uint32_t port_enabled : 1;
165 uint32_t port_over_current : 1;
166 uint32_t port_powered : 1;
167 enum cvmx_usb_speed port_speed : 2;
168 uint32_t connected : 1;
169 uint32_t connect_change : 1;
170 };
171
172 /**
173 * union cvmx_usb_control_header - the structure of a Control packet header
174 *
175 * @s.request_type: Bit 7 tells the direction: 1=IN, 0=OUT
176 * @s.request The standard usb request to make
177 * @s.value Value parameter for the request in little endian format
178 * @s.index Index for the request in little endian format
179 * @s.length Length of the data associated with this request in
180 * little endian format
181 */
182 union cvmx_usb_control_header {
183 uint64_t u64;
184 struct {
185 uint64_t request_type : 8;
186 uint64_t request : 8;
187 uint64_t value : 16;
188 uint64_t index : 16;
189 uint64_t length : 16;
190 } s;
191 };
192
193 /**
194 * struct cvmx_usb_iso_packet - descriptor for Isochronous packets
195 *
196 * @offset: This is the offset in bytes into the main buffer where this data
197 * is stored.
198 * @length: This is the length in bytes of the data.
199 * @status: This is the status of this individual packet transfer.
200 */
201 struct cvmx_usb_iso_packet {
202 int offset;
203 int length;
204 enum cvmx_usb_complete status;
205 };
206
207 /**
208 * enum cvmx_usb_initialize_flags - flags used by the initialization function
209 *
210 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI: The USB port uses a 12MHz crystal
211 * as clock source at USB_XO and
212 * USB_XI.
213 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND: The USB port uses 12/24/48MHz 2.5V
214 * board clock source at USB_XO.
215 * USB_XI should be tied to GND.
216 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK: Mask for clock speed field
217 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ: Speed of reference clock or
218 * crystal
219 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ: Speed of reference clock
220 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ: Speed of reference clock
221 * @CVMX_USB_INITIALIZE_FLAGS_NO_DMA: Disable DMA and used polled IO for
222 * data transfer use for the USB
223 */
224 enum cvmx_usb_initialize_flags {
225 CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI = 1 << 0,
226 CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND = 1 << 1,
227 CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK = 3 << 3,
228 CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ = 1 << 3,
229 CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ = 2 << 3,
230 CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ = 3 << 3,
231 /* Bits 3-4 used to encode the clock frequency */
232 CVMX_USB_INITIALIZE_FLAGS_NO_DMA = 1 << 5,
233 };
234
235 /**
236 * enum cvmx_usb_pipe_flags - internal flags for a pipe.
237 *
238 * @__CVMX_USB_PIPE_FLAGS_SCHEDULED: Used internally to determine if a pipe is
239 * actively using hardware. Do not use.
240 * @__CVMX_USB_PIPE_FLAGS_NEED_PING: Used internally to determine if a high
241 * speed pipe is in the ping state. Do not
242 * use.
243 */
244 enum cvmx_usb_pipe_flags {
245 __CVMX_USB_PIPE_FLAGS_SCHEDULED = 1 << 17,
246 __CVMX_USB_PIPE_FLAGS_NEED_PING = 1 << 18,
247 };
248
249 /* Maximum number of times to retry failed transactions */
250 #define MAX_RETRIES 3
251
252 /* Maximum number of hardware channels supported by the USB block */
253 #define MAX_CHANNELS 8
254
255 /* The highest valid USB device address */
256 #define MAX_USB_ADDRESS 127
257
258 /* The highest valid USB endpoint number */
259 #define MAX_USB_ENDPOINT 15
260
261 /* The highest valid port number on a hub */
262 #define MAX_USB_HUB_PORT 15
263
264 /*
265 * The low level hardware can transfer a maximum of this number of bytes in each
266 * transfer. The field is 19 bits wide
267 */
268 #define MAX_TRANSFER_BYTES ((1<<19)-1)
269
270 /*
271 * The low level hardware can transfer a maximum of this number of packets in
272 * each transfer. The field is 10 bits wide
273 */
274 #define MAX_TRANSFER_PACKETS ((1<<10)-1)
275
276 /**
277 * Logical transactions may take numerous low level
278 * transactions, especially when splits are concerned. This
279 * enum represents all of the possible stages a transaction can
280 * be in. Note that split completes are always even. This is so
281 * the NAK handler can backup to the previous low level
282 * transaction with a simple clearing of bit 0.
283 */
284 enum cvmx_usb_stage {
285 CVMX_USB_STAGE_NON_CONTROL,
286 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE,
287 CVMX_USB_STAGE_SETUP,
288 CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE,
289 CVMX_USB_STAGE_DATA,
290 CVMX_USB_STAGE_DATA_SPLIT_COMPLETE,
291 CVMX_USB_STAGE_STATUS,
292 CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE,
293 };
294
295 /**
296 * struct cvmx_usb_transaction - describes each pending USB transaction
297 * regardless of type. These are linked together
298 * to form a list of pending requests for a pipe.
299 *
300 * @node: List node for transactions in the pipe.
301 * @type: Type of transaction, duplicated of the pipe.
302 * @flags: State flags for this transaction.
303 * @buffer: User's physical buffer address to read/write.
304 * @buffer_length: Size of the user's buffer in bytes.
305 * @control_header: For control transactions, physical address of the 8
306 * byte standard header.
307 * @iso_start_frame: For ISO transactions, the starting frame number.
308 * @iso_number_packets: For ISO transactions, the number of packets in the
309 * request.
310 * @iso_packets: For ISO transactions, the sub packets in the request.
311 * @actual_bytes: Actual bytes transfer for this transaction.
312 * @stage: For control transactions, the current stage.
313 * @urb: URB.
314 */
315 struct cvmx_usb_transaction {
316 struct list_head node;
317 enum cvmx_usb_transfer type;
318 uint64_t buffer;
319 int buffer_length;
320 uint64_t control_header;
321 int iso_start_frame;
322 int iso_number_packets;
323 struct cvmx_usb_iso_packet *iso_packets;
324 int xfersize;
325 int pktcnt;
326 int retries;
327 int actual_bytes;
328 enum cvmx_usb_stage stage;
329 struct urb *urb;
330 };
331
332 /**
333 * struct cvmx_usb_pipe - a pipe represents a virtual connection between Octeon
334 * and some USB device. It contains a list of pending
335 * request to the device.
336 *
337 * @node: List node for pipe list
338 * @next: Pipe after this one in the list
339 * @transactions: List of pending transactions
340 * @interval: For periodic pipes, the interval between packets in
341 * frames
342 * @next_tx_frame: The next frame this pipe is allowed to transmit on
343 * @flags: State flags for this pipe
344 * @device_speed: Speed of device connected to this pipe
345 * @transfer_type: Type of transaction supported by this pipe
346 * @transfer_dir: IN or OUT. Ignored for Control
347 * @multi_count: Max packet in a row for the device
348 * @max_packet: The device's maximum packet size in bytes
349 * @device_addr: USB device address at other end of pipe
350 * @endpoint_num: USB endpoint number at other end of pipe
351 * @hub_device_addr: Hub address this device is connected to
352 * @hub_port: Hub port this device is connected to
353 * @pid_toggle: This toggles between 0/1 on every packet send to track
354 * the data pid needed
355 * @channel: Hardware DMA channel for this pipe
356 * @split_sc_frame: The low order bits of the frame number the split
357 * complete should be sent on
358 */
359 struct cvmx_usb_pipe {
360 struct list_head node;
361 struct list_head transactions;
362 uint64_t interval;
363 uint64_t next_tx_frame;
364 enum cvmx_usb_pipe_flags flags;
365 enum cvmx_usb_speed device_speed;
366 enum cvmx_usb_transfer transfer_type;
367 enum cvmx_usb_direction transfer_dir;
368 int multi_count;
369 uint16_t max_packet;
370 uint8_t device_addr;
371 uint8_t endpoint_num;
372 uint8_t hub_device_addr;
373 uint8_t hub_port;
374 uint8_t pid_toggle;
375 uint8_t channel;
376 int8_t split_sc_frame;
377 };
378
379 struct cvmx_usb_tx_fifo {
380 struct {
381 int channel;
382 int size;
383 uint64_t address;
384 } entry[MAX_CHANNELS+1];
385 int head;
386 int tail;
387 };
388
389 /**
390 * struct cvmx_usb_state - the state of the USB block
391 *
392 * init_flags: Flags passed to initialize.
393 * index: Which USB block this is for.
394 * idle_hardware_channels: Bit set for every idle hardware channel.
395 * usbcx_hprt: Stored port status so we don't need to read a CSR to
396 * determine splits.
397 * pipe_for_channel: Map channels to pipes.
398 * pipe: Storage for pipes.
399 * indent: Used by debug output to indent functions.
400 * port_status: Last port status used for change notification.
401 * idle_pipes: List of open pipes that have no transactions.
402 * active_pipes: Active pipes indexed by transfer type.
403 * frame_number: Increments every SOF interrupt for time keeping.
404 * active_split: Points to the current active split, or NULL.
405 */
406 struct cvmx_usb_state {
407 int init_flags;
408 int index;
409 int idle_hardware_channels;
410 union cvmx_usbcx_hprt usbcx_hprt;
411 struct cvmx_usb_pipe *pipe_for_channel[MAX_CHANNELS];
412 int indent;
413 struct cvmx_usb_port_status port_status;
414 struct list_head idle_pipes;
415 struct list_head active_pipes[4];
416 uint64_t frame_number;
417 struct cvmx_usb_transaction *active_split;
418 struct cvmx_usb_tx_fifo periodic;
419 struct cvmx_usb_tx_fifo nonperiodic;
420 };
421
422 struct octeon_hcd {
423 spinlock_t lock;
424 struct cvmx_usb_state usb;
425 };
426
427 /* This macro spins on a field waiting for it to reach a value */
428 #define CVMX_WAIT_FOR_FIELD32(address, type, field, op, value, timeout_usec)\
429 ({int result; \
430 do { \
431 uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec * \
432 octeon_get_clock_rate() / 1000000; \
433 type c; \
434 while (1) { \
435 c.u32 = __cvmx_usb_read_csr32(usb, address); \
436 if (c.s.field op (value)) { \
437 result = 0; \
438 break; \
439 } else if (cvmx_get_cycle() > done) { \
440 result = -1; \
441 break; \
442 } else \
443 cvmx_wait(100); \
444 } \
445 } while (0); \
446 result; })
447
448 /*
449 * This macro logically sets a single field in a CSR. It does the sequence
450 * read, modify, and write
451 */
452 #define USB_SET_FIELD32(address, type, field, value) \
453 do { \
454 type c; \
455 c.u32 = __cvmx_usb_read_csr32(usb, address); \
456 c.s.field = value; \
457 __cvmx_usb_write_csr32(usb, address, c.u32); \
458 } while (0)
459
460 /* Returns the IO address to push/pop stuff data from the FIFOs */
461 #define USB_FIFO_ADDRESS(channel, usb_index) \
462 (CVMX_USBCX_GOTGCTL(usb_index) + ((channel)+1)*0x1000)
463
464 /**
465 * struct octeon_temp_buffer - a bounce buffer for USB transfers
466 * @temp_buffer: the newly allocated temporary buffer (including meta-data)
467 * @orig_buffer: the original buffer passed by the USB stack
468 * @data: the newly allocated temporary buffer (excluding meta-data)
469 *
470 * Both the DMA engine and FIFO mode will always transfer full 32-bit words. If
471 * the buffer is too short, we need to allocate a temporary one, and this struct
472 * represents it.
473 */
474 struct octeon_temp_buffer {
475 void *temp_buffer;
476 void *orig_buffer;
477 u8 data[0];
478 };
479
480 /**
481 * octeon_alloc_temp_buffer - allocate a temporary buffer for USB transfer
482 * (if needed)
483 * @urb: URB.
484 * @mem_flags: Memory allocation flags.
485 *
486 * This function allocates a temporary bounce buffer whenever it's needed
487 * due to HW limitations.
488 */
489 static int octeon_alloc_temp_buffer(struct urb *urb, gfp_t mem_flags)
490 {
491 struct octeon_temp_buffer *temp;
492
493 if (urb->num_sgs || urb->sg ||
494 (urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) ||
495 !(urb->transfer_buffer_length % sizeof(u32)))
496 return 0;
497
498 temp = kmalloc(ALIGN(urb->transfer_buffer_length, sizeof(u32)) +
499 sizeof(*temp), mem_flags);
500 if (!temp)
501 return -ENOMEM;
502
503 temp->temp_buffer = temp;
504 temp->orig_buffer = urb->transfer_buffer;
505 if (usb_urb_dir_out(urb))
506 memcpy(temp->data, urb->transfer_buffer,
507 urb->transfer_buffer_length);
508 urb->transfer_buffer = temp->data;
509 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
510
511 return 0;
512 }
513
514 /**
515 * octeon_free_temp_buffer - free a temporary buffer used by USB transfers.
516 * @urb: URB.
517 *
518 * Frees a buffer allocated by octeon_alloc_temp_buffer().
519 */
520 static void octeon_free_temp_buffer(struct urb *urb)
521 {
522 struct octeon_temp_buffer *temp;
523
524 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
525 return;
526
527 temp = container_of(urb->transfer_buffer, struct octeon_temp_buffer,
528 data);
529 if (usb_urb_dir_in(urb))
530 memcpy(temp->orig_buffer, urb->transfer_buffer,
531 urb->actual_length);
532 urb->transfer_buffer = temp->orig_buffer;
533 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
534 kfree(temp->temp_buffer);
535 }
536
537 /**
538 * octeon_map_urb_for_dma - Octeon-specific map_urb_for_dma().
539 * @hcd: USB HCD structure.
540 * @urb: URB.
541 * @mem_flags: Memory allocation flags.
542 */
543 static int octeon_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
544 gfp_t mem_flags)
545 {
546 int ret;
547
548 ret = octeon_alloc_temp_buffer(urb, mem_flags);
549 if (ret)
550 return ret;
551
552 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
553 if (ret)
554 octeon_free_temp_buffer(urb);
555
556 return ret;
557 }
558
559 /**
560 * octeon_unmap_urb_for_dma - Octeon-specific unmap_urb_for_dma()
561 * @hcd: USB HCD structure.
562 * @urb: URB.
563 */
564 static void octeon_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
565 {
566 usb_hcd_unmap_urb_for_dma(hcd, urb);
567 octeon_free_temp_buffer(urb);
568 }
569
570 /**
571 * Read a USB 32bit CSR. It performs the necessary address swizzle
572 * for 32bit CSRs and logs the value in a readable format if
573 * debugging is on.
574 *
575 * @usb: USB block this access is for
576 * @address: 64bit address to read
577 *
578 * Returns: Result of the read
579 */
580 static inline uint32_t __cvmx_usb_read_csr32(struct cvmx_usb_state *usb,
581 uint64_t address)
582 {
583 uint32_t result = cvmx_read64_uint32(address ^ 4);
584 return result;
585 }
586
587
588 /**
589 * Write a USB 32bit CSR. It performs the necessary address
590 * swizzle for 32bit CSRs and logs the value in a readable format
591 * if debugging is on.
592 *
593 * @usb: USB block this access is for
594 * @address: 64bit address to write
595 * @value: Value to write
596 */
597 static inline void __cvmx_usb_write_csr32(struct cvmx_usb_state *usb,
598 uint64_t address, uint32_t value)
599 {
600 cvmx_write64_uint32(address ^ 4, value);
601 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
602 }
603
604
605 /**
606 * Read a USB 64bit CSR. It logs the value in a readable format if
607 * debugging is on.
608 *
609 * @usb: USB block this access is for
610 * @address: 64bit address to read
611 *
612 * Returns: Result of the read
613 */
614 static inline uint64_t __cvmx_usb_read_csr64(struct cvmx_usb_state *usb,
615 uint64_t address)
616 {
617 uint64_t result = cvmx_read64_uint64(address);
618 return result;
619 }
620
621
622 /**
623 * Write a USB 64bit CSR. It logs the value in a readable format
624 * if debugging is on.
625 *
626 * @usb: USB block this access is for
627 * @address: 64bit address to write
628 * @value: Value to write
629 */
630 static inline void __cvmx_usb_write_csr64(struct cvmx_usb_state *usb,
631 uint64_t address, uint64_t value)
632 {
633 cvmx_write64_uint64(address, value);
634 }
635
636 /**
637 * Return non zero if this pipe connects to a non HIGH speed
638 * device through a high speed hub.
639 *
640 * @usb: USB block this access is for
641 * @pipe: Pipe to check
642 *
643 * Returns: Non zero if we need to do split transactions
644 */
645 static inline int __cvmx_usb_pipe_needs_split(struct cvmx_usb_state *usb,
646 struct cvmx_usb_pipe *pipe)
647 {
648 return pipe->device_speed != CVMX_USB_SPEED_HIGH &&
649 usb->usbcx_hprt.s.prtspd == CVMX_USB_SPEED_HIGH;
650 }
651
652
653 /**
654 * Trivial utility function to return the correct PID for a pipe
655 *
656 * @pipe: pipe to check
657 *
658 * Returns: PID for pipe
659 */
660 static inline int __cvmx_usb_get_data_pid(struct cvmx_usb_pipe *pipe)
661 {
662 if (pipe->pid_toggle)
663 return 2; /* Data1 */
664 else
665 return 0; /* Data0 */
666 }
667
668 /**
669 * Initialize a USB port for use. This must be called before any
670 * other access to the Octeon USB port is made. The port starts
671 * off in the disabled state.
672 *
673 * @usb: Pointer to an empty struct cvmx_usb_state
674 * that will be populated by the initialize call.
675 * This structure is then passed to all other USB
676 * functions.
677 * @usb_port_number:
678 * Which Octeon USB port to initialize.
679 *
680 * Returns: 0 or a negative error code.
681 */
682 static int cvmx_usb_initialize(struct cvmx_usb_state *usb,
683 int usb_port_number,
684 enum cvmx_usb_initialize_flags flags)
685 {
686 union cvmx_usbnx_clk_ctl usbn_clk_ctl;
687 union cvmx_usbnx_usbp_ctl_status usbn_usbp_ctl_status;
688 int i;
689
690 /* At first allow 0-1 for the usb port number */
691 if ((usb_port_number < 0) || (usb_port_number > 1))
692 return -EINVAL;
693
694 memset(usb, 0, sizeof(*usb));
695 usb->init_flags = flags;
696
697 /* Initialize the USB state structure */
698 usb->index = usb_port_number;
699 INIT_LIST_HEAD(&usb->idle_pipes);
700 for (i = 0; i < ARRAY_SIZE(usb->active_pipes); i++)
701 INIT_LIST_HEAD(&usb->active_pipes[i]);
702
703 /*
704 * Power On Reset and PHY Initialization
705 *
706 * 1. Wait for DCOK to assert (nothing to do)
707 *
708 * 2a. Write USBN0/1_CLK_CTL[POR] = 1 and
709 * USBN0/1_CLK_CTL[HRST,PRST,HCLK_RST] = 0
710 */
711 usbn_clk_ctl.u64 =
712 __cvmx_usb_read_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index));
713 usbn_clk_ctl.s.por = 1;
714 usbn_clk_ctl.s.hrst = 0;
715 usbn_clk_ctl.s.prst = 0;
716 usbn_clk_ctl.s.hclk_rst = 0;
717 usbn_clk_ctl.s.enable = 0;
718 /*
719 * 2b. Select the USB reference clock/crystal parameters by writing
720 * appropriate values to USBN0/1_CLK_CTL[P_C_SEL, P_RTYPE, P_COM_ON]
721 */
722 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND) {
723 /*
724 * The USB port uses 12/24/48MHz 2.5V board clock
725 * source at USB_XO. USB_XI should be tied to GND.
726 * Most Octeon evaluation boards require this setting
727 */
728 if (OCTEON_IS_MODEL(OCTEON_CN3XXX) ||
729 OCTEON_IS_MODEL(OCTEON_CN56XX) ||
730 OCTEON_IS_MODEL(OCTEON_CN50XX))
731 /* From CN56XX,CN50XX,CN31XX,CN30XX manuals */
732 usbn_clk_ctl.s.p_rtype = 2; /* p_rclk=1 & p_xenbn=0 */
733 else
734 /* From CN52XX manual */
735 usbn_clk_ctl.s.p_rtype = 1;
736
737 switch (flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK) {
738 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ:
739 usbn_clk_ctl.s.p_c_sel = 0;
740 break;
741 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ:
742 usbn_clk_ctl.s.p_c_sel = 1;
743 break;
744 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ:
745 usbn_clk_ctl.s.p_c_sel = 2;
746 break;
747 }
748 } else {
749 /*
750 * The USB port uses a 12MHz crystal as clock source
751 * at USB_XO and USB_XI
752 */
753 if (OCTEON_IS_MODEL(OCTEON_CN3XXX))
754 /* From CN31XX,CN30XX manual */
755 usbn_clk_ctl.s.p_rtype = 3; /* p_rclk=1 & p_xenbn=1 */
756 else
757 /* From CN56XX,CN52XX,CN50XX manuals. */
758 usbn_clk_ctl.s.p_rtype = 0;
759
760 usbn_clk_ctl.s.p_c_sel = 0;
761 }
762 /*
763 * 2c. Select the HCLK via writing USBN0/1_CLK_CTL[DIVIDE, DIVIDE2] and
764 * setting USBN0/1_CLK_CTL[ENABLE] = 1. Divide the core clock down
765 * such that USB is as close as possible to 125Mhz
766 */
767 {
768 int divisor = (octeon_get_clock_rate()+125000000-1)/125000000;
769 /* Lower than 4 doesn't seem to work properly */
770 if (divisor < 4)
771 divisor = 4;
772 usbn_clk_ctl.s.divide = divisor;
773 usbn_clk_ctl.s.divide2 = 0;
774 }
775 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
776 usbn_clk_ctl.u64);
777 /* 2d. Write USBN0/1_CLK_CTL[HCLK_RST] = 1 */
778 usbn_clk_ctl.s.hclk_rst = 1;
779 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
780 usbn_clk_ctl.u64);
781 /* 2e. Wait 64 core-clock cycles for HCLK to stabilize */
782 cvmx_wait(64);
783 /*
784 * 3. Program the power-on reset field in the USBN clock-control
785 * register:
786 * USBN_CLK_CTL[POR] = 0
787 */
788 usbn_clk_ctl.s.por = 0;
789 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
790 usbn_clk_ctl.u64);
791 /* 4. Wait 1 ms for PHY clock to start */
792 mdelay(1);
793 /*
794 * 5. Program the Reset input from automatic test equipment field in the
795 * USBP control and status register:
796 * USBN_USBP_CTL_STATUS[ATE_RESET] = 1
797 */
798 usbn_usbp_ctl_status.u64 = __cvmx_usb_read_csr64(usb,
799 CVMX_USBNX_USBP_CTL_STATUS(usb->index));
800 usbn_usbp_ctl_status.s.ate_reset = 1;
801 __cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
802 usbn_usbp_ctl_status.u64);
803 /* 6. Wait 10 cycles */
804 cvmx_wait(10);
805 /*
806 * 7. Clear ATE_RESET field in the USBN clock-control register:
807 * USBN_USBP_CTL_STATUS[ATE_RESET] = 0
808 */
809 usbn_usbp_ctl_status.s.ate_reset = 0;
810 __cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
811 usbn_usbp_ctl_status.u64);
812 /*
813 * 8. Program the PHY reset field in the USBN clock-control register:
814 * USBN_CLK_CTL[PRST] = 1
815 */
816 usbn_clk_ctl.s.prst = 1;
817 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
818 usbn_clk_ctl.u64);
819 /*
820 * 9. Program the USBP control and status register to select host or
821 * device mode. USBN_USBP_CTL_STATUS[HST_MODE] = 0 for host, = 1 for
822 * device
823 */
824 usbn_usbp_ctl_status.s.hst_mode = 0;
825 __cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
826 usbn_usbp_ctl_status.u64);
827 /* 10. Wait 1 us */
828 udelay(1);
829 /*
830 * 11. Program the hreset_n field in the USBN clock-control register:
831 * USBN_CLK_CTL[HRST] = 1
832 */
833 usbn_clk_ctl.s.hrst = 1;
834 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
835 usbn_clk_ctl.u64);
836 /* 12. Proceed to USB core initialization */
837 usbn_clk_ctl.s.enable = 1;
838 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
839 usbn_clk_ctl.u64);
840 udelay(1);
841
842 /*
843 * USB Core Initialization
844 *
845 * 1. Read USBC_GHWCFG1, USBC_GHWCFG2, USBC_GHWCFG3, USBC_GHWCFG4 to
846 * determine USB core configuration parameters.
847 *
848 * Nothing needed
849 *
850 * 2. Program the following fields in the global AHB configuration
851 * register (USBC_GAHBCFG)
852 * DMA mode, USBC_GAHBCFG[DMAEn]: 1 = DMA mode, 0 = slave mode
853 * Burst length, USBC_GAHBCFG[HBSTLEN] = 0
854 * Nonperiodic TxFIFO empty level (slave mode only),
855 * USBC_GAHBCFG[NPTXFEMPLVL]
856 * Periodic TxFIFO empty level (slave mode only),
857 * USBC_GAHBCFG[PTXFEMPLVL]
858 * Global interrupt mask, USBC_GAHBCFG[GLBLINTRMSK] = 1
859 */
860 {
861 union cvmx_usbcx_gahbcfg usbcx_gahbcfg;
862 /* Due to an errata, CN31XX doesn't support DMA */
863 if (OCTEON_IS_MODEL(OCTEON_CN31XX))
864 usb->init_flags |= CVMX_USB_INITIALIZE_FLAGS_NO_DMA;
865 usbcx_gahbcfg.u32 = 0;
866 usbcx_gahbcfg.s.dmaen = !(usb->init_flags &
867 CVMX_USB_INITIALIZE_FLAGS_NO_DMA);
868 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
869 /* Only use one channel with non DMA */
870 usb->idle_hardware_channels = 0x1;
871 else if (OCTEON_IS_MODEL(OCTEON_CN5XXX))
872 /* CN5XXX have an errata with channel 3 */
873 usb->idle_hardware_channels = 0xf7;
874 else
875 usb->idle_hardware_channels = 0xff;
876 usbcx_gahbcfg.s.hbstlen = 0;
877 usbcx_gahbcfg.s.nptxfemplvl = 1;
878 usbcx_gahbcfg.s.ptxfemplvl = 1;
879 usbcx_gahbcfg.s.glblintrmsk = 1;
880 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GAHBCFG(usb->index),
881 usbcx_gahbcfg.u32);
882 }
883 /*
884 * 3. Program the following fields in USBC_GUSBCFG register.
885 * HS/FS timeout calibration, USBC_GUSBCFG[TOUTCAL] = 0
886 * ULPI DDR select, USBC_GUSBCFG[DDRSEL] = 0
887 * USB turnaround time, USBC_GUSBCFG[USBTRDTIM] = 0x5
888 * PHY low-power clock select, USBC_GUSBCFG[PHYLPWRCLKSEL] = 0
889 */
890 {
891 union cvmx_usbcx_gusbcfg usbcx_gusbcfg;
892
893 usbcx_gusbcfg.u32 = __cvmx_usb_read_csr32(usb,
894 CVMX_USBCX_GUSBCFG(usb->index));
895 usbcx_gusbcfg.s.toutcal = 0;
896 usbcx_gusbcfg.s.ddrsel = 0;
897 usbcx_gusbcfg.s.usbtrdtim = 0x5;
898 usbcx_gusbcfg.s.phylpwrclksel = 0;
899 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GUSBCFG(usb->index),
900 usbcx_gusbcfg.u32);
901 }
902 /*
903 * 4. The software must unmask the following bits in the USBC_GINTMSK
904 * register.
905 * OTG interrupt mask, USBC_GINTMSK[OTGINTMSK] = 1
906 * Mode mismatch interrupt mask, USBC_GINTMSK[MODEMISMSK] = 1
907 */
908 {
909 union cvmx_usbcx_gintmsk usbcx_gintmsk;
910 int channel;
911
912 usbcx_gintmsk.u32 = __cvmx_usb_read_csr32(usb,
913 CVMX_USBCX_GINTMSK(usb->index));
914 usbcx_gintmsk.s.otgintmsk = 1;
915 usbcx_gintmsk.s.modemismsk = 1;
916 usbcx_gintmsk.s.hchintmsk = 1;
917 usbcx_gintmsk.s.sofmsk = 0;
918 /* We need RX FIFO interrupts if we don't have DMA */
919 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
920 usbcx_gintmsk.s.rxflvlmsk = 1;
921 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTMSK(usb->index),
922 usbcx_gintmsk.u32);
923
924 /*
925 * Disable all channel interrupts. We'll enable them per channel
926 * later.
927 */
928 for (channel = 0; channel < 8; channel++)
929 __cvmx_usb_write_csr32(usb,
930 CVMX_USBCX_HCINTMSKX(channel, usb->index), 0);
931 }
932
933 {
934 /*
935 * Host Port Initialization
936 *
937 * 1. Program the host-port interrupt-mask field to unmask,
938 * USBC_GINTMSK[PRTINT] = 1
939 */
940 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index),
941 union cvmx_usbcx_gintmsk, prtintmsk, 1);
942 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index),
943 union cvmx_usbcx_gintmsk, disconnintmsk, 1);
944 /*
945 * 2. Program the USBC_HCFG register to select full-speed host
946 * or high-speed host.
947 */
948 {
949 union cvmx_usbcx_hcfg usbcx_hcfg;
950
951 usbcx_hcfg.u32 = __cvmx_usb_read_csr32(usb,
952 CVMX_USBCX_HCFG(usb->index));
953 usbcx_hcfg.s.fslssupp = 0;
954 usbcx_hcfg.s.fslspclksel = 0;
955 __cvmx_usb_write_csr32(usb,
956 CVMX_USBCX_HCFG(usb->index),
957 usbcx_hcfg.u32);
958 }
959 /*
960 * 3. Program the port power bit to drive VBUS on the USB,
961 * USBC_HPRT[PRTPWR] = 1
962 */
963 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index),
964 union cvmx_usbcx_hprt, prtpwr, 1);
965
966 /*
967 * Steps 4-15 from the manual are done later in the port enable
968 */
969 }
970
971 return 0;
972 }
973
974
975 /**
976 * Shutdown a USB port after a call to cvmx_usb_initialize().
977 * The port should be disabled with all pipes closed when this
978 * function is called.
979 *
980 * @usb: USB device state populated by cvmx_usb_initialize().
981 *
982 * Returns: 0 or a negative error code.
983 */
984 static int cvmx_usb_shutdown(struct cvmx_usb_state *usb)
985 {
986 union cvmx_usbnx_clk_ctl usbn_clk_ctl;
987
988 /* Make sure all pipes are closed */
989 if (!list_empty(&usb->idle_pipes) ||
990 !list_empty(&usb->active_pipes[CVMX_USB_TRANSFER_ISOCHRONOUS]) ||
991 !list_empty(&usb->active_pipes[CVMX_USB_TRANSFER_INTERRUPT]) ||
992 !list_empty(&usb->active_pipes[CVMX_USB_TRANSFER_CONTROL]) ||
993 !list_empty(&usb->active_pipes[CVMX_USB_TRANSFER_BULK]))
994 return -EBUSY;
995
996 /* Disable the clocks and put them in power on reset */
997 usbn_clk_ctl.u64 = __cvmx_usb_read_csr64(usb,
998 CVMX_USBNX_CLK_CTL(usb->index));
999 usbn_clk_ctl.s.enable = 1;
1000 usbn_clk_ctl.s.por = 1;
1001 usbn_clk_ctl.s.hclk_rst = 1;
1002 usbn_clk_ctl.s.prst = 0;
1003 usbn_clk_ctl.s.hrst = 0;
1004 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
1005 usbn_clk_ctl.u64);
1006 return 0;
1007 }
1008
1009
1010 /**
1011 * Enable a USB port. After this call succeeds, the USB port is
1012 * online and servicing requests.
1013 *
1014 * @usb: USB device state populated by cvmx_usb_initialize().
1015 *
1016 * Returns: 0 or a negative error code.
1017 */
1018 static int cvmx_usb_enable(struct cvmx_usb_state *usb)
1019 {
1020 union cvmx_usbcx_ghwcfg3 usbcx_ghwcfg3;
1021
1022 usb->usbcx_hprt.u32 = __cvmx_usb_read_csr32(usb,
1023 CVMX_USBCX_HPRT(usb->index));
1024
1025 /*
1026 * If the port is already enabled the just return. We don't need to do
1027 * anything
1028 */
1029 if (usb->usbcx_hprt.s.prtena)
1030 return 0;
1031
1032 /* If there is nothing plugged into the port then fail immediately */
1033 if (!usb->usbcx_hprt.s.prtconnsts)
1034 return -ETIMEDOUT;
1035
1036 /* Program the port reset bit to start the reset process */
1037 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt,
1038 prtrst, 1);
1039
1040 /*
1041 * Wait at least 50ms (high speed), or 10ms (full speed) for the reset
1042 * process to complete.
1043 */
1044 mdelay(50);
1045
1046 /* Program the port reset bit to 0, USBC_HPRT[PRTRST] = 0 */
1047 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt,
1048 prtrst, 0);
1049
1050 /* Wait for the USBC_HPRT[PRTENA]. */
1051 if (CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_HPRT(usb->index),
1052 union cvmx_usbcx_hprt, prtena, ==, 1, 100000))
1053 return -ETIMEDOUT;
1054
1055 /*
1056 * Read the port speed field to get the enumerated speed,
1057 * USBC_HPRT[PRTSPD].
1058 */
1059 usb->usbcx_hprt.u32 = __cvmx_usb_read_csr32(usb,
1060 CVMX_USBCX_HPRT(usb->index));
1061 usbcx_ghwcfg3.u32 = __cvmx_usb_read_csr32(usb,
1062 CVMX_USBCX_GHWCFG3(usb->index));
1063
1064 /*
1065 * 13. Program the USBC_GRXFSIZ register to select the size of the
1066 * receive FIFO (25%).
1067 */
1068 USB_SET_FIELD32(CVMX_USBCX_GRXFSIZ(usb->index),
1069 union cvmx_usbcx_grxfsiz, rxfdep,
1070 usbcx_ghwcfg3.s.dfifodepth / 4);
1071 /*
1072 * 14. Program the USBC_GNPTXFSIZ register to select the size and the
1073 * start address of the non- periodic transmit FIFO for nonperiodic
1074 * transactions (50%).
1075 */
1076 {
1077 union cvmx_usbcx_gnptxfsiz siz;
1078
1079 siz.u32 = __cvmx_usb_read_csr32(usb,
1080 CVMX_USBCX_GNPTXFSIZ(usb->index));
1081 siz.s.nptxfdep = usbcx_ghwcfg3.s.dfifodepth / 2;
1082 siz.s.nptxfstaddr = usbcx_ghwcfg3.s.dfifodepth / 4;
1083 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index),
1084 siz.u32);
1085 }
1086 /*
1087 * 15. Program the USBC_HPTXFSIZ register to select the size and start
1088 * address of the periodic transmit FIFO for periodic transactions
1089 * (25%).
1090 */
1091 {
1092 union cvmx_usbcx_hptxfsiz siz;
1093
1094 siz.u32 = __cvmx_usb_read_csr32(usb,
1095 CVMX_USBCX_HPTXFSIZ(usb->index));
1096 siz.s.ptxfsize = usbcx_ghwcfg3.s.dfifodepth / 4;
1097 siz.s.ptxfstaddr = 3 * usbcx_ghwcfg3.s.dfifodepth / 4;
1098 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HPTXFSIZ(usb->index),
1099 siz.u32);
1100 }
1101 /* Flush all FIFOs */
1102 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index),
1103 union cvmx_usbcx_grstctl, txfnum, 0x10);
1104 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index),
1105 union cvmx_usbcx_grstctl, txfflsh, 1);
1106 CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb->index),
1107 union cvmx_usbcx_grstctl,
1108 txfflsh, ==, 0, 100);
1109 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index),
1110 union cvmx_usbcx_grstctl, rxfflsh, 1);
1111 CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb->index),
1112 union cvmx_usbcx_grstctl,
1113 rxfflsh, ==, 0, 100);
1114
1115 return 0;
1116 }
1117
1118
1119 /**
1120 * Disable a USB port. After this call the USB port will not
1121 * generate data transfers and will not generate events.
1122 * Transactions in process will fail and call their
1123 * associated callbacks.
1124 *
1125 * @usb: USB device state populated by cvmx_usb_initialize().
1126 *
1127 * Returns: 0 or a negative error code.
1128 */
1129 static int cvmx_usb_disable(struct cvmx_usb_state *usb)
1130 {
1131 /* Disable the port */
1132 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt,
1133 prtena, 1);
1134 return 0;
1135 }
1136
1137
1138 /**
1139 * Get the current state of the USB port. Use this call to
1140 * determine if the usb port has anything connected, is enabled,
1141 * or has some sort of error condition. The return value of this
1142 * call has "changed" bits to signal of the value of some fields
1143 * have changed between calls.
1144 *
1145 * @usb: USB device state populated by cvmx_usb_initialize().
1146 *
1147 * Returns: Port status information
1148 */
1149 static struct cvmx_usb_port_status cvmx_usb_get_status(
1150 struct cvmx_usb_state *usb)
1151 {
1152 union cvmx_usbcx_hprt usbc_hprt;
1153 struct cvmx_usb_port_status result;
1154
1155 memset(&result, 0, sizeof(result));
1156
1157 usbc_hprt.u32 = __cvmx_usb_read_csr32(usb,
1158 CVMX_USBCX_HPRT(usb->index));
1159 result.port_enabled = usbc_hprt.s.prtena;
1160 result.port_over_current = usbc_hprt.s.prtovrcurract;
1161 result.port_powered = usbc_hprt.s.prtpwr;
1162 result.port_speed = usbc_hprt.s.prtspd;
1163 result.connected = usbc_hprt.s.prtconnsts;
1164 result.connect_change =
1165 (result.connected != usb->port_status.connected);
1166
1167 return result;
1168 }
1169
1170 /**
1171 * Open a virtual pipe between the host and a USB device. A pipe
1172 * must be opened before data can be transferred between a device
1173 * and Octeon.
1174 *
1175 * @usb: USB device state populated by cvmx_usb_initialize().
1176 * @device_addr:
1177 * USB device address to open the pipe to
1178 * (0-127).
1179 * @endpoint_num:
1180 * USB endpoint number to open the pipe to
1181 * (0-15).
1182 * @device_speed:
1183 * The speed of the device the pipe is going
1184 * to. This must match the device's speed,
1185 * which may be different than the port speed.
1186 * @max_packet: The maximum packet length the device can
1187 * transmit/receive (low speed=0-8, full
1188 * speed=0-1023, high speed=0-1024). This value
1189 * comes from the standard endpoint descriptor
1190 * field wMaxPacketSize bits <10:0>.
1191 * @transfer_type:
1192 * The type of transfer this pipe is for.
1193 * @transfer_dir:
1194 * The direction the pipe is in. This is not
1195 * used for control pipes.
1196 * @interval: For ISOCHRONOUS and INTERRUPT transfers,
1197 * this is how often the transfer is scheduled
1198 * for. All other transfers should specify
1199 * zero. The units are in frames (8000/sec at
1200 * high speed, 1000/sec for full speed).
1201 * @multi_count:
1202 * For high speed devices, this is the maximum
1203 * allowed number of packet per microframe.
1204 * Specify zero for non high speed devices. This
1205 * value comes from the standard endpoint descriptor
1206 * field wMaxPacketSize bits <12:11>.
1207 * @hub_device_addr:
1208 * Hub device address this device is connected
1209 * to. Devices connected directly to Octeon
1210 * use zero. This is only used when the device
1211 * is full/low speed behind a high speed hub.
1212 * The address will be of the high speed hub,
1213 * not and full speed hubs after it.
1214 * @hub_port: Which port on the hub the device is
1215 * connected. Use zero for devices connected
1216 * directly to Octeon. Like hub_device_addr,
1217 * this is only used for full/low speed
1218 * devices behind a high speed hub.
1219 *
1220 * Returns: A non-NULL value is a pipe. NULL means an error.
1221 */
1222 static struct cvmx_usb_pipe *cvmx_usb_open_pipe(struct cvmx_usb_state *usb,
1223 int device_addr,
1224 int endpoint_num,
1225 enum cvmx_usb_speed
1226 device_speed,
1227 int max_packet,
1228 enum cvmx_usb_transfer
1229 transfer_type,
1230 enum cvmx_usb_direction
1231 transfer_dir,
1232 int interval, int multi_count,
1233 int hub_device_addr,
1234 int hub_port)
1235 {
1236 struct cvmx_usb_pipe *pipe;
1237
1238 if (unlikely((device_addr < 0) || (device_addr > MAX_USB_ADDRESS)))
1239 return NULL;
1240 if (unlikely((endpoint_num < 0) || (endpoint_num > MAX_USB_ENDPOINT)))
1241 return NULL;
1242 if (unlikely(device_speed > CVMX_USB_SPEED_LOW))
1243 return NULL;
1244 if (unlikely((max_packet <= 0) || (max_packet > 1024)))
1245 return NULL;
1246 if (unlikely(transfer_type > CVMX_USB_TRANSFER_INTERRUPT))
1247 return NULL;
1248 if (unlikely((transfer_dir != CVMX_USB_DIRECTION_OUT) &&
1249 (transfer_dir != CVMX_USB_DIRECTION_IN)))
1250 return NULL;
1251 if (unlikely(interval < 0))
1252 return NULL;
1253 if (unlikely((transfer_type == CVMX_USB_TRANSFER_CONTROL) && interval))
1254 return NULL;
1255 if (unlikely(multi_count < 0))
1256 return NULL;
1257 if (unlikely((device_speed != CVMX_USB_SPEED_HIGH) &&
1258 (multi_count != 0)))
1259 return NULL;
1260 if (unlikely((hub_device_addr < 0) ||
1261 (hub_device_addr > MAX_USB_ADDRESS)))
1262 return NULL;
1263 if (unlikely((hub_port < 0) || (hub_port > MAX_USB_HUB_PORT)))
1264 return NULL;
1265
1266 pipe = kzalloc(sizeof(*pipe), GFP_ATOMIC);
1267 if (!pipe)
1268 return NULL;
1269 if ((device_speed == CVMX_USB_SPEED_HIGH) &&
1270 (transfer_dir == CVMX_USB_DIRECTION_OUT) &&
1271 (transfer_type == CVMX_USB_TRANSFER_BULK))
1272 pipe->flags |= __CVMX_USB_PIPE_FLAGS_NEED_PING;
1273 pipe->device_addr = device_addr;
1274 pipe->endpoint_num = endpoint_num;
1275 pipe->device_speed = device_speed;
1276 pipe->max_packet = max_packet;
1277 pipe->transfer_type = transfer_type;
1278 pipe->transfer_dir = transfer_dir;
1279 INIT_LIST_HEAD(&pipe->transactions);
1280
1281 /*
1282 * All pipes use interval to rate limit NAK processing. Force an
1283 * interval if one wasn't supplied
1284 */
1285 if (!interval)
1286 interval = 1;
1287 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1288 pipe->interval = interval*8;
1289 /* Force start splits to be schedule on uFrame 0 */
1290 pipe->next_tx_frame = ((usb->frame_number+7)&~7) +
1291 pipe->interval;
1292 } else {
1293 pipe->interval = interval;
1294 pipe->next_tx_frame = usb->frame_number + pipe->interval;
1295 }
1296 pipe->multi_count = multi_count;
1297 pipe->hub_device_addr = hub_device_addr;
1298 pipe->hub_port = hub_port;
1299 pipe->pid_toggle = 0;
1300 pipe->split_sc_frame = -1;
1301 list_add_tail(&pipe->node, &usb->idle_pipes);
1302
1303 /*
1304 * We don't need to tell the hardware about this pipe yet since
1305 * it doesn't have any submitted requests
1306 */
1307
1308 return pipe;
1309 }
1310
1311
1312 /**
1313 * Poll the RX FIFOs and remove data as needed. This function is only used
1314 * in non DMA mode. It is very important that this function be called quickly
1315 * enough to prevent FIFO overflow.
1316 *
1317 * @usb: USB device state populated by cvmx_usb_initialize().
1318 */
1319 static void __cvmx_usb_poll_rx_fifo(struct cvmx_usb_state *usb)
1320 {
1321 union cvmx_usbcx_grxstsph rx_status;
1322 int channel;
1323 int bytes;
1324 uint64_t address;
1325 uint32_t *ptr;
1326
1327 rx_status.u32 = __cvmx_usb_read_csr32(usb,
1328 CVMX_USBCX_GRXSTSPH(usb->index));
1329 /* Only read data if IN data is there */
1330 if (rx_status.s.pktsts != 2)
1331 return;
1332 /* Check if no data is available */
1333 if (!rx_status.s.bcnt)
1334 return;
1335
1336 channel = rx_status.s.chnum;
1337 bytes = rx_status.s.bcnt;
1338 if (!bytes)
1339 return;
1340
1341 /* Get where the DMA engine would have written this data */
1342 address = __cvmx_usb_read_csr64(usb,
1343 CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8);
1344
1345 ptr = cvmx_phys_to_ptr(address);
1346 __cvmx_usb_write_csr64(usb,
1347 CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8,
1348 address + bytes);
1349
1350 /* Loop writing the FIFO data for this packet into memory */
1351 while (bytes > 0) {
1352 *ptr++ = __cvmx_usb_read_csr32(usb, USB_FIFO_ADDRESS(channel, usb->index));
1353 bytes -= 4;
1354 }
1355 CVMX_SYNCW;
1356
1357 return;
1358 }
1359
1360
1361 /**
1362 * Fill the TX hardware fifo with data out of the software
1363 * fifos
1364 *
1365 * @usb: USB device state populated by cvmx_usb_initialize().
1366 * @fifo: Software fifo to use
1367 * @available: Amount of space in the hardware fifo
1368 *
1369 * Returns: Non zero if the hardware fifo was too small and needs
1370 * to be serviced again.
1371 */
1372 static int __cvmx_usb_fill_tx_hw(struct cvmx_usb_state *usb,
1373 struct cvmx_usb_tx_fifo *fifo, int available)
1374 {
1375 /*
1376 * We're done either when there isn't anymore space or the software FIFO
1377 * is empty
1378 */
1379 while (available && (fifo->head != fifo->tail)) {
1380 int i = fifo->tail;
1381 const uint32_t *ptr = cvmx_phys_to_ptr(fifo->entry[i].address);
1382 uint64_t csr_address = USB_FIFO_ADDRESS(fifo->entry[i].channel,
1383 usb->index) ^ 4;
1384 int words = available;
1385
1386 /* Limit the amount of data to waht the SW fifo has */
1387 if (fifo->entry[i].size <= available) {
1388 words = fifo->entry[i].size;
1389 fifo->tail++;
1390 if (fifo->tail > MAX_CHANNELS)
1391 fifo->tail = 0;
1392 }
1393
1394 /* Update the next locations and counts */
1395 available -= words;
1396 fifo->entry[i].address += words * 4;
1397 fifo->entry[i].size -= words;
1398
1399 /*
1400 * Write the HW fifo data. The read every three writes is due
1401 * to an errata on CN3XXX chips
1402 */
1403 while (words > 3) {
1404 cvmx_write64_uint32(csr_address, *ptr++);
1405 cvmx_write64_uint32(csr_address, *ptr++);
1406 cvmx_write64_uint32(csr_address, *ptr++);
1407 cvmx_read64_uint64(
1408 CVMX_USBNX_DMA0_INB_CHN0(usb->index));
1409 words -= 3;
1410 }
1411 cvmx_write64_uint32(csr_address, *ptr++);
1412 if (--words) {
1413 cvmx_write64_uint32(csr_address, *ptr++);
1414 if (--words)
1415 cvmx_write64_uint32(csr_address, *ptr++);
1416 }
1417 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
1418 }
1419 return fifo->head != fifo->tail;
1420 }
1421
1422
1423 /**
1424 * Check the hardware FIFOs and fill them as needed
1425 *
1426 * @usb: USB device state populated by cvmx_usb_initialize().
1427 */
1428 static void __cvmx_usb_poll_tx_fifo(struct cvmx_usb_state *usb)
1429 {
1430 if (usb->periodic.head != usb->periodic.tail) {
1431 union cvmx_usbcx_hptxsts tx_status;
1432
1433 tx_status.u32 = __cvmx_usb_read_csr32(usb,
1434 CVMX_USBCX_HPTXSTS(usb->index));
1435 if (__cvmx_usb_fill_tx_hw(usb, &usb->periodic,
1436 tx_status.s.ptxfspcavail))
1437 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index),
1438 union cvmx_usbcx_gintmsk,
1439 ptxfempmsk, 1);
1440 else
1441 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index),
1442 union cvmx_usbcx_gintmsk,
1443 ptxfempmsk, 0);
1444 }
1445
1446 if (usb->nonperiodic.head != usb->nonperiodic.tail) {
1447 union cvmx_usbcx_gnptxsts tx_status;
1448
1449 tx_status.u32 = __cvmx_usb_read_csr32(usb,
1450 CVMX_USBCX_GNPTXSTS(usb->index));
1451 if (__cvmx_usb_fill_tx_hw(usb, &usb->nonperiodic,
1452 tx_status.s.nptxfspcavail))
1453 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index),
1454 union cvmx_usbcx_gintmsk,
1455 nptxfempmsk, 1);
1456 else
1457 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index),
1458 union cvmx_usbcx_gintmsk,
1459 nptxfempmsk, 0);
1460 }
1461
1462 return;
1463 }
1464
1465
1466 /**
1467 * Fill the TX FIFO with an outgoing packet
1468 *
1469 * @usb: USB device state populated by cvmx_usb_initialize().
1470 * @channel: Channel number to get packet from
1471 */
1472 static void __cvmx_usb_fill_tx_fifo(struct cvmx_usb_state *usb, int channel)
1473 {
1474 union cvmx_usbcx_hccharx hcchar;
1475 union cvmx_usbcx_hcspltx usbc_hcsplt;
1476 union cvmx_usbcx_hctsizx usbc_hctsiz;
1477 struct cvmx_usb_tx_fifo *fifo;
1478
1479 /* We only need to fill data on outbound channels */
1480 hcchar.u32 = __cvmx_usb_read_csr32(usb,
1481 CVMX_USBCX_HCCHARX(channel, usb->index));
1482 if (hcchar.s.epdir != CVMX_USB_DIRECTION_OUT)
1483 return;
1484
1485 /* OUT Splits only have data on the start and not the complete */
1486 usbc_hcsplt.u32 = __cvmx_usb_read_csr32(usb,
1487 CVMX_USBCX_HCSPLTX(channel, usb->index));
1488 if (usbc_hcsplt.s.spltena && usbc_hcsplt.s.compsplt)
1489 return;
1490
1491 /*
1492 * Find out how many bytes we need to fill and convert it into 32bit
1493 * words.
1494 */
1495 usbc_hctsiz.u32 = __cvmx_usb_read_csr32(usb,
1496 CVMX_USBCX_HCTSIZX(channel, usb->index));
1497 if (!usbc_hctsiz.s.xfersize)
1498 return;
1499
1500 if ((hcchar.s.eptype == CVMX_USB_TRANSFER_INTERRUPT) ||
1501 (hcchar.s.eptype == CVMX_USB_TRANSFER_ISOCHRONOUS))
1502 fifo = &usb->periodic;
1503 else
1504 fifo = &usb->nonperiodic;
1505
1506 fifo->entry[fifo->head].channel = channel;
1507 fifo->entry[fifo->head].address = __cvmx_usb_read_csr64(usb, CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8);
1508 fifo->entry[fifo->head].size = (usbc_hctsiz.s.xfersize+3)>>2;
1509 fifo->head++;
1510 if (fifo->head > MAX_CHANNELS)
1511 fifo->head = 0;
1512
1513 __cvmx_usb_poll_tx_fifo(usb);
1514
1515 return;
1516 }
1517
1518 /**
1519 * Perform channel specific setup for Control transactions. All
1520 * the generic stuff will already have been done in
1521 * __cvmx_usb_start_channel()
1522 *
1523 * @usb: USB device state populated by cvmx_usb_initialize().
1524 * @channel: Channel to setup
1525 * @pipe: Pipe for control transaction
1526 */
1527 static void __cvmx_usb_start_channel_control(struct cvmx_usb_state *usb,
1528 int channel,
1529 struct cvmx_usb_pipe *pipe)
1530 {
1531 struct cvmx_usb_transaction *transaction =
1532 list_first_entry(&pipe->transactions, typeof(*transaction),
1533 node);
1534 union cvmx_usb_control_header *header =
1535 cvmx_phys_to_ptr(transaction->control_header);
1536 int bytes_to_transfer = transaction->buffer_length -
1537 transaction->actual_bytes;
1538 int packets_to_transfer;
1539 union cvmx_usbcx_hctsizx usbc_hctsiz;
1540
1541 usbc_hctsiz.u32 = __cvmx_usb_read_csr32(usb,
1542 CVMX_USBCX_HCTSIZX(channel, usb->index));
1543
1544 switch (transaction->stage) {
1545 case CVMX_USB_STAGE_NON_CONTROL:
1546 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE:
1547 cvmx_dprintf("%s: ERROR - Non control stage\n", __func__);
1548 break;
1549 case CVMX_USB_STAGE_SETUP:
1550 usbc_hctsiz.s.pid = 3; /* Setup */
1551 bytes_to_transfer = sizeof(*header);
1552 /* All Control operations start with a setup going OUT */
1553 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1554 union cvmx_usbcx_hccharx, epdir,
1555 CVMX_USB_DIRECTION_OUT);
1556 /*
1557 * Setup send the control header instead of the buffer data. The
1558 * buffer data will be used in the next stage
1559 */
1560 __cvmx_usb_write_csr64(usb,
1561 CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8,
1562 transaction->control_header);
1563 break;
1564 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE:
1565 usbc_hctsiz.s.pid = 3; /* Setup */
1566 bytes_to_transfer = 0;
1567 /* All Control operations start with a setup going OUT */
1568 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1569 union cvmx_usbcx_hccharx, epdir,
1570 CVMX_USB_DIRECTION_OUT);
1571
1572 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index),
1573 union cvmx_usbcx_hcspltx, compsplt, 1);
1574 break;
1575 case CVMX_USB_STAGE_DATA:
1576 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1577 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1578 if (header->s.request_type & 0x80)
1579 bytes_to_transfer = 0;
1580 else if (bytes_to_transfer > pipe->max_packet)
1581 bytes_to_transfer = pipe->max_packet;
1582 }
1583 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1584 union cvmx_usbcx_hccharx, epdir,
1585 ((header->s.request_type & 0x80) ?
1586 CVMX_USB_DIRECTION_IN :
1587 CVMX_USB_DIRECTION_OUT));
1588 break;
1589 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE:
1590 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1591 if (!(header->s.request_type & 0x80))
1592 bytes_to_transfer = 0;
1593 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1594 union cvmx_usbcx_hccharx, epdir,
1595 ((header->s.request_type & 0x80) ?
1596 CVMX_USB_DIRECTION_IN :
1597 CVMX_USB_DIRECTION_OUT));
1598 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index),
1599 union cvmx_usbcx_hcspltx, compsplt, 1);
1600 break;
1601 case CVMX_USB_STAGE_STATUS:
1602 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1603 bytes_to_transfer = 0;
1604 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1605 union cvmx_usbcx_hccharx, epdir,
1606 ((header->s.request_type & 0x80) ?
1607 CVMX_USB_DIRECTION_OUT :
1608 CVMX_USB_DIRECTION_IN));
1609 break;
1610 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE:
1611 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1612 bytes_to_transfer = 0;
1613 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1614 union cvmx_usbcx_hccharx, epdir,
1615 ((header->s.request_type & 0x80) ?
1616 CVMX_USB_DIRECTION_OUT :
1617 CVMX_USB_DIRECTION_IN));
1618 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index),
1619 union cvmx_usbcx_hcspltx, compsplt, 1);
1620 break;
1621 }
1622
1623 /*
1624 * Make sure the transfer never exceeds the byte limit of the hardware.
1625 * Further bytes will be sent as continued transactions
1626 */
1627 if (bytes_to_transfer > MAX_TRANSFER_BYTES) {
1628 /* Round MAX_TRANSFER_BYTES to a multiple of out packet size */
1629 bytes_to_transfer = MAX_TRANSFER_BYTES / pipe->max_packet;
1630 bytes_to_transfer *= pipe->max_packet;
1631 }
1632
1633 /*
1634 * Calculate the number of packets to transfer. If the length is zero
1635 * we still need to transfer one packet
1636 */
1637 packets_to_transfer = (bytes_to_transfer + pipe->max_packet - 1) /
1638 pipe->max_packet;
1639 if (packets_to_transfer == 0)
1640 packets_to_transfer = 1;
1641 else if ((packets_to_transfer > 1) &&
1642 (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)) {
1643 /*
1644 * Limit to one packet when not using DMA. Channels must be
1645 * restarted between every packet for IN transactions, so there
1646 * is no reason to do multiple packets in a row
1647 */
1648 packets_to_transfer = 1;
1649 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1650 } else if (packets_to_transfer > MAX_TRANSFER_PACKETS) {
1651 /*
1652 * Limit the number of packet and data transferred to what the
1653 * hardware can handle
1654 */
1655 packets_to_transfer = MAX_TRANSFER_PACKETS;
1656 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1657 }
1658
1659 usbc_hctsiz.s.xfersize = bytes_to_transfer;
1660 usbc_hctsiz.s.pktcnt = packets_to_transfer;
1661
1662 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index),
1663 usbc_hctsiz.u32);
1664 return;
1665 }
1666
1667
1668 /**
1669 * Start a channel to perform the pipe's head transaction
1670 *
1671 * @usb: USB device state populated by cvmx_usb_initialize().
1672 * @channel: Channel to setup
1673 * @pipe: Pipe to start
1674 */
1675 static void __cvmx_usb_start_channel(struct cvmx_usb_state *usb,
1676 int channel,
1677 struct cvmx_usb_pipe *pipe)
1678 {
1679 struct cvmx_usb_transaction *transaction =
1680 list_first_entry(&pipe->transactions, typeof(*transaction),
1681 node);
1682
1683 /* Make sure all writes to the DMA region get flushed */
1684 CVMX_SYNCW;
1685
1686 /* Attach the channel to the pipe */
1687 usb->pipe_for_channel[channel] = pipe;
1688 pipe->channel = channel;
1689 pipe->flags |= __CVMX_USB_PIPE_FLAGS_SCHEDULED;
1690
1691 /* Mark this channel as in use */
1692 usb->idle_hardware_channels &= ~(1<<channel);
1693
1694 /* Enable the channel interrupt bits */
1695 {
1696 union cvmx_usbcx_hcintx usbc_hcint;
1697 union cvmx_usbcx_hcintmskx usbc_hcintmsk;
1698 union cvmx_usbcx_haintmsk usbc_haintmsk;
1699
1700 /* Clear all channel status bits */
1701 usbc_hcint.u32 = __cvmx_usb_read_csr32(usb,
1702 CVMX_USBCX_HCINTX(channel, usb->index));
1703
1704 __cvmx_usb_write_csr32(usb,
1705 CVMX_USBCX_HCINTX(channel, usb->index),
1706 usbc_hcint.u32);
1707
1708 usbc_hcintmsk.u32 = 0;
1709 usbc_hcintmsk.s.chhltdmsk = 1;
1710 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) {
1711 /*
1712 * Channels need these extra interrupts when we aren't
1713 * in DMA mode.
1714 */
1715 usbc_hcintmsk.s.datatglerrmsk = 1;
1716 usbc_hcintmsk.s.frmovrunmsk = 1;
1717 usbc_hcintmsk.s.bblerrmsk = 1;
1718 usbc_hcintmsk.s.xacterrmsk = 1;
1719 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1720 /*
1721 * Splits don't generate xfercompl, so we need
1722 * ACK and NYET.
1723 */
1724 usbc_hcintmsk.s.nyetmsk = 1;
1725 usbc_hcintmsk.s.ackmsk = 1;
1726 }
1727 usbc_hcintmsk.s.nakmsk = 1;
1728 usbc_hcintmsk.s.stallmsk = 1;
1729 usbc_hcintmsk.s.xfercomplmsk = 1;
1730 }
1731 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), usbc_hcintmsk.u32);
1732
1733 /* Enable the channel interrupt to propagate */
1734 usbc_haintmsk.u32 = __cvmx_usb_read_csr32(usb,
1735 CVMX_USBCX_HAINTMSK(usb->index));
1736 usbc_haintmsk.s.haintmsk |= 1<<channel;
1737 __cvmx_usb_write_csr32(usb,
1738 CVMX_USBCX_HAINTMSK(usb->index),
1739 usbc_haintmsk.u32);
1740 }
1741
1742 /* Setup the locations the DMA engines use */
1743 {
1744 uint64_t dma_address = transaction->buffer +
1745 transaction->actual_bytes;
1746
1747 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
1748 dma_address = transaction->buffer +
1749 transaction->iso_packets[0].offset +
1750 transaction->actual_bytes;
1751
1752 __cvmx_usb_write_csr64(usb,
1753 CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8,
1754 dma_address);
1755
1756 __cvmx_usb_write_csr64(usb,
1757 CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8,
1758 dma_address);
1759 }
1760
1761 /* Setup both the size of the transfer and the SPLIT characteristics */
1762 {
1763 union cvmx_usbcx_hcspltx usbc_hcsplt = {.u32 = 0};
1764 union cvmx_usbcx_hctsizx usbc_hctsiz = {.u32 = 0};
1765 int packets_to_transfer;
1766 int bytes_to_transfer = transaction->buffer_length -
1767 transaction->actual_bytes;
1768
1769 /*
1770 * ISOCHRONOUS transactions store each individual transfer size
1771 * in the packet structure, not the global buffer_length
1772 */
1773 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
1774 bytes_to_transfer =
1775 transaction->iso_packets[0].length -
1776 transaction->actual_bytes;
1777
1778 /*
1779 * We need to do split transactions when we are talking to non
1780 * high speed devices that are behind a high speed hub
1781 */
1782 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1783 /*
1784 * On the start split phase (stage is even) record the
1785 * frame number we will need to send the split complete.
1786 * We only store the lower two bits since the time ahead
1787 * can only be two frames
1788 */
1789 if ((transaction->stage&1) == 0) {
1790 if (transaction->type == CVMX_USB_TRANSFER_BULK)
1791 pipe->split_sc_frame =
1792 (usb->frame_number + 1) & 0x7f;
1793 else
1794 pipe->split_sc_frame =
1795 (usb->frame_number + 2) & 0x7f;
1796 } else
1797 pipe->split_sc_frame = -1;
1798
1799 usbc_hcsplt.s.spltena = 1;
1800 usbc_hcsplt.s.hubaddr = pipe->hub_device_addr;
1801 usbc_hcsplt.s.prtaddr = pipe->hub_port;
1802 usbc_hcsplt.s.compsplt = (transaction->stage ==
1803 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE);
1804
1805 /*
1806 * SPLIT transactions can only ever transmit one data
1807 * packet so limit the transfer size to the max packet
1808 * size
1809 */
1810 if (bytes_to_transfer > pipe->max_packet)
1811 bytes_to_transfer = pipe->max_packet;
1812
1813 /*
1814 * ISOCHRONOUS OUT splits are unique in that they limit
1815 * data transfers to 188 byte chunks representing the
1816 * begin/middle/end of the data or all
1817 */
1818 if (!usbc_hcsplt.s.compsplt &&
1819 (pipe->transfer_dir ==
1820 CVMX_USB_DIRECTION_OUT) &&
1821 (pipe->transfer_type ==
1822 CVMX_USB_TRANSFER_ISOCHRONOUS)) {
1823 /*
1824 * Clear the split complete frame number as
1825 * there isn't going to be a split complete
1826 */
1827 pipe->split_sc_frame = -1;
1828 /*
1829 * See if we've started this transfer and sent
1830 * data
1831 */
1832 if (transaction->actual_bytes == 0) {
1833 /*
1834 * Nothing sent yet, this is either a
1835 * begin or the entire payload
1836 */
1837 if (bytes_to_transfer <= 188)
1838 /* Entire payload in one go */
1839 usbc_hcsplt.s.xactpos = 3;
1840 else
1841 /* First part of payload */
1842 usbc_hcsplt.s.xactpos = 2;
1843 } else {
1844 /*
1845 * Continuing the previous data, we must
1846 * either be in the middle or at the end
1847 */
1848 if (bytes_to_transfer <= 188)
1849 /* End of payload */
1850 usbc_hcsplt.s.xactpos = 1;
1851 else
1852 /* Middle of payload */
1853 usbc_hcsplt.s.xactpos = 0;
1854 }
1855 /*
1856 * Again, the transfer size is limited to 188
1857 * bytes
1858 */
1859 if (bytes_to_transfer > 188)
1860 bytes_to_transfer = 188;
1861 }
1862 }
1863
1864 /*
1865 * Make sure the transfer never exceeds the byte limit of the
1866 * hardware. Further bytes will be sent as continued
1867 * transactions
1868 */
1869 if (bytes_to_transfer > MAX_TRANSFER_BYTES) {
1870 /*
1871 * Round MAX_TRANSFER_BYTES to a multiple of out packet
1872 * size
1873 */
1874 bytes_to_transfer = MAX_TRANSFER_BYTES /
1875 pipe->max_packet;
1876 bytes_to_transfer *= pipe->max_packet;
1877 }
1878
1879 /*
1880 * Calculate the number of packets to transfer. If the length is
1881 * zero we still need to transfer one packet
1882 */
1883 packets_to_transfer =
1884 (bytes_to_transfer + pipe->max_packet - 1) /
1885 pipe->max_packet;
1886 if (packets_to_transfer == 0)
1887 packets_to_transfer = 1;
1888 else if ((packets_to_transfer > 1) &&
1889 (usb->init_flags &
1890 CVMX_USB_INITIALIZE_FLAGS_NO_DMA)) {
1891 /*
1892 * Limit to one packet when not using DMA. Channels must
1893 * be restarted between every packet for IN
1894 * transactions, so there is no reason to do multiple
1895 * packets in a row
1896 */
1897 packets_to_transfer = 1;
1898 bytes_to_transfer = packets_to_transfer *
1899 pipe->max_packet;
1900 } else if (packets_to_transfer > MAX_TRANSFER_PACKETS) {
1901 /*
1902 * Limit the number of packet and data transferred to
1903 * what the hardware can handle
1904 */
1905 packets_to_transfer = MAX_TRANSFER_PACKETS;
1906 bytes_to_transfer = packets_to_transfer *
1907 pipe->max_packet;
1908 }
1909
1910 usbc_hctsiz.s.xfersize = bytes_to_transfer;
1911 usbc_hctsiz.s.pktcnt = packets_to_transfer;
1912
1913 /* Update the DATA0/DATA1 toggle */
1914 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1915 /*
1916 * High speed pipes may need a hardware ping before they start
1917 */
1918 if (pipe->flags & __CVMX_USB_PIPE_FLAGS_NEED_PING)
1919 usbc_hctsiz.s.dopng = 1;
1920
1921 __cvmx_usb_write_csr32(usb,
1922 CVMX_USBCX_HCSPLTX(channel, usb->index),
1923 usbc_hcsplt.u32);
1924 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCTSIZX(channel,
1925 usb->index), usbc_hctsiz.u32);
1926 }
1927
1928 /* Setup the Host Channel Characteristics Register */
1929 {
1930 union cvmx_usbcx_hccharx usbc_hcchar = {.u32 = 0};
1931
1932 /*
1933 * Set the startframe odd/even properly. This is only used for
1934 * periodic
1935 */
1936 usbc_hcchar.s.oddfrm = usb->frame_number&1;
1937
1938 /*
1939 * Set the number of back to back packets allowed by this
1940 * endpoint. Split transactions interpret "ec" as the number of
1941 * immediate retries of failure. These retries happen too
1942 * quickly, so we disable these entirely for splits
1943 */
1944 if (__cvmx_usb_pipe_needs_split(usb, pipe))
1945 usbc_hcchar.s.ec = 1;
1946 else if (pipe->multi_count < 1)
1947 usbc_hcchar.s.ec = 1;
1948 else if (pipe->multi_count > 3)
1949 usbc_hcchar.s.ec = 3;
1950 else
1951 usbc_hcchar.s.ec = pipe->multi_count;
1952
1953 /* Set the rest of the endpoint specific settings */
1954 usbc_hcchar.s.devaddr = pipe->device_addr;
1955 usbc_hcchar.s.eptype = transaction->type;
1956 usbc_hcchar.s.lspddev =
1957 (pipe->device_speed == CVMX_USB_SPEED_LOW);
1958 usbc_hcchar.s.epdir = pipe->transfer_dir;
1959 usbc_hcchar.s.epnum = pipe->endpoint_num;
1960 usbc_hcchar.s.mps = pipe->max_packet;
1961 __cvmx_usb_write_csr32(usb,
1962 CVMX_USBCX_HCCHARX(channel, usb->index),
1963 usbc_hcchar.u32);
1964 }
1965
1966 /* Do transaction type specific fixups as needed */
1967 switch (transaction->type) {
1968 case CVMX_USB_TRANSFER_CONTROL:
1969 __cvmx_usb_start_channel_control(usb, channel, pipe);
1970 break;
1971 case CVMX_USB_TRANSFER_BULK:
1972 case CVMX_USB_TRANSFER_INTERRUPT:
1973 break;
1974 case CVMX_USB_TRANSFER_ISOCHRONOUS:
1975 if (!__cvmx_usb_pipe_needs_split(usb, pipe)) {
1976 /*
1977 * ISO transactions require different PIDs depending on
1978 * direction and how many packets are needed
1979 */
1980 if (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) {
1981 if (pipe->multi_count < 2) /* Need DATA0 */
1982 USB_SET_FIELD32(
1983 CVMX_USBCX_HCTSIZX(channel,
1984 usb->index),
1985 union cvmx_usbcx_hctsizx,
1986 pid, 0);
1987 else /* Need MDATA */
1988 USB_SET_FIELD32(
1989 CVMX_USBCX_HCTSIZX(channel,
1990 usb->index),
1991 union cvmx_usbcx_hctsizx,
1992 pid, 3);
1993 }
1994 }
1995 break;
1996 }
1997 {
1998 union cvmx_usbcx_hctsizx usbc_hctsiz = {.u32 =
1999 __cvmx_usb_read_csr32(usb,
2000 CVMX_USBCX_HCTSIZX(channel, usb->index))};
2001 transaction->xfersize = usbc_hctsiz.s.xfersize;
2002 transaction->pktcnt = usbc_hctsiz.s.pktcnt;
2003 }
2004 /* Remeber when we start a split transaction */
2005 if (__cvmx_usb_pipe_needs_split(usb, pipe))
2006 usb->active_split = transaction;
2007 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
2008 union cvmx_usbcx_hccharx, chena, 1);
2009 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
2010 __cvmx_usb_fill_tx_fifo(usb, channel);
2011 return;
2012 }
2013
2014
2015 /**
2016 * Find a pipe that is ready to be scheduled to hardware.
2017 * @usb: USB device state populated by cvmx_usb_initialize().
2018 * @list: Pipe list to search
2019 * @current_frame:
2020 * Frame counter to use as a time reference.
2021 *
2022 * Returns: Pipe or NULL if none are ready
2023 */
2024 static struct cvmx_usb_pipe *__cvmx_usb_find_ready_pipe(
2025 struct cvmx_usb_state *usb,
2026 struct list_head *list,
2027 uint64_t current_frame)
2028 {
2029 struct cvmx_usb_pipe *pipe;
2030
2031 list_for_each_entry(pipe, list, node) {
2032 struct cvmx_usb_transaction *t =
2033 list_first_entry(&pipe->transactions, typeof(*t),
2034 node);
2035 if (!(pipe->flags & __CVMX_USB_PIPE_FLAGS_SCHEDULED) && t &&
2036 (pipe->next_tx_frame <= current_frame) &&
2037 ((pipe->split_sc_frame == -1) ||
2038 ((((int)current_frame - (int)pipe->split_sc_frame)
2039 & 0x7f) < 0x40)) &&
2040 (!usb->active_split || (usb->active_split == t))) {
2041 prefetch(t);
2042 return pipe;
2043 }
2044 }
2045 return NULL;
2046 }
2047
2048
2049 /**
2050 * Called whenever a pipe might need to be scheduled to the
2051 * hardware.
2052 *
2053 * @usb: USB device state populated by cvmx_usb_initialize().
2054 * @is_sof: True if this schedule was called on a SOF interrupt.
2055 */
2056 static void __cvmx_usb_schedule(struct cvmx_usb_state *usb, int is_sof)
2057 {
2058 int channel;
2059 struct cvmx_usb_pipe *pipe;
2060 int need_sof;
2061 enum cvmx_usb_transfer ttype;
2062
2063 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) {
2064 /*
2065 * Without DMA we need to be careful to not schedule something
2066 * at the end of a frame and cause an overrun.
2067 */
2068 union cvmx_usbcx_hfnum hfnum = {
2069 .u32 = __cvmx_usb_read_csr32(usb,
2070 CVMX_USBCX_HFNUM(usb->index))
2071 };
2072
2073 union cvmx_usbcx_hfir hfir = {
2074 .u32 = __cvmx_usb_read_csr32(usb,
2075 CVMX_USBCX_HFIR(usb->index))
2076 };
2077
2078 if (hfnum.s.frrem < hfir.s.frint/4)
2079 goto done;
2080 }
2081
2082 while (usb->idle_hardware_channels) {
2083 /* Find an idle channel */
2084 channel = __fls(usb->idle_hardware_channels);
2085 if (unlikely(channel > 7))
2086 break;
2087
2088 /* Find a pipe needing service */
2089 pipe = NULL;
2090 if (is_sof) {
2091 /*
2092 * Only process periodic pipes on SOF interrupts. This
2093 * way we are sure that the periodic data is sent in the
2094 * beginning of the frame
2095 */
2096 pipe = __cvmx_usb_find_ready_pipe(usb,
2097 usb->active_pipes +
2098 CVMX_USB_TRANSFER_ISOCHRONOUS,
2099 usb->frame_number);
2100 if (likely(!pipe))
2101 pipe = __cvmx_usb_find_ready_pipe(usb,
2102 usb->active_pipes +
2103 CVMX_USB_TRANSFER_INTERRUPT,
2104 usb->frame_number);
2105 }
2106 if (likely(!pipe)) {
2107 pipe = __cvmx_usb_find_ready_pipe(usb,
2108 usb->active_pipes +
2109 CVMX_USB_TRANSFER_CONTROL,
2110 usb->frame_number);
2111 if (likely(!pipe))
2112 pipe = __cvmx_usb_find_ready_pipe(usb,
2113 usb->active_pipes +
2114 CVMX_USB_TRANSFER_BULK,
2115 usb->frame_number);
2116 }
2117 if (!pipe)
2118 break;
2119
2120 __cvmx_usb_start_channel(usb, channel, pipe);
2121 }
2122
2123 done:
2124 /*
2125 * Only enable SOF interrupts when we have transactions pending in the
2126 * future that might need to be scheduled
2127 */
2128 need_sof = 0;
2129 for (ttype = CVMX_USB_TRANSFER_CONTROL;
2130 ttype <= CVMX_USB_TRANSFER_INTERRUPT; ttype++) {
2131 list_for_each_entry(pipe, &usb->active_pipes[ttype], node) {
2132 if (pipe->next_tx_frame > usb->frame_number) {
2133 need_sof = 1;
2134 break;
2135 }
2136 }
2137 }
2138 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index),
2139 union cvmx_usbcx_gintmsk, sofmsk, need_sof);
2140 return;
2141 }
2142
2143 static inline struct octeon_hcd *cvmx_usb_to_octeon(struct cvmx_usb_state *p)
2144 {
2145 return container_of(p, struct octeon_hcd, usb);
2146 }
2147
2148 static inline struct usb_hcd *octeon_to_hcd(struct octeon_hcd *p)
2149 {
2150 return container_of((void *)p, struct usb_hcd, hcd_priv);
2151 }
2152
2153 static void octeon_usb_urb_complete_callback(struct cvmx_usb_state *usb,
2154 enum cvmx_usb_complete status,
2155 struct cvmx_usb_pipe *pipe,
2156 struct cvmx_usb_transaction
2157 *transaction,
2158 int bytes_transferred,
2159 struct urb *urb)
2160 {
2161 struct octeon_hcd *priv = cvmx_usb_to_octeon(usb);
2162 struct usb_hcd *hcd = octeon_to_hcd(priv);
2163 struct device *dev = hcd->self.controller;
2164
2165 urb->actual_length = bytes_transferred;
2166 urb->hcpriv = NULL;
2167
2168 /* For Isochronous transactions we need to update the URB packet status
2169 list from data in our private copy */
2170 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2171 int i;
2172 /*
2173 * The pointer to the private list is stored in the setup_packet
2174 * field.
2175 */
2176 struct cvmx_usb_iso_packet *iso_packet =
2177 (struct cvmx_usb_iso_packet *) urb->setup_packet;
2178 /* Recalculate the transfer size by adding up each packet */
2179 urb->actual_length = 0;
2180 for (i = 0; i < urb->number_of_packets; i++) {
2181 if (iso_packet[i].status ==
2182 CVMX_USB_COMPLETE_SUCCESS) {
2183 urb->iso_frame_desc[i].status = 0;
2184 urb->iso_frame_desc[i].actual_length =
2185 iso_packet[i].length;
2186 urb->actual_length +=
2187 urb->iso_frame_desc[i].actual_length;
2188 } else {
2189 dev_dbg(dev, "ISOCHRONOUS packet=%d of %d status=%d pipe=%p transaction=%p size=%d\n",
2190 i, urb->number_of_packets,
2191 iso_packet[i].status, pipe,
2192 transaction, iso_packet[i].length);
2193 urb->iso_frame_desc[i].status = -EREMOTEIO;
2194 }
2195 }
2196 /* Free the private list now that we don't need it anymore */
2197 kfree(iso_packet);
2198 urb->setup_packet = NULL;
2199 }
2200
2201 switch (status) {
2202 case CVMX_USB_COMPLETE_SUCCESS:
2203 urb->status = 0;
2204 break;
2205 case CVMX_USB_COMPLETE_CANCEL:
2206 if (urb->status == 0)
2207 urb->status = -ENOENT;
2208 break;
2209 case CVMX_USB_COMPLETE_STALL:
2210 dev_dbg(dev, "status=stall pipe=%p transaction=%p size=%d\n",
2211 pipe, transaction, bytes_transferred);
2212 urb->status = -EPIPE;
2213 break;
2214 case CVMX_USB_COMPLETE_BABBLEERR:
2215 dev_dbg(dev, "status=babble pipe=%p transaction=%p size=%d\n",
2216 pipe, transaction, bytes_transferred);
2217 urb->status = -EPIPE;
2218 break;
2219 case CVMX_USB_COMPLETE_SHORT:
2220 dev_dbg(dev, "status=short pipe=%p transaction=%p size=%d\n",
2221 pipe, transaction, bytes_transferred);
2222 urb->status = -EREMOTEIO;
2223 break;
2224 case CVMX_USB_COMPLETE_ERROR:
2225 case CVMX_USB_COMPLETE_XACTERR:
2226 case CVMX_USB_COMPLETE_DATATGLERR:
2227 case CVMX_USB_COMPLETE_FRAMEERR:
2228 dev_dbg(dev, "status=%d pipe=%p transaction=%p size=%d\n",
2229 status, pipe, transaction, bytes_transferred);
2230 urb->status = -EPROTO;
2231 break;
2232 }
2233 usb_hcd_unlink_urb_from_ep(octeon_to_hcd(priv), urb);
2234 spin_unlock(&priv->lock);
2235 usb_hcd_giveback_urb(octeon_to_hcd(priv), urb, urb->status);
2236 spin_lock(&priv->lock);
2237 }
2238
2239 /**
2240 * Signal the completion of a transaction and free it. The
2241 * transaction will be removed from the pipe transaction list.
2242 *
2243 * @usb: USB device state populated by cvmx_usb_initialize().
2244 * @pipe: Pipe the transaction is on
2245 * @transaction:
2246 * Transaction that completed
2247 * @complete_code:
2248 * Completion code
2249 */
2250 static void __cvmx_usb_perform_complete(
2251 struct cvmx_usb_state *usb,
2252 struct cvmx_usb_pipe *pipe,
2253 struct cvmx_usb_transaction *transaction,
2254 enum cvmx_usb_complete complete_code)
2255 {
2256 /* If this was a split then clear our split in progress marker */
2257 if (usb->active_split == transaction)
2258 usb->active_split = NULL;
2259
2260 /*
2261 * Isochronous transactions need extra processing as they might not be
2262 * done after a single data transfer
2263 */
2264 if (unlikely(transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)) {
2265 /* Update the number of bytes transferred in this ISO packet */
2266 transaction->iso_packets[0].length = transaction->actual_bytes;
2267 transaction->iso_packets[0].status = complete_code;
2268
2269 /*
2270 * If there are more ISOs pending and we succeeded, schedule the
2271 * next one
2272 */
2273 if ((transaction->iso_number_packets > 1) &&
2274 (complete_code == CVMX_USB_COMPLETE_SUCCESS)) {
2275 /* No bytes transferred for this packet as of yet */
2276 transaction->actual_bytes = 0;
2277 /* One less ISO waiting to transfer */
2278 transaction->iso_number_packets--;
2279 /* Increment to the next location in our packet array */
2280 transaction->iso_packets++;
2281 transaction->stage = CVMX_USB_STAGE_NON_CONTROL;
2282 goto done;
2283 }
2284 }
2285
2286 /* Remove the transaction from the pipe list */
2287 list_del(&transaction->node);
2288 if (list_empty(&pipe->transactions))
2289 list_move_tail(&pipe->node, &usb->idle_pipes);
2290 octeon_usb_urb_complete_callback(usb, complete_code, pipe,
2291 transaction,
2292 transaction->actual_bytes,
2293 transaction->urb);
2294 kfree(transaction);
2295 done:
2296 return;
2297 }
2298
2299
2300 /**
2301 * Submit a usb transaction to a pipe. Called for all types
2302 * of transactions.
2303 *
2304 * @usb:
2305 * @pipe: Which pipe to submit to.
2306 * @type: Transaction type
2307 * @buffer: User buffer for the transaction
2308 * @buffer_length:
2309 * User buffer's length in bytes
2310 * @control_header:
2311 * For control transactions, the 8 byte standard header
2312 * @iso_start_frame:
2313 * For ISO transactions, the start frame
2314 * @iso_number_packets:
2315 * For ISO, the number of packet in the transaction.
2316 * @iso_packets:
2317 * A description of each ISO packet
2318 * @urb: URB for the callback
2319 *
2320 * Returns: Transaction or NULL on failure.
2321 */
2322 static struct cvmx_usb_transaction *__cvmx_usb_submit_transaction(
2323 struct cvmx_usb_state *usb,
2324 struct cvmx_usb_pipe *pipe,
2325 enum cvmx_usb_transfer type,
2326 uint64_t buffer,
2327 int buffer_length,
2328 uint64_t control_header,
2329 int iso_start_frame,
2330 int iso_number_packets,
2331 struct cvmx_usb_iso_packet *iso_packets,
2332 struct urb *urb)
2333 {
2334 struct cvmx_usb_transaction *transaction;
2335
2336 if (unlikely(pipe->transfer_type != type))
2337 return NULL;
2338
2339 transaction = kzalloc(sizeof(*transaction), GFP_ATOMIC);
2340 if (unlikely(!transaction))
2341 return NULL;
2342
2343 transaction->type = type;
2344 transaction->buffer = buffer;
2345 transaction->buffer_length = buffer_length;
2346 transaction->control_header = control_header;
2347 /* FIXME: This is not used, implement it. */
2348 transaction->iso_start_frame = iso_start_frame;
2349 transaction->iso_number_packets = iso_number_packets;
2350 transaction->iso_packets = iso_packets;
2351 transaction->urb = urb;
2352 if (transaction->type == CVMX_USB_TRANSFER_CONTROL)
2353 transaction->stage = CVMX_USB_STAGE_SETUP;
2354 else
2355 transaction->stage = CVMX_USB_STAGE_NON_CONTROL;
2356
2357 if (!list_empty(&pipe->transactions)) {
2358 list_add_tail(&transaction->node, &pipe->transactions);
2359 } else {
2360 list_add_tail(&transaction->node, &pipe->transactions);
2361 list_move_tail(&pipe->node,
2362 &usb->active_pipes[pipe->transfer_type]);
2363
2364 /*
2365 * We may need to schedule the pipe if this was the head of the
2366 * pipe.
2367 */
2368 __cvmx_usb_schedule(usb, 0);
2369 }
2370
2371 return transaction;
2372 }
2373
2374
2375 /**
2376 * Call to submit a USB Bulk transfer to a pipe.
2377 *
2378 * @usb: USB device state populated by cvmx_usb_initialize().
2379 * @pipe: Handle to the pipe for the transfer.
2380 * @urb: URB.
2381 *
2382 * Returns: A submitted transaction or NULL on failure.
2383 */
2384 static struct cvmx_usb_transaction *cvmx_usb_submit_bulk(
2385 struct cvmx_usb_state *usb,
2386 struct cvmx_usb_pipe *pipe,
2387 struct urb *urb)
2388 {
2389 return __cvmx_usb_submit_transaction(usb, pipe, CVMX_USB_TRANSFER_BULK,
2390 urb->transfer_dma,
2391 urb->transfer_buffer_length,
2392 0, /* control_header */
2393 0, /* iso_start_frame */
2394 0, /* iso_number_packets */
2395 NULL, /* iso_packets */
2396 urb);
2397 }
2398
2399
2400 /**
2401 * Call to submit a USB Interrupt transfer to a pipe.
2402 *
2403 * @usb: USB device state populated by cvmx_usb_initialize().
2404 * @pipe: Handle to the pipe for the transfer.
2405 * @urb: URB returned when the callback is called.
2406 *
2407 * Returns: A submitted transaction or NULL on failure.
2408 */
2409 static struct cvmx_usb_transaction *cvmx_usb_submit_interrupt(
2410 struct cvmx_usb_state *usb,
2411 struct cvmx_usb_pipe *pipe,
2412 struct urb *urb)
2413 {
2414 return __cvmx_usb_submit_transaction(usb, pipe,
2415 CVMX_USB_TRANSFER_INTERRUPT,
2416 urb->transfer_dma,
2417 urb->transfer_buffer_length,
2418 0, /* control_header */
2419 0, /* iso_start_frame */
2420 0, /* iso_number_packets */
2421 NULL, /* iso_packets */
2422 urb);
2423 }
2424
2425
2426 /**
2427 * Call to submit a USB Control transfer to a pipe.
2428 *
2429 * @usb: USB device state populated by cvmx_usb_initialize().
2430 * @pipe: Handle to the pipe for the transfer.
2431 * @urb: URB.
2432 *
2433 * Returns: A submitted transaction or NULL on failure.
2434 */
2435 static struct cvmx_usb_transaction *cvmx_usb_submit_control(
2436 struct cvmx_usb_state *usb,
2437 struct cvmx_usb_pipe *pipe,
2438 struct urb *urb)
2439 {
2440 int buffer_length = urb->transfer_buffer_length;
2441 uint64_t control_header = urb->setup_dma;
2442 union cvmx_usb_control_header *header =
2443 cvmx_phys_to_ptr(control_header);
2444
2445 if ((header->s.request_type & 0x80) == 0)
2446 buffer_length = le16_to_cpu(header->s.length);
2447
2448 return __cvmx_usb_submit_transaction(usb, pipe,
2449 CVMX_USB_TRANSFER_CONTROL,
2450 urb->transfer_dma, buffer_length,
2451 control_header,
2452 0, /* iso_start_frame */
2453 0, /* iso_number_packets */
2454 NULL, /* iso_packets */
2455 urb);
2456 }
2457
2458
2459 /**
2460 * Call to submit a USB Isochronous transfer to a pipe.
2461 *
2462 * @usb: USB device state populated by cvmx_usb_initialize().
2463 * @pipe: Handle to the pipe for the transfer.
2464 * @urb: URB returned when the callback is called.
2465 *
2466 * Returns: A submitted transaction or NULL on failure.
2467 */
2468 static struct cvmx_usb_transaction *cvmx_usb_submit_isochronous(
2469 struct cvmx_usb_state *usb,
2470 struct cvmx_usb_pipe *pipe,
2471 struct urb *urb)
2472 {
2473 struct cvmx_usb_iso_packet *packets;
2474
2475 packets = (struct cvmx_usb_iso_packet *) urb->setup_packet;
2476 return __cvmx_usb_submit_transaction(usb, pipe,
2477 CVMX_USB_TRANSFER_ISOCHRONOUS,
2478 urb->transfer_dma,
2479 urb->transfer_buffer_length,
2480 0, /* control_header */
2481 urb->start_frame,
2482 urb->number_of_packets,
2483 packets, urb);
2484 }
2485
2486
2487 /**
2488 * Cancel one outstanding request in a pipe. Canceling a request
2489 * can fail if the transaction has already completed before cancel
2490 * is called. Even after a successful cancel call, it may take
2491 * a frame or two for the cvmx_usb_poll() function to call the
2492 * associated callback.
2493 *
2494 * @usb: USB device state populated by cvmx_usb_initialize().
2495 * @pipe: Pipe to cancel requests in.
2496 * @transaction: Transaction to cancel, returned by the submit function.
2497 *
2498 * Returns: 0 or a negative error code.
2499 */
2500 static int cvmx_usb_cancel(struct cvmx_usb_state *usb,
2501 struct cvmx_usb_pipe *pipe,
2502 struct cvmx_usb_transaction *transaction)
2503 {
2504 /*
2505 * If the transaction is the HEAD of the queue and scheduled. We need to
2506 * treat it special
2507 */
2508 if (list_first_entry(&pipe->transactions, typeof(*transaction), node) ==
2509 transaction && (pipe->flags & __CVMX_USB_PIPE_FLAGS_SCHEDULED)) {
2510 union cvmx_usbcx_hccharx usbc_hcchar;
2511
2512 usb->pipe_for_channel[pipe->channel] = NULL;
2513 pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_SCHEDULED;
2514
2515 CVMX_SYNCW;
2516
2517 usbc_hcchar.u32 = __cvmx_usb_read_csr32(usb,
2518 CVMX_USBCX_HCCHARX(pipe->channel, usb->index));
2519 /*
2520 * If the channel isn't enabled then the transaction already
2521 * completed.
2522 */
2523 if (usbc_hcchar.s.chena) {
2524 usbc_hcchar.s.chdis = 1;
2525 __cvmx_usb_write_csr32(usb,
2526 CVMX_USBCX_HCCHARX(pipe->channel,
2527 usb->index),
2528 usbc_hcchar.u32);
2529 }
2530 }
2531 __cvmx_usb_perform_complete(usb, pipe, transaction,
2532 CVMX_USB_COMPLETE_CANCEL);
2533 return 0;
2534 }
2535
2536
2537 /**
2538 * Cancel all outstanding requests in a pipe. Logically all this
2539 * does is call cvmx_usb_cancel() in a loop.
2540 *
2541 * @usb: USB device state populated by cvmx_usb_initialize().
2542 * @pipe: Pipe to cancel requests in.
2543 *
2544 * Returns: 0 or a negative error code.
2545 */
2546 static int cvmx_usb_cancel_all(struct cvmx_usb_state *usb,
2547 struct cvmx_usb_pipe *pipe)
2548 {
2549 struct cvmx_usb_transaction *transaction, *next;
2550
2551 /* Simply loop through and attempt to cancel each transaction */
2552 list_for_each_entry_safe(transaction, next, &pipe->transactions, node) {
2553 int result = cvmx_usb_cancel(usb, pipe, transaction);
2554
2555 if (unlikely(result != 0))
2556 return result;
2557 }
2558 return 0;
2559 }
2560
2561
2562 /**
2563 * Close a pipe created with cvmx_usb_open_pipe().
2564 *
2565 * @usb: USB device state populated by cvmx_usb_initialize().
2566 * @pipe: Pipe to close.
2567 *
2568 * Returns: 0 or a negative error code. EBUSY is returned if the pipe has
2569 * outstanding transfers.
2570 */
2571 static int cvmx_usb_close_pipe(struct cvmx_usb_state *usb,
2572 struct cvmx_usb_pipe *pipe)
2573 {
2574 /* Fail if the pipe has pending transactions */
2575 if (!list_empty(&pipe->transactions))
2576 return -EBUSY;
2577
2578 list_del(&pipe->node);
2579 kfree(pipe);
2580
2581 return 0;
2582 }
2583
2584 /**
2585 * Get the current USB protocol level frame number. The frame
2586 * number is always in the range of 0-0x7ff.
2587 *
2588 * @usb: USB device state populated by cvmx_usb_initialize().
2589 *
2590 * Returns: USB frame number
2591 */
2592 static int cvmx_usb_get_frame_number(struct cvmx_usb_state *usb)
2593 {
2594 int frame_number;
2595 union cvmx_usbcx_hfnum usbc_hfnum;
2596
2597 usbc_hfnum.u32 = __cvmx_usb_read_csr32(usb,
2598 CVMX_USBCX_HFNUM(usb->index));
2599 frame_number = usbc_hfnum.s.frnum;
2600
2601 return frame_number;
2602 }
2603
2604
2605 /**
2606 * Poll a channel for status
2607 *
2608 * @usb: USB device
2609 * @channel: Channel to poll
2610 *
2611 * Returns: Zero on success
2612 */
2613 static int __cvmx_usb_poll_channel(struct cvmx_usb_state *usb, int channel)
2614 {
2615 union cvmx_usbcx_hcintx usbc_hcint;
2616 union cvmx_usbcx_hctsizx usbc_hctsiz;
2617 union cvmx_usbcx_hccharx usbc_hcchar;
2618 struct cvmx_usb_pipe *pipe;
2619 struct cvmx_usb_transaction *transaction;
2620 int bytes_this_transfer;
2621 int bytes_in_last_packet;
2622 int packets_processed;
2623 int buffer_space_left;
2624
2625 /* Read the interrupt status bits for the channel */
2626 usbc_hcint.u32 = __cvmx_usb_read_csr32(usb,
2627 CVMX_USBCX_HCINTX(channel, usb->index));
2628
2629 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) {
2630 usbc_hcchar.u32 = __cvmx_usb_read_csr32(usb,
2631 CVMX_USBCX_HCCHARX(channel, usb->index));
2632
2633 if (usbc_hcchar.s.chena && usbc_hcchar.s.chdis) {
2634 /*
2635 * There seems to be a bug in CN31XX which can cause
2636 * interrupt IN transfers to get stuck until we do a
2637 * write of HCCHARX without changing things
2638 */
2639 __cvmx_usb_write_csr32(usb,
2640 CVMX_USBCX_HCCHARX(channel,
2641 usb->index),
2642 usbc_hcchar.u32);
2643 return 0;
2644 }
2645
2646 /*
2647 * In non DMA mode the channels don't halt themselves. We need
2648 * to manually disable channels that are left running
2649 */
2650 if (!usbc_hcint.s.chhltd) {
2651 if (usbc_hcchar.s.chena) {
2652 union cvmx_usbcx_hcintmskx hcintmsk;
2653 /* Disable all interrupts except CHHLTD */
2654 hcintmsk.u32 = 0;
2655 hcintmsk.s.chhltdmsk = 1;
2656 __cvmx_usb_write_csr32(usb,
2657 CVMX_USBCX_HCINTMSKX(channel,
2658 usb->index),
2659 hcintmsk.u32);
2660 usbc_hcchar.s.chdis = 1;
2661 __cvmx_usb_write_csr32(usb,
2662 CVMX_USBCX_HCCHARX(channel,
2663 usb->index),
2664 usbc_hcchar.u32);
2665 return 0;
2666 } else if (usbc_hcint.s.xfercompl) {
2667 /*
2668 * Successful IN/OUT with transfer complete.
2669 * Channel halt isn't needed.
2670 */
2671 } else {
2672 cvmx_dprintf("USB%d: Channel %d interrupt without halt\n",
2673 usb->index, channel);
2674 return 0;
2675 }
2676 }
2677 } else {
2678 /*
2679 * There is are no interrupts that we need to process when the
2680 * channel is still running
2681 */
2682 if (!usbc_hcint.s.chhltd)
2683 return 0;
2684 }
2685
2686 /* Disable the channel interrupts now that it is done */
2687 __cvmx_usb_write_csr32(usb,
2688 CVMX_USBCX_HCINTMSKX(channel, usb->index),
2689 0);
2690 usb->idle_hardware_channels |= (1<<channel);
2691
2692 /* Make sure this channel is tied to a valid pipe */
2693 pipe = usb->pipe_for_channel[channel];
2694 prefetch(pipe);
2695 if (!pipe)
2696 return 0;
2697 transaction = list_first_entry(&pipe->transactions,
2698 typeof(*transaction),
2699 node);
2700 prefetch(transaction);
2701
2702 /*
2703 * Disconnect this pipe from the HW channel. Later the schedule
2704 * function will figure out which pipe needs to go
2705 */
2706 usb->pipe_for_channel[channel] = NULL;
2707 pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_SCHEDULED;
2708
2709 /*
2710 * Read the channel config info so we can figure out how much data
2711 * transfered
2712 */
2713 usbc_hcchar.u32 = __cvmx_usb_read_csr32(usb,
2714 CVMX_USBCX_HCCHARX(channel, usb->index));
2715 usbc_hctsiz.u32 = __cvmx_usb_read_csr32(usb,
2716 CVMX_USBCX_HCTSIZX(channel, usb->index));
2717
2718 /*
2719 * Calculating the number of bytes successfully transferred is dependent
2720 * on the transfer direction
2721 */
2722 packets_processed = transaction->pktcnt - usbc_hctsiz.s.pktcnt;
2723 if (usbc_hcchar.s.epdir) {
2724 /*
2725 * IN transactions are easy. For every byte received the
2726 * hardware decrements xfersize. All we need to do is subtract
2727 * the current value of xfersize from its starting value and we
2728 * know how many bytes were written to the buffer
2729 */
2730 bytes_this_transfer = transaction->xfersize -
2731 usbc_hctsiz.s.xfersize;
2732 } else {
2733 /*
2734 * OUT transaction don't decrement xfersize. Instead pktcnt is
2735 * decremented on every successful packet send. The hardware
2736 * does this when it receives an ACK, or NYET. If it doesn't
2737 * receive one of these responses pktcnt doesn't change
2738 */
2739 bytes_this_transfer = packets_processed * usbc_hcchar.s.mps;
2740 /*
2741 * The last packet may not be a full transfer if we didn't have
2742 * enough data
2743 */
2744 if (bytes_this_transfer > transaction->xfersize)
2745 bytes_this_transfer = transaction->xfersize;
2746 }
2747 /* Figure out how many bytes were in the last packet of the transfer */
2748 if (packets_processed)
2749 bytes_in_last_packet = bytes_this_transfer -
2750 (packets_processed - 1) * usbc_hcchar.s.mps;
2751 else
2752 bytes_in_last_packet = bytes_this_transfer;
2753
2754 /*
2755 * As a special case, setup transactions output the setup header, not
2756 * the user's data. For this reason we don't count setup data as bytes
2757 * transferred
2758 */
2759 if ((transaction->stage == CVMX_USB_STAGE_SETUP) ||
2760 (transaction->stage == CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE))
2761 bytes_this_transfer = 0;
2762
2763 /*
2764 * Add the bytes transferred to the running total. It is important that
2765 * bytes_this_transfer doesn't count any data that needs to be
2766 * retransmitted
2767 */
2768 transaction->actual_bytes += bytes_this_transfer;
2769 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
2770 buffer_space_left = transaction->iso_packets[0].length -
2771 transaction->actual_bytes;
2772 else
2773 buffer_space_left = transaction->buffer_length -
2774 transaction->actual_bytes;
2775
2776 /*
2777 * We need to remember the PID toggle state for the next transaction.
2778 * The hardware already updated it for the next transaction
2779 */
2780 pipe->pid_toggle = !(usbc_hctsiz.s.pid == 0);
2781
2782 /*
2783 * For high speed bulk out, assume the next transaction will need to do
2784 * a ping before proceeding. If this isn't true the ACK processing below
2785 * will clear this flag
2786 */
2787 if ((pipe->device_speed == CVMX_USB_SPEED_HIGH) &&
2788 (pipe->transfer_type == CVMX_USB_TRANSFER_BULK) &&
2789 (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT))
2790 pipe->flags |= __CVMX_USB_PIPE_FLAGS_NEED_PING;
2791
2792 if (usbc_hcint.s.stall) {
2793 /*
2794 * STALL as a response means this transaction cannot be
2795 * completed because the device can't process transactions. Tell
2796 * the user. Any data that was transferred will be counted on
2797 * the actual bytes transferred
2798 */
2799 pipe->pid_toggle = 0;
2800 __cvmx_usb_perform_complete(usb, pipe, transaction,
2801 CVMX_USB_COMPLETE_STALL);
2802 } else if (usbc_hcint.s.xacterr) {
2803 /*
2804 * We know at least one packet worked if we get a ACK or NAK.
2805 * Reset the retry counter
2806 */
2807 if (usbc_hcint.s.nak || usbc_hcint.s.ack)
2808 transaction->retries = 0;
2809 transaction->retries++;
2810 if (transaction->retries > MAX_RETRIES) {
2811 /*
2812 * XactErr as a response means the device signaled
2813 * something wrong with the transfer. For example, PID
2814 * toggle errors cause these
2815 */
2816 __cvmx_usb_perform_complete(usb, pipe, transaction,
2817 CVMX_USB_COMPLETE_XACTERR);
2818 } else {
2819 /*
2820 * If this was a split then clear our split in progress
2821 * marker
2822 */
2823 if (usb->active_split == transaction)
2824 usb->active_split = NULL;
2825 /*
2826 * Rewind to the beginning of the transaction by anding
2827 * off the split complete bit
2828 */
2829 transaction->stage &= ~1;
2830 pipe->split_sc_frame = -1;
2831 pipe->next_tx_frame += pipe->interval;
2832 if (pipe->next_tx_frame < usb->frame_number)
2833 pipe->next_tx_frame =
2834 usb->frame_number + pipe->interval -
2835 (usb->frame_number -
2836 pipe->next_tx_frame) % pipe->interval;
2837 }
2838 } else if (usbc_hcint.s.bblerr) {
2839 /* Babble Error (BblErr) */
2840 __cvmx_usb_perform_complete(usb, pipe, transaction,
2841 CVMX_USB_COMPLETE_BABBLEERR);
2842 } else if (usbc_hcint.s.datatglerr) {
2843 /* Data toggle error */
2844 __cvmx_usb_perform_complete(usb, pipe, transaction,
2845 CVMX_USB_COMPLETE_DATATGLERR);
2846 } else if (usbc_hcint.s.nyet) {
2847 /*
2848 * NYET as a response is only allowed in three cases: as a
2849 * response to a ping, as a response to a split transaction, and
2850 * as a response to a bulk out. The ping case is handled by
2851 * hardware, so we only have splits and bulk out
2852 */
2853 if (!__cvmx_usb_pipe_needs_split(usb, pipe)) {
2854 transaction->retries = 0;
2855 /*
2856 * If there is more data to go then we need to try
2857 * again. Otherwise this transaction is complete
2858 */
2859 if ((buffer_space_left == 0) ||
2860 (bytes_in_last_packet < pipe->max_packet))
2861 __cvmx_usb_perform_complete(usb, pipe,
2862 transaction,
2863 CVMX_USB_COMPLETE_SUCCESS);
2864 } else {
2865 /*
2866 * Split transactions retry the split complete 4 times
2867 * then rewind to the start split and do the entire
2868 * transactions again
2869 */
2870 transaction->retries++;
2871 if ((transaction->retries & 0x3) == 0) {
2872 /*
2873 * Rewind to the beginning of the transaction by
2874 * anding off the split complete bit
2875 */
2876 transaction->stage &= ~1;
2877 pipe->split_sc_frame = -1;
2878 }
2879 }
2880 } else if (usbc_hcint.s.ack) {
2881 transaction->retries = 0;
2882 /*
2883 * The ACK bit can only be checked after the other error bits.
2884 * This is because a multi packet transfer may succeed in a
2885 * number of packets and then get a different response on the
2886 * last packet. In this case both ACK and the last response bit
2887 * will be set. If none of the other response bits is set, then
2888 * the last packet must have been an ACK
2889 *
2890 * Since we got an ACK, we know we don't need to do a ping on
2891 * this pipe
2892 */
2893 pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_NEED_PING;
2894
2895 switch (transaction->type) {
2896 case CVMX_USB_TRANSFER_CONTROL:
2897 switch (transaction->stage) {
2898 case CVMX_USB_STAGE_NON_CONTROL:
2899 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE:
2900 /* This should be impossible */
2901 __cvmx_usb_perform_complete(usb, pipe,
2902 transaction, CVMX_USB_COMPLETE_ERROR);
2903 break;
2904 case CVMX_USB_STAGE_SETUP:
2905 pipe->pid_toggle = 1;
2906 if (__cvmx_usb_pipe_needs_split(usb, pipe))
2907 transaction->stage =
2908 CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE;
2909 else {
2910 union cvmx_usb_control_header *header =
2911 cvmx_phys_to_ptr(transaction->control_header);
2912 if (header->s.length)
2913 transaction->stage = CVMX_USB_STAGE_DATA;
2914 else
2915 transaction->stage = CVMX_USB_STAGE_STATUS;
2916 }
2917 break;
2918 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE:
2919 {
2920 union cvmx_usb_control_header *header =
2921 cvmx_phys_to_ptr(transaction->control_header);
2922 if (header->s.length)
2923 transaction->stage = CVMX_USB_STAGE_DATA;
2924 else
2925 transaction->stage = CVMX_USB_STAGE_STATUS;
2926 }
2927 break;
2928 case CVMX_USB_STAGE_DATA:
2929 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
2930 transaction->stage =
2931 CVMX_USB_STAGE_DATA_SPLIT_COMPLETE;
2932 /*
2933 * For setup OUT data that are splits,
2934 * the hardware doesn't appear to count
2935 * transferred data. Here we manually
2936 * update the data transferred
2937 */
2938 if (!usbc_hcchar.s.epdir) {
2939 if (buffer_space_left < pipe->max_packet)
2940 transaction->actual_bytes +=
2941 buffer_space_left;
2942 else
2943 transaction->actual_bytes +=
2944 pipe->max_packet;
2945 }
2946 } else if ((buffer_space_left == 0) ||
2947 (bytes_in_last_packet <
2948 pipe->max_packet)) {
2949 pipe->pid_toggle = 1;
2950 transaction->stage =
2951 CVMX_USB_STAGE_STATUS;
2952 }
2953 break;
2954 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE:
2955 if ((buffer_space_left == 0) ||
2956 (bytes_in_last_packet <
2957 pipe->max_packet)) {
2958 pipe->pid_toggle = 1;
2959 transaction->stage =
2960 CVMX_USB_STAGE_STATUS;
2961 } else {
2962 transaction->stage =
2963 CVMX_USB_STAGE_DATA;
2964 }
2965 break;
2966 case CVMX_USB_STAGE_STATUS:
2967 if (__cvmx_usb_pipe_needs_split(usb, pipe))
2968 transaction->stage =
2969 CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE;
2970 else
2971 __cvmx_usb_perform_complete(usb, pipe,
2972 transaction,
2973 CVMX_USB_COMPLETE_SUCCESS);
2974 break;
2975 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE:
2976 __cvmx_usb_perform_complete(usb, pipe,
2977 transaction,
2978 CVMX_USB_COMPLETE_SUCCESS);
2979 break;
2980 }
2981 break;
2982 case CVMX_USB_TRANSFER_BULK:
2983 case CVMX_USB_TRANSFER_INTERRUPT:
2984 /*
2985 * The only time a bulk transfer isn't complete when it
2986 * finishes with an ACK is during a split transaction.
2987 * For splits we need to continue the transfer if more
2988 * data is needed
2989 */
2990 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
2991 if (transaction->stage ==
2992 CVMX_USB_STAGE_NON_CONTROL)
2993 transaction->stage =
2994 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE;
2995 else {
2996 if (buffer_space_left &&
2997 (bytes_in_last_packet ==
2998 pipe->max_packet))
2999 transaction->stage =
3000 CVMX_USB_STAGE_NON_CONTROL;
3001 else {
3002 if (transaction->type ==
3003 CVMX_USB_TRANSFER_INTERRUPT)
3004 pipe->next_tx_frame +=
3005 pipe->interval;
3006 __cvmx_usb_perform_complete(
3007 usb,
3008 pipe,
3009 transaction,
3010 CVMX_USB_COMPLETE_SUCCESS);
3011 }
3012 }
3013 } else {
3014 if ((pipe->device_speed ==
3015 CVMX_USB_SPEED_HIGH) &&
3016 (pipe->transfer_type ==
3017 CVMX_USB_TRANSFER_BULK) &&
3018 (pipe->transfer_dir ==
3019 CVMX_USB_DIRECTION_OUT) &&
3020 (usbc_hcint.s.nak))
3021 pipe->flags |=
3022 __CVMX_USB_PIPE_FLAGS_NEED_PING;
3023 if (!buffer_space_left ||
3024 (bytes_in_last_packet <
3025 pipe->max_packet)) {
3026 if (transaction->type ==
3027 CVMX_USB_TRANSFER_INTERRUPT)
3028 pipe->next_tx_frame +=
3029 pipe->interval;
3030 __cvmx_usb_perform_complete(usb,
3031 pipe,
3032 transaction,
3033 CVMX_USB_COMPLETE_SUCCESS);
3034 }
3035 }
3036 break;
3037 case CVMX_USB_TRANSFER_ISOCHRONOUS:
3038 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
3039 /*
3040 * ISOCHRONOUS OUT splits don't require a
3041 * complete split stage. Instead they use a
3042 * sequence of begin OUT splits to transfer the
3043 * data 188 bytes at a time. Once the transfer
3044 * is complete, the pipe sleeps until the next
3045 * schedule interval
3046 */
3047 if (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) {
3048 /*
3049 * If no space left or this wasn't a max
3050 * size packet then this transfer is
3051 * complete. Otherwise start it again to
3052 * send the next 188 bytes
3053 */
3054 if (!buffer_space_left ||
3055 (bytes_this_transfer < 188)) {
3056 pipe->next_tx_frame +=
3057 pipe->interval;
3058 __cvmx_usb_perform_complete(
3059 usb,
3060 pipe,
3061 transaction,
3062 CVMX_USB_COMPLETE_SUCCESS);
3063 }
3064 } else {
3065 if (transaction->stage ==
3066 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE) {
3067 /*
3068 * We are in the incoming data
3069 * phase. Keep getting data
3070 * until we run out of space or
3071 * get a small packet
3072 */
3073 if ((buffer_space_left == 0) ||
3074 (bytes_in_last_packet <
3075 pipe->max_packet)) {
3076 pipe->next_tx_frame +=
3077 pipe->interval;
3078 __cvmx_usb_perform_complete(
3079 usb,
3080 pipe,
3081 transaction,
3082 CVMX_USB_COMPLETE_SUCCESS);
3083 }
3084 } else
3085 transaction->stage =
3086 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE;
3087 }
3088 } else {
3089 pipe->next_tx_frame += pipe->interval;
3090 __cvmx_usb_perform_complete(usb,
3091 pipe,
3092 transaction,
3093 CVMX_USB_COMPLETE_SUCCESS);
3094 }
3095 break;
3096 }
3097 } else if (usbc_hcint.s.nak) {
3098 /*
3099 * If this was a split then clear our split in progress marker.
3100 */
3101 if (usb->active_split == transaction)
3102 usb->active_split = NULL;
3103 /*
3104 * NAK as a response means the device couldn't accept the
3105 * transaction, but it should be retried in the future. Rewind
3106 * to the beginning of the transaction by anding off the split
3107 * complete bit. Retry in the next interval
3108 */
3109 transaction->retries = 0;
3110 transaction->stage &= ~1;
3111 pipe->next_tx_frame += pipe->interval;
3112 if (pipe->next_tx_frame < usb->frame_number)
3113 pipe->next_tx_frame = usb->frame_number +
3114 pipe->interval -
3115 (usb->frame_number - pipe->next_tx_frame) %
3116 pipe->interval;
3117 } else {
3118 struct cvmx_usb_port_status port;
3119
3120 port = cvmx_usb_get_status(usb);
3121 if (port.port_enabled) {
3122 /* We'll retry the exact same transaction again */
3123 transaction->retries++;
3124 } else {
3125 /*
3126 * We get channel halted interrupts with no result bits
3127 * sets when the cable is unplugged
3128 */
3129 __cvmx_usb_perform_complete(usb, pipe, transaction,
3130 CVMX_USB_COMPLETE_ERROR);
3131 }
3132 }
3133 return 0;
3134 }
3135
3136 static void octeon_usb_port_callback(struct cvmx_usb_state *usb)
3137 {
3138 struct octeon_hcd *priv = cvmx_usb_to_octeon(usb);
3139
3140 spin_unlock(&priv->lock);
3141 usb_hcd_poll_rh_status(octeon_to_hcd(priv));
3142 spin_lock(&priv->lock);
3143 }
3144
3145 /**
3146 * Poll the USB block for status and call all needed callback
3147 * handlers. This function is meant to be called in the interrupt
3148 * handler for the USB controller. It can also be called
3149 * periodically in a loop for non-interrupt based operation.
3150 *
3151 * @usb: USB device state populated by cvmx_usb_initialize().
3152 *
3153 * Returns: 0 or a negative error code.
3154 */
3155 static int cvmx_usb_poll(struct cvmx_usb_state *usb)
3156 {
3157 union cvmx_usbcx_hfnum usbc_hfnum;
3158 union cvmx_usbcx_gintsts usbc_gintsts;
3159
3160 prefetch_range(usb, sizeof(*usb));
3161
3162 /* Update the frame counter */
3163 usbc_hfnum.u32 = __cvmx_usb_read_csr32(usb,
3164 CVMX_USBCX_HFNUM(usb->index));
3165 if ((usb->frame_number&0x3fff) > usbc_hfnum.s.frnum)
3166 usb->frame_number += 0x4000;
3167 usb->frame_number &= ~0x3fffull;
3168 usb->frame_number |= usbc_hfnum.s.frnum;
3169
3170 /* Read the pending interrupts */
3171 usbc_gintsts.u32 = __cvmx_usb_read_csr32(usb,
3172 CVMX_USBCX_GINTSTS(usb->index));
3173
3174 /* Clear the interrupts now that we know about them */
3175 __cvmx_usb_write_csr32(usb,
3176 CVMX_USBCX_GINTSTS(usb->index),
3177 usbc_gintsts.u32);
3178
3179 if (usbc_gintsts.s.rxflvl) {
3180 /*
3181 * RxFIFO Non-Empty (RxFLvl)
3182 * Indicates that there is at least one packet pending to be
3183 * read from the RxFIFO.
3184 *
3185 * In DMA mode this is handled by hardware
3186 */
3187 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
3188 __cvmx_usb_poll_rx_fifo(usb);
3189 }
3190 if (usbc_gintsts.s.ptxfemp || usbc_gintsts.s.nptxfemp) {
3191 /* Fill the Tx FIFOs when not in DMA mode */
3192 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
3193 __cvmx_usb_poll_tx_fifo(usb);
3194 }
3195 if (usbc_gintsts.s.disconnint || usbc_gintsts.s.prtint) {
3196 union cvmx_usbcx_hprt usbc_hprt;
3197 /*
3198 * Disconnect Detected Interrupt (DisconnInt)
3199 * Asserted when a device disconnect is detected.
3200 *
3201 * Host Port Interrupt (PrtInt)
3202 * The core sets this bit to indicate a change in port status of
3203 * one of the O2P USB core ports in Host mode. The application
3204 * must read the Host Port Control and Status (HPRT) register to
3205 * determine the exact event that caused this interrupt. The
3206 * application must clear the appropriate status bit in the Host
3207 * Port Control and Status register to clear this bit.
3208 *
3209 * Call the user's port callback
3210 */
3211 octeon_usb_port_callback(usb);
3212 /* Clear the port change bits */
3213 usbc_hprt.u32 = __cvmx_usb_read_csr32(usb,
3214 CVMX_USBCX_HPRT(usb->index));
3215 usbc_hprt.s.prtena = 0;
3216 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HPRT(usb->index),
3217 usbc_hprt.u32);
3218 }
3219 if (usbc_gintsts.s.hchint) {
3220 /*
3221 * Host Channels Interrupt (HChInt)
3222 * The core sets this bit to indicate that an interrupt is
3223 * pending on one of the channels of the core (in Host mode).
3224 * The application must read the Host All Channels Interrupt
3225 * (HAINT) register to determine the exact number of the channel
3226 * on which the interrupt occurred, and then read the
3227 * corresponding Host Channel-n Interrupt (HCINTn) register to
3228 * determine the exact cause of the interrupt. The application
3229 * must clear the appropriate status bit in the HCINTn register
3230 * to clear this bit.
3231 */
3232 union cvmx_usbcx_haint usbc_haint;
3233
3234 usbc_haint.u32 = __cvmx_usb_read_csr32(usb,
3235 CVMX_USBCX_HAINT(usb->index));
3236 while (usbc_haint.u32) {
3237 int channel;
3238
3239 channel = __fls(usbc_haint.u32);
3240 __cvmx_usb_poll_channel(usb, channel);
3241 usbc_haint.u32 ^= 1<<channel;
3242 }
3243 }
3244
3245 __cvmx_usb_schedule(usb, usbc_gintsts.s.sof);
3246
3247 return 0;
3248 }
3249
3250 /* convert between an HCD pointer and the corresponding struct octeon_hcd */
3251 static inline struct octeon_hcd *hcd_to_octeon(struct usb_hcd *hcd)
3252 {
3253 return (struct octeon_hcd *)(hcd->hcd_priv);
3254 }
3255
3256 static irqreturn_t octeon_usb_irq(struct usb_hcd *hcd)
3257 {
3258 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3259 unsigned long flags;
3260
3261 spin_lock_irqsave(&priv->lock, flags);
3262 cvmx_usb_poll(&priv->usb);
3263 spin_unlock_irqrestore(&priv->lock, flags);
3264 return IRQ_HANDLED;
3265 }
3266
3267 static int octeon_usb_start(struct usb_hcd *hcd)
3268 {
3269 hcd->state = HC_STATE_RUNNING;
3270 return 0;
3271 }
3272
3273 static void octeon_usb_stop(struct usb_hcd *hcd)
3274 {
3275 hcd->state = HC_STATE_HALT;
3276 }
3277
3278 static int octeon_usb_get_frame_number(struct usb_hcd *hcd)
3279 {
3280 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3281
3282 return cvmx_usb_get_frame_number(&priv->usb);
3283 }
3284
3285 static int octeon_usb_urb_enqueue(struct usb_hcd *hcd,
3286 struct urb *urb,
3287 gfp_t mem_flags)
3288 {
3289 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3290 struct device *dev = hcd->self.controller;
3291 struct cvmx_usb_transaction *transaction = NULL;
3292 struct cvmx_usb_pipe *pipe;
3293 unsigned long flags;
3294 struct cvmx_usb_iso_packet *iso_packet;
3295 struct usb_host_endpoint *ep = urb->ep;
3296 int rc;
3297
3298 urb->status = 0;
3299 spin_lock_irqsave(&priv->lock, flags);
3300
3301 rc = usb_hcd_link_urb_to_ep(hcd, urb);
3302 if (rc) {
3303 spin_unlock_irqrestore(&priv->lock, flags);
3304 return rc;
3305 }
3306
3307 if (!ep->hcpriv) {
3308 enum cvmx_usb_transfer transfer_type;
3309 enum cvmx_usb_speed speed;
3310 int split_device = 0;
3311 int split_port = 0;
3312
3313 switch (usb_pipetype(urb->pipe)) {
3314 case PIPE_ISOCHRONOUS:
3315 transfer_type = CVMX_USB_TRANSFER_ISOCHRONOUS;
3316 break;
3317 case PIPE_INTERRUPT:
3318 transfer_type = CVMX_USB_TRANSFER_INTERRUPT;
3319 break;
3320 case PIPE_CONTROL:
3321 transfer_type = CVMX_USB_TRANSFER_CONTROL;
3322 break;
3323 default:
3324 transfer_type = CVMX_USB_TRANSFER_BULK;
3325 break;
3326 }
3327 switch (urb->dev->speed) {
3328 case USB_SPEED_LOW:
3329 speed = CVMX_USB_SPEED_LOW;
3330 break;
3331 case USB_SPEED_FULL:
3332 speed = CVMX_USB_SPEED_FULL;
3333 break;
3334 default:
3335 speed = CVMX_USB_SPEED_HIGH;
3336 break;
3337 }
3338 /*
3339 * For slow devices on high speed ports we need to find the hub
3340 * that does the speed translation so we know where to send the
3341 * split transactions.
3342 */
3343 if (speed != CVMX_USB_SPEED_HIGH) {
3344 /*
3345 * Start at this device and work our way up the usb
3346 * tree.
3347 */
3348 struct usb_device *dev = urb->dev;
3349
3350 while (dev->parent) {
3351 /*
3352 * If our parent is high speed then he'll
3353 * receive the splits.
3354 */
3355 if (dev->parent->speed == USB_SPEED_HIGH) {
3356 split_device = dev->parent->devnum;
3357 split_port = dev->portnum;
3358 break;
3359 }
3360 /*
3361 * Move up the tree one level. If we make it all
3362 * the way up the tree, then the port must not
3363 * be in high speed mode and we don't need a
3364 * split.
3365 */
3366 dev = dev->parent;
3367 }
3368 }
3369 pipe = cvmx_usb_open_pipe(&priv->usb, usb_pipedevice(urb->pipe),
3370 usb_pipeendpoint(urb->pipe), speed,
3371 le16_to_cpu(ep->desc.wMaxPacketSize)
3372 & 0x7ff,
3373 transfer_type,
3374 usb_pipein(urb->pipe) ?
3375 CVMX_USB_DIRECTION_IN :
3376 CVMX_USB_DIRECTION_OUT,
3377 urb->interval,
3378 (le16_to_cpu(ep->desc.wMaxPacketSize)
3379 >> 11) & 0x3,
3380 split_device, split_port);
3381 if (!pipe) {
3382 usb_hcd_unlink_urb_from_ep(hcd, urb);
3383 spin_unlock_irqrestore(&priv->lock, flags);
3384 dev_dbg(dev, "Failed to create pipe\n");
3385 return -ENOMEM;
3386 }
3387 ep->hcpriv = pipe;
3388 } else {
3389 pipe = ep->hcpriv;
3390 }
3391
3392 switch (usb_pipetype(urb->pipe)) {
3393 case PIPE_ISOCHRONOUS:
3394 dev_dbg(dev, "Submit isochronous to %d.%d\n",
3395 usb_pipedevice(urb->pipe),
3396 usb_pipeendpoint(urb->pipe));
3397 /*
3398 * Allocate a structure to use for our private list of
3399 * isochronous packets.
3400 */
3401 iso_packet = kmalloc(urb->number_of_packets *
3402 sizeof(struct cvmx_usb_iso_packet),
3403 GFP_ATOMIC);
3404 if (iso_packet) {
3405 int i;
3406 /* Fill the list with the data from the URB */
3407 for (i = 0; i < urb->number_of_packets; i++) {
3408 iso_packet[i].offset =
3409 urb->iso_frame_desc[i].offset;
3410 iso_packet[i].length =
3411 urb->iso_frame_desc[i].length;
3412 iso_packet[i].status =
3413 CVMX_USB_COMPLETE_ERROR;
3414 }
3415 /*
3416 * Store a pointer to the list in the URB setup_packet
3417 * field. We know this currently isn't being used and
3418 * this saves us a bunch of logic.
3419 */
3420 urb->setup_packet = (char *)iso_packet;
3421 transaction = cvmx_usb_submit_isochronous(&priv->usb,
3422 pipe, urb);
3423 /*
3424 * If submit failed we need to free our private packet
3425 * list.
3426 */
3427 if (!transaction) {
3428 urb->setup_packet = NULL;
3429 kfree(iso_packet);
3430 }
3431 }
3432 break;
3433 case PIPE_INTERRUPT:
3434 dev_dbg(dev, "Submit interrupt to %d.%d\n",
3435 usb_pipedevice(urb->pipe),
3436 usb_pipeendpoint(urb->pipe));
3437 transaction = cvmx_usb_submit_interrupt(&priv->usb, pipe, urb);
3438 break;
3439 case PIPE_CONTROL:
3440 dev_dbg(dev, "Submit control to %d.%d\n",
3441 usb_pipedevice(urb->pipe),
3442 usb_pipeendpoint(urb->pipe));
3443 transaction = cvmx_usb_submit_control(&priv->usb, pipe, urb);
3444 break;
3445 case PIPE_BULK:
3446 dev_dbg(dev, "Submit bulk to %d.%d\n",
3447 usb_pipedevice(urb->pipe),
3448 usb_pipeendpoint(urb->pipe));
3449 transaction = cvmx_usb_submit_bulk(&priv->usb, pipe, urb);
3450 break;
3451 }
3452 if (!transaction) {
3453 usb_hcd_unlink_urb_from_ep(hcd, urb);
3454 spin_unlock_irqrestore(&priv->lock, flags);
3455 dev_dbg(dev, "Failed to submit\n");
3456 return -ENOMEM;
3457 }
3458 urb->hcpriv = transaction;
3459 spin_unlock_irqrestore(&priv->lock, flags);
3460 return 0;
3461 }
3462
3463 static int octeon_usb_urb_dequeue(struct usb_hcd *hcd,
3464 struct urb *urb,
3465 int status)
3466 {
3467 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3468 unsigned long flags;
3469 int rc;
3470
3471 if (!urb->dev)
3472 return -EINVAL;
3473
3474 spin_lock_irqsave(&priv->lock, flags);
3475
3476 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
3477 if (rc)
3478 goto out;
3479
3480 urb->status = status;
3481 cvmx_usb_cancel(&priv->usb, urb->ep->hcpriv, urb->hcpriv);
3482
3483 out:
3484 spin_unlock_irqrestore(&priv->lock, flags);
3485
3486 return rc;
3487 }
3488
3489 static void octeon_usb_endpoint_disable(struct usb_hcd *hcd,
3490 struct usb_host_endpoint *ep)
3491 {
3492 struct device *dev = hcd->self.controller;
3493
3494 if (ep->hcpriv) {
3495 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3496 struct cvmx_usb_pipe *pipe = ep->hcpriv;
3497 unsigned long flags;
3498
3499 spin_lock_irqsave(&priv->lock, flags);
3500 cvmx_usb_cancel_all(&priv->usb, pipe);
3501 if (cvmx_usb_close_pipe(&priv->usb, pipe))
3502 dev_dbg(dev, "Closing pipe %p failed\n", pipe);
3503 spin_unlock_irqrestore(&priv->lock, flags);
3504 ep->hcpriv = NULL;
3505 }
3506 }
3507
3508 static int octeon_usb_hub_status_data(struct usb_hcd *hcd, char *buf)
3509 {
3510 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3511 struct cvmx_usb_port_status port_status;
3512 unsigned long flags;
3513
3514 spin_lock_irqsave(&priv->lock, flags);
3515 port_status = cvmx_usb_get_status(&priv->usb);
3516 spin_unlock_irqrestore(&priv->lock, flags);
3517 buf[0] = 0;
3518 buf[0] = port_status.connect_change << 1;
3519
3520 return buf[0] != 0;
3521 }
3522
3523 static int octeon_usb_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
3524 u16 wIndex, char *buf, u16 wLength)
3525 {
3526 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3527 struct device *dev = hcd->self.controller;
3528 struct cvmx_usb_port_status usb_port_status;
3529 int port_status;
3530 struct usb_hub_descriptor *desc;
3531 unsigned long flags;
3532
3533 switch (typeReq) {
3534 case ClearHubFeature:
3535 dev_dbg(dev, "ClearHubFeature\n");
3536 switch (wValue) {
3537 case C_HUB_LOCAL_POWER:
3538 case C_HUB_OVER_CURRENT:
3539 /* Nothing required here */
3540 break;
3541 default:
3542 return -EINVAL;
3543 }
3544 break;
3545 case ClearPortFeature:
3546 dev_dbg(dev, "ClearPortFeature\n");
3547 if (wIndex != 1) {
3548 dev_dbg(dev, " INVALID\n");
3549 return -EINVAL;
3550 }
3551
3552 switch (wValue) {
3553 case USB_PORT_FEAT_ENABLE:
3554 dev_dbg(dev, " ENABLE\n");
3555 spin_lock_irqsave(&priv->lock, flags);
3556 cvmx_usb_disable(&priv->usb);
3557 spin_unlock_irqrestore(&priv->lock, flags);
3558 break;
3559 case USB_PORT_FEAT_SUSPEND:
3560 dev_dbg(dev, " SUSPEND\n");
3561 /* Not supported on Octeon */
3562 break;
3563 case USB_PORT_FEAT_POWER:
3564 dev_dbg(dev, " POWER\n");
3565 /* Not supported on Octeon */
3566 break;
3567 case USB_PORT_FEAT_INDICATOR:
3568 dev_dbg(dev, " INDICATOR\n");
3569 /* Port inidicator not supported */
3570 break;
3571 case USB_PORT_FEAT_C_CONNECTION:
3572 dev_dbg(dev, " C_CONNECTION\n");
3573 /* Clears drivers internal connect status change flag */
3574 spin_lock_irqsave(&priv->lock, flags);
3575 priv->usb.port_status =
3576 cvmx_usb_get_status(&priv->usb);
3577 spin_unlock_irqrestore(&priv->lock, flags);
3578 break;
3579 case USB_PORT_FEAT_C_RESET:
3580 dev_dbg(dev, " C_RESET\n");
3581 /*
3582 * Clears the driver's internal Port Reset Change flag.
3583 */
3584 spin_lock_irqsave(&priv->lock, flags);
3585 priv->usb.port_status =
3586 cvmx_usb_get_status(&priv->usb);
3587 spin_unlock_irqrestore(&priv->lock, flags);
3588 break;
3589 case USB_PORT_FEAT_C_ENABLE:
3590 dev_dbg(dev, " C_ENABLE\n");
3591 /*
3592 * Clears the driver's internal Port Enable/Disable
3593 * Change flag.
3594 */
3595 spin_lock_irqsave(&priv->lock, flags);
3596 priv->usb.port_status =
3597 cvmx_usb_get_status(&priv->usb);
3598 spin_unlock_irqrestore(&priv->lock, flags);
3599 break;
3600 case USB_PORT_FEAT_C_SUSPEND:
3601 dev_dbg(dev, " C_SUSPEND\n");
3602 /*
3603 * Clears the driver's internal Port Suspend Change
3604 * flag, which is set when resume signaling on the host
3605 * port is complete.
3606 */
3607 break;
3608 case USB_PORT_FEAT_C_OVER_CURRENT:
3609 dev_dbg(dev, " C_OVER_CURRENT\n");
3610 /* Clears the driver's overcurrent Change flag */
3611 spin_lock_irqsave(&priv->lock, flags);
3612 priv->usb.port_status =
3613 cvmx_usb_get_status(&priv->usb);
3614 spin_unlock_irqrestore(&priv->lock, flags);
3615 break;
3616 default:
3617 dev_dbg(dev, " UNKNOWN\n");
3618 return -EINVAL;
3619 }
3620 break;
3621 case GetHubDescriptor:
3622 dev_dbg(dev, "GetHubDescriptor\n");
3623 desc = (struct usb_hub_descriptor *)buf;
3624 desc->bDescLength = 9;
3625 desc->bDescriptorType = 0x29;
3626 desc->bNbrPorts = 1;
3627 desc->wHubCharacteristics = 0x08;
3628 desc->bPwrOn2PwrGood = 1;
3629 desc->bHubContrCurrent = 0;
3630 desc->u.hs.DeviceRemovable[0] = 0;
3631 desc->u.hs.DeviceRemovable[1] = 0xff;
3632 break;
3633 case GetHubStatus:
3634 dev_dbg(dev, "GetHubStatus\n");
3635 *(__le32 *) buf = 0;
3636 break;
3637 case GetPortStatus:
3638 dev_dbg(dev, "GetPortStatus\n");
3639 if (wIndex != 1) {
3640 dev_dbg(dev, " INVALID\n");
3641 return -EINVAL;
3642 }
3643
3644 spin_lock_irqsave(&priv->lock, flags);
3645 usb_port_status = cvmx_usb_get_status(&priv->usb);
3646 spin_unlock_irqrestore(&priv->lock, flags);
3647 port_status = 0;
3648
3649 if (usb_port_status.connect_change) {
3650 port_status |= (1 << USB_PORT_FEAT_C_CONNECTION);
3651 dev_dbg(dev, " C_CONNECTION\n");
3652 }
3653
3654 if (usb_port_status.port_enabled) {
3655 port_status |= (1 << USB_PORT_FEAT_C_ENABLE);
3656 dev_dbg(dev, " C_ENABLE\n");
3657 }
3658
3659 if (usb_port_status.connected) {
3660 port_status |= (1 << USB_PORT_FEAT_CONNECTION);
3661 dev_dbg(dev, " CONNECTION\n");
3662 }
3663
3664 if (usb_port_status.port_enabled) {
3665 port_status |= (1 << USB_PORT_FEAT_ENABLE);
3666 dev_dbg(dev, " ENABLE\n");
3667 }
3668
3669 if (usb_port_status.port_over_current) {
3670 port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT);
3671 dev_dbg(dev, " OVER_CURRENT\n");
3672 }
3673
3674 if (usb_port_status.port_powered) {
3675 port_status |= (1 << USB_PORT_FEAT_POWER);
3676 dev_dbg(dev, " POWER\n");
3677 }
3678
3679 if (usb_port_status.port_speed == CVMX_USB_SPEED_HIGH) {
3680 port_status |= USB_PORT_STAT_HIGH_SPEED;
3681 dev_dbg(dev, " HIGHSPEED\n");
3682 } else if (usb_port_status.port_speed == CVMX_USB_SPEED_LOW) {
3683 port_status |= (1 << USB_PORT_FEAT_LOWSPEED);
3684 dev_dbg(dev, " LOWSPEED\n");
3685 }
3686
3687 *((__le32 *) buf) = cpu_to_le32(port_status);
3688 break;
3689 case SetHubFeature:
3690 dev_dbg(dev, "SetHubFeature\n");
3691 /* No HUB features supported */
3692 break;
3693 case SetPortFeature:
3694 dev_dbg(dev, "SetPortFeature\n");
3695 if (wIndex != 1) {
3696 dev_dbg(dev, " INVALID\n");
3697 return -EINVAL;
3698 }
3699
3700 switch (wValue) {
3701 case USB_PORT_FEAT_SUSPEND:
3702 dev_dbg(dev, " SUSPEND\n");
3703 return -EINVAL;
3704 case USB_PORT_FEAT_POWER:
3705 dev_dbg(dev, " POWER\n");
3706 return -EINVAL;
3707 case USB_PORT_FEAT_RESET:
3708 dev_dbg(dev, " RESET\n");
3709 spin_lock_irqsave(&priv->lock, flags);
3710 cvmx_usb_disable(&priv->usb);
3711 if (cvmx_usb_enable(&priv->usb))
3712 dev_dbg(dev, "Failed to enable the port\n");
3713 spin_unlock_irqrestore(&priv->lock, flags);
3714 return 0;
3715 case USB_PORT_FEAT_INDICATOR:
3716 dev_dbg(dev, " INDICATOR\n");
3717 /* Not supported */
3718 break;
3719 default:
3720 dev_dbg(dev, " UNKNOWN\n");
3721 return -EINVAL;
3722 }
3723 break;
3724 default:
3725 dev_dbg(dev, "Unknown root hub request\n");
3726 return -EINVAL;
3727 }
3728 return 0;
3729 }
3730
3731 static const struct hc_driver octeon_hc_driver = {
3732 .description = "Octeon USB",
3733 .product_desc = "Octeon Host Controller",
3734 .hcd_priv_size = sizeof(struct octeon_hcd),
3735 .irq = octeon_usb_irq,
3736 .flags = HCD_MEMORY | HCD_USB2,
3737 .start = octeon_usb_start,
3738 .stop = octeon_usb_stop,
3739 .urb_enqueue = octeon_usb_urb_enqueue,
3740 .urb_dequeue = octeon_usb_urb_dequeue,
3741 .endpoint_disable = octeon_usb_endpoint_disable,
3742 .get_frame_number = octeon_usb_get_frame_number,
3743 .hub_status_data = octeon_usb_hub_status_data,
3744 .hub_control = octeon_usb_hub_control,
3745 .map_urb_for_dma = octeon_map_urb_for_dma,
3746 .unmap_urb_for_dma = octeon_unmap_urb_for_dma,
3747 };
3748
3749 static int octeon_usb_probe(struct platform_device *pdev)
3750 {
3751 int status;
3752 int initialize_flags;
3753 int usb_num;
3754 struct resource *res_mem;
3755 struct device_node *usbn_node;
3756 int irq = platform_get_irq(pdev, 0);
3757 struct device *dev = &pdev->dev;
3758 struct octeon_hcd *priv;
3759 struct usb_hcd *hcd;
3760 unsigned long flags;
3761 u32 clock_rate = 48000000;
3762 bool is_crystal_clock = false;
3763 const char *clock_type;
3764 int i;
3765
3766 if (dev->of_node == NULL) {
3767 dev_err(dev, "Error: empty of_node\n");
3768 return -ENXIO;
3769 }
3770 usbn_node = dev->of_node->parent;
3771
3772 i = of_property_read_u32(usbn_node,
3773 "refclk-frequency", &clock_rate);
3774 if (i) {
3775 dev_err(dev, "No USBN \"refclk-frequency\"\n");
3776 return -ENXIO;
3777 }
3778 switch (clock_rate) {
3779 case 12000000:
3780 initialize_flags = CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ;
3781 break;
3782 case 24000000:
3783 initialize_flags = CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ;
3784 break;
3785 case 48000000:
3786 initialize_flags = CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ;
3787 break;
3788 default:
3789 dev_err(dev, "Illebal USBN \"refclk-frequency\" %u\n",
3790 clock_rate);
3791 return -ENXIO;
3792
3793 }
3794
3795 i = of_property_read_string(usbn_node,
3796 "refclk-type", &clock_type);
3797
3798 if (!i && strcmp("crystal", clock_type) == 0)
3799 is_crystal_clock = true;
3800
3801 if (is_crystal_clock)
3802 initialize_flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI;
3803 else
3804 initialize_flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND;
3805
3806 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3807 if (res_mem == NULL) {
3808 dev_err(dev, "found no memory resource\n");
3809 return -ENXIO;
3810 }
3811 usb_num = (res_mem->start >> 44) & 1;
3812
3813 if (irq < 0) {
3814 /* Defective device tree, but we know how to fix it. */
3815 irq_hw_number_t hwirq = usb_num ? (1 << 6) + 17 : 56;
3816
3817 irq = irq_create_mapping(NULL, hwirq);
3818 }
3819
3820 /*
3821 * Set the DMA mask to 64bits so we get buffers already translated for
3822 * DMA.
3823 */
3824 dev->coherent_dma_mask = ~0;
3825 dev->dma_mask = &dev->coherent_dma_mask;
3826
3827 /*
3828 * Only cn52XX and cn56XX have DWC_OTG USB hardware and the
3829 * IOB priority registers. Under heavy network load USB
3830 * hardware can be starved by the IOB causing a crash. Give
3831 * it a priority boost if it has been waiting more than 400
3832 * cycles to avoid this situation.
3833 *
3834 * Testing indicates that a cnt_val of 8192 is not sufficient,
3835 * but no failures are seen with 4096. We choose a value of
3836 * 400 to give a safety factor of 10.
3837 */
3838 if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) {
3839 union cvmx_iob_n2c_l2c_pri_cnt pri_cnt;
3840
3841 pri_cnt.u64 = 0;
3842 pri_cnt.s.cnt_enb = 1;
3843 pri_cnt.s.cnt_val = 400;
3844 cvmx_write_csr(CVMX_IOB_N2C_L2C_PRI_CNT, pri_cnt.u64);
3845 }
3846
3847 hcd = usb_create_hcd(&octeon_hc_driver, dev, dev_name(dev));
3848 if (!hcd) {
3849 dev_dbg(dev, "Failed to allocate memory for HCD\n");
3850 return -1;
3851 }
3852 hcd->uses_new_polling = 1;
3853 priv = (struct octeon_hcd *)hcd->hcd_priv;
3854
3855 spin_lock_init(&priv->lock);
3856
3857 status = cvmx_usb_initialize(&priv->usb, usb_num, initialize_flags);
3858 if (status) {
3859 dev_dbg(dev, "USB initialization failed with %d\n", status);
3860 kfree(hcd);
3861 return -1;
3862 }
3863
3864 /* This delay is needed for CN3010, but I don't know why... */
3865 mdelay(10);
3866
3867 spin_lock_irqsave(&priv->lock, flags);
3868 cvmx_usb_poll(&priv->usb);
3869 spin_unlock_irqrestore(&priv->lock, flags);
3870
3871 status = usb_add_hcd(hcd, irq, 0);
3872 if (status) {
3873 dev_dbg(dev, "USB add HCD failed with %d\n", status);
3874 kfree(hcd);
3875 return -1;
3876 }
3877 device_wakeup_enable(hcd->self.controller);
3878
3879 dev_info(dev, "Registered HCD for port %d on irq %d\n", usb_num, irq);
3880
3881 return 0;
3882 }
3883
3884 static int octeon_usb_remove(struct platform_device *pdev)
3885 {
3886 int status;
3887 struct device *dev = &pdev->dev;
3888 struct usb_hcd *hcd = dev_get_drvdata(dev);
3889 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3890 unsigned long flags;
3891
3892 usb_remove_hcd(hcd);
3893 spin_lock_irqsave(&priv->lock, flags);
3894 status = cvmx_usb_shutdown(&priv->usb);
3895 spin_unlock_irqrestore(&priv->lock, flags);
3896 if (status)
3897 dev_dbg(dev, "USB shutdown failed with %d\n", status);
3898
3899 kfree(hcd);
3900
3901 return 0;
3902 }
3903
3904 static struct of_device_id octeon_usb_match[] = {
3905 {
3906 .compatible = "cavium,octeon-5750-usbc",
3907 },
3908 {},
3909 };
3910
3911 static struct platform_driver octeon_usb_driver = {
3912 .driver = {
3913 .name = "OcteonUSB",
3914 .owner = THIS_MODULE,
3915 .of_match_table = octeon_usb_match,
3916 },
3917 .probe = octeon_usb_probe,
3918 .remove = octeon_usb_remove,
3919 };
3920
3921 static int __init octeon_usb_driver_init(void)
3922 {
3923 if (usb_disabled())
3924 return 0;
3925
3926 return platform_driver_register(&octeon_usb_driver);
3927 }
3928 module_init(octeon_usb_driver_init);
3929
3930 static void __exit octeon_usb_driver_exit(void)
3931 {
3932 if (usb_disabled())
3933 return;
3934
3935 platform_driver_unregister(&octeon_usb_driver);
3936 }
3937 module_exit(octeon_usb_driver_exit);
3938
3939 MODULE_LICENSE("GPL");
3940 MODULE_AUTHOR("Cavium, Inc. <support@cavium.com>");
3941 MODULE_DESCRIPTION("Cavium Inc. OCTEON USB Host driver.");
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