2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2008 Cavium Networks
8 * Some parts of the code were originally released under BSD license:
10 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions are
17 * * Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
20 * * Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials provided
23 * with the distribution.
25 * * Neither the name of Cavium Networks nor the names of
26 * its contributors may be used to endorse or promote products
27 * derived from this software without specific prior written
30 * This Software, including technical data, may be subject to U.S. export
31 * control laws, including the U.S. Export Administration Act and its associated
32 * regulations, and may be subject to export or import regulations in other
35 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
36 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
37 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
38 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION
39 * OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
40 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
41 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
42 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
43 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
44 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
46 #include <linux/kernel.h>
47 #include <linux/module.h>
48 #include <linux/init.h>
49 #include <linux/pci.h>
50 #include <linux/prefetch.h>
51 #include <linux/interrupt.h>
52 #include <linux/platform_device.h>
53 #include <linux/usb.h>
55 #include <linux/time.h>
56 #include <linux/delay.h>
58 #include <asm/octeon/cvmx.h>
59 #include <asm/octeon/cvmx-iob-defs.h>
61 #include <linux/usb/hcd.h>
63 #include <linux/err.h>
65 #include <asm/octeon/octeon.h>
66 #include <asm/octeon/cvmx-helper.h>
67 #include <asm/octeon/cvmx-sysinfo.h>
68 #include <asm/octeon/cvmx-helper-board.h>
70 #include "octeon-hcd.h"
73 * enum cvmx_usb_speed - the possible USB device speeds
75 * @CVMX_USB_SPEED_HIGH: Device is operation at 480Mbps
76 * @CVMX_USB_SPEED_FULL: Device is operation at 12Mbps
77 * @CVMX_USB_SPEED_LOW: Device is operation at 1.5Mbps
80 CVMX_USB_SPEED_HIGH
= 0,
81 CVMX_USB_SPEED_FULL
= 1,
82 CVMX_USB_SPEED_LOW
= 2,
86 * enum cvmx_usb_transfer - the possible USB transfer types
88 * @CVMX_USB_TRANSFER_CONTROL: USB transfer type control for hub and status
90 * @CVMX_USB_TRANSFER_ISOCHRONOUS: USB transfer type isochronous for low
91 * priority periodic transfers
92 * @CVMX_USB_TRANSFER_BULK: USB transfer type bulk for large low priority
94 * @CVMX_USB_TRANSFER_INTERRUPT: USB transfer type interrupt for high priority
97 enum cvmx_usb_transfer
{
98 CVMX_USB_TRANSFER_CONTROL
= 0,
99 CVMX_USB_TRANSFER_ISOCHRONOUS
= 1,
100 CVMX_USB_TRANSFER_BULK
= 2,
101 CVMX_USB_TRANSFER_INTERRUPT
= 3,
105 * enum cvmx_usb_direction - the transfer directions
107 * @CVMX_USB_DIRECTION_OUT: Data is transferring from Octeon to the device/host
108 * @CVMX_USB_DIRECTION_IN: Data is transferring from the device/host to Octeon
110 enum cvmx_usb_direction
{
111 CVMX_USB_DIRECTION_OUT
,
112 CVMX_USB_DIRECTION_IN
,
116 * enum cvmx_usb_complete - possible callback function status codes
118 * @CVMX_USB_COMPLETE_SUCCESS: The transaction / operation finished without
120 * @CVMX_USB_COMPLETE_SHORT: FIXME: This is currently not implemented
121 * @CVMX_USB_COMPLETE_CANCEL: The transaction was canceled while in flight
122 * by a user call to cvmx_usb_cancel
123 * @CVMX_USB_COMPLETE_ERROR: The transaction aborted with an unexpected
125 * @CVMX_USB_COMPLETE_STALL: The transaction received a USB STALL response
127 * @CVMX_USB_COMPLETE_XACTERR: The transaction failed with an error from the
128 * device even after a number of retries
129 * @CVMX_USB_COMPLETE_DATATGLERR: The transaction failed with a data toggle
130 * error even after a number of retries
131 * @CVMX_USB_COMPLETE_BABBLEERR: The transaction failed with a babble error
132 * @CVMX_USB_COMPLETE_FRAMEERR: The transaction failed with a frame error
133 * even after a number of retries
135 enum cvmx_usb_complete
{
136 CVMX_USB_COMPLETE_SUCCESS
,
137 CVMX_USB_COMPLETE_SHORT
,
138 CVMX_USB_COMPLETE_CANCEL
,
139 CVMX_USB_COMPLETE_ERROR
,
140 CVMX_USB_COMPLETE_STALL
,
141 CVMX_USB_COMPLETE_XACTERR
,
142 CVMX_USB_COMPLETE_DATATGLERR
,
143 CVMX_USB_COMPLETE_BABBLEERR
,
144 CVMX_USB_COMPLETE_FRAMEERR
,
148 * struct cvmx_usb_port_status - the USB port status information
150 * @port_enabled: 1 = Usb port is enabled, 0 = disabled
151 * @port_over_current: 1 = Over current detected, 0 = Over current not
152 * detected. Octeon doesn't support over current detection.
153 * @port_powered: 1 = Port power is being supplied to the device, 0 =
154 * power is off. Octeon doesn't support turning port power
156 * @port_speed: Current port speed.
157 * @connected: 1 = A device is connected to the port, 0 = No device is
159 * @connect_change: 1 = Device connected state changed since the last set
162 struct cvmx_usb_port_status
{
163 uint32_t reserved
: 25;
164 uint32_t port_enabled
: 1;
165 uint32_t port_over_current
: 1;
166 uint32_t port_powered
: 1;
167 enum cvmx_usb_speed port_speed
: 2;
168 uint32_t connected
: 1;
169 uint32_t connect_change
: 1;
173 * struct cvmx_usb_iso_packet - descriptor for Isochronous packets
175 * @offset: This is the offset in bytes into the main buffer where this data
177 * @length: This is the length in bytes of the data.
178 * @status: This is the status of this individual packet transfer.
180 struct cvmx_usb_iso_packet
{
183 enum cvmx_usb_complete status
;
187 * enum cvmx_usb_initialize_flags - flags used by the initialization function
189 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI: The USB port uses a 12MHz crystal
190 * as clock source at USB_XO and
192 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND: The USB port uses 12/24/48MHz 2.5V
193 * board clock source at USB_XO.
194 * USB_XI should be tied to GND.
195 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK: Mask for clock speed field
196 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ: Speed of reference clock or
198 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ: Speed of reference clock
199 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ: Speed of reference clock
200 * @CVMX_USB_INITIALIZE_FLAGS_NO_DMA: Disable DMA and used polled IO for
201 * data transfer use for the USB
203 enum cvmx_usb_initialize_flags
{
204 CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI
= 1 << 0,
205 CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND
= 1 << 1,
206 CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK
= 3 << 3,
207 CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ
= 1 << 3,
208 CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ
= 2 << 3,
209 CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ
= 3 << 3,
210 /* Bits 3-4 used to encode the clock frequency */
211 CVMX_USB_INITIALIZE_FLAGS_NO_DMA
= 1 << 5,
215 * enum cvmx_usb_pipe_flags - internal flags for a pipe.
217 * @CVMX_USB_PIPE_FLAGS_SCHEDULED: Used internally to determine if a pipe is
218 * actively using hardware.
219 * @CVMX_USB_PIPE_FLAGS_NEED_PING: Used internally to determine if a high speed
220 * pipe is in the ping state.
222 enum cvmx_usb_pipe_flags
{
223 CVMX_USB_PIPE_FLAGS_SCHEDULED
= 1 << 17,
224 CVMX_USB_PIPE_FLAGS_NEED_PING
= 1 << 18,
227 /* Maximum number of times to retry failed transactions */
228 #define MAX_RETRIES 3
230 /* Maximum number of hardware channels supported by the USB block */
231 #define MAX_CHANNELS 8
234 * The low level hardware can transfer a maximum of this number of bytes in each
235 * transfer. The field is 19 bits wide
237 #define MAX_TRANSFER_BYTES ((1<<19)-1)
240 * The low level hardware can transfer a maximum of this number of packets in
241 * each transfer. The field is 10 bits wide
243 #define MAX_TRANSFER_PACKETS ((1<<10)-1)
246 * Logical transactions may take numerous low level
247 * transactions, especially when splits are concerned. This
248 * enum represents all of the possible stages a transaction can
249 * be in. Note that split completes are always even. This is so
250 * the NAK handler can backup to the previous low level
251 * transaction with a simple clearing of bit 0.
253 enum cvmx_usb_stage
{
254 CVMX_USB_STAGE_NON_CONTROL
,
255 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
,
256 CVMX_USB_STAGE_SETUP
,
257 CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE
,
259 CVMX_USB_STAGE_DATA_SPLIT_COMPLETE
,
260 CVMX_USB_STAGE_STATUS
,
261 CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE
,
265 * struct cvmx_usb_transaction - describes each pending USB transaction
266 * regardless of type. These are linked together
267 * to form a list of pending requests for a pipe.
269 * @node: List node for transactions in the pipe.
270 * @type: Type of transaction, duplicated of the pipe.
271 * @flags: State flags for this transaction.
272 * @buffer: User's physical buffer address to read/write.
273 * @buffer_length: Size of the user's buffer in bytes.
274 * @control_header: For control transactions, physical address of the 8
275 * byte standard header.
276 * @iso_start_frame: For ISO transactions, the starting frame number.
277 * @iso_number_packets: For ISO transactions, the number of packets in the
279 * @iso_packets: For ISO transactions, the sub packets in the request.
280 * @actual_bytes: Actual bytes transfer for this transaction.
281 * @stage: For control transactions, the current stage.
284 struct cvmx_usb_transaction
{
285 struct list_head node
;
286 enum cvmx_usb_transfer type
;
289 uint64_t control_header
;
291 int iso_number_packets
;
292 struct cvmx_usb_iso_packet
*iso_packets
;
297 enum cvmx_usb_stage stage
;
302 * struct cvmx_usb_pipe - a pipe represents a virtual connection between Octeon
303 * and some USB device. It contains a list of pending
304 * request to the device.
306 * @node: List node for pipe list
307 * @next: Pipe after this one in the list
308 * @transactions: List of pending transactions
309 * @interval: For periodic pipes, the interval between packets in
311 * @next_tx_frame: The next frame this pipe is allowed to transmit on
312 * @flags: State flags for this pipe
313 * @device_speed: Speed of device connected to this pipe
314 * @transfer_type: Type of transaction supported by this pipe
315 * @transfer_dir: IN or OUT. Ignored for Control
316 * @multi_count: Max packet in a row for the device
317 * @max_packet: The device's maximum packet size in bytes
318 * @device_addr: USB device address at other end of pipe
319 * @endpoint_num: USB endpoint number at other end of pipe
320 * @hub_device_addr: Hub address this device is connected to
321 * @hub_port: Hub port this device is connected to
322 * @pid_toggle: This toggles between 0/1 on every packet send to track
323 * the data pid needed
324 * @channel: Hardware DMA channel for this pipe
325 * @split_sc_frame: The low order bits of the frame number the split
326 * complete should be sent on
328 struct cvmx_usb_pipe
{
329 struct list_head node
;
330 struct list_head transactions
;
332 uint64_t next_tx_frame
;
333 enum cvmx_usb_pipe_flags flags
;
334 enum cvmx_usb_speed device_speed
;
335 enum cvmx_usb_transfer transfer_type
;
336 enum cvmx_usb_direction transfer_dir
;
340 uint8_t endpoint_num
;
341 uint8_t hub_device_addr
;
345 int8_t split_sc_frame
;
348 struct cvmx_usb_tx_fifo
{
353 } entry
[MAX_CHANNELS
+1];
359 * struct cvmx_usb_state - the state of the USB block
361 * init_flags: Flags passed to initialize.
362 * index: Which USB block this is for.
363 * idle_hardware_channels: Bit set for every idle hardware channel.
364 * usbcx_hprt: Stored port status so we don't need to read a CSR to
366 * pipe_for_channel: Map channels to pipes.
367 * pipe: Storage for pipes.
368 * indent: Used by debug output to indent functions.
369 * port_status: Last port status used for change notification.
370 * idle_pipes: List of open pipes that have no transactions.
371 * active_pipes: Active pipes indexed by transfer type.
372 * frame_number: Increments every SOF interrupt for time keeping.
373 * active_split: Points to the current active split, or NULL.
375 struct cvmx_usb_state
{
378 int idle_hardware_channels
;
379 union cvmx_usbcx_hprt usbcx_hprt
;
380 struct cvmx_usb_pipe
*pipe_for_channel
[MAX_CHANNELS
];
382 struct cvmx_usb_port_status port_status
;
383 struct list_head idle_pipes
;
384 struct list_head active_pipes
[4];
385 uint64_t frame_number
;
386 struct cvmx_usb_transaction
*active_split
;
387 struct cvmx_usb_tx_fifo periodic
;
388 struct cvmx_usb_tx_fifo nonperiodic
;
393 struct cvmx_usb_state usb
;
396 /* This macro spins on a field waiting for it to reach a value */
397 #define CVMX_WAIT_FOR_FIELD32(address, type, field, op, value, timeout_usec)\
400 uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec * \
401 octeon_get_clock_rate() / 1000000; \
404 c.u32 = cvmx_usb_read_csr32(usb, address); \
405 if (c.s.field op (value)) { \
408 } else if (cvmx_get_cycle() > done) { \
418 * This macro logically sets a single field in a CSR. It does the sequence
419 * read, modify, and write
421 #define USB_SET_FIELD32(address, type, field, value) \
424 c.u32 = cvmx_usb_read_csr32(usb, address); \
426 cvmx_usb_write_csr32(usb, address, c.u32); \
429 /* Returns the IO address to push/pop stuff data from the FIFOs */
430 #define USB_FIFO_ADDRESS(channel, usb_index) \
431 (CVMX_USBCX_GOTGCTL(usb_index) + ((channel)+1)*0x1000)
434 * struct octeon_temp_buffer - a bounce buffer for USB transfers
435 * @orig_buffer: the original buffer passed by the USB stack
436 * @data: the newly allocated temporary buffer (excluding meta-data)
438 * Both the DMA engine and FIFO mode will always transfer full 32-bit words. If
439 * the buffer is too short, we need to allocate a temporary one, and this struct
442 struct octeon_temp_buffer
{
447 static inline struct octeon_hcd
*cvmx_usb_to_octeon(struct cvmx_usb_state
*p
)
449 return container_of(p
, struct octeon_hcd
, usb
);
452 static inline struct usb_hcd
*octeon_to_hcd(struct octeon_hcd
*p
)
454 return container_of((void *)p
, struct usb_hcd
, hcd_priv
);
458 * octeon_alloc_temp_buffer - allocate a temporary buffer for USB transfer
461 * @mem_flags: Memory allocation flags.
463 * This function allocates a temporary bounce buffer whenever it's needed
464 * due to HW limitations.
466 static int octeon_alloc_temp_buffer(struct urb
*urb
, gfp_t mem_flags
)
468 struct octeon_temp_buffer
*temp
;
470 if (urb
->num_sgs
|| urb
->sg
||
471 (urb
->transfer_flags
& URB_NO_TRANSFER_DMA_MAP
) ||
472 !(urb
->transfer_buffer_length
% sizeof(u32
)))
475 temp
= kmalloc(ALIGN(urb
->transfer_buffer_length
, sizeof(u32
)) +
476 sizeof(*temp
), mem_flags
);
480 temp
->orig_buffer
= urb
->transfer_buffer
;
481 if (usb_urb_dir_out(urb
))
482 memcpy(temp
->data
, urb
->transfer_buffer
,
483 urb
->transfer_buffer_length
);
484 urb
->transfer_buffer
= temp
->data
;
485 urb
->transfer_flags
|= URB_ALIGNED_TEMP_BUFFER
;
491 * octeon_free_temp_buffer - free a temporary buffer used by USB transfers.
494 * Frees a buffer allocated by octeon_alloc_temp_buffer().
496 static void octeon_free_temp_buffer(struct urb
*urb
)
498 struct octeon_temp_buffer
*temp
;
500 if (!(urb
->transfer_flags
& URB_ALIGNED_TEMP_BUFFER
))
503 temp
= container_of(urb
->transfer_buffer
, struct octeon_temp_buffer
,
505 if (usb_urb_dir_in(urb
))
506 memcpy(temp
->orig_buffer
, urb
->transfer_buffer
,
508 urb
->transfer_buffer
= temp
->orig_buffer
;
509 urb
->transfer_flags
&= ~URB_ALIGNED_TEMP_BUFFER
;
514 * octeon_map_urb_for_dma - Octeon-specific map_urb_for_dma().
515 * @hcd: USB HCD structure.
517 * @mem_flags: Memory allocation flags.
519 static int octeon_map_urb_for_dma(struct usb_hcd
*hcd
, struct urb
*urb
,
524 ret
= octeon_alloc_temp_buffer(urb
, mem_flags
);
528 ret
= usb_hcd_map_urb_for_dma(hcd
, urb
, mem_flags
);
530 octeon_free_temp_buffer(urb
);
536 * octeon_unmap_urb_for_dma - Octeon-specific unmap_urb_for_dma()
537 * @hcd: USB HCD structure.
540 static void octeon_unmap_urb_for_dma(struct usb_hcd
*hcd
, struct urb
*urb
)
542 usb_hcd_unmap_urb_for_dma(hcd
, urb
);
543 octeon_free_temp_buffer(urb
);
547 * Read a USB 32bit CSR. It performs the necessary address swizzle
548 * for 32bit CSRs and logs the value in a readable format if
551 * @usb: USB block this access is for
552 * @address: 64bit address to read
554 * Returns: Result of the read
556 static inline uint32_t cvmx_usb_read_csr32(struct cvmx_usb_state
*usb
,
559 uint32_t result
= cvmx_read64_uint32(address
^ 4);
565 * Write a USB 32bit CSR. It performs the necessary address
566 * swizzle for 32bit CSRs and logs the value in a readable format
567 * if debugging is on.
569 * @usb: USB block this access is for
570 * @address: 64bit address to write
571 * @value: Value to write
573 static inline void cvmx_usb_write_csr32(struct cvmx_usb_state
*usb
,
574 uint64_t address
, uint32_t value
)
576 cvmx_write64_uint32(address
^ 4, value
);
577 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb
->index
));
581 * Return non zero if this pipe connects to a non HIGH speed
582 * device through a high speed hub.
584 * @usb: USB block this access is for
585 * @pipe: Pipe to check
587 * Returns: Non zero if we need to do split transactions
589 static inline int cvmx_usb_pipe_needs_split(struct cvmx_usb_state
*usb
,
590 struct cvmx_usb_pipe
*pipe
)
592 return pipe
->device_speed
!= CVMX_USB_SPEED_HIGH
&&
593 usb
->usbcx_hprt
.s
.prtspd
== CVMX_USB_SPEED_HIGH
;
598 * Trivial utility function to return the correct PID for a pipe
600 * @pipe: pipe to check
602 * Returns: PID for pipe
604 static inline int cvmx_usb_get_data_pid(struct cvmx_usb_pipe
*pipe
)
606 if (pipe
->pid_toggle
)
607 return 2; /* Data1 */
608 return 0; /* Data0 */
612 * Initialize a USB port for use. This must be called before any
613 * other access to the Octeon USB port is made. The port starts
614 * off in the disabled state.
616 * @usb: Pointer to struct cvmx_usb_state.
618 * Returns: 0 or a negative error code.
620 static int cvmx_usb_initialize(struct cvmx_usb_state
*usb
)
622 union cvmx_usbnx_clk_ctl usbn_clk_ctl
;
623 union cvmx_usbnx_usbp_ctl_status usbn_usbp_ctl_status
;
626 * Power On Reset and PHY Initialization
628 * 1. Wait for DCOK to assert (nothing to do)
630 * 2a. Write USBN0/1_CLK_CTL[POR] = 1 and
631 * USBN0/1_CLK_CTL[HRST,PRST,HCLK_RST] = 0
633 usbn_clk_ctl
.u64
= cvmx_read64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
));
634 usbn_clk_ctl
.s
.por
= 1;
635 usbn_clk_ctl
.s
.hrst
= 0;
636 usbn_clk_ctl
.s
.prst
= 0;
637 usbn_clk_ctl
.s
.hclk_rst
= 0;
638 usbn_clk_ctl
.s
.enable
= 0;
640 * 2b. Select the USB reference clock/crystal parameters by writing
641 * appropriate values to USBN0/1_CLK_CTL[P_C_SEL, P_RTYPE, P_COM_ON]
643 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND
) {
645 * The USB port uses 12/24/48MHz 2.5V board clock
646 * source at USB_XO. USB_XI should be tied to GND.
647 * Most Octeon evaluation boards require this setting
649 if (OCTEON_IS_MODEL(OCTEON_CN3XXX
) ||
650 OCTEON_IS_MODEL(OCTEON_CN56XX
) ||
651 OCTEON_IS_MODEL(OCTEON_CN50XX
))
652 /* From CN56XX,CN50XX,CN31XX,CN30XX manuals */
653 usbn_clk_ctl
.s
.p_rtype
= 2; /* p_rclk=1 & p_xenbn=0 */
655 /* From CN52XX manual */
656 usbn_clk_ctl
.s
.p_rtype
= 1;
658 switch (usb
->init_flags
&
659 CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK
) {
660 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ
:
661 usbn_clk_ctl
.s
.p_c_sel
= 0;
663 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ
:
664 usbn_clk_ctl
.s
.p_c_sel
= 1;
666 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ
:
667 usbn_clk_ctl
.s
.p_c_sel
= 2;
672 * The USB port uses a 12MHz crystal as clock source
673 * at USB_XO and USB_XI
675 if (OCTEON_IS_MODEL(OCTEON_CN3XXX
))
676 /* From CN31XX,CN30XX manual */
677 usbn_clk_ctl
.s
.p_rtype
= 3; /* p_rclk=1 & p_xenbn=1 */
679 /* From CN56XX,CN52XX,CN50XX manuals. */
680 usbn_clk_ctl
.s
.p_rtype
= 0;
682 usbn_clk_ctl
.s
.p_c_sel
= 0;
685 * 2c. Select the HCLK via writing USBN0/1_CLK_CTL[DIVIDE, DIVIDE2] and
686 * setting USBN0/1_CLK_CTL[ENABLE] = 1. Divide the core clock down
687 * such that USB is as close as possible to 125Mhz
690 int divisor
= DIV_ROUND_UP(octeon_get_clock_rate(), 125000000);
691 /* Lower than 4 doesn't seem to work properly */
694 usbn_clk_ctl
.s
.divide
= divisor
;
695 usbn_clk_ctl
.s
.divide2
= 0;
697 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
), usbn_clk_ctl
.u64
);
698 /* 2d. Write USBN0/1_CLK_CTL[HCLK_RST] = 1 */
699 usbn_clk_ctl
.s
.hclk_rst
= 1;
700 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
), usbn_clk_ctl
.u64
);
701 /* 2e. Wait 64 core-clock cycles for HCLK to stabilize */
704 * 3. Program the power-on reset field in the USBN clock-control
706 * USBN_CLK_CTL[POR] = 0
708 usbn_clk_ctl
.s
.por
= 0;
709 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
), usbn_clk_ctl
.u64
);
710 /* 4. Wait 1 ms for PHY clock to start */
713 * 5. Program the Reset input from automatic test equipment field in the
714 * USBP control and status register:
715 * USBN_USBP_CTL_STATUS[ATE_RESET] = 1
717 usbn_usbp_ctl_status
.u64
=
718 cvmx_read64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb
->index
));
719 usbn_usbp_ctl_status
.s
.ate_reset
= 1;
720 cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb
->index
),
721 usbn_usbp_ctl_status
.u64
);
722 /* 6. Wait 10 cycles */
725 * 7. Clear ATE_RESET field in the USBN clock-control register:
726 * USBN_USBP_CTL_STATUS[ATE_RESET] = 0
728 usbn_usbp_ctl_status
.s
.ate_reset
= 0;
729 cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb
->index
),
730 usbn_usbp_ctl_status
.u64
);
732 * 8. Program the PHY reset field in the USBN clock-control register:
733 * USBN_CLK_CTL[PRST] = 1
735 usbn_clk_ctl
.s
.prst
= 1;
736 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
), usbn_clk_ctl
.u64
);
738 * 9. Program the USBP control and status register to select host or
739 * device mode. USBN_USBP_CTL_STATUS[HST_MODE] = 0 for host, = 1 for
742 usbn_usbp_ctl_status
.s
.hst_mode
= 0;
743 cvmx_write64_uint64(CVMX_USBNX_USBP_CTL_STATUS(usb
->index
),
744 usbn_usbp_ctl_status
.u64
);
748 * 11. Program the hreset_n field in the USBN clock-control register:
749 * USBN_CLK_CTL[HRST] = 1
751 usbn_clk_ctl
.s
.hrst
= 1;
752 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
), usbn_clk_ctl
.u64
);
753 /* 12. Proceed to USB core initialization */
754 usbn_clk_ctl
.s
.enable
= 1;
755 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
), usbn_clk_ctl
.u64
);
759 * USB Core Initialization
761 * 1. Read USBC_GHWCFG1, USBC_GHWCFG2, USBC_GHWCFG3, USBC_GHWCFG4 to
762 * determine USB core configuration parameters.
766 * 2. Program the following fields in the global AHB configuration
767 * register (USBC_GAHBCFG)
768 * DMA mode, USBC_GAHBCFG[DMAEn]: 1 = DMA mode, 0 = slave mode
769 * Burst length, USBC_GAHBCFG[HBSTLEN] = 0
770 * Nonperiodic TxFIFO empty level (slave mode only),
771 * USBC_GAHBCFG[NPTXFEMPLVL]
772 * Periodic TxFIFO empty level (slave mode only),
773 * USBC_GAHBCFG[PTXFEMPLVL]
774 * Global interrupt mask, USBC_GAHBCFG[GLBLINTRMSK] = 1
777 union cvmx_usbcx_gahbcfg usbcx_gahbcfg
;
778 usbcx_gahbcfg
.u32
= 0;
779 usbcx_gahbcfg
.s
.dmaen
= !(usb
->init_flags
&
780 CVMX_USB_INITIALIZE_FLAGS_NO_DMA
);
781 usbcx_gahbcfg
.s
.hbstlen
= 0;
782 usbcx_gahbcfg
.s
.nptxfemplvl
= 1;
783 usbcx_gahbcfg
.s
.ptxfemplvl
= 1;
784 usbcx_gahbcfg
.s
.glblintrmsk
= 1;
785 cvmx_usb_write_csr32(usb
, CVMX_USBCX_GAHBCFG(usb
->index
),
789 * 3. Program the following fields in USBC_GUSBCFG register.
790 * HS/FS timeout calibration, USBC_GUSBCFG[TOUTCAL] = 0
791 * ULPI DDR select, USBC_GUSBCFG[DDRSEL] = 0
792 * USB turnaround time, USBC_GUSBCFG[USBTRDTIM] = 0x5
793 * PHY low-power clock select, USBC_GUSBCFG[PHYLPWRCLKSEL] = 0
796 union cvmx_usbcx_gusbcfg usbcx_gusbcfg
;
798 usbcx_gusbcfg
.u32
= cvmx_usb_read_csr32(usb
,
799 CVMX_USBCX_GUSBCFG(usb
->index
));
800 usbcx_gusbcfg
.s
.toutcal
= 0;
801 usbcx_gusbcfg
.s
.ddrsel
= 0;
802 usbcx_gusbcfg
.s
.usbtrdtim
= 0x5;
803 usbcx_gusbcfg
.s
.phylpwrclksel
= 0;
804 cvmx_usb_write_csr32(usb
, CVMX_USBCX_GUSBCFG(usb
->index
),
808 * 4. The software must unmask the following bits in the USBC_GINTMSK
810 * OTG interrupt mask, USBC_GINTMSK[OTGINTMSK] = 1
811 * Mode mismatch interrupt mask, USBC_GINTMSK[MODEMISMSK] = 1
814 union cvmx_usbcx_gintmsk usbcx_gintmsk
;
817 usbcx_gintmsk
.u32
= cvmx_usb_read_csr32(usb
,
818 CVMX_USBCX_GINTMSK(usb
->index
));
819 usbcx_gintmsk
.s
.otgintmsk
= 1;
820 usbcx_gintmsk
.s
.modemismsk
= 1;
821 usbcx_gintmsk
.s
.hchintmsk
= 1;
822 usbcx_gintmsk
.s
.sofmsk
= 0;
823 /* We need RX FIFO interrupts if we don't have DMA */
824 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)
825 usbcx_gintmsk
.s
.rxflvlmsk
= 1;
826 cvmx_usb_write_csr32(usb
, CVMX_USBCX_GINTMSK(usb
->index
),
830 * Disable all channel interrupts. We'll enable them per channel
833 for (channel
= 0; channel
< 8; channel
++)
834 cvmx_usb_write_csr32(usb
,
835 CVMX_USBCX_HCINTMSKX(channel
, usb
->index
), 0);
840 * Host Port Initialization
842 * 1. Program the host-port interrupt-mask field to unmask,
843 * USBC_GINTMSK[PRTINT] = 1
845 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
),
846 union cvmx_usbcx_gintmsk
, prtintmsk
, 1);
847 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
),
848 union cvmx_usbcx_gintmsk
, disconnintmsk
, 1);
850 * 2. Program the USBC_HCFG register to select full-speed host
851 * or high-speed host.
854 union cvmx_usbcx_hcfg usbcx_hcfg
;
856 usbcx_hcfg
.u32
= cvmx_usb_read_csr32(usb
,
857 CVMX_USBCX_HCFG(usb
->index
));
858 usbcx_hcfg
.s
.fslssupp
= 0;
859 usbcx_hcfg
.s
.fslspclksel
= 0;
860 cvmx_usb_write_csr32(usb
, CVMX_USBCX_HCFG(usb
->index
),
864 * 3. Program the port power bit to drive VBUS on the USB,
865 * USBC_HPRT[PRTPWR] = 1
867 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb
->index
),
868 union cvmx_usbcx_hprt
, prtpwr
, 1);
871 * Steps 4-15 from the manual are done later in the port enable
880 * Shutdown a USB port after a call to cvmx_usb_initialize().
881 * The port should be disabled with all pipes closed when this
882 * function is called.
884 * @usb: USB device state populated by cvmx_usb_initialize().
886 * Returns: 0 or a negative error code.
888 static int cvmx_usb_shutdown(struct cvmx_usb_state
*usb
)
890 union cvmx_usbnx_clk_ctl usbn_clk_ctl
;
892 /* Make sure all pipes are closed */
893 if (!list_empty(&usb
->idle_pipes
) ||
894 !list_empty(&usb
->active_pipes
[CVMX_USB_TRANSFER_ISOCHRONOUS
]) ||
895 !list_empty(&usb
->active_pipes
[CVMX_USB_TRANSFER_INTERRUPT
]) ||
896 !list_empty(&usb
->active_pipes
[CVMX_USB_TRANSFER_CONTROL
]) ||
897 !list_empty(&usb
->active_pipes
[CVMX_USB_TRANSFER_BULK
]))
900 /* Disable the clocks and put them in power on reset */
901 usbn_clk_ctl
.u64
= cvmx_read64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
));
902 usbn_clk_ctl
.s
.enable
= 1;
903 usbn_clk_ctl
.s
.por
= 1;
904 usbn_clk_ctl
.s
.hclk_rst
= 1;
905 usbn_clk_ctl
.s
.prst
= 0;
906 usbn_clk_ctl
.s
.hrst
= 0;
907 cvmx_write64_uint64(CVMX_USBNX_CLK_CTL(usb
->index
), usbn_clk_ctl
.u64
);
913 * Enable a USB port. After this call succeeds, the USB port is
914 * online and servicing requests.
916 * @usb: USB device state populated by cvmx_usb_initialize().
918 * Returns: 0 or a negative error code.
920 static int cvmx_usb_enable(struct cvmx_usb_state
*usb
)
922 union cvmx_usbcx_ghwcfg3 usbcx_ghwcfg3
;
924 usb
->usbcx_hprt
.u32
= cvmx_usb_read_csr32(usb
,
925 CVMX_USBCX_HPRT(usb
->index
));
928 * If the port is already enabled the just return. We don't need to do
931 if (usb
->usbcx_hprt
.s
.prtena
)
934 /* If there is nothing plugged into the port then fail immediately */
935 if (!usb
->usbcx_hprt
.s
.prtconnsts
)
938 /* Program the port reset bit to start the reset process */
939 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb
->index
), union cvmx_usbcx_hprt
,
943 * Wait at least 50ms (high speed), or 10ms (full speed) for the reset
944 * process to complete.
948 /* Program the port reset bit to 0, USBC_HPRT[PRTRST] = 0 */
949 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb
->index
), union cvmx_usbcx_hprt
,
952 /* Wait for the USBC_HPRT[PRTENA]. */
953 if (CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_HPRT(usb
->index
),
954 union cvmx_usbcx_hprt
, prtena
, ==, 1, 100000))
958 * Read the port speed field to get the enumerated speed,
961 usb
->usbcx_hprt
.u32
= cvmx_usb_read_csr32(usb
,
962 CVMX_USBCX_HPRT(usb
->index
));
963 usbcx_ghwcfg3
.u32
= cvmx_usb_read_csr32(usb
,
964 CVMX_USBCX_GHWCFG3(usb
->index
));
967 * 13. Program the USBC_GRXFSIZ register to select the size of the
968 * receive FIFO (25%).
970 USB_SET_FIELD32(CVMX_USBCX_GRXFSIZ(usb
->index
),
971 union cvmx_usbcx_grxfsiz
, rxfdep
,
972 usbcx_ghwcfg3
.s
.dfifodepth
/ 4);
974 * 14. Program the USBC_GNPTXFSIZ register to select the size and the
975 * start address of the non- periodic transmit FIFO for nonperiodic
976 * transactions (50%).
979 union cvmx_usbcx_gnptxfsiz siz
;
981 siz
.u32
= cvmx_usb_read_csr32(usb
,
982 CVMX_USBCX_GNPTXFSIZ(usb
->index
));
983 siz
.s
.nptxfdep
= usbcx_ghwcfg3
.s
.dfifodepth
/ 2;
984 siz
.s
.nptxfstaddr
= usbcx_ghwcfg3
.s
.dfifodepth
/ 4;
985 cvmx_usb_write_csr32(usb
, CVMX_USBCX_GNPTXFSIZ(usb
->index
),
989 * 15. Program the USBC_HPTXFSIZ register to select the size and start
990 * address of the periodic transmit FIFO for periodic transactions
994 union cvmx_usbcx_hptxfsiz siz
;
996 siz
.u32
= cvmx_usb_read_csr32(usb
,
997 CVMX_USBCX_HPTXFSIZ(usb
->index
));
998 siz
.s
.ptxfsize
= usbcx_ghwcfg3
.s
.dfifodepth
/ 4;
999 siz
.s
.ptxfstaddr
= 3 * usbcx_ghwcfg3
.s
.dfifodepth
/ 4;
1000 cvmx_usb_write_csr32(usb
, CVMX_USBCX_HPTXFSIZ(usb
->index
),
1003 /* Flush all FIFOs */
1004 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb
->index
),
1005 union cvmx_usbcx_grstctl
, txfnum
, 0x10);
1006 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb
->index
),
1007 union cvmx_usbcx_grstctl
, txfflsh
, 1);
1008 CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb
->index
),
1009 union cvmx_usbcx_grstctl
,
1010 txfflsh
, ==, 0, 100);
1011 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb
->index
),
1012 union cvmx_usbcx_grstctl
, rxfflsh
, 1);
1013 CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb
->index
),
1014 union cvmx_usbcx_grstctl
,
1015 rxfflsh
, ==, 0, 100);
1022 * Disable a USB port. After this call the USB port will not
1023 * generate data transfers and will not generate events.
1024 * Transactions in process will fail and call their
1025 * associated callbacks.
1027 * @usb: USB device state populated by cvmx_usb_initialize().
1029 * Returns: 0 or a negative error code.
1031 static int cvmx_usb_disable(struct cvmx_usb_state
*usb
)
1033 /* Disable the port */
1034 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb
->index
), union cvmx_usbcx_hprt
,
1041 * Get the current state of the USB port. Use this call to
1042 * determine if the usb port has anything connected, is enabled,
1043 * or has some sort of error condition. The return value of this
1044 * call has "changed" bits to signal of the value of some fields
1045 * have changed between calls.
1047 * @usb: USB device state populated by cvmx_usb_initialize().
1049 * Returns: Port status information
1051 static struct cvmx_usb_port_status
cvmx_usb_get_status(
1052 struct cvmx_usb_state
*usb
)
1054 union cvmx_usbcx_hprt usbc_hprt
;
1055 struct cvmx_usb_port_status result
;
1057 memset(&result
, 0, sizeof(result
));
1059 usbc_hprt
.u32
= cvmx_usb_read_csr32(usb
, CVMX_USBCX_HPRT(usb
->index
));
1060 result
.port_enabled
= usbc_hprt
.s
.prtena
;
1061 result
.port_over_current
= usbc_hprt
.s
.prtovrcurract
;
1062 result
.port_powered
= usbc_hprt
.s
.prtpwr
;
1063 result
.port_speed
= usbc_hprt
.s
.prtspd
;
1064 result
.connected
= usbc_hprt
.s
.prtconnsts
;
1065 result
.connect_change
=
1066 (result
.connected
!= usb
->port_status
.connected
);
1072 * Open a virtual pipe between the host and a USB device. A pipe
1073 * must be opened before data can be transferred between a device
1076 * @usb: USB device state populated by cvmx_usb_initialize().
1078 * USB device address to open the pipe to
1081 * USB endpoint number to open the pipe to
1084 * The speed of the device the pipe is going
1085 * to. This must match the device's speed,
1086 * which may be different than the port speed.
1087 * @max_packet: The maximum packet length the device can
1088 * transmit/receive (low speed=0-8, full
1089 * speed=0-1023, high speed=0-1024). This value
1090 * comes from the standard endpoint descriptor
1091 * field wMaxPacketSize bits <10:0>.
1093 * The type of transfer this pipe is for.
1095 * The direction the pipe is in. This is not
1096 * used for control pipes.
1097 * @interval: For ISOCHRONOUS and INTERRUPT transfers,
1098 * this is how often the transfer is scheduled
1099 * for. All other transfers should specify
1100 * zero. The units are in frames (8000/sec at
1101 * high speed, 1000/sec for full speed).
1103 * For high speed devices, this is the maximum
1104 * allowed number of packet per microframe.
1105 * Specify zero for non high speed devices. This
1106 * value comes from the standard endpoint descriptor
1107 * field wMaxPacketSize bits <12:11>.
1109 * Hub device address this device is connected
1110 * to. Devices connected directly to Octeon
1111 * use zero. This is only used when the device
1112 * is full/low speed behind a high speed hub.
1113 * The address will be of the high speed hub,
1114 * not and full speed hubs after it.
1115 * @hub_port: Which port on the hub the device is
1116 * connected. Use zero for devices connected
1117 * directly to Octeon. Like hub_device_addr,
1118 * this is only used for full/low speed
1119 * devices behind a high speed hub.
1121 * Returns: A non-NULL value is a pipe. NULL means an error.
1123 static struct cvmx_usb_pipe
*cvmx_usb_open_pipe(struct cvmx_usb_state
*usb
,
1129 enum cvmx_usb_transfer
1131 enum cvmx_usb_direction
1133 int interval
, int multi_count
,
1134 int hub_device_addr
,
1137 struct cvmx_usb_pipe
*pipe
;
1139 pipe
= kzalloc(sizeof(*pipe
), GFP_ATOMIC
);
1142 if ((device_speed
== CVMX_USB_SPEED_HIGH
) &&
1143 (transfer_dir
== CVMX_USB_DIRECTION_OUT
) &&
1144 (transfer_type
== CVMX_USB_TRANSFER_BULK
))
1145 pipe
->flags
|= CVMX_USB_PIPE_FLAGS_NEED_PING
;
1146 pipe
->device_addr
= device_addr
;
1147 pipe
->endpoint_num
= endpoint_num
;
1148 pipe
->device_speed
= device_speed
;
1149 pipe
->max_packet
= max_packet
;
1150 pipe
->transfer_type
= transfer_type
;
1151 pipe
->transfer_dir
= transfer_dir
;
1152 INIT_LIST_HEAD(&pipe
->transactions
);
1155 * All pipes use interval to rate limit NAK processing. Force an
1156 * interval if one wasn't supplied
1160 if (cvmx_usb_pipe_needs_split(usb
, pipe
)) {
1161 pipe
->interval
= interval
*8;
1162 /* Force start splits to be schedule on uFrame 0 */
1163 pipe
->next_tx_frame
= ((usb
->frame_number
+7)&~7) +
1166 pipe
->interval
= interval
;
1167 pipe
->next_tx_frame
= usb
->frame_number
+ pipe
->interval
;
1169 pipe
->multi_count
= multi_count
;
1170 pipe
->hub_device_addr
= hub_device_addr
;
1171 pipe
->hub_port
= hub_port
;
1172 pipe
->pid_toggle
= 0;
1173 pipe
->split_sc_frame
= -1;
1174 list_add_tail(&pipe
->node
, &usb
->idle_pipes
);
1177 * We don't need to tell the hardware about this pipe yet since
1178 * it doesn't have any submitted requests
1186 * Poll the RX FIFOs and remove data as needed. This function is only used
1187 * in non DMA mode. It is very important that this function be called quickly
1188 * enough to prevent FIFO overflow.
1190 * @usb: USB device state populated by cvmx_usb_initialize().
1192 static void cvmx_usb_poll_rx_fifo(struct cvmx_usb_state
*usb
)
1194 union cvmx_usbcx_grxstsph rx_status
;
1200 rx_status
.u32
= cvmx_usb_read_csr32(usb
,
1201 CVMX_USBCX_GRXSTSPH(usb
->index
));
1202 /* Only read data if IN data is there */
1203 if (rx_status
.s
.pktsts
!= 2)
1205 /* Check if no data is available */
1206 if (!rx_status
.s
.bcnt
)
1209 channel
= rx_status
.s
.chnum
;
1210 bytes
= rx_status
.s
.bcnt
;
1214 /* Get where the DMA engine would have written this data */
1215 address
= cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb
->index
) +
1218 ptr
= cvmx_phys_to_ptr(address
);
1219 cvmx_write64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb
->index
) + channel
* 8,
1222 /* Loop writing the FIFO data for this packet into memory */
1224 *ptr
++ = cvmx_usb_read_csr32(usb
,
1225 USB_FIFO_ADDRESS(channel
, usb
->index
));
1233 * Fill the TX hardware fifo with data out of the software
1236 * @usb: USB device state populated by cvmx_usb_initialize().
1237 * @fifo: Software fifo to use
1238 * @available: Amount of space in the hardware fifo
1240 * Returns: Non zero if the hardware fifo was too small and needs
1241 * to be serviced again.
1243 static int cvmx_usb_fill_tx_hw(struct cvmx_usb_state
*usb
,
1244 struct cvmx_usb_tx_fifo
*fifo
, int available
)
1247 * We're done either when there isn't anymore space or the software FIFO
1250 while (available
&& (fifo
->head
!= fifo
->tail
)) {
1252 const uint32_t *ptr
= cvmx_phys_to_ptr(fifo
->entry
[i
].address
);
1253 uint64_t csr_address
= USB_FIFO_ADDRESS(fifo
->entry
[i
].channel
,
1255 int words
= available
;
1257 /* Limit the amount of data to waht the SW fifo has */
1258 if (fifo
->entry
[i
].size
<= available
) {
1259 words
= fifo
->entry
[i
].size
;
1261 if (fifo
->tail
> MAX_CHANNELS
)
1265 /* Update the next locations and counts */
1267 fifo
->entry
[i
].address
+= words
* 4;
1268 fifo
->entry
[i
].size
-= words
;
1271 * Write the HW fifo data. The read every three writes is due
1272 * to an errata on CN3XXX chips
1275 cvmx_write64_uint32(csr_address
, *ptr
++);
1276 cvmx_write64_uint32(csr_address
, *ptr
++);
1277 cvmx_write64_uint32(csr_address
, *ptr
++);
1279 CVMX_USBNX_DMA0_INB_CHN0(usb
->index
));
1282 cvmx_write64_uint32(csr_address
, *ptr
++);
1284 cvmx_write64_uint32(csr_address
, *ptr
++);
1286 cvmx_write64_uint32(csr_address
, *ptr
++);
1288 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb
->index
));
1290 return fifo
->head
!= fifo
->tail
;
1295 * Check the hardware FIFOs and fill them as needed
1297 * @usb: USB device state populated by cvmx_usb_initialize().
1299 static void cvmx_usb_poll_tx_fifo(struct cvmx_usb_state
*usb
)
1301 if (usb
->periodic
.head
!= usb
->periodic
.tail
) {
1302 union cvmx_usbcx_hptxsts tx_status
;
1304 tx_status
.u32
= cvmx_usb_read_csr32(usb
,
1305 CVMX_USBCX_HPTXSTS(usb
->index
));
1306 if (cvmx_usb_fill_tx_hw(usb
, &usb
->periodic
,
1307 tx_status
.s
.ptxfspcavail
))
1308 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
),
1309 union cvmx_usbcx_gintmsk
,
1312 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
),
1313 union cvmx_usbcx_gintmsk
,
1317 if (usb
->nonperiodic
.head
!= usb
->nonperiodic
.tail
) {
1318 union cvmx_usbcx_gnptxsts tx_status
;
1320 tx_status
.u32
= cvmx_usb_read_csr32(usb
,
1321 CVMX_USBCX_GNPTXSTS(usb
->index
));
1322 if (cvmx_usb_fill_tx_hw(usb
, &usb
->nonperiodic
,
1323 tx_status
.s
.nptxfspcavail
))
1324 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
),
1325 union cvmx_usbcx_gintmsk
,
1328 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
),
1329 union cvmx_usbcx_gintmsk
,
1336 * Fill the TX FIFO with an outgoing packet
1338 * @usb: USB device state populated by cvmx_usb_initialize().
1339 * @channel: Channel number to get packet from
1341 static void cvmx_usb_fill_tx_fifo(struct cvmx_usb_state
*usb
, int channel
)
1343 union cvmx_usbcx_hccharx hcchar
;
1344 union cvmx_usbcx_hcspltx usbc_hcsplt
;
1345 union cvmx_usbcx_hctsizx usbc_hctsiz
;
1346 struct cvmx_usb_tx_fifo
*fifo
;
1348 /* We only need to fill data on outbound channels */
1349 hcchar
.u32
= cvmx_usb_read_csr32(usb
,
1350 CVMX_USBCX_HCCHARX(channel
, usb
->index
));
1351 if (hcchar
.s
.epdir
!= CVMX_USB_DIRECTION_OUT
)
1354 /* OUT Splits only have data on the start and not the complete */
1355 usbc_hcsplt
.u32
= cvmx_usb_read_csr32(usb
,
1356 CVMX_USBCX_HCSPLTX(channel
, usb
->index
));
1357 if (usbc_hcsplt
.s
.spltena
&& usbc_hcsplt
.s
.compsplt
)
1361 * Find out how many bytes we need to fill and convert it into 32bit
1364 usbc_hctsiz
.u32
= cvmx_usb_read_csr32(usb
,
1365 CVMX_USBCX_HCTSIZX(channel
, usb
->index
));
1366 if (!usbc_hctsiz
.s
.xfersize
)
1369 if ((hcchar
.s
.eptype
== CVMX_USB_TRANSFER_INTERRUPT
) ||
1370 (hcchar
.s
.eptype
== CVMX_USB_TRANSFER_ISOCHRONOUS
))
1371 fifo
= &usb
->periodic
;
1373 fifo
= &usb
->nonperiodic
;
1375 fifo
->entry
[fifo
->head
].channel
= channel
;
1376 fifo
->entry
[fifo
->head
].address
=
1377 cvmx_read64_uint64(CVMX_USBNX_DMA0_OUTB_CHN0(usb
->index
) +
1379 fifo
->entry
[fifo
->head
].size
= (usbc_hctsiz
.s
.xfersize
+3)>>2;
1381 if (fifo
->head
> MAX_CHANNELS
)
1384 cvmx_usb_poll_tx_fifo(usb
);
1388 * Perform channel specific setup for Control transactions. All
1389 * the generic stuff will already have been done in cvmx_usb_start_channel().
1391 * @usb: USB device state populated by cvmx_usb_initialize().
1392 * @channel: Channel to setup
1393 * @pipe: Pipe for control transaction
1395 static void cvmx_usb_start_channel_control(struct cvmx_usb_state
*usb
,
1397 struct cvmx_usb_pipe
*pipe
)
1399 struct octeon_hcd
*priv
= cvmx_usb_to_octeon(usb
);
1400 struct usb_hcd
*hcd
= octeon_to_hcd(priv
);
1401 struct device
*dev
= hcd
->self
.controller
;
1402 struct cvmx_usb_transaction
*transaction
=
1403 list_first_entry(&pipe
->transactions
, typeof(*transaction
),
1405 struct usb_ctrlrequest
*header
=
1406 cvmx_phys_to_ptr(transaction
->control_header
);
1407 int bytes_to_transfer
= transaction
->buffer_length
-
1408 transaction
->actual_bytes
;
1409 int packets_to_transfer
;
1410 union cvmx_usbcx_hctsizx usbc_hctsiz
;
1412 usbc_hctsiz
.u32
= cvmx_usb_read_csr32(usb
,
1413 CVMX_USBCX_HCTSIZX(channel
, usb
->index
));
1415 switch (transaction
->stage
) {
1416 case CVMX_USB_STAGE_NON_CONTROL
:
1417 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
:
1418 dev_err(dev
, "%s: ERROR - Non control stage\n", __func__
);
1420 case CVMX_USB_STAGE_SETUP
:
1421 usbc_hctsiz
.s
.pid
= 3; /* Setup */
1422 bytes_to_transfer
= sizeof(*header
);
1423 /* All Control operations start with a setup going OUT */
1424 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1425 union cvmx_usbcx_hccharx
, epdir
,
1426 CVMX_USB_DIRECTION_OUT
);
1428 * Setup send the control header instead of the buffer data. The
1429 * buffer data will be used in the next stage
1431 cvmx_write64_uint64(CVMX_USBNX_DMA0_OUTB_CHN0(usb
->index
) +
1433 transaction
->control_header
);
1435 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE
:
1436 usbc_hctsiz
.s
.pid
= 3; /* Setup */
1437 bytes_to_transfer
= 0;
1438 /* All Control operations start with a setup going OUT */
1439 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1440 union cvmx_usbcx_hccharx
, epdir
,
1441 CVMX_USB_DIRECTION_OUT
);
1443 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel
, usb
->index
),
1444 union cvmx_usbcx_hcspltx
, compsplt
, 1);
1446 case CVMX_USB_STAGE_DATA
:
1447 usbc_hctsiz
.s
.pid
= cvmx_usb_get_data_pid(pipe
);
1448 if (cvmx_usb_pipe_needs_split(usb
, pipe
)) {
1449 if (header
->bRequestType
& USB_DIR_IN
)
1450 bytes_to_transfer
= 0;
1451 else if (bytes_to_transfer
> pipe
->max_packet
)
1452 bytes_to_transfer
= pipe
->max_packet
;
1454 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1455 union cvmx_usbcx_hccharx
, epdir
,
1456 ((header
->bRequestType
& USB_DIR_IN
) ?
1457 CVMX_USB_DIRECTION_IN
:
1458 CVMX_USB_DIRECTION_OUT
));
1460 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE
:
1461 usbc_hctsiz
.s
.pid
= cvmx_usb_get_data_pid(pipe
);
1462 if (!(header
->bRequestType
& USB_DIR_IN
))
1463 bytes_to_transfer
= 0;
1464 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1465 union cvmx_usbcx_hccharx
, epdir
,
1466 ((header
->bRequestType
& USB_DIR_IN
) ?
1467 CVMX_USB_DIRECTION_IN
:
1468 CVMX_USB_DIRECTION_OUT
));
1469 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel
, usb
->index
),
1470 union cvmx_usbcx_hcspltx
, compsplt
, 1);
1472 case CVMX_USB_STAGE_STATUS
:
1473 usbc_hctsiz
.s
.pid
= cvmx_usb_get_data_pid(pipe
);
1474 bytes_to_transfer
= 0;
1475 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1476 union cvmx_usbcx_hccharx
, epdir
,
1477 ((header
->bRequestType
& USB_DIR_IN
) ?
1478 CVMX_USB_DIRECTION_OUT
:
1479 CVMX_USB_DIRECTION_IN
));
1481 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE
:
1482 usbc_hctsiz
.s
.pid
= cvmx_usb_get_data_pid(pipe
);
1483 bytes_to_transfer
= 0;
1484 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1485 union cvmx_usbcx_hccharx
, epdir
,
1486 ((header
->bRequestType
& USB_DIR_IN
) ?
1487 CVMX_USB_DIRECTION_OUT
:
1488 CVMX_USB_DIRECTION_IN
));
1489 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel
, usb
->index
),
1490 union cvmx_usbcx_hcspltx
, compsplt
, 1);
1495 * Make sure the transfer never exceeds the byte limit of the hardware.
1496 * Further bytes will be sent as continued transactions
1498 if (bytes_to_transfer
> MAX_TRANSFER_BYTES
) {
1499 /* Round MAX_TRANSFER_BYTES to a multiple of out packet size */
1500 bytes_to_transfer
= MAX_TRANSFER_BYTES
/ pipe
->max_packet
;
1501 bytes_to_transfer
*= pipe
->max_packet
;
1505 * Calculate the number of packets to transfer. If the length is zero
1506 * we still need to transfer one packet
1508 packets_to_transfer
= DIV_ROUND_UP(bytes_to_transfer
,
1510 if (packets_to_transfer
== 0)
1511 packets_to_transfer
= 1;
1512 else if ((packets_to_transfer
> 1) &&
1513 (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)) {
1515 * Limit to one packet when not using DMA. Channels must be
1516 * restarted between every packet for IN transactions, so there
1517 * is no reason to do multiple packets in a row
1519 packets_to_transfer
= 1;
1520 bytes_to_transfer
= packets_to_transfer
* pipe
->max_packet
;
1521 } else if (packets_to_transfer
> MAX_TRANSFER_PACKETS
) {
1523 * Limit the number of packet and data transferred to what the
1524 * hardware can handle
1526 packets_to_transfer
= MAX_TRANSFER_PACKETS
;
1527 bytes_to_transfer
= packets_to_transfer
* pipe
->max_packet
;
1530 usbc_hctsiz
.s
.xfersize
= bytes_to_transfer
;
1531 usbc_hctsiz
.s
.pktcnt
= packets_to_transfer
;
1533 cvmx_usb_write_csr32(usb
, CVMX_USBCX_HCTSIZX(channel
, usb
->index
),
1539 * Start a channel to perform the pipe's head transaction
1541 * @usb: USB device state populated by cvmx_usb_initialize().
1542 * @channel: Channel to setup
1543 * @pipe: Pipe to start
1545 static void cvmx_usb_start_channel(struct cvmx_usb_state
*usb
, int channel
,
1546 struct cvmx_usb_pipe
*pipe
)
1548 struct cvmx_usb_transaction
*transaction
=
1549 list_first_entry(&pipe
->transactions
, typeof(*transaction
),
1552 /* Make sure all writes to the DMA region get flushed */
1555 /* Attach the channel to the pipe */
1556 usb
->pipe_for_channel
[channel
] = pipe
;
1557 pipe
->channel
= channel
;
1558 pipe
->flags
|= CVMX_USB_PIPE_FLAGS_SCHEDULED
;
1560 /* Mark this channel as in use */
1561 usb
->idle_hardware_channels
&= ~(1<<channel
);
1563 /* Enable the channel interrupt bits */
1565 union cvmx_usbcx_hcintx usbc_hcint
;
1566 union cvmx_usbcx_hcintmskx usbc_hcintmsk
;
1567 union cvmx_usbcx_haintmsk usbc_haintmsk
;
1569 /* Clear all channel status bits */
1570 usbc_hcint
.u32
= cvmx_usb_read_csr32(usb
,
1571 CVMX_USBCX_HCINTX(channel
, usb
->index
));
1573 cvmx_usb_write_csr32(usb
,
1574 CVMX_USBCX_HCINTX(channel
, usb
->index
),
1577 usbc_hcintmsk
.u32
= 0;
1578 usbc_hcintmsk
.s
.chhltdmsk
= 1;
1579 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
) {
1581 * Channels need these extra interrupts when we aren't
1584 usbc_hcintmsk
.s
.datatglerrmsk
= 1;
1585 usbc_hcintmsk
.s
.frmovrunmsk
= 1;
1586 usbc_hcintmsk
.s
.bblerrmsk
= 1;
1587 usbc_hcintmsk
.s
.xacterrmsk
= 1;
1588 if (cvmx_usb_pipe_needs_split(usb
, pipe
)) {
1590 * Splits don't generate xfercompl, so we need
1593 usbc_hcintmsk
.s
.nyetmsk
= 1;
1594 usbc_hcintmsk
.s
.ackmsk
= 1;
1596 usbc_hcintmsk
.s
.nakmsk
= 1;
1597 usbc_hcintmsk
.s
.stallmsk
= 1;
1598 usbc_hcintmsk
.s
.xfercomplmsk
= 1;
1600 cvmx_usb_write_csr32(usb
,
1601 CVMX_USBCX_HCINTMSKX(channel
, usb
->index
),
1604 /* Enable the channel interrupt to propagate */
1605 usbc_haintmsk
.u32
= cvmx_usb_read_csr32(usb
,
1606 CVMX_USBCX_HAINTMSK(usb
->index
));
1607 usbc_haintmsk
.s
.haintmsk
|= 1<<channel
;
1608 cvmx_usb_write_csr32(usb
, CVMX_USBCX_HAINTMSK(usb
->index
),
1612 /* Setup the location the DMA engine uses. */
1615 uint64_t dma_address
= transaction
->buffer
+
1616 transaction
->actual_bytes
;
1618 if (transaction
->type
== CVMX_USB_TRANSFER_ISOCHRONOUS
)
1619 dma_address
= transaction
->buffer
+
1620 transaction
->iso_packets
[0].offset
+
1621 transaction
->actual_bytes
;
1623 if (pipe
->transfer_dir
== CVMX_USB_DIRECTION_OUT
)
1624 reg
= CVMX_USBNX_DMA0_OUTB_CHN0(usb
->index
);
1626 reg
= CVMX_USBNX_DMA0_INB_CHN0(usb
->index
);
1627 cvmx_write64_uint64(reg
+ channel
* 8, dma_address
);
1630 /* Setup both the size of the transfer and the SPLIT characteristics */
1632 union cvmx_usbcx_hcspltx usbc_hcsplt
= {.u32
= 0};
1633 union cvmx_usbcx_hctsizx usbc_hctsiz
= {.u32
= 0};
1634 int packets_to_transfer
;
1635 int bytes_to_transfer
= transaction
->buffer_length
-
1636 transaction
->actual_bytes
;
1639 * ISOCHRONOUS transactions store each individual transfer size
1640 * in the packet structure, not the global buffer_length
1642 if (transaction
->type
== CVMX_USB_TRANSFER_ISOCHRONOUS
)
1644 transaction
->iso_packets
[0].length
-
1645 transaction
->actual_bytes
;
1648 * We need to do split transactions when we are talking to non
1649 * high speed devices that are behind a high speed hub
1651 if (cvmx_usb_pipe_needs_split(usb
, pipe
)) {
1653 * On the start split phase (stage is even) record the
1654 * frame number we will need to send the split complete.
1655 * We only store the lower two bits since the time ahead
1656 * can only be two frames
1658 if ((transaction
->stage
&1) == 0) {
1659 if (transaction
->type
== CVMX_USB_TRANSFER_BULK
)
1660 pipe
->split_sc_frame
=
1661 (usb
->frame_number
+ 1) & 0x7f;
1663 pipe
->split_sc_frame
=
1664 (usb
->frame_number
+ 2) & 0x7f;
1666 pipe
->split_sc_frame
= -1;
1668 usbc_hcsplt
.s
.spltena
= 1;
1669 usbc_hcsplt
.s
.hubaddr
= pipe
->hub_device_addr
;
1670 usbc_hcsplt
.s
.prtaddr
= pipe
->hub_port
;
1671 usbc_hcsplt
.s
.compsplt
= (transaction
->stage
==
1672 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
);
1675 * SPLIT transactions can only ever transmit one data
1676 * packet so limit the transfer size to the max packet
1679 if (bytes_to_transfer
> pipe
->max_packet
)
1680 bytes_to_transfer
= pipe
->max_packet
;
1683 * ISOCHRONOUS OUT splits are unique in that they limit
1684 * data transfers to 188 byte chunks representing the
1685 * begin/middle/end of the data or all
1687 if (!usbc_hcsplt
.s
.compsplt
&&
1688 (pipe
->transfer_dir
==
1689 CVMX_USB_DIRECTION_OUT
) &&
1690 (pipe
->transfer_type
==
1691 CVMX_USB_TRANSFER_ISOCHRONOUS
)) {
1693 * Clear the split complete frame number as
1694 * there isn't going to be a split complete
1696 pipe
->split_sc_frame
= -1;
1698 * See if we've started this transfer and sent
1701 if (transaction
->actual_bytes
== 0) {
1703 * Nothing sent yet, this is either a
1704 * begin or the entire payload
1706 if (bytes_to_transfer
<= 188)
1707 /* Entire payload in one go */
1708 usbc_hcsplt
.s
.xactpos
= 3;
1710 /* First part of payload */
1711 usbc_hcsplt
.s
.xactpos
= 2;
1714 * Continuing the previous data, we must
1715 * either be in the middle or at the end
1717 if (bytes_to_transfer
<= 188)
1718 /* End of payload */
1719 usbc_hcsplt
.s
.xactpos
= 1;
1721 /* Middle of payload */
1722 usbc_hcsplt
.s
.xactpos
= 0;
1725 * Again, the transfer size is limited to 188
1728 if (bytes_to_transfer
> 188)
1729 bytes_to_transfer
= 188;
1734 * Make sure the transfer never exceeds the byte limit of the
1735 * hardware. Further bytes will be sent as continued
1738 if (bytes_to_transfer
> MAX_TRANSFER_BYTES
) {
1740 * Round MAX_TRANSFER_BYTES to a multiple of out packet
1743 bytes_to_transfer
= MAX_TRANSFER_BYTES
/
1745 bytes_to_transfer
*= pipe
->max_packet
;
1749 * Calculate the number of packets to transfer. If the length is
1750 * zero we still need to transfer one packet
1752 packets_to_transfer
=
1753 DIV_ROUND_UP(bytes_to_transfer
, pipe
->max_packet
);
1754 if (packets_to_transfer
== 0)
1755 packets_to_transfer
= 1;
1756 else if ((packets_to_transfer
> 1) &&
1758 CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)) {
1760 * Limit to one packet when not using DMA. Channels must
1761 * be restarted between every packet for IN
1762 * transactions, so there is no reason to do multiple
1765 packets_to_transfer
= 1;
1766 bytes_to_transfer
= packets_to_transfer
*
1768 } else if (packets_to_transfer
> MAX_TRANSFER_PACKETS
) {
1770 * Limit the number of packet and data transferred to
1771 * what the hardware can handle
1773 packets_to_transfer
= MAX_TRANSFER_PACKETS
;
1774 bytes_to_transfer
= packets_to_transfer
*
1778 usbc_hctsiz
.s
.xfersize
= bytes_to_transfer
;
1779 usbc_hctsiz
.s
.pktcnt
= packets_to_transfer
;
1781 /* Update the DATA0/DATA1 toggle */
1782 usbc_hctsiz
.s
.pid
= cvmx_usb_get_data_pid(pipe
);
1784 * High speed pipes may need a hardware ping before they start
1786 if (pipe
->flags
& CVMX_USB_PIPE_FLAGS_NEED_PING
)
1787 usbc_hctsiz
.s
.dopng
= 1;
1789 cvmx_usb_write_csr32(usb
,
1790 CVMX_USBCX_HCSPLTX(channel
, usb
->index
),
1792 cvmx_usb_write_csr32(usb
,
1793 CVMX_USBCX_HCTSIZX(channel
, usb
->index
),
1797 /* Setup the Host Channel Characteristics Register */
1799 union cvmx_usbcx_hccharx usbc_hcchar
= {.u32
= 0};
1802 * Set the startframe odd/even properly. This is only used for
1805 usbc_hcchar
.s
.oddfrm
= usb
->frame_number
&1;
1808 * Set the number of back to back packets allowed by this
1809 * endpoint. Split transactions interpret "ec" as the number of
1810 * immediate retries of failure. These retries happen too
1811 * quickly, so we disable these entirely for splits
1813 if (cvmx_usb_pipe_needs_split(usb
, pipe
))
1814 usbc_hcchar
.s
.ec
= 1;
1815 else if (pipe
->multi_count
< 1)
1816 usbc_hcchar
.s
.ec
= 1;
1817 else if (pipe
->multi_count
> 3)
1818 usbc_hcchar
.s
.ec
= 3;
1820 usbc_hcchar
.s
.ec
= pipe
->multi_count
;
1822 /* Set the rest of the endpoint specific settings */
1823 usbc_hcchar
.s
.devaddr
= pipe
->device_addr
;
1824 usbc_hcchar
.s
.eptype
= transaction
->type
;
1825 usbc_hcchar
.s
.lspddev
=
1826 (pipe
->device_speed
== CVMX_USB_SPEED_LOW
);
1827 usbc_hcchar
.s
.epdir
= pipe
->transfer_dir
;
1828 usbc_hcchar
.s
.epnum
= pipe
->endpoint_num
;
1829 usbc_hcchar
.s
.mps
= pipe
->max_packet
;
1830 cvmx_usb_write_csr32(usb
,
1831 CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1835 /* Do transaction type specific fixups as needed */
1836 switch (transaction
->type
) {
1837 case CVMX_USB_TRANSFER_CONTROL
:
1838 cvmx_usb_start_channel_control(usb
, channel
, pipe
);
1840 case CVMX_USB_TRANSFER_BULK
:
1841 case CVMX_USB_TRANSFER_INTERRUPT
:
1843 case CVMX_USB_TRANSFER_ISOCHRONOUS
:
1844 if (!cvmx_usb_pipe_needs_split(usb
, pipe
)) {
1846 * ISO transactions require different PIDs depending on
1847 * direction and how many packets are needed
1849 if (pipe
->transfer_dir
== CVMX_USB_DIRECTION_OUT
) {
1850 if (pipe
->multi_count
< 2) /* Need DATA0 */
1852 CVMX_USBCX_HCTSIZX(channel
,
1854 union cvmx_usbcx_hctsizx
,
1856 else /* Need MDATA */
1858 CVMX_USBCX_HCTSIZX(channel
,
1860 union cvmx_usbcx_hctsizx
,
1867 union cvmx_usbcx_hctsizx usbc_hctsiz
= {.u32
=
1868 cvmx_usb_read_csr32(usb
,
1869 CVMX_USBCX_HCTSIZX(channel
, usb
->index
))};
1870 transaction
->xfersize
= usbc_hctsiz
.s
.xfersize
;
1871 transaction
->pktcnt
= usbc_hctsiz
.s
.pktcnt
;
1873 /* Remeber when we start a split transaction */
1874 if (cvmx_usb_pipe_needs_split(usb
, pipe
))
1875 usb
->active_split
= transaction
;
1876 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1877 union cvmx_usbcx_hccharx
, chena
, 1);
1878 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)
1879 cvmx_usb_fill_tx_fifo(usb
, channel
);
1884 * Find a pipe that is ready to be scheduled to hardware.
1885 * @usb: USB device state populated by cvmx_usb_initialize().
1886 * @list: Pipe list to search
1888 * Frame counter to use as a time reference.
1890 * Returns: Pipe or NULL if none are ready
1892 static struct cvmx_usb_pipe
*cvmx_usb_find_ready_pipe(
1893 struct cvmx_usb_state
*usb
,
1894 struct list_head
*list
,
1895 uint64_t current_frame
)
1897 struct cvmx_usb_pipe
*pipe
;
1899 list_for_each_entry(pipe
, list
, node
) {
1900 struct cvmx_usb_transaction
*t
=
1901 list_first_entry(&pipe
->transactions
, typeof(*t
),
1903 if (!(pipe
->flags
& CVMX_USB_PIPE_FLAGS_SCHEDULED
) && t
&&
1904 (pipe
->next_tx_frame
<= current_frame
) &&
1905 ((pipe
->split_sc_frame
== -1) ||
1906 ((((int)current_frame
- (int)pipe
->split_sc_frame
)
1908 (!usb
->active_split
|| (usb
->active_split
== t
))) {
1918 * Called whenever a pipe might need to be scheduled to the
1921 * @usb: USB device state populated by cvmx_usb_initialize().
1922 * @is_sof: True if this schedule was called on a SOF interrupt.
1924 static void cvmx_usb_schedule(struct cvmx_usb_state
*usb
, int is_sof
)
1927 struct cvmx_usb_pipe
*pipe
;
1929 enum cvmx_usb_transfer ttype
;
1931 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
) {
1933 * Without DMA we need to be careful to not schedule something
1934 * at the end of a frame and cause an overrun.
1936 union cvmx_usbcx_hfnum hfnum
= {
1937 .u32
= cvmx_usb_read_csr32(usb
,
1938 CVMX_USBCX_HFNUM(usb
->index
))
1941 union cvmx_usbcx_hfir hfir
= {
1942 .u32
= cvmx_usb_read_csr32(usb
,
1943 CVMX_USBCX_HFIR(usb
->index
))
1946 if (hfnum
.s
.frrem
< hfir
.s
.frint
/4)
1950 while (usb
->idle_hardware_channels
) {
1951 /* Find an idle channel */
1952 channel
= __fls(usb
->idle_hardware_channels
);
1953 if (unlikely(channel
> 7))
1956 /* Find a pipe needing service */
1960 * Only process periodic pipes on SOF interrupts. This
1961 * way we are sure that the periodic data is sent in the
1962 * beginning of the frame
1964 pipe
= cvmx_usb_find_ready_pipe(usb
,
1966 CVMX_USB_TRANSFER_ISOCHRONOUS
,
1969 pipe
= cvmx_usb_find_ready_pipe(usb
,
1971 CVMX_USB_TRANSFER_INTERRUPT
,
1974 if (likely(!pipe
)) {
1975 pipe
= cvmx_usb_find_ready_pipe(usb
,
1977 CVMX_USB_TRANSFER_CONTROL
,
1980 pipe
= cvmx_usb_find_ready_pipe(usb
,
1982 CVMX_USB_TRANSFER_BULK
,
1988 cvmx_usb_start_channel(usb
, channel
, pipe
);
1993 * Only enable SOF interrupts when we have transactions pending in the
1994 * future that might need to be scheduled
1997 for (ttype
= CVMX_USB_TRANSFER_CONTROL
;
1998 ttype
<= CVMX_USB_TRANSFER_INTERRUPT
; ttype
++) {
1999 list_for_each_entry(pipe
, &usb
->active_pipes
[ttype
], node
) {
2000 if (pipe
->next_tx_frame
> usb
->frame_number
) {
2006 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
),
2007 union cvmx_usbcx_gintmsk
, sofmsk
, need_sof
);
2010 static void octeon_usb_urb_complete_callback(struct cvmx_usb_state
*usb
,
2011 enum cvmx_usb_complete status
,
2012 struct cvmx_usb_pipe
*pipe
,
2013 struct cvmx_usb_transaction
2015 int bytes_transferred
,
2018 struct octeon_hcd
*priv
= cvmx_usb_to_octeon(usb
);
2019 struct usb_hcd
*hcd
= octeon_to_hcd(priv
);
2020 struct device
*dev
= hcd
->self
.controller
;
2022 if (likely(status
== CVMX_USB_COMPLETE_SUCCESS
))
2023 urb
->actual_length
= bytes_transferred
;
2025 urb
->actual_length
= 0;
2029 /* For Isochronous transactions we need to update the URB packet status
2030 list from data in our private copy */
2031 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
2034 * The pointer to the private list is stored in the setup_packet
2037 struct cvmx_usb_iso_packet
*iso_packet
=
2038 (struct cvmx_usb_iso_packet
*) urb
->setup_packet
;
2039 /* Recalculate the transfer size by adding up each packet */
2040 urb
->actual_length
= 0;
2041 for (i
= 0; i
< urb
->number_of_packets
; i
++) {
2042 if (iso_packet
[i
].status
==
2043 CVMX_USB_COMPLETE_SUCCESS
) {
2044 urb
->iso_frame_desc
[i
].status
= 0;
2045 urb
->iso_frame_desc
[i
].actual_length
=
2046 iso_packet
[i
].length
;
2047 urb
->actual_length
+=
2048 urb
->iso_frame_desc
[i
].actual_length
;
2050 dev_dbg(dev
, "ISOCHRONOUS packet=%d of %d status=%d pipe=%p transaction=%p size=%d\n",
2051 i
, urb
->number_of_packets
,
2052 iso_packet
[i
].status
, pipe
,
2053 transaction
, iso_packet
[i
].length
);
2054 urb
->iso_frame_desc
[i
].status
= -EREMOTEIO
;
2057 /* Free the private list now that we don't need it anymore */
2059 urb
->setup_packet
= NULL
;
2063 case CVMX_USB_COMPLETE_SUCCESS
:
2066 case CVMX_USB_COMPLETE_CANCEL
:
2067 if (urb
->status
== 0)
2068 urb
->status
= -ENOENT
;
2070 case CVMX_USB_COMPLETE_STALL
:
2071 dev_dbg(dev
, "status=stall pipe=%p transaction=%p size=%d\n",
2072 pipe
, transaction
, bytes_transferred
);
2073 urb
->status
= -EPIPE
;
2075 case CVMX_USB_COMPLETE_BABBLEERR
:
2076 dev_dbg(dev
, "status=babble pipe=%p transaction=%p size=%d\n",
2077 pipe
, transaction
, bytes_transferred
);
2078 urb
->status
= -EPIPE
;
2080 case CVMX_USB_COMPLETE_SHORT
:
2081 dev_dbg(dev
, "status=short pipe=%p transaction=%p size=%d\n",
2082 pipe
, transaction
, bytes_transferred
);
2083 urb
->status
= -EREMOTEIO
;
2085 case CVMX_USB_COMPLETE_ERROR
:
2086 case CVMX_USB_COMPLETE_XACTERR
:
2087 case CVMX_USB_COMPLETE_DATATGLERR
:
2088 case CVMX_USB_COMPLETE_FRAMEERR
:
2089 dev_dbg(dev
, "status=%d pipe=%p transaction=%p size=%d\n",
2090 status
, pipe
, transaction
, bytes_transferred
);
2091 urb
->status
= -EPROTO
;
2094 usb_hcd_unlink_urb_from_ep(octeon_to_hcd(priv
), urb
);
2095 spin_unlock(&priv
->lock
);
2096 usb_hcd_giveback_urb(octeon_to_hcd(priv
), urb
, urb
->status
);
2097 spin_lock(&priv
->lock
);
2101 * Signal the completion of a transaction and free it. The
2102 * transaction will be removed from the pipe transaction list.
2104 * @usb: USB device state populated by cvmx_usb_initialize().
2105 * @pipe: Pipe the transaction is on
2107 * Transaction that completed
2111 static void cvmx_usb_perform_complete(struct cvmx_usb_state
*usb
,
2112 struct cvmx_usb_pipe
*pipe
,
2113 struct cvmx_usb_transaction
*transaction
,
2114 enum cvmx_usb_complete complete_code
)
2116 /* If this was a split then clear our split in progress marker */
2117 if (usb
->active_split
== transaction
)
2118 usb
->active_split
= NULL
;
2121 * Isochronous transactions need extra processing as they might not be
2122 * done after a single data transfer
2124 if (unlikely(transaction
->type
== CVMX_USB_TRANSFER_ISOCHRONOUS
)) {
2125 /* Update the number of bytes transferred in this ISO packet */
2126 transaction
->iso_packets
[0].length
= transaction
->actual_bytes
;
2127 transaction
->iso_packets
[0].status
= complete_code
;
2130 * If there are more ISOs pending and we succeeded, schedule the
2133 if ((transaction
->iso_number_packets
> 1) &&
2134 (complete_code
== CVMX_USB_COMPLETE_SUCCESS
)) {
2135 /* No bytes transferred for this packet as of yet */
2136 transaction
->actual_bytes
= 0;
2137 /* One less ISO waiting to transfer */
2138 transaction
->iso_number_packets
--;
2139 /* Increment to the next location in our packet array */
2140 transaction
->iso_packets
++;
2141 transaction
->stage
= CVMX_USB_STAGE_NON_CONTROL
;
2146 /* Remove the transaction from the pipe list */
2147 list_del(&transaction
->node
);
2148 if (list_empty(&pipe
->transactions
))
2149 list_move_tail(&pipe
->node
, &usb
->idle_pipes
);
2150 octeon_usb_urb_complete_callback(usb
, complete_code
, pipe
,
2152 transaction
->actual_bytes
,
2159 * Submit a usb transaction to a pipe. Called for all types
2163 * @pipe: Which pipe to submit to.
2164 * @type: Transaction type
2165 * @buffer: User buffer for the transaction
2167 * User buffer's length in bytes
2169 * For control transactions, the 8 byte standard header
2171 * For ISO transactions, the start frame
2172 * @iso_number_packets:
2173 * For ISO, the number of packet in the transaction.
2175 * A description of each ISO packet
2176 * @urb: URB for the callback
2178 * Returns: Transaction or NULL on failure.
2180 static struct cvmx_usb_transaction
*cvmx_usb_submit_transaction(
2181 struct cvmx_usb_state
*usb
,
2182 struct cvmx_usb_pipe
*pipe
,
2183 enum cvmx_usb_transfer type
,
2186 uint64_t control_header
,
2187 int iso_start_frame
,
2188 int iso_number_packets
,
2189 struct cvmx_usb_iso_packet
*iso_packets
,
2192 struct cvmx_usb_transaction
*transaction
;
2194 if (unlikely(pipe
->transfer_type
!= type
))
2197 transaction
= kzalloc(sizeof(*transaction
), GFP_ATOMIC
);
2198 if (unlikely(!transaction
))
2201 transaction
->type
= type
;
2202 transaction
->buffer
= buffer
;
2203 transaction
->buffer_length
= buffer_length
;
2204 transaction
->control_header
= control_header
;
2205 /* FIXME: This is not used, implement it. */
2206 transaction
->iso_start_frame
= iso_start_frame
;
2207 transaction
->iso_number_packets
= iso_number_packets
;
2208 transaction
->iso_packets
= iso_packets
;
2209 transaction
->urb
= urb
;
2210 if (transaction
->type
== CVMX_USB_TRANSFER_CONTROL
)
2211 transaction
->stage
= CVMX_USB_STAGE_SETUP
;
2213 transaction
->stage
= CVMX_USB_STAGE_NON_CONTROL
;
2215 if (!list_empty(&pipe
->transactions
)) {
2216 list_add_tail(&transaction
->node
, &pipe
->transactions
);
2218 list_add_tail(&transaction
->node
, &pipe
->transactions
);
2219 list_move_tail(&pipe
->node
,
2220 &usb
->active_pipes
[pipe
->transfer_type
]);
2223 * We may need to schedule the pipe if this was the head of the
2226 cvmx_usb_schedule(usb
, 0);
2234 * Call to submit a USB Bulk transfer to a pipe.
2236 * @usb: USB device state populated by cvmx_usb_initialize().
2237 * @pipe: Handle to the pipe for the transfer.
2240 * Returns: A submitted transaction or NULL on failure.
2242 static struct cvmx_usb_transaction
*cvmx_usb_submit_bulk(
2243 struct cvmx_usb_state
*usb
,
2244 struct cvmx_usb_pipe
*pipe
,
2247 return cvmx_usb_submit_transaction(usb
, pipe
, CVMX_USB_TRANSFER_BULK
,
2249 urb
->transfer_buffer_length
,
2250 0, /* control_header */
2251 0, /* iso_start_frame */
2252 0, /* iso_number_packets */
2253 NULL
, /* iso_packets */
2259 * Call to submit a USB Interrupt transfer to a pipe.
2261 * @usb: USB device state populated by cvmx_usb_initialize().
2262 * @pipe: Handle to the pipe for the transfer.
2263 * @urb: URB returned when the callback is called.
2265 * Returns: A submitted transaction or NULL on failure.
2267 static struct cvmx_usb_transaction
*cvmx_usb_submit_interrupt(
2268 struct cvmx_usb_state
*usb
,
2269 struct cvmx_usb_pipe
*pipe
,
2272 return cvmx_usb_submit_transaction(usb
, pipe
,
2273 CVMX_USB_TRANSFER_INTERRUPT
,
2275 urb
->transfer_buffer_length
,
2276 0, /* control_header */
2277 0, /* iso_start_frame */
2278 0, /* iso_number_packets */
2279 NULL
, /* iso_packets */
2285 * Call to submit a USB Control transfer to a pipe.
2287 * @usb: USB device state populated by cvmx_usb_initialize().
2288 * @pipe: Handle to the pipe for the transfer.
2291 * Returns: A submitted transaction or NULL on failure.
2293 static struct cvmx_usb_transaction
*cvmx_usb_submit_control(
2294 struct cvmx_usb_state
*usb
,
2295 struct cvmx_usb_pipe
*pipe
,
2298 int buffer_length
= urb
->transfer_buffer_length
;
2299 uint64_t control_header
= urb
->setup_dma
;
2300 struct usb_ctrlrequest
*header
= cvmx_phys_to_ptr(control_header
);
2302 if ((header
->bRequestType
& USB_DIR_IN
) == 0)
2303 buffer_length
= le16_to_cpu(header
->wLength
);
2305 return cvmx_usb_submit_transaction(usb
, pipe
,
2306 CVMX_USB_TRANSFER_CONTROL
,
2307 urb
->transfer_dma
, buffer_length
,
2309 0, /* iso_start_frame */
2310 0, /* iso_number_packets */
2311 NULL
, /* iso_packets */
2317 * Call to submit a USB Isochronous transfer to a pipe.
2319 * @usb: USB device state populated by cvmx_usb_initialize().
2320 * @pipe: Handle to the pipe for the transfer.
2321 * @urb: URB returned when the callback is called.
2323 * Returns: A submitted transaction or NULL on failure.
2325 static struct cvmx_usb_transaction
*cvmx_usb_submit_isochronous(
2326 struct cvmx_usb_state
*usb
,
2327 struct cvmx_usb_pipe
*pipe
,
2330 struct cvmx_usb_iso_packet
*packets
;
2332 packets
= (struct cvmx_usb_iso_packet
*) urb
->setup_packet
;
2333 return cvmx_usb_submit_transaction(usb
, pipe
,
2334 CVMX_USB_TRANSFER_ISOCHRONOUS
,
2336 urb
->transfer_buffer_length
,
2337 0, /* control_header */
2339 urb
->number_of_packets
,
2345 * Cancel one outstanding request in a pipe. Canceling a request
2346 * can fail if the transaction has already completed before cancel
2347 * is called. Even after a successful cancel call, it may take
2348 * a frame or two for the cvmx_usb_poll() function to call the
2349 * associated callback.
2351 * @usb: USB device state populated by cvmx_usb_initialize().
2352 * @pipe: Pipe to cancel requests in.
2353 * @transaction: Transaction to cancel, returned by the submit function.
2355 * Returns: 0 or a negative error code.
2357 static int cvmx_usb_cancel(struct cvmx_usb_state
*usb
,
2358 struct cvmx_usb_pipe
*pipe
,
2359 struct cvmx_usb_transaction
*transaction
)
2362 * If the transaction is the HEAD of the queue and scheduled. We need to
2365 if (list_first_entry(&pipe
->transactions
, typeof(*transaction
), node
) ==
2366 transaction
&& (pipe
->flags
& CVMX_USB_PIPE_FLAGS_SCHEDULED
)) {
2367 union cvmx_usbcx_hccharx usbc_hcchar
;
2369 usb
->pipe_for_channel
[pipe
->channel
] = NULL
;
2370 pipe
->flags
&= ~CVMX_USB_PIPE_FLAGS_SCHEDULED
;
2374 usbc_hcchar
.u32
= cvmx_usb_read_csr32(usb
,
2375 CVMX_USBCX_HCCHARX(pipe
->channel
, usb
->index
));
2377 * If the channel isn't enabled then the transaction already
2380 if (usbc_hcchar
.s
.chena
) {
2381 usbc_hcchar
.s
.chdis
= 1;
2382 cvmx_usb_write_csr32(usb
,
2383 CVMX_USBCX_HCCHARX(pipe
->channel
,
2388 cvmx_usb_perform_complete(usb
, pipe
, transaction
,
2389 CVMX_USB_COMPLETE_CANCEL
);
2395 * Cancel all outstanding requests in a pipe. Logically all this
2396 * does is call cvmx_usb_cancel() in a loop.
2398 * @usb: USB device state populated by cvmx_usb_initialize().
2399 * @pipe: Pipe to cancel requests in.
2401 * Returns: 0 or a negative error code.
2403 static int cvmx_usb_cancel_all(struct cvmx_usb_state
*usb
,
2404 struct cvmx_usb_pipe
*pipe
)
2406 struct cvmx_usb_transaction
*transaction
, *next
;
2408 /* Simply loop through and attempt to cancel each transaction */
2409 list_for_each_entry_safe(transaction
, next
, &pipe
->transactions
, node
) {
2410 int result
= cvmx_usb_cancel(usb
, pipe
, transaction
);
2412 if (unlikely(result
!= 0))
2420 * Close a pipe created with cvmx_usb_open_pipe().
2422 * @usb: USB device state populated by cvmx_usb_initialize().
2423 * @pipe: Pipe to close.
2425 * Returns: 0 or a negative error code. EBUSY is returned if the pipe has
2426 * outstanding transfers.
2428 static int cvmx_usb_close_pipe(struct cvmx_usb_state
*usb
,
2429 struct cvmx_usb_pipe
*pipe
)
2431 /* Fail if the pipe has pending transactions */
2432 if (!list_empty(&pipe
->transactions
))
2435 list_del(&pipe
->node
);
2442 * Get the current USB protocol level frame number. The frame
2443 * number is always in the range of 0-0x7ff.
2445 * @usb: USB device state populated by cvmx_usb_initialize().
2447 * Returns: USB frame number
2449 static int cvmx_usb_get_frame_number(struct cvmx_usb_state
*usb
)
2452 union cvmx_usbcx_hfnum usbc_hfnum
;
2454 usbc_hfnum
.u32
= cvmx_usb_read_csr32(usb
, CVMX_USBCX_HFNUM(usb
->index
));
2455 frame_number
= usbc_hfnum
.s
.frnum
;
2457 return frame_number
;
2462 * Poll a channel for status
2465 * @channel: Channel to poll
2467 * Returns: Zero on success
2469 static int cvmx_usb_poll_channel(struct cvmx_usb_state
*usb
, int channel
)
2471 struct octeon_hcd
*priv
= cvmx_usb_to_octeon(usb
);
2472 struct usb_hcd
*hcd
= octeon_to_hcd(priv
);
2473 struct device
*dev
= hcd
->self
.controller
;
2474 union cvmx_usbcx_hcintx usbc_hcint
;
2475 union cvmx_usbcx_hctsizx usbc_hctsiz
;
2476 union cvmx_usbcx_hccharx usbc_hcchar
;
2477 struct cvmx_usb_pipe
*pipe
;
2478 struct cvmx_usb_transaction
*transaction
;
2479 int bytes_this_transfer
;
2480 int bytes_in_last_packet
;
2481 int packets_processed
;
2482 int buffer_space_left
;
2484 /* Read the interrupt status bits for the channel */
2485 usbc_hcint
.u32
= cvmx_usb_read_csr32(usb
,
2486 CVMX_USBCX_HCINTX(channel
, usb
->index
));
2488 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
) {
2489 usbc_hcchar
.u32
= cvmx_usb_read_csr32(usb
,
2490 CVMX_USBCX_HCCHARX(channel
, usb
->index
));
2492 if (usbc_hcchar
.s
.chena
&& usbc_hcchar
.s
.chdis
) {
2494 * There seems to be a bug in CN31XX which can cause
2495 * interrupt IN transfers to get stuck until we do a
2496 * write of HCCHARX without changing things
2498 cvmx_usb_write_csr32(usb
,
2499 CVMX_USBCX_HCCHARX(channel
,
2506 * In non DMA mode the channels don't halt themselves. We need
2507 * to manually disable channels that are left running
2509 if (!usbc_hcint
.s
.chhltd
) {
2510 if (usbc_hcchar
.s
.chena
) {
2511 union cvmx_usbcx_hcintmskx hcintmsk
;
2512 /* Disable all interrupts except CHHLTD */
2514 hcintmsk
.s
.chhltdmsk
= 1;
2515 cvmx_usb_write_csr32(usb
,
2516 CVMX_USBCX_HCINTMSKX(channel
,
2519 usbc_hcchar
.s
.chdis
= 1;
2520 cvmx_usb_write_csr32(usb
,
2521 CVMX_USBCX_HCCHARX(channel
,
2525 } else if (usbc_hcint
.s
.xfercompl
) {
2527 * Successful IN/OUT with transfer complete.
2528 * Channel halt isn't needed.
2531 dev_err(dev
, "USB%d: Channel %d interrupt without halt\n",
2532 usb
->index
, channel
);
2538 * There is are no interrupts that we need to process when the
2539 * channel is still running
2541 if (!usbc_hcint
.s
.chhltd
)
2545 /* Disable the channel interrupts now that it is done */
2546 cvmx_usb_write_csr32(usb
, CVMX_USBCX_HCINTMSKX(channel
, usb
->index
), 0);
2547 usb
->idle_hardware_channels
|= (1<<channel
);
2549 /* Make sure this channel is tied to a valid pipe */
2550 pipe
= usb
->pipe_for_channel
[channel
];
2554 transaction
= list_first_entry(&pipe
->transactions
,
2555 typeof(*transaction
),
2557 prefetch(transaction
);
2560 * Disconnect this pipe from the HW channel. Later the schedule
2561 * function will figure out which pipe needs to go
2563 usb
->pipe_for_channel
[channel
] = NULL
;
2564 pipe
->flags
&= ~CVMX_USB_PIPE_FLAGS_SCHEDULED
;
2567 * Read the channel config info so we can figure out how much data
2570 usbc_hcchar
.u32
= cvmx_usb_read_csr32(usb
,
2571 CVMX_USBCX_HCCHARX(channel
, usb
->index
));
2572 usbc_hctsiz
.u32
= cvmx_usb_read_csr32(usb
,
2573 CVMX_USBCX_HCTSIZX(channel
, usb
->index
));
2576 * Calculating the number of bytes successfully transferred is dependent
2577 * on the transfer direction
2579 packets_processed
= transaction
->pktcnt
- usbc_hctsiz
.s
.pktcnt
;
2580 if (usbc_hcchar
.s
.epdir
) {
2582 * IN transactions are easy. For every byte received the
2583 * hardware decrements xfersize. All we need to do is subtract
2584 * the current value of xfersize from its starting value and we
2585 * know how many bytes were written to the buffer
2587 bytes_this_transfer
= transaction
->xfersize
-
2588 usbc_hctsiz
.s
.xfersize
;
2591 * OUT transaction don't decrement xfersize. Instead pktcnt is
2592 * decremented on every successful packet send. The hardware
2593 * does this when it receives an ACK, or NYET. If it doesn't
2594 * receive one of these responses pktcnt doesn't change
2596 bytes_this_transfer
= packets_processed
* usbc_hcchar
.s
.mps
;
2598 * The last packet may not be a full transfer if we didn't have
2601 if (bytes_this_transfer
> transaction
->xfersize
)
2602 bytes_this_transfer
= transaction
->xfersize
;
2604 /* Figure out how many bytes were in the last packet of the transfer */
2605 if (packets_processed
)
2606 bytes_in_last_packet
= bytes_this_transfer
-
2607 (packets_processed
- 1) * usbc_hcchar
.s
.mps
;
2609 bytes_in_last_packet
= bytes_this_transfer
;
2612 * As a special case, setup transactions output the setup header, not
2613 * the user's data. For this reason we don't count setup data as bytes
2616 if ((transaction
->stage
== CVMX_USB_STAGE_SETUP
) ||
2617 (transaction
->stage
== CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE
))
2618 bytes_this_transfer
= 0;
2621 * Add the bytes transferred to the running total. It is important that
2622 * bytes_this_transfer doesn't count any data that needs to be
2625 transaction
->actual_bytes
+= bytes_this_transfer
;
2626 if (transaction
->type
== CVMX_USB_TRANSFER_ISOCHRONOUS
)
2627 buffer_space_left
= transaction
->iso_packets
[0].length
-
2628 transaction
->actual_bytes
;
2630 buffer_space_left
= transaction
->buffer_length
-
2631 transaction
->actual_bytes
;
2634 * We need to remember the PID toggle state for the next transaction.
2635 * The hardware already updated it for the next transaction
2637 pipe
->pid_toggle
= !(usbc_hctsiz
.s
.pid
== 0);
2640 * For high speed bulk out, assume the next transaction will need to do
2641 * a ping before proceeding. If this isn't true the ACK processing below
2642 * will clear this flag
2644 if ((pipe
->device_speed
== CVMX_USB_SPEED_HIGH
) &&
2645 (pipe
->transfer_type
== CVMX_USB_TRANSFER_BULK
) &&
2646 (pipe
->transfer_dir
== CVMX_USB_DIRECTION_OUT
))
2647 pipe
->flags
|= CVMX_USB_PIPE_FLAGS_NEED_PING
;
2649 if (usbc_hcint
.s
.stall
) {
2651 * STALL as a response means this transaction cannot be
2652 * completed because the device can't process transactions. Tell
2653 * the user. Any data that was transferred will be counted on
2654 * the actual bytes transferred
2656 pipe
->pid_toggle
= 0;
2657 cvmx_usb_perform_complete(usb
, pipe
, transaction
,
2658 CVMX_USB_COMPLETE_STALL
);
2659 } else if (usbc_hcint
.s
.xacterr
) {
2661 * XactErr as a response means the device signaled
2662 * something wrong with the transfer. For example, PID
2663 * toggle errors cause these.
2665 cvmx_usb_perform_complete(usb
, pipe
, transaction
,
2666 CVMX_USB_COMPLETE_XACTERR
);
2667 } else if (usbc_hcint
.s
.bblerr
) {
2668 /* Babble Error (BblErr) */
2669 cvmx_usb_perform_complete(usb
, pipe
, transaction
,
2670 CVMX_USB_COMPLETE_BABBLEERR
);
2671 } else if (usbc_hcint
.s
.datatglerr
) {
2672 /* Data toggle error */
2673 cvmx_usb_perform_complete(usb
, pipe
, transaction
,
2674 CVMX_USB_COMPLETE_DATATGLERR
);
2675 } else if (usbc_hcint
.s
.nyet
) {
2677 * NYET as a response is only allowed in three cases: as a
2678 * response to a ping, as a response to a split transaction, and
2679 * as a response to a bulk out. The ping case is handled by
2680 * hardware, so we only have splits and bulk out
2682 if (!cvmx_usb_pipe_needs_split(usb
, pipe
)) {
2683 transaction
->retries
= 0;
2685 * If there is more data to go then we need to try
2686 * again. Otherwise this transaction is complete
2688 if ((buffer_space_left
== 0) ||
2689 (bytes_in_last_packet
< pipe
->max_packet
))
2690 cvmx_usb_perform_complete(usb
, pipe
,
2692 CVMX_USB_COMPLETE_SUCCESS
);
2695 * Split transactions retry the split complete 4 times
2696 * then rewind to the start split and do the entire
2697 * transactions again
2699 transaction
->retries
++;
2700 if ((transaction
->retries
& 0x3) == 0) {
2702 * Rewind to the beginning of the transaction by
2703 * anding off the split complete bit
2705 transaction
->stage
&= ~1;
2706 pipe
->split_sc_frame
= -1;
2709 } else if (usbc_hcint
.s
.ack
) {
2710 transaction
->retries
= 0;
2712 * The ACK bit can only be checked after the other error bits.
2713 * This is because a multi packet transfer may succeed in a
2714 * number of packets and then get a different response on the
2715 * last packet. In this case both ACK and the last response bit
2716 * will be set. If none of the other response bits is set, then
2717 * the last packet must have been an ACK
2719 * Since we got an ACK, we know we don't need to do a ping on
2722 pipe
->flags
&= ~CVMX_USB_PIPE_FLAGS_NEED_PING
;
2724 switch (transaction
->type
) {
2725 case CVMX_USB_TRANSFER_CONTROL
:
2726 switch (transaction
->stage
) {
2727 case CVMX_USB_STAGE_NON_CONTROL
:
2728 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
:
2729 /* This should be impossible */
2730 cvmx_usb_perform_complete(usb
, pipe
,
2731 transaction
, CVMX_USB_COMPLETE_ERROR
);
2733 case CVMX_USB_STAGE_SETUP
:
2734 pipe
->pid_toggle
= 1;
2735 if (cvmx_usb_pipe_needs_split(usb
, pipe
))
2736 transaction
->stage
=
2737 CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE
;
2739 struct usb_ctrlrequest
*header
=
2740 cvmx_phys_to_ptr(transaction
->control_header
);
2741 if (header
->wLength
)
2742 transaction
->stage
=
2743 CVMX_USB_STAGE_DATA
;
2745 transaction
->stage
=
2746 CVMX_USB_STAGE_STATUS
;
2749 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE
:
2751 struct usb_ctrlrequest
*header
=
2752 cvmx_phys_to_ptr(transaction
->control_header
);
2753 if (header
->wLength
)
2754 transaction
->stage
=
2755 CVMX_USB_STAGE_DATA
;
2757 transaction
->stage
=
2758 CVMX_USB_STAGE_STATUS
;
2761 case CVMX_USB_STAGE_DATA
:
2762 if (cvmx_usb_pipe_needs_split(usb
, pipe
)) {
2763 transaction
->stage
=
2764 CVMX_USB_STAGE_DATA_SPLIT_COMPLETE
;
2766 * For setup OUT data that are splits,
2767 * the hardware doesn't appear to count
2768 * transferred data. Here we manually
2769 * update the data transferred
2771 if (!usbc_hcchar
.s
.epdir
) {
2772 if (buffer_space_left
< pipe
->max_packet
)
2773 transaction
->actual_bytes
+=
2776 transaction
->actual_bytes
+=
2779 } else if ((buffer_space_left
== 0) ||
2780 (bytes_in_last_packet
<
2781 pipe
->max_packet
)) {
2782 pipe
->pid_toggle
= 1;
2783 transaction
->stage
=
2784 CVMX_USB_STAGE_STATUS
;
2787 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE
:
2788 if ((buffer_space_left
== 0) ||
2789 (bytes_in_last_packet
<
2790 pipe
->max_packet
)) {
2791 pipe
->pid_toggle
= 1;
2792 transaction
->stage
=
2793 CVMX_USB_STAGE_STATUS
;
2795 transaction
->stage
=
2796 CVMX_USB_STAGE_DATA
;
2799 case CVMX_USB_STAGE_STATUS
:
2800 if (cvmx_usb_pipe_needs_split(usb
, pipe
))
2801 transaction
->stage
=
2802 CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE
;
2804 cvmx_usb_perform_complete(usb
, pipe
,
2806 CVMX_USB_COMPLETE_SUCCESS
);
2808 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE
:
2809 cvmx_usb_perform_complete(usb
, pipe
,
2811 CVMX_USB_COMPLETE_SUCCESS
);
2815 case CVMX_USB_TRANSFER_BULK
:
2816 case CVMX_USB_TRANSFER_INTERRUPT
:
2818 * The only time a bulk transfer isn't complete when it
2819 * finishes with an ACK is during a split transaction.
2820 * For splits we need to continue the transfer if more
2823 if (cvmx_usb_pipe_needs_split(usb
, pipe
)) {
2824 if (transaction
->stage
==
2825 CVMX_USB_STAGE_NON_CONTROL
)
2826 transaction
->stage
=
2827 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
;
2829 if (buffer_space_left
&&
2830 (bytes_in_last_packet
==
2832 transaction
->stage
=
2833 CVMX_USB_STAGE_NON_CONTROL
;
2835 if (transaction
->type
==
2836 CVMX_USB_TRANSFER_INTERRUPT
)
2837 pipe
->next_tx_frame
+=
2839 cvmx_usb_perform_complete(
2843 CVMX_USB_COMPLETE_SUCCESS
);
2847 if ((pipe
->device_speed
==
2848 CVMX_USB_SPEED_HIGH
) &&
2849 (pipe
->transfer_type
==
2850 CVMX_USB_TRANSFER_BULK
) &&
2851 (pipe
->transfer_dir
==
2852 CVMX_USB_DIRECTION_OUT
) &&
2855 CVMX_USB_PIPE_FLAGS_NEED_PING
;
2856 if (!buffer_space_left
||
2857 (bytes_in_last_packet
<
2858 pipe
->max_packet
)) {
2859 if (transaction
->type
==
2860 CVMX_USB_TRANSFER_INTERRUPT
)
2861 pipe
->next_tx_frame
+=
2863 cvmx_usb_perform_complete(usb
, pipe
,
2865 CVMX_USB_COMPLETE_SUCCESS
);
2869 case CVMX_USB_TRANSFER_ISOCHRONOUS
:
2870 if (cvmx_usb_pipe_needs_split(usb
, pipe
)) {
2872 * ISOCHRONOUS OUT splits don't require a
2873 * complete split stage. Instead they use a
2874 * sequence of begin OUT splits to transfer the
2875 * data 188 bytes at a time. Once the transfer
2876 * is complete, the pipe sleeps until the next
2879 if (pipe
->transfer_dir
==
2880 CVMX_USB_DIRECTION_OUT
) {
2882 * If no space left or this wasn't a max
2883 * size packet then this transfer is
2884 * complete. Otherwise start it again to
2885 * send the next 188 bytes
2887 if (!buffer_space_left
||
2888 (bytes_this_transfer
< 188)) {
2889 pipe
->next_tx_frame
+=
2891 cvmx_usb_perform_complete(usb
,
2893 CVMX_USB_COMPLETE_SUCCESS
);
2896 if (transaction
->stage
==
2897 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
) {
2899 * We are in the incoming data
2900 * phase. Keep getting data
2901 * until we run out of space or
2902 * get a small packet
2904 if ((buffer_space_left
== 0) ||
2905 (bytes_in_last_packet
<
2906 pipe
->max_packet
)) {
2907 pipe
->next_tx_frame
+=
2909 cvmx_usb_perform_complete(
2913 CVMX_USB_COMPLETE_SUCCESS
);
2916 transaction
->stage
=
2917 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
;
2920 pipe
->next_tx_frame
+= pipe
->interval
;
2921 cvmx_usb_perform_complete(usb
, pipe
,
2923 CVMX_USB_COMPLETE_SUCCESS
);
2927 } else if (usbc_hcint
.s
.nak
) {
2929 * If this was a split then clear our split in progress marker.
2931 if (usb
->active_split
== transaction
)
2932 usb
->active_split
= NULL
;
2934 * NAK as a response means the device couldn't accept the
2935 * transaction, but it should be retried in the future. Rewind
2936 * to the beginning of the transaction by anding off the split
2937 * complete bit. Retry in the next interval
2939 transaction
->retries
= 0;
2940 transaction
->stage
&= ~1;
2941 pipe
->next_tx_frame
+= pipe
->interval
;
2942 if (pipe
->next_tx_frame
< usb
->frame_number
)
2943 pipe
->next_tx_frame
= usb
->frame_number
+
2945 (usb
->frame_number
- pipe
->next_tx_frame
) %
2948 struct cvmx_usb_port_status port
;
2950 port
= cvmx_usb_get_status(usb
);
2951 if (port
.port_enabled
) {
2952 /* We'll retry the exact same transaction again */
2953 transaction
->retries
++;
2956 * We get channel halted interrupts with no result bits
2957 * sets when the cable is unplugged
2959 cvmx_usb_perform_complete(usb
, pipe
, transaction
,
2960 CVMX_USB_COMPLETE_ERROR
);
2966 static void octeon_usb_port_callback(struct cvmx_usb_state
*usb
)
2968 struct octeon_hcd
*priv
= cvmx_usb_to_octeon(usb
);
2970 spin_unlock(&priv
->lock
);
2971 usb_hcd_poll_rh_status(octeon_to_hcd(priv
));
2972 spin_lock(&priv
->lock
);
2976 * Poll the USB block for status and call all needed callback
2977 * handlers. This function is meant to be called in the interrupt
2978 * handler for the USB controller. It can also be called
2979 * periodically in a loop for non-interrupt based operation.
2981 * @usb: USB device state populated by cvmx_usb_initialize().
2983 * Returns: 0 or a negative error code.
2985 static int cvmx_usb_poll(struct cvmx_usb_state
*usb
)
2987 union cvmx_usbcx_hfnum usbc_hfnum
;
2988 union cvmx_usbcx_gintsts usbc_gintsts
;
2990 prefetch_range(usb
, sizeof(*usb
));
2992 /* Update the frame counter */
2993 usbc_hfnum
.u32
= cvmx_usb_read_csr32(usb
, CVMX_USBCX_HFNUM(usb
->index
));
2994 if ((usb
->frame_number
&0x3fff) > usbc_hfnum
.s
.frnum
)
2995 usb
->frame_number
+= 0x4000;
2996 usb
->frame_number
&= ~0x3fffull
;
2997 usb
->frame_number
|= usbc_hfnum
.s
.frnum
;
2999 /* Read the pending interrupts */
3000 usbc_gintsts
.u32
= cvmx_usb_read_csr32(usb
,
3001 CVMX_USBCX_GINTSTS(usb
->index
));
3003 /* Clear the interrupts now that we know about them */
3004 cvmx_usb_write_csr32(usb
, CVMX_USBCX_GINTSTS(usb
->index
),
3007 if (usbc_gintsts
.s
.rxflvl
) {
3009 * RxFIFO Non-Empty (RxFLvl)
3010 * Indicates that there is at least one packet pending to be
3011 * read from the RxFIFO.
3013 * In DMA mode this is handled by hardware
3015 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)
3016 cvmx_usb_poll_rx_fifo(usb
);
3018 if (usbc_gintsts
.s
.ptxfemp
|| usbc_gintsts
.s
.nptxfemp
) {
3019 /* Fill the Tx FIFOs when not in DMA mode */
3020 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)
3021 cvmx_usb_poll_tx_fifo(usb
);
3023 if (usbc_gintsts
.s
.disconnint
|| usbc_gintsts
.s
.prtint
) {
3024 union cvmx_usbcx_hprt usbc_hprt
;
3026 * Disconnect Detected Interrupt (DisconnInt)
3027 * Asserted when a device disconnect is detected.
3029 * Host Port Interrupt (PrtInt)
3030 * The core sets this bit to indicate a change in port status of
3031 * one of the O2P USB core ports in Host mode. The application
3032 * must read the Host Port Control and Status (HPRT) register to
3033 * determine the exact event that caused this interrupt. The
3034 * application must clear the appropriate status bit in the Host
3035 * Port Control and Status register to clear this bit.
3037 * Call the user's port callback
3039 octeon_usb_port_callback(usb
);
3040 /* Clear the port change bits */
3041 usbc_hprt
.u32
= cvmx_usb_read_csr32(usb
,
3042 CVMX_USBCX_HPRT(usb
->index
));
3043 usbc_hprt
.s
.prtena
= 0;
3044 cvmx_usb_write_csr32(usb
, CVMX_USBCX_HPRT(usb
->index
),
3047 if (usbc_gintsts
.s
.hchint
) {
3049 * Host Channels Interrupt (HChInt)
3050 * The core sets this bit to indicate that an interrupt is
3051 * pending on one of the channels of the core (in Host mode).
3052 * The application must read the Host All Channels Interrupt
3053 * (HAINT) register to determine the exact number of the channel
3054 * on which the interrupt occurred, and then read the
3055 * corresponding Host Channel-n Interrupt (HCINTn) register to
3056 * determine the exact cause of the interrupt. The application
3057 * must clear the appropriate status bit in the HCINTn register
3058 * to clear this bit.
3060 union cvmx_usbcx_haint usbc_haint
;
3062 usbc_haint
.u32
= cvmx_usb_read_csr32(usb
,
3063 CVMX_USBCX_HAINT(usb
->index
));
3064 while (usbc_haint
.u32
) {
3067 channel
= __fls(usbc_haint
.u32
);
3068 cvmx_usb_poll_channel(usb
, channel
);
3069 usbc_haint
.u32
^= 1<<channel
;
3073 cvmx_usb_schedule(usb
, usbc_gintsts
.s
.sof
);
3078 /* convert between an HCD pointer and the corresponding struct octeon_hcd */
3079 static inline struct octeon_hcd
*hcd_to_octeon(struct usb_hcd
*hcd
)
3081 return (struct octeon_hcd
*)(hcd
->hcd_priv
);
3084 static irqreturn_t
octeon_usb_irq(struct usb_hcd
*hcd
)
3086 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3087 unsigned long flags
;
3089 spin_lock_irqsave(&priv
->lock
, flags
);
3090 cvmx_usb_poll(&priv
->usb
);
3091 spin_unlock_irqrestore(&priv
->lock
, flags
);
3095 static int octeon_usb_start(struct usb_hcd
*hcd
)
3097 hcd
->state
= HC_STATE_RUNNING
;
3101 static void octeon_usb_stop(struct usb_hcd
*hcd
)
3103 hcd
->state
= HC_STATE_HALT
;
3106 static int octeon_usb_get_frame_number(struct usb_hcd
*hcd
)
3108 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3110 return cvmx_usb_get_frame_number(&priv
->usb
);
3113 static int octeon_usb_urb_enqueue(struct usb_hcd
*hcd
,
3117 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3118 struct device
*dev
= hcd
->self
.controller
;
3119 struct cvmx_usb_transaction
*transaction
= NULL
;
3120 struct cvmx_usb_pipe
*pipe
;
3121 unsigned long flags
;
3122 struct cvmx_usb_iso_packet
*iso_packet
;
3123 struct usb_host_endpoint
*ep
= urb
->ep
;
3127 spin_lock_irqsave(&priv
->lock
, flags
);
3129 rc
= usb_hcd_link_urb_to_ep(hcd
, urb
);
3131 spin_unlock_irqrestore(&priv
->lock
, flags
);
3136 enum cvmx_usb_transfer transfer_type
;
3137 enum cvmx_usb_speed speed
;
3138 int split_device
= 0;
3141 switch (usb_pipetype(urb
->pipe
)) {
3142 case PIPE_ISOCHRONOUS
:
3143 transfer_type
= CVMX_USB_TRANSFER_ISOCHRONOUS
;
3145 case PIPE_INTERRUPT
:
3146 transfer_type
= CVMX_USB_TRANSFER_INTERRUPT
;
3149 transfer_type
= CVMX_USB_TRANSFER_CONTROL
;
3152 transfer_type
= CVMX_USB_TRANSFER_BULK
;
3155 switch (urb
->dev
->speed
) {
3157 speed
= CVMX_USB_SPEED_LOW
;
3159 case USB_SPEED_FULL
:
3160 speed
= CVMX_USB_SPEED_FULL
;
3163 speed
= CVMX_USB_SPEED_HIGH
;
3167 * For slow devices on high speed ports we need to find the hub
3168 * that does the speed translation so we know where to send the
3169 * split transactions.
3171 if (speed
!= CVMX_USB_SPEED_HIGH
) {
3173 * Start at this device and work our way up the usb
3176 struct usb_device
*dev
= urb
->dev
;
3178 while (dev
->parent
) {
3180 * If our parent is high speed then he'll
3181 * receive the splits.
3183 if (dev
->parent
->speed
== USB_SPEED_HIGH
) {
3184 split_device
= dev
->parent
->devnum
;
3185 split_port
= dev
->portnum
;
3189 * Move up the tree one level. If we make it all
3190 * the way up the tree, then the port must not
3191 * be in high speed mode and we don't need a
3197 pipe
= cvmx_usb_open_pipe(&priv
->usb
, usb_pipedevice(urb
->pipe
),
3198 usb_pipeendpoint(urb
->pipe
), speed
,
3199 le16_to_cpu(ep
->desc
.wMaxPacketSize
)
3202 usb_pipein(urb
->pipe
) ?
3203 CVMX_USB_DIRECTION_IN
:
3204 CVMX_USB_DIRECTION_OUT
,
3206 (le16_to_cpu(ep
->desc
.wMaxPacketSize
)
3208 split_device
, split_port
);
3210 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
3211 spin_unlock_irqrestore(&priv
->lock
, flags
);
3212 dev_dbg(dev
, "Failed to create pipe\n");
3220 switch (usb_pipetype(urb
->pipe
)) {
3221 case PIPE_ISOCHRONOUS
:
3222 dev_dbg(dev
, "Submit isochronous to %d.%d\n",
3223 usb_pipedevice(urb
->pipe
),
3224 usb_pipeendpoint(urb
->pipe
));
3226 * Allocate a structure to use for our private list of
3227 * isochronous packets.
3229 iso_packet
= kmalloc(urb
->number_of_packets
*
3230 sizeof(struct cvmx_usb_iso_packet
),
3234 /* Fill the list with the data from the URB */
3235 for (i
= 0; i
< urb
->number_of_packets
; i
++) {
3236 iso_packet
[i
].offset
=
3237 urb
->iso_frame_desc
[i
].offset
;
3238 iso_packet
[i
].length
=
3239 urb
->iso_frame_desc
[i
].length
;
3240 iso_packet
[i
].status
=
3241 CVMX_USB_COMPLETE_ERROR
;
3244 * Store a pointer to the list in the URB setup_packet
3245 * field. We know this currently isn't being used and
3246 * this saves us a bunch of logic.
3248 urb
->setup_packet
= (char *)iso_packet
;
3249 transaction
= cvmx_usb_submit_isochronous(&priv
->usb
,
3252 * If submit failed we need to free our private packet
3256 urb
->setup_packet
= NULL
;
3261 case PIPE_INTERRUPT
:
3262 dev_dbg(dev
, "Submit interrupt to %d.%d\n",
3263 usb_pipedevice(urb
->pipe
),
3264 usb_pipeendpoint(urb
->pipe
));
3265 transaction
= cvmx_usb_submit_interrupt(&priv
->usb
, pipe
, urb
);
3268 dev_dbg(dev
, "Submit control to %d.%d\n",
3269 usb_pipedevice(urb
->pipe
),
3270 usb_pipeendpoint(urb
->pipe
));
3271 transaction
= cvmx_usb_submit_control(&priv
->usb
, pipe
, urb
);
3274 dev_dbg(dev
, "Submit bulk to %d.%d\n",
3275 usb_pipedevice(urb
->pipe
),
3276 usb_pipeendpoint(urb
->pipe
));
3277 transaction
= cvmx_usb_submit_bulk(&priv
->usb
, pipe
, urb
);
3281 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
3282 spin_unlock_irqrestore(&priv
->lock
, flags
);
3283 dev_dbg(dev
, "Failed to submit\n");
3286 urb
->hcpriv
= transaction
;
3287 spin_unlock_irqrestore(&priv
->lock
, flags
);
3291 static int octeon_usb_urb_dequeue(struct usb_hcd
*hcd
,
3295 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3296 unsigned long flags
;
3302 spin_lock_irqsave(&priv
->lock
, flags
);
3304 rc
= usb_hcd_check_unlink_urb(hcd
, urb
, status
);
3308 urb
->status
= status
;
3309 cvmx_usb_cancel(&priv
->usb
, urb
->ep
->hcpriv
, urb
->hcpriv
);
3312 spin_unlock_irqrestore(&priv
->lock
, flags
);
3317 static void octeon_usb_endpoint_disable(struct usb_hcd
*hcd
,
3318 struct usb_host_endpoint
*ep
)
3320 struct device
*dev
= hcd
->self
.controller
;
3323 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3324 struct cvmx_usb_pipe
*pipe
= ep
->hcpriv
;
3325 unsigned long flags
;
3327 spin_lock_irqsave(&priv
->lock
, flags
);
3328 cvmx_usb_cancel_all(&priv
->usb
, pipe
);
3329 if (cvmx_usb_close_pipe(&priv
->usb
, pipe
))
3330 dev_dbg(dev
, "Closing pipe %p failed\n", pipe
);
3331 spin_unlock_irqrestore(&priv
->lock
, flags
);
3336 static int octeon_usb_hub_status_data(struct usb_hcd
*hcd
, char *buf
)
3338 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3339 struct cvmx_usb_port_status port_status
;
3340 unsigned long flags
;
3342 spin_lock_irqsave(&priv
->lock
, flags
);
3343 port_status
= cvmx_usb_get_status(&priv
->usb
);
3344 spin_unlock_irqrestore(&priv
->lock
, flags
);
3346 buf
[0] = port_status
.connect_change
<< 1;
3351 static int octeon_usb_hub_control(struct usb_hcd
*hcd
, u16 typeReq
, u16 wValue
,
3352 u16 wIndex
, char *buf
, u16 wLength
)
3354 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3355 struct device
*dev
= hcd
->self
.controller
;
3356 struct cvmx_usb_port_status usb_port_status
;
3358 struct usb_hub_descriptor
*desc
;
3359 unsigned long flags
;
3362 case ClearHubFeature
:
3363 dev_dbg(dev
, "ClearHubFeature\n");
3365 case C_HUB_LOCAL_POWER
:
3366 case C_HUB_OVER_CURRENT
:
3367 /* Nothing required here */
3373 case ClearPortFeature
:
3374 dev_dbg(dev
, "ClearPortFeature\n");
3376 dev_dbg(dev
, " INVALID\n");
3381 case USB_PORT_FEAT_ENABLE
:
3382 dev_dbg(dev
, " ENABLE\n");
3383 spin_lock_irqsave(&priv
->lock
, flags
);
3384 cvmx_usb_disable(&priv
->usb
);
3385 spin_unlock_irqrestore(&priv
->lock
, flags
);
3387 case USB_PORT_FEAT_SUSPEND
:
3388 dev_dbg(dev
, " SUSPEND\n");
3389 /* Not supported on Octeon */
3391 case USB_PORT_FEAT_POWER
:
3392 dev_dbg(dev
, " POWER\n");
3393 /* Not supported on Octeon */
3395 case USB_PORT_FEAT_INDICATOR
:
3396 dev_dbg(dev
, " INDICATOR\n");
3397 /* Port inidicator not supported */
3399 case USB_PORT_FEAT_C_CONNECTION
:
3400 dev_dbg(dev
, " C_CONNECTION\n");
3401 /* Clears drivers internal connect status change flag */
3402 spin_lock_irqsave(&priv
->lock
, flags
);
3403 priv
->usb
.port_status
=
3404 cvmx_usb_get_status(&priv
->usb
);
3405 spin_unlock_irqrestore(&priv
->lock
, flags
);
3407 case USB_PORT_FEAT_C_RESET
:
3408 dev_dbg(dev
, " C_RESET\n");
3410 * Clears the driver's internal Port Reset Change flag.
3412 spin_lock_irqsave(&priv
->lock
, flags
);
3413 priv
->usb
.port_status
=
3414 cvmx_usb_get_status(&priv
->usb
);
3415 spin_unlock_irqrestore(&priv
->lock
, flags
);
3417 case USB_PORT_FEAT_C_ENABLE
:
3418 dev_dbg(dev
, " C_ENABLE\n");
3420 * Clears the driver's internal Port Enable/Disable
3423 spin_lock_irqsave(&priv
->lock
, flags
);
3424 priv
->usb
.port_status
=
3425 cvmx_usb_get_status(&priv
->usb
);
3426 spin_unlock_irqrestore(&priv
->lock
, flags
);
3428 case USB_PORT_FEAT_C_SUSPEND
:
3429 dev_dbg(dev
, " C_SUSPEND\n");
3431 * Clears the driver's internal Port Suspend Change
3432 * flag, which is set when resume signaling on the host
3436 case USB_PORT_FEAT_C_OVER_CURRENT
:
3437 dev_dbg(dev
, " C_OVER_CURRENT\n");
3438 /* Clears the driver's overcurrent Change flag */
3439 spin_lock_irqsave(&priv
->lock
, flags
);
3440 priv
->usb
.port_status
=
3441 cvmx_usb_get_status(&priv
->usb
);
3442 spin_unlock_irqrestore(&priv
->lock
, flags
);
3445 dev_dbg(dev
, " UNKNOWN\n");
3449 case GetHubDescriptor
:
3450 dev_dbg(dev
, "GetHubDescriptor\n");
3451 desc
= (struct usb_hub_descriptor
*)buf
;
3452 desc
->bDescLength
= 9;
3453 desc
->bDescriptorType
= 0x29;
3454 desc
->bNbrPorts
= 1;
3455 desc
->wHubCharacteristics
= cpu_to_le16(0x08);
3456 desc
->bPwrOn2PwrGood
= 1;
3457 desc
->bHubContrCurrent
= 0;
3458 desc
->u
.hs
.DeviceRemovable
[0] = 0;
3459 desc
->u
.hs
.DeviceRemovable
[1] = 0xff;
3462 dev_dbg(dev
, "GetHubStatus\n");
3463 *(__le32
*) buf
= 0;
3466 dev_dbg(dev
, "GetPortStatus\n");
3468 dev_dbg(dev
, " INVALID\n");
3472 spin_lock_irqsave(&priv
->lock
, flags
);
3473 usb_port_status
= cvmx_usb_get_status(&priv
->usb
);
3474 spin_unlock_irqrestore(&priv
->lock
, flags
);
3477 if (usb_port_status
.connect_change
) {
3478 port_status
|= (1 << USB_PORT_FEAT_C_CONNECTION
);
3479 dev_dbg(dev
, " C_CONNECTION\n");
3482 if (usb_port_status
.port_enabled
) {
3483 port_status
|= (1 << USB_PORT_FEAT_C_ENABLE
);
3484 dev_dbg(dev
, " C_ENABLE\n");
3487 if (usb_port_status
.connected
) {
3488 port_status
|= (1 << USB_PORT_FEAT_CONNECTION
);
3489 dev_dbg(dev
, " CONNECTION\n");
3492 if (usb_port_status
.port_enabled
) {
3493 port_status
|= (1 << USB_PORT_FEAT_ENABLE
);
3494 dev_dbg(dev
, " ENABLE\n");
3497 if (usb_port_status
.port_over_current
) {
3498 port_status
|= (1 << USB_PORT_FEAT_OVER_CURRENT
);
3499 dev_dbg(dev
, " OVER_CURRENT\n");
3502 if (usb_port_status
.port_powered
) {
3503 port_status
|= (1 << USB_PORT_FEAT_POWER
);
3504 dev_dbg(dev
, " POWER\n");
3507 if (usb_port_status
.port_speed
== CVMX_USB_SPEED_HIGH
) {
3508 port_status
|= USB_PORT_STAT_HIGH_SPEED
;
3509 dev_dbg(dev
, " HIGHSPEED\n");
3510 } else if (usb_port_status
.port_speed
== CVMX_USB_SPEED_LOW
) {
3511 port_status
|= (1 << USB_PORT_FEAT_LOWSPEED
);
3512 dev_dbg(dev
, " LOWSPEED\n");
3515 *((__le32
*) buf
) = cpu_to_le32(port_status
);
3518 dev_dbg(dev
, "SetHubFeature\n");
3519 /* No HUB features supported */
3521 case SetPortFeature
:
3522 dev_dbg(dev
, "SetPortFeature\n");
3524 dev_dbg(dev
, " INVALID\n");
3529 case USB_PORT_FEAT_SUSPEND
:
3530 dev_dbg(dev
, " SUSPEND\n");
3532 case USB_PORT_FEAT_POWER
:
3533 dev_dbg(dev
, " POWER\n");
3535 case USB_PORT_FEAT_RESET
:
3536 dev_dbg(dev
, " RESET\n");
3537 spin_lock_irqsave(&priv
->lock
, flags
);
3538 cvmx_usb_disable(&priv
->usb
);
3539 if (cvmx_usb_enable(&priv
->usb
))
3540 dev_dbg(dev
, "Failed to enable the port\n");
3541 spin_unlock_irqrestore(&priv
->lock
, flags
);
3543 case USB_PORT_FEAT_INDICATOR
:
3544 dev_dbg(dev
, " INDICATOR\n");
3548 dev_dbg(dev
, " UNKNOWN\n");
3553 dev_dbg(dev
, "Unknown root hub request\n");
3559 static const struct hc_driver octeon_hc_driver
= {
3560 .description
= "Octeon USB",
3561 .product_desc
= "Octeon Host Controller",
3562 .hcd_priv_size
= sizeof(struct octeon_hcd
),
3563 .irq
= octeon_usb_irq
,
3564 .flags
= HCD_MEMORY
| HCD_USB2
,
3565 .start
= octeon_usb_start
,
3566 .stop
= octeon_usb_stop
,
3567 .urb_enqueue
= octeon_usb_urb_enqueue
,
3568 .urb_dequeue
= octeon_usb_urb_dequeue
,
3569 .endpoint_disable
= octeon_usb_endpoint_disable
,
3570 .get_frame_number
= octeon_usb_get_frame_number
,
3571 .hub_status_data
= octeon_usb_hub_status_data
,
3572 .hub_control
= octeon_usb_hub_control
,
3573 .map_urb_for_dma
= octeon_map_urb_for_dma
,
3574 .unmap_urb_for_dma
= octeon_unmap_urb_for_dma
,
3577 static int octeon_usb_probe(struct platform_device
*pdev
)
3580 int initialize_flags
;
3582 struct resource
*res_mem
;
3583 struct device_node
*usbn_node
;
3584 int irq
= platform_get_irq(pdev
, 0);
3585 struct device
*dev
= &pdev
->dev
;
3586 struct octeon_hcd
*priv
;
3587 struct usb_hcd
*hcd
;
3588 unsigned long flags
;
3589 u32 clock_rate
= 48000000;
3590 bool is_crystal_clock
= false;
3591 const char *clock_type
;
3594 if (dev
->of_node
== NULL
) {
3595 dev_err(dev
, "Error: empty of_node\n");
3598 usbn_node
= dev
->of_node
->parent
;
3600 i
= of_property_read_u32(usbn_node
,
3601 "refclk-frequency", &clock_rate
);
3603 dev_err(dev
, "No USBN \"refclk-frequency\"\n");
3606 switch (clock_rate
) {
3608 initialize_flags
= CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ
;
3611 initialize_flags
= CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ
;
3614 initialize_flags
= CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ
;
3617 dev_err(dev
, "Illebal USBN \"refclk-frequency\" %u\n",
3623 i
= of_property_read_string(usbn_node
,
3624 "refclk-type", &clock_type
);
3626 if (!i
&& strcmp("crystal", clock_type
) == 0)
3627 is_crystal_clock
= true;
3629 if (is_crystal_clock
)
3630 initialize_flags
|= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI
;
3632 initialize_flags
|= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND
;
3634 res_mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
3635 if (res_mem
== NULL
) {
3636 dev_err(dev
, "found no memory resource\n");
3639 usb_num
= (res_mem
->start
>> 44) & 1;
3642 /* Defective device tree, but we know how to fix it. */
3643 irq_hw_number_t hwirq
= usb_num
? (1 << 6) + 17 : 56;
3645 irq
= irq_create_mapping(NULL
, hwirq
);
3649 * Set the DMA mask to 64bits so we get buffers already translated for
3652 dev
->coherent_dma_mask
= ~0;
3653 dev
->dma_mask
= &dev
->coherent_dma_mask
;
3656 * Only cn52XX and cn56XX have DWC_OTG USB hardware and the
3657 * IOB priority registers. Under heavy network load USB
3658 * hardware can be starved by the IOB causing a crash. Give
3659 * it a priority boost if it has been waiting more than 400
3660 * cycles to avoid this situation.
3662 * Testing indicates that a cnt_val of 8192 is not sufficient,
3663 * but no failures are seen with 4096. We choose a value of
3664 * 400 to give a safety factor of 10.
3666 if (OCTEON_IS_MODEL(OCTEON_CN52XX
) || OCTEON_IS_MODEL(OCTEON_CN56XX
)) {
3667 union cvmx_iob_n2c_l2c_pri_cnt pri_cnt
;
3670 pri_cnt
.s
.cnt_enb
= 1;
3671 pri_cnt
.s
.cnt_val
= 400;
3672 cvmx_write_csr(CVMX_IOB_N2C_L2C_PRI_CNT
, pri_cnt
.u64
);
3675 hcd
= usb_create_hcd(&octeon_hc_driver
, dev
, dev_name(dev
));
3677 dev_dbg(dev
, "Failed to allocate memory for HCD\n");
3680 hcd
->uses_new_polling
= 1;
3681 priv
= (struct octeon_hcd
*)hcd
->hcd_priv
;
3683 spin_lock_init(&priv
->lock
);
3685 priv
->usb
.init_flags
= initialize_flags
;
3687 /* Initialize the USB state structure */
3688 priv
->usb
.index
= usb_num
;
3689 INIT_LIST_HEAD(&priv
->usb
.idle_pipes
);
3690 for (i
= 0; i
< ARRAY_SIZE(priv
->usb
.active_pipes
); i
++)
3691 INIT_LIST_HEAD(&priv
->usb
.active_pipes
[i
]);
3693 /* Due to an errata, CN31XX doesn't support DMA */
3694 if (OCTEON_IS_MODEL(OCTEON_CN31XX
)) {
3695 priv
->usb
.init_flags
|= CVMX_USB_INITIALIZE_FLAGS_NO_DMA
;
3696 /* Only use one channel with non DMA */
3697 priv
->usb
.idle_hardware_channels
= 0x1;
3698 } else if (OCTEON_IS_MODEL(OCTEON_CN5XXX
)) {
3699 /* CN5XXX have an errata with channel 3 */
3700 priv
->usb
.idle_hardware_channels
= 0xf7;
3702 priv
->usb
.idle_hardware_channels
= 0xff;
3705 status
= cvmx_usb_initialize(&priv
->usb
);
3707 dev_dbg(dev
, "USB initialization failed with %d\n", status
);
3712 /* This delay is needed for CN3010, but I don't know why... */
3715 spin_lock_irqsave(&priv
->lock
, flags
);
3716 cvmx_usb_poll(&priv
->usb
);
3717 spin_unlock_irqrestore(&priv
->lock
, flags
);
3719 status
= usb_add_hcd(hcd
, irq
, 0);
3721 dev_dbg(dev
, "USB add HCD failed with %d\n", status
);
3725 device_wakeup_enable(hcd
->self
.controller
);
3727 dev_info(dev
, "Registered HCD for port %d on irq %d\n", usb_num
, irq
);
3732 static int octeon_usb_remove(struct platform_device
*pdev
)
3735 struct device
*dev
= &pdev
->dev
;
3736 struct usb_hcd
*hcd
= dev_get_drvdata(dev
);
3737 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3738 unsigned long flags
;
3740 usb_remove_hcd(hcd
);
3741 spin_lock_irqsave(&priv
->lock
, flags
);
3742 status
= cvmx_usb_shutdown(&priv
->usb
);
3743 spin_unlock_irqrestore(&priv
->lock
, flags
);
3745 dev_dbg(dev
, "USB shutdown failed with %d\n", status
);
3752 static const struct of_device_id octeon_usb_match
[] = {
3754 .compatible
= "cavium,octeon-5750-usbc",
3759 static struct platform_driver octeon_usb_driver
= {
3761 .name
= "OcteonUSB",
3762 .of_match_table
= octeon_usb_match
,
3764 .probe
= octeon_usb_probe
,
3765 .remove
= octeon_usb_remove
,
3768 static int __init
octeon_usb_driver_init(void)
3773 return platform_driver_register(&octeon_usb_driver
);
3775 module_init(octeon_usb_driver_init
);
3777 static void __exit
octeon_usb_driver_exit(void)
3782 platform_driver_unregister(&octeon_usb_driver
);
3784 module_exit(octeon_usb_driver_exit
);
3786 MODULE_LICENSE("GPL");
3787 MODULE_AUTHOR("Cavium, Inc. <support@cavium.com>");
3788 MODULE_DESCRIPTION("Cavium Inc. OCTEON USB Host driver.");