staging: octeon-usb: use list_for_each_entry_safe()
[deliverable/linux.git] / drivers / staging / octeon-usb / octeon-hcd.c
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Cavium Networks
7 *
8 * Some parts of the code were originally released under BSD license:
9 *
10 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
11 * reserved.
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions are
15 * met:
16 *
17 * * Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 *
20 * * Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials provided
23 * with the distribution.
24 *
25 * * Neither the name of Cavium Networks nor the names of
26 * its contributors may be used to endorse or promote products
27 * derived from this software without specific prior written
28 * permission.
29 *
30 * This Software, including technical data, may be subject to U.S. export
31 * control laws, including the U.S. Export Administration Act and its associated
32 * regulations, and may be subject to export or import regulations in other
33 * countries.
34 *
35 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
36 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
37 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
38 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION
39 * OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
40 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
41 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
42 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
43 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
44 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
45 */
46 #include <linux/kernel.h>
47 #include <linux/module.h>
48 #include <linux/init.h>
49 #include <linux/pci.h>
50 #include <linux/interrupt.h>
51 #include <linux/platform_device.h>
52 #include <linux/usb.h>
53
54 #include <linux/time.h>
55 #include <linux/delay.h>
56
57 #include <asm/octeon/cvmx.h>
58 #include <asm/octeon/cvmx-iob-defs.h>
59
60 #include <linux/usb/hcd.h>
61
62 #include <linux/err.h>
63
64 #include <asm/octeon/octeon.h>
65 #include <asm/octeon/cvmx-helper.h>
66 #include <asm/octeon/cvmx-sysinfo.h>
67 #include <asm/octeon/cvmx-helper-board.h>
68
69 #include "octeon-hcd.h"
70
71 /**
72 * enum cvmx_usb_speed - the possible USB device speeds
73 *
74 * @CVMX_USB_SPEED_HIGH: Device is operation at 480Mbps
75 * @CVMX_USB_SPEED_FULL: Device is operation at 12Mbps
76 * @CVMX_USB_SPEED_LOW: Device is operation at 1.5Mbps
77 */
78 enum cvmx_usb_speed {
79 CVMX_USB_SPEED_HIGH = 0,
80 CVMX_USB_SPEED_FULL = 1,
81 CVMX_USB_SPEED_LOW = 2,
82 };
83
84 /**
85 * enum cvmx_usb_transfer - the possible USB transfer types
86 *
87 * @CVMX_USB_TRANSFER_CONTROL: USB transfer type control for hub and status
88 * transfers
89 * @CVMX_USB_TRANSFER_ISOCHRONOUS: USB transfer type isochronous for low
90 * priority periodic transfers
91 * @CVMX_USB_TRANSFER_BULK: USB transfer type bulk for large low priority
92 * transfers
93 * @CVMX_USB_TRANSFER_INTERRUPT: USB transfer type interrupt for high priority
94 * periodic transfers
95 */
96 enum cvmx_usb_transfer {
97 CVMX_USB_TRANSFER_CONTROL = 0,
98 CVMX_USB_TRANSFER_ISOCHRONOUS = 1,
99 CVMX_USB_TRANSFER_BULK = 2,
100 CVMX_USB_TRANSFER_INTERRUPT = 3,
101 };
102
103 /**
104 * enum cvmx_usb_direction - the transfer directions
105 *
106 * @CVMX_USB_DIRECTION_OUT: Data is transferring from Octeon to the device/host
107 * @CVMX_USB_DIRECTION_IN: Data is transferring from the device/host to Octeon
108 */
109 enum cvmx_usb_direction {
110 CVMX_USB_DIRECTION_OUT,
111 CVMX_USB_DIRECTION_IN,
112 };
113
114 /**
115 * enum cvmx_usb_complete - possible callback function status codes
116 *
117 * @CVMX_USB_COMPLETE_SUCCESS: The transaction / operation finished without
118 * any errors
119 * @CVMX_USB_COMPLETE_SHORT: FIXME: This is currently not implemented
120 * @CVMX_USB_COMPLETE_CANCEL: The transaction was canceled while in flight
121 * by a user call to cvmx_usb_cancel
122 * @CVMX_USB_COMPLETE_ERROR: The transaction aborted with an unexpected
123 * error status
124 * @CVMX_USB_COMPLETE_STALL: The transaction received a USB STALL response
125 * from the device
126 * @CVMX_USB_COMPLETE_XACTERR: The transaction failed with an error from the
127 * device even after a number of retries
128 * @CVMX_USB_COMPLETE_DATATGLERR: The transaction failed with a data toggle
129 * error even after a number of retries
130 * @CVMX_USB_COMPLETE_BABBLEERR: The transaction failed with a babble error
131 * @CVMX_USB_COMPLETE_FRAMEERR: The transaction failed with a frame error
132 * even after a number of retries
133 */
134 enum cvmx_usb_complete {
135 CVMX_USB_COMPLETE_SUCCESS,
136 CVMX_USB_COMPLETE_SHORT,
137 CVMX_USB_COMPLETE_CANCEL,
138 CVMX_USB_COMPLETE_ERROR,
139 CVMX_USB_COMPLETE_STALL,
140 CVMX_USB_COMPLETE_XACTERR,
141 CVMX_USB_COMPLETE_DATATGLERR,
142 CVMX_USB_COMPLETE_BABBLEERR,
143 CVMX_USB_COMPLETE_FRAMEERR,
144 };
145
146 /**
147 * struct cvmx_usb_port_status - the USB port status information
148 *
149 * @port_enabled: 1 = Usb port is enabled, 0 = disabled
150 * @port_over_current: 1 = Over current detected, 0 = Over current not
151 * detected. Octeon doesn't support over current detection.
152 * @port_powered: 1 = Port power is being supplied to the device, 0 =
153 * power is off. Octeon doesn't support turning port power
154 * off.
155 * @port_speed: Current port speed.
156 * @connected: 1 = A device is connected to the port, 0 = No device is
157 * connected.
158 * @connect_change: 1 = Device connected state changed since the last set
159 * status call.
160 */
161 struct cvmx_usb_port_status {
162 uint32_t reserved : 25;
163 uint32_t port_enabled : 1;
164 uint32_t port_over_current : 1;
165 uint32_t port_powered : 1;
166 enum cvmx_usb_speed port_speed : 2;
167 uint32_t connected : 1;
168 uint32_t connect_change : 1;
169 };
170
171 /**
172 * union cvmx_usb_control_header - the structure of a Control packet header
173 *
174 * @s.request_type: Bit 7 tells the direction: 1=IN, 0=OUT
175 * @s.request The standard usb request to make
176 * @s.value Value parameter for the request in little endian format
177 * @s.index Index for the request in little endian format
178 * @s.length Length of the data associated with this request in
179 * little endian format
180 */
181 union cvmx_usb_control_header {
182 uint64_t u64;
183 struct {
184 uint64_t request_type : 8;
185 uint64_t request : 8;
186 uint64_t value : 16;
187 uint64_t index : 16;
188 uint64_t length : 16;
189 } s;
190 };
191
192 /**
193 * struct cvmx_usb_iso_packet - descriptor for Isochronous packets
194 *
195 * @offset: This is the offset in bytes into the main buffer where this data
196 * is stored.
197 * @length: This is the length in bytes of the data.
198 * @status: This is the status of this individual packet transfer.
199 */
200 struct cvmx_usb_iso_packet {
201 int offset;
202 int length;
203 enum cvmx_usb_complete status;
204 };
205
206 /**
207 * enum cvmx_usb_initialize_flags - flags used by the initialization function
208 *
209 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI: The USB port uses a 12MHz crystal
210 * as clock source at USB_XO and
211 * USB_XI.
212 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND: The USB port uses 12/24/48MHz 2.5V
213 * board clock source at USB_XO.
214 * USB_XI should be tied to GND.
215 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK: Mask for clock speed field
216 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ: Speed of reference clock or
217 * crystal
218 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ: Speed of reference clock
219 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ: Speed of reference clock
220 * @CVMX_USB_INITIALIZE_FLAGS_NO_DMA: Disable DMA and used polled IO for
221 * data transfer use for the USB
222 */
223 enum cvmx_usb_initialize_flags {
224 CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI = 1 << 0,
225 CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND = 1 << 1,
226 CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK = 3 << 3,
227 CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ = 1 << 3,
228 CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ = 2 << 3,
229 CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ = 3 << 3,
230 /* Bits 3-4 used to encode the clock frequency */
231 CVMX_USB_INITIALIZE_FLAGS_NO_DMA = 1 << 5,
232 };
233
234 /**
235 * enum cvmx_usb_pipe_flags - internal flags for a pipe.
236 *
237 * @__CVMX_USB_PIPE_FLAGS_SCHEDULED: Used internally to determine if a pipe is
238 * actively using hardware. Do not use.
239 * @__CVMX_USB_PIPE_FLAGS_NEED_PING: Used internally to determine if a high
240 * speed pipe is in the ping state. Do not
241 * use.
242 */
243 enum cvmx_usb_pipe_flags {
244 __CVMX_USB_PIPE_FLAGS_SCHEDULED = 1 << 17,
245 __CVMX_USB_PIPE_FLAGS_NEED_PING = 1 << 18,
246 };
247
248 /* Normal prefetch that use the pref instruction. */
249 #define CVMX_PREFETCH(address, offset) asm volatile ("pref %[type], %[off](%[rbase])" : : [rbase] "d" (address), [off] "I" (offset), [type] "n" (0))
250
251 /* Maximum number of times to retry failed transactions */
252 #define MAX_RETRIES 3
253
254 /* Maximum number of hardware channels supported by the USB block */
255 #define MAX_CHANNELS 8
256
257 /* The highest valid USB device address */
258 #define MAX_USB_ADDRESS 127
259
260 /* The highest valid USB endpoint number */
261 #define MAX_USB_ENDPOINT 15
262
263 /* The highest valid port number on a hub */
264 #define MAX_USB_HUB_PORT 15
265
266 /*
267 * The low level hardware can transfer a maximum of this number of bytes in each
268 * transfer. The field is 19 bits wide
269 */
270 #define MAX_TRANSFER_BYTES ((1<<19)-1)
271
272 /*
273 * The low level hardware can transfer a maximum of this number of packets in
274 * each transfer. The field is 10 bits wide
275 */
276 #define MAX_TRANSFER_PACKETS ((1<<10)-1)
277
278 enum {
279 USB_CLOCK_TYPE_REF_12,
280 USB_CLOCK_TYPE_REF_24,
281 USB_CLOCK_TYPE_REF_48,
282 USB_CLOCK_TYPE_CRYSTAL_12,
283 };
284
285 /**
286 * Logical transactions may take numerous low level
287 * transactions, especially when splits are concerned. This
288 * enum represents all of the possible stages a transaction can
289 * be in. Note that split completes are always even. This is so
290 * the NAK handler can backup to the previous low level
291 * transaction with a simple clearing of bit 0.
292 */
293 enum cvmx_usb_stage {
294 CVMX_USB_STAGE_NON_CONTROL,
295 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE,
296 CVMX_USB_STAGE_SETUP,
297 CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE,
298 CVMX_USB_STAGE_DATA,
299 CVMX_USB_STAGE_DATA_SPLIT_COMPLETE,
300 CVMX_USB_STAGE_STATUS,
301 CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE,
302 };
303
304 /**
305 * struct cvmx_usb_transaction - describes each pending USB transaction
306 * regardless of type. These are linked together
307 * to form a list of pending requests for a pipe.
308 *
309 * @prev: Transaction before this one in the pipe.
310 * @next: Transaction after this one in the pipe.
311 * @type: Type of transaction, duplicated of the pipe.
312 * @flags: State flags for this transaction.
313 * @buffer: User's physical buffer address to read/write.
314 * @buffer_length: Size of the user's buffer in bytes.
315 * @control_header: For control transactions, physical address of the 8
316 * byte standard header.
317 * @iso_start_frame: For ISO transactions, the starting frame number.
318 * @iso_number_packets: For ISO transactions, the number of packets in the
319 * request.
320 * @iso_packets: For ISO transactions, the sub packets in the request.
321 * @actual_bytes: Actual bytes transfer for this transaction.
322 * @stage: For control transactions, the current stage.
323 * @urb: URB.
324 */
325 struct cvmx_usb_transaction {
326 struct cvmx_usb_transaction *prev;
327 struct cvmx_usb_transaction *next;
328 enum cvmx_usb_transfer type;
329 uint64_t buffer;
330 int buffer_length;
331 uint64_t control_header;
332 int iso_start_frame;
333 int iso_number_packets;
334 struct cvmx_usb_iso_packet *iso_packets;
335 int xfersize;
336 int pktcnt;
337 int retries;
338 int actual_bytes;
339 enum cvmx_usb_stage stage;
340 struct urb *urb;
341 };
342
343 /**
344 * struct cvmx_usb_pipe - a pipe represents a virtual connection between Octeon
345 * and some USB device. It contains a list of pending
346 * request to the device.
347 *
348 * @prev: Pipe before this one in the list
349 * @next: Pipe after this one in the list
350 * @head: The first pending transaction
351 * @tail: The last pending transaction
352 * @interval: For periodic pipes, the interval between packets in
353 * frames
354 * @next_tx_frame: The next frame this pipe is allowed to transmit on
355 * @flags: State flags for this pipe
356 * @device_speed: Speed of device connected to this pipe
357 * @transfer_type: Type of transaction supported by this pipe
358 * @transfer_dir: IN or OUT. Ignored for Control
359 * @multi_count: Max packet in a row for the device
360 * @max_packet: The device's maximum packet size in bytes
361 * @device_addr: USB device address at other end of pipe
362 * @endpoint_num: USB endpoint number at other end of pipe
363 * @hub_device_addr: Hub address this device is connected to
364 * @hub_port: Hub port this device is connected to
365 * @pid_toggle: This toggles between 0/1 on every packet send to track
366 * the data pid needed
367 * @channel: Hardware DMA channel for this pipe
368 * @split_sc_frame: The low order bits of the frame number the split
369 * complete should be sent on
370 */
371 struct cvmx_usb_pipe {
372 struct cvmx_usb_pipe *prev;
373 struct cvmx_usb_pipe *next;
374 struct cvmx_usb_transaction *head;
375 struct cvmx_usb_transaction *tail;
376 uint64_t interval;
377 uint64_t next_tx_frame;
378 enum cvmx_usb_pipe_flags flags;
379 enum cvmx_usb_speed device_speed;
380 enum cvmx_usb_transfer transfer_type;
381 enum cvmx_usb_direction transfer_dir;
382 int multi_count;
383 uint16_t max_packet;
384 uint8_t device_addr;
385 uint8_t endpoint_num;
386 uint8_t hub_device_addr;
387 uint8_t hub_port;
388 uint8_t pid_toggle;
389 uint8_t channel;
390 int8_t split_sc_frame;
391 };
392
393 /**
394 * struct cvmx_usb_pipe_list
395 *
396 * @head: Head of the list, or NULL if empty.
397 * @tail: Tail if the list, or NULL if empty.
398 */
399 struct cvmx_usb_pipe_list {
400 struct cvmx_usb_pipe *head;
401 struct cvmx_usb_pipe *tail;
402 };
403
404 struct cvmx_usb_tx_fifo {
405 struct {
406 int channel;
407 int size;
408 uint64_t address;
409 } entry[MAX_CHANNELS+1];
410 int head;
411 int tail;
412 };
413
414 /**
415 * struct cvmx_usb_state - the state of the USB block
416 *
417 * init_flags: Flags passed to initialize.
418 * index: Which USB block this is for.
419 * idle_hardware_channels: Bit set for every idle hardware channel.
420 * usbcx_hprt: Stored port status so we don't need to read a CSR to
421 * determine splits.
422 * pipe_for_channel: Map channels to pipes.
423 * pipe: Storage for pipes.
424 * indent: Used by debug output to indent functions.
425 * port_status: Last port status used for change notification.
426 * idle_pipes: List of open pipes that have no transactions.
427 * active_pipes: Active pipes indexed by transfer type.
428 * frame_number: Increments every SOF interrupt for time keeping.
429 * active_split: Points to the current active split, or NULL.
430 */
431 struct cvmx_usb_state {
432 int init_flags;
433 int index;
434 int idle_hardware_channels;
435 union cvmx_usbcx_hprt usbcx_hprt;
436 struct cvmx_usb_pipe *pipe_for_channel[MAX_CHANNELS];
437 int indent;
438 struct cvmx_usb_port_status port_status;
439 struct cvmx_usb_pipe_list idle_pipes;
440 struct cvmx_usb_pipe_list active_pipes[4];
441 uint64_t frame_number;
442 struct cvmx_usb_transaction *active_split;
443 struct cvmx_usb_tx_fifo periodic;
444 struct cvmx_usb_tx_fifo nonperiodic;
445 };
446
447 struct octeon_hcd {
448 spinlock_t lock;
449 struct cvmx_usb_state usb;
450 struct tasklet_struct dequeue_tasklet;
451 struct list_head dequeue_list;
452 };
453
454 /* This macro spins on a field waiting for it to reach a value */
455 #define CVMX_WAIT_FOR_FIELD32(address, type, field, op, value, timeout_usec)\
456 ({int result; \
457 do { \
458 uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec * \
459 octeon_get_clock_rate() / 1000000; \
460 type c; \
461 while (1) { \
462 c.u32 = __cvmx_usb_read_csr32(usb, address); \
463 if (c.s.field op (value)) { \
464 result = 0; \
465 break; \
466 } else if (cvmx_get_cycle() > done) { \
467 result = -1; \
468 break; \
469 } else \
470 cvmx_wait(100); \
471 } \
472 } while (0); \
473 result; })
474
475 /*
476 * This macro logically sets a single field in a CSR. It does the sequence
477 * read, modify, and write
478 */
479 #define USB_SET_FIELD32(address, type, field, value) \
480 do { \
481 type c; \
482 c.u32 = __cvmx_usb_read_csr32(usb, address); \
483 c.s.field = value; \
484 __cvmx_usb_write_csr32(usb, address, c.u32); \
485 } while (0)
486
487 /* Returns the IO address to push/pop stuff data from the FIFOs */
488 #define USB_FIFO_ADDRESS(channel, usb_index) (CVMX_USBCX_GOTGCTL(usb_index) + ((channel)+1)*0x1000)
489
490 static int octeon_usb_get_clock_type(void)
491 {
492 switch (cvmx_sysinfo_get()->board_type) {
493 case CVMX_BOARD_TYPE_BBGW_REF:
494 case CVMX_BOARD_TYPE_LANAI2_A:
495 case CVMX_BOARD_TYPE_LANAI2_U:
496 case CVMX_BOARD_TYPE_LANAI2_G:
497 case CVMX_BOARD_TYPE_UBNT_E100:
498 return USB_CLOCK_TYPE_CRYSTAL_12;
499 }
500 return USB_CLOCK_TYPE_REF_48;
501 }
502
503 /**
504 * Read a USB 32bit CSR. It performs the necessary address swizzle
505 * for 32bit CSRs and logs the value in a readable format if
506 * debugging is on.
507 *
508 * @usb: USB block this access is for
509 * @address: 64bit address to read
510 *
511 * Returns: Result of the read
512 */
513 static inline uint32_t __cvmx_usb_read_csr32(struct cvmx_usb_state *usb,
514 uint64_t address)
515 {
516 uint32_t result = cvmx_read64_uint32(address ^ 4);
517 return result;
518 }
519
520
521 /**
522 * Write a USB 32bit CSR. It performs the necessary address
523 * swizzle for 32bit CSRs and logs the value in a readable format
524 * if debugging is on.
525 *
526 * @usb: USB block this access is for
527 * @address: 64bit address to write
528 * @value: Value to write
529 */
530 static inline void __cvmx_usb_write_csr32(struct cvmx_usb_state *usb,
531 uint64_t address, uint32_t value)
532 {
533 cvmx_write64_uint32(address ^ 4, value);
534 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
535 }
536
537
538 /**
539 * Read a USB 64bit CSR. It logs the value in a readable format if
540 * debugging is on.
541 *
542 * @usb: USB block this access is for
543 * @address: 64bit address to read
544 *
545 * Returns: Result of the read
546 */
547 static inline uint64_t __cvmx_usb_read_csr64(struct cvmx_usb_state *usb,
548 uint64_t address)
549 {
550 uint64_t result = cvmx_read64_uint64(address);
551 return result;
552 }
553
554
555 /**
556 * Write a USB 64bit CSR. It logs the value in a readable format
557 * if debugging is on.
558 *
559 * @usb: USB block this access is for
560 * @address: 64bit address to write
561 * @value: Value to write
562 */
563 static inline void __cvmx_usb_write_csr64(struct cvmx_usb_state *usb,
564 uint64_t address, uint64_t value)
565 {
566 cvmx_write64_uint64(address, value);
567 }
568
569 /**
570 * Return non zero if this pipe connects to a non HIGH speed
571 * device through a high speed hub.
572 *
573 * @usb: USB block this access is for
574 * @pipe: Pipe to check
575 *
576 * Returns: Non zero if we need to do split transactions
577 */
578 static inline int __cvmx_usb_pipe_needs_split(struct cvmx_usb_state *usb,
579 struct cvmx_usb_pipe *pipe)
580 {
581 return pipe->device_speed != CVMX_USB_SPEED_HIGH &&
582 usb->usbcx_hprt.s.prtspd == CVMX_USB_SPEED_HIGH;
583 }
584
585
586 /**
587 * Trivial utility function to return the correct PID for a pipe
588 *
589 * @pipe: pipe to check
590 *
591 * Returns: PID for pipe
592 */
593 static inline int __cvmx_usb_get_data_pid(struct cvmx_usb_pipe *pipe)
594 {
595 if (pipe->pid_toggle)
596 return 2; /* Data1 */
597 else
598 return 0; /* Data0 */
599 }
600
601
602 /**
603 * Return the number of USB ports supported by this Octeon
604 * chip. If the chip doesn't support USB, or is not supported
605 * by this API, a zero will be returned. Most Octeon chips
606 * support one usb port, but some support two ports.
607 * cvmx_usb_initialize() must be called on independent
608 * struct cvmx_usb_state.
609 *
610 * Returns: Number of port, zero if usb isn't supported
611 */
612 static int cvmx_usb_get_num_ports(void)
613 {
614 int arch_ports = 0;
615
616 if (OCTEON_IS_MODEL(OCTEON_CN56XX))
617 arch_ports = 1;
618 else if (OCTEON_IS_MODEL(OCTEON_CN52XX))
619 arch_ports = 2;
620 else if (OCTEON_IS_MODEL(OCTEON_CN50XX))
621 arch_ports = 1;
622 else if (OCTEON_IS_MODEL(OCTEON_CN31XX))
623 arch_ports = 1;
624 else if (OCTEON_IS_MODEL(OCTEON_CN30XX))
625 arch_ports = 1;
626 else
627 arch_ports = 0;
628
629 return arch_ports;
630 }
631
632 /**
633 * Add a pipe to the tail of a list
634 * @list: List to add pipe to
635 * @pipe: Pipe to add
636 */
637 static inline void __cvmx_usb_append_pipe(struct cvmx_usb_pipe_list *list, struct cvmx_usb_pipe *pipe)
638 {
639 pipe->next = NULL;
640 pipe->prev = list->tail;
641 if (list->tail)
642 list->tail->next = pipe;
643 else
644 list->head = pipe;
645 list->tail = pipe;
646 }
647
648
649 /**
650 * Remove a pipe from a list
651 * @list: List to remove pipe from
652 * @pipe: Pipe to remove
653 */
654 static inline void __cvmx_usb_remove_pipe(struct cvmx_usb_pipe_list *list, struct cvmx_usb_pipe *pipe)
655 {
656 if (list->head == pipe) {
657 list->head = pipe->next;
658 pipe->next = NULL;
659 if (list->head)
660 list->head->prev = NULL;
661 else
662 list->tail = NULL;
663 } else if (list->tail == pipe) {
664 list->tail = pipe->prev;
665 list->tail->next = NULL;
666 pipe->prev = NULL;
667 } else {
668 pipe->prev->next = pipe->next;
669 pipe->next->prev = pipe->prev;
670 pipe->prev = NULL;
671 pipe->next = NULL;
672 }
673 }
674
675
676 /**
677 * Initialize a USB port for use. This must be called before any
678 * other access to the Octeon USB port is made. The port starts
679 * off in the disabled state.
680 *
681 * @usb: Pointer to an empty struct cvmx_usb_state
682 * that will be populated by the initialize call.
683 * This structure is then passed to all other USB
684 * functions.
685 * @usb_port_number:
686 * Which Octeon USB port to initialize.
687 *
688 * Returns: 0 or a negative error code.
689 */
690 static int cvmx_usb_initialize(struct cvmx_usb_state *usb,
691 int usb_port_number)
692 {
693 union cvmx_usbnx_clk_ctl usbn_clk_ctl;
694 union cvmx_usbnx_usbp_ctl_status usbn_usbp_ctl_status;
695 enum cvmx_usb_initialize_flags flags = 0;
696
697 /* At first allow 0-1 for the usb port number */
698 if ((usb_port_number < 0) || (usb_port_number > 1))
699 return -EINVAL;
700 /* For all chips except 52XX there is only one port */
701 if (!OCTEON_IS_MODEL(OCTEON_CN52XX) && (usb_port_number > 0))
702 return -EINVAL;
703 /* Try to determine clock type automatically */
704 if (octeon_usb_get_clock_type() == USB_CLOCK_TYPE_CRYSTAL_12) {
705 /* Only 12 MHZ crystals are supported */
706 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI;
707 } else {
708 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND;
709
710 switch (octeon_usb_get_clock_type()) {
711 case USB_CLOCK_TYPE_REF_12:
712 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ;
713 break;
714 case USB_CLOCK_TYPE_REF_24:
715 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ;
716 break;
717 case USB_CLOCK_TYPE_REF_48:
718 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ;
719 break;
720 default:
721 return -EINVAL;
722 break;
723 }
724 }
725
726 memset(usb, 0, sizeof(*usb));
727 usb->init_flags = flags;
728
729 /* Initialize the USB state structure */
730 usb->index = usb_port_number;
731
732 /*
733 * Power On Reset and PHY Initialization
734 *
735 * 1. Wait for DCOK to assert (nothing to do)
736 *
737 * 2a. Write USBN0/1_CLK_CTL[POR] = 1 and
738 * USBN0/1_CLK_CTL[HRST,PRST,HCLK_RST] = 0
739 */
740 usbn_clk_ctl.u64 = __cvmx_usb_read_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index));
741 usbn_clk_ctl.s.por = 1;
742 usbn_clk_ctl.s.hrst = 0;
743 usbn_clk_ctl.s.prst = 0;
744 usbn_clk_ctl.s.hclk_rst = 0;
745 usbn_clk_ctl.s.enable = 0;
746 /*
747 * 2b. Select the USB reference clock/crystal parameters by writing
748 * appropriate values to USBN0/1_CLK_CTL[P_C_SEL, P_RTYPE, P_COM_ON]
749 */
750 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND) {
751 /*
752 * The USB port uses 12/24/48MHz 2.5V board clock
753 * source at USB_XO. USB_XI should be tied to GND.
754 * Most Octeon evaluation boards require this setting
755 */
756 if (OCTEON_IS_MODEL(OCTEON_CN3XXX) ||
757 OCTEON_IS_MODEL(OCTEON_CN56XX) ||
758 OCTEON_IS_MODEL(OCTEON_CN50XX))
759 /* From CN56XX,CN50XX,CN31XX,CN30XX manuals */
760 usbn_clk_ctl.s.p_rtype = 2; /* p_rclk=1 & p_xenbn=0 */
761 else
762 /* From CN52XX manual */
763 usbn_clk_ctl.s.p_rtype = 1;
764
765 switch (flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK) {
766 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ:
767 usbn_clk_ctl.s.p_c_sel = 0;
768 break;
769 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ:
770 usbn_clk_ctl.s.p_c_sel = 1;
771 break;
772 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ:
773 usbn_clk_ctl.s.p_c_sel = 2;
774 break;
775 }
776 } else {
777 /*
778 * The USB port uses a 12MHz crystal as clock source
779 * at USB_XO and USB_XI
780 */
781 if (OCTEON_IS_MODEL(OCTEON_CN3XXX))
782 /* From CN31XX,CN30XX manual */
783 usbn_clk_ctl.s.p_rtype = 3; /* p_rclk=1 & p_xenbn=1 */
784 else
785 /* From CN56XX,CN52XX,CN50XX manuals. */
786 usbn_clk_ctl.s.p_rtype = 0;
787
788 usbn_clk_ctl.s.p_c_sel = 0;
789 }
790 /*
791 * 2c. Select the HCLK via writing USBN0/1_CLK_CTL[DIVIDE, DIVIDE2] and
792 * setting USBN0/1_CLK_CTL[ENABLE] = 1. Divide the core clock down
793 * such that USB is as close as possible to 125Mhz
794 */
795 {
796 int divisor = (octeon_get_clock_rate()+125000000-1)/125000000;
797 /* Lower than 4 doesn't seem to work properly */
798 if (divisor < 4)
799 divisor = 4;
800 usbn_clk_ctl.s.divide = divisor;
801 usbn_clk_ctl.s.divide2 = 0;
802 }
803 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
804 usbn_clk_ctl.u64);
805 /* 2d. Write USBN0/1_CLK_CTL[HCLK_RST] = 1 */
806 usbn_clk_ctl.s.hclk_rst = 1;
807 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
808 usbn_clk_ctl.u64);
809 /* 2e. Wait 64 core-clock cycles for HCLK to stabilize */
810 cvmx_wait(64);
811 /*
812 * 3. Program the power-on reset field in the USBN clock-control
813 * register:
814 * USBN_CLK_CTL[POR] = 0
815 */
816 usbn_clk_ctl.s.por = 0;
817 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
818 usbn_clk_ctl.u64);
819 /* 4. Wait 1 ms for PHY clock to start */
820 mdelay(1);
821 /*
822 * 5. Program the Reset input from automatic test equipment field in the
823 * USBP control and status register:
824 * USBN_USBP_CTL_STATUS[ATE_RESET] = 1
825 */
826 usbn_usbp_ctl_status.u64 = __cvmx_usb_read_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index));
827 usbn_usbp_ctl_status.s.ate_reset = 1;
828 __cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
829 usbn_usbp_ctl_status.u64);
830 /* 6. Wait 10 cycles */
831 cvmx_wait(10);
832 /*
833 * 7. Clear ATE_RESET field in the USBN clock-control register:
834 * USBN_USBP_CTL_STATUS[ATE_RESET] = 0
835 */
836 usbn_usbp_ctl_status.s.ate_reset = 0;
837 __cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
838 usbn_usbp_ctl_status.u64);
839 /*
840 * 8. Program the PHY reset field in the USBN clock-control register:
841 * USBN_CLK_CTL[PRST] = 1
842 */
843 usbn_clk_ctl.s.prst = 1;
844 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
845 usbn_clk_ctl.u64);
846 /*
847 * 9. Program the USBP control and status register to select host or
848 * device mode. USBN_USBP_CTL_STATUS[HST_MODE] = 0 for host, = 1 for
849 * device
850 */
851 usbn_usbp_ctl_status.s.hst_mode = 0;
852 __cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
853 usbn_usbp_ctl_status.u64);
854 /* 10. Wait 1 us */
855 udelay(1);
856 /*
857 * 11. Program the hreset_n field in the USBN clock-control register:
858 * USBN_CLK_CTL[HRST] = 1
859 */
860 usbn_clk_ctl.s.hrst = 1;
861 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
862 usbn_clk_ctl.u64);
863 /* 12. Proceed to USB core initialization */
864 usbn_clk_ctl.s.enable = 1;
865 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
866 usbn_clk_ctl.u64);
867 udelay(1);
868
869 /*
870 * USB Core Initialization
871 *
872 * 1. Read USBC_GHWCFG1, USBC_GHWCFG2, USBC_GHWCFG3, USBC_GHWCFG4 to
873 * determine USB core configuration parameters.
874 *
875 * Nothing needed
876 *
877 * 2. Program the following fields in the global AHB configuration
878 * register (USBC_GAHBCFG)
879 * DMA mode, USBC_GAHBCFG[DMAEn]: 1 = DMA mode, 0 = slave mode
880 * Burst length, USBC_GAHBCFG[HBSTLEN] = 0
881 * Nonperiodic TxFIFO empty level (slave mode only),
882 * USBC_GAHBCFG[NPTXFEMPLVL]
883 * Periodic TxFIFO empty level (slave mode only),
884 * USBC_GAHBCFG[PTXFEMPLVL]
885 * Global interrupt mask, USBC_GAHBCFG[GLBLINTRMSK] = 1
886 */
887 {
888 union cvmx_usbcx_gahbcfg usbcx_gahbcfg;
889 /* Due to an errata, CN31XX doesn't support DMA */
890 if (OCTEON_IS_MODEL(OCTEON_CN31XX))
891 usb->init_flags |= CVMX_USB_INITIALIZE_FLAGS_NO_DMA;
892 usbcx_gahbcfg.u32 = 0;
893 usbcx_gahbcfg.s.dmaen = !(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA);
894 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
895 /* Only use one channel with non DMA */
896 usb->idle_hardware_channels = 0x1;
897 else if (OCTEON_IS_MODEL(OCTEON_CN5XXX))
898 /* CN5XXX have an errata with channel 3 */
899 usb->idle_hardware_channels = 0xf7;
900 else
901 usb->idle_hardware_channels = 0xff;
902 usbcx_gahbcfg.s.hbstlen = 0;
903 usbcx_gahbcfg.s.nptxfemplvl = 1;
904 usbcx_gahbcfg.s.ptxfemplvl = 1;
905 usbcx_gahbcfg.s.glblintrmsk = 1;
906 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GAHBCFG(usb->index),
907 usbcx_gahbcfg.u32);
908 }
909 /*
910 * 3. Program the following fields in USBC_GUSBCFG register.
911 * HS/FS timeout calibration, USBC_GUSBCFG[TOUTCAL] = 0
912 * ULPI DDR select, USBC_GUSBCFG[DDRSEL] = 0
913 * USB turnaround time, USBC_GUSBCFG[USBTRDTIM] = 0x5
914 * PHY low-power clock select, USBC_GUSBCFG[PHYLPWRCLKSEL] = 0
915 */
916 {
917 union cvmx_usbcx_gusbcfg usbcx_gusbcfg;
918 usbcx_gusbcfg.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GUSBCFG(usb->index));
919 usbcx_gusbcfg.s.toutcal = 0;
920 usbcx_gusbcfg.s.ddrsel = 0;
921 usbcx_gusbcfg.s.usbtrdtim = 0x5;
922 usbcx_gusbcfg.s.phylpwrclksel = 0;
923 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GUSBCFG(usb->index),
924 usbcx_gusbcfg.u32);
925 }
926 /*
927 * 4. The software must unmask the following bits in the USBC_GINTMSK
928 * register.
929 * OTG interrupt mask, USBC_GINTMSK[OTGINTMSK] = 1
930 * Mode mismatch interrupt mask, USBC_GINTMSK[MODEMISMSK] = 1
931 */
932 {
933 union cvmx_usbcx_gintmsk usbcx_gintmsk;
934 int channel;
935
936 usbcx_gintmsk.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GINTMSK(usb->index));
937 usbcx_gintmsk.s.otgintmsk = 1;
938 usbcx_gintmsk.s.modemismsk = 1;
939 usbcx_gintmsk.s.hchintmsk = 1;
940 usbcx_gintmsk.s.sofmsk = 0;
941 /* We need RX FIFO interrupts if we don't have DMA */
942 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
943 usbcx_gintmsk.s.rxflvlmsk = 1;
944 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTMSK(usb->index),
945 usbcx_gintmsk.u32);
946
947 /*
948 * Disable all channel interrupts. We'll enable them per channel
949 * later.
950 */
951 for (channel = 0; channel < 8; channel++)
952 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), 0);
953 }
954
955 {
956 /*
957 * Host Port Initialization
958 *
959 * 1. Program the host-port interrupt-mask field to unmask,
960 * USBC_GINTMSK[PRTINT] = 1
961 */
962 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk,
963 prtintmsk, 1);
964 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk,
965 disconnintmsk, 1);
966 /*
967 * 2. Program the USBC_HCFG register to select full-speed host
968 * or high-speed host.
969 */
970 {
971 union cvmx_usbcx_hcfg usbcx_hcfg;
972 usbcx_hcfg.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCFG(usb->index));
973 usbcx_hcfg.s.fslssupp = 0;
974 usbcx_hcfg.s.fslspclksel = 0;
975 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCFG(usb->index), usbcx_hcfg.u32);
976 }
977 /*
978 * 3. Program the port power bit to drive VBUS on the USB,
979 * USBC_HPRT[PRTPWR] = 1
980 */
981 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt, prtpwr, 1);
982
983 /*
984 * Steps 4-15 from the manual are done later in the port enable
985 */
986 }
987
988 return 0;
989 }
990
991
992 /**
993 * Shutdown a USB port after a call to cvmx_usb_initialize().
994 * The port should be disabled with all pipes closed when this
995 * function is called.
996 *
997 * @usb: USB device state populated by cvmx_usb_initialize().
998 *
999 * Returns: 0 or a negative error code.
1000 */
1001 static int cvmx_usb_shutdown(struct cvmx_usb_state *usb)
1002 {
1003 union cvmx_usbnx_clk_ctl usbn_clk_ctl;
1004
1005 /* Make sure all pipes are closed */
1006 if (usb->idle_pipes.head ||
1007 usb->active_pipes[CVMX_USB_TRANSFER_ISOCHRONOUS].head ||
1008 usb->active_pipes[CVMX_USB_TRANSFER_INTERRUPT].head ||
1009 usb->active_pipes[CVMX_USB_TRANSFER_CONTROL].head ||
1010 usb->active_pipes[CVMX_USB_TRANSFER_BULK].head)
1011 return -EBUSY;
1012
1013 /* Disable the clocks and put them in power on reset */
1014 usbn_clk_ctl.u64 = __cvmx_usb_read_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index));
1015 usbn_clk_ctl.s.enable = 1;
1016 usbn_clk_ctl.s.por = 1;
1017 usbn_clk_ctl.s.hclk_rst = 1;
1018 usbn_clk_ctl.s.prst = 0;
1019 usbn_clk_ctl.s.hrst = 0;
1020 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
1021 usbn_clk_ctl.u64);
1022 return 0;
1023 }
1024
1025
1026 /**
1027 * Enable a USB port. After this call succeeds, the USB port is
1028 * online and servicing requests.
1029 *
1030 * @usb: USB device state populated by cvmx_usb_initialize().
1031 *
1032 * Returns: 0 or a negative error code.
1033 */
1034 static int cvmx_usb_enable(struct cvmx_usb_state *usb)
1035 {
1036 union cvmx_usbcx_ghwcfg3 usbcx_ghwcfg3;
1037
1038 usb->usbcx_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
1039
1040 /*
1041 * If the port is already enabled the just return. We don't need to do
1042 * anything
1043 */
1044 if (usb->usbcx_hprt.s.prtena)
1045 return 0;
1046
1047 /* If there is nothing plugged into the port then fail immediately */
1048 if (!usb->usbcx_hprt.s.prtconnsts) {
1049 return -ETIMEDOUT;
1050 }
1051
1052 /* Program the port reset bit to start the reset process */
1053 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt, prtrst, 1);
1054
1055 /*
1056 * Wait at least 50ms (high speed), or 10ms (full speed) for the reset
1057 * process to complete.
1058 */
1059 mdelay(50);
1060
1061 /* Program the port reset bit to 0, USBC_HPRT[PRTRST] = 0 */
1062 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt, prtrst, 0);
1063
1064 /* Wait for the USBC_HPRT[PRTENA]. */
1065 if (CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt,
1066 prtena, ==, 1, 100000))
1067 return -ETIMEDOUT;
1068
1069 /*
1070 * Read the port speed field to get the enumerated speed,
1071 * USBC_HPRT[PRTSPD].
1072 */
1073 usb->usbcx_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
1074 usbcx_ghwcfg3.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GHWCFG3(usb->index));
1075
1076 /*
1077 * 13. Program the USBC_GRXFSIZ register to select the size of the
1078 * receive FIFO (25%).
1079 */
1080 USB_SET_FIELD32(CVMX_USBCX_GRXFSIZ(usb->index), union cvmx_usbcx_grxfsiz,
1081 rxfdep, usbcx_ghwcfg3.s.dfifodepth / 4);
1082 /*
1083 * 14. Program the USBC_GNPTXFSIZ register to select the size and the
1084 * start address of the non- periodic transmit FIFO for nonperiodic
1085 * transactions (50%).
1086 */
1087 {
1088 union cvmx_usbcx_gnptxfsiz siz;
1089 siz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index));
1090 siz.s.nptxfdep = usbcx_ghwcfg3.s.dfifodepth / 2;
1091 siz.s.nptxfstaddr = usbcx_ghwcfg3.s.dfifodepth / 4;
1092 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index), siz.u32);
1093 }
1094 /*
1095 * 15. Program the USBC_HPTXFSIZ register to select the size and start
1096 * address of the periodic transmit FIFO for periodic transactions
1097 * (25%).
1098 */
1099 {
1100 union cvmx_usbcx_hptxfsiz siz;
1101 siz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPTXFSIZ(usb->index));
1102 siz.s.ptxfsize = usbcx_ghwcfg3.s.dfifodepth / 4;
1103 siz.s.ptxfstaddr = 3 * usbcx_ghwcfg3.s.dfifodepth / 4;
1104 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HPTXFSIZ(usb->index), siz.u32);
1105 }
1106 /* Flush all FIFOs */
1107 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), union cvmx_usbcx_grstctl, txfnum, 0x10);
1108 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), union cvmx_usbcx_grstctl, txfflsh, 1);
1109 CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), union cvmx_usbcx_grstctl,
1110 txfflsh, ==, 0, 100);
1111 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), union cvmx_usbcx_grstctl, rxfflsh, 1);
1112 CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), union cvmx_usbcx_grstctl,
1113 rxfflsh, ==, 0, 100);
1114
1115 return 0;
1116 }
1117
1118
1119 /**
1120 * Disable a USB port. After this call the USB port will not
1121 * generate data transfers and will not generate events.
1122 * Transactions in process will fail and call their
1123 * associated callbacks.
1124 *
1125 * @usb: USB device state populated by cvmx_usb_initialize().
1126 *
1127 * Returns: 0 or a negative error code.
1128 */
1129 static int cvmx_usb_disable(struct cvmx_usb_state *usb)
1130 {
1131 /* Disable the port */
1132 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt, prtena, 1);
1133 return 0;
1134 }
1135
1136
1137 /**
1138 * Get the current state of the USB port. Use this call to
1139 * determine if the usb port has anything connected, is enabled,
1140 * or has some sort of error condition. The return value of this
1141 * call has "changed" bits to signal of the value of some fields
1142 * have changed between calls.
1143 *
1144 * @usb: USB device state populated by cvmx_usb_initialize().
1145 *
1146 * Returns: Port status information
1147 */
1148 static struct cvmx_usb_port_status cvmx_usb_get_status(struct cvmx_usb_state *usb)
1149 {
1150 union cvmx_usbcx_hprt usbc_hprt;
1151 struct cvmx_usb_port_status result;
1152
1153 memset(&result, 0, sizeof(result));
1154
1155 usbc_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
1156 result.port_enabled = usbc_hprt.s.prtena;
1157 result.port_over_current = usbc_hprt.s.prtovrcurract;
1158 result.port_powered = usbc_hprt.s.prtpwr;
1159 result.port_speed = usbc_hprt.s.prtspd;
1160 result.connected = usbc_hprt.s.prtconnsts;
1161 result.connect_change = (result.connected != usb->port_status.connected);
1162
1163 return result;
1164 }
1165
1166 /**
1167 * Open a virtual pipe between the host and a USB device. A pipe
1168 * must be opened before data can be transferred between a device
1169 * and Octeon.
1170 *
1171 * @usb: USB device state populated by cvmx_usb_initialize().
1172 * @device_addr:
1173 * USB device address to open the pipe to
1174 * (0-127).
1175 * @endpoint_num:
1176 * USB endpoint number to open the pipe to
1177 * (0-15).
1178 * @device_speed:
1179 * The speed of the device the pipe is going
1180 * to. This must match the device's speed,
1181 * which may be different than the port speed.
1182 * @max_packet: The maximum packet length the device can
1183 * transmit/receive (low speed=0-8, full
1184 * speed=0-1023, high speed=0-1024). This value
1185 * comes from the standard endpoint descriptor
1186 * field wMaxPacketSize bits <10:0>.
1187 * @transfer_type:
1188 * The type of transfer this pipe is for.
1189 * @transfer_dir:
1190 * The direction the pipe is in. This is not
1191 * used for control pipes.
1192 * @interval: For ISOCHRONOUS and INTERRUPT transfers,
1193 * this is how often the transfer is scheduled
1194 * for. All other transfers should specify
1195 * zero. The units are in frames (8000/sec at
1196 * high speed, 1000/sec for full speed).
1197 * @multi_count:
1198 * For high speed devices, this is the maximum
1199 * allowed number of packet per microframe.
1200 * Specify zero for non high speed devices. This
1201 * value comes from the standard endpoint descriptor
1202 * field wMaxPacketSize bits <12:11>.
1203 * @hub_device_addr:
1204 * Hub device address this device is connected
1205 * to. Devices connected directly to Octeon
1206 * use zero. This is only used when the device
1207 * is full/low speed behind a high speed hub.
1208 * The address will be of the high speed hub,
1209 * not and full speed hubs after it.
1210 * @hub_port: Which port on the hub the device is
1211 * connected. Use zero for devices connected
1212 * directly to Octeon. Like hub_device_addr,
1213 * this is only used for full/low speed
1214 * devices behind a high speed hub.
1215 *
1216 * Returns: A non-NULL value is a pipe. NULL means an error.
1217 */
1218 static struct cvmx_usb_pipe *cvmx_usb_open_pipe(struct cvmx_usb_state *usb,
1219 int device_addr, int
1220 endpoint_num,
1221 enum cvmx_usb_speed
1222 device_speed,
1223 int max_packet,
1224 enum cvmx_usb_transfer
1225 transfer_type,
1226 enum cvmx_usb_direction
1227 transfer_dir,
1228 int interval, int multi_count,
1229 int hub_device_addr,
1230 int hub_port)
1231 {
1232 struct cvmx_usb_pipe *pipe;
1233
1234 if (unlikely((device_addr < 0) || (device_addr > MAX_USB_ADDRESS)))
1235 return NULL;
1236 if (unlikely((endpoint_num < 0) || (endpoint_num > MAX_USB_ENDPOINT)))
1237 return NULL;
1238 if (unlikely(device_speed > CVMX_USB_SPEED_LOW))
1239 return NULL;
1240 if (unlikely((max_packet <= 0) || (max_packet > 1024)))
1241 return NULL;
1242 if (unlikely(transfer_type > CVMX_USB_TRANSFER_INTERRUPT))
1243 return NULL;
1244 if (unlikely((transfer_dir != CVMX_USB_DIRECTION_OUT) &&
1245 (transfer_dir != CVMX_USB_DIRECTION_IN)))
1246 return NULL;
1247 if (unlikely(interval < 0))
1248 return NULL;
1249 if (unlikely((transfer_type == CVMX_USB_TRANSFER_CONTROL) && interval))
1250 return NULL;
1251 if (unlikely(multi_count < 0))
1252 return NULL;
1253 if (unlikely((device_speed != CVMX_USB_SPEED_HIGH) &&
1254 (multi_count != 0)))
1255 return NULL;
1256 if (unlikely((hub_device_addr < 0) || (hub_device_addr > MAX_USB_ADDRESS)))
1257 return NULL;
1258 if (unlikely((hub_port < 0) || (hub_port > MAX_USB_HUB_PORT)))
1259 return NULL;
1260
1261 pipe = kzalloc(sizeof(*pipe), GFP_ATOMIC);
1262 if (!pipe)
1263 return NULL;
1264 if ((device_speed == CVMX_USB_SPEED_HIGH) &&
1265 (transfer_dir == CVMX_USB_DIRECTION_OUT) &&
1266 (transfer_type == CVMX_USB_TRANSFER_BULK))
1267 pipe->flags |= __CVMX_USB_PIPE_FLAGS_NEED_PING;
1268 pipe->device_addr = device_addr;
1269 pipe->endpoint_num = endpoint_num;
1270 pipe->device_speed = device_speed;
1271 pipe->max_packet = max_packet;
1272 pipe->transfer_type = transfer_type;
1273 pipe->transfer_dir = transfer_dir;
1274 /*
1275 * All pipes use interval to rate limit NAK processing. Force an
1276 * interval if one wasn't supplied
1277 */
1278 if (!interval)
1279 interval = 1;
1280 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1281 pipe->interval = interval*8;
1282 /* Force start splits to be schedule on uFrame 0 */
1283 pipe->next_tx_frame = ((usb->frame_number+7)&~7) + pipe->interval;
1284 } else {
1285 pipe->interval = interval;
1286 pipe->next_tx_frame = usb->frame_number + pipe->interval;
1287 }
1288 pipe->multi_count = multi_count;
1289 pipe->hub_device_addr = hub_device_addr;
1290 pipe->hub_port = hub_port;
1291 pipe->pid_toggle = 0;
1292 pipe->split_sc_frame = -1;
1293 __cvmx_usb_append_pipe(&usb->idle_pipes, pipe);
1294
1295 /*
1296 * We don't need to tell the hardware about this pipe yet since
1297 * it doesn't have any submitted requests
1298 */
1299
1300 return pipe;
1301 }
1302
1303
1304 /**
1305 * Poll the RX FIFOs and remove data as needed. This function is only used
1306 * in non DMA mode. It is very important that this function be called quickly
1307 * enough to prevent FIFO overflow.
1308 *
1309 * @usb: USB device state populated by cvmx_usb_initialize().
1310 */
1311 static void __cvmx_usb_poll_rx_fifo(struct cvmx_usb_state *usb)
1312 {
1313 union cvmx_usbcx_grxstsph rx_status;
1314 int channel;
1315 int bytes;
1316 uint64_t address;
1317 uint32_t *ptr;
1318
1319 rx_status.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GRXSTSPH(usb->index));
1320 /* Only read data if IN data is there */
1321 if (rx_status.s.pktsts != 2)
1322 return;
1323 /* Check if no data is available */
1324 if (!rx_status.s.bcnt)
1325 return;
1326
1327 channel = rx_status.s.chnum;
1328 bytes = rx_status.s.bcnt;
1329 if (!bytes)
1330 return;
1331
1332 /* Get where the DMA engine would have written this data */
1333 address = __cvmx_usb_read_csr64(usb, CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8);
1334 ptr = cvmx_phys_to_ptr(address);
1335 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8, address + bytes);
1336
1337 /* Loop writing the FIFO data for this packet into memory */
1338 while (bytes > 0) {
1339 *ptr++ = __cvmx_usb_read_csr32(usb, USB_FIFO_ADDRESS(channel, usb->index));
1340 bytes -= 4;
1341 }
1342 CVMX_SYNCW;
1343
1344 return;
1345 }
1346
1347
1348 /**
1349 * Fill the TX hardware fifo with data out of the software
1350 * fifos
1351 *
1352 * @usb: USB device state populated by cvmx_usb_initialize().
1353 * @fifo: Software fifo to use
1354 * @available: Amount of space in the hardware fifo
1355 *
1356 * Returns: Non zero if the hardware fifo was too small and needs
1357 * to be serviced again.
1358 */
1359 static int __cvmx_usb_fill_tx_hw(struct cvmx_usb_state *usb,
1360 struct cvmx_usb_tx_fifo *fifo, int available)
1361 {
1362 /*
1363 * We're done either when there isn't anymore space or the software FIFO
1364 * is empty
1365 */
1366 while (available && (fifo->head != fifo->tail)) {
1367 int i = fifo->tail;
1368 const uint32_t *ptr = cvmx_phys_to_ptr(fifo->entry[i].address);
1369 uint64_t csr_address = USB_FIFO_ADDRESS(fifo->entry[i].channel, usb->index) ^ 4;
1370 int words = available;
1371
1372 /* Limit the amount of data to waht the SW fifo has */
1373 if (fifo->entry[i].size <= available) {
1374 words = fifo->entry[i].size;
1375 fifo->tail++;
1376 if (fifo->tail > MAX_CHANNELS)
1377 fifo->tail = 0;
1378 }
1379
1380 /* Update the next locations and counts */
1381 available -= words;
1382 fifo->entry[i].address += words * 4;
1383 fifo->entry[i].size -= words;
1384
1385 /*
1386 * Write the HW fifo data. The read every three writes is due
1387 * to an errata on CN3XXX chips
1388 */
1389 while (words > 3) {
1390 cvmx_write64_uint32(csr_address, *ptr++);
1391 cvmx_write64_uint32(csr_address, *ptr++);
1392 cvmx_write64_uint32(csr_address, *ptr++);
1393 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
1394 words -= 3;
1395 }
1396 cvmx_write64_uint32(csr_address, *ptr++);
1397 if (--words) {
1398 cvmx_write64_uint32(csr_address, *ptr++);
1399 if (--words)
1400 cvmx_write64_uint32(csr_address, *ptr++);
1401 }
1402 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
1403 }
1404 return fifo->head != fifo->tail;
1405 }
1406
1407
1408 /**
1409 * Check the hardware FIFOs and fill them as needed
1410 *
1411 * @usb: USB device state populated by cvmx_usb_initialize().
1412 */
1413 static void __cvmx_usb_poll_tx_fifo(struct cvmx_usb_state *usb)
1414 {
1415 if (usb->periodic.head != usb->periodic.tail) {
1416 union cvmx_usbcx_hptxsts tx_status;
1417 tx_status.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPTXSTS(usb->index));
1418 if (__cvmx_usb_fill_tx_hw(usb, &usb->periodic, tx_status.s.ptxfspcavail))
1419 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk, ptxfempmsk, 1);
1420 else
1421 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk, ptxfempmsk, 0);
1422 }
1423
1424 if (usb->nonperiodic.head != usb->nonperiodic.tail) {
1425 union cvmx_usbcx_gnptxsts tx_status;
1426 tx_status.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GNPTXSTS(usb->index));
1427 if (__cvmx_usb_fill_tx_hw(usb, &usb->nonperiodic, tx_status.s.nptxfspcavail))
1428 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk, nptxfempmsk, 1);
1429 else
1430 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk, nptxfempmsk, 0);
1431 }
1432
1433 return;
1434 }
1435
1436
1437 /**
1438 * Fill the TX FIFO with an outgoing packet
1439 *
1440 * @usb: USB device state populated by cvmx_usb_initialize().
1441 * @channel: Channel number to get packet from
1442 */
1443 static void __cvmx_usb_fill_tx_fifo(struct cvmx_usb_state *usb, int channel)
1444 {
1445 union cvmx_usbcx_hccharx hcchar;
1446 union cvmx_usbcx_hcspltx usbc_hcsplt;
1447 union cvmx_usbcx_hctsizx usbc_hctsiz;
1448 struct cvmx_usb_tx_fifo *fifo;
1449
1450 /* We only need to fill data on outbound channels */
1451 hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index));
1452 if (hcchar.s.epdir != CVMX_USB_DIRECTION_OUT)
1453 return;
1454
1455 /* OUT Splits only have data on the start and not the complete */
1456 usbc_hcsplt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCSPLTX(channel, usb->index));
1457 if (usbc_hcsplt.s.spltena && usbc_hcsplt.s.compsplt)
1458 return;
1459
1460 /*
1461 * Find out how many bytes we need to fill and convert it into 32bit
1462 * words.
1463 */
1464 usbc_hctsiz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index));
1465 if (!usbc_hctsiz.s.xfersize)
1466 return;
1467
1468 if ((hcchar.s.eptype == CVMX_USB_TRANSFER_INTERRUPT) ||
1469 (hcchar.s.eptype == CVMX_USB_TRANSFER_ISOCHRONOUS))
1470 fifo = &usb->periodic;
1471 else
1472 fifo = &usb->nonperiodic;
1473
1474 fifo->entry[fifo->head].channel = channel;
1475 fifo->entry[fifo->head].address = __cvmx_usb_read_csr64(usb, CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8);
1476 fifo->entry[fifo->head].size = (usbc_hctsiz.s.xfersize+3)>>2;
1477 fifo->head++;
1478 if (fifo->head > MAX_CHANNELS)
1479 fifo->head = 0;
1480
1481 __cvmx_usb_poll_tx_fifo(usb);
1482
1483 return;
1484 }
1485
1486 /**
1487 * Perform channel specific setup for Control transactions. All
1488 * the generic stuff will already have been done in
1489 * __cvmx_usb_start_channel()
1490 *
1491 * @usb: USB device state populated by cvmx_usb_initialize().
1492 * @channel: Channel to setup
1493 * @pipe: Pipe for control transaction
1494 */
1495 static void __cvmx_usb_start_channel_control(struct cvmx_usb_state *usb,
1496 int channel,
1497 struct cvmx_usb_pipe *pipe)
1498 {
1499 struct cvmx_usb_transaction *transaction = pipe->head;
1500 union cvmx_usb_control_header *header =
1501 cvmx_phys_to_ptr(transaction->control_header);
1502 int bytes_to_transfer = transaction->buffer_length - transaction->actual_bytes;
1503 int packets_to_transfer;
1504 union cvmx_usbcx_hctsizx usbc_hctsiz;
1505
1506 usbc_hctsiz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index));
1507
1508 switch (transaction->stage) {
1509 case CVMX_USB_STAGE_NON_CONTROL:
1510 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE:
1511 cvmx_dprintf("%s: ERROR - Non control stage\n", __FUNCTION__);
1512 break;
1513 case CVMX_USB_STAGE_SETUP:
1514 usbc_hctsiz.s.pid = 3; /* Setup */
1515 bytes_to_transfer = sizeof(*header);
1516 /* All Control operations start with a setup going OUT */
1517 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), union cvmx_usbcx_hccharx, epdir, CVMX_USB_DIRECTION_OUT);
1518 /*
1519 * Setup send the control header instead of the buffer data. The
1520 * buffer data will be used in the next stage
1521 */
1522 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8, transaction->control_header);
1523 break;
1524 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE:
1525 usbc_hctsiz.s.pid = 3; /* Setup */
1526 bytes_to_transfer = 0;
1527 /* All Control operations start with a setup going OUT */
1528 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), union cvmx_usbcx_hccharx, epdir, CVMX_USB_DIRECTION_OUT);
1529 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), union cvmx_usbcx_hcspltx, compsplt, 1);
1530 break;
1531 case CVMX_USB_STAGE_DATA:
1532 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1533 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1534 if (header->s.request_type & 0x80)
1535 bytes_to_transfer = 0;
1536 else if (bytes_to_transfer > pipe->max_packet)
1537 bytes_to_transfer = pipe->max_packet;
1538 }
1539 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1540 union cvmx_usbcx_hccharx, epdir,
1541 ((header->s.request_type & 0x80) ?
1542 CVMX_USB_DIRECTION_IN :
1543 CVMX_USB_DIRECTION_OUT));
1544 break;
1545 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE:
1546 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1547 if (!(header->s.request_type & 0x80))
1548 bytes_to_transfer = 0;
1549 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1550 union cvmx_usbcx_hccharx, epdir,
1551 ((header->s.request_type & 0x80) ?
1552 CVMX_USB_DIRECTION_IN :
1553 CVMX_USB_DIRECTION_OUT));
1554 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), union cvmx_usbcx_hcspltx, compsplt, 1);
1555 break;
1556 case CVMX_USB_STAGE_STATUS:
1557 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1558 bytes_to_transfer = 0;
1559 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), union cvmx_usbcx_hccharx, epdir,
1560 ((header->s.request_type & 0x80) ?
1561 CVMX_USB_DIRECTION_OUT :
1562 CVMX_USB_DIRECTION_IN));
1563 break;
1564 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE:
1565 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1566 bytes_to_transfer = 0;
1567 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), union cvmx_usbcx_hccharx, epdir,
1568 ((header->s.request_type & 0x80) ?
1569 CVMX_USB_DIRECTION_OUT :
1570 CVMX_USB_DIRECTION_IN));
1571 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), union cvmx_usbcx_hcspltx, compsplt, 1);
1572 break;
1573 }
1574
1575 /*
1576 * Make sure the transfer never exceeds the byte limit of the hardware.
1577 * Further bytes will be sent as continued transactions
1578 */
1579 if (bytes_to_transfer > MAX_TRANSFER_BYTES) {
1580 /* Round MAX_TRANSFER_BYTES to a multiple of out packet size */
1581 bytes_to_transfer = MAX_TRANSFER_BYTES / pipe->max_packet;
1582 bytes_to_transfer *= pipe->max_packet;
1583 }
1584
1585 /*
1586 * Calculate the number of packets to transfer. If the length is zero
1587 * we still need to transfer one packet
1588 */
1589 packets_to_transfer = (bytes_to_transfer + pipe->max_packet - 1) / pipe->max_packet;
1590 if (packets_to_transfer == 0)
1591 packets_to_transfer = 1;
1592 else if ((packets_to_transfer > 1) && (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)) {
1593 /*
1594 * Limit to one packet when not using DMA. Channels must be
1595 * restarted between every packet for IN transactions, so there
1596 * is no reason to do multiple packets in a row
1597 */
1598 packets_to_transfer = 1;
1599 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1600 } else if (packets_to_transfer > MAX_TRANSFER_PACKETS) {
1601 /*
1602 * Limit the number of packet and data transferred to what the
1603 * hardware can handle
1604 */
1605 packets_to_transfer = MAX_TRANSFER_PACKETS;
1606 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1607 }
1608
1609 usbc_hctsiz.s.xfersize = bytes_to_transfer;
1610 usbc_hctsiz.s.pktcnt = packets_to_transfer;
1611
1612 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index), usbc_hctsiz.u32);
1613 return;
1614 }
1615
1616
1617 /**
1618 * Start a channel to perform the pipe's head transaction
1619 *
1620 * @usb: USB device state populated by cvmx_usb_initialize().
1621 * @channel: Channel to setup
1622 * @pipe: Pipe to start
1623 */
1624 static void __cvmx_usb_start_channel(struct cvmx_usb_state *usb,
1625 int channel,
1626 struct cvmx_usb_pipe *pipe)
1627 {
1628 struct cvmx_usb_transaction *transaction = pipe->head;
1629
1630 /* Make sure all writes to the DMA region get flushed */
1631 CVMX_SYNCW;
1632
1633 /* Attach the channel to the pipe */
1634 usb->pipe_for_channel[channel] = pipe;
1635 pipe->channel = channel;
1636 pipe->flags |= __CVMX_USB_PIPE_FLAGS_SCHEDULED;
1637
1638 /* Mark this channel as in use */
1639 usb->idle_hardware_channels &= ~(1<<channel);
1640
1641 /* Enable the channel interrupt bits */
1642 {
1643 union cvmx_usbcx_hcintx usbc_hcint;
1644 union cvmx_usbcx_hcintmskx usbc_hcintmsk;
1645 union cvmx_usbcx_haintmsk usbc_haintmsk;
1646
1647 /* Clear all channel status bits */
1648 usbc_hcint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCINTX(channel, usb->index));
1649 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTX(channel, usb->index), usbc_hcint.u32);
1650
1651 usbc_hcintmsk.u32 = 0;
1652 usbc_hcintmsk.s.chhltdmsk = 1;
1653 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) {
1654 /*
1655 * Channels need these extra interrupts when we aren't
1656 * in DMA mode.
1657 */
1658 usbc_hcintmsk.s.datatglerrmsk = 1;
1659 usbc_hcintmsk.s.frmovrunmsk = 1;
1660 usbc_hcintmsk.s.bblerrmsk = 1;
1661 usbc_hcintmsk.s.xacterrmsk = 1;
1662 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1663 /*
1664 * Splits don't generate xfercompl, so we need
1665 * ACK and NYET.
1666 */
1667 usbc_hcintmsk.s.nyetmsk = 1;
1668 usbc_hcintmsk.s.ackmsk = 1;
1669 }
1670 usbc_hcintmsk.s.nakmsk = 1;
1671 usbc_hcintmsk.s.stallmsk = 1;
1672 usbc_hcintmsk.s.xfercomplmsk = 1;
1673 }
1674 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), usbc_hcintmsk.u32);
1675
1676 /* Enable the channel interrupt to propagate */
1677 usbc_haintmsk.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HAINTMSK(usb->index));
1678 usbc_haintmsk.s.haintmsk |= 1<<channel;
1679 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HAINTMSK(usb->index), usbc_haintmsk.u32);
1680 }
1681
1682 /* Setup the locations the DMA engines use */
1683 {
1684 uint64_t dma_address = transaction->buffer + transaction->actual_bytes;
1685 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
1686 dma_address = transaction->buffer + transaction->iso_packets[0].offset + transaction->actual_bytes;
1687 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8, dma_address);
1688 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8, dma_address);
1689 }
1690
1691 /* Setup both the size of the transfer and the SPLIT characteristics */
1692 {
1693 union cvmx_usbcx_hcspltx usbc_hcsplt = {.u32 = 0};
1694 union cvmx_usbcx_hctsizx usbc_hctsiz = {.u32 = 0};
1695 int packets_to_transfer;
1696 int bytes_to_transfer = transaction->buffer_length - transaction->actual_bytes;
1697
1698 /*
1699 * ISOCHRONOUS transactions store each individual transfer size
1700 * in the packet structure, not the global buffer_length
1701 */
1702 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
1703 bytes_to_transfer = transaction->iso_packets[0].length - transaction->actual_bytes;
1704
1705 /*
1706 * We need to do split transactions when we are talking to non
1707 * high speed devices that are behind a high speed hub
1708 */
1709 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1710 /*
1711 * On the start split phase (stage is even) record the
1712 * frame number we will need to send the split complete.
1713 * We only store the lower two bits since the time ahead
1714 * can only be two frames
1715 */
1716 if ((transaction->stage&1) == 0) {
1717 if (transaction->type == CVMX_USB_TRANSFER_BULK)
1718 pipe->split_sc_frame = (usb->frame_number + 1) & 0x7f;
1719 else
1720 pipe->split_sc_frame = (usb->frame_number + 2) & 0x7f;
1721 } else
1722 pipe->split_sc_frame = -1;
1723
1724 usbc_hcsplt.s.spltena = 1;
1725 usbc_hcsplt.s.hubaddr = pipe->hub_device_addr;
1726 usbc_hcsplt.s.prtaddr = pipe->hub_port;
1727 usbc_hcsplt.s.compsplt = (transaction->stage == CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE);
1728
1729 /*
1730 * SPLIT transactions can only ever transmit one data
1731 * packet so limit the transfer size to the max packet
1732 * size
1733 */
1734 if (bytes_to_transfer > pipe->max_packet)
1735 bytes_to_transfer = pipe->max_packet;
1736
1737 /*
1738 * ISOCHRONOUS OUT splits are unique in that they limit
1739 * data transfers to 188 byte chunks representing the
1740 * begin/middle/end of the data or all
1741 */
1742 if (!usbc_hcsplt.s.compsplt &&
1743 (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) &&
1744 (pipe->transfer_type == CVMX_USB_TRANSFER_ISOCHRONOUS)) {
1745 /*
1746 * Clear the split complete frame number as
1747 * there isn't going to be a split complete
1748 */
1749 pipe->split_sc_frame = -1;
1750 /*
1751 * See if we've started this transfer and sent
1752 * data
1753 */
1754 if (transaction->actual_bytes == 0) {
1755 /*
1756 * Nothing sent yet, this is either a
1757 * begin or the entire payload
1758 */
1759 if (bytes_to_transfer <= 188)
1760 /* Entire payload in one go */
1761 usbc_hcsplt.s.xactpos = 3;
1762 else
1763 /* First part of payload */
1764 usbc_hcsplt.s.xactpos = 2;
1765 } else {
1766 /*
1767 * Continuing the previous data, we must
1768 * either be in the middle or at the end
1769 */
1770 if (bytes_to_transfer <= 188)
1771 /* End of payload */
1772 usbc_hcsplt.s.xactpos = 1;
1773 else
1774 /* Middle of payload */
1775 usbc_hcsplt.s.xactpos = 0;
1776 }
1777 /*
1778 * Again, the transfer size is limited to 188
1779 * bytes
1780 */
1781 if (bytes_to_transfer > 188)
1782 bytes_to_transfer = 188;
1783 }
1784 }
1785
1786 /*
1787 * Make sure the transfer never exceeds the byte limit of the
1788 * hardware. Further bytes will be sent as continued
1789 * transactions
1790 */
1791 if (bytes_to_transfer > MAX_TRANSFER_BYTES) {
1792 /*
1793 * Round MAX_TRANSFER_BYTES to a multiple of out packet
1794 * size
1795 */
1796 bytes_to_transfer = MAX_TRANSFER_BYTES / pipe->max_packet;
1797 bytes_to_transfer *= pipe->max_packet;
1798 }
1799
1800 /*
1801 * Calculate the number of packets to transfer. If the length is
1802 * zero we still need to transfer one packet
1803 */
1804 packets_to_transfer = (bytes_to_transfer + pipe->max_packet - 1) / pipe->max_packet;
1805 if (packets_to_transfer == 0)
1806 packets_to_transfer = 1;
1807 else if ((packets_to_transfer > 1) && (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)) {
1808 /*
1809 * Limit to one packet when not using DMA. Channels must
1810 * be restarted between every packet for IN
1811 * transactions, so there is no reason to do multiple
1812 * packets in a row
1813 */
1814 packets_to_transfer = 1;
1815 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1816 } else if (packets_to_transfer > MAX_TRANSFER_PACKETS) {
1817 /*
1818 * Limit the number of packet and data transferred to
1819 * what the hardware can handle
1820 */
1821 packets_to_transfer = MAX_TRANSFER_PACKETS;
1822 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1823 }
1824
1825 usbc_hctsiz.s.xfersize = bytes_to_transfer;
1826 usbc_hctsiz.s.pktcnt = packets_to_transfer;
1827
1828 /* Update the DATA0/DATA1 toggle */
1829 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1830 /*
1831 * High speed pipes may need a hardware ping before they start
1832 */
1833 if (pipe->flags & __CVMX_USB_PIPE_FLAGS_NEED_PING)
1834 usbc_hctsiz.s.dopng = 1;
1835
1836 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCSPLTX(channel, usb->index), usbc_hcsplt.u32);
1837 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index), usbc_hctsiz.u32);
1838 }
1839
1840 /* Setup the Host Channel Characteristics Register */
1841 {
1842 union cvmx_usbcx_hccharx usbc_hcchar = {.u32 = 0};
1843
1844 /*
1845 * Set the startframe odd/even properly. This is only used for
1846 * periodic
1847 */
1848 usbc_hcchar.s.oddfrm = usb->frame_number&1;
1849
1850 /*
1851 * Set the number of back to back packets allowed by this
1852 * endpoint. Split transactions interpret "ec" as the number of
1853 * immediate retries of failure. These retries happen too
1854 * quickly, so we disable these entirely for splits
1855 */
1856 if (__cvmx_usb_pipe_needs_split(usb, pipe))
1857 usbc_hcchar.s.ec = 1;
1858 else if (pipe->multi_count < 1)
1859 usbc_hcchar.s.ec = 1;
1860 else if (pipe->multi_count > 3)
1861 usbc_hcchar.s.ec = 3;
1862 else
1863 usbc_hcchar.s.ec = pipe->multi_count;
1864
1865 /* Set the rest of the endpoint specific settings */
1866 usbc_hcchar.s.devaddr = pipe->device_addr;
1867 usbc_hcchar.s.eptype = transaction->type;
1868 usbc_hcchar.s.lspddev = (pipe->device_speed == CVMX_USB_SPEED_LOW);
1869 usbc_hcchar.s.epdir = pipe->transfer_dir;
1870 usbc_hcchar.s.epnum = pipe->endpoint_num;
1871 usbc_hcchar.s.mps = pipe->max_packet;
1872 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index), usbc_hcchar.u32);
1873 }
1874
1875 /* Do transaction type specific fixups as needed */
1876 switch (transaction->type) {
1877 case CVMX_USB_TRANSFER_CONTROL:
1878 __cvmx_usb_start_channel_control(usb, channel, pipe);
1879 break;
1880 case CVMX_USB_TRANSFER_BULK:
1881 case CVMX_USB_TRANSFER_INTERRUPT:
1882 break;
1883 case CVMX_USB_TRANSFER_ISOCHRONOUS:
1884 if (!__cvmx_usb_pipe_needs_split(usb, pipe)) {
1885 /*
1886 * ISO transactions require different PIDs depending on
1887 * direction and how many packets are needed
1888 */
1889 if (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) {
1890 if (pipe->multi_count < 2) /* Need DATA0 */
1891 USB_SET_FIELD32(CVMX_USBCX_HCTSIZX(channel, usb->index), union cvmx_usbcx_hctsizx, pid, 0);
1892 else /* Need MDATA */
1893 USB_SET_FIELD32(CVMX_USBCX_HCTSIZX(channel, usb->index), union cvmx_usbcx_hctsizx, pid, 3);
1894 }
1895 }
1896 break;
1897 }
1898 {
1899 union cvmx_usbcx_hctsizx usbc_hctsiz = {.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index))};
1900 transaction->xfersize = usbc_hctsiz.s.xfersize;
1901 transaction->pktcnt = usbc_hctsiz.s.pktcnt;
1902 }
1903 /* Remeber when we start a split transaction */
1904 if (__cvmx_usb_pipe_needs_split(usb, pipe))
1905 usb->active_split = transaction;
1906 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), union cvmx_usbcx_hccharx, chena, 1);
1907 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
1908 __cvmx_usb_fill_tx_fifo(usb, channel);
1909 return;
1910 }
1911
1912
1913 /**
1914 * Find a pipe that is ready to be scheduled to hardware.
1915 * @usb: USB device state populated by cvmx_usb_initialize().
1916 * @list: Pipe list to search
1917 * @current_frame:
1918 * Frame counter to use as a time reference.
1919 *
1920 * Returns: Pipe or NULL if none are ready
1921 */
1922 static struct cvmx_usb_pipe *__cvmx_usb_find_ready_pipe(struct cvmx_usb_state *usb, struct cvmx_usb_pipe_list *list, uint64_t current_frame)
1923 {
1924 struct cvmx_usb_pipe *pipe = list->head;
1925 while (pipe) {
1926 if (!(pipe->flags & __CVMX_USB_PIPE_FLAGS_SCHEDULED) && pipe->head &&
1927 (pipe->next_tx_frame <= current_frame) &&
1928 ((pipe->split_sc_frame == -1) || ((((int)current_frame - (int)pipe->split_sc_frame) & 0x7f) < 0x40)) &&
1929 (!usb->active_split || (usb->active_split == pipe->head))) {
1930 CVMX_PREFETCH(pipe, 128);
1931 CVMX_PREFETCH(pipe->head, 0);
1932 return pipe;
1933 }
1934 pipe = pipe->next;
1935 }
1936 return NULL;
1937 }
1938
1939
1940 /**
1941 * Called whenever a pipe might need to be scheduled to the
1942 * hardware.
1943 *
1944 * @usb: USB device state populated by cvmx_usb_initialize().
1945 * @is_sof: True if this schedule was called on a SOF interrupt.
1946 */
1947 static void __cvmx_usb_schedule(struct cvmx_usb_state *usb, int is_sof)
1948 {
1949 int channel;
1950 struct cvmx_usb_pipe *pipe;
1951 int need_sof;
1952 enum cvmx_usb_transfer ttype;
1953
1954 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) {
1955 /*
1956 * Without DMA we need to be careful to not schedule something
1957 * at the end of a frame and cause an overrun.
1958 */
1959 union cvmx_usbcx_hfnum hfnum = {.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index))};
1960 union cvmx_usbcx_hfir hfir = {.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFIR(usb->index))};
1961 if (hfnum.s.frrem < hfir.s.frint/4)
1962 goto done;
1963 }
1964
1965 while (usb->idle_hardware_channels) {
1966 /* Find an idle channel */
1967 channel = __fls(usb->idle_hardware_channels);
1968 if (unlikely(channel > 7))
1969 break;
1970
1971 /* Find a pipe needing service */
1972 pipe = NULL;
1973 if (is_sof) {
1974 /*
1975 * Only process periodic pipes on SOF interrupts. This
1976 * way we are sure that the periodic data is sent in the
1977 * beginning of the frame
1978 */
1979 pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_ISOCHRONOUS, usb->frame_number);
1980 if (likely(!pipe))
1981 pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_INTERRUPT, usb->frame_number);
1982 }
1983 if (likely(!pipe)) {
1984 pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_CONTROL, usb->frame_number);
1985 if (likely(!pipe))
1986 pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_BULK, usb->frame_number);
1987 }
1988 if (!pipe)
1989 break;
1990
1991 __cvmx_usb_start_channel(usb, channel, pipe);
1992 }
1993
1994 done:
1995 /*
1996 * Only enable SOF interrupts when we have transactions pending in the
1997 * future that might need to be scheduled
1998 */
1999 need_sof = 0;
2000 for (ttype = CVMX_USB_TRANSFER_CONTROL; ttype <= CVMX_USB_TRANSFER_INTERRUPT; ttype++) {
2001 pipe = usb->active_pipes[ttype].head;
2002 while (pipe) {
2003 if (pipe->next_tx_frame > usb->frame_number) {
2004 need_sof = 1;
2005 break;
2006 }
2007 pipe = pipe->next;
2008 }
2009 }
2010 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk, sofmsk, need_sof);
2011 return;
2012 }
2013
2014 static inline struct octeon_hcd *cvmx_usb_to_octeon(struct cvmx_usb_state *p)
2015 {
2016 return container_of(p, struct octeon_hcd, usb);
2017 }
2018
2019 static inline struct usb_hcd *octeon_to_hcd(struct octeon_hcd *p)
2020 {
2021 return container_of((void *)p, struct usb_hcd, hcd_priv);
2022 }
2023
2024 static void octeon_usb_urb_complete_callback(struct cvmx_usb_state *usb,
2025 enum cvmx_usb_complete status,
2026 struct cvmx_usb_pipe *pipe,
2027 struct cvmx_usb_transaction
2028 *transaction,
2029 int bytes_transferred,
2030 struct urb *urb)
2031 {
2032 struct octeon_hcd *priv = cvmx_usb_to_octeon(usb);
2033 struct usb_hcd *hcd = octeon_to_hcd(priv);
2034 struct device *dev = hcd->self.controller;
2035
2036 urb->actual_length = bytes_transferred;
2037 urb->hcpriv = NULL;
2038
2039 if (!list_empty(&urb->urb_list))
2040 /*
2041 * It is on the dequeue_list, but we are going to call
2042 * usb_hcd_giveback_urb(), so we must clear it from
2043 * the list. We got to it before the
2044 * octeon_usb_urb_dequeue_work() tasklet did.
2045 */
2046 list_del_init(&urb->urb_list);
2047
2048 /* For Isochronous transactions we need to update the URB packet status
2049 list from data in our private copy */
2050 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2051 int i;
2052 /*
2053 * The pointer to the private list is stored in the setup_packet
2054 * field.
2055 */
2056 struct cvmx_usb_iso_packet *iso_packet =
2057 (struct cvmx_usb_iso_packet *) urb->setup_packet;
2058 /* Recalculate the transfer size by adding up each packet */
2059 urb->actual_length = 0;
2060 for (i = 0; i < urb->number_of_packets; i++) {
2061 if (iso_packet[i].status == CVMX_USB_COMPLETE_SUCCESS) {
2062 urb->iso_frame_desc[i].status = 0;
2063 urb->iso_frame_desc[i].actual_length = iso_packet[i].length;
2064 urb->actual_length += urb->iso_frame_desc[i].actual_length;
2065 } else {
2066 dev_dbg(dev, "ISOCHRONOUS packet=%d of %d status=%d pipe=%p transaction=%p size=%d\n",
2067 i, urb->number_of_packets,
2068 iso_packet[i].status, pipe,
2069 transaction, iso_packet[i].length);
2070 urb->iso_frame_desc[i].status = -EREMOTEIO;
2071 }
2072 }
2073 /* Free the private list now that we don't need it anymore */
2074 kfree(iso_packet);
2075 urb->setup_packet = NULL;
2076 }
2077
2078 switch (status) {
2079 case CVMX_USB_COMPLETE_SUCCESS:
2080 urb->status = 0;
2081 break;
2082 case CVMX_USB_COMPLETE_CANCEL:
2083 if (urb->status == 0)
2084 urb->status = -ENOENT;
2085 break;
2086 case CVMX_USB_COMPLETE_STALL:
2087 dev_dbg(dev, "status=stall pipe=%p transaction=%p size=%d\n",
2088 pipe, transaction, bytes_transferred);
2089 urb->status = -EPIPE;
2090 break;
2091 case CVMX_USB_COMPLETE_BABBLEERR:
2092 dev_dbg(dev, "status=babble pipe=%p transaction=%p size=%d\n",
2093 pipe, transaction, bytes_transferred);
2094 urb->status = -EPIPE;
2095 break;
2096 case CVMX_USB_COMPLETE_SHORT:
2097 dev_dbg(dev, "status=short pipe=%p transaction=%p size=%d\n",
2098 pipe, transaction, bytes_transferred);
2099 urb->status = -EREMOTEIO;
2100 break;
2101 case CVMX_USB_COMPLETE_ERROR:
2102 case CVMX_USB_COMPLETE_XACTERR:
2103 case CVMX_USB_COMPLETE_DATATGLERR:
2104 case CVMX_USB_COMPLETE_FRAMEERR:
2105 dev_dbg(dev, "status=%d pipe=%p transaction=%p size=%d\n",
2106 status, pipe, transaction, bytes_transferred);
2107 urb->status = -EPROTO;
2108 break;
2109 }
2110 spin_unlock(&priv->lock);
2111 usb_hcd_giveback_urb(octeon_to_hcd(priv), urb, urb->status);
2112 spin_lock(&priv->lock);
2113 }
2114
2115 /**
2116 * Signal the completion of a transaction and free it. The
2117 * transaction will be removed from the pipe transaction list.
2118 *
2119 * @usb: USB device state populated by cvmx_usb_initialize().
2120 * @pipe: Pipe the transaction is on
2121 * @transaction:
2122 * Transaction that completed
2123 * @complete_code:
2124 * Completion code
2125 */
2126 static void __cvmx_usb_perform_complete(struct cvmx_usb_state *usb,
2127 struct cvmx_usb_pipe *pipe,
2128 struct cvmx_usb_transaction *transaction,
2129 enum cvmx_usb_complete complete_code)
2130 {
2131 /* If this was a split then clear our split in progress marker */
2132 if (usb->active_split == transaction)
2133 usb->active_split = NULL;
2134
2135 /*
2136 * Isochronous transactions need extra processing as they might not be
2137 * done after a single data transfer
2138 */
2139 if (unlikely(transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)) {
2140 /* Update the number of bytes transferred in this ISO packet */
2141 transaction->iso_packets[0].length = transaction->actual_bytes;
2142 transaction->iso_packets[0].status = complete_code;
2143
2144 /*
2145 * If there are more ISOs pending and we succeeded, schedule the
2146 * next one
2147 */
2148 if ((transaction->iso_number_packets > 1) && (complete_code == CVMX_USB_COMPLETE_SUCCESS)) {
2149 /* No bytes transferred for this packet as of yet */
2150 transaction->actual_bytes = 0;
2151 /* One less ISO waiting to transfer */
2152 transaction->iso_number_packets--;
2153 /* Increment to the next location in our packet array */
2154 transaction->iso_packets++;
2155 transaction->stage = CVMX_USB_STAGE_NON_CONTROL;
2156 goto done;
2157 }
2158 }
2159
2160 /* Remove the transaction from the pipe list */
2161 if (transaction->next)
2162 transaction->next->prev = transaction->prev;
2163 else
2164 pipe->tail = transaction->prev;
2165 if (transaction->prev)
2166 transaction->prev->next = transaction->next;
2167 else
2168 pipe->head = transaction->next;
2169 if (!pipe->head) {
2170 __cvmx_usb_remove_pipe(usb->active_pipes + pipe->transfer_type, pipe);
2171 __cvmx_usb_append_pipe(&usb->idle_pipes, pipe);
2172
2173 }
2174 octeon_usb_urb_complete_callback(usb, complete_code, pipe,
2175 transaction,
2176 transaction->actual_bytes,
2177 transaction->urb);
2178 kfree(transaction);
2179 done:
2180 return;
2181 }
2182
2183
2184 /**
2185 * Submit a usb transaction to a pipe. Called for all types
2186 * of transactions.
2187 *
2188 * @usb:
2189 * @pipe: Which pipe to submit to.
2190 * @type: Transaction type
2191 * @buffer: User buffer for the transaction
2192 * @buffer_length:
2193 * User buffer's length in bytes
2194 * @control_header:
2195 * For control transactions, the 8 byte standard header
2196 * @iso_start_frame:
2197 * For ISO transactions, the start frame
2198 * @iso_number_packets:
2199 * For ISO, the number of packet in the transaction.
2200 * @iso_packets:
2201 * A description of each ISO packet
2202 * @urb: URB for the callback
2203 *
2204 * Returns: Transaction or NULL on failure.
2205 */
2206 static struct cvmx_usb_transaction *__cvmx_usb_submit_transaction(struct cvmx_usb_state *usb,
2207 struct cvmx_usb_pipe *pipe,
2208 enum cvmx_usb_transfer type,
2209 uint64_t buffer,
2210 int buffer_length,
2211 uint64_t control_header,
2212 int iso_start_frame,
2213 int iso_number_packets,
2214 struct cvmx_usb_iso_packet *iso_packets,
2215 struct urb *urb)
2216 {
2217 struct cvmx_usb_transaction *transaction;
2218
2219 if (unlikely(pipe->transfer_type != type))
2220 return NULL;
2221
2222 transaction = kzalloc(sizeof(*transaction), GFP_ATOMIC);
2223 if (unlikely(!transaction))
2224 return NULL;
2225
2226 transaction->type = type;
2227 transaction->buffer = buffer;
2228 transaction->buffer_length = buffer_length;
2229 transaction->control_header = control_header;
2230 /* FIXME: This is not used, implement it. */
2231 transaction->iso_start_frame = iso_start_frame;
2232 transaction->iso_number_packets = iso_number_packets;
2233 transaction->iso_packets = iso_packets;
2234 transaction->urb = urb;
2235 if (transaction->type == CVMX_USB_TRANSFER_CONTROL)
2236 transaction->stage = CVMX_USB_STAGE_SETUP;
2237 else
2238 transaction->stage = CVMX_USB_STAGE_NON_CONTROL;
2239
2240 transaction->next = NULL;
2241 if (pipe->tail) {
2242 transaction->prev = pipe->tail;
2243 transaction->prev->next = transaction;
2244 } else {
2245 if (pipe->next_tx_frame < usb->frame_number)
2246 pipe->next_tx_frame = usb->frame_number + pipe->interval -
2247 (usb->frame_number - pipe->next_tx_frame) % pipe->interval;
2248 transaction->prev = NULL;
2249 pipe->head = transaction;
2250 __cvmx_usb_remove_pipe(&usb->idle_pipes, pipe);
2251 __cvmx_usb_append_pipe(usb->active_pipes + pipe->transfer_type, pipe);
2252 }
2253 pipe->tail = transaction;
2254
2255 /* We may need to schedule the pipe if this was the head of the pipe */
2256 if (!transaction->prev)
2257 __cvmx_usb_schedule(usb, 0);
2258
2259 return transaction;
2260 }
2261
2262
2263 /**
2264 * Call to submit a USB Bulk transfer to a pipe.
2265 *
2266 * @usb: USB device state populated by cvmx_usb_initialize().
2267 * @pipe: Handle to the pipe for the transfer.
2268 * @urb: URB.
2269 *
2270 * Returns: A submitted transaction or NULL on failure.
2271 */
2272 static struct cvmx_usb_transaction *cvmx_usb_submit_bulk(struct cvmx_usb_state *usb,
2273 struct cvmx_usb_pipe *pipe,
2274 struct urb *urb)
2275 {
2276 return __cvmx_usb_submit_transaction(usb, pipe, CVMX_USB_TRANSFER_BULK,
2277 urb->transfer_dma,
2278 urb->transfer_buffer_length,
2279 0, /* control_header */
2280 0, /* iso_start_frame */
2281 0, /* iso_number_packets */
2282 NULL, /* iso_packets */
2283 urb);
2284 }
2285
2286
2287 /**
2288 * Call to submit a USB Interrupt transfer to a pipe.
2289 *
2290 * @usb: USB device state populated by cvmx_usb_initialize().
2291 * @pipe: Handle to the pipe for the transfer.
2292 * @urb: URB returned when the callback is called.
2293 *
2294 * Returns: A submitted transaction or NULL on failure.
2295 */
2296 static struct cvmx_usb_transaction *cvmx_usb_submit_interrupt(struct cvmx_usb_state *usb,
2297 struct cvmx_usb_pipe *pipe,
2298 struct urb *urb)
2299 {
2300 return __cvmx_usb_submit_transaction(usb, pipe,
2301 CVMX_USB_TRANSFER_INTERRUPT,
2302 urb->transfer_dma,
2303 urb->transfer_buffer_length,
2304 0, /* control_header */
2305 0, /* iso_start_frame */
2306 0, /* iso_number_packets */
2307 NULL, /* iso_packets */
2308 urb);
2309 }
2310
2311
2312 /**
2313 * Call to submit a USB Control transfer to a pipe.
2314 *
2315 * @usb: USB device state populated by cvmx_usb_initialize().
2316 * @pipe: Handle to the pipe for the transfer.
2317 * @urb: URB.
2318 *
2319 * Returns: A submitted transaction or NULL on failure.
2320 */
2321 static struct cvmx_usb_transaction *cvmx_usb_submit_control(struct cvmx_usb_state *usb,
2322 struct cvmx_usb_pipe *pipe,
2323 struct urb *urb)
2324 {
2325 int buffer_length = urb->transfer_buffer_length;
2326 uint64_t control_header = urb->setup_dma;
2327 union cvmx_usb_control_header *header =
2328 cvmx_phys_to_ptr(control_header);
2329
2330 if ((header->s.request_type & 0x80) == 0)
2331 buffer_length = le16_to_cpu(header->s.length);
2332
2333 return __cvmx_usb_submit_transaction(usb, pipe,
2334 CVMX_USB_TRANSFER_CONTROL,
2335 urb->transfer_dma, buffer_length,
2336 control_header,
2337 0, /* iso_start_frame */
2338 0, /* iso_number_packets */
2339 NULL, /* iso_packets */
2340 urb);
2341 }
2342
2343
2344 /**
2345 * Call to submit a USB Isochronous transfer to a pipe.
2346 *
2347 * @usb: USB device state populated by cvmx_usb_initialize().
2348 * @pipe: Handle to the pipe for the transfer.
2349 * @urb: URB returned when the callback is called.
2350 *
2351 * Returns: A submitted transaction or NULL on failure.
2352 */
2353 static struct cvmx_usb_transaction *cvmx_usb_submit_isochronous(struct cvmx_usb_state *usb,
2354 struct cvmx_usb_pipe *pipe,
2355 struct urb *urb)
2356 {
2357 struct cvmx_usb_iso_packet *packets;
2358
2359 packets = (struct cvmx_usb_iso_packet *) urb->setup_packet;
2360 return __cvmx_usb_submit_transaction(usb, pipe,
2361 CVMX_USB_TRANSFER_ISOCHRONOUS,
2362 urb->transfer_dma,
2363 urb->transfer_buffer_length,
2364 0, /* control_header */
2365 urb->start_frame,
2366 urb->number_of_packets,
2367 packets, urb);
2368 }
2369
2370
2371 /**
2372 * Cancel one outstanding request in a pipe. Canceling a request
2373 * can fail if the transaction has already completed before cancel
2374 * is called. Even after a successful cancel call, it may take
2375 * a frame or two for the cvmx_usb_poll() function to call the
2376 * associated callback.
2377 *
2378 * @usb: USB device state populated by cvmx_usb_initialize().
2379 * @pipe: Pipe to cancel requests in.
2380 * @transaction: Transaction to cancel, returned by the submit function.
2381 *
2382 * Returns: 0 or a negative error code.
2383 */
2384 static int cvmx_usb_cancel(struct cvmx_usb_state *usb,
2385 struct cvmx_usb_pipe *pipe,
2386 struct cvmx_usb_transaction *transaction)
2387 {
2388 /*
2389 * If the transaction is the HEAD of the queue and scheduled. We need to
2390 * treat it special
2391 */
2392 if ((pipe->head == transaction) &&
2393 (pipe->flags & __CVMX_USB_PIPE_FLAGS_SCHEDULED)) {
2394 union cvmx_usbcx_hccharx usbc_hcchar;
2395
2396 usb->pipe_for_channel[pipe->channel] = NULL;
2397 pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_SCHEDULED;
2398
2399 CVMX_SYNCW;
2400
2401 usbc_hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(pipe->channel, usb->index));
2402 /*
2403 * If the channel isn't enabled then the transaction already
2404 * completed.
2405 */
2406 if (usbc_hcchar.s.chena) {
2407 usbc_hcchar.s.chdis = 1;
2408 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(pipe->channel, usb->index), usbc_hcchar.u32);
2409 }
2410 }
2411 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_CANCEL);
2412 return 0;
2413 }
2414
2415
2416 /**
2417 * Cancel all outstanding requests in a pipe. Logically all this
2418 * does is call cvmx_usb_cancel() in a loop.
2419 *
2420 * @usb: USB device state populated by cvmx_usb_initialize().
2421 * @pipe: Pipe to cancel requests in.
2422 *
2423 * Returns: 0 or a negative error code.
2424 */
2425 static int cvmx_usb_cancel_all(struct cvmx_usb_state *usb,
2426 struct cvmx_usb_pipe *pipe)
2427 {
2428 /* Simply loop through and attempt to cancel each transaction */
2429 while (pipe->head) {
2430 int result = cvmx_usb_cancel(usb, pipe, pipe->head);
2431 if (unlikely(result != 0))
2432 return result;
2433 }
2434 return 0;
2435 }
2436
2437
2438 /**
2439 * Close a pipe created with cvmx_usb_open_pipe().
2440 *
2441 * @usb: USB device state populated by cvmx_usb_initialize().
2442 * @pipe: Pipe to close.
2443 *
2444 * Returns: 0 or a negative error code. EBUSY is returned if the pipe has
2445 * outstanding transfers.
2446 */
2447 static int cvmx_usb_close_pipe(struct cvmx_usb_state *usb,
2448 struct cvmx_usb_pipe *pipe)
2449 {
2450 /* Fail if the pipe has pending transactions */
2451 if (unlikely(pipe->head))
2452 return -EBUSY;
2453
2454 __cvmx_usb_remove_pipe(&usb->idle_pipes, pipe);
2455 kfree(pipe);
2456
2457 return 0;
2458 }
2459
2460 /**
2461 * Get the current USB protocol level frame number. The frame
2462 * number is always in the range of 0-0x7ff.
2463 *
2464 * @usb: USB device state populated by cvmx_usb_initialize().
2465 *
2466 * Returns: USB frame number
2467 */
2468 static int cvmx_usb_get_frame_number(struct cvmx_usb_state *usb)
2469 {
2470 int frame_number;
2471 union cvmx_usbcx_hfnum usbc_hfnum;
2472
2473 usbc_hfnum.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index));
2474 frame_number = usbc_hfnum.s.frnum;
2475
2476 return frame_number;
2477 }
2478
2479
2480 /**
2481 * Poll a channel for status
2482 *
2483 * @usb: USB device
2484 * @channel: Channel to poll
2485 *
2486 * Returns: Zero on success
2487 */
2488 static int __cvmx_usb_poll_channel(struct cvmx_usb_state *usb, int channel)
2489 {
2490 union cvmx_usbcx_hcintx usbc_hcint;
2491 union cvmx_usbcx_hctsizx usbc_hctsiz;
2492 union cvmx_usbcx_hccharx usbc_hcchar;
2493 struct cvmx_usb_pipe *pipe;
2494 struct cvmx_usb_transaction *transaction;
2495 int bytes_this_transfer;
2496 int bytes_in_last_packet;
2497 int packets_processed;
2498 int buffer_space_left;
2499
2500 /* Read the interrupt status bits for the channel */
2501 usbc_hcint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCINTX(channel, usb->index));
2502
2503 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) {
2504 usbc_hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index));
2505
2506 if (usbc_hcchar.s.chena && usbc_hcchar.s.chdis) {
2507 /*
2508 * There seems to be a bug in CN31XX which can cause
2509 * interrupt IN transfers to get stuck until we do a
2510 * write of HCCHARX without changing things
2511 */
2512 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index), usbc_hcchar.u32);
2513 return 0;
2514 }
2515
2516 /*
2517 * In non DMA mode the channels don't halt themselves. We need
2518 * to manually disable channels that are left running
2519 */
2520 if (!usbc_hcint.s.chhltd) {
2521 if (usbc_hcchar.s.chena) {
2522 union cvmx_usbcx_hcintmskx hcintmsk;
2523 /* Disable all interrupts except CHHLTD */
2524 hcintmsk.u32 = 0;
2525 hcintmsk.s.chhltdmsk = 1;
2526 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), hcintmsk.u32);
2527 usbc_hcchar.s.chdis = 1;
2528 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index), usbc_hcchar.u32);
2529 return 0;
2530 } else if (usbc_hcint.s.xfercompl) {
2531 /*
2532 * Successful IN/OUT with transfer complete.
2533 * Channel halt isn't needed.
2534 */
2535 } else {
2536 cvmx_dprintf("USB%d: Channel %d interrupt without halt\n", usb->index, channel);
2537 return 0;
2538 }
2539 }
2540 } else {
2541 /*
2542 * There is are no interrupts that we need to process when the
2543 * channel is still running
2544 */
2545 if (!usbc_hcint.s.chhltd)
2546 return 0;
2547 }
2548
2549 /* Disable the channel interrupts now that it is done */
2550 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), 0);
2551 usb->idle_hardware_channels |= (1<<channel);
2552
2553 /* Make sure this channel is tied to a valid pipe */
2554 pipe = usb->pipe_for_channel[channel];
2555 CVMX_PREFETCH(pipe, 0);
2556 CVMX_PREFETCH(pipe, 128);
2557 if (!pipe)
2558 return 0;
2559 transaction = pipe->head;
2560 CVMX_PREFETCH(transaction, 0);
2561
2562 /*
2563 * Disconnect this pipe from the HW channel. Later the schedule
2564 * function will figure out which pipe needs to go
2565 */
2566 usb->pipe_for_channel[channel] = NULL;
2567 pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_SCHEDULED;
2568
2569 /*
2570 * Read the channel config info so we can figure out how much data
2571 * transfered
2572 */
2573 usbc_hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index));
2574 usbc_hctsiz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index));
2575
2576 /*
2577 * Calculating the number of bytes successfully transferred is dependent
2578 * on the transfer direction
2579 */
2580 packets_processed = transaction->pktcnt - usbc_hctsiz.s.pktcnt;
2581 if (usbc_hcchar.s.epdir) {
2582 /*
2583 * IN transactions are easy. For every byte received the
2584 * hardware decrements xfersize. All we need to do is subtract
2585 * the current value of xfersize from its starting value and we
2586 * know how many bytes were written to the buffer
2587 */
2588 bytes_this_transfer = transaction->xfersize - usbc_hctsiz.s.xfersize;
2589 } else {
2590 /*
2591 * OUT transaction don't decrement xfersize. Instead pktcnt is
2592 * decremented on every successful packet send. The hardware
2593 * does this when it receives an ACK, or NYET. If it doesn't
2594 * receive one of these responses pktcnt doesn't change
2595 */
2596 bytes_this_transfer = packets_processed * usbc_hcchar.s.mps;
2597 /*
2598 * The last packet may not be a full transfer if we didn't have
2599 * enough data
2600 */
2601 if (bytes_this_transfer > transaction->xfersize)
2602 bytes_this_transfer = transaction->xfersize;
2603 }
2604 /* Figure out how many bytes were in the last packet of the transfer */
2605 if (packets_processed)
2606 bytes_in_last_packet = bytes_this_transfer - (packets_processed-1) * usbc_hcchar.s.mps;
2607 else
2608 bytes_in_last_packet = bytes_this_transfer;
2609
2610 /*
2611 * As a special case, setup transactions output the setup header, not
2612 * the user's data. For this reason we don't count setup data as bytes
2613 * transferred
2614 */
2615 if ((transaction->stage == CVMX_USB_STAGE_SETUP) ||
2616 (transaction->stage == CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE))
2617 bytes_this_transfer = 0;
2618
2619 /*
2620 * Add the bytes transferred to the running total. It is important that
2621 * bytes_this_transfer doesn't count any data that needs to be
2622 * retransmitted
2623 */
2624 transaction->actual_bytes += bytes_this_transfer;
2625 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
2626 buffer_space_left = transaction->iso_packets[0].length - transaction->actual_bytes;
2627 else
2628 buffer_space_left = transaction->buffer_length - transaction->actual_bytes;
2629
2630 /*
2631 * We need to remember the PID toggle state for the next transaction.
2632 * The hardware already updated it for the next transaction
2633 */
2634 pipe->pid_toggle = !(usbc_hctsiz.s.pid == 0);
2635
2636 /*
2637 * For high speed bulk out, assume the next transaction will need to do
2638 * a ping before proceeding. If this isn't true the ACK processing below
2639 * will clear this flag
2640 */
2641 if ((pipe->device_speed == CVMX_USB_SPEED_HIGH) &&
2642 (pipe->transfer_type == CVMX_USB_TRANSFER_BULK) &&
2643 (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT))
2644 pipe->flags |= __CVMX_USB_PIPE_FLAGS_NEED_PING;
2645
2646 if (usbc_hcint.s.stall) {
2647 /*
2648 * STALL as a response means this transaction cannot be
2649 * completed because the device can't process transactions. Tell
2650 * the user. Any data that was transferred will be counted on
2651 * the actual bytes transferred
2652 */
2653 pipe->pid_toggle = 0;
2654 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_STALL);
2655 } else if (usbc_hcint.s.xacterr) {
2656 /*
2657 * We know at least one packet worked if we get a ACK or NAK.
2658 * Reset the retry counter
2659 */
2660 if (usbc_hcint.s.nak || usbc_hcint.s.ack)
2661 transaction->retries = 0;
2662 transaction->retries++;
2663 if (transaction->retries > MAX_RETRIES) {
2664 /*
2665 * XactErr as a response means the device signaled
2666 * something wrong with the transfer. For example, PID
2667 * toggle errors cause these
2668 */
2669 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_XACTERR);
2670 } else {
2671 /*
2672 * If this was a split then clear our split in progress
2673 * marker
2674 */
2675 if (usb->active_split == transaction)
2676 usb->active_split = NULL;
2677 /*
2678 * Rewind to the beginning of the transaction by anding
2679 * off the split complete bit
2680 */
2681 transaction->stage &= ~1;
2682 pipe->split_sc_frame = -1;
2683 pipe->next_tx_frame += pipe->interval;
2684 if (pipe->next_tx_frame < usb->frame_number)
2685 pipe->next_tx_frame = usb->frame_number + pipe->interval -
2686 (usb->frame_number - pipe->next_tx_frame) % pipe->interval;
2687 }
2688 } else if (usbc_hcint.s.bblerr) {
2689 /* Babble Error (BblErr) */
2690 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_BABBLEERR);
2691 } else if (usbc_hcint.s.datatglerr) {
2692 /* We'll retry the exact same transaction again */
2693 transaction->retries++;
2694 } else if (usbc_hcint.s.nyet) {
2695 /*
2696 * NYET as a response is only allowed in three cases: as a
2697 * response to a ping, as a response to a split transaction, and
2698 * as a response to a bulk out. The ping case is handled by
2699 * hardware, so we only have splits and bulk out
2700 */
2701 if (!__cvmx_usb_pipe_needs_split(usb, pipe)) {
2702 transaction->retries = 0;
2703 /*
2704 * If there is more data to go then we need to try
2705 * again. Otherwise this transaction is complete
2706 */
2707 if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet))
2708 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2709 } else {
2710 /*
2711 * Split transactions retry the split complete 4 times
2712 * then rewind to the start split and do the entire
2713 * transactions again
2714 */
2715 transaction->retries++;
2716 if ((transaction->retries & 0x3) == 0) {
2717 /*
2718 * Rewind to the beginning of the transaction by
2719 * anding off the split complete bit
2720 */
2721 transaction->stage &= ~1;
2722 pipe->split_sc_frame = -1;
2723 }
2724 }
2725 } else if (usbc_hcint.s.ack) {
2726 transaction->retries = 0;
2727 /*
2728 * The ACK bit can only be checked after the other error bits.
2729 * This is because a multi packet transfer may succeed in a
2730 * number of packets and then get a different response on the
2731 * last packet. In this case both ACK and the last response bit
2732 * will be set. If none of the other response bits is set, then
2733 * the last packet must have been an ACK
2734 *
2735 * Since we got an ACK, we know we don't need to do a ping on
2736 * this pipe
2737 */
2738 pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_NEED_PING;
2739
2740 switch (transaction->type) {
2741 case CVMX_USB_TRANSFER_CONTROL:
2742 switch (transaction->stage) {
2743 case CVMX_USB_STAGE_NON_CONTROL:
2744 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE:
2745 /* This should be impossible */
2746 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_ERROR);
2747 break;
2748 case CVMX_USB_STAGE_SETUP:
2749 pipe->pid_toggle = 1;
2750 if (__cvmx_usb_pipe_needs_split(usb, pipe))
2751 transaction->stage = CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE;
2752 else {
2753 union cvmx_usb_control_header *header =
2754 cvmx_phys_to_ptr(transaction->control_header);
2755 if (header->s.length)
2756 transaction->stage = CVMX_USB_STAGE_DATA;
2757 else
2758 transaction->stage = CVMX_USB_STAGE_STATUS;
2759 }
2760 break;
2761 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE:
2762 {
2763 union cvmx_usb_control_header *header =
2764 cvmx_phys_to_ptr(transaction->control_header);
2765 if (header->s.length)
2766 transaction->stage = CVMX_USB_STAGE_DATA;
2767 else
2768 transaction->stage = CVMX_USB_STAGE_STATUS;
2769 }
2770 break;
2771 case CVMX_USB_STAGE_DATA:
2772 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
2773 transaction->stage = CVMX_USB_STAGE_DATA_SPLIT_COMPLETE;
2774 /*
2775 * For setup OUT data that are splits,
2776 * the hardware doesn't appear to count
2777 * transferred data. Here we manually
2778 * update the data transferred
2779 */
2780 if (!usbc_hcchar.s.epdir) {
2781 if (buffer_space_left < pipe->max_packet)
2782 transaction->actual_bytes += buffer_space_left;
2783 else
2784 transaction->actual_bytes += pipe->max_packet;
2785 }
2786 } else if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet)) {
2787 pipe->pid_toggle = 1;
2788 transaction->stage = CVMX_USB_STAGE_STATUS;
2789 }
2790 break;
2791 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE:
2792 if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet)) {
2793 pipe->pid_toggle = 1;
2794 transaction->stage = CVMX_USB_STAGE_STATUS;
2795 } else {
2796 transaction->stage = CVMX_USB_STAGE_DATA;
2797 }
2798 break;
2799 case CVMX_USB_STAGE_STATUS:
2800 if (__cvmx_usb_pipe_needs_split(usb, pipe))
2801 transaction->stage = CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE;
2802 else
2803 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2804 break;
2805 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE:
2806 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2807 break;
2808 }
2809 break;
2810 case CVMX_USB_TRANSFER_BULK:
2811 case CVMX_USB_TRANSFER_INTERRUPT:
2812 /*
2813 * The only time a bulk transfer isn't complete when it
2814 * finishes with an ACK is during a split transaction.
2815 * For splits we need to continue the transfer if more
2816 * data is needed
2817 */
2818 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
2819 if (transaction->stage == CVMX_USB_STAGE_NON_CONTROL)
2820 transaction->stage = CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE;
2821 else {
2822 if (buffer_space_left && (bytes_in_last_packet == pipe->max_packet))
2823 transaction->stage = CVMX_USB_STAGE_NON_CONTROL;
2824 else {
2825 if (transaction->type == CVMX_USB_TRANSFER_INTERRUPT)
2826 pipe->next_tx_frame += pipe->interval;
2827 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2828 }
2829 }
2830 } else {
2831 if ((pipe->device_speed == CVMX_USB_SPEED_HIGH) &&
2832 (pipe->transfer_type == CVMX_USB_TRANSFER_BULK) &&
2833 (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) &&
2834 (usbc_hcint.s.nak))
2835 pipe->flags |= __CVMX_USB_PIPE_FLAGS_NEED_PING;
2836 if (!buffer_space_left || (bytes_in_last_packet < pipe->max_packet)) {
2837 if (transaction->type == CVMX_USB_TRANSFER_INTERRUPT)
2838 pipe->next_tx_frame += pipe->interval;
2839 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2840 }
2841 }
2842 break;
2843 case CVMX_USB_TRANSFER_ISOCHRONOUS:
2844 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
2845 /*
2846 * ISOCHRONOUS OUT splits don't require a
2847 * complete split stage. Instead they use a
2848 * sequence of begin OUT splits to transfer the
2849 * data 188 bytes at a time. Once the transfer
2850 * is complete, the pipe sleeps until the next
2851 * schedule interval
2852 */
2853 if (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) {
2854 /*
2855 * If no space left or this wasn't a max
2856 * size packet then this transfer is
2857 * complete. Otherwise start it again to
2858 * send the next 188 bytes
2859 */
2860 if (!buffer_space_left || (bytes_this_transfer < 188)) {
2861 pipe->next_tx_frame += pipe->interval;
2862 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2863 }
2864 } else {
2865 if (transaction->stage == CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE) {
2866 /*
2867 * We are in the incoming data
2868 * phase. Keep getting data
2869 * until we run out of space or
2870 * get a small packet
2871 */
2872 if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet)) {
2873 pipe->next_tx_frame += pipe->interval;
2874 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2875 }
2876 } else
2877 transaction->stage = CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE;
2878 }
2879 } else {
2880 pipe->next_tx_frame += pipe->interval;
2881 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2882 }
2883 break;
2884 }
2885 } else if (usbc_hcint.s.nak) {
2886 /*
2887 * If this was a split then clear our split in progress marker.
2888 */
2889 if (usb->active_split == transaction)
2890 usb->active_split = NULL;
2891 /*
2892 * NAK as a response means the device couldn't accept the
2893 * transaction, but it should be retried in the future. Rewind
2894 * to the beginning of the transaction by anding off the split
2895 * complete bit. Retry in the next interval
2896 */
2897 transaction->retries = 0;
2898 transaction->stage &= ~1;
2899 pipe->next_tx_frame += pipe->interval;
2900 if (pipe->next_tx_frame < usb->frame_number)
2901 pipe->next_tx_frame = usb->frame_number + pipe->interval -
2902 (usb->frame_number - pipe->next_tx_frame) % pipe->interval;
2903 } else {
2904 struct cvmx_usb_port_status port;
2905 port = cvmx_usb_get_status(usb);
2906 if (port.port_enabled) {
2907 /* We'll retry the exact same transaction again */
2908 transaction->retries++;
2909 } else {
2910 /*
2911 * We get channel halted interrupts with no result bits
2912 * sets when the cable is unplugged
2913 */
2914 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_ERROR);
2915 }
2916 }
2917 return 0;
2918 }
2919
2920 static void octeon_usb_port_callback(struct cvmx_usb_state *usb)
2921 {
2922 struct octeon_hcd *priv = cvmx_usb_to_octeon(usb);
2923
2924 spin_unlock(&priv->lock);
2925 usb_hcd_poll_rh_status(octeon_to_hcd(priv));
2926 spin_lock(&priv->lock);
2927 }
2928
2929 /**
2930 * Poll the USB block for status and call all needed callback
2931 * handlers. This function is meant to be called in the interrupt
2932 * handler for the USB controller. It can also be called
2933 * periodically in a loop for non-interrupt based operation.
2934 *
2935 * @usb: USB device state populated by cvmx_usb_initialize().
2936 *
2937 * Returns: 0 or a negative error code.
2938 */
2939 static int cvmx_usb_poll(struct cvmx_usb_state *usb)
2940 {
2941 union cvmx_usbcx_hfnum usbc_hfnum;
2942 union cvmx_usbcx_gintsts usbc_gintsts;
2943
2944 CVMX_PREFETCH(usb, 0);
2945 CVMX_PREFETCH(usb, 1*128);
2946 CVMX_PREFETCH(usb, 2*128);
2947 CVMX_PREFETCH(usb, 3*128);
2948 CVMX_PREFETCH(usb, 4*128);
2949
2950 /* Update the frame counter */
2951 usbc_hfnum.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index));
2952 if ((usb->frame_number&0x3fff) > usbc_hfnum.s.frnum)
2953 usb->frame_number += 0x4000;
2954 usb->frame_number &= ~0x3fffull;
2955 usb->frame_number |= usbc_hfnum.s.frnum;
2956
2957 /* Read the pending interrupts */
2958 usbc_gintsts.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GINTSTS(usb->index));
2959
2960 /* Clear the interrupts now that we know about them */
2961 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTSTS(usb->index), usbc_gintsts.u32);
2962
2963 if (usbc_gintsts.s.rxflvl) {
2964 /*
2965 * RxFIFO Non-Empty (RxFLvl)
2966 * Indicates that there is at least one packet pending to be
2967 * read from the RxFIFO.
2968 *
2969 * In DMA mode this is handled by hardware
2970 */
2971 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
2972 __cvmx_usb_poll_rx_fifo(usb);
2973 }
2974 if (usbc_gintsts.s.ptxfemp || usbc_gintsts.s.nptxfemp) {
2975 /* Fill the Tx FIFOs when not in DMA mode */
2976 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
2977 __cvmx_usb_poll_tx_fifo(usb);
2978 }
2979 if (usbc_gintsts.s.disconnint || usbc_gintsts.s.prtint) {
2980 union cvmx_usbcx_hprt usbc_hprt;
2981 /*
2982 * Disconnect Detected Interrupt (DisconnInt)
2983 * Asserted when a device disconnect is detected.
2984 *
2985 * Host Port Interrupt (PrtInt)
2986 * The core sets this bit to indicate a change in port status of
2987 * one of the O2P USB core ports in Host mode. The application
2988 * must read the Host Port Control and Status (HPRT) register to
2989 * determine the exact event that caused this interrupt. The
2990 * application must clear the appropriate status bit in the Host
2991 * Port Control and Status register to clear this bit.
2992 *
2993 * Call the user's port callback
2994 */
2995 octeon_usb_port_callback(usb);
2996 /* Clear the port change bits */
2997 usbc_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
2998 usbc_hprt.s.prtena = 0;
2999 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HPRT(usb->index), usbc_hprt.u32);
3000 }
3001 if (usbc_gintsts.s.hchint) {
3002 /*
3003 * Host Channels Interrupt (HChInt)
3004 * The core sets this bit to indicate that an interrupt is
3005 * pending on one of the channels of the core (in Host mode).
3006 * The application must read the Host All Channels Interrupt
3007 * (HAINT) register to determine the exact number of the channel
3008 * on which the interrupt occurred, and then read the
3009 * corresponding Host Channel-n Interrupt (HCINTn) register to
3010 * determine the exact cause of the interrupt. The application
3011 * must clear the appropriate status bit in the HCINTn register
3012 * to clear this bit.
3013 */
3014 union cvmx_usbcx_haint usbc_haint;
3015 usbc_haint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HAINT(usb->index));
3016 while (usbc_haint.u32) {
3017 int channel;
3018
3019 channel = __fls(usbc_haint.u32);
3020 __cvmx_usb_poll_channel(usb, channel);
3021 usbc_haint.u32 ^= 1<<channel;
3022 }
3023 }
3024
3025 __cvmx_usb_schedule(usb, usbc_gintsts.s.sof);
3026
3027 return 0;
3028 }
3029
3030 /* convert between an HCD pointer and the corresponding struct octeon_hcd */
3031 static inline struct octeon_hcd *hcd_to_octeon(struct usb_hcd *hcd)
3032 {
3033 return (struct octeon_hcd *)(hcd->hcd_priv);
3034 }
3035
3036 static irqreturn_t octeon_usb_irq(struct usb_hcd *hcd)
3037 {
3038 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3039 unsigned long flags;
3040
3041 spin_lock_irqsave(&priv->lock, flags);
3042 cvmx_usb_poll(&priv->usb);
3043 spin_unlock_irqrestore(&priv->lock, flags);
3044 return IRQ_HANDLED;
3045 }
3046
3047 static int octeon_usb_start(struct usb_hcd *hcd)
3048 {
3049 hcd->state = HC_STATE_RUNNING;
3050 return 0;
3051 }
3052
3053 static void octeon_usb_stop(struct usb_hcd *hcd)
3054 {
3055 hcd->state = HC_STATE_HALT;
3056 }
3057
3058 static int octeon_usb_get_frame_number(struct usb_hcd *hcd)
3059 {
3060 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3061
3062 return cvmx_usb_get_frame_number(&priv->usb);
3063 }
3064
3065 static int octeon_usb_urb_enqueue(struct usb_hcd *hcd,
3066 struct urb *urb,
3067 gfp_t mem_flags)
3068 {
3069 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3070 struct device *dev = hcd->self.controller;
3071 struct cvmx_usb_transaction *transaction = NULL;
3072 struct cvmx_usb_pipe *pipe;
3073 unsigned long flags;
3074 struct cvmx_usb_iso_packet *iso_packet;
3075 struct usb_host_endpoint *ep = urb->ep;
3076
3077 urb->status = 0;
3078 INIT_LIST_HEAD(&urb->urb_list); /* not enqueued on dequeue_list */
3079 spin_lock_irqsave(&priv->lock, flags);
3080
3081 if (!ep->hcpriv) {
3082 enum cvmx_usb_transfer transfer_type;
3083 enum cvmx_usb_speed speed;
3084 int split_device = 0;
3085 int split_port = 0;
3086 switch (usb_pipetype(urb->pipe)) {
3087 case PIPE_ISOCHRONOUS:
3088 transfer_type = CVMX_USB_TRANSFER_ISOCHRONOUS;
3089 break;
3090 case PIPE_INTERRUPT:
3091 transfer_type = CVMX_USB_TRANSFER_INTERRUPT;
3092 break;
3093 case PIPE_CONTROL:
3094 transfer_type = CVMX_USB_TRANSFER_CONTROL;
3095 break;
3096 default:
3097 transfer_type = CVMX_USB_TRANSFER_BULK;
3098 break;
3099 }
3100 switch (urb->dev->speed) {
3101 case USB_SPEED_LOW:
3102 speed = CVMX_USB_SPEED_LOW;
3103 break;
3104 case USB_SPEED_FULL:
3105 speed = CVMX_USB_SPEED_FULL;
3106 break;
3107 default:
3108 speed = CVMX_USB_SPEED_HIGH;
3109 break;
3110 }
3111 /*
3112 * For slow devices on high speed ports we need to find the hub
3113 * that does the speed translation so we know where to send the
3114 * split transactions.
3115 */
3116 if (speed != CVMX_USB_SPEED_HIGH) {
3117 /*
3118 * Start at this device and work our way up the usb
3119 * tree.
3120 */
3121 struct usb_device *dev = urb->dev;
3122 while (dev->parent) {
3123 /*
3124 * If our parent is high speed then he'll
3125 * receive the splits.
3126 */
3127 if (dev->parent->speed == USB_SPEED_HIGH) {
3128 split_device = dev->parent->devnum;
3129 split_port = dev->portnum;
3130 break;
3131 }
3132 /*
3133 * Move up the tree one level. If we make it all
3134 * the way up the tree, then the port must not
3135 * be in high speed mode and we don't need a
3136 * split.
3137 */
3138 dev = dev->parent;
3139 }
3140 }
3141 pipe = cvmx_usb_open_pipe(&priv->usb, usb_pipedevice(urb->pipe),
3142 usb_pipeendpoint(urb->pipe), speed,
3143 le16_to_cpu(ep->desc.wMaxPacketSize) & 0x7ff,
3144 transfer_type,
3145 usb_pipein(urb->pipe) ?
3146 CVMX_USB_DIRECTION_IN :
3147 CVMX_USB_DIRECTION_OUT,
3148 urb->interval,
3149 (le16_to_cpu(ep->desc.wMaxPacketSize) >> 11) & 0x3,
3150 split_device, split_port);
3151 if (!pipe) {
3152 spin_unlock_irqrestore(&priv->lock, flags);
3153 dev_dbg(dev, "Failed to create pipe\n");
3154 return -ENOMEM;
3155 }
3156 ep->hcpriv = pipe;
3157 } else {
3158 pipe = ep->hcpriv;
3159 }
3160
3161 switch (usb_pipetype(urb->pipe)) {
3162 case PIPE_ISOCHRONOUS:
3163 dev_dbg(dev, "Submit isochronous to %d.%d\n",
3164 usb_pipedevice(urb->pipe), usb_pipeendpoint(urb->pipe));
3165 /*
3166 * Allocate a structure to use for our private list of
3167 * isochronous packets.
3168 */
3169 iso_packet = kmalloc(urb->number_of_packets *
3170 sizeof(struct cvmx_usb_iso_packet),
3171 GFP_ATOMIC);
3172 if (iso_packet) {
3173 int i;
3174 /* Fill the list with the data from the URB */
3175 for (i = 0; i < urb->number_of_packets; i++) {
3176 iso_packet[i].offset = urb->iso_frame_desc[i].offset;
3177 iso_packet[i].length = urb->iso_frame_desc[i].length;
3178 iso_packet[i].status = CVMX_USB_COMPLETE_ERROR;
3179 }
3180 /*
3181 * Store a pointer to the list in the URB setup_packet
3182 * field. We know this currently isn't being used and
3183 * this saves us a bunch of logic.
3184 */
3185 urb->setup_packet = (char *)iso_packet;
3186 transaction = cvmx_usb_submit_isochronous(&priv->usb,
3187 pipe, urb);
3188 /*
3189 * If submit failed we need to free our private packet
3190 * list.
3191 */
3192 if (!transaction) {
3193 urb->setup_packet = NULL;
3194 kfree(iso_packet);
3195 }
3196 }
3197 break;
3198 case PIPE_INTERRUPT:
3199 dev_dbg(dev, "Submit interrupt to %d.%d\n",
3200 usb_pipedevice(urb->pipe), usb_pipeendpoint(urb->pipe));
3201 transaction = cvmx_usb_submit_interrupt(&priv->usb, pipe, urb);
3202 break;
3203 case PIPE_CONTROL:
3204 dev_dbg(dev, "Submit control to %d.%d\n",
3205 usb_pipedevice(urb->pipe), usb_pipeendpoint(urb->pipe));
3206 transaction = cvmx_usb_submit_control(&priv->usb, pipe, urb);
3207 break;
3208 case PIPE_BULK:
3209 dev_dbg(dev, "Submit bulk to %d.%d\n",
3210 usb_pipedevice(urb->pipe), usb_pipeendpoint(urb->pipe));
3211 transaction = cvmx_usb_submit_bulk(&priv->usb, pipe, urb);
3212 break;
3213 }
3214 if (!transaction) {
3215 spin_unlock_irqrestore(&priv->lock, flags);
3216 dev_dbg(dev, "Failed to submit\n");
3217 return -ENOMEM;
3218 }
3219 urb->hcpriv = transaction;
3220 spin_unlock_irqrestore(&priv->lock, flags);
3221 return 0;
3222 }
3223
3224 static void octeon_usb_urb_dequeue_work(unsigned long arg)
3225 {
3226 struct urb *urb;
3227 struct urb *next;
3228 unsigned long flags;
3229 struct octeon_hcd *priv = (struct octeon_hcd *)arg;
3230
3231 spin_lock_irqsave(&priv->lock, flags);
3232
3233 list_for_each_entry_safe(urb, next, &priv->dequeue_list, urb_list) {
3234 list_del_init(&urb->urb_list);
3235 cvmx_usb_cancel(&priv->usb, urb->ep->hcpriv, urb->hcpriv);
3236 }
3237
3238 spin_unlock_irqrestore(&priv->lock, flags);
3239 }
3240
3241 static int octeon_usb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
3242 {
3243 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3244 unsigned long flags;
3245
3246 if (!urb->dev)
3247 return -EINVAL;
3248
3249 spin_lock_irqsave(&priv->lock, flags);
3250
3251 urb->status = status;
3252 list_add_tail(&urb->urb_list, &priv->dequeue_list);
3253
3254 spin_unlock_irqrestore(&priv->lock, flags);
3255
3256 tasklet_schedule(&priv->dequeue_tasklet);
3257
3258 return 0;
3259 }
3260
3261 static void octeon_usb_endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
3262 {
3263 struct device *dev = hcd->self.controller;
3264
3265 if (ep->hcpriv) {
3266 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3267 struct cvmx_usb_pipe *pipe = ep->hcpriv;
3268 unsigned long flags;
3269 spin_lock_irqsave(&priv->lock, flags);
3270 cvmx_usb_cancel_all(&priv->usb, pipe);
3271 if (cvmx_usb_close_pipe(&priv->usb, pipe))
3272 dev_dbg(dev, "Closing pipe %p failed\n", pipe);
3273 spin_unlock_irqrestore(&priv->lock, flags);
3274 ep->hcpriv = NULL;
3275 }
3276 }
3277
3278 static int octeon_usb_hub_status_data(struct usb_hcd *hcd, char *buf)
3279 {
3280 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3281 struct cvmx_usb_port_status port_status;
3282 unsigned long flags;
3283
3284 spin_lock_irqsave(&priv->lock, flags);
3285 port_status = cvmx_usb_get_status(&priv->usb);
3286 spin_unlock_irqrestore(&priv->lock, flags);
3287 buf[0] = 0;
3288 buf[0] = port_status.connect_change << 1;
3289
3290 return (buf[0] != 0);
3291 }
3292
3293 static int octeon_usb_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength)
3294 {
3295 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3296 struct device *dev = hcd->self.controller;
3297 struct cvmx_usb_port_status usb_port_status;
3298 int port_status;
3299 struct usb_hub_descriptor *desc;
3300 unsigned long flags;
3301
3302 switch (typeReq) {
3303 case ClearHubFeature:
3304 dev_dbg(dev, "ClearHubFeature\n");
3305 switch (wValue) {
3306 case C_HUB_LOCAL_POWER:
3307 case C_HUB_OVER_CURRENT:
3308 /* Nothing required here */
3309 break;
3310 default:
3311 return -EINVAL;
3312 }
3313 break;
3314 case ClearPortFeature:
3315 dev_dbg(dev, "ClearPortFeature\n");
3316 if (wIndex != 1) {
3317 dev_dbg(dev, " INVALID\n");
3318 return -EINVAL;
3319 }
3320
3321 switch (wValue) {
3322 case USB_PORT_FEAT_ENABLE:
3323 dev_dbg(dev, " ENABLE\n");
3324 spin_lock_irqsave(&priv->lock, flags);
3325 cvmx_usb_disable(&priv->usb);
3326 spin_unlock_irqrestore(&priv->lock, flags);
3327 break;
3328 case USB_PORT_FEAT_SUSPEND:
3329 dev_dbg(dev, " SUSPEND\n");
3330 /* Not supported on Octeon */
3331 break;
3332 case USB_PORT_FEAT_POWER:
3333 dev_dbg(dev, " POWER\n");
3334 /* Not supported on Octeon */
3335 break;
3336 case USB_PORT_FEAT_INDICATOR:
3337 dev_dbg(dev, " INDICATOR\n");
3338 /* Port inidicator not supported */
3339 break;
3340 case USB_PORT_FEAT_C_CONNECTION:
3341 dev_dbg(dev, " C_CONNECTION\n");
3342 /* Clears drivers internal connect status change flag */
3343 spin_lock_irqsave(&priv->lock, flags);
3344 priv->usb.port_status = cvmx_usb_get_status(&priv->usb);
3345 spin_unlock_irqrestore(&priv->lock, flags);
3346 break;
3347 case USB_PORT_FEAT_C_RESET:
3348 dev_dbg(dev, " C_RESET\n");
3349 /*
3350 * Clears the driver's internal Port Reset Change flag.
3351 */
3352 spin_lock_irqsave(&priv->lock, flags);
3353 priv->usb.port_status = cvmx_usb_get_status(&priv->usb);
3354 spin_unlock_irqrestore(&priv->lock, flags);
3355 break;
3356 case USB_PORT_FEAT_C_ENABLE:
3357 dev_dbg(dev, " C_ENABLE\n");
3358 /*
3359 * Clears the driver's internal Port Enable/Disable
3360 * Change flag.
3361 */
3362 spin_lock_irqsave(&priv->lock, flags);
3363 priv->usb.port_status = cvmx_usb_get_status(&priv->usb);
3364 spin_unlock_irqrestore(&priv->lock, flags);
3365 break;
3366 case USB_PORT_FEAT_C_SUSPEND:
3367 dev_dbg(dev, " C_SUSPEND\n");
3368 /*
3369 * Clears the driver's internal Port Suspend Change
3370 * flag, which is set when resume signaling on the host
3371 * port is complete.
3372 */
3373 break;
3374 case USB_PORT_FEAT_C_OVER_CURRENT:
3375 dev_dbg(dev, " C_OVER_CURRENT\n");
3376 /* Clears the driver's overcurrent Change flag */
3377 spin_lock_irqsave(&priv->lock, flags);
3378 priv->usb.port_status = cvmx_usb_get_status(&priv->usb);
3379 spin_unlock_irqrestore(&priv->lock, flags);
3380 break;
3381 default:
3382 dev_dbg(dev, " UNKNOWN\n");
3383 return -EINVAL;
3384 }
3385 break;
3386 case GetHubDescriptor:
3387 dev_dbg(dev, "GetHubDescriptor\n");
3388 desc = (struct usb_hub_descriptor *)buf;
3389 desc->bDescLength = 9;
3390 desc->bDescriptorType = 0x29;
3391 desc->bNbrPorts = 1;
3392 desc->wHubCharacteristics = 0x08;
3393 desc->bPwrOn2PwrGood = 1;
3394 desc->bHubContrCurrent = 0;
3395 desc->u.hs.DeviceRemovable[0] = 0;
3396 desc->u.hs.DeviceRemovable[1] = 0xff;
3397 break;
3398 case GetHubStatus:
3399 dev_dbg(dev, "GetHubStatus\n");
3400 *(__le32 *) buf = 0;
3401 break;
3402 case GetPortStatus:
3403 dev_dbg(dev, "GetPortStatus\n");
3404 if (wIndex != 1) {
3405 dev_dbg(dev, " INVALID\n");
3406 return -EINVAL;
3407 }
3408
3409 spin_lock_irqsave(&priv->lock, flags);
3410 usb_port_status = cvmx_usb_get_status(&priv->usb);
3411 spin_unlock_irqrestore(&priv->lock, flags);
3412 port_status = 0;
3413
3414 if (usb_port_status.connect_change) {
3415 port_status |= (1 << USB_PORT_FEAT_C_CONNECTION);
3416 dev_dbg(dev, " C_CONNECTION\n");
3417 }
3418
3419 if (usb_port_status.port_enabled) {
3420 port_status |= (1 << USB_PORT_FEAT_C_ENABLE);
3421 dev_dbg(dev, " C_ENABLE\n");
3422 }
3423
3424 if (usb_port_status.connected) {
3425 port_status |= (1 << USB_PORT_FEAT_CONNECTION);
3426 dev_dbg(dev, " CONNECTION\n");
3427 }
3428
3429 if (usb_port_status.port_enabled) {
3430 port_status |= (1 << USB_PORT_FEAT_ENABLE);
3431 dev_dbg(dev, " ENABLE\n");
3432 }
3433
3434 if (usb_port_status.port_over_current) {
3435 port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT);
3436 dev_dbg(dev, " OVER_CURRENT\n");
3437 }
3438
3439 if (usb_port_status.port_powered) {
3440 port_status |= (1 << USB_PORT_FEAT_POWER);
3441 dev_dbg(dev, " POWER\n");
3442 }
3443
3444 if (usb_port_status.port_speed == CVMX_USB_SPEED_HIGH) {
3445 port_status |= USB_PORT_STAT_HIGH_SPEED;
3446 dev_dbg(dev, " HIGHSPEED\n");
3447 } else if (usb_port_status.port_speed == CVMX_USB_SPEED_LOW) {
3448 port_status |= (1 << USB_PORT_FEAT_LOWSPEED);
3449 dev_dbg(dev, " LOWSPEED\n");
3450 }
3451
3452 *((__le32 *) buf) = cpu_to_le32(port_status);
3453 break;
3454 case SetHubFeature:
3455 dev_dbg(dev, "SetHubFeature\n");
3456 /* No HUB features supported */
3457 break;
3458 case SetPortFeature:
3459 dev_dbg(dev, "SetPortFeature\n");
3460 if (wIndex != 1) {
3461 dev_dbg(dev, " INVALID\n");
3462 return -EINVAL;
3463 }
3464
3465 switch (wValue) {
3466 case USB_PORT_FEAT_SUSPEND:
3467 dev_dbg(dev, " SUSPEND\n");
3468 return -EINVAL;
3469 case USB_PORT_FEAT_POWER:
3470 dev_dbg(dev, " POWER\n");
3471 return -EINVAL;
3472 case USB_PORT_FEAT_RESET:
3473 dev_dbg(dev, " RESET\n");
3474 spin_lock_irqsave(&priv->lock, flags);
3475 cvmx_usb_disable(&priv->usb);
3476 if (cvmx_usb_enable(&priv->usb))
3477 dev_dbg(dev, "Failed to enable the port\n");
3478 spin_unlock_irqrestore(&priv->lock, flags);
3479 return 0;
3480 case USB_PORT_FEAT_INDICATOR:
3481 dev_dbg(dev, " INDICATOR\n");
3482 /* Not supported */
3483 break;
3484 default:
3485 dev_dbg(dev, " UNKNOWN\n");
3486 return -EINVAL;
3487 }
3488 break;
3489 default:
3490 dev_dbg(dev, "Unknown root hub request\n");
3491 return -EINVAL;
3492 }
3493 return 0;
3494 }
3495
3496
3497 static const struct hc_driver octeon_hc_driver = {
3498 .description = "Octeon USB",
3499 .product_desc = "Octeon Host Controller",
3500 .hcd_priv_size = sizeof(struct octeon_hcd),
3501 .irq = octeon_usb_irq,
3502 .flags = HCD_MEMORY | HCD_USB2,
3503 .start = octeon_usb_start,
3504 .stop = octeon_usb_stop,
3505 .urb_enqueue = octeon_usb_urb_enqueue,
3506 .urb_dequeue = octeon_usb_urb_dequeue,
3507 .endpoint_disable = octeon_usb_endpoint_disable,
3508 .get_frame_number = octeon_usb_get_frame_number,
3509 .hub_status_data = octeon_usb_hub_status_data,
3510 .hub_control = octeon_usb_hub_control,
3511 };
3512
3513
3514 static int octeon_usb_driver_probe(struct device *dev)
3515 {
3516 int status;
3517 int usb_num = to_platform_device(dev)->id;
3518 int irq = platform_get_irq(to_platform_device(dev), 0);
3519 struct octeon_hcd *priv;
3520 struct usb_hcd *hcd;
3521 unsigned long flags;
3522
3523 /*
3524 * Set the DMA mask to 64bits so we get buffers already translated for
3525 * DMA.
3526 */
3527 dev->coherent_dma_mask = ~0;
3528 dev->dma_mask = &dev->coherent_dma_mask;
3529
3530 hcd = usb_create_hcd(&octeon_hc_driver, dev, dev_name(dev));
3531 if (!hcd) {
3532 dev_dbg(dev, "Failed to allocate memory for HCD\n");
3533 return -1;
3534 }
3535 hcd->uses_new_polling = 1;
3536 priv = (struct octeon_hcd *)hcd->hcd_priv;
3537
3538 spin_lock_init(&priv->lock);
3539
3540 tasklet_init(&priv->dequeue_tasklet, octeon_usb_urb_dequeue_work, (unsigned long)priv);
3541 INIT_LIST_HEAD(&priv->dequeue_list);
3542
3543 status = cvmx_usb_initialize(&priv->usb, usb_num);
3544 if (status) {
3545 dev_dbg(dev, "USB initialization failed with %d\n", status);
3546 kfree(hcd);
3547 return -1;
3548 }
3549
3550 /* This delay is needed for CN3010, but I don't know why... */
3551 mdelay(10);
3552
3553 spin_lock_irqsave(&priv->lock, flags);
3554 cvmx_usb_poll(&priv->usb);
3555 spin_unlock_irqrestore(&priv->lock, flags);
3556
3557 status = usb_add_hcd(hcd, irq, IRQF_SHARED);
3558 if (status) {
3559 dev_dbg(dev, "USB add HCD failed with %d\n", status);
3560 kfree(hcd);
3561 return -1;
3562 }
3563
3564 dev_dbg(dev, "Registered HCD for port %d on irq %d\n", usb_num, irq);
3565
3566 return 0;
3567 }
3568
3569 static int octeon_usb_driver_remove(struct device *dev)
3570 {
3571 int status;
3572 struct usb_hcd *hcd = dev_get_drvdata(dev);
3573 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3574 unsigned long flags;
3575
3576 usb_remove_hcd(hcd);
3577 tasklet_kill(&priv->dequeue_tasklet);
3578 spin_lock_irqsave(&priv->lock, flags);
3579 status = cvmx_usb_shutdown(&priv->usb);
3580 spin_unlock_irqrestore(&priv->lock, flags);
3581 if (status)
3582 dev_dbg(dev, "USB shutdown failed with %d\n", status);
3583
3584 kfree(hcd);
3585
3586 return 0;
3587 }
3588
3589 static struct device_driver octeon_usb_driver = {
3590 .name = "OcteonUSB",
3591 .bus = &platform_bus_type,
3592 .probe = octeon_usb_driver_probe,
3593 .remove = octeon_usb_driver_remove,
3594 };
3595
3596
3597 #define MAX_USB_PORTS 10
3598 static struct platform_device *pdev_glob[MAX_USB_PORTS];
3599 static int octeon_usb_registered;
3600 static int __init octeon_usb_module_init(void)
3601 {
3602 int num_devices = cvmx_usb_get_num_ports();
3603 int device;
3604
3605 if (usb_disabled() || num_devices == 0)
3606 return -ENODEV;
3607
3608 if (driver_register(&octeon_usb_driver))
3609 return -ENOMEM;
3610
3611 octeon_usb_registered = 1;
3612
3613 /*
3614 * Only cn52XX and cn56XX have DWC_OTG USB hardware and the
3615 * IOB priority registers. Under heavy network load USB
3616 * hardware can be starved by the IOB causing a crash. Give
3617 * it a priority boost if it has been waiting more than 400
3618 * cycles to avoid this situation.
3619 *
3620 * Testing indicates that a cnt_val of 8192 is not sufficient,
3621 * but no failures are seen with 4096. We choose a value of
3622 * 400 to give a safety factor of 10.
3623 */
3624 if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) {
3625 union cvmx_iob_n2c_l2c_pri_cnt pri_cnt;
3626
3627 pri_cnt.u64 = 0;
3628 pri_cnt.s.cnt_enb = 1;
3629 pri_cnt.s.cnt_val = 400;
3630 cvmx_write_csr(CVMX_IOB_N2C_L2C_PRI_CNT, pri_cnt.u64);
3631 }
3632
3633 for (device = 0; device < num_devices; device++) {
3634 struct resource irq_resource;
3635 struct platform_device *pdev;
3636 memset(&irq_resource, 0, sizeof(irq_resource));
3637 irq_resource.start = (device == 0) ? OCTEON_IRQ_USB0 : OCTEON_IRQ_USB1;
3638 irq_resource.end = irq_resource.start;
3639 irq_resource.flags = IORESOURCE_IRQ;
3640 pdev = platform_device_register_simple((char *)octeon_usb_driver. name, device, &irq_resource, 1);
3641 if (IS_ERR(pdev)) {
3642 driver_unregister(&octeon_usb_driver);
3643 octeon_usb_registered = 0;
3644 return PTR_ERR(pdev);
3645 }
3646 if (device < MAX_USB_PORTS)
3647 pdev_glob[device] = pdev;
3648
3649 }
3650 return 0;
3651 }
3652
3653 static void __exit octeon_usb_module_cleanup(void)
3654 {
3655 int i;
3656
3657 for (i = 0; i < MAX_USB_PORTS; i++)
3658 if (pdev_glob[i]) {
3659 platform_device_unregister(pdev_glob[i]);
3660 pdev_glob[i] = NULL;
3661 }
3662 if (octeon_usb_registered)
3663 driver_unregister(&octeon_usb_driver);
3664 }
3665
3666 MODULE_LICENSE("GPL");
3667 MODULE_AUTHOR("Cavium Networks <support@caviumnetworks.com>");
3668 MODULE_DESCRIPTION("Cavium Networks Octeon USB Host driver.");
3669 module_init(octeon_usb_module_init);
3670 module_exit(octeon_usb_module_cleanup);
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