2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2008 Cavium Networks
8 * Some parts of the code were originally released under BSD license:
10 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions are
17 * * Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
20 * * Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials provided
23 * with the distribution.
25 * * Neither the name of Cavium Networks nor the names of
26 * its contributors may be used to endorse or promote products
27 * derived from this software without specific prior written
30 * This Software, including technical data, may be subject to U.S. export
31 * control laws, including the U.S. Export Administration Act and its associated
32 * regulations, and may be subject to export or import regulations in other
35 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
36 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
37 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
38 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION
39 * OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
40 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
41 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
42 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
43 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
44 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
46 #include <linux/kernel.h>
47 #include <linux/module.h>
48 #include <linux/init.h>
49 #include <linux/pci.h>
50 #include <linux/interrupt.h>
51 #include <linux/platform_device.h>
52 #include <linux/usb.h>
54 #include <linux/time.h>
55 #include <linux/delay.h>
57 #include <asm/octeon/cvmx.h>
58 #include <asm/octeon/cvmx-iob-defs.h>
60 #include <linux/usb/hcd.h>
62 #include <linux/err.h>
64 #include <asm/octeon/octeon.h>
65 #include <asm/octeon/cvmx-helper.h>
66 #include <asm/octeon/cvmx-sysinfo.h>
67 #include <asm/octeon/cvmx-helper-board.h>
69 #include "octeon-hcd.h"
72 * enum cvmx_usb_speed - the possible USB device speeds
74 * @CVMX_USB_SPEED_HIGH: Device is operation at 480Mbps
75 * @CVMX_USB_SPEED_FULL: Device is operation at 12Mbps
76 * @CVMX_USB_SPEED_LOW: Device is operation at 1.5Mbps
79 CVMX_USB_SPEED_HIGH
= 0,
80 CVMX_USB_SPEED_FULL
= 1,
81 CVMX_USB_SPEED_LOW
= 2,
85 * enum cvmx_usb_transfer - the possible USB transfer types
87 * @CVMX_USB_TRANSFER_CONTROL: USB transfer type control for hub and status
89 * @CVMX_USB_TRANSFER_ISOCHRONOUS: USB transfer type isochronous for low
90 * priority periodic transfers
91 * @CVMX_USB_TRANSFER_BULK: USB transfer type bulk for large low priority
93 * @CVMX_USB_TRANSFER_INTERRUPT: USB transfer type interrupt for high priority
96 enum cvmx_usb_transfer
{
97 CVMX_USB_TRANSFER_CONTROL
= 0,
98 CVMX_USB_TRANSFER_ISOCHRONOUS
= 1,
99 CVMX_USB_TRANSFER_BULK
= 2,
100 CVMX_USB_TRANSFER_INTERRUPT
= 3,
104 * enum cvmx_usb_direction - the transfer directions
106 * @CVMX_USB_DIRECTION_OUT: Data is transferring from Octeon to the device/host
107 * @CVMX_USB_DIRECTION_IN: Data is transferring from the device/host to Octeon
109 enum cvmx_usb_direction
{
110 CVMX_USB_DIRECTION_OUT
,
111 CVMX_USB_DIRECTION_IN
,
115 * enum cvmx_usb_complete - possible callback function status codes
117 * @CVMX_USB_COMPLETE_SUCCESS: The transaction / operation finished without
119 * @CVMX_USB_COMPLETE_SHORT: FIXME: This is currently not implemented
120 * @CVMX_USB_COMPLETE_CANCEL: The transaction was canceled while in flight
121 * by a user call to cvmx_usb_cancel
122 * @CVMX_USB_COMPLETE_ERROR: The transaction aborted with an unexpected
124 * @CVMX_USB_COMPLETE_STALL: The transaction received a USB STALL response
126 * @CVMX_USB_COMPLETE_XACTERR: The transaction failed with an error from the
127 * device even after a number of retries
128 * @CVMX_USB_COMPLETE_DATATGLERR: The transaction failed with a data toggle
129 * error even after a number of retries
130 * @CVMX_USB_COMPLETE_BABBLEERR: The transaction failed with a babble error
131 * @CVMX_USB_COMPLETE_FRAMEERR: The transaction failed with a frame error
132 * even after a number of retries
134 enum cvmx_usb_complete
{
135 CVMX_USB_COMPLETE_SUCCESS
,
136 CVMX_USB_COMPLETE_SHORT
,
137 CVMX_USB_COMPLETE_CANCEL
,
138 CVMX_USB_COMPLETE_ERROR
,
139 CVMX_USB_COMPLETE_STALL
,
140 CVMX_USB_COMPLETE_XACTERR
,
141 CVMX_USB_COMPLETE_DATATGLERR
,
142 CVMX_USB_COMPLETE_BABBLEERR
,
143 CVMX_USB_COMPLETE_FRAMEERR
,
147 * struct cvmx_usb_port_status - the USB port status information
149 * @port_enabled: 1 = Usb port is enabled, 0 = disabled
150 * @port_over_current: 1 = Over current detected, 0 = Over current not
151 * detected. Octeon doesn't support over current detection.
152 * @port_powered: 1 = Port power is being supplied to the device, 0 =
153 * power is off. Octeon doesn't support turning port power
155 * @port_speed: Current port speed.
156 * @connected: 1 = A device is connected to the port, 0 = No device is
158 * @connect_change: 1 = Device connected state changed since the last set
161 struct cvmx_usb_port_status
{
162 uint32_t reserved
: 25;
163 uint32_t port_enabled
: 1;
164 uint32_t port_over_current
: 1;
165 uint32_t port_powered
: 1;
166 enum cvmx_usb_speed port_speed
: 2;
167 uint32_t connected
: 1;
168 uint32_t connect_change
: 1;
172 * union cvmx_usb_control_header - the structure of a Control packet header
174 * @s.request_type: Bit 7 tells the direction: 1=IN, 0=OUT
175 * @s.request The standard usb request to make
176 * @s.value Value parameter for the request in little endian format
177 * @s.index Index for the request in little endian format
178 * @s.length Length of the data associated with this request in
179 * little endian format
181 union cvmx_usb_control_header
{
184 uint64_t request_type
: 8;
185 uint64_t request
: 8;
188 uint64_t length
: 16;
193 * struct cvmx_usb_iso_packet - descriptor for Isochronous packets
195 * @offset: This is the offset in bytes into the main buffer where this data
197 * @length: This is the length in bytes of the data.
198 * @status: This is the status of this individual packet transfer.
200 struct cvmx_usb_iso_packet
{
203 enum cvmx_usb_complete status
;
207 * enum cvmx_usb_initialize_flags - flags used by the initialization function
209 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI: The USB port uses a 12MHz crystal
210 * as clock source at USB_XO and
212 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND: The USB port uses 12/24/48MHz 2.5V
213 * board clock source at USB_XO.
214 * USB_XI should be tied to GND.
215 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK: Mask for clock speed field
216 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ: Speed of reference clock or
218 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ: Speed of reference clock
219 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ: Speed of reference clock
220 * @CVMX_USB_INITIALIZE_FLAGS_NO_DMA: Disable DMA and used polled IO for
221 * data transfer use for the USB
223 enum cvmx_usb_initialize_flags
{
224 CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI
= 1 << 0,
225 CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND
= 1 << 1,
226 CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK
= 3 << 3,
227 CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ
= 1 << 3,
228 CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ
= 2 << 3,
229 CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ
= 3 << 3,
230 /* Bits 3-4 used to encode the clock frequency */
231 CVMX_USB_INITIALIZE_FLAGS_NO_DMA
= 1 << 5,
235 * enum cvmx_usb_pipe_flags - internal flags for a pipe.
237 * @__CVMX_USB_PIPE_FLAGS_OPEN: Used internally to determine if a pipe is
239 * @__CVMX_USB_PIPE_FLAGS_SCHEDULED: Used internally to determine if a pipe is
240 * actively using hardware. Do not use.
241 * @__CVMX_USB_PIPE_FLAGS_NEED_PING: Used internally to determine if a high
242 * speed pipe is in the ping state. Do not
245 enum cvmx_usb_pipe_flags
{
246 __CVMX_USB_PIPE_FLAGS_OPEN
= 1 << 16,
247 __CVMX_USB_PIPE_FLAGS_SCHEDULED
= 1 << 17,
248 __CVMX_USB_PIPE_FLAGS_NEED_PING
= 1 << 18,
251 /* Normal prefetch that use the pref instruction. */
252 #define CVMX_PREFETCH(address, offset) asm volatile ("pref %[type], %[off](%[rbase])" : : [rbase] "d" (address), [off] "I" (offset), [type] "n" (0))
254 /* Maximum number of times to retry failed transactions */
255 #define MAX_RETRIES 3
257 /* Maximum number of pipes that can be open at once */
260 /* Maximum number of hardware channels supported by the USB block */
261 #define MAX_CHANNELS 8
263 /* The highest valid USB device address */
264 #define MAX_USB_ADDRESS 127
266 /* The highest valid USB endpoint number */
267 #define MAX_USB_ENDPOINT 15
269 /* The highest valid port number on a hub */
270 #define MAX_USB_HUB_PORT 15
273 * The low level hardware can transfer a maximum of this number of bytes in each
274 * transfer. The field is 19 bits wide
276 #define MAX_TRANSFER_BYTES ((1<<19)-1)
279 * The low level hardware can transfer a maximum of this number of packets in
280 * each transfer. The field is 10 bits wide
282 #define MAX_TRANSFER_PACKETS ((1<<10)-1)
285 USB_CLOCK_TYPE_REF_12
,
286 USB_CLOCK_TYPE_REF_24
,
287 USB_CLOCK_TYPE_REF_48
,
288 USB_CLOCK_TYPE_CRYSTAL_12
,
292 * Logical transactions may take numerous low level
293 * transactions, especially when splits are concerned. This
294 * enum represents all of the possible stages a transaction can
295 * be in. Note that split completes are always even. This is so
296 * the NAK handler can backup to the previous low level
297 * transaction with a simple clearing of bit 0.
299 enum cvmx_usb_stage
{
300 CVMX_USB_STAGE_NON_CONTROL
,
301 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
,
302 CVMX_USB_STAGE_SETUP
,
303 CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE
,
305 CVMX_USB_STAGE_DATA_SPLIT_COMPLETE
,
306 CVMX_USB_STAGE_STATUS
,
307 CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE
,
311 * struct cvmx_usb_transaction - describes each pending USB transaction
312 * regardless of type. These are linked together
313 * to form a list of pending requests for a pipe.
315 * @prev: Transaction before this one in the pipe.
316 * @next: Transaction after this one in the pipe.
317 * @type: Type of transaction, duplicated of the pipe.
318 * @flags: State flags for this transaction.
319 * @buffer: User's physical buffer address to read/write.
320 * @buffer_length: Size of the user's buffer in bytes.
321 * @control_header: For control transactions, physical address of the 8
322 * byte standard header.
323 * @iso_start_frame: For ISO transactions, the starting frame number.
324 * @iso_number_packets: For ISO transactions, the number of packets in the
326 * @iso_packets: For ISO transactions, the sub packets in the request.
327 * @actual_bytes: Actual bytes transfer for this transaction.
328 * @stage: For control transactions, the current stage.
331 struct cvmx_usb_transaction
{
332 struct cvmx_usb_transaction
*prev
;
333 struct cvmx_usb_transaction
*next
;
334 enum cvmx_usb_transfer type
;
337 uint64_t control_header
;
339 int iso_number_packets
;
340 struct cvmx_usb_iso_packet
*iso_packets
;
345 enum cvmx_usb_stage stage
;
350 * struct cvmx_usb_pipe - a pipe represents a virtual connection between Octeon
351 * and some USB device. It contains a list of pending
352 * request to the device.
354 * @prev: Pipe before this one in the list
355 * @next: Pipe after this one in the list
356 * @head: The first pending transaction
357 * @tail: The last pending transaction
358 * @interval: For periodic pipes, the interval between packets in
360 * @next_tx_frame: The next frame this pipe is allowed to transmit on
361 * @flags: State flags for this pipe
362 * @device_speed: Speed of device connected to this pipe
363 * @transfer_type: Type of transaction supported by this pipe
364 * @transfer_dir: IN or OUT. Ignored for Control
365 * @multi_count: Max packet in a row for the device
366 * @max_packet: The device's maximum packet size in bytes
367 * @device_addr: USB device address at other end of pipe
368 * @endpoint_num: USB endpoint number at other end of pipe
369 * @hub_device_addr: Hub address this device is connected to
370 * @hub_port: Hub port this device is connected to
371 * @pid_toggle: This toggles between 0/1 on every packet send to track
372 * the data pid needed
373 * @channel: Hardware DMA channel for this pipe
374 * @split_sc_frame: The low order bits of the frame number the split
375 * complete should be sent on
377 struct cvmx_usb_pipe
{
378 struct cvmx_usb_pipe
*prev
;
379 struct cvmx_usb_pipe
*next
;
380 struct cvmx_usb_transaction
*head
;
381 struct cvmx_usb_transaction
*tail
;
383 uint64_t next_tx_frame
;
384 enum cvmx_usb_pipe_flags flags
;
385 enum cvmx_usb_speed device_speed
;
386 enum cvmx_usb_transfer transfer_type
;
387 enum cvmx_usb_direction transfer_dir
;
391 uint8_t endpoint_num
;
392 uint8_t hub_device_addr
;
396 int8_t split_sc_frame
;
400 * struct cvmx_usb_pipe_list
402 * @head: Head of the list, or NULL if empty.
403 * @tail: Tail if the list, or NULL if empty.
405 struct cvmx_usb_pipe_list
{
406 struct cvmx_usb_pipe
*head
;
407 struct cvmx_usb_pipe
*tail
;
410 struct cvmx_usb_tx_fifo
{
415 } entry
[MAX_CHANNELS
+1];
421 * struct cvmx_usb_state - the state of the USB block
423 * init_flags: Flags passed to initialize.
424 * index: Which USB block this is for.
425 * idle_hardware_channels: Bit set for every idle hardware channel.
426 * usbcx_hprt: Stored port status so we don't need to read a CSR to
428 * pipe_for_channel: Map channels to pipes.
429 * pipe: Storage for pipes.
430 * indent: Used by debug output to indent functions.
431 * port_status: Last port status used for change notification.
432 * free_pipes: List of all pipes that are currently closed.
433 * idle_pipes: List of open pipes that have no transactions.
434 * active_pipes: Active pipes indexed by transfer type.
435 * frame_number: Increments every SOF interrupt for time keeping.
436 * active_split: Points to the current active split, or NULL.
438 struct cvmx_usb_state
{
441 int idle_hardware_channels
;
442 union cvmx_usbcx_hprt usbcx_hprt
;
443 struct cvmx_usb_pipe
*pipe_for_channel
[MAX_CHANNELS
];
444 struct cvmx_usb_pipe pipe
[MAX_PIPES
];
446 struct cvmx_usb_port_status port_status
;
447 struct cvmx_usb_pipe_list free_pipes
;
448 struct cvmx_usb_pipe_list idle_pipes
;
449 struct cvmx_usb_pipe_list active_pipes
[4];
450 uint64_t frame_number
;
451 struct cvmx_usb_transaction
*active_split
;
452 struct cvmx_usb_tx_fifo periodic
;
453 struct cvmx_usb_tx_fifo nonperiodic
;
458 struct cvmx_usb_state usb
;
459 struct tasklet_struct dequeue_tasklet
;
460 struct list_head dequeue_list
;
463 /* This macro spins on a field waiting for it to reach a value */
464 #define CVMX_WAIT_FOR_FIELD32(address, type, field, op, value, timeout_usec)\
467 uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec * \
468 octeon_get_clock_rate() / 1000000; \
471 c.u32 = __cvmx_usb_read_csr32(usb, address); \
472 if (c.s.field op (value)) { \
475 } else if (cvmx_get_cycle() > done) { \
485 * This macro logically sets a single field in a CSR. It does the sequence
486 * read, modify, and write
488 #define USB_SET_FIELD32(address, type, field, value) \
491 c.u32 = __cvmx_usb_read_csr32(usb, address); \
493 __cvmx_usb_write_csr32(usb, address, c.u32); \
496 /* Returns the IO address to push/pop stuff data from the FIFOs */
497 #define USB_FIFO_ADDRESS(channel, usb_index) (CVMX_USBCX_GOTGCTL(usb_index) + ((channel)+1)*0x1000)
499 static int octeon_usb_get_clock_type(void)
501 switch (cvmx_sysinfo_get()->board_type
) {
502 case CVMX_BOARD_TYPE_BBGW_REF
:
503 case CVMX_BOARD_TYPE_LANAI2_A
:
504 case CVMX_BOARD_TYPE_LANAI2_U
:
505 case CVMX_BOARD_TYPE_LANAI2_G
:
506 case CVMX_BOARD_TYPE_UBNT_E100
:
507 return USB_CLOCK_TYPE_CRYSTAL_12
;
509 return USB_CLOCK_TYPE_REF_48
;
513 * Read a USB 32bit CSR. It performs the necessary address swizzle
514 * for 32bit CSRs and logs the value in a readable format if
517 * @usb: USB block this access is for
518 * @address: 64bit address to read
520 * Returns: Result of the read
522 static inline uint32_t __cvmx_usb_read_csr32(struct cvmx_usb_state
*usb
,
525 uint32_t result
= cvmx_read64_uint32(address
^ 4);
531 * Write a USB 32bit CSR. It performs the necessary address
532 * swizzle for 32bit CSRs and logs the value in a readable format
533 * if debugging is on.
535 * @usb: USB block this access is for
536 * @address: 64bit address to write
537 * @value: Value to write
539 static inline void __cvmx_usb_write_csr32(struct cvmx_usb_state
*usb
,
540 uint64_t address
, uint32_t value
)
542 cvmx_write64_uint32(address
^ 4, value
);
543 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb
->index
));
548 * Read a USB 64bit CSR. It logs the value in a readable format if
551 * @usb: USB block this access is for
552 * @address: 64bit address to read
554 * Returns: Result of the read
556 static inline uint64_t __cvmx_usb_read_csr64(struct cvmx_usb_state
*usb
,
559 uint64_t result
= cvmx_read64_uint64(address
);
565 * Write a USB 64bit CSR. It logs the value in a readable format
566 * if debugging is on.
568 * @usb: USB block this access is for
569 * @address: 64bit address to write
570 * @value: Value to write
572 static inline void __cvmx_usb_write_csr64(struct cvmx_usb_state
*usb
,
573 uint64_t address
, uint64_t value
)
575 cvmx_write64_uint64(address
, value
);
579 * Return non zero if this pipe connects to a non HIGH speed
580 * device through a high speed hub.
582 * @usb: USB block this access is for
583 * @pipe: Pipe to check
585 * Returns: Non zero if we need to do split transactions
587 static inline int __cvmx_usb_pipe_needs_split(struct cvmx_usb_state
*usb
,
588 struct cvmx_usb_pipe
*pipe
)
590 return pipe
->device_speed
!= CVMX_USB_SPEED_HIGH
&&
591 usb
->usbcx_hprt
.s
.prtspd
== CVMX_USB_SPEED_HIGH
;
596 * Trivial utility function to return the correct PID for a pipe
598 * @pipe: pipe to check
600 * Returns: PID for pipe
602 static inline int __cvmx_usb_get_data_pid(struct cvmx_usb_pipe
*pipe
)
604 if (pipe
->pid_toggle
)
605 return 2; /* Data1 */
607 return 0; /* Data0 */
612 * Return the number of USB ports supported by this Octeon
613 * chip. If the chip doesn't support USB, or is not supported
614 * by this API, a zero will be returned. Most Octeon chips
615 * support one usb port, but some support two ports.
616 * cvmx_usb_initialize() must be called on independent
617 * struct cvmx_usb_state.
619 * Returns: Number of port, zero if usb isn't supported
621 static int cvmx_usb_get_num_ports(void)
625 if (OCTEON_IS_MODEL(OCTEON_CN56XX
))
627 else if (OCTEON_IS_MODEL(OCTEON_CN52XX
))
629 else if (OCTEON_IS_MODEL(OCTEON_CN50XX
))
631 else if (OCTEON_IS_MODEL(OCTEON_CN31XX
))
633 else if (OCTEON_IS_MODEL(OCTEON_CN30XX
))
642 * Add a pipe to the tail of a list
643 * @list: List to add pipe to
646 static inline void __cvmx_usb_append_pipe(struct cvmx_usb_pipe_list
*list
, struct cvmx_usb_pipe
*pipe
)
649 pipe
->prev
= list
->tail
;
651 list
->tail
->next
= pipe
;
659 * Remove a pipe from a list
660 * @list: List to remove pipe from
661 * @pipe: Pipe to remove
663 static inline void __cvmx_usb_remove_pipe(struct cvmx_usb_pipe_list
*list
, struct cvmx_usb_pipe
*pipe
)
665 if (list
->head
== pipe
) {
666 list
->head
= pipe
->next
;
669 list
->head
->prev
= NULL
;
672 } else if (list
->tail
== pipe
) {
673 list
->tail
= pipe
->prev
;
674 list
->tail
->next
= NULL
;
677 pipe
->prev
->next
= pipe
->next
;
678 pipe
->next
->prev
= pipe
->prev
;
686 * Initialize a USB port for use. This must be called before any
687 * other access to the Octeon USB port is made. The port starts
688 * off in the disabled state.
690 * @usb: Pointer to an empty struct cvmx_usb_state
691 * that will be populated by the initialize call.
692 * This structure is then passed to all other USB
695 * Which Octeon USB port to initialize.
697 * Returns: 0 or a negative error code.
699 static int cvmx_usb_initialize(struct cvmx_usb_state
*usb
,
702 union cvmx_usbnx_clk_ctl usbn_clk_ctl
;
703 union cvmx_usbnx_usbp_ctl_status usbn_usbp_ctl_status
;
704 enum cvmx_usb_initialize_flags flags
= 0;
706 /* At first allow 0-1 for the usb port number */
707 if ((usb_port_number
< 0) || (usb_port_number
> 1))
709 /* For all chips except 52XX there is only one port */
710 if (!OCTEON_IS_MODEL(OCTEON_CN52XX
) && (usb_port_number
> 0))
712 /* Try to determine clock type automatically */
713 if (octeon_usb_get_clock_type() == USB_CLOCK_TYPE_CRYSTAL_12
) {
714 /* Only 12 MHZ crystals are supported */
715 flags
|= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI
;
717 flags
|= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND
;
719 switch (octeon_usb_get_clock_type()) {
720 case USB_CLOCK_TYPE_REF_12
:
721 flags
|= CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ
;
723 case USB_CLOCK_TYPE_REF_24
:
724 flags
|= CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ
;
726 case USB_CLOCK_TYPE_REF_48
:
727 flags
|= CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ
;
735 memset(usb
, 0, sizeof(*usb
));
736 usb
->init_flags
= flags
;
738 /* Initialize the USB state structure */
741 usb
->index
= usb_port_number
;
743 for (i
= 0; i
< MAX_PIPES
; i
++)
744 __cvmx_usb_append_pipe(&usb
->free_pipes
, usb
->pipe
+ i
);
748 * Power On Reset and PHY Initialization
750 * 1. Wait for DCOK to assert (nothing to do)
752 * 2a. Write USBN0/1_CLK_CTL[POR] = 1 and
753 * USBN0/1_CLK_CTL[HRST,PRST,HCLK_RST] = 0
755 usbn_clk_ctl
.u64
= __cvmx_usb_read_csr64(usb
, CVMX_USBNX_CLK_CTL(usb
->index
));
756 usbn_clk_ctl
.s
.por
= 1;
757 usbn_clk_ctl
.s
.hrst
= 0;
758 usbn_clk_ctl
.s
.prst
= 0;
759 usbn_clk_ctl
.s
.hclk_rst
= 0;
760 usbn_clk_ctl
.s
.enable
= 0;
762 * 2b. Select the USB reference clock/crystal parameters by writing
763 * appropriate values to USBN0/1_CLK_CTL[P_C_SEL, P_RTYPE, P_COM_ON]
765 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND
) {
767 * The USB port uses 12/24/48MHz 2.5V board clock
768 * source at USB_XO. USB_XI should be tied to GND.
769 * Most Octeon evaluation boards require this setting
771 if (OCTEON_IS_MODEL(OCTEON_CN3XXX
) ||
772 OCTEON_IS_MODEL(OCTEON_CN56XX
) ||
773 OCTEON_IS_MODEL(OCTEON_CN50XX
))
774 /* From CN56XX,CN50XX,CN31XX,CN30XX manuals */
775 usbn_clk_ctl
.s
.p_rtype
= 2; /* p_rclk=1 & p_xenbn=0 */
777 /* From CN52XX manual */
778 usbn_clk_ctl
.s
.p_rtype
= 1;
780 switch (flags
& CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK
) {
781 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ
:
782 usbn_clk_ctl
.s
.p_c_sel
= 0;
784 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ
:
785 usbn_clk_ctl
.s
.p_c_sel
= 1;
787 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ
:
788 usbn_clk_ctl
.s
.p_c_sel
= 2;
793 * The USB port uses a 12MHz crystal as clock source
794 * at USB_XO and USB_XI
796 if (OCTEON_IS_MODEL(OCTEON_CN3XXX
))
797 /* From CN31XX,CN30XX manual */
798 usbn_clk_ctl
.s
.p_rtype
= 3; /* p_rclk=1 & p_xenbn=1 */
800 /* From CN56XX,CN52XX,CN50XX manuals. */
801 usbn_clk_ctl
.s
.p_rtype
= 0;
803 usbn_clk_ctl
.s
.p_c_sel
= 0;
806 * 2c. Select the HCLK via writing USBN0/1_CLK_CTL[DIVIDE, DIVIDE2] and
807 * setting USBN0/1_CLK_CTL[ENABLE] = 1. Divide the core clock down
808 * such that USB is as close as possible to 125Mhz
811 int divisor
= (octeon_get_clock_rate()+125000000-1)/125000000;
812 /* Lower than 4 doesn't seem to work properly */
815 usbn_clk_ctl
.s
.divide
= divisor
;
816 usbn_clk_ctl
.s
.divide2
= 0;
818 __cvmx_usb_write_csr64(usb
, CVMX_USBNX_CLK_CTL(usb
->index
),
820 /* 2d. Write USBN0/1_CLK_CTL[HCLK_RST] = 1 */
821 usbn_clk_ctl
.s
.hclk_rst
= 1;
822 __cvmx_usb_write_csr64(usb
, CVMX_USBNX_CLK_CTL(usb
->index
),
824 /* 2e. Wait 64 core-clock cycles for HCLK to stabilize */
827 * 3. Program the power-on reset field in the USBN clock-control
829 * USBN_CLK_CTL[POR] = 0
831 usbn_clk_ctl
.s
.por
= 0;
832 __cvmx_usb_write_csr64(usb
, CVMX_USBNX_CLK_CTL(usb
->index
),
834 /* 4. Wait 1 ms for PHY clock to start */
837 * 5. Program the Reset input from automatic test equipment field in the
838 * USBP control and status register:
839 * USBN_USBP_CTL_STATUS[ATE_RESET] = 1
841 usbn_usbp_ctl_status
.u64
= __cvmx_usb_read_csr64(usb
, CVMX_USBNX_USBP_CTL_STATUS(usb
->index
));
842 usbn_usbp_ctl_status
.s
.ate_reset
= 1;
843 __cvmx_usb_write_csr64(usb
, CVMX_USBNX_USBP_CTL_STATUS(usb
->index
),
844 usbn_usbp_ctl_status
.u64
);
845 /* 6. Wait 10 cycles */
848 * 7. Clear ATE_RESET field in the USBN clock-control register:
849 * USBN_USBP_CTL_STATUS[ATE_RESET] = 0
851 usbn_usbp_ctl_status
.s
.ate_reset
= 0;
852 __cvmx_usb_write_csr64(usb
, CVMX_USBNX_USBP_CTL_STATUS(usb
->index
),
853 usbn_usbp_ctl_status
.u64
);
855 * 8. Program the PHY reset field in the USBN clock-control register:
856 * USBN_CLK_CTL[PRST] = 1
858 usbn_clk_ctl
.s
.prst
= 1;
859 __cvmx_usb_write_csr64(usb
, CVMX_USBNX_CLK_CTL(usb
->index
),
862 * 9. Program the USBP control and status register to select host or
863 * device mode. USBN_USBP_CTL_STATUS[HST_MODE] = 0 for host, = 1 for
866 usbn_usbp_ctl_status
.s
.hst_mode
= 0;
867 __cvmx_usb_write_csr64(usb
, CVMX_USBNX_USBP_CTL_STATUS(usb
->index
),
868 usbn_usbp_ctl_status
.u64
);
872 * 11. Program the hreset_n field in the USBN clock-control register:
873 * USBN_CLK_CTL[HRST] = 1
875 usbn_clk_ctl
.s
.hrst
= 1;
876 __cvmx_usb_write_csr64(usb
, CVMX_USBNX_CLK_CTL(usb
->index
),
878 /* 12. Proceed to USB core initialization */
879 usbn_clk_ctl
.s
.enable
= 1;
880 __cvmx_usb_write_csr64(usb
, CVMX_USBNX_CLK_CTL(usb
->index
),
885 * USB Core Initialization
887 * 1. Read USBC_GHWCFG1, USBC_GHWCFG2, USBC_GHWCFG3, USBC_GHWCFG4 to
888 * determine USB core configuration parameters.
892 * 2. Program the following fields in the global AHB configuration
893 * register (USBC_GAHBCFG)
894 * DMA mode, USBC_GAHBCFG[DMAEn]: 1 = DMA mode, 0 = slave mode
895 * Burst length, USBC_GAHBCFG[HBSTLEN] = 0
896 * Nonperiodic TxFIFO empty level (slave mode only),
897 * USBC_GAHBCFG[NPTXFEMPLVL]
898 * Periodic TxFIFO empty level (slave mode only),
899 * USBC_GAHBCFG[PTXFEMPLVL]
900 * Global interrupt mask, USBC_GAHBCFG[GLBLINTRMSK] = 1
903 union cvmx_usbcx_gahbcfg usbcx_gahbcfg
;
904 /* Due to an errata, CN31XX doesn't support DMA */
905 if (OCTEON_IS_MODEL(OCTEON_CN31XX
))
906 usb
->init_flags
|= CVMX_USB_INITIALIZE_FLAGS_NO_DMA
;
907 usbcx_gahbcfg
.u32
= 0;
908 usbcx_gahbcfg
.s
.dmaen
= !(usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
);
909 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)
910 /* Only use one channel with non DMA */
911 usb
->idle_hardware_channels
= 0x1;
912 else if (OCTEON_IS_MODEL(OCTEON_CN5XXX
))
913 /* CN5XXX have an errata with channel 3 */
914 usb
->idle_hardware_channels
= 0xf7;
916 usb
->idle_hardware_channels
= 0xff;
917 usbcx_gahbcfg
.s
.hbstlen
= 0;
918 usbcx_gahbcfg
.s
.nptxfemplvl
= 1;
919 usbcx_gahbcfg
.s
.ptxfemplvl
= 1;
920 usbcx_gahbcfg
.s
.glblintrmsk
= 1;
921 __cvmx_usb_write_csr32(usb
, CVMX_USBCX_GAHBCFG(usb
->index
),
925 * 3. Program the following fields in USBC_GUSBCFG register.
926 * HS/FS timeout calibration, USBC_GUSBCFG[TOUTCAL] = 0
927 * ULPI DDR select, USBC_GUSBCFG[DDRSEL] = 0
928 * USB turnaround time, USBC_GUSBCFG[USBTRDTIM] = 0x5
929 * PHY low-power clock select, USBC_GUSBCFG[PHYLPWRCLKSEL] = 0
932 union cvmx_usbcx_gusbcfg usbcx_gusbcfg
;
933 usbcx_gusbcfg
.u32
= __cvmx_usb_read_csr32(usb
, CVMX_USBCX_GUSBCFG(usb
->index
));
934 usbcx_gusbcfg
.s
.toutcal
= 0;
935 usbcx_gusbcfg
.s
.ddrsel
= 0;
936 usbcx_gusbcfg
.s
.usbtrdtim
= 0x5;
937 usbcx_gusbcfg
.s
.phylpwrclksel
= 0;
938 __cvmx_usb_write_csr32(usb
, CVMX_USBCX_GUSBCFG(usb
->index
),
942 * 4. The software must unmask the following bits in the USBC_GINTMSK
944 * OTG interrupt mask, USBC_GINTMSK[OTGINTMSK] = 1
945 * Mode mismatch interrupt mask, USBC_GINTMSK[MODEMISMSK] = 1
948 union cvmx_usbcx_gintmsk usbcx_gintmsk
;
951 usbcx_gintmsk
.u32
= __cvmx_usb_read_csr32(usb
, CVMX_USBCX_GINTMSK(usb
->index
));
952 usbcx_gintmsk
.s
.otgintmsk
= 1;
953 usbcx_gintmsk
.s
.modemismsk
= 1;
954 usbcx_gintmsk
.s
.hchintmsk
= 1;
955 usbcx_gintmsk
.s
.sofmsk
= 0;
956 /* We need RX FIFO interrupts if we don't have DMA */
957 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)
958 usbcx_gintmsk
.s
.rxflvlmsk
= 1;
959 __cvmx_usb_write_csr32(usb
, CVMX_USBCX_GINTMSK(usb
->index
),
963 * Disable all channel interrupts. We'll enable them per channel
966 for (channel
= 0; channel
< 8; channel
++)
967 __cvmx_usb_write_csr32(usb
, CVMX_USBCX_HCINTMSKX(channel
, usb
->index
), 0);
972 * Host Port Initialization
974 * 1. Program the host-port interrupt-mask field to unmask,
975 * USBC_GINTMSK[PRTINT] = 1
977 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
), union cvmx_usbcx_gintmsk
,
979 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
), union cvmx_usbcx_gintmsk
,
982 * 2. Program the USBC_HCFG register to select full-speed host
983 * or high-speed host.
986 union cvmx_usbcx_hcfg usbcx_hcfg
;
987 usbcx_hcfg
.u32
= __cvmx_usb_read_csr32(usb
, CVMX_USBCX_HCFG(usb
->index
));
988 usbcx_hcfg
.s
.fslssupp
= 0;
989 usbcx_hcfg
.s
.fslspclksel
= 0;
990 __cvmx_usb_write_csr32(usb
, CVMX_USBCX_HCFG(usb
->index
), usbcx_hcfg
.u32
);
993 * 3. Program the port power bit to drive VBUS on the USB,
994 * USBC_HPRT[PRTPWR] = 1
996 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb
->index
), union cvmx_usbcx_hprt
, prtpwr
, 1);
999 * Steps 4-15 from the manual are done later in the port enable
1008 * Shutdown a USB port after a call to cvmx_usb_initialize().
1009 * The port should be disabled with all pipes closed when this
1010 * function is called.
1012 * @usb: USB device state populated by cvmx_usb_initialize().
1014 * Returns: 0 or a negative error code.
1016 static int cvmx_usb_shutdown(struct cvmx_usb_state
*usb
)
1018 union cvmx_usbnx_clk_ctl usbn_clk_ctl
;
1020 /* Make sure all pipes are closed */
1021 if (usb
->idle_pipes
.head
||
1022 usb
->active_pipes
[CVMX_USB_TRANSFER_ISOCHRONOUS
].head
||
1023 usb
->active_pipes
[CVMX_USB_TRANSFER_INTERRUPT
].head
||
1024 usb
->active_pipes
[CVMX_USB_TRANSFER_CONTROL
].head
||
1025 usb
->active_pipes
[CVMX_USB_TRANSFER_BULK
].head
)
1028 /* Disable the clocks and put them in power on reset */
1029 usbn_clk_ctl
.u64
= __cvmx_usb_read_csr64(usb
, CVMX_USBNX_CLK_CTL(usb
->index
));
1030 usbn_clk_ctl
.s
.enable
= 1;
1031 usbn_clk_ctl
.s
.por
= 1;
1032 usbn_clk_ctl
.s
.hclk_rst
= 1;
1033 usbn_clk_ctl
.s
.prst
= 0;
1034 usbn_clk_ctl
.s
.hrst
= 0;
1035 __cvmx_usb_write_csr64(usb
, CVMX_USBNX_CLK_CTL(usb
->index
),
1042 * Enable a USB port. After this call succeeds, the USB port is
1043 * online and servicing requests.
1045 * @usb: USB device state populated by cvmx_usb_initialize().
1047 * Returns: 0 or a negative error code.
1049 static int cvmx_usb_enable(struct cvmx_usb_state
*usb
)
1051 union cvmx_usbcx_ghwcfg3 usbcx_ghwcfg3
;
1053 usb
->usbcx_hprt
.u32
= __cvmx_usb_read_csr32(usb
, CVMX_USBCX_HPRT(usb
->index
));
1056 * If the port is already enabled the just return. We don't need to do
1059 if (usb
->usbcx_hprt
.s
.prtena
)
1062 /* If there is nothing plugged into the port then fail immediately */
1063 if (!usb
->usbcx_hprt
.s
.prtconnsts
) {
1067 /* Program the port reset bit to start the reset process */
1068 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb
->index
), union cvmx_usbcx_hprt
, prtrst
, 1);
1071 * Wait at least 50ms (high speed), or 10ms (full speed) for the reset
1072 * process to complete.
1076 /* Program the port reset bit to 0, USBC_HPRT[PRTRST] = 0 */
1077 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb
->index
), union cvmx_usbcx_hprt
, prtrst
, 0);
1079 /* Wait for the USBC_HPRT[PRTENA]. */
1080 if (CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_HPRT(usb
->index
), union cvmx_usbcx_hprt
,
1081 prtena
, ==, 1, 100000))
1085 * Read the port speed field to get the enumerated speed,
1086 * USBC_HPRT[PRTSPD].
1088 usb
->usbcx_hprt
.u32
= __cvmx_usb_read_csr32(usb
, CVMX_USBCX_HPRT(usb
->index
));
1089 usbcx_ghwcfg3
.u32
= __cvmx_usb_read_csr32(usb
, CVMX_USBCX_GHWCFG3(usb
->index
));
1092 * 13. Program the USBC_GRXFSIZ register to select the size of the
1093 * receive FIFO (25%).
1095 USB_SET_FIELD32(CVMX_USBCX_GRXFSIZ(usb
->index
), union cvmx_usbcx_grxfsiz
,
1096 rxfdep
, usbcx_ghwcfg3
.s
.dfifodepth
/ 4);
1098 * 14. Program the USBC_GNPTXFSIZ register to select the size and the
1099 * start address of the non- periodic transmit FIFO for nonperiodic
1100 * transactions (50%).
1103 union cvmx_usbcx_gnptxfsiz siz
;
1104 siz
.u32
= __cvmx_usb_read_csr32(usb
, CVMX_USBCX_GNPTXFSIZ(usb
->index
));
1105 siz
.s
.nptxfdep
= usbcx_ghwcfg3
.s
.dfifodepth
/ 2;
1106 siz
.s
.nptxfstaddr
= usbcx_ghwcfg3
.s
.dfifodepth
/ 4;
1107 __cvmx_usb_write_csr32(usb
, CVMX_USBCX_GNPTXFSIZ(usb
->index
), siz
.u32
);
1110 * 15. Program the USBC_HPTXFSIZ register to select the size and start
1111 * address of the periodic transmit FIFO for periodic transactions
1115 union cvmx_usbcx_hptxfsiz siz
;
1116 siz
.u32
= __cvmx_usb_read_csr32(usb
, CVMX_USBCX_HPTXFSIZ(usb
->index
));
1117 siz
.s
.ptxfsize
= usbcx_ghwcfg3
.s
.dfifodepth
/ 4;
1118 siz
.s
.ptxfstaddr
= 3 * usbcx_ghwcfg3
.s
.dfifodepth
/ 4;
1119 __cvmx_usb_write_csr32(usb
, CVMX_USBCX_HPTXFSIZ(usb
->index
), siz
.u32
);
1121 /* Flush all FIFOs */
1122 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb
->index
), union cvmx_usbcx_grstctl
, txfnum
, 0x10);
1123 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb
->index
), union cvmx_usbcx_grstctl
, txfflsh
, 1);
1124 CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb
->index
), union cvmx_usbcx_grstctl
,
1125 txfflsh
, ==, 0, 100);
1126 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb
->index
), union cvmx_usbcx_grstctl
, rxfflsh
, 1);
1127 CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb
->index
), union cvmx_usbcx_grstctl
,
1128 rxfflsh
, ==, 0, 100);
1135 * Disable a USB port. After this call the USB port will not
1136 * generate data transfers and will not generate events.
1137 * Transactions in process will fail and call their
1138 * associated callbacks.
1140 * @usb: USB device state populated by cvmx_usb_initialize().
1142 * Returns: 0 or a negative error code.
1144 static int cvmx_usb_disable(struct cvmx_usb_state
*usb
)
1146 /* Disable the port */
1147 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb
->index
), union cvmx_usbcx_hprt
, prtena
, 1);
1153 * Get the current state of the USB port. Use this call to
1154 * determine if the usb port has anything connected, is enabled,
1155 * or has some sort of error condition. The return value of this
1156 * call has "changed" bits to signal of the value of some fields
1157 * have changed between calls.
1159 * @usb: USB device state populated by cvmx_usb_initialize().
1161 * Returns: Port status information
1163 static struct cvmx_usb_port_status
cvmx_usb_get_status(struct cvmx_usb_state
*usb
)
1165 union cvmx_usbcx_hprt usbc_hprt
;
1166 struct cvmx_usb_port_status result
;
1168 memset(&result
, 0, sizeof(result
));
1170 usbc_hprt
.u32
= __cvmx_usb_read_csr32(usb
, CVMX_USBCX_HPRT(usb
->index
));
1171 result
.port_enabled
= usbc_hprt
.s
.prtena
;
1172 result
.port_over_current
= usbc_hprt
.s
.prtovrcurract
;
1173 result
.port_powered
= usbc_hprt
.s
.prtpwr
;
1174 result
.port_speed
= usbc_hprt
.s
.prtspd
;
1175 result
.connected
= usbc_hprt
.s
.prtconnsts
;
1176 result
.connect_change
= (result
.connected
!= usb
->port_status
.connected
);
1182 * Open a virtual pipe between the host and a USB device. A pipe
1183 * must be opened before data can be transferred between a device
1186 * @usb: USB device state populated by cvmx_usb_initialize().
1188 * USB device address to open the pipe to
1191 * USB endpoint number to open the pipe to
1194 * The speed of the device the pipe is going
1195 * to. This must match the device's speed,
1196 * which may be different than the port speed.
1197 * @max_packet: The maximum packet length the device can
1198 * transmit/receive (low speed=0-8, full
1199 * speed=0-1023, high speed=0-1024). This value
1200 * comes from the standard endpoint descriptor
1201 * field wMaxPacketSize bits <10:0>.
1203 * The type of transfer this pipe is for.
1205 * The direction the pipe is in. This is not
1206 * used for control pipes.
1207 * @interval: For ISOCHRONOUS and INTERRUPT transfers,
1208 * this is how often the transfer is scheduled
1209 * for. All other transfers should specify
1210 * zero. The units are in frames (8000/sec at
1211 * high speed, 1000/sec for full speed).
1213 * For high speed devices, this is the maximum
1214 * allowed number of packet per microframe.
1215 * Specify zero for non high speed devices. This
1216 * value comes from the standard endpoint descriptor
1217 * field wMaxPacketSize bits <12:11>.
1219 * Hub device address this device is connected
1220 * to. Devices connected directly to Octeon
1221 * use zero. This is only used when the device
1222 * is full/low speed behind a high speed hub.
1223 * The address will be of the high speed hub,
1224 * not and full speed hubs after it.
1225 * @hub_port: Which port on the hub the device is
1226 * connected. Use zero for devices connected
1227 * directly to Octeon. Like hub_device_addr,
1228 * this is only used for full/low speed
1229 * devices behind a high speed hub.
1231 * Returns: A non-NULL value is a pipe. NULL means an error.
1233 static struct cvmx_usb_pipe
*cvmx_usb_open_pipe(struct cvmx_usb_state
*usb
,
1234 int device_addr
, int
1239 enum cvmx_usb_transfer
1241 enum cvmx_usb_direction
1243 int interval
, int multi_count
,
1244 int hub_device_addr
,
1247 struct cvmx_usb_pipe
*pipe
;
1249 if (unlikely((device_addr
< 0) || (device_addr
> MAX_USB_ADDRESS
)))
1251 if (unlikely((endpoint_num
< 0) || (endpoint_num
> MAX_USB_ENDPOINT
)))
1253 if (unlikely(device_speed
> CVMX_USB_SPEED_LOW
))
1255 if (unlikely((max_packet
<= 0) || (max_packet
> 1024)))
1257 if (unlikely(transfer_type
> CVMX_USB_TRANSFER_INTERRUPT
))
1259 if (unlikely((transfer_dir
!= CVMX_USB_DIRECTION_OUT
) &&
1260 (transfer_dir
!= CVMX_USB_DIRECTION_IN
)))
1262 if (unlikely(interval
< 0))
1264 if (unlikely((transfer_type
== CVMX_USB_TRANSFER_CONTROL
) && interval
))
1266 if (unlikely(multi_count
< 0))
1268 if (unlikely((device_speed
!= CVMX_USB_SPEED_HIGH
) &&
1269 (multi_count
!= 0)))
1271 if (unlikely((hub_device_addr
< 0) || (hub_device_addr
> MAX_USB_ADDRESS
)))
1273 if (unlikely((hub_port
< 0) || (hub_port
> MAX_USB_HUB_PORT
)))
1276 /* Find a free pipe */
1277 pipe
= usb
->free_pipes
.head
;
1280 __cvmx_usb_remove_pipe(&usb
->free_pipes
, pipe
);
1281 pipe
->flags
= __CVMX_USB_PIPE_FLAGS_OPEN
;
1282 if ((device_speed
== CVMX_USB_SPEED_HIGH
) &&
1283 (transfer_dir
== CVMX_USB_DIRECTION_OUT
) &&
1284 (transfer_type
== CVMX_USB_TRANSFER_BULK
))
1285 pipe
->flags
|= __CVMX_USB_PIPE_FLAGS_NEED_PING
;
1286 pipe
->device_addr
= device_addr
;
1287 pipe
->endpoint_num
= endpoint_num
;
1288 pipe
->device_speed
= device_speed
;
1289 pipe
->max_packet
= max_packet
;
1290 pipe
->transfer_type
= transfer_type
;
1291 pipe
->transfer_dir
= transfer_dir
;
1293 * All pipes use interval to rate limit NAK processing. Force an
1294 * interval if one wasn't supplied
1298 if (__cvmx_usb_pipe_needs_split(usb
, pipe
)) {
1299 pipe
->interval
= interval
*8;
1300 /* Force start splits to be schedule on uFrame 0 */
1301 pipe
->next_tx_frame
= ((usb
->frame_number
+7)&~7) + pipe
->interval
;
1303 pipe
->interval
= interval
;
1304 pipe
->next_tx_frame
= usb
->frame_number
+ pipe
->interval
;
1306 pipe
->multi_count
= multi_count
;
1307 pipe
->hub_device_addr
= hub_device_addr
;
1308 pipe
->hub_port
= hub_port
;
1309 pipe
->pid_toggle
= 0;
1310 pipe
->split_sc_frame
= -1;
1311 __cvmx_usb_append_pipe(&usb
->idle_pipes
, pipe
);
1314 * We don't need to tell the hardware about this pipe yet since
1315 * it doesn't have any submitted requests
1323 * Poll the RX FIFOs and remove data as needed. This function is only used
1324 * in non DMA mode. It is very important that this function be called quickly
1325 * enough to prevent FIFO overflow.
1327 * @usb: USB device state populated by cvmx_usb_initialize().
1329 static void __cvmx_usb_poll_rx_fifo(struct cvmx_usb_state
*usb
)
1331 union cvmx_usbcx_grxstsph rx_status
;
1337 rx_status
.u32
= __cvmx_usb_read_csr32(usb
, CVMX_USBCX_GRXSTSPH(usb
->index
));
1338 /* Only read data if IN data is there */
1339 if (rx_status
.s
.pktsts
!= 2)
1341 /* Check if no data is available */
1342 if (!rx_status
.s
.bcnt
)
1345 channel
= rx_status
.s
.chnum
;
1346 bytes
= rx_status
.s
.bcnt
;
1350 /* Get where the DMA engine would have written this data */
1351 address
= __cvmx_usb_read_csr64(usb
, CVMX_USBNX_DMA0_INB_CHN0(usb
->index
) + channel
*8);
1352 ptr
= cvmx_phys_to_ptr(address
);
1353 __cvmx_usb_write_csr64(usb
, CVMX_USBNX_DMA0_INB_CHN0(usb
->index
) + channel
*8, address
+ bytes
);
1355 /* Loop writing the FIFO data for this packet into memory */
1357 *ptr
++ = __cvmx_usb_read_csr32(usb
, USB_FIFO_ADDRESS(channel
, usb
->index
));
1367 * Fill the TX hardware fifo with data out of the software
1370 * @usb: USB device state populated by cvmx_usb_initialize().
1371 * @fifo: Software fifo to use
1372 * @available: Amount of space in the hardware fifo
1374 * Returns: Non zero if the hardware fifo was too small and needs
1375 * to be serviced again.
1377 static int __cvmx_usb_fill_tx_hw(struct cvmx_usb_state
*usb
,
1378 struct cvmx_usb_tx_fifo
*fifo
, int available
)
1381 * We're done either when there isn't anymore space or the software FIFO
1384 while (available
&& (fifo
->head
!= fifo
->tail
)) {
1386 const uint32_t *ptr
= cvmx_phys_to_ptr(fifo
->entry
[i
].address
);
1387 uint64_t csr_address
= USB_FIFO_ADDRESS(fifo
->entry
[i
].channel
, usb
->index
) ^ 4;
1388 int words
= available
;
1390 /* Limit the amount of data to waht the SW fifo has */
1391 if (fifo
->entry
[i
].size
<= available
) {
1392 words
= fifo
->entry
[i
].size
;
1394 if (fifo
->tail
> MAX_CHANNELS
)
1398 /* Update the next locations and counts */
1400 fifo
->entry
[i
].address
+= words
* 4;
1401 fifo
->entry
[i
].size
-= words
;
1404 * Write the HW fifo data. The read every three writes is due
1405 * to an errata on CN3XXX chips
1408 cvmx_write64_uint32(csr_address
, *ptr
++);
1409 cvmx_write64_uint32(csr_address
, *ptr
++);
1410 cvmx_write64_uint32(csr_address
, *ptr
++);
1411 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb
->index
));
1414 cvmx_write64_uint32(csr_address
, *ptr
++);
1416 cvmx_write64_uint32(csr_address
, *ptr
++);
1418 cvmx_write64_uint32(csr_address
, *ptr
++);
1420 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb
->index
));
1422 return fifo
->head
!= fifo
->tail
;
1427 * Check the hardware FIFOs and fill them as needed
1429 * @usb: USB device state populated by cvmx_usb_initialize().
1431 static void __cvmx_usb_poll_tx_fifo(struct cvmx_usb_state
*usb
)
1433 if (usb
->periodic
.head
!= usb
->periodic
.tail
) {
1434 union cvmx_usbcx_hptxsts tx_status
;
1435 tx_status
.u32
= __cvmx_usb_read_csr32(usb
, CVMX_USBCX_HPTXSTS(usb
->index
));
1436 if (__cvmx_usb_fill_tx_hw(usb
, &usb
->periodic
, tx_status
.s
.ptxfspcavail
))
1437 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
), union cvmx_usbcx_gintmsk
, ptxfempmsk
, 1);
1439 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
), union cvmx_usbcx_gintmsk
, ptxfempmsk
, 0);
1442 if (usb
->nonperiodic
.head
!= usb
->nonperiodic
.tail
) {
1443 union cvmx_usbcx_gnptxsts tx_status
;
1444 tx_status
.u32
= __cvmx_usb_read_csr32(usb
, CVMX_USBCX_GNPTXSTS(usb
->index
));
1445 if (__cvmx_usb_fill_tx_hw(usb
, &usb
->nonperiodic
, tx_status
.s
.nptxfspcavail
))
1446 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
), union cvmx_usbcx_gintmsk
, nptxfempmsk
, 1);
1448 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
), union cvmx_usbcx_gintmsk
, nptxfempmsk
, 0);
1456 * Fill the TX FIFO with an outgoing packet
1458 * @usb: USB device state populated by cvmx_usb_initialize().
1459 * @channel: Channel number to get packet from
1461 static void __cvmx_usb_fill_tx_fifo(struct cvmx_usb_state
*usb
, int channel
)
1463 union cvmx_usbcx_hccharx hcchar
;
1464 union cvmx_usbcx_hcspltx usbc_hcsplt
;
1465 union cvmx_usbcx_hctsizx usbc_hctsiz
;
1466 struct cvmx_usb_tx_fifo
*fifo
;
1468 /* We only need to fill data on outbound channels */
1469 hcchar
.u32
= __cvmx_usb_read_csr32(usb
, CVMX_USBCX_HCCHARX(channel
, usb
->index
));
1470 if (hcchar
.s
.epdir
!= CVMX_USB_DIRECTION_OUT
)
1473 /* OUT Splits only have data on the start and not the complete */
1474 usbc_hcsplt
.u32
= __cvmx_usb_read_csr32(usb
, CVMX_USBCX_HCSPLTX(channel
, usb
->index
));
1475 if (usbc_hcsplt
.s
.spltena
&& usbc_hcsplt
.s
.compsplt
)
1479 * Find out how many bytes we need to fill and convert it into 32bit
1482 usbc_hctsiz
.u32
= __cvmx_usb_read_csr32(usb
, CVMX_USBCX_HCTSIZX(channel
, usb
->index
));
1483 if (!usbc_hctsiz
.s
.xfersize
)
1486 if ((hcchar
.s
.eptype
== CVMX_USB_TRANSFER_INTERRUPT
) ||
1487 (hcchar
.s
.eptype
== CVMX_USB_TRANSFER_ISOCHRONOUS
))
1488 fifo
= &usb
->periodic
;
1490 fifo
= &usb
->nonperiodic
;
1492 fifo
->entry
[fifo
->head
].channel
= channel
;
1493 fifo
->entry
[fifo
->head
].address
= __cvmx_usb_read_csr64(usb
, CVMX_USBNX_DMA0_OUTB_CHN0(usb
->index
) + channel
*8);
1494 fifo
->entry
[fifo
->head
].size
= (usbc_hctsiz
.s
.xfersize
+3)>>2;
1496 if (fifo
->head
> MAX_CHANNELS
)
1499 __cvmx_usb_poll_tx_fifo(usb
);
1505 * Perform channel specific setup for Control transactions. All
1506 * the generic stuff will already have been done in
1507 * __cvmx_usb_start_channel()
1509 * @usb: USB device state populated by cvmx_usb_initialize().
1510 * @channel: Channel to setup
1511 * @pipe: Pipe for control transaction
1513 static void __cvmx_usb_start_channel_control(struct cvmx_usb_state
*usb
,
1515 struct cvmx_usb_pipe
*pipe
)
1517 struct cvmx_usb_transaction
*transaction
= pipe
->head
;
1518 union cvmx_usb_control_header
*header
=
1519 cvmx_phys_to_ptr(transaction
->control_header
);
1520 int bytes_to_transfer
= transaction
->buffer_length
- transaction
->actual_bytes
;
1521 int packets_to_transfer
;
1522 union cvmx_usbcx_hctsizx usbc_hctsiz
;
1524 usbc_hctsiz
.u32
= __cvmx_usb_read_csr32(usb
, CVMX_USBCX_HCTSIZX(channel
, usb
->index
));
1526 switch (transaction
->stage
) {
1527 case CVMX_USB_STAGE_NON_CONTROL
:
1528 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
:
1529 cvmx_dprintf("%s: ERROR - Non control stage\n", __FUNCTION__
);
1531 case CVMX_USB_STAGE_SETUP
:
1532 usbc_hctsiz
.s
.pid
= 3; /* Setup */
1533 bytes_to_transfer
= sizeof(*header
);
1534 /* All Control operations start with a setup going OUT */
1535 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
), union cvmx_usbcx_hccharx
, epdir
, CVMX_USB_DIRECTION_OUT
);
1537 * Setup send the control header instead of the buffer data. The
1538 * buffer data will be used in the next stage
1540 __cvmx_usb_write_csr64(usb
, CVMX_USBNX_DMA0_OUTB_CHN0(usb
->index
) + channel
*8, transaction
->control_header
);
1542 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE
:
1543 usbc_hctsiz
.s
.pid
= 3; /* Setup */
1544 bytes_to_transfer
= 0;
1545 /* All Control operations start with a setup going OUT */
1546 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
), union cvmx_usbcx_hccharx
, epdir
, CVMX_USB_DIRECTION_OUT
);
1547 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel
, usb
->index
), union cvmx_usbcx_hcspltx
, compsplt
, 1);
1549 case CVMX_USB_STAGE_DATA
:
1550 usbc_hctsiz
.s
.pid
= __cvmx_usb_get_data_pid(pipe
);
1551 if (__cvmx_usb_pipe_needs_split(usb
, pipe
)) {
1552 if (header
->s
.request_type
& 0x80)
1553 bytes_to_transfer
= 0;
1554 else if (bytes_to_transfer
> pipe
->max_packet
)
1555 bytes_to_transfer
= pipe
->max_packet
;
1557 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1558 union cvmx_usbcx_hccharx
, epdir
,
1559 ((header
->s
.request_type
& 0x80) ?
1560 CVMX_USB_DIRECTION_IN
:
1561 CVMX_USB_DIRECTION_OUT
));
1563 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE
:
1564 usbc_hctsiz
.s
.pid
= __cvmx_usb_get_data_pid(pipe
);
1565 if (!(header
->s
.request_type
& 0x80))
1566 bytes_to_transfer
= 0;
1567 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
),
1568 union cvmx_usbcx_hccharx
, epdir
,
1569 ((header
->s
.request_type
& 0x80) ?
1570 CVMX_USB_DIRECTION_IN
:
1571 CVMX_USB_DIRECTION_OUT
));
1572 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel
, usb
->index
), union cvmx_usbcx_hcspltx
, compsplt
, 1);
1574 case CVMX_USB_STAGE_STATUS
:
1575 usbc_hctsiz
.s
.pid
= __cvmx_usb_get_data_pid(pipe
);
1576 bytes_to_transfer
= 0;
1577 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
), union cvmx_usbcx_hccharx
, epdir
,
1578 ((header
->s
.request_type
& 0x80) ?
1579 CVMX_USB_DIRECTION_OUT
:
1580 CVMX_USB_DIRECTION_IN
));
1582 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE
:
1583 usbc_hctsiz
.s
.pid
= __cvmx_usb_get_data_pid(pipe
);
1584 bytes_to_transfer
= 0;
1585 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
), union cvmx_usbcx_hccharx
, epdir
,
1586 ((header
->s
.request_type
& 0x80) ?
1587 CVMX_USB_DIRECTION_OUT
:
1588 CVMX_USB_DIRECTION_IN
));
1589 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel
, usb
->index
), union cvmx_usbcx_hcspltx
, compsplt
, 1);
1594 * Make sure the transfer never exceeds the byte limit of the hardware.
1595 * Further bytes will be sent as continued transactions
1597 if (bytes_to_transfer
> MAX_TRANSFER_BYTES
) {
1598 /* Round MAX_TRANSFER_BYTES to a multiple of out packet size */
1599 bytes_to_transfer
= MAX_TRANSFER_BYTES
/ pipe
->max_packet
;
1600 bytes_to_transfer
*= pipe
->max_packet
;
1604 * Calculate the number of packets to transfer. If the length is zero
1605 * we still need to transfer one packet
1607 packets_to_transfer
= (bytes_to_transfer
+ pipe
->max_packet
- 1) / pipe
->max_packet
;
1608 if (packets_to_transfer
== 0)
1609 packets_to_transfer
= 1;
1610 else if ((packets_to_transfer
> 1) && (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)) {
1612 * Limit to one packet when not using DMA. Channels must be
1613 * restarted between every packet for IN transactions, so there
1614 * is no reason to do multiple packets in a row
1616 packets_to_transfer
= 1;
1617 bytes_to_transfer
= packets_to_transfer
* pipe
->max_packet
;
1618 } else if (packets_to_transfer
> MAX_TRANSFER_PACKETS
) {
1620 * Limit the number of packet and data transferred to what the
1621 * hardware can handle
1623 packets_to_transfer
= MAX_TRANSFER_PACKETS
;
1624 bytes_to_transfer
= packets_to_transfer
* pipe
->max_packet
;
1627 usbc_hctsiz
.s
.xfersize
= bytes_to_transfer
;
1628 usbc_hctsiz
.s
.pktcnt
= packets_to_transfer
;
1630 __cvmx_usb_write_csr32(usb
, CVMX_USBCX_HCTSIZX(channel
, usb
->index
), usbc_hctsiz
.u32
);
1636 * Start a channel to perform the pipe's head transaction
1638 * @usb: USB device state populated by cvmx_usb_initialize().
1639 * @channel: Channel to setup
1640 * @pipe: Pipe to start
1642 static void __cvmx_usb_start_channel(struct cvmx_usb_state
*usb
,
1644 struct cvmx_usb_pipe
*pipe
)
1646 struct cvmx_usb_transaction
*transaction
= pipe
->head
;
1648 /* Make sure all writes to the DMA region get flushed */
1651 /* Attach the channel to the pipe */
1652 usb
->pipe_for_channel
[channel
] = pipe
;
1653 pipe
->channel
= channel
;
1654 pipe
->flags
|= __CVMX_USB_PIPE_FLAGS_SCHEDULED
;
1656 /* Mark this channel as in use */
1657 usb
->idle_hardware_channels
&= ~(1<<channel
);
1659 /* Enable the channel interrupt bits */
1661 union cvmx_usbcx_hcintx usbc_hcint
;
1662 union cvmx_usbcx_hcintmskx usbc_hcintmsk
;
1663 union cvmx_usbcx_haintmsk usbc_haintmsk
;
1665 /* Clear all channel status bits */
1666 usbc_hcint
.u32
= __cvmx_usb_read_csr32(usb
, CVMX_USBCX_HCINTX(channel
, usb
->index
));
1667 __cvmx_usb_write_csr32(usb
, CVMX_USBCX_HCINTX(channel
, usb
->index
), usbc_hcint
.u32
);
1669 usbc_hcintmsk
.u32
= 0;
1670 usbc_hcintmsk
.s
.chhltdmsk
= 1;
1671 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
) {
1673 * Channels need these extra interrupts when we aren't
1676 usbc_hcintmsk
.s
.datatglerrmsk
= 1;
1677 usbc_hcintmsk
.s
.frmovrunmsk
= 1;
1678 usbc_hcintmsk
.s
.bblerrmsk
= 1;
1679 usbc_hcintmsk
.s
.xacterrmsk
= 1;
1680 if (__cvmx_usb_pipe_needs_split(usb
, pipe
)) {
1682 * Splits don't generate xfercompl, so we need
1685 usbc_hcintmsk
.s
.nyetmsk
= 1;
1686 usbc_hcintmsk
.s
.ackmsk
= 1;
1688 usbc_hcintmsk
.s
.nakmsk
= 1;
1689 usbc_hcintmsk
.s
.stallmsk
= 1;
1690 usbc_hcintmsk
.s
.xfercomplmsk
= 1;
1692 __cvmx_usb_write_csr32(usb
, CVMX_USBCX_HCINTMSKX(channel
, usb
->index
), usbc_hcintmsk
.u32
);
1694 /* Enable the channel interrupt to propagate */
1695 usbc_haintmsk
.u32
= __cvmx_usb_read_csr32(usb
, CVMX_USBCX_HAINTMSK(usb
->index
));
1696 usbc_haintmsk
.s
.haintmsk
|= 1<<channel
;
1697 __cvmx_usb_write_csr32(usb
, CVMX_USBCX_HAINTMSK(usb
->index
), usbc_haintmsk
.u32
);
1700 /* Setup the locations the DMA engines use */
1702 uint64_t dma_address
= transaction
->buffer
+ transaction
->actual_bytes
;
1703 if (transaction
->type
== CVMX_USB_TRANSFER_ISOCHRONOUS
)
1704 dma_address
= transaction
->buffer
+ transaction
->iso_packets
[0].offset
+ transaction
->actual_bytes
;
1705 __cvmx_usb_write_csr64(usb
, CVMX_USBNX_DMA0_OUTB_CHN0(usb
->index
) + channel
*8, dma_address
);
1706 __cvmx_usb_write_csr64(usb
, CVMX_USBNX_DMA0_INB_CHN0(usb
->index
) + channel
*8, dma_address
);
1709 /* Setup both the size of the transfer and the SPLIT characteristics */
1711 union cvmx_usbcx_hcspltx usbc_hcsplt
= {.u32
= 0};
1712 union cvmx_usbcx_hctsizx usbc_hctsiz
= {.u32
= 0};
1713 int packets_to_transfer
;
1714 int bytes_to_transfer
= transaction
->buffer_length
- transaction
->actual_bytes
;
1717 * ISOCHRONOUS transactions store each individual transfer size
1718 * in the packet structure, not the global buffer_length
1720 if (transaction
->type
== CVMX_USB_TRANSFER_ISOCHRONOUS
)
1721 bytes_to_transfer
= transaction
->iso_packets
[0].length
- transaction
->actual_bytes
;
1724 * We need to do split transactions when we are talking to non
1725 * high speed devices that are behind a high speed hub
1727 if (__cvmx_usb_pipe_needs_split(usb
, pipe
)) {
1729 * On the start split phase (stage is even) record the
1730 * frame number we will need to send the split complete.
1731 * We only store the lower two bits since the time ahead
1732 * can only be two frames
1734 if ((transaction
->stage
&1) == 0) {
1735 if (transaction
->type
== CVMX_USB_TRANSFER_BULK
)
1736 pipe
->split_sc_frame
= (usb
->frame_number
+ 1) & 0x7f;
1738 pipe
->split_sc_frame
= (usb
->frame_number
+ 2) & 0x7f;
1740 pipe
->split_sc_frame
= -1;
1742 usbc_hcsplt
.s
.spltena
= 1;
1743 usbc_hcsplt
.s
.hubaddr
= pipe
->hub_device_addr
;
1744 usbc_hcsplt
.s
.prtaddr
= pipe
->hub_port
;
1745 usbc_hcsplt
.s
.compsplt
= (transaction
->stage
== CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
);
1748 * SPLIT transactions can only ever transmit one data
1749 * packet so limit the transfer size to the max packet
1752 if (bytes_to_transfer
> pipe
->max_packet
)
1753 bytes_to_transfer
= pipe
->max_packet
;
1756 * ISOCHRONOUS OUT splits are unique in that they limit
1757 * data transfers to 188 byte chunks representing the
1758 * begin/middle/end of the data or all
1760 if (!usbc_hcsplt
.s
.compsplt
&&
1761 (pipe
->transfer_dir
== CVMX_USB_DIRECTION_OUT
) &&
1762 (pipe
->transfer_type
== CVMX_USB_TRANSFER_ISOCHRONOUS
)) {
1764 * Clear the split complete frame number as
1765 * there isn't going to be a split complete
1767 pipe
->split_sc_frame
= -1;
1769 * See if we've started this transfer and sent
1772 if (transaction
->actual_bytes
== 0) {
1774 * Nothing sent yet, this is either a
1775 * begin or the entire payload
1777 if (bytes_to_transfer
<= 188)
1778 /* Entire payload in one go */
1779 usbc_hcsplt
.s
.xactpos
= 3;
1781 /* First part of payload */
1782 usbc_hcsplt
.s
.xactpos
= 2;
1785 * Continuing the previous data, we must
1786 * either be in the middle or at the end
1788 if (bytes_to_transfer
<= 188)
1789 /* End of payload */
1790 usbc_hcsplt
.s
.xactpos
= 1;
1792 /* Middle of payload */
1793 usbc_hcsplt
.s
.xactpos
= 0;
1796 * Again, the transfer size is limited to 188
1799 if (bytes_to_transfer
> 188)
1800 bytes_to_transfer
= 188;
1805 * Make sure the transfer never exceeds the byte limit of the
1806 * hardware. Further bytes will be sent as continued
1809 if (bytes_to_transfer
> MAX_TRANSFER_BYTES
) {
1811 * Round MAX_TRANSFER_BYTES to a multiple of out packet
1814 bytes_to_transfer
= MAX_TRANSFER_BYTES
/ pipe
->max_packet
;
1815 bytes_to_transfer
*= pipe
->max_packet
;
1819 * Calculate the number of packets to transfer. If the length is
1820 * zero we still need to transfer one packet
1822 packets_to_transfer
= (bytes_to_transfer
+ pipe
->max_packet
- 1) / pipe
->max_packet
;
1823 if (packets_to_transfer
== 0)
1824 packets_to_transfer
= 1;
1825 else if ((packets_to_transfer
> 1) && (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)) {
1827 * Limit to one packet when not using DMA. Channels must
1828 * be restarted between every packet for IN
1829 * transactions, so there is no reason to do multiple
1832 packets_to_transfer
= 1;
1833 bytes_to_transfer
= packets_to_transfer
* pipe
->max_packet
;
1834 } else if (packets_to_transfer
> MAX_TRANSFER_PACKETS
) {
1836 * Limit the number of packet and data transferred to
1837 * what the hardware can handle
1839 packets_to_transfer
= MAX_TRANSFER_PACKETS
;
1840 bytes_to_transfer
= packets_to_transfer
* pipe
->max_packet
;
1843 usbc_hctsiz
.s
.xfersize
= bytes_to_transfer
;
1844 usbc_hctsiz
.s
.pktcnt
= packets_to_transfer
;
1846 /* Update the DATA0/DATA1 toggle */
1847 usbc_hctsiz
.s
.pid
= __cvmx_usb_get_data_pid(pipe
);
1849 * High speed pipes may need a hardware ping before they start
1851 if (pipe
->flags
& __CVMX_USB_PIPE_FLAGS_NEED_PING
)
1852 usbc_hctsiz
.s
.dopng
= 1;
1854 __cvmx_usb_write_csr32(usb
, CVMX_USBCX_HCSPLTX(channel
, usb
->index
), usbc_hcsplt
.u32
);
1855 __cvmx_usb_write_csr32(usb
, CVMX_USBCX_HCTSIZX(channel
, usb
->index
), usbc_hctsiz
.u32
);
1858 /* Setup the Host Channel Characteristics Register */
1860 union cvmx_usbcx_hccharx usbc_hcchar
= {.u32
= 0};
1863 * Set the startframe odd/even properly. This is only used for
1866 usbc_hcchar
.s
.oddfrm
= usb
->frame_number
&1;
1869 * Set the number of back to back packets allowed by this
1870 * endpoint. Split transactions interpret "ec" as the number of
1871 * immediate retries of failure. These retries happen too
1872 * quickly, so we disable these entirely for splits
1874 if (__cvmx_usb_pipe_needs_split(usb
, pipe
))
1875 usbc_hcchar
.s
.ec
= 1;
1876 else if (pipe
->multi_count
< 1)
1877 usbc_hcchar
.s
.ec
= 1;
1878 else if (pipe
->multi_count
> 3)
1879 usbc_hcchar
.s
.ec
= 3;
1881 usbc_hcchar
.s
.ec
= pipe
->multi_count
;
1883 /* Set the rest of the endpoint specific settings */
1884 usbc_hcchar
.s
.devaddr
= pipe
->device_addr
;
1885 usbc_hcchar
.s
.eptype
= transaction
->type
;
1886 usbc_hcchar
.s
.lspddev
= (pipe
->device_speed
== CVMX_USB_SPEED_LOW
);
1887 usbc_hcchar
.s
.epdir
= pipe
->transfer_dir
;
1888 usbc_hcchar
.s
.epnum
= pipe
->endpoint_num
;
1889 usbc_hcchar
.s
.mps
= pipe
->max_packet
;
1890 __cvmx_usb_write_csr32(usb
, CVMX_USBCX_HCCHARX(channel
, usb
->index
), usbc_hcchar
.u32
);
1893 /* Do transaction type specific fixups as needed */
1894 switch (transaction
->type
) {
1895 case CVMX_USB_TRANSFER_CONTROL
:
1896 __cvmx_usb_start_channel_control(usb
, channel
, pipe
);
1898 case CVMX_USB_TRANSFER_BULK
:
1899 case CVMX_USB_TRANSFER_INTERRUPT
:
1901 case CVMX_USB_TRANSFER_ISOCHRONOUS
:
1902 if (!__cvmx_usb_pipe_needs_split(usb
, pipe
)) {
1904 * ISO transactions require different PIDs depending on
1905 * direction and how many packets are needed
1907 if (pipe
->transfer_dir
== CVMX_USB_DIRECTION_OUT
) {
1908 if (pipe
->multi_count
< 2) /* Need DATA0 */
1909 USB_SET_FIELD32(CVMX_USBCX_HCTSIZX(channel
, usb
->index
), union cvmx_usbcx_hctsizx
, pid
, 0);
1910 else /* Need MDATA */
1911 USB_SET_FIELD32(CVMX_USBCX_HCTSIZX(channel
, usb
->index
), union cvmx_usbcx_hctsizx
, pid
, 3);
1917 union cvmx_usbcx_hctsizx usbc_hctsiz
= {.u32
= __cvmx_usb_read_csr32(usb
, CVMX_USBCX_HCTSIZX(channel
, usb
->index
))};
1918 transaction
->xfersize
= usbc_hctsiz
.s
.xfersize
;
1919 transaction
->pktcnt
= usbc_hctsiz
.s
.pktcnt
;
1921 /* Remeber when we start a split transaction */
1922 if (__cvmx_usb_pipe_needs_split(usb
, pipe
))
1923 usb
->active_split
= transaction
;
1924 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel
, usb
->index
), union cvmx_usbcx_hccharx
, chena
, 1);
1925 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)
1926 __cvmx_usb_fill_tx_fifo(usb
, channel
);
1932 * Find a pipe that is ready to be scheduled to hardware.
1933 * @usb: USB device state populated by cvmx_usb_initialize().
1934 * @list: Pipe list to search
1936 * Frame counter to use as a time reference.
1938 * Returns: Pipe or NULL if none are ready
1940 static struct cvmx_usb_pipe
*__cvmx_usb_find_ready_pipe(struct cvmx_usb_state
*usb
, struct cvmx_usb_pipe_list
*list
, uint64_t current_frame
)
1942 struct cvmx_usb_pipe
*pipe
= list
->head
;
1944 if (!(pipe
->flags
& __CVMX_USB_PIPE_FLAGS_SCHEDULED
) && pipe
->head
&&
1945 (pipe
->next_tx_frame
<= current_frame
) &&
1946 ((pipe
->split_sc_frame
== -1) || ((((int)current_frame
- (int)pipe
->split_sc_frame
) & 0x7f) < 0x40)) &&
1947 (!usb
->active_split
|| (usb
->active_split
== pipe
->head
))) {
1948 CVMX_PREFETCH(pipe
, 128);
1949 CVMX_PREFETCH(pipe
->head
, 0);
1959 * Called whenever a pipe might need to be scheduled to the
1962 * @usb: USB device state populated by cvmx_usb_initialize().
1963 * @is_sof: True if this schedule was called on a SOF interrupt.
1965 static void __cvmx_usb_schedule(struct cvmx_usb_state
*usb
, int is_sof
)
1968 struct cvmx_usb_pipe
*pipe
;
1970 enum cvmx_usb_transfer ttype
;
1972 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
) {
1974 * Without DMA we need to be careful to not schedule something
1975 * at the end of a frame and cause an overrun.
1977 union cvmx_usbcx_hfnum hfnum
= {.u32
= __cvmx_usb_read_csr32(usb
, CVMX_USBCX_HFNUM(usb
->index
))};
1978 union cvmx_usbcx_hfir hfir
= {.u32
= __cvmx_usb_read_csr32(usb
, CVMX_USBCX_HFIR(usb
->index
))};
1979 if (hfnum
.s
.frrem
< hfir
.s
.frint
/4)
1983 while (usb
->idle_hardware_channels
) {
1984 /* Find an idle channel */
1985 channel
= __fls(usb
->idle_hardware_channels
);
1986 if (unlikely(channel
> 7))
1989 /* Find a pipe needing service */
1993 * Only process periodic pipes on SOF interrupts. This
1994 * way we are sure that the periodic data is sent in the
1995 * beginning of the frame
1997 pipe
= __cvmx_usb_find_ready_pipe(usb
, usb
->active_pipes
+ CVMX_USB_TRANSFER_ISOCHRONOUS
, usb
->frame_number
);
1999 pipe
= __cvmx_usb_find_ready_pipe(usb
, usb
->active_pipes
+ CVMX_USB_TRANSFER_INTERRUPT
, usb
->frame_number
);
2001 if (likely(!pipe
)) {
2002 pipe
= __cvmx_usb_find_ready_pipe(usb
, usb
->active_pipes
+ CVMX_USB_TRANSFER_CONTROL
, usb
->frame_number
);
2004 pipe
= __cvmx_usb_find_ready_pipe(usb
, usb
->active_pipes
+ CVMX_USB_TRANSFER_BULK
, usb
->frame_number
);
2009 __cvmx_usb_start_channel(usb
, channel
, pipe
);
2014 * Only enable SOF interrupts when we have transactions pending in the
2015 * future that might need to be scheduled
2018 for (ttype
= CVMX_USB_TRANSFER_CONTROL
; ttype
<= CVMX_USB_TRANSFER_INTERRUPT
; ttype
++) {
2019 pipe
= usb
->active_pipes
[ttype
].head
;
2021 if (pipe
->next_tx_frame
> usb
->frame_number
) {
2028 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb
->index
), union cvmx_usbcx_gintmsk
, sofmsk
, need_sof
);
2032 static inline struct octeon_hcd
*cvmx_usb_to_octeon(struct cvmx_usb_state
*p
)
2034 return container_of(p
, struct octeon_hcd
, usb
);
2037 static inline struct usb_hcd
*octeon_to_hcd(struct octeon_hcd
*p
)
2039 return container_of((void *)p
, struct usb_hcd
, hcd_priv
);
2042 static void octeon_usb_urb_complete_callback(struct cvmx_usb_state
*usb
,
2043 enum cvmx_usb_complete status
,
2044 struct cvmx_usb_pipe
*pipe
,
2045 struct cvmx_usb_transaction
2047 int bytes_transferred
,
2050 struct octeon_hcd
*priv
= cvmx_usb_to_octeon(usb
);
2051 struct usb_hcd
*hcd
= octeon_to_hcd(priv
);
2052 struct device
*dev
= hcd
->self
.controller
;
2054 urb
->actual_length
= bytes_transferred
;
2057 if (!list_empty(&urb
->urb_list
)) {
2059 * It is on the dequeue_list, but we are going to call
2060 * usb_hcd_giveback_urb(), so we must clear it from
2061 * the list. We got to it before the
2062 * octeon_usb_urb_dequeue_work() tasklet did.
2064 list_del(&urb
->urb_list
);
2065 /* No longer on the dequeue_list. */
2066 INIT_LIST_HEAD(&urb
->urb_list
);
2069 /* For Isochronous transactions we need to update the URB packet status
2070 list from data in our private copy */
2071 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
2074 * The pointer to the private list is stored in the setup_packet
2077 struct cvmx_usb_iso_packet
*iso_packet
=
2078 (struct cvmx_usb_iso_packet
*) urb
->setup_packet
;
2079 /* Recalculate the transfer size by adding up each packet */
2080 urb
->actual_length
= 0;
2081 for (i
= 0; i
< urb
->number_of_packets
; i
++) {
2082 if (iso_packet
[i
].status
== CVMX_USB_COMPLETE_SUCCESS
) {
2083 urb
->iso_frame_desc
[i
].status
= 0;
2084 urb
->iso_frame_desc
[i
].actual_length
= iso_packet
[i
].length
;
2085 urb
->actual_length
+= urb
->iso_frame_desc
[i
].actual_length
;
2087 dev_dbg(dev
, "ISOCHRONOUS packet=%d of %d status=%d pipe=%p transaction=%p size=%d\n",
2088 i
, urb
->number_of_packets
,
2089 iso_packet
[i
].status
, pipe
,
2090 transaction
, iso_packet
[i
].length
);
2091 urb
->iso_frame_desc
[i
].status
= -EREMOTEIO
;
2094 /* Free the private list now that we don't need it anymore */
2096 urb
->setup_packet
= NULL
;
2100 case CVMX_USB_COMPLETE_SUCCESS
:
2103 case CVMX_USB_COMPLETE_CANCEL
:
2104 if (urb
->status
== 0)
2105 urb
->status
= -ENOENT
;
2107 case CVMX_USB_COMPLETE_STALL
:
2108 dev_dbg(dev
, "status=stall pipe=%p transaction=%p size=%d\n",
2109 pipe
, transaction
, bytes_transferred
);
2110 urb
->status
= -EPIPE
;
2112 case CVMX_USB_COMPLETE_BABBLEERR
:
2113 dev_dbg(dev
, "status=babble pipe=%p transaction=%p size=%d\n",
2114 pipe
, transaction
, bytes_transferred
);
2115 urb
->status
= -EPIPE
;
2117 case CVMX_USB_COMPLETE_SHORT
:
2118 dev_dbg(dev
, "status=short pipe=%p transaction=%p size=%d\n",
2119 pipe
, transaction
, bytes_transferred
);
2120 urb
->status
= -EREMOTEIO
;
2122 case CVMX_USB_COMPLETE_ERROR
:
2123 case CVMX_USB_COMPLETE_XACTERR
:
2124 case CVMX_USB_COMPLETE_DATATGLERR
:
2125 case CVMX_USB_COMPLETE_FRAMEERR
:
2126 dev_dbg(dev
, "status=%d pipe=%p transaction=%p size=%d\n",
2127 status
, pipe
, transaction
, bytes_transferred
);
2128 urb
->status
= -EPROTO
;
2131 spin_unlock(&priv
->lock
);
2132 usb_hcd_giveback_urb(octeon_to_hcd(priv
), urb
, urb
->status
);
2133 spin_lock(&priv
->lock
);
2137 * Signal the completion of a transaction and free it. The
2138 * transaction will be removed from the pipe transaction list.
2140 * @usb: USB device state populated by cvmx_usb_initialize().
2141 * @pipe: Pipe the transaction is on
2143 * Transaction that completed
2147 static void __cvmx_usb_perform_complete(struct cvmx_usb_state
*usb
,
2148 struct cvmx_usb_pipe
*pipe
,
2149 struct cvmx_usb_transaction
*transaction
,
2150 enum cvmx_usb_complete complete_code
)
2152 /* If this was a split then clear our split in progress marker */
2153 if (usb
->active_split
== transaction
)
2154 usb
->active_split
= NULL
;
2157 * Isochronous transactions need extra processing as they might not be
2158 * done after a single data transfer
2160 if (unlikely(transaction
->type
== CVMX_USB_TRANSFER_ISOCHRONOUS
)) {
2161 /* Update the number of bytes transferred in this ISO packet */
2162 transaction
->iso_packets
[0].length
= transaction
->actual_bytes
;
2163 transaction
->iso_packets
[0].status
= complete_code
;
2166 * If there are more ISOs pending and we succeeded, schedule the
2169 if ((transaction
->iso_number_packets
> 1) && (complete_code
== CVMX_USB_COMPLETE_SUCCESS
)) {
2170 /* No bytes transferred for this packet as of yet */
2171 transaction
->actual_bytes
= 0;
2172 /* One less ISO waiting to transfer */
2173 transaction
->iso_number_packets
--;
2174 /* Increment to the next location in our packet array */
2175 transaction
->iso_packets
++;
2176 transaction
->stage
= CVMX_USB_STAGE_NON_CONTROL
;
2181 /* Remove the transaction from the pipe list */
2182 if (transaction
->next
)
2183 transaction
->next
->prev
= transaction
->prev
;
2185 pipe
->tail
= transaction
->prev
;
2186 if (transaction
->prev
)
2187 transaction
->prev
->next
= transaction
->next
;
2189 pipe
->head
= transaction
->next
;
2191 __cvmx_usb_remove_pipe(usb
->active_pipes
+ pipe
->transfer_type
, pipe
);
2192 __cvmx_usb_append_pipe(&usb
->idle_pipes
, pipe
);
2195 octeon_usb_urb_complete_callback(usb
, complete_code
, pipe
,
2197 transaction
->actual_bytes
,
2206 * Submit a usb transaction to a pipe. Called for all types
2210 * @pipe: Which pipe to submit to.
2211 * @type: Transaction type
2212 * @buffer: User buffer for the transaction
2214 * User buffer's length in bytes
2216 * For control transactions, the 8 byte standard header
2218 * For ISO transactions, the start frame
2219 * @iso_number_packets:
2220 * For ISO, the number of packet in the transaction.
2222 * A description of each ISO packet
2223 * @urb: URB for the callback
2225 * Returns: Transaction or NULL on failure.
2227 static struct cvmx_usb_transaction
*__cvmx_usb_submit_transaction(struct cvmx_usb_state
*usb
,
2228 struct cvmx_usb_pipe
*pipe
,
2229 enum cvmx_usb_transfer type
,
2232 uint64_t control_header
,
2233 int iso_start_frame
,
2234 int iso_number_packets
,
2235 struct cvmx_usb_iso_packet
*iso_packets
,
2238 struct cvmx_usb_transaction
*transaction
;
2240 /* Fail if the pipe isn't open */
2241 if (unlikely((pipe
->flags
& __CVMX_USB_PIPE_FLAGS_OPEN
) == 0))
2243 if (unlikely(pipe
->transfer_type
!= type
))
2246 transaction
= kzalloc(sizeof(*transaction
), GFP_ATOMIC
);
2247 if (unlikely(!transaction
))
2250 transaction
->type
= type
;
2251 transaction
->buffer
= buffer
;
2252 transaction
->buffer_length
= buffer_length
;
2253 transaction
->control_header
= control_header
;
2254 /* FIXME: This is not used, implement it. */
2255 transaction
->iso_start_frame
= iso_start_frame
;
2256 transaction
->iso_number_packets
= iso_number_packets
;
2257 transaction
->iso_packets
= iso_packets
;
2258 transaction
->urb
= urb
;
2259 if (transaction
->type
== CVMX_USB_TRANSFER_CONTROL
)
2260 transaction
->stage
= CVMX_USB_STAGE_SETUP
;
2262 transaction
->stage
= CVMX_USB_STAGE_NON_CONTROL
;
2264 transaction
->next
= NULL
;
2266 transaction
->prev
= pipe
->tail
;
2267 transaction
->prev
->next
= transaction
;
2269 if (pipe
->next_tx_frame
< usb
->frame_number
)
2270 pipe
->next_tx_frame
= usb
->frame_number
+ pipe
->interval
-
2271 (usb
->frame_number
- pipe
->next_tx_frame
) % pipe
->interval
;
2272 transaction
->prev
= NULL
;
2273 pipe
->head
= transaction
;
2274 __cvmx_usb_remove_pipe(&usb
->idle_pipes
, pipe
);
2275 __cvmx_usb_append_pipe(usb
->active_pipes
+ pipe
->transfer_type
, pipe
);
2277 pipe
->tail
= transaction
;
2279 /* We may need to schedule the pipe if this was the head of the pipe */
2280 if (!transaction
->prev
)
2281 __cvmx_usb_schedule(usb
, 0);
2288 * Call to submit a USB Bulk transfer to a pipe.
2290 * @usb: USB device state populated by cvmx_usb_initialize().
2291 * @pipe: Handle to the pipe for the transfer.
2294 * Returns: A submitted transaction or NULL on failure.
2296 static struct cvmx_usb_transaction
*cvmx_usb_submit_bulk(struct cvmx_usb_state
*usb
,
2297 struct cvmx_usb_pipe
*pipe
,
2300 return __cvmx_usb_submit_transaction(usb
, pipe
, CVMX_USB_TRANSFER_BULK
,
2302 urb
->transfer_buffer_length
,
2303 0, /* control_header */
2304 0, /* iso_start_frame */
2305 0, /* iso_number_packets */
2306 NULL
, /* iso_packets */
2312 * Call to submit a USB Interrupt transfer to a pipe.
2314 * @usb: USB device state populated by cvmx_usb_initialize().
2315 * @pipe: Handle to the pipe for the transfer.
2316 * @urb: URB returned when the callback is called.
2318 * Returns: A submitted transaction or NULL on failure.
2320 static struct cvmx_usb_transaction
*cvmx_usb_submit_interrupt(struct cvmx_usb_state
*usb
,
2321 struct cvmx_usb_pipe
*pipe
,
2324 return __cvmx_usb_submit_transaction(usb
, pipe
,
2325 CVMX_USB_TRANSFER_INTERRUPT
,
2327 urb
->transfer_buffer_length
,
2328 0, /* control_header */
2329 0, /* iso_start_frame */
2330 0, /* iso_number_packets */
2331 NULL
, /* iso_packets */
2337 * Call to submit a USB Control transfer to a pipe.
2339 * @usb: USB device state populated by cvmx_usb_initialize().
2340 * @pipe: Handle to the pipe for the transfer.
2343 * Returns: A submitted transaction or NULL on failure.
2345 static struct cvmx_usb_transaction
*cvmx_usb_submit_control(struct cvmx_usb_state
*usb
,
2346 struct cvmx_usb_pipe
*pipe
,
2349 int buffer_length
= urb
->transfer_buffer_length
;
2350 uint64_t control_header
= urb
->setup_dma
;
2351 union cvmx_usb_control_header
*header
=
2352 cvmx_phys_to_ptr(control_header
);
2354 if ((header
->s
.request_type
& 0x80) == 0)
2355 buffer_length
= le16_to_cpu(header
->s
.length
);
2357 return __cvmx_usb_submit_transaction(usb
, pipe
,
2358 CVMX_USB_TRANSFER_CONTROL
,
2359 urb
->transfer_dma
, buffer_length
,
2361 0, /* iso_start_frame */
2362 0, /* iso_number_packets */
2363 NULL
, /* iso_packets */
2369 * Call to submit a USB Isochronous transfer to a pipe.
2371 * @usb: USB device state populated by cvmx_usb_initialize().
2372 * @pipe: Handle to the pipe for the transfer.
2373 * @urb: URB returned when the callback is called.
2375 * Returns: A submitted transaction or NULL on failure.
2377 static struct cvmx_usb_transaction
*cvmx_usb_submit_isochronous(struct cvmx_usb_state
*usb
,
2378 struct cvmx_usb_pipe
*pipe
,
2381 struct cvmx_usb_iso_packet
*packets
;
2383 packets
= (struct cvmx_usb_iso_packet
*) urb
->setup_packet
;
2384 return __cvmx_usb_submit_transaction(usb
, pipe
,
2385 CVMX_USB_TRANSFER_ISOCHRONOUS
,
2387 urb
->transfer_buffer_length
,
2388 0, /* control_header */
2390 urb
->number_of_packets
,
2396 * Cancel one outstanding request in a pipe. Canceling a request
2397 * can fail if the transaction has already completed before cancel
2398 * is called. Even after a successful cancel call, it may take
2399 * a frame or two for the cvmx_usb_poll() function to call the
2400 * associated callback.
2402 * @usb: USB device state populated by cvmx_usb_initialize().
2403 * @pipe: Pipe to cancel requests in.
2404 * @transaction: Transaction to cancel, returned by the submit function.
2406 * Returns: 0 or a negative error code.
2408 static int cvmx_usb_cancel(struct cvmx_usb_state
*usb
,
2409 struct cvmx_usb_pipe
*pipe
,
2410 struct cvmx_usb_transaction
*transaction
)
2412 /* Fail if the pipe isn't open */
2413 if (unlikely((pipe
->flags
& __CVMX_USB_PIPE_FLAGS_OPEN
) == 0))
2417 * If the transaction is the HEAD of the queue and scheduled. We need to
2420 if ((pipe
->head
== transaction
) &&
2421 (pipe
->flags
& __CVMX_USB_PIPE_FLAGS_SCHEDULED
)) {
2422 union cvmx_usbcx_hccharx usbc_hcchar
;
2424 usb
->pipe_for_channel
[pipe
->channel
] = NULL
;
2425 pipe
->flags
&= ~__CVMX_USB_PIPE_FLAGS_SCHEDULED
;
2429 usbc_hcchar
.u32
= __cvmx_usb_read_csr32(usb
, CVMX_USBCX_HCCHARX(pipe
->channel
, usb
->index
));
2431 * If the channel isn't enabled then the transaction already
2434 if (usbc_hcchar
.s
.chena
) {
2435 usbc_hcchar
.s
.chdis
= 1;
2436 __cvmx_usb_write_csr32(usb
, CVMX_USBCX_HCCHARX(pipe
->channel
, usb
->index
), usbc_hcchar
.u32
);
2439 __cvmx_usb_perform_complete(usb
, pipe
, transaction
, CVMX_USB_COMPLETE_CANCEL
);
2445 * Cancel all outstanding requests in a pipe. Logically all this
2446 * does is call cvmx_usb_cancel() in a loop.
2448 * @usb: USB device state populated by cvmx_usb_initialize().
2449 * @pipe: Pipe to cancel requests in.
2451 * Returns: 0 or a negative error code.
2453 static int cvmx_usb_cancel_all(struct cvmx_usb_state
*usb
,
2454 struct cvmx_usb_pipe
*pipe
)
2456 /* Fail if the pipe isn't open */
2457 if (unlikely((pipe
->flags
& __CVMX_USB_PIPE_FLAGS_OPEN
) == 0))
2460 /* Simply loop through and attempt to cancel each transaction */
2461 while (pipe
->head
) {
2462 int result
= cvmx_usb_cancel(usb
, pipe
, pipe
->head
);
2463 if (unlikely(result
!= 0))
2471 * Close a pipe created with cvmx_usb_open_pipe().
2473 * @usb: USB device state populated by cvmx_usb_initialize().
2474 * @pipe: Pipe to close.
2476 * Returns: 0 or a negative error code. EBUSY is returned if the pipe has
2477 * outstanding transfers.
2479 static int cvmx_usb_close_pipe(struct cvmx_usb_state
*usb
,
2480 struct cvmx_usb_pipe
*pipe
)
2482 /* Fail if the pipe isn't open */
2483 if (unlikely((pipe
->flags
& __CVMX_USB_PIPE_FLAGS_OPEN
) == 0))
2486 /* Fail if the pipe has pending transactions */
2487 if (unlikely(pipe
->head
))
2491 __cvmx_usb_remove_pipe(&usb
->idle_pipes
, pipe
);
2492 __cvmx_usb_append_pipe(&usb
->free_pipes
, pipe
);
2498 * Get the current USB protocol level frame number. The frame
2499 * number is always in the range of 0-0x7ff.
2501 * @usb: USB device state populated by cvmx_usb_initialize().
2503 * Returns: USB frame number
2505 static int cvmx_usb_get_frame_number(struct cvmx_usb_state
*usb
)
2508 union cvmx_usbcx_hfnum usbc_hfnum
;
2510 usbc_hfnum
.u32
= __cvmx_usb_read_csr32(usb
, CVMX_USBCX_HFNUM(usb
->index
));
2511 frame_number
= usbc_hfnum
.s
.frnum
;
2513 return frame_number
;
2518 * Poll a channel for status
2521 * @channel: Channel to poll
2523 * Returns: Zero on success
2525 static int __cvmx_usb_poll_channel(struct cvmx_usb_state
*usb
, int channel
)
2527 union cvmx_usbcx_hcintx usbc_hcint
;
2528 union cvmx_usbcx_hctsizx usbc_hctsiz
;
2529 union cvmx_usbcx_hccharx usbc_hcchar
;
2530 struct cvmx_usb_pipe
*pipe
;
2531 struct cvmx_usb_transaction
*transaction
;
2532 int bytes_this_transfer
;
2533 int bytes_in_last_packet
;
2534 int packets_processed
;
2535 int buffer_space_left
;
2537 /* Read the interrupt status bits for the channel */
2538 usbc_hcint
.u32
= __cvmx_usb_read_csr32(usb
, CVMX_USBCX_HCINTX(channel
, usb
->index
));
2540 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
) {
2541 usbc_hcchar
.u32
= __cvmx_usb_read_csr32(usb
, CVMX_USBCX_HCCHARX(channel
, usb
->index
));
2543 if (usbc_hcchar
.s
.chena
&& usbc_hcchar
.s
.chdis
) {
2545 * There seems to be a bug in CN31XX which can cause
2546 * interrupt IN transfers to get stuck until we do a
2547 * write of HCCHARX without changing things
2549 __cvmx_usb_write_csr32(usb
, CVMX_USBCX_HCCHARX(channel
, usb
->index
), usbc_hcchar
.u32
);
2554 * In non DMA mode the channels don't halt themselves. We need
2555 * to manually disable channels that are left running
2557 if (!usbc_hcint
.s
.chhltd
) {
2558 if (usbc_hcchar
.s
.chena
) {
2559 union cvmx_usbcx_hcintmskx hcintmsk
;
2560 /* Disable all interrupts except CHHLTD */
2562 hcintmsk
.s
.chhltdmsk
= 1;
2563 __cvmx_usb_write_csr32(usb
, CVMX_USBCX_HCINTMSKX(channel
, usb
->index
), hcintmsk
.u32
);
2564 usbc_hcchar
.s
.chdis
= 1;
2565 __cvmx_usb_write_csr32(usb
, CVMX_USBCX_HCCHARX(channel
, usb
->index
), usbc_hcchar
.u32
);
2567 } else if (usbc_hcint
.s
.xfercompl
) {
2569 * Successful IN/OUT with transfer complete.
2570 * Channel halt isn't needed.
2573 cvmx_dprintf("USB%d: Channel %d interrupt without halt\n", usb
->index
, channel
);
2579 * There is are no interrupts that we need to process when the
2580 * channel is still running
2582 if (!usbc_hcint
.s
.chhltd
)
2586 /* Disable the channel interrupts now that it is done */
2587 __cvmx_usb_write_csr32(usb
, CVMX_USBCX_HCINTMSKX(channel
, usb
->index
), 0);
2588 usb
->idle_hardware_channels
|= (1<<channel
);
2590 /* Make sure this channel is tied to a valid pipe */
2591 pipe
= usb
->pipe_for_channel
[channel
];
2592 CVMX_PREFETCH(pipe
, 0);
2593 CVMX_PREFETCH(pipe
, 128);
2596 transaction
= pipe
->head
;
2597 CVMX_PREFETCH(transaction
, 0);
2600 * Disconnect this pipe from the HW channel. Later the schedule
2601 * function will figure out which pipe needs to go
2603 usb
->pipe_for_channel
[channel
] = NULL
;
2604 pipe
->flags
&= ~__CVMX_USB_PIPE_FLAGS_SCHEDULED
;
2607 * Read the channel config info so we can figure out how much data
2610 usbc_hcchar
.u32
= __cvmx_usb_read_csr32(usb
, CVMX_USBCX_HCCHARX(channel
, usb
->index
));
2611 usbc_hctsiz
.u32
= __cvmx_usb_read_csr32(usb
, CVMX_USBCX_HCTSIZX(channel
, usb
->index
));
2614 * Calculating the number of bytes successfully transferred is dependent
2615 * on the transfer direction
2617 packets_processed
= transaction
->pktcnt
- usbc_hctsiz
.s
.pktcnt
;
2618 if (usbc_hcchar
.s
.epdir
) {
2620 * IN transactions are easy. For every byte received the
2621 * hardware decrements xfersize. All we need to do is subtract
2622 * the current value of xfersize from its starting value and we
2623 * know how many bytes were written to the buffer
2625 bytes_this_transfer
= transaction
->xfersize
- usbc_hctsiz
.s
.xfersize
;
2628 * OUT transaction don't decrement xfersize. Instead pktcnt is
2629 * decremented on every successful packet send. The hardware
2630 * does this when it receives an ACK, or NYET. If it doesn't
2631 * receive one of these responses pktcnt doesn't change
2633 bytes_this_transfer
= packets_processed
* usbc_hcchar
.s
.mps
;
2635 * The last packet may not be a full transfer if we didn't have
2638 if (bytes_this_transfer
> transaction
->xfersize
)
2639 bytes_this_transfer
= transaction
->xfersize
;
2641 /* Figure out how many bytes were in the last packet of the transfer */
2642 if (packets_processed
)
2643 bytes_in_last_packet
= bytes_this_transfer
- (packets_processed
-1) * usbc_hcchar
.s
.mps
;
2645 bytes_in_last_packet
= bytes_this_transfer
;
2648 * As a special case, setup transactions output the setup header, not
2649 * the user's data. For this reason we don't count setup data as bytes
2652 if ((transaction
->stage
== CVMX_USB_STAGE_SETUP
) ||
2653 (transaction
->stage
== CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE
))
2654 bytes_this_transfer
= 0;
2657 * Add the bytes transferred to the running total. It is important that
2658 * bytes_this_transfer doesn't count any data that needs to be
2661 transaction
->actual_bytes
+= bytes_this_transfer
;
2662 if (transaction
->type
== CVMX_USB_TRANSFER_ISOCHRONOUS
)
2663 buffer_space_left
= transaction
->iso_packets
[0].length
- transaction
->actual_bytes
;
2665 buffer_space_left
= transaction
->buffer_length
- transaction
->actual_bytes
;
2668 * We need to remember the PID toggle state for the next transaction.
2669 * The hardware already updated it for the next transaction
2671 pipe
->pid_toggle
= !(usbc_hctsiz
.s
.pid
== 0);
2674 * For high speed bulk out, assume the next transaction will need to do
2675 * a ping before proceeding. If this isn't true the ACK processing below
2676 * will clear this flag
2678 if ((pipe
->device_speed
== CVMX_USB_SPEED_HIGH
) &&
2679 (pipe
->transfer_type
== CVMX_USB_TRANSFER_BULK
) &&
2680 (pipe
->transfer_dir
== CVMX_USB_DIRECTION_OUT
))
2681 pipe
->flags
|= __CVMX_USB_PIPE_FLAGS_NEED_PING
;
2683 if (usbc_hcint
.s
.stall
) {
2685 * STALL as a response means this transaction cannot be
2686 * completed because the device can't process transactions. Tell
2687 * the user. Any data that was transferred will be counted on
2688 * the actual bytes transferred
2690 pipe
->pid_toggle
= 0;
2691 __cvmx_usb_perform_complete(usb
, pipe
, transaction
, CVMX_USB_COMPLETE_STALL
);
2692 } else if (usbc_hcint
.s
.xacterr
) {
2694 * We know at least one packet worked if we get a ACK or NAK.
2695 * Reset the retry counter
2697 if (usbc_hcint
.s
.nak
|| usbc_hcint
.s
.ack
)
2698 transaction
->retries
= 0;
2699 transaction
->retries
++;
2700 if (transaction
->retries
> MAX_RETRIES
) {
2702 * XactErr as a response means the device signaled
2703 * something wrong with the transfer. For example, PID
2704 * toggle errors cause these
2706 __cvmx_usb_perform_complete(usb
, pipe
, transaction
, CVMX_USB_COMPLETE_XACTERR
);
2709 * If this was a split then clear our split in progress
2712 if (usb
->active_split
== transaction
)
2713 usb
->active_split
= NULL
;
2715 * Rewind to the beginning of the transaction by anding
2716 * off the split complete bit
2718 transaction
->stage
&= ~1;
2719 pipe
->split_sc_frame
= -1;
2720 pipe
->next_tx_frame
+= pipe
->interval
;
2721 if (pipe
->next_tx_frame
< usb
->frame_number
)
2722 pipe
->next_tx_frame
= usb
->frame_number
+ pipe
->interval
-
2723 (usb
->frame_number
- pipe
->next_tx_frame
) % pipe
->interval
;
2725 } else if (usbc_hcint
.s
.bblerr
) {
2726 /* Babble Error (BblErr) */
2727 __cvmx_usb_perform_complete(usb
, pipe
, transaction
, CVMX_USB_COMPLETE_BABBLEERR
);
2728 } else if (usbc_hcint
.s
.datatglerr
) {
2729 /* We'll retry the exact same transaction again */
2730 transaction
->retries
++;
2731 } else if (usbc_hcint
.s
.nyet
) {
2733 * NYET as a response is only allowed in three cases: as a
2734 * response to a ping, as a response to a split transaction, and
2735 * as a response to a bulk out. The ping case is handled by
2736 * hardware, so we only have splits and bulk out
2738 if (!__cvmx_usb_pipe_needs_split(usb
, pipe
)) {
2739 transaction
->retries
= 0;
2741 * If there is more data to go then we need to try
2742 * again. Otherwise this transaction is complete
2744 if ((buffer_space_left
== 0) || (bytes_in_last_packet
< pipe
->max_packet
))
2745 __cvmx_usb_perform_complete(usb
, pipe
, transaction
, CVMX_USB_COMPLETE_SUCCESS
);
2748 * Split transactions retry the split complete 4 times
2749 * then rewind to the start split and do the entire
2750 * transactions again
2752 transaction
->retries
++;
2753 if ((transaction
->retries
& 0x3) == 0) {
2755 * Rewind to the beginning of the transaction by
2756 * anding off the split complete bit
2758 transaction
->stage
&= ~1;
2759 pipe
->split_sc_frame
= -1;
2762 } else if (usbc_hcint
.s
.ack
) {
2763 transaction
->retries
= 0;
2765 * The ACK bit can only be checked after the other error bits.
2766 * This is because a multi packet transfer may succeed in a
2767 * number of packets and then get a different response on the
2768 * last packet. In this case both ACK and the last response bit
2769 * will be set. If none of the other response bits is set, then
2770 * the last packet must have been an ACK
2772 * Since we got an ACK, we know we don't need to do a ping on
2775 pipe
->flags
&= ~__CVMX_USB_PIPE_FLAGS_NEED_PING
;
2777 switch (transaction
->type
) {
2778 case CVMX_USB_TRANSFER_CONTROL
:
2779 switch (transaction
->stage
) {
2780 case CVMX_USB_STAGE_NON_CONTROL
:
2781 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
:
2782 /* This should be impossible */
2783 __cvmx_usb_perform_complete(usb
, pipe
, transaction
, CVMX_USB_COMPLETE_ERROR
);
2785 case CVMX_USB_STAGE_SETUP
:
2786 pipe
->pid_toggle
= 1;
2787 if (__cvmx_usb_pipe_needs_split(usb
, pipe
))
2788 transaction
->stage
= CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE
;
2790 union cvmx_usb_control_header
*header
=
2791 cvmx_phys_to_ptr(transaction
->control_header
);
2792 if (header
->s
.length
)
2793 transaction
->stage
= CVMX_USB_STAGE_DATA
;
2795 transaction
->stage
= CVMX_USB_STAGE_STATUS
;
2798 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE
:
2800 union cvmx_usb_control_header
*header
=
2801 cvmx_phys_to_ptr(transaction
->control_header
);
2802 if (header
->s
.length
)
2803 transaction
->stage
= CVMX_USB_STAGE_DATA
;
2805 transaction
->stage
= CVMX_USB_STAGE_STATUS
;
2808 case CVMX_USB_STAGE_DATA
:
2809 if (__cvmx_usb_pipe_needs_split(usb
, pipe
)) {
2810 transaction
->stage
= CVMX_USB_STAGE_DATA_SPLIT_COMPLETE
;
2812 * For setup OUT data that are splits,
2813 * the hardware doesn't appear to count
2814 * transferred data. Here we manually
2815 * update the data transferred
2817 if (!usbc_hcchar
.s
.epdir
) {
2818 if (buffer_space_left
< pipe
->max_packet
)
2819 transaction
->actual_bytes
+= buffer_space_left
;
2821 transaction
->actual_bytes
+= pipe
->max_packet
;
2823 } else if ((buffer_space_left
== 0) || (bytes_in_last_packet
< pipe
->max_packet
)) {
2824 pipe
->pid_toggle
= 1;
2825 transaction
->stage
= CVMX_USB_STAGE_STATUS
;
2828 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE
:
2829 if ((buffer_space_left
== 0) || (bytes_in_last_packet
< pipe
->max_packet
)) {
2830 pipe
->pid_toggle
= 1;
2831 transaction
->stage
= CVMX_USB_STAGE_STATUS
;
2833 transaction
->stage
= CVMX_USB_STAGE_DATA
;
2836 case CVMX_USB_STAGE_STATUS
:
2837 if (__cvmx_usb_pipe_needs_split(usb
, pipe
))
2838 transaction
->stage
= CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE
;
2840 __cvmx_usb_perform_complete(usb
, pipe
, transaction
, CVMX_USB_COMPLETE_SUCCESS
);
2842 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE
:
2843 __cvmx_usb_perform_complete(usb
, pipe
, transaction
, CVMX_USB_COMPLETE_SUCCESS
);
2847 case CVMX_USB_TRANSFER_BULK
:
2848 case CVMX_USB_TRANSFER_INTERRUPT
:
2850 * The only time a bulk transfer isn't complete when it
2851 * finishes with an ACK is during a split transaction.
2852 * For splits we need to continue the transfer if more
2855 if (__cvmx_usb_pipe_needs_split(usb
, pipe
)) {
2856 if (transaction
->stage
== CVMX_USB_STAGE_NON_CONTROL
)
2857 transaction
->stage
= CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
;
2859 if (buffer_space_left
&& (bytes_in_last_packet
== pipe
->max_packet
))
2860 transaction
->stage
= CVMX_USB_STAGE_NON_CONTROL
;
2862 if (transaction
->type
== CVMX_USB_TRANSFER_INTERRUPT
)
2863 pipe
->next_tx_frame
+= pipe
->interval
;
2864 __cvmx_usb_perform_complete(usb
, pipe
, transaction
, CVMX_USB_COMPLETE_SUCCESS
);
2868 if ((pipe
->device_speed
== CVMX_USB_SPEED_HIGH
) &&
2869 (pipe
->transfer_type
== CVMX_USB_TRANSFER_BULK
) &&
2870 (pipe
->transfer_dir
== CVMX_USB_DIRECTION_OUT
) &&
2872 pipe
->flags
|= __CVMX_USB_PIPE_FLAGS_NEED_PING
;
2873 if (!buffer_space_left
|| (bytes_in_last_packet
< pipe
->max_packet
)) {
2874 if (transaction
->type
== CVMX_USB_TRANSFER_INTERRUPT
)
2875 pipe
->next_tx_frame
+= pipe
->interval
;
2876 __cvmx_usb_perform_complete(usb
, pipe
, transaction
, CVMX_USB_COMPLETE_SUCCESS
);
2880 case CVMX_USB_TRANSFER_ISOCHRONOUS
:
2881 if (__cvmx_usb_pipe_needs_split(usb
, pipe
)) {
2883 * ISOCHRONOUS OUT splits don't require a
2884 * complete split stage. Instead they use a
2885 * sequence of begin OUT splits to transfer the
2886 * data 188 bytes at a time. Once the transfer
2887 * is complete, the pipe sleeps until the next
2890 if (pipe
->transfer_dir
== CVMX_USB_DIRECTION_OUT
) {
2892 * If no space left or this wasn't a max
2893 * size packet then this transfer is
2894 * complete. Otherwise start it again to
2895 * send the next 188 bytes
2897 if (!buffer_space_left
|| (bytes_this_transfer
< 188)) {
2898 pipe
->next_tx_frame
+= pipe
->interval
;
2899 __cvmx_usb_perform_complete(usb
, pipe
, transaction
, CVMX_USB_COMPLETE_SUCCESS
);
2902 if (transaction
->stage
== CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
) {
2904 * We are in the incoming data
2905 * phase. Keep getting data
2906 * until we run out of space or
2907 * get a small packet
2909 if ((buffer_space_left
== 0) || (bytes_in_last_packet
< pipe
->max_packet
)) {
2910 pipe
->next_tx_frame
+= pipe
->interval
;
2911 __cvmx_usb_perform_complete(usb
, pipe
, transaction
, CVMX_USB_COMPLETE_SUCCESS
);
2914 transaction
->stage
= CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE
;
2917 pipe
->next_tx_frame
+= pipe
->interval
;
2918 __cvmx_usb_perform_complete(usb
, pipe
, transaction
, CVMX_USB_COMPLETE_SUCCESS
);
2922 } else if (usbc_hcint
.s
.nak
) {
2924 * If this was a split then clear our split in progress marker.
2926 if (usb
->active_split
== transaction
)
2927 usb
->active_split
= NULL
;
2929 * NAK as a response means the device couldn't accept the
2930 * transaction, but it should be retried in the future. Rewind
2931 * to the beginning of the transaction by anding off the split
2932 * complete bit. Retry in the next interval
2934 transaction
->retries
= 0;
2935 transaction
->stage
&= ~1;
2936 pipe
->next_tx_frame
+= pipe
->interval
;
2937 if (pipe
->next_tx_frame
< usb
->frame_number
)
2938 pipe
->next_tx_frame
= usb
->frame_number
+ pipe
->interval
-
2939 (usb
->frame_number
- pipe
->next_tx_frame
) % pipe
->interval
;
2941 struct cvmx_usb_port_status port
;
2942 port
= cvmx_usb_get_status(usb
);
2943 if (port
.port_enabled
) {
2944 /* We'll retry the exact same transaction again */
2945 transaction
->retries
++;
2948 * We get channel halted interrupts with no result bits
2949 * sets when the cable is unplugged
2951 __cvmx_usb_perform_complete(usb
, pipe
, transaction
, CVMX_USB_COMPLETE_ERROR
);
2957 static void octeon_usb_port_callback(struct cvmx_usb_state
*usb
)
2959 struct octeon_hcd
*priv
= cvmx_usb_to_octeon(usb
);
2961 spin_unlock(&priv
->lock
);
2962 usb_hcd_poll_rh_status(octeon_to_hcd(priv
));
2963 spin_lock(&priv
->lock
);
2967 * Poll the USB block for status and call all needed callback
2968 * handlers. This function is meant to be called in the interrupt
2969 * handler for the USB controller. It can also be called
2970 * periodically in a loop for non-interrupt based operation.
2972 * @usb: USB device state populated by cvmx_usb_initialize().
2974 * Returns: 0 or a negative error code.
2976 static int cvmx_usb_poll(struct cvmx_usb_state
*usb
)
2978 union cvmx_usbcx_hfnum usbc_hfnum
;
2979 union cvmx_usbcx_gintsts usbc_gintsts
;
2981 CVMX_PREFETCH(usb
, 0);
2982 CVMX_PREFETCH(usb
, 1*128);
2983 CVMX_PREFETCH(usb
, 2*128);
2984 CVMX_PREFETCH(usb
, 3*128);
2985 CVMX_PREFETCH(usb
, 4*128);
2987 /* Update the frame counter */
2988 usbc_hfnum
.u32
= __cvmx_usb_read_csr32(usb
, CVMX_USBCX_HFNUM(usb
->index
));
2989 if ((usb
->frame_number
&0x3fff) > usbc_hfnum
.s
.frnum
)
2990 usb
->frame_number
+= 0x4000;
2991 usb
->frame_number
&= ~0x3fffull
;
2992 usb
->frame_number
|= usbc_hfnum
.s
.frnum
;
2994 /* Read the pending interrupts */
2995 usbc_gintsts
.u32
= __cvmx_usb_read_csr32(usb
, CVMX_USBCX_GINTSTS(usb
->index
));
2997 /* Clear the interrupts now that we know about them */
2998 __cvmx_usb_write_csr32(usb
, CVMX_USBCX_GINTSTS(usb
->index
), usbc_gintsts
.u32
);
3000 if (usbc_gintsts
.s
.rxflvl
) {
3002 * RxFIFO Non-Empty (RxFLvl)
3003 * Indicates that there is at least one packet pending to be
3004 * read from the RxFIFO.
3006 * In DMA mode this is handled by hardware
3008 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)
3009 __cvmx_usb_poll_rx_fifo(usb
);
3011 if (usbc_gintsts
.s
.ptxfemp
|| usbc_gintsts
.s
.nptxfemp
) {
3012 /* Fill the Tx FIFOs when not in DMA mode */
3013 if (usb
->init_flags
& CVMX_USB_INITIALIZE_FLAGS_NO_DMA
)
3014 __cvmx_usb_poll_tx_fifo(usb
);
3016 if (usbc_gintsts
.s
.disconnint
|| usbc_gintsts
.s
.prtint
) {
3017 union cvmx_usbcx_hprt usbc_hprt
;
3019 * Disconnect Detected Interrupt (DisconnInt)
3020 * Asserted when a device disconnect is detected.
3022 * Host Port Interrupt (PrtInt)
3023 * The core sets this bit to indicate a change in port status of
3024 * one of the O2P USB core ports in Host mode. The application
3025 * must read the Host Port Control and Status (HPRT) register to
3026 * determine the exact event that caused this interrupt. The
3027 * application must clear the appropriate status bit in the Host
3028 * Port Control and Status register to clear this bit.
3030 * Call the user's port callback
3032 octeon_usb_port_callback(usb
);
3033 /* Clear the port change bits */
3034 usbc_hprt
.u32
= __cvmx_usb_read_csr32(usb
, CVMX_USBCX_HPRT(usb
->index
));
3035 usbc_hprt
.s
.prtena
= 0;
3036 __cvmx_usb_write_csr32(usb
, CVMX_USBCX_HPRT(usb
->index
), usbc_hprt
.u32
);
3038 if (usbc_gintsts
.s
.hchint
) {
3040 * Host Channels Interrupt (HChInt)
3041 * The core sets this bit to indicate that an interrupt is
3042 * pending on one of the channels of the core (in Host mode).
3043 * The application must read the Host All Channels Interrupt
3044 * (HAINT) register to determine the exact number of the channel
3045 * on which the interrupt occurred, and then read the
3046 * corresponding Host Channel-n Interrupt (HCINTn) register to
3047 * determine the exact cause of the interrupt. The application
3048 * must clear the appropriate status bit in the HCINTn register
3049 * to clear this bit.
3051 union cvmx_usbcx_haint usbc_haint
;
3052 usbc_haint
.u32
= __cvmx_usb_read_csr32(usb
, CVMX_USBCX_HAINT(usb
->index
));
3053 while (usbc_haint
.u32
) {
3056 channel
= __fls(usbc_haint
.u32
);
3057 __cvmx_usb_poll_channel(usb
, channel
);
3058 usbc_haint
.u32
^= 1<<channel
;
3062 __cvmx_usb_schedule(usb
, usbc_gintsts
.s
.sof
);
3067 /* convert between an HCD pointer and the corresponding struct octeon_hcd */
3068 static inline struct octeon_hcd
*hcd_to_octeon(struct usb_hcd
*hcd
)
3070 return (struct octeon_hcd
*)(hcd
->hcd_priv
);
3073 static irqreturn_t
octeon_usb_irq(struct usb_hcd
*hcd
)
3075 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3076 unsigned long flags
;
3078 spin_lock_irqsave(&priv
->lock
, flags
);
3079 cvmx_usb_poll(&priv
->usb
);
3080 spin_unlock_irqrestore(&priv
->lock
, flags
);
3084 static int octeon_usb_start(struct usb_hcd
*hcd
)
3086 hcd
->state
= HC_STATE_RUNNING
;
3090 static void octeon_usb_stop(struct usb_hcd
*hcd
)
3092 hcd
->state
= HC_STATE_HALT
;
3095 static int octeon_usb_get_frame_number(struct usb_hcd
*hcd
)
3097 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3099 return cvmx_usb_get_frame_number(&priv
->usb
);
3102 static int octeon_usb_urb_enqueue(struct usb_hcd
*hcd
,
3106 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3107 struct device
*dev
= hcd
->self
.controller
;
3108 struct cvmx_usb_transaction
*transaction
= NULL
;
3109 struct cvmx_usb_pipe
*pipe
;
3110 unsigned long flags
;
3111 struct cvmx_usb_iso_packet
*iso_packet
;
3112 struct usb_host_endpoint
*ep
= urb
->ep
;
3115 INIT_LIST_HEAD(&urb
->urb_list
); /* not enqueued on dequeue_list */
3116 spin_lock_irqsave(&priv
->lock
, flags
);
3119 enum cvmx_usb_transfer transfer_type
;
3120 enum cvmx_usb_speed speed
;
3121 int split_device
= 0;
3123 switch (usb_pipetype(urb
->pipe
)) {
3124 case PIPE_ISOCHRONOUS
:
3125 transfer_type
= CVMX_USB_TRANSFER_ISOCHRONOUS
;
3127 case PIPE_INTERRUPT
:
3128 transfer_type
= CVMX_USB_TRANSFER_INTERRUPT
;
3131 transfer_type
= CVMX_USB_TRANSFER_CONTROL
;
3134 transfer_type
= CVMX_USB_TRANSFER_BULK
;
3137 switch (urb
->dev
->speed
) {
3139 speed
= CVMX_USB_SPEED_LOW
;
3141 case USB_SPEED_FULL
:
3142 speed
= CVMX_USB_SPEED_FULL
;
3145 speed
= CVMX_USB_SPEED_HIGH
;
3149 * For slow devices on high speed ports we need to find the hub
3150 * that does the speed translation so we know where to send the
3151 * split transactions.
3153 if (speed
!= CVMX_USB_SPEED_HIGH
) {
3155 * Start at this device and work our way up the usb
3158 struct usb_device
*dev
= urb
->dev
;
3159 while (dev
->parent
) {
3161 * If our parent is high speed then he'll
3162 * receive the splits.
3164 if (dev
->parent
->speed
== USB_SPEED_HIGH
) {
3165 split_device
= dev
->parent
->devnum
;
3166 split_port
= dev
->portnum
;
3170 * Move up the tree one level. If we make it all
3171 * the way up the tree, then the port must not
3172 * be in high speed mode and we don't need a
3178 pipe
= cvmx_usb_open_pipe(&priv
->usb
, usb_pipedevice(urb
->pipe
),
3179 usb_pipeendpoint(urb
->pipe
), speed
,
3180 le16_to_cpu(ep
->desc
.wMaxPacketSize
) & 0x7ff,
3182 usb_pipein(urb
->pipe
) ?
3183 CVMX_USB_DIRECTION_IN
:
3184 CVMX_USB_DIRECTION_OUT
,
3186 (le16_to_cpu(ep
->desc
.wMaxPacketSize
) >> 11) & 0x3,
3187 split_device
, split_port
);
3189 spin_unlock_irqrestore(&priv
->lock
, flags
);
3190 dev_dbg(dev
, "Failed to create pipe\n");
3198 switch (usb_pipetype(urb
->pipe
)) {
3199 case PIPE_ISOCHRONOUS
:
3200 dev_dbg(dev
, "Submit isochronous to %d.%d\n",
3201 usb_pipedevice(urb
->pipe
), usb_pipeendpoint(urb
->pipe
));
3203 * Allocate a structure to use for our private list of
3204 * isochronous packets.
3206 iso_packet
= kmalloc(urb
->number_of_packets
*
3207 sizeof(struct cvmx_usb_iso_packet
),
3211 /* Fill the list with the data from the URB */
3212 for (i
= 0; i
< urb
->number_of_packets
; i
++) {
3213 iso_packet
[i
].offset
= urb
->iso_frame_desc
[i
].offset
;
3214 iso_packet
[i
].length
= urb
->iso_frame_desc
[i
].length
;
3215 iso_packet
[i
].status
= CVMX_USB_COMPLETE_ERROR
;
3218 * Store a pointer to the list in the URB setup_packet
3219 * field. We know this currently isn't being used and
3220 * this saves us a bunch of logic.
3222 urb
->setup_packet
= (char *)iso_packet
;
3223 transaction
= cvmx_usb_submit_isochronous(&priv
->usb
,
3226 * If submit failed we need to free our private packet
3230 urb
->setup_packet
= NULL
;
3235 case PIPE_INTERRUPT
:
3236 dev_dbg(dev
, "Submit interrupt to %d.%d\n",
3237 usb_pipedevice(urb
->pipe
), usb_pipeendpoint(urb
->pipe
));
3238 transaction
= cvmx_usb_submit_interrupt(&priv
->usb
, pipe
, urb
);
3241 dev_dbg(dev
, "Submit control to %d.%d\n",
3242 usb_pipedevice(urb
->pipe
), usb_pipeendpoint(urb
->pipe
));
3243 transaction
= cvmx_usb_submit_control(&priv
->usb
, pipe
, urb
);
3246 dev_dbg(dev
, "Submit bulk to %d.%d\n",
3247 usb_pipedevice(urb
->pipe
), usb_pipeendpoint(urb
->pipe
));
3248 transaction
= cvmx_usb_submit_bulk(&priv
->usb
, pipe
, urb
);
3252 spin_unlock_irqrestore(&priv
->lock
, flags
);
3253 dev_dbg(dev
, "Failed to submit\n");
3256 urb
->hcpriv
= transaction
;
3257 spin_unlock_irqrestore(&priv
->lock
, flags
);
3261 static void octeon_usb_urb_dequeue_work(unsigned long arg
)
3263 unsigned long flags
;
3264 struct octeon_hcd
*priv
= (struct octeon_hcd
*)arg
;
3266 spin_lock_irqsave(&priv
->lock
, flags
);
3268 while (!list_empty(&priv
->dequeue_list
)) {
3269 struct urb
*urb
= container_of(priv
->dequeue_list
.next
, struct urb
, urb_list
);
3270 list_del(&urb
->urb_list
);
3271 /* not enqueued on dequeue_list */
3272 INIT_LIST_HEAD(&urb
->urb_list
);
3273 cvmx_usb_cancel(&priv
->usb
, urb
->ep
->hcpriv
, urb
->hcpriv
);
3276 spin_unlock_irqrestore(&priv
->lock
, flags
);
3279 static int octeon_usb_urb_dequeue(struct usb_hcd
*hcd
, struct urb
*urb
, int status
)
3281 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3282 unsigned long flags
;
3287 spin_lock_irqsave(&priv
->lock
, flags
);
3289 urb
->status
= status
;
3290 list_add_tail(&urb
->urb_list
, &priv
->dequeue_list
);
3292 spin_unlock_irqrestore(&priv
->lock
, flags
);
3294 tasklet_schedule(&priv
->dequeue_tasklet
);
3299 static void octeon_usb_endpoint_disable(struct usb_hcd
*hcd
, struct usb_host_endpoint
*ep
)
3301 struct device
*dev
= hcd
->self
.controller
;
3304 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3305 struct cvmx_usb_pipe
*pipe
= ep
->hcpriv
;
3306 unsigned long flags
;
3307 spin_lock_irqsave(&priv
->lock
, flags
);
3308 cvmx_usb_cancel_all(&priv
->usb
, pipe
);
3309 if (cvmx_usb_close_pipe(&priv
->usb
, pipe
))
3310 dev_dbg(dev
, "Closing pipe %p failed\n", pipe
);
3311 spin_unlock_irqrestore(&priv
->lock
, flags
);
3316 static int octeon_usb_hub_status_data(struct usb_hcd
*hcd
, char *buf
)
3318 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3319 struct cvmx_usb_port_status port_status
;
3320 unsigned long flags
;
3322 spin_lock_irqsave(&priv
->lock
, flags
);
3323 port_status
= cvmx_usb_get_status(&priv
->usb
);
3324 spin_unlock_irqrestore(&priv
->lock
, flags
);
3326 buf
[0] = port_status
.connect_change
<< 1;
3328 return (buf
[0] != 0);
3331 static int octeon_usb_hub_control(struct usb_hcd
*hcd
, u16 typeReq
, u16 wValue
, u16 wIndex
, char *buf
, u16 wLength
)
3333 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3334 struct device
*dev
= hcd
->self
.controller
;
3335 struct cvmx_usb_port_status usb_port_status
;
3337 struct usb_hub_descriptor
*desc
;
3338 unsigned long flags
;
3341 case ClearHubFeature
:
3342 dev_dbg(dev
, "ClearHubFeature\n");
3344 case C_HUB_LOCAL_POWER
:
3345 case C_HUB_OVER_CURRENT
:
3346 /* Nothing required here */
3352 case ClearPortFeature
:
3353 dev_dbg(dev
, "ClearPortFeature\n");
3355 dev_dbg(dev
, " INVALID\n");
3360 case USB_PORT_FEAT_ENABLE
:
3361 dev_dbg(dev
, " ENABLE\n");
3362 spin_lock_irqsave(&priv
->lock
, flags
);
3363 cvmx_usb_disable(&priv
->usb
);
3364 spin_unlock_irqrestore(&priv
->lock
, flags
);
3366 case USB_PORT_FEAT_SUSPEND
:
3367 dev_dbg(dev
, " SUSPEND\n");
3368 /* Not supported on Octeon */
3370 case USB_PORT_FEAT_POWER
:
3371 dev_dbg(dev
, " POWER\n");
3372 /* Not supported on Octeon */
3374 case USB_PORT_FEAT_INDICATOR
:
3375 dev_dbg(dev
, " INDICATOR\n");
3376 /* Port inidicator not supported */
3378 case USB_PORT_FEAT_C_CONNECTION
:
3379 dev_dbg(dev
, " C_CONNECTION\n");
3380 /* Clears drivers internal connect status change flag */
3381 spin_lock_irqsave(&priv
->lock
, flags
);
3382 priv
->usb
.port_status
= cvmx_usb_get_status(&priv
->usb
);
3383 spin_unlock_irqrestore(&priv
->lock
, flags
);
3385 case USB_PORT_FEAT_C_RESET
:
3386 dev_dbg(dev
, " C_RESET\n");
3388 * Clears the driver's internal Port Reset Change flag.
3390 spin_lock_irqsave(&priv
->lock
, flags
);
3391 priv
->usb
.port_status
= cvmx_usb_get_status(&priv
->usb
);
3392 spin_unlock_irqrestore(&priv
->lock
, flags
);
3394 case USB_PORT_FEAT_C_ENABLE
:
3395 dev_dbg(dev
, " C_ENABLE\n");
3397 * Clears the driver's internal Port Enable/Disable
3400 spin_lock_irqsave(&priv
->lock
, flags
);
3401 priv
->usb
.port_status
= cvmx_usb_get_status(&priv
->usb
);
3402 spin_unlock_irqrestore(&priv
->lock
, flags
);
3404 case USB_PORT_FEAT_C_SUSPEND
:
3405 dev_dbg(dev
, " C_SUSPEND\n");
3407 * Clears the driver's internal Port Suspend Change
3408 * flag, which is set when resume signaling on the host
3412 case USB_PORT_FEAT_C_OVER_CURRENT
:
3413 dev_dbg(dev
, " C_OVER_CURRENT\n");
3414 /* Clears the driver's overcurrent Change flag */
3415 spin_lock_irqsave(&priv
->lock
, flags
);
3416 priv
->usb
.port_status
= cvmx_usb_get_status(&priv
->usb
);
3417 spin_unlock_irqrestore(&priv
->lock
, flags
);
3420 dev_dbg(dev
, " UNKNOWN\n");
3424 case GetHubDescriptor
:
3425 dev_dbg(dev
, "GetHubDescriptor\n");
3426 desc
= (struct usb_hub_descriptor
*)buf
;
3427 desc
->bDescLength
= 9;
3428 desc
->bDescriptorType
= 0x29;
3429 desc
->bNbrPorts
= 1;
3430 desc
->wHubCharacteristics
= 0x08;
3431 desc
->bPwrOn2PwrGood
= 1;
3432 desc
->bHubContrCurrent
= 0;
3433 desc
->u
.hs
.DeviceRemovable
[0] = 0;
3434 desc
->u
.hs
.DeviceRemovable
[1] = 0xff;
3437 dev_dbg(dev
, "GetHubStatus\n");
3438 *(__le32
*) buf
= 0;
3441 dev_dbg(dev
, "GetPortStatus\n");
3443 dev_dbg(dev
, " INVALID\n");
3447 spin_lock_irqsave(&priv
->lock
, flags
);
3448 usb_port_status
= cvmx_usb_get_status(&priv
->usb
);
3449 spin_unlock_irqrestore(&priv
->lock
, flags
);
3452 if (usb_port_status
.connect_change
) {
3453 port_status
|= (1 << USB_PORT_FEAT_C_CONNECTION
);
3454 dev_dbg(dev
, " C_CONNECTION\n");
3457 if (usb_port_status
.port_enabled
) {
3458 port_status
|= (1 << USB_PORT_FEAT_C_ENABLE
);
3459 dev_dbg(dev
, " C_ENABLE\n");
3462 if (usb_port_status
.connected
) {
3463 port_status
|= (1 << USB_PORT_FEAT_CONNECTION
);
3464 dev_dbg(dev
, " CONNECTION\n");
3467 if (usb_port_status
.port_enabled
) {
3468 port_status
|= (1 << USB_PORT_FEAT_ENABLE
);
3469 dev_dbg(dev
, " ENABLE\n");
3472 if (usb_port_status
.port_over_current
) {
3473 port_status
|= (1 << USB_PORT_FEAT_OVER_CURRENT
);
3474 dev_dbg(dev
, " OVER_CURRENT\n");
3477 if (usb_port_status
.port_powered
) {
3478 port_status
|= (1 << USB_PORT_FEAT_POWER
);
3479 dev_dbg(dev
, " POWER\n");
3482 if (usb_port_status
.port_speed
== CVMX_USB_SPEED_HIGH
) {
3483 port_status
|= USB_PORT_STAT_HIGH_SPEED
;
3484 dev_dbg(dev
, " HIGHSPEED\n");
3485 } else if (usb_port_status
.port_speed
== CVMX_USB_SPEED_LOW
) {
3486 port_status
|= (1 << USB_PORT_FEAT_LOWSPEED
);
3487 dev_dbg(dev
, " LOWSPEED\n");
3490 *((__le32
*) buf
) = cpu_to_le32(port_status
);
3493 dev_dbg(dev
, "SetHubFeature\n");
3494 /* No HUB features supported */
3496 case SetPortFeature
:
3497 dev_dbg(dev
, "SetPortFeature\n");
3499 dev_dbg(dev
, " INVALID\n");
3504 case USB_PORT_FEAT_SUSPEND
:
3505 dev_dbg(dev
, " SUSPEND\n");
3507 case USB_PORT_FEAT_POWER
:
3508 dev_dbg(dev
, " POWER\n");
3510 case USB_PORT_FEAT_RESET
:
3511 dev_dbg(dev
, " RESET\n");
3512 spin_lock_irqsave(&priv
->lock
, flags
);
3513 cvmx_usb_disable(&priv
->usb
);
3514 if (cvmx_usb_enable(&priv
->usb
))
3515 dev_dbg(dev
, "Failed to enable the port\n");
3516 spin_unlock_irqrestore(&priv
->lock
, flags
);
3518 case USB_PORT_FEAT_INDICATOR
:
3519 dev_dbg(dev
, " INDICATOR\n");
3523 dev_dbg(dev
, " UNKNOWN\n");
3528 dev_dbg(dev
, "Unknown root hub request\n");
3535 static const struct hc_driver octeon_hc_driver
= {
3536 .description
= "Octeon USB",
3537 .product_desc
= "Octeon Host Controller",
3538 .hcd_priv_size
= sizeof(struct octeon_hcd
),
3539 .irq
= octeon_usb_irq
,
3540 .flags
= HCD_MEMORY
| HCD_USB2
,
3541 .start
= octeon_usb_start
,
3542 .stop
= octeon_usb_stop
,
3543 .urb_enqueue
= octeon_usb_urb_enqueue
,
3544 .urb_dequeue
= octeon_usb_urb_dequeue
,
3545 .endpoint_disable
= octeon_usb_endpoint_disable
,
3546 .get_frame_number
= octeon_usb_get_frame_number
,
3547 .hub_status_data
= octeon_usb_hub_status_data
,
3548 .hub_control
= octeon_usb_hub_control
,
3552 static int octeon_usb_driver_probe(struct device
*dev
)
3555 int usb_num
= to_platform_device(dev
)->id
;
3556 int irq
= platform_get_irq(to_platform_device(dev
), 0);
3557 struct octeon_hcd
*priv
;
3558 struct usb_hcd
*hcd
;
3559 unsigned long flags
;
3562 * Set the DMA mask to 64bits so we get buffers already translated for
3565 dev
->coherent_dma_mask
= ~0;
3566 dev
->dma_mask
= &dev
->coherent_dma_mask
;
3568 hcd
= usb_create_hcd(&octeon_hc_driver
, dev
, dev_name(dev
));
3570 dev_dbg(dev
, "Failed to allocate memory for HCD\n");
3573 hcd
->uses_new_polling
= 1;
3574 priv
= (struct octeon_hcd
*)hcd
->hcd_priv
;
3576 spin_lock_init(&priv
->lock
);
3578 tasklet_init(&priv
->dequeue_tasklet
, octeon_usb_urb_dequeue_work
, (unsigned long)priv
);
3579 INIT_LIST_HEAD(&priv
->dequeue_list
);
3581 status
= cvmx_usb_initialize(&priv
->usb
, usb_num
);
3583 dev_dbg(dev
, "USB initialization failed with %d\n", status
);
3588 /* This delay is needed for CN3010, but I don't know why... */
3591 spin_lock_irqsave(&priv
->lock
, flags
);
3592 cvmx_usb_poll(&priv
->usb
);
3593 spin_unlock_irqrestore(&priv
->lock
, flags
);
3595 status
= usb_add_hcd(hcd
, irq
, IRQF_SHARED
);
3597 dev_dbg(dev
, "USB add HCD failed with %d\n", status
);
3602 dev_dbg(dev
, "Registered HCD for port %d on irq %d\n", usb_num
, irq
);
3607 static int octeon_usb_driver_remove(struct device
*dev
)
3610 struct usb_hcd
*hcd
= dev_get_drvdata(dev
);
3611 struct octeon_hcd
*priv
= hcd_to_octeon(hcd
);
3612 unsigned long flags
;
3614 usb_remove_hcd(hcd
);
3615 tasklet_kill(&priv
->dequeue_tasklet
);
3616 spin_lock_irqsave(&priv
->lock
, flags
);
3617 status
= cvmx_usb_shutdown(&priv
->usb
);
3618 spin_unlock_irqrestore(&priv
->lock
, flags
);
3620 dev_dbg(dev
, "USB shutdown failed with %d\n", status
);
3627 static struct device_driver octeon_usb_driver
= {
3628 .name
= "OcteonUSB",
3629 .bus
= &platform_bus_type
,
3630 .probe
= octeon_usb_driver_probe
,
3631 .remove
= octeon_usb_driver_remove
,
3635 #define MAX_USB_PORTS 10
3636 static struct platform_device
*pdev_glob
[MAX_USB_PORTS
];
3637 static int octeon_usb_registered
;
3638 static int __init
octeon_usb_module_init(void)
3640 int num_devices
= cvmx_usb_get_num_ports();
3643 if (usb_disabled() || num_devices
== 0)
3646 if (driver_register(&octeon_usb_driver
))
3649 octeon_usb_registered
= 1;
3652 * Only cn52XX and cn56XX have DWC_OTG USB hardware and the
3653 * IOB priority registers. Under heavy network load USB
3654 * hardware can be starved by the IOB causing a crash. Give
3655 * it a priority boost if it has been waiting more than 400
3656 * cycles to avoid this situation.
3658 * Testing indicates that a cnt_val of 8192 is not sufficient,
3659 * but no failures are seen with 4096. We choose a value of
3660 * 400 to give a safety factor of 10.
3662 if (OCTEON_IS_MODEL(OCTEON_CN52XX
) || OCTEON_IS_MODEL(OCTEON_CN56XX
)) {
3663 union cvmx_iob_n2c_l2c_pri_cnt pri_cnt
;
3666 pri_cnt
.s
.cnt_enb
= 1;
3667 pri_cnt
.s
.cnt_val
= 400;
3668 cvmx_write_csr(CVMX_IOB_N2C_L2C_PRI_CNT
, pri_cnt
.u64
);
3671 for (device
= 0; device
< num_devices
; device
++) {
3672 struct resource irq_resource
;
3673 struct platform_device
*pdev
;
3674 memset(&irq_resource
, 0, sizeof(irq_resource
));
3675 irq_resource
.start
= (device
== 0) ? OCTEON_IRQ_USB0
: OCTEON_IRQ_USB1
;
3676 irq_resource
.end
= irq_resource
.start
;
3677 irq_resource
.flags
= IORESOURCE_IRQ
;
3678 pdev
= platform_device_register_simple((char *)octeon_usb_driver
. name
, device
, &irq_resource
, 1);
3680 driver_unregister(&octeon_usb_driver
);
3681 octeon_usb_registered
= 0;
3682 return PTR_ERR(pdev
);
3684 if (device
< MAX_USB_PORTS
)
3685 pdev_glob
[device
] = pdev
;
3691 static void __exit
octeon_usb_module_cleanup(void)
3695 for (i
= 0; i
< MAX_USB_PORTS
; i
++)
3697 platform_device_unregister(pdev_glob
[i
]);
3698 pdev_glob
[i
] = NULL
;
3700 if (octeon_usb_registered
)
3701 driver_unregister(&octeon_usb_driver
);
3704 MODULE_LICENSE("GPL");
3705 MODULE_AUTHOR("Cavium Networks <support@caviumnetworks.com>");
3706 MODULE_DESCRIPTION("Cavium Networks Octeon USB Host driver.");
3707 module_init(octeon_usb_module_init
);
3708 module_exit(octeon_usb_module_cleanup
);