staging: octeon-usb: use dynamic allocation for transactions
[deliverable/linux.git] / drivers / staging / octeon-usb / octeon-hcd.c
1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Cavium Networks
7 *
8 * Some parts of the code were originally released under BSD license:
9 *
10 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
11 * reserved.
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions are
15 * met:
16 *
17 * * Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 *
20 * * Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials provided
23 * with the distribution.
24 *
25 * * Neither the name of Cavium Networks nor the names of
26 * its contributors may be used to endorse or promote products
27 * derived from this software without specific prior written
28 * permission.
29 *
30 * This Software, including technical data, may be subject to U.S. export
31 * control laws, including the U.S. Export Administration Act and its associated
32 * regulations, and may be subject to export or import regulations in other
33 * countries.
34 *
35 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
36 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR
37 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
38 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION
39 * OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
40 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
41 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
42 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
43 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
44 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
45 */
46 #include <linux/kernel.h>
47 #include <linux/module.h>
48 #include <linux/init.h>
49 #include <linux/pci.h>
50 #include <linux/interrupt.h>
51 #include <linux/platform_device.h>
52 #include <linux/usb.h>
53
54 #include <linux/time.h>
55 #include <linux/delay.h>
56
57 #include <asm/octeon/cvmx.h>
58 #include <asm/octeon/cvmx-iob-defs.h>
59
60 #include <linux/usb/hcd.h>
61
62 #include <linux/err.h>
63
64 #include <asm/octeon/octeon.h>
65 #include <asm/octeon/cvmx-helper.h>
66 #include <asm/octeon/cvmx-sysinfo.h>
67 #include <asm/octeon/cvmx-helper-board.h>
68
69 #include "octeon-hcd.h"
70
71 /**
72 * enum cvmx_usb_speed - the possible USB device speeds
73 *
74 * @CVMX_USB_SPEED_HIGH: Device is operation at 480Mbps
75 * @CVMX_USB_SPEED_FULL: Device is operation at 12Mbps
76 * @CVMX_USB_SPEED_LOW: Device is operation at 1.5Mbps
77 */
78 enum cvmx_usb_speed {
79 CVMX_USB_SPEED_HIGH = 0,
80 CVMX_USB_SPEED_FULL = 1,
81 CVMX_USB_SPEED_LOW = 2,
82 };
83
84 /**
85 * enum cvmx_usb_transfer - the possible USB transfer types
86 *
87 * @CVMX_USB_TRANSFER_CONTROL: USB transfer type control for hub and status
88 * transfers
89 * @CVMX_USB_TRANSFER_ISOCHRONOUS: USB transfer type isochronous for low
90 * priority periodic transfers
91 * @CVMX_USB_TRANSFER_BULK: USB transfer type bulk for large low priority
92 * transfers
93 * @CVMX_USB_TRANSFER_INTERRUPT: USB transfer type interrupt for high priority
94 * periodic transfers
95 */
96 enum cvmx_usb_transfer {
97 CVMX_USB_TRANSFER_CONTROL = 0,
98 CVMX_USB_TRANSFER_ISOCHRONOUS = 1,
99 CVMX_USB_TRANSFER_BULK = 2,
100 CVMX_USB_TRANSFER_INTERRUPT = 3,
101 };
102
103 /**
104 * enum cvmx_usb_direction - the transfer directions
105 *
106 * @CVMX_USB_DIRECTION_OUT: Data is transferring from Octeon to the device/host
107 * @CVMX_USB_DIRECTION_IN: Data is transferring from the device/host to Octeon
108 */
109 enum cvmx_usb_direction {
110 CVMX_USB_DIRECTION_OUT,
111 CVMX_USB_DIRECTION_IN,
112 };
113
114 /**
115 * enum cvmx_usb_complete - possible callback function status codes
116 *
117 * @CVMX_USB_COMPLETE_SUCCESS: The transaction / operation finished without
118 * any errors
119 * @CVMX_USB_COMPLETE_SHORT: FIXME: This is currently not implemented
120 * @CVMX_USB_COMPLETE_CANCEL: The transaction was canceled while in flight
121 * by a user call to cvmx_usb_cancel
122 * @CVMX_USB_COMPLETE_ERROR: The transaction aborted with an unexpected
123 * error status
124 * @CVMX_USB_COMPLETE_STALL: The transaction received a USB STALL response
125 * from the device
126 * @CVMX_USB_COMPLETE_XACTERR: The transaction failed with an error from the
127 * device even after a number of retries
128 * @CVMX_USB_COMPLETE_DATATGLERR: The transaction failed with a data toggle
129 * error even after a number of retries
130 * @CVMX_USB_COMPLETE_BABBLEERR: The transaction failed with a babble error
131 * @CVMX_USB_COMPLETE_FRAMEERR: The transaction failed with a frame error
132 * even after a number of retries
133 */
134 enum cvmx_usb_complete {
135 CVMX_USB_COMPLETE_SUCCESS,
136 CVMX_USB_COMPLETE_SHORT,
137 CVMX_USB_COMPLETE_CANCEL,
138 CVMX_USB_COMPLETE_ERROR,
139 CVMX_USB_COMPLETE_STALL,
140 CVMX_USB_COMPLETE_XACTERR,
141 CVMX_USB_COMPLETE_DATATGLERR,
142 CVMX_USB_COMPLETE_BABBLEERR,
143 CVMX_USB_COMPLETE_FRAMEERR,
144 };
145
146 /**
147 * struct cvmx_usb_port_status - the USB port status information
148 *
149 * @port_enabled: 1 = Usb port is enabled, 0 = disabled
150 * @port_over_current: 1 = Over current detected, 0 = Over current not
151 * detected. Octeon doesn't support over current detection.
152 * @port_powered: 1 = Port power is being supplied to the device, 0 =
153 * power is off. Octeon doesn't support turning port power
154 * off.
155 * @port_speed: Current port speed.
156 * @connected: 1 = A device is connected to the port, 0 = No device is
157 * connected.
158 * @connect_change: 1 = Device connected state changed since the last set
159 * status call.
160 */
161 struct cvmx_usb_port_status {
162 uint32_t reserved : 25;
163 uint32_t port_enabled : 1;
164 uint32_t port_over_current : 1;
165 uint32_t port_powered : 1;
166 enum cvmx_usb_speed port_speed : 2;
167 uint32_t connected : 1;
168 uint32_t connect_change : 1;
169 };
170
171 /**
172 * union cvmx_usb_control_header - the structure of a Control packet header
173 *
174 * @s.request_type: Bit 7 tells the direction: 1=IN, 0=OUT
175 * @s.request The standard usb request to make
176 * @s.value Value parameter for the request in little endian format
177 * @s.index Index for the request in little endian format
178 * @s.length Length of the data associated with this request in
179 * little endian format
180 */
181 union cvmx_usb_control_header {
182 uint64_t u64;
183 struct {
184 uint64_t request_type : 8;
185 uint64_t request : 8;
186 uint64_t value : 16;
187 uint64_t index : 16;
188 uint64_t length : 16;
189 } s;
190 };
191
192 /**
193 * struct cvmx_usb_iso_packet - descriptor for Isochronous packets
194 *
195 * @offset: This is the offset in bytes into the main buffer where this data
196 * is stored.
197 * @length: This is the length in bytes of the data.
198 * @status: This is the status of this individual packet transfer.
199 */
200 struct cvmx_usb_iso_packet {
201 int offset;
202 int length;
203 enum cvmx_usb_complete status;
204 };
205
206 /**
207 * enum cvmx_usb_initialize_flags - flags used by the initialization function
208 *
209 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI: The USB port uses a 12MHz crystal
210 * as clock source at USB_XO and
211 * USB_XI.
212 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND: The USB port uses 12/24/48MHz 2.5V
213 * board clock source at USB_XO.
214 * USB_XI should be tied to GND.
215 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK: Mask for clock speed field
216 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ: Speed of reference clock or
217 * crystal
218 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ: Speed of reference clock
219 * @CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ: Speed of reference clock
220 * @CVMX_USB_INITIALIZE_FLAGS_NO_DMA: Disable DMA and used polled IO for
221 * data transfer use for the USB
222 */
223 enum cvmx_usb_initialize_flags {
224 CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI = 1 << 0,
225 CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND = 1 << 1,
226 CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK = 3 << 3,
227 CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ = 1 << 3,
228 CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ = 2 << 3,
229 CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ = 3 << 3,
230 /* Bits 3-4 used to encode the clock frequency */
231 CVMX_USB_INITIALIZE_FLAGS_NO_DMA = 1 << 5,
232 };
233
234 /**
235 * enum cvmx_usb_pipe_flags - internal flags for a pipe.
236 *
237 * @__CVMX_USB_PIPE_FLAGS_OPEN: Used internally to determine if a pipe is
238 * open. Do not use.
239 * @__CVMX_USB_PIPE_FLAGS_SCHEDULED: Used internally to determine if a pipe is
240 * actively using hardware. Do not use.
241 * @__CVMX_USB_PIPE_FLAGS_NEED_PING: Used internally to determine if a high
242 * speed pipe is in the ping state. Do not
243 * use.
244 */
245 enum cvmx_usb_pipe_flags {
246 __CVMX_USB_PIPE_FLAGS_OPEN = 1 << 16,
247 __CVMX_USB_PIPE_FLAGS_SCHEDULED = 1 << 17,
248 __CVMX_USB_PIPE_FLAGS_NEED_PING = 1 << 18,
249 };
250
251 /* Normal prefetch that use the pref instruction. */
252 #define CVMX_PREFETCH(address, offset) asm volatile ("pref %[type], %[off](%[rbase])" : : [rbase] "d" (address), [off] "I" (offset), [type] "n" (0))
253
254 /* Maximum number of times to retry failed transactions */
255 #define MAX_RETRIES 3
256
257 /* Maximum number of pipes that can be open at once */
258 #define MAX_PIPES 32
259
260 /* Maximum number of hardware channels supported by the USB block */
261 #define MAX_CHANNELS 8
262
263 /* The highest valid USB device address */
264 #define MAX_USB_ADDRESS 127
265
266 /* The highest valid USB endpoint number */
267 #define MAX_USB_ENDPOINT 15
268
269 /* The highest valid port number on a hub */
270 #define MAX_USB_HUB_PORT 15
271
272 /*
273 * The low level hardware can transfer a maximum of this number of bytes in each
274 * transfer. The field is 19 bits wide
275 */
276 #define MAX_TRANSFER_BYTES ((1<<19)-1)
277
278 /*
279 * The low level hardware can transfer a maximum of this number of packets in
280 * each transfer. The field is 10 bits wide
281 */
282 #define MAX_TRANSFER_PACKETS ((1<<10)-1)
283
284 enum {
285 USB_CLOCK_TYPE_REF_12,
286 USB_CLOCK_TYPE_REF_24,
287 USB_CLOCK_TYPE_REF_48,
288 USB_CLOCK_TYPE_CRYSTAL_12,
289 };
290
291 /**
292 * Logical transactions may take numerous low level
293 * transactions, especially when splits are concerned. This
294 * enum represents all of the possible stages a transaction can
295 * be in. Note that split completes are always even. This is so
296 * the NAK handler can backup to the previous low level
297 * transaction with a simple clearing of bit 0.
298 */
299 enum cvmx_usb_stage {
300 CVMX_USB_STAGE_NON_CONTROL,
301 CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE,
302 CVMX_USB_STAGE_SETUP,
303 CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE,
304 CVMX_USB_STAGE_DATA,
305 CVMX_USB_STAGE_DATA_SPLIT_COMPLETE,
306 CVMX_USB_STAGE_STATUS,
307 CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE,
308 };
309
310 /**
311 * struct cvmx_usb_transaction - describes each pending USB transaction
312 * regardless of type. These are linked together
313 * to form a list of pending requests for a pipe.
314 *
315 * @prev: Transaction before this one in the pipe.
316 * @next: Transaction after this one in the pipe.
317 * @type: Type of transaction, duplicated of the pipe.
318 * @flags: State flags for this transaction.
319 * @buffer: User's physical buffer address to read/write.
320 * @buffer_length: Size of the user's buffer in bytes.
321 * @control_header: For control transactions, physical address of the 8
322 * byte standard header.
323 * @iso_start_frame: For ISO transactions, the starting frame number.
324 * @iso_number_packets: For ISO transactions, the number of packets in the
325 * request.
326 * @iso_packets: For ISO transactions, the sub packets in the request.
327 * @actual_bytes: Actual bytes transfer for this transaction.
328 * @stage: For control transactions, the current stage.
329 * @urb: URB.
330 */
331 struct cvmx_usb_transaction {
332 struct cvmx_usb_transaction *prev;
333 struct cvmx_usb_transaction *next;
334 enum cvmx_usb_transfer type;
335 uint64_t buffer;
336 int buffer_length;
337 uint64_t control_header;
338 int iso_start_frame;
339 int iso_number_packets;
340 struct cvmx_usb_iso_packet *iso_packets;
341 int xfersize;
342 int pktcnt;
343 int retries;
344 int actual_bytes;
345 enum cvmx_usb_stage stage;
346 struct urb *urb;
347 };
348
349 /**
350 * struct cvmx_usb_pipe - a pipe represents a virtual connection between Octeon
351 * and some USB device. It contains a list of pending
352 * request to the device.
353 *
354 * @prev: Pipe before this one in the list
355 * @next: Pipe after this one in the list
356 * @head: The first pending transaction
357 * @tail: The last pending transaction
358 * @interval: For periodic pipes, the interval between packets in
359 * frames
360 * @next_tx_frame: The next frame this pipe is allowed to transmit on
361 * @flags: State flags for this pipe
362 * @device_speed: Speed of device connected to this pipe
363 * @transfer_type: Type of transaction supported by this pipe
364 * @transfer_dir: IN or OUT. Ignored for Control
365 * @multi_count: Max packet in a row for the device
366 * @max_packet: The device's maximum packet size in bytes
367 * @device_addr: USB device address at other end of pipe
368 * @endpoint_num: USB endpoint number at other end of pipe
369 * @hub_device_addr: Hub address this device is connected to
370 * @hub_port: Hub port this device is connected to
371 * @pid_toggle: This toggles between 0/1 on every packet send to track
372 * the data pid needed
373 * @channel: Hardware DMA channel for this pipe
374 * @split_sc_frame: The low order bits of the frame number the split
375 * complete should be sent on
376 */
377 struct cvmx_usb_pipe {
378 struct cvmx_usb_pipe *prev;
379 struct cvmx_usb_pipe *next;
380 struct cvmx_usb_transaction *head;
381 struct cvmx_usb_transaction *tail;
382 uint64_t interval;
383 uint64_t next_tx_frame;
384 enum cvmx_usb_pipe_flags flags;
385 enum cvmx_usb_speed device_speed;
386 enum cvmx_usb_transfer transfer_type;
387 enum cvmx_usb_direction transfer_dir;
388 int multi_count;
389 uint16_t max_packet;
390 uint8_t device_addr;
391 uint8_t endpoint_num;
392 uint8_t hub_device_addr;
393 uint8_t hub_port;
394 uint8_t pid_toggle;
395 uint8_t channel;
396 int8_t split_sc_frame;
397 };
398
399 /**
400 * struct cvmx_usb_pipe_list
401 *
402 * @head: Head of the list, or NULL if empty.
403 * @tail: Tail if the list, or NULL if empty.
404 */
405 struct cvmx_usb_pipe_list {
406 struct cvmx_usb_pipe *head;
407 struct cvmx_usb_pipe *tail;
408 };
409
410 struct cvmx_usb_tx_fifo {
411 struct {
412 int channel;
413 int size;
414 uint64_t address;
415 } entry[MAX_CHANNELS+1];
416 int head;
417 int tail;
418 };
419
420 /**
421 * struct cvmx_usb_state - the state of the USB block
422 *
423 * init_flags: Flags passed to initialize.
424 * index: Which USB block this is for.
425 * idle_hardware_channels: Bit set for every idle hardware channel.
426 * usbcx_hprt: Stored port status so we don't need to read a CSR to
427 * determine splits.
428 * pipe_for_channel: Map channels to pipes.
429 * pipe: Storage for pipes.
430 * indent: Used by debug output to indent functions.
431 * port_status: Last port status used for change notification.
432 * free_pipes: List of all pipes that are currently closed.
433 * idle_pipes: List of open pipes that have no transactions.
434 * active_pipes: Active pipes indexed by transfer type.
435 * frame_number: Increments every SOF interrupt for time keeping.
436 * active_split: Points to the current active split, or NULL.
437 */
438 struct cvmx_usb_state {
439 int init_flags;
440 int index;
441 int idle_hardware_channels;
442 union cvmx_usbcx_hprt usbcx_hprt;
443 struct cvmx_usb_pipe *pipe_for_channel[MAX_CHANNELS];
444 struct cvmx_usb_pipe pipe[MAX_PIPES];
445 int indent;
446 struct cvmx_usb_port_status port_status;
447 struct cvmx_usb_pipe_list free_pipes;
448 struct cvmx_usb_pipe_list idle_pipes;
449 struct cvmx_usb_pipe_list active_pipes[4];
450 uint64_t frame_number;
451 struct cvmx_usb_transaction *active_split;
452 struct cvmx_usb_tx_fifo periodic;
453 struct cvmx_usb_tx_fifo nonperiodic;
454 };
455
456 struct octeon_hcd {
457 spinlock_t lock;
458 struct cvmx_usb_state usb;
459 struct tasklet_struct dequeue_tasklet;
460 struct list_head dequeue_list;
461 };
462
463 /* This macro spins on a field waiting for it to reach a value */
464 #define CVMX_WAIT_FOR_FIELD32(address, type, field, op, value, timeout_usec)\
465 ({int result; \
466 do { \
467 uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec * \
468 octeon_get_clock_rate() / 1000000; \
469 type c; \
470 while (1) { \
471 c.u32 = __cvmx_usb_read_csr32(usb, address); \
472 if (c.s.field op (value)) { \
473 result = 0; \
474 break; \
475 } else if (cvmx_get_cycle() > done) { \
476 result = -1; \
477 break; \
478 } else \
479 cvmx_wait(100); \
480 } \
481 } while (0); \
482 result; })
483
484 /*
485 * This macro logically sets a single field in a CSR. It does the sequence
486 * read, modify, and write
487 */
488 #define USB_SET_FIELD32(address, type, field, value) \
489 do { \
490 type c; \
491 c.u32 = __cvmx_usb_read_csr32(usb, address); \
492 c.s.field = value; \
493 __cvmx_usb_write_csr32(usb, address, c.u32); \
494 } while (0)
495
496 /* Returns the IO address to push/pop stuff data from the FIFOs */
497 #define USB_FIFO_ADDRESS(channel, usb_index) (CVMX_USBCX_GOTGCTL(usb_index) + ((channel)+1)*0x1000)
498
499 static int octeon_usb_get_clock_type(void)
500 {
501 switch (cvmx_sysinfo_get()->board_type) {
502 case CVMX_BOARD_TYPE_BBGW_REF:
503 case CVMX_BOARD_TYPE_LANAI2_A:
504 case CVMX_BOARD_TYPE_LANAI2_U:
505 case CVMX_BOARD_TYPE_LANAI2_G:
506 case CVMX_BOARD_TYPE_UBNT_E100:
507 return USB_CLOCK_TYPE_CRYSTAL_12;
508 }
509 return USB_CLOCK_TYPE_REF_48;
510 }
511
512 /**
513 * Read a USB 32bit CSR. It performs the necessary address swizzle
514 * for 32bit CSRs and logs the value in a readable format if
515 * debugging is on.
516 *
517 * @usb: USB block this access is for
518 * @address: 64bit address to read
519 *
520 * Returns: Result of the read
521 */
522 static inline uint32_t __cvmx_usb_read_csr32(struct cvmx_usb_state *usb,
523 uint64_t address)
524 {
525 uint32_t result = cvmx_read64_uint32(address ^ 4);
526 return result;
527 }
528
529
530 /**
531 * Write a USB 32bit CSR. It performs the necessary address
532 * swizzle for 32bit CSRs and logs the value in a readable format
533 * if debugging is on.
534 *
535 * @usb: USB block this access is for
536 * @address: 64bit address to write
537 * @value: Value to write
538 */
539 static inline void __cvmx_usb_write_csr32(struct cvmx_usb_state *usb,
540 uint64_t address, uint32_t value)
541 {
542 cvmx_write64_uint32(address ^ 4, value);
543 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
544 }
545
546
547 /**
548 * Read a USB 64bit CSR. It logs the value in a readable format if
549 * debugging is on.
550 *
551 * @usb: USB block this access is for
552 * @address: 64bit address to read
553 *
554 * Returns: Result of the read
555 */
556 static inline uint64_t __cvmx_usb_read_csr64(struct cvmx_usb_state *usb,
557 uint64_t address)
558 {
559 uint64_t result = cvmx_read64_uint64(address);
560 return result;
561 }
562
563
564 /**
565 * Write a USB 64bit CSR. It logs the value in a readable format
566 * if debugging is on.
567 *
568 * @usb: USB block this access is for
569 * @address: 64bit address to write
570 * @value: Value to write
571 */
572 static inline void __cvmx_usb_write_csr64(struct cvmx_usb_state *usb,
573 uint64_t address, uint64_t value)
574 {
575 cvmx_write64_uint64(address, value);
576 }
577
578 /**
579 * Return non zero if this pipe connects to a non HIGH speed
580 * device through a high speed hub.
581 *
582 * @usb: USB block this access is for
583 * @pipe: Pipe to check
584 *
585 * Returns: Non zero if we need to do split transactions
586 */
587 static inline int __cvmx_usb_pipe_needs_split(struct cvmx_usb_state *usb,
588 struct cvmx_usb_pipe *pipe)
589 {
590 return pipe->device_speed != CVMX_USB_SPEED_HIGH &&
591 usb->usbcx_hprt.s.prtspd == CVMX_USB_SPEED_HIGH;
592 }
593
594
595 /**
596 * Trivial utility function to return the correct PID for a pipe
597 *
598 * @pipe: pipe to check
599 *
600 * Returns: PID for pipe
601 */
602 static inline int __cvmx_usb_get_data_pid(struct cvmx_usb_pipe *pipe)
603 {
604 if (pipe->pid_toggle)
605 return 2; /* Data1 */
606 else
607 return 0; /* Data0 */
608 }
609
610
611 /**
612 * Return the number of USB ports supported by this Octeon
613 * chip. If the chip doesn't support USB, or is not supported
614 * by this API, a zero will be returned. Most Octeon chips
615 * support one usb port, but some support two ports.
616 * cvmx_usb_initialize() must be called on independent
617 * struct cvmx_usb_state.
618 *
619 * Returns: Number of port, zero if usb isn't supported
620 */
621 static int cvmx_usb_get_num_ports(void)
622 {
623 int arch_ports = 0;
624
625 if (OCTEON_IS_MODEL(OCTEON_CN56XX))
626 arch_ports = 1;
627 else if (OCTEON_IS_MODEL(OCTEON_CN52XX))
628 arch_ports = 2;
629 else if (OCTEON_IS_MODEL(OCTEON_CN50XX))
630 arch_ports = 1;
631 else if (OCTEON_IS_MODEL(OCTEON_CN31XX))
632 arch_ports = 1;
633 else if (OCTEON_IS_MODEL(OCTEON_CN30XX))
634 arch_ports = 1;
635 else
636 arch_ports = 0;
637
638 return arch_ports;
639 }
640
641 /**
642 * Add a pipe to the tail of a list
643 * @list: List to add pipe to
644 * @pipe: Pipe to add
645 */
646 static inline void __cvmx_usb_append_pipe(struct cvmx_usb_pipe_list *list, struct cvmx_usb_pipe *pipe)
647 {
648 pipe->next = NULL;
649 pipe->prev = list->tail;
650 if (list->tail)
651 list->tail->next = pipe;
652 else
653 list->head = pipe;
654 list->tail = pipe;
655 }
656
657
658 /**
659 * Remove a pipe from a list
660 * @list: List to remove pipe from
661 * @pipe: Pipe to remove
662 */
663 static inline void __cvmx_usb_remove_pipe(struct cvmx_usb_pipe_list *list, struct cvmx_usb_pipe *pipe)
664 {
665 if (list->head == pipe) {
666 list->head = pipe->next;
667 pipe->next = NULL;
668 if (list->head)
669 list->head->prev = NULL;
670 else
671 list->tail = NULL;
672 } else if (list->tail == pipe) {
673 list->tail = pipe->prev;
674 list->tail->next = NULL;
675 pipe->prev = NULL;
676 } else {
677 pipe->prev->next = pipe->next;
678 pipe->next->prev = pipe->prev;
679 pipe->prev = NULL;
680 pipe->next = NULL;
681 }
682 }
683
684
685 /**
686 * Initialize a USB port for use. This must be called before any
687 * other access to the Octeon USB port is made. The port starts
688 * off in the disabled state.
689 *
690 * @usb: Pointer to an empty struct cvmx_usb_state
691 * that will be populated by the initialize call.
692 * This structure is then passed to all other USB
693 * functions.
694 * @usb_port_number:
695 * Which Octeon USB port to initialize.
696 *
697 * Returns: 0 or a negative error code.
698 */
699 static int cvmx_usb_initialize(struct cvmx_usb_state *usb,
700 int usb_port_number)
701 {
702 union cvmx_usbnx_clk_ctl usbn_clk_ctl;
703 union cvmx_usbnx_usbp_ctl_status usbn_usbp_ctl_status;
704 enum cvmx_usb_initialize_flags flags = 0;
705
706 /* At first allow 0-1 for the usb port number */
707 if ((usb_port_number < 0) || (usb_port_number > 1))
708 return -EINVAL;
709 /* For all chips except 52XX there is only one port */
710 if (!OCTEON_IS_MODEL(OCTEON_CN52XX) && (usb_port_number > 0))
711 return -EINVAL;
712 /* Try to determine clock type automatically */
713 if (octeon_usb_get_clock_type() == USB_CLOCK_TYPE_CRYSTAL_12) {
714 /* Only 12 MHZ crystals are supported */
715 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_XI;
716 } else {
717 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND;
718
719 switch (octeon_usb_get_clock_type()) {
720 case USB_CLOCK_TYPE_REF_12:
721 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ;
722 break;
723 case USB_CLOCK_TYPE_REF_24:
724 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ;
725 break;
726 case USB_CLOCK_TYPE_REF_48:
727 flags |= CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ;
728 break;
729 default:
730 return -EINVAL;
731 break;
732 }
733 }
734
735 memset(usb, 0, sizeof(*usb));
736 usb->init_flags = flags;
737
738 /* Initialize the USB state structure */
739 {
740 int i;
741 usb->index = usb_port_number;
742
743 for (i = 0; i < MAX_PIPES; i++)
744 __cvmx_usb_append_pipe(&usb->free_pipes, usb->pipe + i);
745 }
746
747 /*
748 * Power On Reset and PHY Initialization
749 *
750 * 1. Wait for DCOK to assert (nothing to do)
751 *
752 * 2a. Write USBN0/1_CLK_CTL[POR] = 1 and
753 * USBN0/1_CLK_CTL[HRST,PRST,HCLK_RST] = 0
754 */
755 usbn_clk_ctl.u64 = __cvmx_usb_read_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index));
756 usbn_clk_ctl.s.por = 1;
757 usbn_clk_ctl.s.hrst = 0;
758 usbn_clk_ctl.s.prst = 0;
759 usbn_clk_ctl.s.hclk_rst = 0;
760 usbn_clk_ctl.s.enable = 0;
761 /*
762 * 2b. Select the USB reference clock/crystal parameters by writing
763 * appropriate values to USBN0/1_CLK_CTL[P_C_SEL, P_RTYPE, P_COM_ON]
764 */
765 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_XO_GND) {
766 /*
767 * The USB port uses 12/24/48MHz 2.5V board clock
768 * source at USB_XO. USB_XI should be tied to GND.
769 * Most Octeon evaluation boards require this setting
770 */
771 if (OCTEON_IS_MODEL(OCTEON_CN3XXX) ||
772 OCTEON_IS_MODEL(OCTEON_CN56XX) ||
773 OCTEON_IS_MODEL(OCTEON_CN50XX))
774 /* From CN56XX,CN50XX,CN31XX,CN30XX manuals */
775 usbn_clk_ctl.s.p_rtype = 2; /* p_rclk=1 & p_xenbn=0 */
776 else
777 /* From CN52XX manual */
778 usbn_clk_ctl.s.p_rtype = 1;
779
780 switch (flags & CVMX_USB_INITIALIZE_FLAGS_CLOCK_MHZ_MASK) {
781 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_12MHZ:
782 usbn_clk_ctl.s.p_c_sel = 0;
783 break;
784 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_24MHZ:
785 usbn_clk_ctl.s.p_c_sel = 1;
786 break;
787 case CVMX_USB_INITIALIZE_FLAGS_CLOCK_48MHZ:
788 usbn_clk_ctl.s.p_c_sel = 2;
789 break;
790 }
791 } else {
792 /*
793 * The USB port uses a 12MHz crystal as clock source
794 * at USB_XO and USB_XI
795 */
796 if (OCTEON_IS_MODEL(OCTEON_CN3XXX))
797 /* From CN31XX,CN30XX manual */
798 usbn_clk_ctl.s.p_rtype = 3; /* p_rclk=1 & p_xenbn=1 */
799 else
800 /* From CN56XX,CN52XX,CN50XX manuals. */
801 usbn_clk_ctl.s.p_rtype = 0;
802
803 usbn_clk_ctl.s.p_c_sel = 0;
804 }
805 /*
806 * 2c. Select the HCLK via writing USBN0/1_CLK_CTL[DIVIDE, DIVIDE2] and
807 * setting USBN0/1_CLK_CTL[ENABLE] = 1. Divide the core clock down
808 * such that USB is as close as possible to 125Mhz
809 */
810 {
811 int divisor = (octeon_get_clock_rate()+125000000-1)/125000000;
812 /* Lower than 4 doesn't seem to work properly */
813 if (divisor < 4)
814 divisor = 4;
815 usbn_clk_ctl.s.divide = divisor;
816 usbn_clk_ctl.s.divide2 = 0;
817 }
818 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
819 usbn_clk_ctl.u64);
820 /* 2d. Write USBN0/1_CLK_CTL[HCLK_RST] = 1 */
821 usbn_clk_ctl.s.hclk_rst = 1;
822 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
823 usbn_clk_ctl.u64);
824 /* 2e. Wait 64 core-clock cycles for HCLK to stabilize */
825 cvmx_wait(64);
826 /*
827 * 3. Program the power-on reset field in the USBN clock-control
828 * register:
829 * USBN_CLK_CTL[POR] = 0
830 */
831 usbn_clk_ctl.s.por = 0;
832 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
833 usbn_clk_ctl.u64);
834 /* 4. Wait 1 ms for PHY clock to start */
835 mdelay(1);
836 /*
837 * 5. Program the Reset input from automatic test equipment field in the
838 * USBP control and status register:
839 * USBN_USBP_CTL_STATUS[ATE_RESET] = 1
840 */
841 usbn_usbp_ctl_status.u64 = __cvmx_usb_read_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index));
842 usbn_usbp_ctl_status.s.ate_reset = 1;
843 __cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
844 usbn_usbp_ctl_status.u64);
845 /* 6. Wait 10 cycles */
846 cvmx_wait(10);
847 /*
848 * 7. Clear ATE_RESET field in the USBN clock-control register:
849 * USBN_USBP_CTL_STATUS[ATE_RESET] = 0
850 */
851 usbn_usbp_ctl_status.s.ate_reset = 0;
852 __cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
853 usbn_usbp_ctl_status.u64);
854 /*
855 * 8. Program the PHY reset field in the USBN clock-control register:
856 * USBN_CLK_CTL[PRST] = 1
857 */
858 usbn_clk_ctl.s.prst = 1;
859 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
860 usbn_clk_ctl.u64);
861 /*
862 * 9. Program the USBP control and status register to select host or
863 * device mode. USBN_USBP_CTL_STATUS[HST_MODE] = 0 for host, = 1 for
864 * device
865 */
866 usbn_usbp_ctl_status.s.hst_mode = 0;
867 __cvmx_usb_write_csr64(usb, CVMX_USBNX_USBP_CTL_STATUS(usb->index),
868 usbn_usbp_ctl_status.u64);
869 /* 10. Wait 1 us */
870 udelay(1);
871 /*
872 * 11. Program the hreset_n field in the USBN clock-control register:
873 * USBN_CLK_CTL[HRST] = 1
874 */
875 usbn_clk_ctl.s.hrst = 1;
876 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
877 usbn_clk_ctl.u64);
878 /* 12. Proceed to USB core initialization */
879 usbn_clk_ctl.s.enable = 1;
880 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
881 usbn_clk_ctl.u64);
882 udelay(1);
883
884 /*
885 * USB Core Initialization
886 *
887 * 1. Read USBC_GHWCFG1, USBC_GHWCFG2, USBC_GHWCFG3, USBC_GHWCFG4 to
888 * determine USB core configuration parameters.
889 *
890 * Nothing needed
891 *
892 * 2. Program the following fields in the global AHB configuration
893 * register (USBC_GAHBCFG)
894 * DMA mode, USBC_GAHBCFG[DMAEn]: 1 = DMA mode, 0 = slave mode
895 * Burst length, USBC_GAHBCFG[HBSTLEN] = 0
896 * Nonperiodic TxFIFO empty level (slave mode only),
897 * USBC_GAHBCFG[NPTXFEMPLVL]
898 * Periodic TxFIFO empty level (slave mode only),
899 * USBC_GAHBCFG[PTXFEMPLVL]
900 * Global interrupt mask, USBC_GAHBCFG[GLBLINTRMSK] = 1
901 */
902 {
903 union cvmx_usbcx_gahbcfg usbcx_gahbcfg;
904 /* Due to an errata, CN31XX doesn't support DMA */
905 if (OCTEON_IS_MODEL(OCTEON_CN31XX))
906 usb->init_flags |= CVMX_USB_INITIALIZE_FLAGS_NO_DMA;
907 usbcx_gahbcfg.u32 = 0;
908 usbcx_gahbcfg.s.dmaen = !(usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA);
909 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
910 /* Only use one channel with non DMA */
911 usb->idle_hardware_channels = 0x1;
912 else if (OCTEON_IS_MODEL(OCTEON_CN5XXX))
913 /* CN5XXX have an errata with channel 3 */
914 usb->idle_hardware_channels = 0xf7;
915 else
916 usb->idle_hardware_channels = 0xff;
917 usbcx_gahbcfg.s.hbstlen = 0;
918 usbcx_gahbcfg.s.nptxfemplvl = 1;
919 usbcx_gahbcfg.s.ptxfemplvl = 1;
920 usbcx_gahbcfg.s.glblintrmsk = 1;
921 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GAHBCFG(usb->index),
922 usbcx_gahbcfg.u32);
923 }
924 /*
925 * 3. Program the following fields in USBC_GUSBCFG register.
926 * HS/FS timeout calibration, USBC_GUSBCFG[TOUTCAL] = 0
927 * ULPI DDR select, USBC_GUSBCFG[DDRSEL] = 0
928 * USB turnaround time, USBC_GUSBCFG[USBTRDTIM] = 0x5
929 * PHY low-power clock select, USBC_GUSBCFG[PHYLPWRCLKSEL] = 0
930 */
931 {
932 union cvmx_usbcx_gusbcfg usbcx_gusbcfg;
933 usbcx_gusbcfg.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GUSBCFG(usb->index));
934 usbcx_gusbcfg.s.toutcal = 0;
935 usbcx_gusbcfg.s.ddrsel = 0;
936 usbcx_gusbcfg.s.usbtrdtim = 0x5;
937 usbcx_gusbcfg.s.phylpwrclksel = 0;
938 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GUSBCFG(usb->index),
939 usbcx_gusbcfg.u32);
940 }
941 /*
942 * 4. The software must unmask the following bits in the USBC_GINTMSK
943 * register.
944 * OTG interrupt mask, USBC_GINTMSK[OTGINTMSK] = 1
945 * Mode mismatch interrupt mask, USBC_GINTMSK[MODEMISMSK] = 1
946 */
947 {
948 union cvmx_usbcx_gintmsk usbcx_gintmsk;
949 int channel;
950
951 usbcx_gintmsk.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GINTMSK(usb->index));
952 usbcx_gintmsk.s.otgintmsk = 1;
953 usbcx_gintmsk.s.modemismsk = 1;
954 usbcx_gintmsk.s.hchintmsk = 1;
955 usbcx_gintmsk.s.sofmsk = 0;
956 /* We need RX FIFO interrupts if we don't have DMA */
957 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
958 usbcx_gintmsk.s.rxflvlmsk = 1;
959 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTMSK(usb->index),
960 usbcx_gintmsk.u32);
961
962 /*
963 * Disable all channel interrupts. We'll enable them per channel
964 * later.
965 */
966 for (channel = 0; channel < 8; channel++)
967 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), 0);
968 }
969
970 {
971 /*
972 * Host Port Initialization
973 *
974 * 1. Program the host-port interrupt-mask field to unmask,
975 * USBC_GINTMSK[PRTINT] = 1
976 */
977 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk,
978 prtintmsk, 1);
979 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk,
980 disconnintmsk, 1);
981 /*
982 * 2. Program the USBC_HCFG register to select full-speed host
983 * or high-speed host.
984 */
985 {
986 union cvmx_usbcx_hcfg usbcx_hcfg;
987 usbcx_hcfg.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCFG(usb->index));
988 usbcx_hcfg.s.fslssupp = 0;
989 usbcx_hcfg.s.fslspclksel = 0;
990 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCFG(usb->index), usbcx_hcfg.u32);
991 }
992 /*
993 * 3. Program the port power bit to drive VBUS on the USB,
994 * USBC_HPRT[PRTPWR] = 1
995 */
996 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt, prtpwr, 1);
997
998 /*
999 * Steps 4-15 from the manual are done later in the port enable
1000 */
1001 }
1002
1003 return 0;
1004 }
1005
1006
1007 /**
1008 * Shutdown a USB port after a call to cvmx_usb_initialize().
1009 * The port should be disabled with all pipes closed when this
1010 * function is called.
1011 *
1012 * @usb: USB device state populated by cvmx_usb_initialize().
1013 *
1014 * Returns: 0 or a negative error code.
1015 */
1016 static int cvmx_usb_shutdown(struct cvmx_usb_state *usb)
1017 {
1018 union cvmx_usbnx_clk_ctl usbn_clk_ctl;
1019
1020 /* Make sure all pipes are closed */
1021 if (usb->idle_pipes.head ||
1022 usb->active_pipes[CVMX_USB_TRANSFER_ISOCHRONOUS].head ||
1023 usb->active_pipes[CVMX_USB_TRANSFER_INTERRUPT].head ||
1024 usb->active_pipes[CVMX_USB_TRANSFER_CONTROL].head ||
1025 usb->active_pipes[CVMX_USB_TRANSFER_BULK].head)
1026 return -EBUSY;
1027
1028 /* Disable the clocks and put them in power on reset */
1029 usbn_clk_ctl.u64 = __cvmx_usb_read_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index));
1030 usbn_clk_ctl.s.enable = 1;
1031 usbn_clk_ctl.s.por = 1;
1032 usbn_clk_ctl.s.hclk_rst = 1;
1033 usbn_clk_ctl.s.prst = 0;
1034 usbn_clk_ctl.s.hrst = 0;
1035 __cvmx_usb_write_csr64(usb, CVMX_USBNX_CLK_CTL(usb->index),
1036 usbn_clk_ctl.u64);
1037 return 0;
1038 }
1039
1040
1041 /**
1042 * Enable a USB port. After this call succeeds, the USB port is
1043 * online and servicing requests.
1044 *
1045 * @usb: USB device state populated by cvmx_usb_initialize().
1046 *
1047 * Returns: 0 or a negative error code.
1048 */
1049 static int cvmx_usb_enable(struct cvmx_usb_state *usb)
1050 {
1051 union cvmx_usbcx_ghwcfg3 usbcx_ghwcfg3;
1052
1053 usb->usbcx_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
1054
1055 /*
1056 * If the port is already enabled the just return. We don't need to do
1057 * anything
1058 */
1059 if (usb->usbcx_hprt.s.prtena)
1060 return 0;
1061
1062 /* If there is nothing plugged into the port then fail immediately */
1063 if (!usb->usbcx_hprt.s.prtconnsts) {
1064 return -ETIMEDOUT;
1065 }
1066
1067 /* Program the port reset bit to start the reset process */
1068 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt, prtrst, 1);
1069
1070 /*
1071 * Wait at least 50ms (high speed), or 10ms (full speed) for the reset
1072 * process to complete.
1073 */
1074 mdelay(50);
1075
1076 /* Program the port reset bit to 0, USBC_HPRT[PRTRST] = 0 */
1077 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt, prtrst, 0);
1078
1079 /* Wait for the USBC_HPRT[PRTENA]. */
1080 if (CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt,
1081 prtena, ==, 1, 100000))
1082 return -ETIMEDOUT;
1083
1084 /*
1085 * Read the port speed field to get the enumerated speed,
1086 * USBC_HPRT[PRTSPD].
1087 */
1088 usb->usbcx_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
1089 usbcx_ghwcfg3.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GHWCFG3(usb->index));
1090
1091 /*
1092 * 13. Program the USBC_GRXFSIZ register to select the size of the
1093 * receive FIFO (25%).
1094 */
1095 USB_SET_FIELD32(CVMX_USBCX_GRXFSIZ(usb->index), union cvmx_usbcx_grxfsiz,
1096 rxfdep, usbcx_ghwcfg3.s.dfifodepth / 4);
1097 /*
1098 * 14. Program the USBC_GNPTXFSIZ register to select the size and the
1099 * start address of the non- periodic transmit FIFO for nonperiodic
1100 * transactions (50%).
1101 */
1102 {
1103 union cvmx_usbcx_gnptxfsiz siz;
1104 siz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index));
1105 siz.s.nptxfdep = usbcx_ghwcfg3.s.dfifodepth / 2;
1106 siz.s.nptxfstaddr = usbcx_ghwcfg3.s.dfifodepth / 4;
1107 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GNPTXFSIZ(usb->index), siz.u32);
1108 }
1109 /*
1110 * 15. Program the USBC_HPTXFSIZ register to select the size and start
1111 * address of the periodic transmit FIFO for periodic transactions
1112 * (25%).
1113 */
1114 {
1115 union cvmx_usbcx_hptxfsiz siz;
1116 siz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPTXFSIZ(usb->index));
1117 siz.s.ptxfsize = usbcx_ghwcfg3.s.dfifodepth / 4;
1118 siz.s.ptxfstaddr = 3 * usbcx_ghwcfg3.s.dfifodepth / 4;
1119 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HPTXFSIZ(usb->index), siz.u32);
1120 }
1121 /* Flush all FIFOs */
1122 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), union cvmx_usbcx_grstctl, txfnum, 0x10);
1123 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), union cvmx_usbcx_grstctl, txfflsh, 1);
1124 CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), union cvmx_usbcx_grstctl,
1125 txfflsh, ==, 0, 100);
1126 USB_SET_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), union cvmx_usbcx_grstctl, rxfflsh, 1);
1127 CVMX_WAIT_FOR_FIELD32(CVMX_USBCX_GRSTCTL(usb->index), union cvmx_usbcx_grstctl,
1128 rxfflsh, ==, 0, 100);
1129
1130 return 0;
1131 }
1132
1133
1134 /**
1135 * Disable a USB port. After this call the USB port will not
1136 * generate data transfers and will not generate events.
1137 * Transactions in process will fail and call their
1138 * associated callbacks.
1139 *
1140 * @usb: USB device state populated by cvmx_usb_initialize().
1141 *
1142 * Returns: 0 or a negative error code.
1143 */
1144 static int cvmx_usb_disable(struct cvmx_usb_state *usb)
1145 {
1146 /* Disable the port */
1147 USB_SET_FIELD32(CVMX_USBCX_HPRT(usb->index), union cvmx_usbcx_hprt, prtena, 1);
1148 return 0;
1149 }
1150
1151
1152 /**
1153 * Get the current state of the USB port. Use this call to
1154 * determine if the usb port has anything connected, is enabled,
1155 * or has some sort of error condition. The return value of this
1156 * call has "changed" bits to signal of the value of some fields
1157 * have changed between calls.
1158 *
1159 * @usb: USB device state populated by cvmx_usb_initialize().
1160 *
1161 * Returns: Port status information
1162 */
1163 static struct cvmx_usb_port_status cvmx_usb_get_status(struct cvmx_usb_state *usb)
1164 {
1165 union cvmx_usbcx_hprt usbc_hprt;
1166 struct cvmx_usb_port_status result;
1167
1168 memset(&result, 0, sizeof(result));
1169
1170 usbc_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
1171 result.port_enabled = usbc_hprt.s.prtena;
1172 result.port_over_current = usbc_hprt.s.prtovrcurract;
1173 result.port_powered = usbc_hprt.s.prtpwr;
1174 result.port_speed = usbc_hprt.s.prtspd;
1175 result.connected = usbc_hprt.s.prtconnsts;
1176 result.connect_change = (result.connected != usb->port_status.connected);
1177
1178 return result;
1179 }
1180
1181 /**
1182 * Open a virtual pipe between the host and a USB device. A pipe
1183 * must be opened before data can be transferred between a device
1184 * and Octeon.
1185 *
1186 * @usb: USB device state populated by cvmx_usb_initialize().
1187 * @device_addr:
1188 * USB device address to open the pipe to
1189 * (0-127).
1190 * @endpoint_num:
1191 * USB endpoint number to open the pipe to
1192 * (0-15).
1193 * @device_speed:
1194 * The speed of the device the pipe is going
1195 * to. This must match the device's speed,
1196 * which may be different than the port speed.
1197 * @max_packet: The maximum packet length the device can
1198 * transmit/receive (low speed=0-8, full
1199 * speed=0-1023, high speed=0-1024). This value
1200 * comes from the standard endpoint descriptor
1201 * field wMaxPacketSize bits <10:0>.
1202 * @transfer_type:
1203 * The type of transfer this pipe is for.
1204 * @transfer_dir:
1205 * The direction the pipe is in. This is not
1206 * used for control pipes.
1207 * @interval: For ISOCHRONOUS and INTERRUPT transfers,
1208 * this is how often the transfer is scheduled
1209 * for. All other transfers should specify
1210 * zero. The units are in frames (8000/sec at
1211 * high speed, 1000/sec for full speed).
1212 * @multi_count:
1213 * For high speed devices, this is the maximum
1214 * allowed number of packet per microframe.
1215 * Specify zero for non high speed devices. This
1216 * value comes from the standard endpoint descriptor
1217 * field wMaxPacketSize bits <12:11>.
1218 * @hub_device_addr:
1219 * Hub device address this device is connected
1220 * to. Devices connected directly to Octeon
1221 * use zero. This is only used when the device
1222 * is full/low speed behind a high speed hub.
1223 * The address will be of the high speed hub,
1224 * not and full speed hubs after it.
1225 * @hub_port: Which port on the hub the device is
1226 * connected. Use zero for devices connected
1227 * directly to Octeon. Like hub_device_addr,
1228 * this is only used for full/low speed
1229 * devices behind a high speed hub.
1230 *
1231 * Returns: A non-NULL value is a pipe. NULL means an error.
1232 */
1233 static struct cvmx_usb_pipe *cvmx_usb_open_pipe(struct cvmx_usb_state *usb,
1234 int device_addr, int
1235 endpoint_num,
1236 enum cvmx_usb_speed
1237 device_speed,
1238 int max_packet,
1239 enum cvmx_usb_transfer
1240 transfer_type,
1241 enum cvmx_usb_direction
1242 transfer_dir,
1243 int interval, int multi_count,
1244 int hub_device_addr,
1245 int hub_port)
1246 {
1247 struct cvmx_usb_pipe *pipe;
1248
1249 if (unlikely((device_addr < 0) || (device_addr > MAX_USB_ADDRESS)))
1250 return NULL;
1251 if (unlikely((endpoint_num < 0) || (endpoint_num > MAX_USB_ENDPOINT)))
1252 return NULL;
1253 if (unlikely(device_speed > CVMX_USB_SPEED_LOW))
1254 return NULL;
1255 if (unlikely((max_packet <= 0) || (max_packet > 1024)))
1256 return NULL;
1257 if (unlikely(transfer_type > CVMX_USB_TRANSFER_INTERRUPT))
1258 return NULL;
1259 if (unlikely((transfer_dir != CVMX_USB_DIRECTION_OUT) &&
1260 (transfer_dir != CVMX_USB_DIRECTION_IN)))
1261 return NULL;
1262 if (unlikely(interval < 0))
1263 return NULL;
1264 if (unlikely((transfer_type == CVMX_USB_TRANSFER_CONTROL) && interval))
1265 return NULL;
1266 if (unlikely(multi_count < 0))
1267 return NULL;
1268 if (unlikely((device_speed != CVMX_USB_SPEED_HIGH) &&
1269 (multi_count != 0)))
1270 return NULL;
1271 if (unlikely((hub_device_addr < 0) || (hub_device_addr > MAX_USB_ADDRESS)))
1272 return NULL;
1273 if (unlikely((hub_port < 0) || (hub_port > MAX_USB_HUB_PORT)))
1274 return NULL;
1275
1276 /* Find a free pipe */
1277 pipe = usb->free_pipes.head;
1278 if (!pipe)
1279 return NULL;
1280 __cvmx_usb_remove_pipe(&usb->free_pipes, pipe);
1281 pipe->flags = __CVMX_USB_PIPE_FLAGS_OPEN;
1282 if ((device_speed == CVMX_USB_SPEED_HIGH) &&
1283 (transfer_dir == CVMX_USB_DIRECTION_OUT) &&
1284 (transfer_type == CVMX_USB_TRANSFER_BULK))
1285 pipe->flags |= __CVMX_USB_PIPE_FLAGS_NEED_PING;
1286 pipe->device_addr = device_addr;
1287 pipe->endpoint_num = endpoint_num;
1288 pipe->device_speed = device_speed;
1289 pipe->max_packet = max_packet;
1290 pipe->transfer_type = transfer_type;
1291 pipe->transfer_dir = transfer_dir;
1292 /*
1293 * All pipes use interval to rate limit NAK processing. Force an
1294 * interval if one wasn't supplied
1295 */
1296 if (!interval)
1297 interval = 1;
1298 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1299 pipe->interval = interval*8;
1300 /* Force start splits to be schedule on uFrame 0 */
1301 pipe->next_tx_frame = ((usb->frame_number+7)&~7) + pipe->interval;
1302 } else {
1303 pipe->interval = interval;
1304 pipe->next_tx_frame = usb->frame_number + pipe->interval;
1305 }
1306 pipe->multi_count = multi_count;
1307 pipe->hub_device_addr = hub_device_addr;
1308 pipe->hub_port = hub_port;
1309 pipe->pid_toggle = 0;
1310 pipe->split_sc_frame = -1;
1311 __cvmx_usb_append_pipe(&usb->idle_pipes, pipe);
1312
1313 /*
1314 * We don't need to tell the hardware about this pipe yet since
1315 * it doesn't have any submitted requests
1316 */
1317
1318 return pipe;
1319 }
1320
1321
1322 /**
1323 * Poll the RX FIFOs and remove data as needed. This function is only used
1324 * in non DMA mode. It is very important that this function be called quickly
1325 * enough to prevent FIFO overflow.
1326 *
1327 * @usb: USB device state populated by cvmx_usb_initialize().
1328 */
1329 static void __cvmx_usb_poll_rx_fifo(struct cvmx_usb_state *usb)
1330 {
1331 union cvmx_usbcx_grxstsph rx_status;
1332 int channel;
1333 int bytes;
1334 uint64_t address;
1335 uint32_t *ptr;
1336
1337 rx_status.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GRXSTSPH(usb->index));
1338 /* Only read data if IN data is there */
1339 if (rx_status.s.pktsts != 2)
1340 return;
1341 /* Check if no data is available */
1342 if (!rx_status.s.bcnt)
1343 return;
1344
1345 channel = rx_status.s.chnum;
1346 bytes = rx_status.s.bcnt;
1347 if (!bytes)
1348 return;
1349
1350 /* Get where the DMA engine would have written this data */
1351 address = __cvmx_usb_read_csr64(usb, CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8);
1352 ptr = cvmx_phys_to_ptr(address);
1353 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8, address + bytes);
1354
1355 /* Loop writing the FIFO data for this packet into memory */
1356 while (bytes > 0) {
1357 *ptr++ = __cvmx_usb_read_csr32(usb, USB_FIFO_ADDRESS(channel, usb->index));
1358 bytes -= 4;
1359 }
1360 CVMX_SYNCW;
1361
1362 return;
1363 }
1364
1365
1366 /**
1367 * Fill the TX hardware fifo with data out of the software
1368 * fifos
1369 *
1370 * @usb: USB device state populated by cvmx_usb_initialize().
1371 * @fifo: Software fifo to use
1372 * @available: Amount of space in the hardware fifo
1373 *
1374 * Returns: Non zero if the hardware fifo was too small and needs
1375 * to be serviced again.
1376 */
1377 static int __cvmx_usb_fill_tx_hw(struct cvmx_usb_state *usb,
1378 struct cvmx_usb_tx_fifo *fifo, int available)
1379 {
1380 /*
1381 * We're done either when there isn't anymore space or the software FIFO
1382 * is empty
1383 */
1384 while (available && (fifo->head != fifo->tail)) {
1385 int i = fifo->tail;
1386 const uint32_t *ptr = cvmx_phys_to_ptr(fifo->entry[i].address);
1387 uint64_t csr_address = USB_FIFO_ADDRESS(fifo->entry[i].channel, usb->index) ^ 4;
1388 int words = available;
1389
1390 /* Limit the amount of data to waht the SW fifo has */
1391 if (fifo->entry[i].size <= available) {
1392 words = fifo->entry[i].size;
1393 fifo->tail++;
1394 if (fifo->tail > MAX_CHANNELS)
1395 fifo->tail = 0;
1396 }
1397
1398 /* Update the next locations and counts */
1399 available -= words;
1400 fifo->entry[i].address += words * 4;
1401 fifo->entry[i].size -= words;
1402
1403 /*
1404 * Write the HW fifo data. The read every three writes is due
1405 * to an errata on CN3XXX chips
1406 */
1407 while (words > 3) {
1408 cvmx_write64_uint32(csr_address, *ptr++);
1409 cvmx_write64_uint32(csr_address, *ptr++);
1410 cvmx_write64_uint32(csr_address, *ptr++);
1411 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
1412 words -= 3;
1413 }
1414 cvmx_write64_uint32(csr_address, *ptr++);
1415 if (--words) {
1416 cvmx_write64_uint32(csr_address, *ptr++);
1417 if (--words)
1418 cvmx_write64_uint32(csr_address, *ptr++);
1419 }
1420 cvmx_read64_uint64(CVMX_USBNX_DMA0_INB_CHN0(usb->index));
1421 }
1422 return fifo->head != fifo->tail;
1423 }
1424
1425
1426 /**
1427 * Check the hardware FIFOs and fill them as needed
1428 *
1429 * @usb: USB device state populated by cvmx_usb_initialize().
1430 */
1431 static void __cvmx_usb_poll_tx_fifo(struct cvmx_usb_state *usb)
1432 {
1433 if (usb->periodic.head != usb->periodic.tail) {
1434 union cvmx_usbcx_hptxsts tx_status;
1435 tx_status.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPTXSTS(usb->index));
1436 if (__cvmx_usb_fill_tx_hw(usb, &usb->periodic, tx_status.s.ptxfspcavail))
1437 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk, ptxfempmsk, 1);
1438 else
1439 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk, ptxfempmsk, 0);
1440 }
1441
1442 if (usb->nonperiodic.head != usb->nonperiodic.tail) {
1443 union cvmx_usbcx_gnptxsts tx_status;
1444 tx_status.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GNPTXSTS(usb->index));
1445 if (__cvmx_usb_fill_tx_hw(usb, &usb->nonperiodic, tx_status.s.nptxfspcavail))
1446 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk, nptxfempmsk, 1);
1447 else
1448 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk, nptxfempmsk, 0);
1449 }
1450
1451 return;
1452 }
1453
1454
1455 /**
1456 * Fill the TX FIFO with an outgoing packet
1457 *
1458 * @usb: USB device state populated by cvmx_usb_initialize().
1459 * @channel: Channel number to get packet from
1460 */
1461 static void __cvmx_usb_fill_tx_fifo(struct cvmx_usb_state *usb, int channel)
1462 {
1463 union cvmx_usbcx_hccharx hcchar;
1464 union cvmx_usbcx_hcspltx usbc_hcsplt;
1465 union cvmx_usbcx_hctsizx usbc_hctsiz;
1466 struct cvmx_usb_tx_fifo *fifo;
1467
1468 /* We only need to fill data on outbound channels */
1469 hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index));
1470 if (hcchar.s.epdir != CVMX_USB_DIRECTION_OUT)
1471 return;
1472
1473 /* OUT Splits only have data on the start and not the complete */
1474 usbc_hcsplt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCSPLTX(channel, usb->index));
1475 if (usbc_hcsplt.s.spltena && usbc_hcsplt.s.compsplt)
1476 return;
1477
1478 /*
1479 * Find out how many bytes we need to fill and convert it into 32bit
1480 * words.
1481 */
1482 usbc_hctsiz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index));
1483 if (!usbc_hctsiz.s.xfersize)
1484 return;
1485
1486 if ((hcchar.s.eptype == CVMX_USB_TRANSFER_INTERRUPT) ||
1487 (hcchar.s.eptype == CVMX_USB_TRANSFER_ISOCHRONOUS))
1488 fifo = &usb->periodic;
1489 else
1490 fifo = &usb->nonperiodic;
1491
1492 fifo->entry[fifo->head].channel = channel;
1493 fifo->entry[fifo->head].address = __cvmx_usb_read_csr64(usb, CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8);
1494 fifo->entry[fifo->head].size = (usbc_hctsiz.s.xfersize+3)>>2;
1495 fifo->head++;
1496 if (fifo->head > MAX_CHANNELS)
1497 fifo->head = 0;
1498
1499 __cvmx_usb_poll_tx_fifo(usb);
1500
1501 return;
1502 }
1503
1504 /**
1505 * Perform channel specific setup for Control transactions. All
1506 * the generic stuff will already have been done in
1507 * __cvmx_usb_start_channel()
1508 *
1509 * @usb: USB device state populated by cvmx_usb_initialize().
1510 * @channel: Channel to setup
1511 * @pipe: Pipe for control transaction
1512 */
1513 static void __cvmx_usb_start_channel_control(struct cvmx_usb_state *usb,
1514 int channel,
1515 struct cvmx_usb_pipe *pipe)
1516 {
1517 struct cvmx_usb_transaction *transaction = pipe->head;
1518 union cvmx_usb_control_header *header =
1519 cvmx_phys_to_ptr(transaction->control_header);
1520 int bytes_to_transfer = transaction->buffer_length - transaction->actual_bytes;
1521 int packets_to_transfer;
1522 union cvmx_usbcx_hctsizx usbc_hctsiz;
1523
1524 usbc_hctsiz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index));
1525
1526 switch (transaction->stage) {
1527 case CVMX_USB_STAGE_NON_CONTROL:
1528 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE:
1529 cvmx_dprintf("%s: ERROR - Non control stage\n", __FUNCTION__);
1530 break;
1531 case CVMX_USB_STAGE_SETUP:
1532 usbc_hctsiz.s.pid = 3; /* Setup */
1533 bytes_to_transfer = sizeof(*header);
1534 /* All Control operations start with a setup going OUT */
1535 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), union cvmx_usbcx_hccharx, epdir, CVMX_USB_DIRECTION_OUT);
1536 /*
1537 * Setup send the control header instead of the buffer data. The
1538 * buffer data will be used in the next stage
1539 */
1540 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8, transaction->control_header);
1541 break;
1542 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE:
1543 usbc_hctsiz.s.pid = 3; /* Setup */
1544 bytes_to_transfer = 0;
1545 /* All Control operations start with a setup going OUT */
1546 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), union cvmx_usbcx_hccharx, epdir, CVMX_USB_DIRECTION_OUT);
1547 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), union cvmx_usbcx_hcspltx, compsplt, 1);
1548 break;
1549 case CVMX_USB_STAGE_DATA:
1550 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1551 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1552 if (header->s.request_type & 0x80)
1553 bytes_to_transfer = 0;
1554 else if (bytes_to_transfer > pipe->max_packet)
1555 bytes_to_transfer = pipe->max_packet;
1556 }
1557 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1558 union cvmx_usbcx_hccharx, epdir,
1559 ((header->s.request_type & 0x80) ?
1560 CVMX_USB_DIRECTION_IN :
1561 CVMX_USB_DIRECTION_OUT));
1562 break;
1563 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE:
1564 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1565 if (!(header->s.request_type & 0x80))
1566 bytes_to_transfer = 0;
1567 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index),
1568 union cvmx_usbcx_hccharx, epdir,
1569 ((header->s.request_type & 0x80) ?
1570 CVMX_USB_DIRECTION_IN :
1571 CVMX_USB_DIRECTION_OUT));
1572 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), union cvmx_usbcx_hcspltx, compsplt, 1);
1573 break;
1574 case CVMX_USB_STAGE_STATUS:
1575 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1576 bytes_to_transfer = 0;
1577 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), union cvmx_usbcx_hccharx, epdir,
1578 ((header->s.request_type & 0x80) ?
1579 CVMX_USB_DIRECTION_OUT :
1580 CVMX_USB_DIRECTION_IN));
1581 break;
1582 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE:
1583 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1584 bytes_to_transfer = 0;
1585 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), union cvmx_usbcx_hccharx, epdir,
1586 ((header->s.request_type & 0x80) ?
1587 CVMX_USB_DIRECTION_OUT :
1588 CVMX_USB_DIRECTION_IN));
1589 USB_SET_FIELD32(CVMX_USBCX_HCSPLTX(channel, usb->index), union cvmx_usbcx_hcspltx, compsplt, 1);
1590 break;
1591 }
1592
1593 /*
1594 * Make sure the transfer never exceeds the byte limit of the hardware.
1595 * Further bytes will be sent as continued transactions
1596 */
1597 if (bytes_to_transfer > MAX_TRANSFER_BYTES) {
1598 /* Round MAX_TRANSFER_BYTES to a multiple of out packet size */
1599 bytes_to_transfer = MAX_TRANSFER_BYTES / pipe->max_packet;
1600 bytes_to_transfer *= pipe->max_packet;
1601 }
1602
1603 /*
1604 * Calculate the number of packets to transfer. If the length is zero
1605 * we still need to transfer one packet
1606 */
1607 packets_to_transfer = (bytes_to_transfer + pipe->max_packet - 1) / pipe->max_packet;
1608 if (packets_to_transfer == 0)
1609 packets_to_transfer = 1;
1610 else if ((packets_to_transfer > 1) && (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)) {
1611 /*
1612 * Limit to one packet when not using DMA. Channels must be
1613 * restarted between every packet for IN transactions, so there
1614 * is no reason to do multiple packets in a row
1615 */
1616 packets_to_transfer = 1;
1617 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1618 } else if (packets_to_transfer > MAX_TRANSFER_PACKETS) {
1619 /*
1620 * Limit the number of packet and data transferred to what the
1621 * hardware can handle
1622 */
1623 packets_to_transfer = MAX_TRANSFER_PACKETS;
1624 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1625 }
1626
1627 usbc_hctsiz.s.xfersize = bytes_to_transfer;
1628 usbc_hctsiz.s.pktcnt = packets_to_transfer;
1629
1630 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index), usbc_hctsiz.u32);
1631 return;
1632 }
1633
1634
1635 /**
1636 * Start a channel to perform the pipe's head transaction
1637 *
1638 * @usb: USB device state populated by cvmx_usb_initialize().
1639 * @channel: Channel to setup
1640 * @pipe: Pipe to start
1641 */
1642 static void __cvmx_usb_start_channel(struct cvmx_usb_state *usb,
1643 int channel,
1644 struct cvmx_usb_pipe *pipe)
1645 {
1646 struct cvmx_usb_transaction *transaction = pipe->head;
1647
1648 /* Make sure all writes to the DMA region get flushed */
1649 CVMX_SYNCW;
1650
1651 /* Attach the channel to the pipe */
1652 usb->pipe_for_channel[channel] = pipe;
1653 pipe->channel = channel;
1654 pipe->flags |= __CVMX_USB_PIPE_FLAGS_SCHEDULED;
1655
1656 /* Mark this channel as in use */
1657 usb->idle_hardware_channels &= ~(1<<channel);
1658
1659 /* Enable the channel interrupt bits */
1660 {
1661 union cvmx_usbcx_hcintx usbc_hcint;
1662 union cvmx_usbcx_hcintmskx usbc_hcintmsk;
1663 union cvmx_usbcx_haintmsk usbc_haintmsk;
1664
1665 /* Clear all channel status bits */
1666 usbc_hcint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCINTX(channel, usb->index));
1667 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTX(channel, usb->index), usbc_hcint.u32);
1668
1669 usbc_hcintmsk.u32 = 0;
1670 usbc_hcintmsk.s.chhltdmsk = 1;
1671 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) {
1672 /*
1673 * Channels need these extra interrupts when we aren't
1674 * in DMA mode.
1675 */
1676 usbc_hcintmsk.s.datatglerrmsk = 1;
1677 usbc_hcintmsk.s.frmovrunmsk = 1;
1678 usbc_hcintmsk.s.bblerrmsk = 1;
1679 usbc_hcintmsk.s.xacterrmsk = 1;
1680 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1681 /*
1682 * Splits don't generate xfercompl, so we need
1683 * ACK and NYET.
1684 */
1685 usbc_hcintmsk.s.nyetmsk = 1;
1686 usbc_hcintmsk.s.ackmsk = 1;
1687 }
1688 usbc_hcintmsk.s.nakmsk = 1;
1689 usbc_hcintmsk.s.stallmsk = 1;
1690 usbc_hcintmsk.s.xfercomplmsk = 1;
1691 }
1692 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), usbc_hcintmsk.u32);
1693
1694 /* Enable the channel interrupt to propagate */
1695 usbc_haintmsk.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HAINTMSK(usb->index));
1696 usbc_haintmsk.s.haintmsk |= 1<<channel;
1697 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HAINTMSK(usb->index), usbc_haintmsk.u32);
1698 }
1699
1700 /* Setup the locations the DMA engines use */
1701 {
1702 uint64_t dma_address = transaction->buffer + transaction->actual_bytes;
1703 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
1704 dma_address = transaction->buffer + transaction->iso_packets[0].offset + transaction->actual_bytes;
1705 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_OUTB_CHN0(usb->index) + channel*8, dma_address);
1706 __cvmx_usb_write_csr64(usb, CVMX_USBNX_DMA0_INB_CHN0(usb->index) + channel*8, dma_address);
1707 }
1708
1709 /* Setup both the size of the transfer and the SPLIT characteristics */
1710 {
1711 union cvmx_usbcx_hcspltx usbc_hcsplt = {.u32 = 0};
1712 union cvmx_usbcx_hctsizx usbc_hctsiz = {.u32 = 0};
1713 int packets_to_transfer;
1714 int bytes_to_transfer = transaction->buffer_length - transaction->actual_bytes;
1715
1716 /*
1717 * ISOCHRONOUS transactions store each individual transfer size
1718 * in the packet structure, not the global buffer_length
1719 */
1720 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
1721 bytes_to_transfer = transaction->iso_packets[0].length - transaction->actual_bytes;
1722
1723 /*
1724 * We need to do split transactions when we are talking to non
1725 * high speed devices that are behind a high speed hub
1726 */
1727 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
1728 /*
1729 * On the start split phase (stage is even) record the
1730 * frame number we will need to send the split complete.
1731 * We only store the lower two bits since the time ahead
1732 * can only be two frames
1733 */
1734 if ((transaction->stage&1) == 0) {
1735 if (transaction->type == CVMX_USB_TRANSFER_BULK)
1736 pipe->split_sc_frame = (usb->frame_number + 1) & 0x7f;
1737 else
1738 pipe->split_sc_frame = (usb->frame_number + 2) & 0x7f;
1739 } else
1740 pipe->split_sc_frame = -1;
1741
1742 usbc_hcsplt.s.spltena = 1;
1743 usbc_hcsplt.s.hubaddr = pipe->hub_device_addr;
1744 usbc_hcsplt.s.prtaddr = pipe->hub_port;
1745 usbc_hcsplt.s.compsplt = (transaction->stage == CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE);
1746
1747 /*
1748 * SPLIT transactions can only ever transmit one data
1749 * packet so limit the transfer size to the max packet
1750 * size
1751 */
1752 if (bytes_to_transfer > pipe->max_packet)
1753 bytes_to_transfer = pipe->max_packet;
1754
1755 /*
1756 * ISOCHRONOUS OUT splits are unique in that they limit
1757 * data transfers to 188 byte chunks representing the
1758 * begin/middle/end of the data or all
1759 */
1760 if (!usbc_hcsplt.s.compsplt &&
1761 (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) &&
1762 (pipe->transfer_type == CVMX_USB_TRANSFER_ISOCHRONOUS)) {
1763 /*
1764 * Clear the split complete frame number as
1765 * there isn't going to be a split complete
1766 */
1767 pipe->split_sc_frame = -1;
1768 /*
1769 * See if we've started this transfer and sent
1770 * data
1771 */
1772 if (transaction->actual_bytes == 0) {
1773 /*
1774 * Nothing sent yet, this is either a
1775 * begin or the entire payload
1776 */
1777 if (bytes_to_transfer <= 188)
1778 /* Entire payload in one go */
1779 usbc_hcsplt.s.xactpos = 3;
1780 else
1781 /* First part of payload */
1782 usbc_hcsplt.s.xactpos = 2;
1783 } else {
1784 /*
1785 * Continuing the previous data, we must
1786 * either be in the middle or at the end
1787 */
1788 if (bytes_to_transfer <= 188)
1789 /* End of payload */
1790 usbc_hcsplt.s.xactpos = 1;
1791 else
1792 /* Middle of payload */
1793 usbc_hcsplt.s.xactpos = 0;
1794 }
1795 /*
1796 * Again, the transfer size is limited to 188
1797 * bytes
1798 */
1799 if (bytes_to_transfer > 188)
1800 bytes_to_transfer = 188;
1801 }
1802 }
1803
1804 /*
1805 * Make sure the transfer never exceeds the byte limit of the
1806 * hardware. Further bytes will be sent as continued
1807 * transactions
1808 */
1809 if (bytes_to_transfer > MAX_TRANSFER_BYTES) {
1810 /*
1811 * Round MAX_TRANSFER_BYTES to a multiple of out packet
1812 * size
1813 */
1814 bytes_to_transfer = MAX_TRANSFER_BYTES / pipe->max_packet;
1815 bytes_to_transfer *= pipe->max_packet;
1816 }
1817
1818 /*
1819 * Calculate the number of packets to transfer. If the length is
1820 * zero we still need to transfer one packet
1821 */
1822 packets_to_transfer = (bytes_to_transfer + pipe->max_packet - 1) / pipe->max_packet;
1823 if (packets_to_transfer == 0)
1824 packets_to_transfer = 1;
1825 else if ((packets_to_transfer > 1) && (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)) {
1826 /*
1827 * Limit to one packet when not using DMA. Channels must
1828 * be restarted between every packet for IN
1829 * transactions, so there is no reason to do multiple
1830 * packets in a row
1831 */
1832 packets_to_transfer = 1;
1833 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1834 } else if (packets_to_transfer > MAX_TRANSFER_PACKETS) {
1835 /*
1836 * Limit the number of packet and data transferred to
1837 * what the hardware can handle
1838 */
1839 packets_to_transfer = MAX_TRANSFER_PACKETS;
1840 bytes_to_transfer = packets_to_transfer * pipe->max_packet;
1841 }
1842
1843 usbc_hctsiz.s.xfersize = bytes_to_transfer;
1844 usbc_hctsiz.s.pktcnt = packets_to_transfer;
1845
1846 /* Update the DATA0/DATA1 toggle */
1847 usbc_hctsiz.s.pid = __cvmx_usb_get_data_pid(pipe);
1848 /*
1849 * High speed pipes may need a hardware ping before they start
1850 */
1851 if (pipe->flags & __CVMX_USB_PIPE_FLAGS_NEED_PING)
1852 usbc_hctsiz.s.dopng = 1;
1853
1854 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCSPLTX(channel, usb->index), usbc_hcsplt.u32);
1855 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index), usbc_hctsiz.u32);
1856 }
1857
1858 /* Setup the Host Channel Characteristics Register */
1859 {
1860 union cvmx_usbcx_hccharx usbc_hcchar = {.u32 = 0};
1861
1862 /*
1863 * Set the startframe odd/even properly. This is only used for
1864 * periodic
1865 */
1866 usbc_hcchar.s.oddfrm = usb->frame_number&1;
1867
1868 /*
1869 * Set the number of back to back packets allowed by this
1870 * endpoint. Split transactions interpret "ec" as the number of
1871 * immediate retries of failure. These retries happen too
1872 * quickly, so we disable these entirely for splits
1873 */
1874 if (__cvmx_usb_pipe_needs_split(usb, pipe))
1875 usbc_hcchar.s.ec = 1;
1876 else if (pipe->multi_count < 1)
1877 usbc_hcchar.s.ec = 1;
1878 else if (pipe->multi_count > 3)
1879 usbc_hcchar.s.ec = 3;
1880 else
1881 usbc_hcchar.s.ec = pipe->multi_count;
1882
1883 /* Set the rest of the endpoint specific settings */
1884 usbc_hcchar.s.devaddr = pipe->device_addr;
1885 usbc_hcchar.s.eptype = transaction->type;
1886 usbc_hcchar.s.lspddev = (pipe->device_speed == CVMX_USB_SPEED_LOW);
1887 usbc_hcchar.s.epdir = pipe->transfer_dir;
1888 usbc_hcchar.s.epnum = pipe->endpoint_num;
1889 usbc_hcchar.s.mps = pipe->max_packet;
1890 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index), usbc_hcchar.u32);
1891 }
1892
1893 /* Do transaction type specific fixups as needed */
1894 switch (transaction->type) {
1895 case CVMX_USB_TRANSFER_CONTROL:
1896 __cvmx_usb_start_channel_control(usb, channel, pipe);
1897 break;
1898 case CVMX_USB_TRANSFER_BULK:
1899 case CVMX_USB_TRANSFER_INTERRUPT:
1900 break;
1901 case CVMX_USB_TRANSFER_ISOCHRONOUS:
1902 if (!__cvmx_usb_pipe_needs_split(usb, pipe)) {
1903 /*
1904 * ISO transactions require different PIDs depending on
1905 * direction and how many packets are needed
1906 */
1907 if (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) {
1908 if (pipe->multi_count < 2) /* Need DATA0 */
1909 USB_SET_FIELD32(CVMX_USBCX_HCTSIZX(channel, usb->index), union cvmx_usbcx_hctsizx, pid, 0);
1910 else /* Need MDATA */
1911 USB_SET_FIELD32(CVMX_USBCX_HCTSIZX(channel, usb->index), union cvmx_usbcx_hctsizx, pid, 3);
1912 }
1913 }
1914 break;
1915 }
1916 {
1917 union cvmx_usbcx_hctsizx usbc_hctsiz = {.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index))};
1918 transaction->xfersize = usbc_hctsiz.s.xfersize;
1919 transaction->pktcnt = usbc_hctsiz.s.pktcnt;
1920 }
1921 /* Remeber when we start a split transaction */
1922 if (__cvmx_usb_pipe_needs_split(usb, pipe))
1923 usb->active_split = transaction;
1924 USB_SET_FIELD32(CVMX_USBCX_HCCHARX(channel, usb->index), union cvmx_usbcx_hccharx, chena, 1);
1925 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
1926 __cvmx_usb_fill_tx_fifo(usb, channel);
1927 return;
1928 }
1929
1930
1931 /**
1932 * Find a pipe that is ready to be scheduled to hardware.
1933 * @usb: USB device state populated by cvmx_usb_initialize().
1934 * @list: Pipe list to search
1935 * @current_frame:
1936 * Frame counter to use as a time reference.
1937 *
1938 * Returns: Pipe or NULL if none are ready
1939 */
1940 static struct cvmx_usb_pipe *__cvmx_usb_find_ready_pipe(struct cvmx_usb_state *usb, struct cvmx_usb_pipe_list *list, uint64_t current_frame)
1941 {
1942 struct cvmx_usb_pipe *pipe = list->head;
1943 while (pipe) {
1944 if (!(pipe->flags & __CVMX_USB_PIPE_FLAGS_SCHEDULED) && pipe->head &&
1945 (pipe->next_tx_frame <= current_frame) &&
1946 ((pipe->split_sc_frame == -1) || ((((int)current_frame - (int)pipe->split_sc_frame) & 0x7f) < 0x40)) &&
1947 (!usb->active_split || (usb->active_split == pipe->head))) {
1948 CVMX_PREFETCH(pipe, 128);
1949 CVMX_PREFETCH(pipe->head, 0);
1950 return pipe;
1951 }
1952 pipe = pipe->next;
1953 }
1954 return NULL;
1955 }
1956
1957
1958 /**
1959 * Called whenever a pipe might need to be scheduled to the
1960 * hardware.
1961 *
1962 * @usb: USB device state populated by cvmx_usb_initialize().
1963 * @is_sof: True if this schedule was called on a SOF interrupt.
1964 */
1965 static void __cvmx_usb_schedule(struct cvmx_usb_state *usb, int is_sof)
1966 {
1967 int channel;
1968 struct cvmx_usb_pipe *pipe;
1969 int need_sof;
1970 enum cvmx_usb_transfer ttype;
1971
1972 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) {
1973 /*
1974 * Without DMA we need to be careful to not schedule something
1975 * at the end of a frame and cause an overrun.
1976 */
1977 union cvmx_usbcx_hfnum hfnum = {.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index))};
1978 union cvmx_usbcx_hfir hfir = {.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFIR(usb->index))};
1979 if (hfnum.s.frrem < hfir.s.frint/4)
1980 goto done;
1981 }
1982
1983 while (usb->idle_hardware_channels) {
1984 /* Find an idle channel */
1985 channel = __fls(usb->idle_hardware_channels);
1986 if (unlikely(channel > 7))
1987 break;
1988
1989 /* Find a pipe needing service */
1990 pipe = NULL;
1991 if (is_sof) {
1992 /*
1993 * Only process periodic pipes on SOF interrupts. This
1994 * way we are sure that the periodic data is sent in the
1995 * beginning of the frame
1996 */
1997 pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_ISOCHRONOUS, usb->frame_number);
1998 if (likely(!pipe))
1999 pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_INTERRUPT, usb->frame_number);
2000 }
2001 if (likely(!pipe)) {
2002 pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_CONTROL, usb->frame_number);
2003 if (likely(!pipe))
2004 pipe = __cvmx_usb_find_ready_pipe(usb, usb->active_pipes + CVMX_USB_TRANSFER_BULK, usb->frame_number);
2005 }
2006 if (!pipe)
2007 break;
2008
2009 __cvmx_usb_start_channel(usb, channel, pipe);
2010 }
2011
2012 done:
2013 /*
2014 * Only enable SOF interrupts when we have transactions pending in the
2015 * future that might need to be scheduled
2016 */
2017 need_sof = 0;
2018 for (ttype = CVMX_USB_TRANSFER_CONTROL; ttype <= CVMX_USB_TRANSFER_INTERRUPT; ttype++) {
2019 pipe = usb->active_pipes[ttype].head;
2020 while (pipe) {
2021 if (pipe->next_tx_frame > usb->frame_number) {
2022 need_sof = 1;
2023 break;
2024 }
2025 pipe = pipe->next;
2026 }
2027 }
2028 USB_SET_FIELD32(CVMX_USBCX_GINTMSK(usb->index), union cvmx_usbcx_gintmsk, sofmsk, need_sof);
2029 return;
2030 }
2031
2032 static inline struct octeon_hcd *cvmx_usb_to_octeon(struct cvmx_usb_state *p)
2033 {
2034 return container_of(p, struct octeon_hcd, usb);
2035 }
2036
2037 static inline struct usb_hcd *octeon_to_hcd(struct octeon_hcd *p)
2038 {
2039 return container_of((void *)p, struct usb_hcd, hcd_priv);
2040 }
2041
2042 static void octeon_usb_urb_complete_callback(struct cvmx_usb_state *usb,
2043 enum cvmx_usb_complete status,
2044 struct cvmx_usb_pipe *pipe,
2045 struct cvmx_usb_transaction
2046 *transaction,
2047 int bytes_transferred,
2048 struct urb *urb)
2049 {
2050 struct octeon_hcd *priv = cvmx_usb_to_octeon(usb);
2051 struct usb_hcd *hcd = octeon_to_hcd(priv);
2052 struct device *dev = hcd->self.controller;
2053
2054 urb->actual_length = bytes_transferred;
2055 urb->hcpriv = NULL;
2056
2057 if (!list_empty(&urb->urb_list)) {
2058 /*
2059 * It is on the dequeue_list, but we are going to call
2060 * usb_hcd_giveback_urb(), so we must clear it from
2061 * the list. We got to it before the
2062 * octeon_usb_urb_dequeue_work() tasklet did.
2063 */
2064 list_del(&urb->urb_list);
2065 /* No longer on the dequeue_list. */
2066 INIT_LIST_HEAD(&urb->urb_list);
2067 }
2068
2069 /* For Isochronous transactions we need to update the URB packet status
2070 list from data in our private copy */
2071 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2072 int i;
2073 /*
2074 * The pointer to the private list is stored in the setup_packet
2075 * field.
2076 */
2077 struct cvmx_usb_iso_packet *iso_packet =
2078 (struct cvmx_usb_iso_packet *) urb->setup_packet;
2079 /* Recalculate the transfer size by adding up each packet */
2080 urb->actual_length = 0;
2081 for (i = 0; i < urb->number_of_packets; i++) {
2082 if (iso_packet[i].status == CVMX_USB_COMPLETE_SUCCESS) {
2083 urb->iso_frame_desc[i].status = 0;
2084 urb->iso_frame_desc[i].actual_length = iso_packet[i].length;
2085 urb->actual_length += urb->iso_frame_desc[i].actual_length;
2086 } else {
2087 dev_dbg(dev, "ISOCHRONOUS packet=%d of %d status=%d pipe=%p transaction=%p size=%d\n",
2088 i, urb->number_of_packets,
2089 iso_packet[i].status, pipe,
2090 transaction, iso_packet[i].length);
2091 urb->iso_frame_desc[i].status = -EREMOTEIO;
2092 }
2093 }
2094 /* Free the private list now that we don't need it anymore */
2095 kfree(iso_packet);
2096 urb->setup_packet = NULL;
2097 }
2098
2099 switch (status) {
2100 case CVMX_USB_COMPLETE_SUCCESS:
2101 urb->status = 0;
2102 break;
2103 case CVMX_USB_COMPLETE_CANCEL:
2104 if (urb->status == 0)
2105 urb->status = -ENOENT;
2106 break;
2107 case CVMX_USB_COMPLETE_STALL:
2108 dev_dbg(dev, "status=stall pipe=%p transaction=%p size=%d\n",
2109 pipe, transaction, bytes_transferred);
2110 urb->status = -EPIPE;
2111 break;
2112 case CVMX_USB_COMPLETE_BABBLEERR:
2113 dev_dbg(dev, "status=babble pipe=%p transaction=%p size=%d\n",
2114 pipe, transaction, bytes_transferred);
2115 urb->status = -EPIPE;
2116 break;
2117 case CVMX_USB_COMPLETE_SHORT:
2118 dev_dbg(dev, "status=short pipe=%p transaction=%p size=%d\n",
2119 pipe, transaction, bytes_transferred);
2120 urb->status = -EREMOTEIO;
2121 break;
2122 case CVMX_USB_COMPLETE_ERROR:
2123 case CVMX_USB_COMPLETE_XACTERR:
2124 case CVMX_USB_COMPLETE_DATATGLERR:
2125 case CVMX_USB_COMPLETE_FRAMEERR:
2126 dev_dbg(dev, "status=%d pipe=%p transaction=%p size=%d\n",
2127 status, pipe, transaction, bytes_transferred);
2128 urb->status = -EPROTO;
2129 break;
2130 }
2131 spin_unlock(&priv->lock);
2132 usb_hcd_giveback_urb(octeon_to_hcd(priv), urb, urb->status);
2133 spin_lock(&priv->lock);
2134 }
2135
2136 /**
2137 * Signal the completion of a transaction and free it. The
2138 * transaction will be removed from the pipe transaction list.
2139 *
2140 * @usb: USB device state populated by cvmx_usb_initialize().
2141 * @pipe: Pipe the transaction is on
2142 * @transaction:
2143 * Transaction that completed
2144 * @complete_code:
2145 * Completion code
2146 */
2147 static void __cvmx_usb_perform_complete(struct cvmx_usb_state *usb,
2148 struct cvmx_usb_pipe *pipe,
2149 struct cvmx_usb_transaction *transaction,
2150 enum cvmx_usb_complete complete_code)
2151 {
2152 /* If this was a split then clear our split in progress marker */
2153 if (usb->active_split == transaction)
2154 usb->active_split = NULL;
2155
2156 /*
2157 * Isochronous transactions need extra processing as they might not be
2158 * done after a single data transfer
2159 */
2160 if (unlikely(transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)) {
2161 /* Update the number of bytes transferred in this ISO packet */
2162 transaction->iso_packets[0].length = transaction->actual_bytes;
2163 transaction->iso_packets[0].status = complete_code;
2164
2165 /*
2166 * If there are more ISOs pending and we succeeded, schedule the
2167 * next one
2168 */
2169 if ((transaction->iso_number_packets > 1) && (complete_code == CVMX_USB_COMPLETE_SUCCESS)) {
2170 /* No bytes transferred for this packet as of yet */
2171 transaction->actual_bytes = 0;
2172 /* One less ISO waiting to transfer */
2173 transaction->iso_number_packets--;
2174 /* Increment to the next location in our packet array */
2175 transaction->iso_packets++;
2176 transaction->stage = CVMX_USB_STAGE_NON_CONTROL;
2177 goto done;
2178 }
2179 }
2180
2181 /* Remove the transaction from the pipe list */
2182 if (transaction->next)
2183 transaction->next->prev = transaction->prev;
2184 else
2185 pipe->tail = transaction->prev;
2186 if (transaction->prev)
2187 transaction->prev->next = transaction->next;
2188 else
2189 pipe->head = transaction->next;
2190 if (!pipe->head) {
2191 __cvmx_usb_remove_pipe(usb->active_pipes + pipe->transfer_type, pipe);
2192 __cvmx_usb_append_pipe(&usb->idle_pipes, pipe);
2193
2194 }
2195 octeon_usb_urb_complete_callback(usb, complete_code, pipe,
2196 transaction,
2197 transaction->actual_bytes,
2198 transaction->urb);
2199 kfree(transaction);
2200 done:
2201 return;
2202 }
2203
2204
2205 /**
2206 * Submit a usb transaction to a pipe. Called for all types
2207 * of transactions.
2208 *
2209 * @usb:
2210 * @pipe: Which pipe to submit to.
2211 * @type: Transaction type
2212 * @buffer: User buffer for the transaction
2213 * @buffer_length:
2214 * User buffer's length in bytes
2215 * @control_header:
2216 * For control transactions, the 8 byte standard header
2217 * @iso_start_frame:
2218 * For ISO transactions, the start frame
2219 * @iso_number_packets:
2220 * For ISO, the number of packet in the transaction.
2221 * @iso_packets:
2222 * A description of each ISO packet
2223 * @urb: URB for the callback
2224 *
2225 * Returns: Transaction or NULL on failure.
2226 */
2227 static struct cvmx_usb_transaction *__cvmx_usb_submit_transaction(struct cvmx_usb_state *usb,
2228 struct cvmx_usb_pipe *pipe,
2229 enum cvmx_usb_transfer type,
2230 uint64_t buffer,
2231 int buffer_length,
2232 uint64_t control_header,
2233 int iso_start_frame,
2234 int iso_number_packets,
2235 struct cvmx_usb_iso_packet *iso_packets,
2236 struct urb *urb)
2237 {
2238 struct cvmx_usb_transaction *transaction;
2239
2240 /* Fail if the pipe isn't open */
2241 if (unlikely((pipe->flags & __CVMX_USB_PIPE_FLAGS_OPEN) == 0))
2242 return NULL;
2243 if (unlikely(pipe->transfer_type != type))
2244 return NULL;
2245
2246 transaction = kzalloc(sizeof(*transaction), GFP_ATOMIC);
2247 if (unlikely(!transaction))
2248 return NULL;
2249
2250 transaction->type = type;
2251 transaction->buffer = buffer;
2252 transaction->buffer_length = buffer_length;
2253 transaction->control_header = control_header;
2254 /* FIXME: This is not used, implement it. */
2255 transaction->iso_start_frame = iso_start_frame;
2256 transaction->iso_number_packets = iso_number_packets;
2257 transaction->iso_packets = iso_packets;
2258 transaction->urb = urb;
2259 if (transaction->type == CVMX_USB_TRANSFER_CONTROL)
2260 transaction->stage = CVMX_USB_STAGE_SETUP;
2261 else
2262 transaction->stage = CVMX_USB_STAGE_NON_CONTROL;
2263
2264 transaction->next = NULL;
2265 if (pipe->tail) {
2266 transaction->prev = pipe->tail;
2267 transaction->prev->next = transaction;
2268 } else {
2269 if (pipe->next_tx_frame < usb->frame_number)
2270 pipe->next_tx_frame = usb->frame_number + pipe->interval -
2271 (usb->frame_number - pipe->next_tx_frame) % pipe->interval;
2272 transaction->prev = NULL;
2273 pipe->head = transaction;
2274 __cvmx_usb_remove_pipe(&usb->idle_pipes, pipe);
2275 __cvmx_usb_append_pipe(usb->active_pipes + pipe->transfer_type, pipe);
2276 }
2277 pipe->tail = transaction;
2278
2279 /* We may need to schedule the pipe if this was the head of the pipe */
2280 if (!transaction->prev)
2281 __cvmx_usb_schedule(usb, 0);
2282
2283 return transaction;
2284 }
2285
2286
2287 /**
2288 * Call to submit a USB Bulk transfer to a pipe.
2289 *
2290 * @usb: USB device state populated by cvmx_usb_initialize().
2291 * @pipe: Handle to the pipe for the transfer.
2292 * @urb: URB.
2293 *
2294 * Returns: A submitted transaction or NULL on failure.
2295 */
2296 static struct cvmx_usb_transaction *cvmx_usb_submit_bulk(struct cvmx_usb_state *usb,
2297 struct cvmx_usb_pipe *pipe,
2298 struct urb *urb)
2299 {
2300 return __cvmx_usb_submit_transaction(usb, pipe, CVMX_USB_TRANSFER_BULK,
2301 urb->transfer_dma,
2302 urb->transfer_buffer_length,
2303 0, /* control_header */
2304 0, /* iso_start_frame */
2305 0, /* iso_number_packets */
2306 NULL, /* iso_packets */
2307 urb);
2308 }
2309
2310
2311 /**
2312 * Call to submit a USB Interrupt transfer to a pipe.
2313 *
2314 * @usb: USB device state populated by cvmx_usb_initialize().
2315 * @pipe: Handle to the pipe for the transfer.
2316 * @urb: URB returned when the callback is called.
2317 *
2318 * Returns: A submitted transaction or NULL on failure.
2319 */
2320 static struct cvmx_usb_transaction *cvmx_usb_submit_interrupt(struct cvmx_usb_state *usb,
2321 struct cvmx_usb_pipe *pipe,
2322 struct urb *urb)
2323 {
2324 return __cvmx_usb_submit_transaction(usb, pipe,
2325 CVMX_USB_TRANSFER_INTERRUPT,
2326 urb->transfer_dma,
2327 urb->transfer_buffer_length,
2328 0, /* control_header */
2329 0, /* iso_start_frame */
2330 0, /* iso_number_packets */
2331 NULL, /* iso_packets */
2332 urb);
2333 }
2334
2335
2336 /**
2337 * Call to submit a USB Control transfer to a pipe.
2338 *
2339 * @usb: USB device state populated by cvmx_usb_initialize().
2340 * @pipe: Handle to the pipe for the transfer.
2341 * @urb: URB.
2342 *
2343 * Returns: A submitted transaction or NULL on failure.
2344 */
2345 static struct cvmx_usb_transaction *cvmx_usb_submit_control(struct cvmx_usb_state *usb,
2346 struct cvmx_usb_pipe *pipe,
2347 struct urb *urb)
2348 {
2349 int buffer_length = urb->transfer_buffer_length;
2350 uint64_t control_header = urb->setup_dma;
2351 union cvmx_usb_control_header *header =
2352 cvmx_phys_to_ptr(control_header);
2353
2354 if ((header->s.request_type & 0x80) == 0)
2355 buffer_length = le16_to_cpu(header->s.length);
2356
2357 return __cvmx_usb_submit_transaction(usb, pipe,
2358 CVMX_USB_TRANSFER_CONTROL,
2359 urb->transfer_dma, buffer_length,
2360 control_header,
2361 0, /* iso_start_frame */
2362 0, /* iso_number_packets */
2363 NULL, /* iso_packets */
2364 urb);
2365 }
2366
2367
2368 /**
2369 * Call to submit a USB Isochronous transfer to a pipe.
2370 *
2371 * @usb: USB device state populated by cvmx_usb_initialize().
2372 * @pipe: Handle to the pipe for the transfer.
2373 * @urb: URB returned when the callback is called.
2374 *
2375 * Returns: A submitted transaction or NULL on failure.
2376 */
2377 static struct cvmx_usb_transaction *cvmx_usb_submit_isochronous(struct cvmx_usb_state *usb,
2378 struct cvmx_usb_pipe *pipe,
2379 struct urb *urb)
2380 {
2381 struct cvmx_usb_iso_packet *packets;
2382
2383 packets = (struct cvmx_usb_iso_packet *) urb->setup_packet;
2384 return __cvmx_usb_submit_transaction(usb, pipe,
2385 CVMX_USB_TRANSFER_ISOCHRONOUS,
2386 urb->transfer_dma,
2387 urb->transfer_buffer_length,
2388 0, /* control_header */
2389 urb->start_frame,
2390 urb->number_of_packets,
2391 packets, urb);
2392 }
2393
2394
2395 /**
2396 * Cancel one outstanding request in a pipe. Canceling a request
2397 * can fail if the transaction has already completed before cancel
2398 * is called. Even after a successful cancel call, it may take
2399 * a frame or two for the cvmx_usb_poll() function to call the
2400 * associated callback.
2401 *
2402 * @usb: USB device state populated by cvmx_usb_initialize().
2403 * @pipe: Pipe to cancel requests in.
2404 * @transaction: Transaction to cancel, returned by the submit function.
2405 *
2406 * Returns: 0 or a negative error code.
2407 */
2408 static int cvmx_usb_cancel(struct cvmx_usb_state *usb,
2409 struct cvmx_usb_pipe *pipe,
2410 struct cvmx_usb_transaction *transaction)
2411 {
2412 /* Fail if the pipe isn't open */
2413 if (unlikely((pipe->flags & __CVMX_USB_PIPE_FLAGS_OPEN) == 0))
2414 return -EINVAL;
2415
2416 /*
2417 * If the transaction is the HEAD of the queue and scheduled. We need to
2418 * treat it special
2419 */
2420 if ((pipe->head == transaction) &&
2421 (pipe->flags & __CVMX_USB_PIPE_FLAGS_SCHEDULED)) {
2422 union cvmx_usbcx_hccharx usbc_hcchar;
2423
2424 usb->pipe_for_channel[pipe->channel] = NULL;
2425 pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_SCHEDULED;
2426
2427 CVMX_SYNCW;
2428
2429 usbc_hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(pipe->channel, usb->index));
2430 /*
2431 * If the channel isn't enabled then the transaction already
2432 * completed.
2433 */
2434 if (usbc_hcchar.s.chena) {
2435 usbc_hcchar.s.chdis = 1;
2436 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(pipe->channel, usb->index), usbc_hcchar.u32);
2437 }
2438 }
2439 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_CANCEL);
2440 return 0;
2441 }
2442
2443
2444 /**
2445 * Cancel all outstanding requests in a pipe. Logically all this
2446 * does is call cvmx_usb_cancel() in a loop.
2447 *
2448 * @usb: USB device state populated by cvmx_usb_initialize().
2449 * @pipe: Pipe to cancel requests in.
2450 *
2451 * Returns: 0 or a negative error code.
2452 */
2453 static int cvmx_usb_cancel_all(struct cvmx_usb_state *usb,
2454 struct cvmx_usb_pipe *pipe)
2455 {
2456 /* Fail if the pipe isn't open */
2457 if (unlikely((pipe->flags & __CVMX_USB_PIPE_FLAGS_OPEN) == 0))
2458 return -EINVAL;
2459
2460 /* Simply loop through and attempt to cancel each transaction */
2461 while (pipe->head) {
2462 int result = cvmx_usb_cancel(usb, pipe, pipe->head);
2463 if (unlikely(result != 0))
2464 return result;
2465 }
2466 return 0;
2467 }
2468
2469
2470 /**
2471 * Close a pipe created with cvmx_usb_open_pipe().
2472 *
2473 * @usb: USB device state populated by cvmx_usb_initialize().
2474 * @pipe: Pipe to close.
2475 *
2476 * Returns: 0 or a negative error code. EBUSY is returned if the pipe has
2477 * outstanding transfers.
2478 */
2479 static int cvmx_usb_close_pipe(struct cvmx_usb_state *usb,
2480 struct cvmx_usb_pipe *pipe)
2481 {
2482 /* Fail if the pipe isn't open */
2483 if (unlikely((pipe->flags & __CVMX_USB_PIPE_FLAGS_OPEN) == 0))
2484 return -EINVAL;
2485
2486 /* Fail if the pipe has pending transactions */
2487 if (unlikely(pipe->head))
2488 return -EBUSY;
2489
2490 pipe->flags = 0;
2491 __cvmx_usb_remove_pipe(&usb->idle_pipes, pipe);
2492 __cvmx_usb_append_pipe(&usb->free_pipes, pipe);
2493
2494 return 0;
2495 }
2496
2497 /**
2498 * Get the current USB protocol level frame number. The frame
2499 * number is always in the range of 0-0x7ff.
2500 *
2501 * @usb: USB device state populated by cvmx_usb_initialize().
2502 *
2503 * Returns: USB frame number
2504 */
2505 static int cvmx_usb_get_frame_number(struct cvmx_usb_state *usb)
2506 {
2507 int frame_number;
2508 union cvmx_usbcx_hfnum usbc_hfnum;
2509
2510 usbc_hfnum.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index));
2511 frame_number = usbc_hfnum.s.frnum;
2512
2513 return frame_number;
2514 }
2515
2516
2517 /**
2518 * Poll a channel for status
2519 *
2520 * @usb: USB device
2521 * @channel: Channel to poll
2522 *
2523 * Returns: Zero on success
2524 */
2525 static int __cvmx_usb_poll_channel(struct cvmx_usb_state *usb, int channel)
2526 {
2527 union cvmx_usbcx_hcintx usbc_hcint;
2528 union cvmx_usbcx_hctsizx usbc_hctsiz;
2529 union cvmx_usbcx_hccharx usbc_hcchar;
2530 struct cvmx_usb_pipe *pipe;
2531 struct cvmx_usb_transaction *transaction;
2532 int bytes_this_transfer;
2533 int bytes_in_last_packet;
2534 int packets_processed;
2535 int buffer_space_left;
2536
2537 /* Read the interrupt status bits for the channel */
2538 usbc_hcint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCINTX(channel, usb->index));
2539
2540 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA) {
2541 usbc_hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index));
2542
2543 if (usbc_hcchar.s.chena && usbc_hcchar.s.chdis) {
2544 /*
2545 * There seems to be a bug in CN31XX which can cause
2546 * interrupt IN transfers to get stuck until we do a
2547 * write of HCCHARX without changing things
2548 */
2549 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index), usbc_hcchar.u32);
2550 return 0;
2551 }
2552
2553 /*
2554 * In non DMA mode the channels don't halt themselves. We need
2555 * to manually disable channels that are left running
2556 */
2557 if (!usbc_hcint.s.chhltd) {
2558 if (usbc_hcchar.s.chena) {
2559 union cvmx_usbcx_hcintmskx hcintmsk;
2560 /* Disable all interrupts except CHHLTD */
2561 hcintmsk.u32 = 0;
2562 hcintmsk.s.chhltdmsk = 1;
2563 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), hcintmsk.u32);
2564 usbc_hcchar.s.chdis = 1;
2565 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index), usbc_hcchar.u32);
2566 return 0;
2567 } else if (usbc_hcint.s.xfercompl) {
2568 /*
2569 * Successful IN/OUT with transfer complete.
2570 * Channel halt isn't needed.
2571 */
2572 } else {
2573 cvmx_dprintf("USB%d: Channel %d interrupt without halt\n", usb->index, channel);
2574 return 0;
2575 }
2576 }
2577 } else {
2578 /*
2579 * There is are no interrupts that we need to process when the
2580 * channel is still running
2581 */
2582 if (!usbc_hcint.s.chhltd)
2583 return 0;
2584 }
2585
2586 /* Disable the channel interrupts now that it is done */
2587 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HCINTMSKX(channel, usb->index), 0);
2588 usb->idle_hardware_channels |= (1<<channel);
2589
2590 /* Make sure this channel is tied to a valid pipe */
2591 pipe = usb->pipe_for_channel[channel];
2592 CVMX_PREFETCH(pipe, 0);
2593 CVMX_PREFETCH(pipe, 128);
2594 if (!pipe)
2595 return 0;
2596 transaction = pipe->head;
2597 CVMX_PREFETCH(transaction, 0);
2598
2599 /*
2600 * Disconnect this pipe from the HW channel. Later the schedule
2601 * function will figure out which pipe needs to go
2602 */
2603 usb->pipe_for_channel[channel] = NULL;
2604 pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_SCHEDULED;
2605
2606 /*
2607 * Read the channel config info so we can figure out how much data
2608 * transfered
2609 */
2610 usbc_hcchar.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCCHARX(channel, usb->index));
2611 usbc_hctsiz.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HCTSIZX(channel, usb->index));
2612
2613 /*
2614 * Calculating the number of bytes successfully transferred is dependent
2615 * on the transfer direction
2616 */
2617 packets_processed = transaction->pktcnt - usbc_hctsiz.s.pktcnt;
2618 if (usbc_hcchar.s.epdir) {
2619 /*
2620 * IN transactions are easy. For every byte received the
2621 * hardware decrements xfersize. All we need to do is subtract
2622 * the current value of xfersize from its starting value and we
2623 * know how many bytes were written to the buffer
2624 */
2625 bytes_this_transfer = transaction->xfersize - usbc_hctsiz.s.xfersize;
2626 } else {
2627 /*
2628 * OUT transaction don't decrement xfersize. Instead pktcnt is
2629 * decremented on every successful packet send. The hardware
2630 * does this when it receives an ACK, or NYET. If it doesn't
2631 * receive one of these responses pktcnt doesn't change
2632 */
2633 bytes_this_transfer = packets_processed * usbc_hcchar.s.mps;
2634 /*
2635 * The last packet may not be a full transfer if we didn't have
2636 * enough data
2637 */
2638 if (bytes_this_transfer > transaction->xfersize)
2639 bytes_this_transfer = transaction->xfersize;
2640 }
2641 /* Figure out how many bytes were in the last packet of the transfer */
2642 if (packets_processed)
2643 bytes_in_last_packet = bytes_this_transfer - (packets_processed-1) * usbc_hcchar.s.mps;
2644 else
2645 bytes_in_last_packet = bytes_this_transfer;
2646
2647 /*
2648 * As a special case, setup transactions output the setup header, not
2649 * the user's data. For this reason we don't count setup data as bytes
2650 * transferred
2651 */
2652 if ((transaction->stage == CVMX_USB_STAGE_SETUP) ||
2653 (transaction->stage == CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE))
2654 bytes_this_transfer = 0;
2655
2656 /*
2657 * Add the bytes transferred to the running total. It is important that
2658 * bytes_this_transfer doesn't count any data that needs to be
2659 * retransmitted
2660 */
2661 transaction->actual_bytes += bytes_this_transfer;
2662 if (transaction->type == CVMX_USB_TRANSFER_ISOCHRONOUS)
2663 buffer_space_left = transaction->iso_packets[0].length - transaction->actual_bytes;
2664 else
2665 buffer_space_left = transaction->buffer_length - transaction->actual_bytes;
2666
2667 /*
2668 * We need to remember the PID toggle state for the next transaction.
2669 * The hardware already updated it for the next transaction
2670 */
2671 pipe->pid_toggle = !(usbc_hctsiz.s.pid == 0);
2672
2673 /*
2674 * For high speed bulk out, assume the next transaction will need to do
2675 * a ping before proceeding. If this isn't true the ACK processing below
2676 * will clear this flag
2677 */
2678 if ((pipe->device_speed == CVMX_USB_SPEED_HIGH) &&
2679 (pipe->transfer_type == CVMX_USB_TRANSFER_BULK) &&
2680 (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT))
2681 pipe->flags |= __CVMX_USB_PIPE_FLAGS_NEED_PING;
2682
2683 if (usbc_hcint.s.stall) {
2684 /*
2685 * STALL as a response means this transaction cannot be
2686 * completed because the device can't process transactions. Tell
2687 * the user. Any data that was transferred will be counted on
2688 * the actual bytes transferred
2689 */
2690 pipe->pid_toggle = 0;
2691 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_STALL);
2692 } else if (usbc_hcint.s.xacterr) {
2693 /*
2694 * We know at least one packet worked if we get a ACK or NAK.
2695 * Reset the retry counter
2696 */
2697 if (usbc_hcint.s.nak || usbc_hcint.s.ack)
2698 transaction->retries = 0;
2699 transaction->retries++;
2700 if (transaction->retries > MAX_RETRIES) {
2701 /*
2702 * XactErr as a response means the device signaled
2703 * something wrong with the transfer. For example, PID
2704 * toggle errors cause these
2705 */
2706 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_XACTERR);
2707 } else {
2708 /*
2709 * If this was a split then clear our split in progress
2710 * marker
2711 */
2712 if (usb->active_split == transaction)
2713 usb->active_split = NULL;
2714 /*
2715 * Rewind to the beginning of the transaction by anding
2716 * off the split complete bit
2717 */
2718 transaction->stage &= ~1;
2719 pipe->split_sc_frame = -1;
2720 pipe->next_tx_frame += pipe->interval;
2721 if (pipe->next_tx_frame < usb->frame_number)
2722 pipe->next_tx_frame = usb->frame_number + pipe->interval -
2723 (usb->frame_number - pipe->next_tx_frame) % pipe->interval;
2724 }
2725 } else if (usbc_hcint.s.bblerr) {
2726 /* Babble Error (BblErr) */
2727 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_BABBLEERR);
2728 } else if (usbc_hcint.s.datatglerr) {
2729 /* We'll retry the exact same transaction again */
2730 transaction->retries++;
2731 } else if (usbc_hcint.s.nyet) {
2732 /*
2733 * NYET as a response is only allowed in three cases: as a
2734 * response to a ping, as a response to a split transaction, and
2735 * as a response to a bulk out. The ping case is handled by
2736 * hardware, so we only have splits and bulk out
2737 */
2738 if (!__cvmx_usb_pipe_needs_split(usb, pipe)) {
2739 transaction->retries = 0;
2740 /*
2741 * If there is more data to go then we need to try
2742 * again. Otherwise this transaction is complete
2743 */
2744 if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet))
2745 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2746 } else {
2747 /*
2748 * Split transactions retry the split complete 4 times
2749 * then rewind to the start split and do the entire
2750 * transactions again
2751 */
2752 transaction->retries++;
2753 if ((transaction->retries & 0x3) == 0) {
2754 /*
2755 * Rewind to the beginning of the transaction by
2756 * anding off the split complete bit
2757 */
2758 transaction->stage &= ~1;
2759 pipe->split_sc_frame = -1;
2760 }
2761 }
2762 } else if (usbc_hcint.s.ack) {
2763 transaction->retries = 0;
2764 /*
2765 * The ACK bit can only be checked after the other error bits.
2766 * This is because a multi packet transfer may succeed in a
2767 * number of packets and then get a different response on the
2768 * last packet. In this case both ACK and the last response bit
2769 * will be set. If none of the other response bits is set, then
2770 * the last packet must have been an ACK
2771 *
2772 * Since we got an ACK, we know we don't need to do a ping on
2773 * this pipe
2774 */
2775 pipe->flags &= ~__CVMX_USB_PIPE_FLAGS_NEED_PING;
2776
2777 switch (transaction->type) {
2778 case CVMX_USB_TRANSFER_CONTROL:
2779 switch (transaction->stage) {
2780 case CVMX_USB_STAGE_NON_CONTROL:
2781 case CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE:
2782 /* This should be impossible */
2783 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_ERROR);
2784 break;
2785 case CVMX_USB_STAGE_SETUP:
2786 pipe->pid_toggle = 1;
2787 if (__cvmx_usb_pipe_needs_split(usb, pipe))
2788 transaction->stage = CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE;
2789 else {
2790 union cvmx_usb_control_header *header =
2791 cvmx_phys_to_ptr(transaction->control_header);
2792 if (header->s.length)
2793 transaction->stage = CVMX_USB_STAGE_DATA;
2794 else
2795 transaction->stage = CVMX_USB_STAGE_STATUS;
2796 }
2797 break;
2798 case CVMX_USB_STAGE_SETUP_SPLIT_COMPLETE:
2799 {
2800 union cvmx_usb_control_header *header =
2801 cvmx_phys_to_ptr(transaction->control_header);
2802 if (header->s.length)
2803 transaction->stage = CVMX_USB_STAGE_DATA;
2804 else
2805 transaction->stage = CVMX_USB_STAGE_STATUS;
2806 }
2807 break;
2808 case CVMX_USB_STAGE_DATA:
2809 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
2810 transaction->stage = CVMX_USB_STAGE_DATA_SPLIT_COMPLETE;
2811 /*
2812 * For setup OUT data that are splits,
2813 * the hardware doesn't appear to count
2814 * transferred data. Here we manually
2815 * update the data transferred
2816 */
2817 if (!usbc_hcchar.s.epdir) {
2818 if (buffer_space_left < pipe->max_packet)
2819 transaction->actual_bytes += buffer_space_left;
2820 else
2821 transaction->actual_bytes += pipe->max_packet;
2822 }
2823 } else if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet)) {
2824 pipe->pid_toggle = 1;
2825 transaction->stage = CVMX_USB_STAGE_STATUS;
2826 }
2827 break;
2828 case CVMX_USB_STAGE_DATA_SPLIT_COMPLETE:
2829 if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet)) {
2830 pipe->pid_toggle = 1;
2831 transaction->stage = CVMX_USB_STAGE_STATUS;
2832 } else {
2833 transaction->stage = CVMX_USB_STAGE_DATA;
2834 }
2835 break;
2836 case CVMX_USB_STAGE_STATUS:
2837 if (__cvmx_usb_pipe_needs_split(usb, pipe))
2838 transaction->stage = CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE;
2839 else
2840 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2841 break;
2842 case CVMX_USB_STAGE_STATUS_SPLIT_COMPLETE:
2843 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2844 break;
2845 }
2846 break;
2847 case CVMX_USB_TRANSFER_BULK:
2848 case CVMX_USB_TRANSFER_INTERRUPT:
2849 /*
2850 * The only time a bulk transfer isn't complete when it
2851 * finishes with an ACK is during a split transaction.
2852 * For splits we need to continue the transfer if more
2853 * data is needed
2854 */
2855 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
2856 if (transaction->stage == CVMX_USB_STAGE_NON_CONTROL)
2857 transaction->stage = CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE;
2858 else {
2859 if (buffer_space_left && (bytes_in_last_packet == pipe->max_packet))
2860 transaction->stage = CVMX_USB_STAGE_NON_CONTROL;
2861 else {
2862 if (transaction->type == CVMX_USB_TRANSFER_INTERRUPT)
2863 pipe->next_tx_frame += pipe->interval;
2864 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2865 }
2866 }
2867 } else {
2868 if ((pipe->device_speed == CVMX_USB_SPEED_HIGH) &&
2869 (pipe->transfer_type == CVMX_USB_TRANSFER_BULK) &&
2870 (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) &&
2871 (usbc_hcint.s.nak))
2872 pipe->flags |= __CVMX_USB_PIPE_FLAGS_NEED_PING;
2873 if (!buffer_space_left || (bytes_in_last_packet < pipe->max_packet)) {
2874 if (transaction->type == CVMX_USB_TRANSFER_INTERRUPT)
2875 pipe->next_tx_frame += pipe->interval;
2876 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2877 }
2878 }
2879 break;
2880 case CVMX_USB_TRANSFER_ISOCHRONOUS:
2881 if (__cvmx_usb_pipe_needs_split(usb, pipe)) {
2882 /*
2883 * ISOCHRONOUS OUT splits don't require a
2884 * complete split stage. Instead they use a
2885 * sequence of begin OUT splits to transfer the
2886 * data 188 bytes at a time. Once the transfer
2887 * is complete, the pipe sleeps until the next
2888 * schedule interval
2889 */
2890 if (pipe->transfer_dir == CVMX_USB_DIRECTION_OUT) {
2891 /*
2892 * If no space left or this wasn't a max
2893 * size packet then this transfer is
2894 * complete. Otherwise start it again to
2895 * send the next 188 bytes
2896 */
2897 if (!buffer_space_left || (bytes_this_transfer < 188)) {
2898 pipe->next_tx_frame += pipe->interval;
2899 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2900 }
2901 } else {
2902 if (transaction->stage == CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE) {
2903 /*
2904 * We are in the incoming data
2905 * phase. Keep getting data
2906 * until we run out of space or
2907 * get a small packet
2908 */
2909 if ((buffer_space_left == 0) || (bytes_in_last_packet < pipe->max_packet)) {
2910 pipe->next_tx_frame += pipe->interval;
2911 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2912 }
2913 } else
2914 transaction->stage = CVMX_USB_STAGE_NON_CONTROL_SPLIT_COMPLETE;
2915 }
2916 } else {
2917 pipe->next_tx_frame += pipe->interval;
2918 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_SUCCESS);
2919 }
2920 break;
2921 }
2922 } else if (usbc_hcint.s.nak) {
2923 /*
2924 * If this was a split then clear our split in progress marker.
2925 */
2926 if (usb->active_split == transaction)
2927 usb->active_split = NULL;
2928 /*
2929 * NAK as a response means the device couldn't accept the
2930 * transaction, but it should be retried in the future. Rewind
2931 * to the beginning of the transaction by anding off the split
2932 * complete bit. Retry in the next interval
2933 */
2934 transaction->retries = 0;
2935 transaction->stage &= ~1;
2936 pipe->next_tx_frame += pipe->interval;
2937 if (pipe->next_tx_frame < usb->frame_number)
2938 pipe->next_tx_frame = usb->frame_number + pipe->interval -
2939 (usb->frame_number - pipe->next_tx_frame) % pipe->interval;
2940 } else {
2941 struct cvmx_usb_port_status port;
2942 port = cvmx_usb_get_status(usb);
2943 if (port.port_enabled) {
2944 /* We'll retry the exact same transaction again */
2945 transaction->retries++;
2946 } else {
2947 /*
2948 * We get channel halted interrupts with no result bits
2949 * sets when the cable is unplugged
2950 */
2951 __cvmx_usb_perform_complete(usb, pipe, transaction, CVMX_USB_COMPLETE_ERROR);
2952 }
2953 }
2954 return 0;
2955 }
2956
2957 static void octeon_usb_port_callback(struct cvmx_usb_state *usb)
2958 {
2959 struct octeon_hcd *priv = cvmx_usb_to_octeon(usb);
2960
2961 spin_unlock(&priv->lock);
2962 usb_hcd_poll_rh_status(octeon_to_hcd(priv));
2963 spin_lock(&priv->lock);
2964 }
2965
2966 /**
2967 * Poll the USB block for status and call all needed callback
2968 * handlers. This function is meant to be called in the interrupt
2969 * handler for the USB controller. It can also be called
2970 * periodically in a loop for non-interrupt based operation.
2971 *
2972 * @usb: USB device state populated by cvmx_usb_initialize().
2973 *
2974 * Returns: 0 or a negative error code.
2975 */
2976 static int cvmx_usb_poll(struct cvmx_usb_state *usb)
2977 {
2978 union cvmx_usbcx_hfnum usbc_hfnum;
2979 union cvmx_usbcx_gintsts usbc_gintsts;
2980
2981 CVMX_PREFETCH(usb, 0);
2982 CVMX_PREFETCH(usb, 1*128);
2983 CVMX_PREFETCH(usb, 2*128);
2984 CVMX_PREFETCH(usb, 3*128);
2985 CVMX_PREFETCH(usb, 4*128);
2986
2987 /* Update the frame counter */
2988 usbc_hfnum.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HFNUM(usb->index));
2989 if ((usb->frame_number&0x3fff) > usbc_hfnum.s.frnum)
2990 usb->frame_number += 0x4000;
2991 usb->frame_number &= ~0x3fffull;
2992 usb->frame_number |= usbc_hfnum.s.frnum;
2993
2994 /* Read the pending interrupts */
2995 usbc_gintsts.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_GINTSTS(usb->index));
2996
2997 /* Clear the interrupts now that we know about them */
2998 __cvmx_usb_write_csr32(usb, CVMX_USBCX_GINTSTS(usb->index), usbc_gintsts.u32);
2999
3000 if (usbc_gintsts.s.rxflvl) {
3001 /*
3002 * RxFIFO Non-Empty (RxFLvl)
3003 * Indicates that there is at least one packet pending to be
3004 * read from the RxFIFO.
3005 *
3006 * In DMA mode this is handled by hardware
3007 */
3008 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
3009 __cvmx_usb_poll_rx_fifo(usb);
3010 }
3011 if (usbc_gintsts.s.ptxfemp || usbc_gintsts.s.nptxfemp) {
3012 /* Fill the Tx FIFOs when not in DMA mode */
3013 if (usb->init_flags & CVMX_USB_INITIALIZE_FLAGS_NO_DMA)
3014 __cvmx_usb_poll_tx_fifo(usb);
3015 }
3016 if (usbc_gintsts.s.disconnint || usbc_gintsts.s.prtint) {
3017 union cvmx_usbcx_hprt usbc_hprt;
3018 /*
3019 * Disconnect Detected Interrupt (DisconnInt)
3020 * Asserted when a device disconnect is detected.
3021 *
3022 * Host Port Interrupt (PrtInt)
3023 * The core sets this bit to indicate a change in port status of
3024 * one of the O2P USB core ports in Host mode. The application
3025 * must read the Host Port Control and Status (HPRT) register to
3026 * determine the exact event that caused this interrupt. The
3027 * application must clear the appropriate status bit in the Host
3028 * Port Control and Status register to clear this bit.
3029 *
3030 * Call the user's port callback
3031 */
3032 octeon_usb_port_callback(usb);
3033 /* Clear the port change bits */
3034 usbc_hprt.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HPRT(usb->index));
3035 usbc_hprt.s.prtena = 0;
3036 __cvmx_usb_write_csr32(usb, CVMX_USBCX_HPRT(usb->index), usbc_hprt.u32);
3037 }
3038 if (usbc_gintsts.s.hchint) {
3039 /*
3040 * Host Channels Interrupt (HChInt)
3041 * The core sets this bit to indicate that an interrupt is
3042 * pending on one of the channels of the core (in Host mode).
3043 * The application must read the Host All Channels Interrupt
3044 * (HAINT) register to determine the exact number of the channel
3045 * on which the interrupt occurred, and then read the
3046 * corresponding Host Channel-n Interrupt (HCINTn) register to
3047 * determine the exact cause of the interrupt. The application
3048 * must clear the appropriate status bit in the HCINTn register
3049 * to clear this bit.
3050 */
3051 union cvmx_usbcx_haint usbc_haint;
3052 usbc_haint.u32 = __cvmx_usb_read_csr32(usb, CVMX_USBCX_HAINT(usb->index));
3053 while (usbc_haint.u32) {
3054 int channel;
3055
3056 channel = __fls(usbc_haint.u32);
3057 __cvmx_usb_poll_channel(usb, channel);
3058 usbc_haint.u32 ^= 1<<channel;
3059 }
3060 }
3061
3062 __cvmx_usb_schedule(usb, usbc_gintsts.s.sof);
3063
3064 return 0;
3065 }
3066
3067 /* convert between an HCD pointer and the corresponding struct octeon_hcd */
3068 static inline struct octeon_hcd *hcd_to_octeon(struct usb_hcd *hcd)
3069 {
3070 return (struct octeon_hcd *)(hcd->hcd_priv);
3071 }
3072
3073 static irqreturn_t octeon_usb_irq(struct usb_hcd *hcd)
3074 {
3075 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3076 unsigned long flags;
3077
3078 spin_lock_irqsave(&priv->lock, flags);
3079 cvmx_usb_poll(&priv->usb);
3080 spin_unlock_irqrestore(&priv->lock, flags);
3081 return IRQ_HANDLED;
3082 }
3083
3084 static int octeon_usb_start(struct usb_hcd *hcd)
3085 {
3086 hcd->state = HC_STATE_RUNNING;
3087 return 0;
3088 }
3089
3090 static void octeon_usb_stop(struct usb_hcd *hcd)
3091 {
3092 hcd->state = HC_STATE_HALT;
3093 }
3094
3095 static int octeon_usb_get_frame_number(struct usb_hcd *hcd)
3096 {
3097 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3098
3099 return cvmx_usb_get_frame_number(&priv->usb);
3100 }
3101
3102 static int octeon_usb_urb_enqueue(struct usb_hcd *hcd,
3103 struct urb *urb,
3104 gfp_t mem_flags)
3105 {
3106 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3107 struct device *dev = hcd->self.controller;
3108 struct cvmx_usb_transaction *transaction = NULL;
3109 struct cvmx_usb_pipe *pipe;
3110 unsigned long flags;
3111 struct cvmx_usb_iso_packet *iso_packet;
3112 struct usb_host_endpoint *ep = urb->ep;
3113
3114 urb->status = 0;
3115 INIT_LIST_HEAD(&urb->urb_list); /* not enqueued on dequeue_list */
3116 spin_lock_irqsave(&priv->lock, flags);
3117
3118 if (!ep->hcpriv) {
3119 enum cvmx_usb_transfer transfer_type;
3120 enum cvmx_usb_speed speed;
3121 int split_device = 0;
3122 int split_port = 0;
3123 switch (usb_pipetype(urb->pipe)) {
3124 case PIPE_ISOCHRONOUS:
3125 transfer_type = CVMX_USB_TRANSFER_ISOCHRONOUS;
3126 break;
3127 case PIPE_INTERRUPT:
3128 transfer_type = CVMX_USB_TRANSFER_INTERRUPT;
3129 break;
3130 case PIPE_CONTROL:
3131 transfer_type = CVMX_USB_TRANSFER_CONTROL;
3132 break;
3133 default:
3134 transfer_type = CVMX_USB_TRANSFER_BULK;
3135 break;
3136 }
3137 switch (urb->dev->speed) {
3138 case USB_SPEED_LOW:
3139 speed = CVMX_USB_SPEED_LOW;
3140 break;
3141 case USB_SPEED_FULL:
3142 speed = CVMX_USB_SPEED_FULL;
3143 break;
3144 default:
3145 speed = CVMX_USB_SPEED_HIGH;
3146 break;
3147 }
3148 /*
3149 * For slow devices on high speed ports we need to find the hub
3150 * that does the speed translation so we know where to send the
3151 * split transactions.
3152 */
3153 if (speed != CVMX_USB_SPEED_HIGH) {
3154 /*
3155 * Start at this device and work our way up the usb
3156 * tree.
3157 */
3158 struct usb_device *dev = urb->dev;
3159 while (dev->parent) {
3160 /*
3161 * If our parent is high speed then he'll
3162 * receive the splits.
3163 */
3164 if (dev->parent->speed == USB_SPEED_HIGH) {
3165 split_device = dev->parent->devnum;
3166 split_port = dev->portnum;
3167 break;
3168 }
3169 /*
3170 * Move up the tree one level. If we make it all
3171 * the way up the tree, then the port must not
3172 * be in high speed mode and we don't need a
3173 * split.
3174 */
3175 dev = dev->parent;
3176 }
3177 }
3178 pipe = cvmx_usb_open_pipe(&priv->usb, usb_pipedevice(urb->pipe),
3179 usb_pipeendpoint(urb->pipe), speed,
3180 le16_to_cpu(ep->desc.wMaxPacketSize) & 0x7ff,
3181 transfer_type,
3182 usb_pipein(urb->pipe) ?
3183 CVMX_USB_DIRECTION_IN :
3184 CVMX_USB_DIRECTION_OUT,
3185 urb->interval,
3186 (le16_to_cpu(ep->desc.wMaxPacketSize) >> 11) & 0x3,
3187 split_device, split_port);
3188 if (!pipe) {
3189 spin_unlock_irqrestore(&priv->lock, flags);
3190 dev_dbg(dev, "Failed to create pipe\n");
3191 return -ENOMEM;
3192 }
3193 ep->hcpriv = pipe;
3194 } else {
3195 pipe = ep->hcpriv;
3196 }
3197
3198 switch (usb_pipetype(urb->pipe)) {
3199 case PIPE_ISOCHRONOUS:
3200 dev_dbg(dev, "Submit isochronous to %d.%d\n",
3201 usb_pipedevice(urb->pipe), usb_pipeendpoint(urb->pipe));
3202 /*
3203 * Allocate a structure to use for our private list of
3204 * isochronous packets.
3205 */
3206 iso_packet = kmalloc(urb->number_of_packets *
3207 sizeof(struct cvmx_usb_iso_packet),
3208 GFP_ATOMIC);
3209 if (iso_packet) {
3210 int i;
3211 /* Fill the list with the data from the URB */
3212 for (i = 0; i < urb->number_of_packets; i++) {
3213 iso_packet[i].offset = urb->iso_frame_desc[i].offset;
3214 iso_packet[i].length = urb->iso_frame_desc[i].length;
3215 iso_packet[i].status = CVMX_USB_COMPLETE_ERROR;
3216 }
3217 /*
3218 * Store a pointer to the list in the URB setup_packet
3219 * field. We know this currently isn't being used and
3220 * this saves us a bunch of logic.
3221 */
3222 urb->setup_packet = (char *)iso_packet;
3223 transaction = cvmx_usb_submit_isochronous(&priv->usb,
3224 pipe, urb);
3225 /*
3226 * If submit failed we need to free our private packet
3227 * list.
3228 */
3229 if (!transaction) {
3230 urb->setup_packet = NULL;
3231 kfree(iso_packet);
3232 }
3233 }
3234 break;
3235 case PIPE_INTERRUPT:
3236 dev_dbg(dev, "Submit interrupt to %d.%d\n",
3237 usb_pipedevice(urb->pipe), usb_pipeendpoint(urb->pipe));
3238 transaction = cvmx_usb_submit_interrupt(&priv->usb, pipe, urb);
3239 break;
3240 case PIPE_CONTROL:
3241 dev_dbg(dev, "Submit control to %d.%d\n",
3242 usb_pipedevice(urb->pipe), usb_pipeendpoint(urb->pipe));
3243 transaction = cvmx_usb_submit_control(&priv->usb, pipe, urb);
3244 break;
3245 case PIPE_BULK:
3246 dev_dbg(dev, "Submit bulk to %d.%d\n",
3247 usb_pipedevice(urb->pipe), usb_pipeendpoint(urb->pipe));
3248 transaction = cvmx_usb_submit_bulk(&priv->usb, pipe, urb);
3249 break;
3250 }
3251 if (!transaction) {
3252 spin_unlock_irqrestore(&priv->lock, flags);
3253 dev_dbg(dev, "Failed to submit\n");
3254 return -ENOMEM;
3255 }
3256 urb->hcpriv = transaction;
3257 spin_unlock_irqrestore(&priv->lock, flags);
3258 return 0;
3259 }
3260
3261 static void octeon_usb_urb_dequeue_work(unsigned long arg)
3262 {
3263 unsigned long flags;
3264 struct octeon_hcd *priv = (struct octeon_hcd *)arg;
3265
3266 spin_lock_irqsave(&priv->lock, flags);
3267
3268 while (!list_empty(&priv->dequeue_list)) {
3269 struct urb *urb = container_of(priv->dequeue_list.next, struct urb, urb_list);
3270 list_del(&urb->urb_list);
3271 /* not enqueued on dequeue_list */
3272 INIT_LIST_HEAD(&urb->urb_list);
3273 cvmx_usb_cancel(&priv->usb, urb->ep->hcpriv, urb->hcpriv);
3274 }
3275
3276 spin_unlock_irqrestore(&priv->lock, flags);
3277 }
3278
3279 static int octeon_usb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
3280 {
3281 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3282 unsigned long flags;
3283
3284 if (!urb->dev)
3285 return -EINVAL;
3286
3287 spin_lock_irqsave(&priv->lock, flags);
3288
3289 urb->status = status;
3290 list_add_tail(&urb->urb_list, &priv->dequeue_list);
3291
3292 spin_unlock_irqrestore(&priv->lock, flags);
3293
3294 tasklet_schedule(&priv->dequeue_tasklet);
3295
3296 return 0;
3297 }
3298
3299 static void octeon_usb_endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
3300 {
3301 struct device *dev = hcd->self.controller;
3302
3303 if (ep->hcpriv) {
3304 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3305 struct cvmx_usb_pipe *pipe = ep->hcpriv;
3306 unsigned long flags;
3307 spin_lock_irqsave(&priv->lock, flags);
3308 cvmx_usb_cancel_all(&priv->usb, pipe);
3309 if (cvmx_usb_close_pipe(&priv->usb, pipe))
3310 dev_dbg(dev, "Closing pipe %p failed\n", pipe);
3311 spin_unlock_irqrestore(&priv->lock, flags);
3312 ep->hcpriv = NULL;
3313 }
3314 }
3315
3316 static int octeon_usb_hub_status_data(struct usb_hcd *hcd, char *buf)
3317 {
3318 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3319 struct cvmx_usb_port_status port_status;
3320 unsigned long flags;
3321
3322 spin_lock_irqsave(&priv->lock, flags);
3323 port_status = cvmx_usb_get_status(&priv->usb);
3324 spin_unlock_irqrestore(&priv->lock, flags);
3325 buf[0] = 0;
3326 buf[0] = port_status.connect_change << 1;
3327
3328 return (buf[0] != 0);
3329 }
3330
3331 static int octeon_usb_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength)
3332 {
3333 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3334 struct device *dev = hcd->self.controller;
3335 struct cvmx_usb_port_status usb_port_status;
3336 int port_status;
3337 struct usb_hub_descriptor *desc;
3338 unsigned long flags;
3339
3340 switch (typeReq) {
3341 case ClearHubFeature:
3342 dev_dbg(dev, "ClearHubFeature\n");
3343 switch (wValue) {
3344 case C_HUB_LOCAL_POWER:
3345 case C_HUB_OVER_CURRENT:
3346 /* Nothing required here */
3347 break;
3348 default:
3349 return -EINVAL;
3350 }
3351 break;
3352 case ClearPortFeature:
3353 dev_dbg(dev, "ClearPortFeature\n");
3354 if (wIndex != 1) {
3355 dev_dbg(dev, " INVALID\n");
3356 return -EINVAL;
3357 }
3358
3359 switch (wValue) {
3360 case USB_PORT_FEAT_ENABLE:
3361 dev_dbg(dev, " ENABLE\n");
3362 spin_lock_irqsave(&priv->lock, flags);
3363 cvmx_usb_disable(&priv->usb);
3364 spin_unlock_irqrestore(&priv->lock, flags);
3365 break;
3366 case USB_PORT_FEAT_SUSPEND:
3367 dev_dbg(dev, " SUSPEND\n");
3368 /* Not supported on Octeon */
3369 break;
3370 case USB_PORT_FEAT_POWER:
3371 dev_dbg(dev, " POWER\n");
3372 /* Not supported on Octeon */
3373 break;
3374 case USB_PORT_FEAT_INDICATOR:
3375 dev_dbg(dev, " INDICATOR\n");
3376 /* Port inidicator not supported */
3377 break;
3378 case USB_PORT_FEAT_C_CONNECTION:
3379 dev_dbg(dev, " C_CONNECTION\n");
3380 /* Clears drivers internal connect status change flag */
3381 spin_lock_irqsave(&priv->lock, flags);
3382 priv->usb.port_status = cvmx_usb_get_status(&priv->usb);
3383 spin_unlock_irqrestore(&priv->lock, flags);
3384 break;
3385 case USB_PORT_FEAT_C_RESET:
3386 dev_dbg(dev, " C_RESET\n");
3387 /*
3388 * Clears the driver's internal Port Reset Change flag.
3389 */
3390 spin_lock_irqsave(&priv->lock, flags);
3391 priv->usb.port_status = cvmx_usb_get_status(&priv->usb);
3392 spin_unlock_irqrestore(&priv->lock, flags);
3393 break;
3394 case USB_PORT_FEAT_C_ENABLE:
3395 dev_dbg(dev, " C_ENABLE\n");
3396 /*
3397 * Clears the driver's internal Port Enable/Disable
3398 * Change flag.
3399 */
3400 spin_lock_irqsave(&priv->lock, flags);
3401 priv->usb.port_status = cvmx_usb_get_status(&priv->usb);
3402 spin_unlock_irqrestore(&priv->lock, flags);
3403 break;
3404 case USB_PORT_FEAT_C_SUSPEND:
3405 dev_dbg(dev, " C_SUSPEND\n");
3406 /*
3407 * Clears the driver's internal Port Suspend Change
3408 * flag, which is set when resume signaling on the host
3409 * port is complete.
3410 */
3411 break;
3412 case USB_PORT_FEAT_C_OVER_CURRENT:
3413 dev_dbg(dev, " C_OVER_CURRENT\n");
3414 /* Clears the driver's overcurrent Change flag */
3415 spin_lock_irqsave(&priv->lock, flags);
3416 priv->usb.port_status = cvmx_usb_get_status(&priv->usb);
3417 spin_unlock_irqrestore(&priv->lock, flags);
3418 break;
3419 default:
3420 dev_dbg(dev, " UNKNOWN\n");
3421 return -EINVAL;
3422 }
3423 break;
3424 case GetHubDescriptor:
3425 dev_dbg(dev, "GetHubDescriptor\n");
3426 desc = (struct usb_hub_descriptor *)buf;
3427 desc->bDescLength = 9;
3428 desc->bDescriptorType = 0x29;
3429 desc->bNbrPorts = 1;
3430 desc->wHubCharacteristics = 0x08;
3431 desc->bPwrOn2PwrGood = 1;
3432 desc->bHubContrCurrent = 0;
3433 desc->u.hs.DeviceRemovable[0] = 0;
3434 desc->u.hs.DeviceRemovable[1] = 0xff;
3435 break;
3436 case GetHubStatus:
3437 dev_dbg(dev, "GetHubStatus\n");
3438 *(__le32 *) buf = 0;
3439 break;
3440 case GetPortStatus:
3441 dev_dbg(dev, "GetPortStatus\n");
3442 if (wIndex != 1) {
3443 dev_dbg(dev, " INVALID\n");
3444 return -EINVAL;
3445 }
3446
3447 spin_lock_irqsave(&priv->lock, flags);
3448 usb_port_status = cvmx_usb_get_status(&priv->usb);
3449 spin_unlock_irqrestore(&priv->lock, flags);
3450 port_status = 0;
3451
3452 if (usb_port_status.connect_change) {
3453 port_status |= (1 << USB_PORT_FEAT_C_CONNECTION);
3454 dev_dbg(dev, " C_CONNECTION\n");
3455 }
3456
3457 if (usb_port_status.port_enabled) {
3458 port_status |= (1 << USB_PORT_FEAT_C_ENABLE);
3459 dev_dbg(dev, " C_ENABLE\n");
3460 }
3461
3462 if (usb_port_status.connected) {
3463 port_status |= (1 << USB_PORT_FEAT_CONNECTION);
3464 dev_dbg(dev, " CONNECTION\n");
3465 }
3466
3467 if (usb_port_status.port_enabled) {
3468 port_status |= (1 << USB_PORT_FEAT_ENABLE);
3469 dev_dbg(dev, " ENABLE\n");
3470 }
3471
3472 if (usb_port_status.port_over_current) {
3473 port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT);
3474 dev_dbg(dev, " OVER_CURRENT\n");
3475 }
3476
3477 if (usb_port_status.port_powered) {
3478 port_status |= (1 << USB_PORT_FEAT_POWER);
3479 dev_dbg(dev, " POWER\n");
3480 }
3481
3482 if (usb_port_status.port_speed == CVMX_USB_SPEED_HIGH) {
3483 port_status |= USB_PORT_STAT_HIGH_SPEED;
3484 dev_dbg(dev, " HIGHSPEED\n");
3485 } else if (usb_port_status.port_speed == CVMX_USB_SPEED_LOW) {
3486 port_status |= (1 << USB_PORT_FEAT_LOWSPEED);
3487 dev_dbg(dev, " LOWSPEED\n");
3488 }
3489
3490 *((__le32 *) buf) = cpu_to_le32(port_status);
3491 break;
3492 case SetHubFeature:
3493 dev_dbg(dev, "SetHubFeature\n");
3494 /* No HUB features supported */
3495 break;
3496 case SetPortFeature:
3497 dev_dbg(dev, "SetPortFeature\n");
3498 if (wIndex != 1) {
3499 dev_dbg(dev, " INVALID\n");
3500 return -EINVAL;
3501 }
3502
3503 switch (wValue) {
3504 case USB_PORT_FEAT_SUSPEND:
3505 dev_dbg(dev, " SUSPEND\n");
3506 return -EINVAL;
3507 case USB_PORT_FEAT_POWER:
3508 dev_dbg(dev, " POWER\n");
3509 return -EINVAL;
3510 case USB_PORT_FEAT_RESET:
3511 dev_dbg(dev, " RESET\n");
3512 spin_lock_irqsave(&priv->lock, flags);
3513 cvmx_usb_disable(&priv->usb);
3514 if (cvmx_usb_enable(&priv->usb))
3515 dev_dbg(dev, "Failed to enable the port\n");
3516 spin_unlock_irqrestore(&priv->lock, flags);
3517 return 0;
3518 case USB_PORT_FEAT_INDICATOR:
3519 dev_dbg(dev, " INDICATOR\n");
3520 /* Not supported */
3521 break;
3522 default:
3523 dev_dbg(dev, " UNKNOWN\n");
3524 return -EINVAL;
3525 }
3526 break;
3527 default:
3528 dev_dbg(dev, "Unknown root hub request\n");
3529 return -EINVAL;
3530 }
3531 return 0;
3532 }
3533
3534
3535 static const struct hc_driver octeon_hc_driver = {
3536 .description = "Octeon USB",
3537 .product_desc = "Octeon Host Controller",
3538 .hcd_priv_size = sizeof(struct octeon_hcd),
3539 .irq = octeon_usb_irq,
3540 .flags = HCD_MEMORY | HCD_USB2,
3541 .start = octeon_usb_start,
3542 .stop = octeon_usb_stop,
3543 .urb_enqueue = octeon_usb_urb_enqueue,
3544 .urb_dequeue = octeon_usb_urb_dequeue,
3545 .endpoint_disable = octeon_usb_endpoint_disable,
3546 .get_frame_number = octeon_usb_get_frame_number,
3547 .hub_status_data = octeon_usb_hub_status_data,
3548 .hub_control = octeon_usb_hub_control,
3549 };
3550
3551
3552 static int octeon_usb_driver_probe(struct device *dev)
3553 {
3554 int status;
3555 int usb_num = to_platform_device(dev)->id;
3556 int irq = platform_get_irq(to_platform_device(dev), 0);
3557 struct octeon_hcd *priv;
3558 struct usb_hcd *hcd;
3559 unsigned long flags;
3560
3561 /*
3562 * Set the DMA mask to 64bits so we get buffers already translated for
3563 * DMA.
3564 */
3565 dev->coherent_dma_mask = ~0;
3566 dev->dma_mask = &dev->coherent_dma_mask;
3567
3568 hcd = usb_create_hcd(&octeon_hc_driver, dev, dev_name(dev));
3569 if (!hcd) {
3570 dev_dbg(dev, "Failed to allocate memory for HCD\n");
3571 return -1;
3572 }
3573 hcd->uses_new_polling = 1;
3574 priv = (struct octeon_hcd *)hcd->hcd_priv;
3575
3576 spin_lock_init(&priv->lock);
3577
3578 tasklet_init(&priv->dequeue_tasklet, octeon_usb_urb_dequeue_work, (unsigned long)priv);
3579 INIT_LIST_HEAD(&priv->dequeue_list);
3580
3581 status = cvmx_usb_initialize(&priv->usb, usb_num);
3582 if (status) {
3583 dev_dbg(dev, "USB initialization failed with %d\n", status);
3584 kfree(hcd);
3585 return -1;
3586 }
3587
3588 /* This delay is needed for CN3010, but I don't know why... */
3589 mdelay(10);
3590
3591 spin_lock_irqsave(&priv->lock, flags);
3592 cvmx_usb_poll(&priv->usb);
3593 spin_unlock_irqrestore(&priv->lock, flags);
3594
3595 status = usb_add_hcd(hcd, irq, IRQF_SHARED);
3596 if (status) {
3597 dev_dbg(dev, "USB add HCD failed with %d\n", status);
3598 kfree(hcd);
3599 return -1;
3600 }
3601
3602 dev_dbg(dev, "Registered HCD for port %d on irq %d\n", usb_num, irq);
3603
3604 return 0;
3605 }
3606
3607 static int octeon_usb_driver_remove(struct device *dev)
3608 {
3609 int status;
3610 struct usb_hcd *hcd = dev_get_drvdata(dev);
3611 struct octeon_hcd *priv = hcd_to_octeon(hcd);
3612 unsigned long flags;
3613
3614 usb_remove_hcd(hcd);
3615 tasklet_kill(&priv->dequeue_tasklet);
3616 spin_lock_irqsave(&priv->lock, flags);
3617 status = cvmx_usb_shutdown(&priv->usb);
3618 spin_unlock_irqrestore(&priv->lock, flags);
3619 if (status)
3620 dev_dbg(dev, "USB shutdown failed with %d\n", status);
3621
3622 kfree(hcd);
3623
3624 return 0;
3625 }
3626
3627 static struct device_driver octeon_usb_driver = {
3628 .name = "OcteonUSB",
3629 .bus = &platform_bus_type,
3630 .probe = octeon_usb_driver_probe,
3631 .remove = octeon_usb_driver_remove,
3632 };
3633
3634
3635 #define MAX_USB_PORTS 10
3636 static struct platform_device *pdev_glob[MAX_USB_PORTS];
3637 static int octeon_usb_registered;
3638 static int __init octeon_usb_module_init(void)
3639 {
3640 int num_devices = cvmx_usb_get_num_ports();
3641 int device;
3642
3643 if (usb_disabled() || num_devices == 0)
3644 return -ENODEV;
3645
3646 if (driver_register(&octeon_usb_driver))
3647 return -ENOMEM;
3648
3649 octeon_usb_registered = 1;
3650
3651 /*
3652 * Only cn52XX and cn56XX have DWC_OTG USB hardware and the
3653 * IOB priority registers. Under heavy network load USB
3654 * hardware can be starved by the IOB causing a crash. Give
3655 * it a priority boost if it has been waiting more than 400
3656 * cycles to avoid this situation.
3657 *
3658 * Testing indicates that a cnt_val of 8192 is not sufficient,
3659 * but no failures are seen with 4096. We choose a value of
3660 * 400 to give a safety factor of 10.
3661 */
3662 if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) {
3663 union cvmx_iob_n2c_l2c_pri_cnt pri_cnt;
3664
3665 pri_cnt.u64 = 0;
3666 pri_cnt.s.cnt_enb = 1;
3667 pri_cnt.s.cnt_val = 400;
3668 cvmx_write_csr(CVMX_IOB_N2C_L2C_PRI_CNT, pri_cnt.u64);
3669 }
3670
3671 for (device = 0; device < num_devices; device++) {
3672 struct resource irq_resource;
3673 struct platform_device *pdev;
3674 memset(&irq_resource, 0, sizeof(irq_resource));
3675 irq_resource.start = (device == 0) ? OCTEON_IRQ_USB0 : OCTEON_IRQ_USB1;
3676 irq_resource.end = irq_resource.start;
3677 irq_resource.flags = IORESOURCE_IRQ;
3678 pdev = platform_device_register_simple((char *)octeon_usb_driver. name, device, &irq_resource, 1);
3679 if (IS_ERR(pdev)) {
3680 driver_unregister(&octeon_usb_driver);
3681 octeon_usb_registered = 0;
3682 return PTR_ERR(pdev);
3683 }
3684 if (device < MAX_USB_PORTS)
3685 pdev_glob[device] = pdev;
3686
3687 }
3688 return 0;
3689 }
3690
3691 static void __exit octeon_usb_module_cleanup(void)
3692 {
3693 int i;
3694
3695 for (i = 0; i < MAX_USB_PORTS; i++)
3696 if (pdev_glob[i]) {
3697 platform_device_unregister(pdev_glob[i]);
3698 pdev_glob[i] = NULL;
3699 }
3700 if (octeon_usb_registered)
3701 driver_unregister(&octeon_usb_driver);
3702 }
3703
3704 MODULE_LICENSE("GPL");
3705 MODULE_AUTHOR("Cavium Networks <support@caviumnetworks.com>");
3706 MODULE_DESCRIPTION("Cavium Networks Octeon USB Host driver.");
3707 module_init(octeon_usb_module_init);
3708 module_exit(octeon_usb_module_cleanup);
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