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Staging: add otus Atheros wireless network driver
[deliverable/linux.git] / drivers / staging / otus / hal / hpmain.c
1 /*
2 * Copyright (c) 2007-2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16 #include "../80211core/cprecomp.h"
17 #include "hpani.h"
18 #include "hpusb.h"
19 #include "otus.ini"
20
21 extern const u32_t zcFwImage[];
22 extern const u32_t zcFwImageSize;
23 extern const u32_t zcDKFwImage[];
24 extern const u32_t zcDKFwImageSize;
25 extern const u32_t zcFwImageSPI[];
26 extern const u32_t zcFwImageSPISize;
27
28 #ifdef ZM_OTUS_LINUX_PHASE_2
29 extern const u32_t zcFwBufImage[];
30 extern const u32_t zcFwBufImageSize;
31 extern const u32_t zcP2FwImage[];
32 extern const u32_t zcP2FwImageSize;
33 #endif
34 extern void zfInitCmdQueue(zdev_t* dev);
35 extern u16_t zfIssueCmd(zdev_t* dev, u32_t* cmd, u16_t cmdLen,
36 u16_t src, u8_t* buf);
37 extern void zfIdlRsp(zdev_t* dev, u32_t* rsp, u16_t rspLen);
38 extern u16_t zfDelayWriteInternalReg(zdev_t* dev, u32_t addr, u32_t val);
39 extern u16_t zfFlushDelayWrite(zdev_t* dev);
40 extern void zfUsbInit(zdev_t* dev);
41 extern u16_t zfFirmwareDownload(zdev_t* dev, u32_t* fw, u32_t len, u32_t offset);
42 extern u16_t zfFirmwareDownloadNotJump(zdev_t* dev, u32_t* fw, u32_t len, u32_t offset);
43 extern void zfUsbFree(zdev_t* dev);
44 extern u16_t zfCwmIsExtChanBusy(u32_t ctlBusy, u32_t extBusy);
45 extern void zfCoreCwmBusy(zdev_t* dev, u16_t busy);
46
47 /* Prototypes */
48 void zfInitRf(zdev_t* dev, u32_t frequency);
49 void zfInitPhy(zdev_t* dev, u32_t frequency, u8_t bw40);
50 void zfInitMac(zdev_t* dev);
51
52 void zfSetPowerCalTable(zdev_t* dev, u32_t frequency, u8_t bw40, u8_t extOffset);
53 void zfInitPowerCal(zdev_t* dev);
54
55 #ifdef ZM_DRV_INIT_USB_MODE
56 void zfInitUsbMode(zdev_t* dev);
57 u16_t zfHpUsbReset(zdev_t* dev);
58 #endif
59
60 /* Bank 0 1 2 3 5 6 7 */
61 void zfSetRfRegs(zdev_t* dev, u32_t frequency);
62 /* Bank 4 */
63 void zfSetBank4AndPowerTable(zdev_t* dev, u32_t frequency, u8_t bw40,
64 u8_t extOffset);
65 /* Get param for turnoffdyn */
66 void zfGetHwTurnOffdynParam(zdev_t* dev,
67 u32_t frequency, u8_t bw40, u8_t extOffset,
68 int* delta_slope_coeff_exp,
69 int* delta_slope_coeff_man,
70 int* delta_slope_coeff_exp_shgi,
71 int* delta_slope_coeff_man_shgi);
72
73 void zfSelAdcClk(zdev_t* dev, u8_t bw40, u32_t frequency);
74 u32_t zfHpEchoCommand(zdev_t* dev, u32_t value);
75
76
77
78 #define zm_hp_priv(x) (((struct zsHpPriv*)wd->hpPrivate)->x)
79 struct zsHpPriv zgHpPriv;
80
81 #define ZM_FIRMWARE_WLAN_ADDR 0x200000
82 #define ZM_FIRMWARE_SPI_ADDR 0x114000
83 /* 0: real chip 1: FPGA test */
84 #define ZM_FPGA_PHY 0
85
86 #define reg_write(addr, val) zfDelayWriteInternalReg(dev, addr+0x1bc000, val)
87 #define zm_min(A, B) ((A>B)? B:A)
88
89
90 /******************** Intialization ********************/
91 u16_t zfHpInit(zdev_t* dev, u32_t frequency)
92 {
93 u16_t ret;
94 zmw_get_wlan_dev(dev);
95
96 /* Initializa HAL Plus private variables */
97 wd->hpPrivate = &zgHpPriv;
98
99 ((struct zsHpPriv*)wd->hpPrivate)->halCapability = ZM_HP_CAP_11N;
100
101 ((struct zsHpPriv*)wd->hpPrivate)->hwFrequency = 0;
102 ((struct zsHpPriv*)wd->hpPrivate)->hwBw40 = 0;
103 ((struct zsHpPriv*)wd->hpPrivate)->hwExtOffset = 0;
104
105 ((struct zsHpPriv*)wd->hpPrivate)->disableDfsCh = 0;
106
107 ((struct zsHpPriv*)wd->hpPrivate)->ledMode[0] = 1;
108 ((struct zsHpPriv*)wd->hpPrivate)->ledMode[1] = 1;
109 ((struct zsHpPriv*)wd->hpPrivate)->strongRSSI = 0;
110 ((struct zsHpPriv*)wd->hpPrivate)->rxStrongRSSI = 0;
111
112 ((struct zsHpPriv*)wd->hpPrivate)->slotType = 1;
113 ((struct zsHpPriv*)wd->hpPrivate)->aggPktNum = 0x10000a;
114
115 ((struct zsHpPriv*)wd->hpPrivate)->eepromImageIndex = 0;
116
117
118 ((struct zsHpPriv*)wd->hpPrivate)->eepromImageRdReq = 0;
119 #ifdef ZM_OTUS_RX_STREAM_MODE
120 ((struct zsHpPriv*)wd->hpPrivate)->remainBuf = NULL;
121 ((struct zsHpPriv*)wd->hpPrivate)->usbRxRemainLen = 0;
122 ((struct zsHpPriv*)wd->hpPrivate)->usbRxPktLen = 0;
123 ((struct zsHpPriv*)wd->hpPrivate)->usbRxPadLen = 0;
124 ((struct zsHpPriv*)wd->hpPrivate)->usbRxTransferLen = 0;
125 #endif
126
127 ((struct zsHpPriv*)wd->hpPrivate)->enableBBHeavyClip = 1;
128 ((struct zsHpPriv*)wd->hpPrivate)->hwBBHeavyClip = 1; // force enable 8107
129 ((struct zsHpPriv*)wd->hpPrivate)->doBBHeavyClip = 0;
130 ((struct zsHpPriv*)wd->hpPrivate)->setValueHeavyClip = 0;
131
132
133 /* Initialize driver core */
134 zfInitCmdQueue(dev);
135
136 /* Initialize USB */
137 zfUsbInit(dev);
138
139 #if ZM_SW_LOOP_BACK != 1
140
141 /* TODO : [Download FW] */
142 if (wd->modeMDKEnable)
143 {
144 /* download the MDK firmware */
145 if ((ret = zfFirmwareDownload(dev, (u32_t*)zcDKFwImage,
146 (u32_t)zcDKFwImageSize, ZM_FIRMWARE_WLAN_ADDR)) != ZM_SUCCESS)
147 {
148 /* TODO : exception handling */
149 //return 1;
150 }
151 }
152 else
153 {
154 #ifndef ZM_OTUS_LINUX_PHASE_2
155 /* donwload the normal frimware */
156 if ((ret = zfFirmwareDownload(dev, (u32_t*)zcFwImage,
157 (u32_t)zcFwImageSize, ZM_FIRMWARE_WLAN_ADDR)) != ZM_SUCCESS)
158 {
159 /* TODO : exception handling */
160 //return 1;
161 }
162 #else
163
164 // 1-PH fw: ReadMac() store some global variable
165 if ((ret = zfFirmwareDownloadNotJump(dev, (u32_t*)zcFwBufImage,
166 (u32_t)zcFwBufImageSize, 0x102800)) != ZM_SUCCESS)
167 {
168 DbgPrint("Dl zcFwBufImage failed!");
169 }
170
171 zfwSleep(dev, 1000);
172
173 if ((ret = zfFirmwareDownload(dev, (u32_t*)zcFwImage,
174 (u32_t)zcFwImageSize, ZM_FIRMWARE_WLAN_ADDR)) != ZM_SUCCESS)
175 {
176 DbgPrint("Dl zcFwBufImage failed!");
177 }
178 #endif
179 }
180 #endif
181
182 #ifdef ZM_DRV_INIT_USB_MODE
183 /* Init USB Mode */
184 zfInitUsbMode(dev);
185
186 /* Do the USB Reset */
187 zfHpUsbReset(dev);
188 #endif
189
190 /* Register setting */
191 /* ZM_DRIVER_MODEL_TYPE_MDK
192 * 1=>for MDK, disable init RF, PHY, and MAC,
193 * 0=>normal init
194 */
195 //#if ((ZM_SW_LOOP_BACK != 1) && (ZM_DRIVER_MODEL_TYPE_MDK !=1))
196 #if ZM_SW_LOOP_BACK != 1
197 if(!wd->modeMDKEnable)
198 {
199 /* Init MAC */
200 zfInitMac(dev);
201
202 #if ZM_FW_LOOP_BACK != 1
203 /* Init PHY */
204 zfInitPhy(dev, frequency, 0);
205
206 /* Init RF */
207 zfInitRf(dev, frequency);
208
209 #if ZM_FPGA_PHY == 0
210 /* BringUp issue */
211 //zfDelayWriteInternalReg(dev, 0x9800+0x1bc000, 0x10000007);
212 //zfFlushDelayWrite(dev);
213 #endif
214
215 #endif /* end of ZM_FW_LOOP_BACK != 1 */
216 }
217 #endif /* end of ((ZM_SW_LOOP_BACK != 1) && (ZM_DRIVER_MODEL_TYPE_MDK !=1)) */
218
219 zfHpEchoCommand(dev, 0xAABBCCDD);
220
221 return 0;
222 }
223
224
225 u16_t zfHpReinit(zdev_t* dev, u32_t frequency)
226 {
227 u16_t ret;
228 zmw_get_wlan_dev(dev);
229
230 ((struct zsHpPriv*)wd->hpPrivate)->halReInit = 1;
231
232 ((struct zsHpPriv*)wd->hpPrivate)->strongRSSI = 0;
233 ((struct zsHpPriv*)wd->hpPrivate)->rxStrongRSSI = 0;
234
235 #ifdef ZM_OTUS_RX_STREAM_MODE
236 if (((struct zsHpPriv*)wd->hpPrivate)->remainBuf != NULL)
237 {
238 zfwBufFree(dev, ((struct zsHpPriv*)wd->hpPrivate)->remainBuf, 0);
239 }
240 ((struct zsHpPriv*)wd->hpPrivate)->remainBuf = NULL;
241 ((struct zsHpPriv*)wd->hpPrivate)->usbRxRemainLen = 0;
242 ((struct zsHpPriv*)wd->hpPrivate)->usbRxPktLen = 0;
243 ((struct zsHpPriv*)wd->hpPrivate)->usbRxPadLen = 0;
244 ((struct zsHpPriv*)wd->hpPrivate)->usbRxTransferLen = 0;
245 #endif
246
247 zfInitCmdQueue(dev);
248 zfCoreReinit(dev);
249
250 #ifndef ZM_OTUS_LINUX_PHASE_2
251 /* Download firmware */
252 if ((ret = zfFirmwareDownload(dev, (u32_t*)zcFwImage,
253 (u32_t)zcFwImageSize, ZM_FIRMWARE_WLAN_ADDR)) != ZM_SUCCESS)
254 {
255 /* TODO : exception handling */
256 //return 1;
257 }
258 #else
259 if ((ret = zfFirmwareDownload(dev, (u32_t*)zcP2FwImage,
260 (u32_t)zcP2FwImageSize, ZM_FIRMWARE_WLAN_ADDR)) != ZM_SUCCESS)
261 {
262 /* TODO : exception handling */
263 //return 1;
264 }
265 #endif
266
267 #ifdef ZM_DRV_INIT_USB_MODE
268 /* Init USB Mode */
269 zfInitUsbMode(dev);
270
271 /* Do the USB Reset */
272 zfHpUsbReset(dev);
273 #endif
274
275 /* Init MAC */
276 zfInitMac(dev);
277
278 /* Init PHY */
279 zfInitPhy(dev, frequency, 0);
280 /* Init RF */
281 zfInitRf(dev, frequency);
282
283 #if ZM_FPGA_PHY == 0
284 /* BringUp issue */
285 //zfDelayWriteInternalReg(dev, 0x9800+0x1bc000, 0x10000007);
286 //zfFlushDelayWrite(dev);
287 #endif
288
289 zfHpEchoCommand(dev, 0xAABBCCDD);
290
291 return 0;
292 }
293
294
295 u16_t zfHpRelease(zdev_t* dev)
296 {
297 /* Free USB resource */
298 zfUsbFree(dev);
299
300 return 0;
301 }
302
303 /* MDK mode setting for dontRetransmit */
304 void zfHpConfigFM(zdev_t* dev, u32_t RxMaxSize, u32_t DontRetransmit)
305 {
306 u32_t cmd[3];
307 u16_t ret;
308
309 cmd[0] = 8 | (ZM_CMD_CONFIG << 8);
310 cmd[1] = RxMaxSize; /* zgRxMaxSize */
311 cmd[2] = DontRetransmit; /* zgDontRetransmit */
312
313 ret = zfIssueCmd(dev, cmd, 12, ZM_OID_INTERNAL_WRITE, 0);
314 }
315
316 const u8_t zcXpdToPd[16] =
317 {
318 /* 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xA, 0xB, 0xC, 0xD, 0xE, 0xF */
319 0x2, 0x2, 0x2, 0x1, 0x2, 0x2, 0x6, 0x2, 0x2, 0x3, 0x7, 0x2, 0xB, 0x2, 0x2, 0x2
320 };
321
322 /******************** RF and PHY ********************/
323
324 void zfInitPhy(zdev_t* dev, u32_t frequency, u8_t bw40)
325 {
326 u16_t i, j, k;
327 u16_t entries;
328 u16_t modesIndex = 0;
329 u16_t freqIndex = 0;
330 u32_t tmp, tmp1;
331 zmw_get_wlan_dev(dev);
332 struct zsHpPriv* hpPriv=wd->hpPrivate;
333 u32_t eepromBoardData[15][6] = {
334 /* Register A-20 A-20/40 G-20/40 G-20 G-Turbo */
335 {0x9964, 0, 0, 0, 0, 0},
336 {0x9960, 0, 0, 0, 0, 0},
337 {0xb960, 0, 0, 0, 0, 0},
338 {0x9844, 0, 0, 0, 0, 0},
339 {0x9850, 0, 0, 0, 0, 0},
340 {0x9834, 0, 0, 0, 0, 0},
341 {0x9828, 0, 0, 0, 0, 0},
342 {0xc864, 0, 0, 0, 0, 0},
343 {0x9848, 0, 0, 0, 0, 0},
344 {0xb848, 0, 0, 0, 0, 0},
345 {0xa20c, 0, 0, 0, 0, 0},
346 {0xc20c, 0, 0, 0, 0, 0},
347 {0x9920, 0, 0, 0, 0, 0},
348 {0xb920, 0, 0, 0, 0, 0},
349 {0xa258, 0, 0, 0, 0, 0},
350 };
351
352 /* #1 Save the initial value of the related RIFS register settings */
353 //((struct zsHpPriv*)wd->hpPrivate)->isInitialPhy++;
354
355 /*
356 * Setup the indices for the next set of register array writes
357 * PHY mode is static20 / 2040
358 * Frequency is 2.4GHz (B) / 5GHz (A)
359 */
360 if ( frequency > ZM_CH_G_14 )
361 {
362 /* 5GHz */
363 freqIndex = 1;
364 if (bw40)
365 {
366 modesIndex = 2;
367 zm_debug_msg0("init ar5416Modes in 2: A-20/40");
368 }
369 else
370 {
371 modesIndex = 1;
372 zm_debug_msg0("init ar5416Modes in 1: A-20");
373 }
374 }
375 else
376 {
377 /* 2.4GHz */
378 freqIndex = 2;
379 if (bw40)
380 {
381 modesIndex = 3;
382 zm_debug_msg0("init ar5416Modes in 3: G-20/40");
383 }
384 else
385 {
386 modesIndex = 4;
387 zm_debug_msg0("init ar5416Modes in 4: G-20");
388 }
389 }
390
391
392 #if ZM_FPGA_PHY == 1
393 /* Starting External Hainan Register Initialization */
394 /* TODO: */
395
396 zfwSleep(dev, 10);
397 #endif
398
399 /*
400 *Set correct Baseband to analog shift setting to access analog chips.
401 */
402 //reg_write(PHY_BASE, 0x00000007);
403 // reg_write(0x9800, 0x00000007);
404
405 /*
406 * Write addac shifts
407 */
408 // do this in firmware
409
410
411
412 /* Zeroize board data */
413 for (j=0; j<15; j++)
414 {
415 for (k=1; k<=4; k++)
416 {
417 eepromBoardData[j][k] = 0;
418 }
419 }
420 /*
421 * Register setting by mode
422 */
423
424 entries = sizeof(ar5416Modes) / sizeof(*ar5416Modes);
425 zm_msg1_scan(ZM_LV_2, "Modes register setting entries=", entries);
426 for (i=0; i<entries; i++)
427 {
428 #if 0
429 if ( ((struct zsHpPriv*)wd->hpPrivate)->hwNotFirstInit && (ar5416Modes[i][0] == 0xa27c) )
430 {
431 /* Force disable CR671 bit20 / 7823 */
432 /* The bug has to do with the polarity of the pdadc offset calibration. There */
433 /* is an initial calibration that is OK, and there is a continuous */
434 /* calibration that updates the pddac with the wrong polarity. Fortunately */
435 /* the second loop can be disabled with a bit called en_pd_dc_offset_thr. */
436
437 reg_write(ar5416Modes[i][0], (ar5416Modes[i][modesIndex]& 0xffefffff) );
438 ((struct zsHpPriv*)wd->hpPrivate)->hwNotFirstInit = 1;
439 }
440 else
441 {
442 #endif
443 /* FirstTime Init or not 0xa27c(CR671) */
444 reg_write(ar5416Modes[i][0], ar5416Modes[i][modesIndex]);
445 // }
446 /* Initialize board data */
447 for (j=0; j<15; j++)
448 {
449 if (ar5416Modes[i][0] == eepromBoardData[j][0])
450 {
451 for (k=1; k<=4; k++)
452 {
453 eepromBoardData[j][k] = ar5416Modes[i][k];
454 }
455 }
456 }
457 /* #1 Save the initial value of the related RIFS register settings */
458 //if( ((struct zsHpPriv*)wd->hpPrivate)->isInitialPhy == 1 )
459 {
460 switch(ar5416Modes[i][0])
461 {
462 case 0x9850 :
463 ((struct zsHpPriv*)wd->hpPrivate)->initDesiredSigSize = ar5416Modes[i][modesIndex];
464 break;
465 case 0x985c :
466 ((struct zsHpPriv*)wd->hpPrivate)->initAGC = ar5416Modes[i][modesIndex];
467 break;
468 case 0x9860 :
469 ((struct zsHpPriv*)wd->hpPrivate)->initAgcControl = ar5416Modes[i][modesIndex];
470 break;
471 case 0x9918 :
472 ((struct zsHpPriv*)wd->hpPrivate)->initSearchStartDelay = ar5416Modes[i][modesIndex];
473 break;
474 case 0x99ec :
475 ((struct zsHpPriv*)wd->hpPrivate)->initRIFSSearchParams = ar5416Modes[i][modesIndex];
476 break;
477 case 0xa388 :
478 ((struct zsHpPriv*)wd->hpPrivate)->initFastChannelChangeControl = ar5416Modes[i][modesIndex];
479 default :
480 break;
481 }
482 }
483 }
484 #if 0
485 zfFlushDelayWrite(dev);
486
487 /*
488 * Common Register setting
489 */
490 entries = sizeof(ar5416Common) / sizeof(*ar5416Common);
491 for (i=0; i<entries; i++)
492 {
493 reg_write(ar5416Common[i][0], ar5416Common[i][1]);
494 }
495 zfFlushDelayWrite(dev);
496
497 /*
498 * RF Gain setting by freqIndex
499 */
500 entries = sizeof(ar5416BB_RfGain) / sizeof(*ar5416BB_RfGain);
501 for (i=0; i<entries; i++)
502 {
503 reg_write(ar5416BB_RfGain[i][0], ar5416BB_RfGain[i][freqIndex]);
504 }
505 zfFlushDelayWrite(dev);
506
507 /*
508 * Moved ar5416InitChainMask() here to ensure the swap bit is set before
509 * the pdadc table is written. Swap must occur before any radio dependent
510 * replicated register access. The pdadc curve addressing in particular
511 * depends on the consistent setting of the swap bit.
512 */
513 //ar5416InitChainMask(pDev);
514
515 /* Setup the transmit power values. */
516 // TODO
517 #endif
518
519 /* Update 5G board data */
520 //Ant control common
521 tmp = hpPriv->eepromImage[0x100+0x144*2/4];
522 eepromBoardData[0][1] = tmp;
523 eepromBoardData[0][2] = tmp;
524 //Ant control chain 0
525 tmp = hpPriv->eepromImage[0x100+0x140*2/4];
526 eepromBoardData[1][1] = tmp;
527 eepromBoardData[1][2] = tmp;
528 //Ant control chain 2
529 tmp = hpPriv->eepromImage[0x100+0x142*2/4];
530 eepromBoardData[2][1] = tmp;
531 eepromBoardData[2][2] = tmp;
532 //SwSettle
533 tmp = hpPriv->eepromImage[0x100+0x146*2/4];
534 tmp = (tmp >> 16) & 0x7f;
535 eepromBoardData[3][1] &= (~((u32_t)0x3f80));
536 eepromBoardData[3][1] |= (tmp << 7);
537 #if 0
538 //swSettleHt40
539 tmp = hpPriv->eepromImage[0x100+0x158*2/4];
540 tmp = (tmp) & 0x7f;
541 eepromBoardData[3][2] &= (~((u32_t)0x3f80));
542 eepromBoardData[3][2] |= (tmp << 7);
543 #endif
544 //adcDesired, pdaDesired
545 tmp = hpPriv->eepromImage[0x100+0x148*2/4];
546 tmp = (tmp >> 24);
547 tmp1 = hpPriv->eepromImage[0x100+0x14a*2/4];
548 tmp1 = tmp1 & 0xff;
549 tmp = tmp + (tmp1<<8);
550 eepromBoardData[4][1] &= (~((u32_t)0xffff));
551 eepromBoardData[4][1] |= tmp;
552 eepromBoardData[4][2] &= (~((u32_t)0xffff));
553 eepromBoardData[4][2] |= tmp;
554 //TxEndToXpaOff, TxFrameToXpaOn
555 tmp = hpPriv->eepromImage[0x100+0x14a*2/4];
556 tmp = (tmp >> 24) & 0xff;
557 tmp1 = hpPriv->eepromImage[0x100+0x14c*2/4];
558 tmp1 = (tmp1 >> 8) & 0xff;
559 tmp = (tmp<<24) + (tmp<<16) + (tmp1<<8) + tmp1;
560 eepromBoardData[5][1] = tmp;
561 eepromBoardData[5][2] = tmp;
562 //TxEnaToRxOm
563 tmp = hpPriv->eepromImage[0x100+0x14c*2/4] & 0xff;
564 eepromBoardData[6][1] &= (~((u32_t)0xff0000));
565 eepromBoardData[6][1] |= (tmp<<16);
566 eepromBoardData[6][2] &= (~((u32_t)0xff0000));
567 eepromBoardData[6][2] |= (tmp<<16);
568 //Thresh62
569 tmp = hpPriv->eepromImage[0x100+0x14c*2/4];
570 tmp = (tmp >> 16) & 0x7f;
571 eepromBoardData[7][1] &= (~((u32_t)0x7f000));
572 eepromBoardData[7][1] |= (tmp<<12);
573 eepromBoardData[7][2] &= (~((u32_t)0x7f000));
574 eepromBoardData[7][2] |= (tmp<<12);
575 //TxRxAtten chain_0
576 tmp = hpPriv->eepromImage[0x100+0x146*2/4];
577 tmp = (tmp >> 24) & 0x3f;
578 eepromBoardData[8][1] &= (~((u32_t)0x3f000));
579 eepromBoardData[8][1] |= (tmp<<12);
580 eepromBoardData[8][2] &= (~((u32_t)0x3f000));
581 eepromBoardData[8][2] |= (tmp<<12);
582 //TxRxAtten chain_2
583 tmp = hpPriv->eepromImage[0x100+0x148*2/4] & 0x3f;
584 eepromBoardData[9][1] &= (~((u32_t)0x3f000));
585 eepromBoardData[9][1] |= (tmp<<12);
586 eepromBoardData[9][2] &= (~((u32_t)0x3f000));
587 eepromBoardData[9][2] |= (tmp<<12);
588 //TxRxMargin chain_0
589 tmp = hpPriv->eepromImage[0x100+0x148*2/4];
590 tmp = (tmp >> 8) & 0x3f;
591 eepromBoardData[10][1] &= (~((u32_t)0xfc0000));
592 eepromBoardData[10][1] |= (tmp<<18);
593 eepromBoardData[10][2] &= (~((u32_t)0xfc0000));
594 eepromBoardData[10][2] |= (tmp<<18);
595 //TxRxMargin chain_2
596 tmp = hpPriv->eepromImage[0x100+0x148*2/4];
597 tmp = (tmp >> 16) & 0x3f;
598 eepromBoardData[11][1] &= (~((u32_t)0xfc0000));
599 eepromBoardData[11][1] |= (tmp<<18);
600 eepromBoardData[11][2] &= (~((u32_t)0xfc0000));
601 eepromBoardData[11][2] |= (tmp<<18);
602 //iqCall chain_0, iqCallQ chain_0
603 tmp = hpPriv->eepromImage[0x100+0x14e*2/4];
604 tmp = (tmp >> 24) & 0x3f;
605 tmp1 = hpPriv->eepromImage[0x100+0x150*2/4];
606 tmp1 = (tmp1 >> 8) & 0x1f;
607 tmp = (tmp<<5) + tmp1;
608 eepromBoardData[12][1] &= (~((u32_t)0x7ff));
609 eepromBoardData[12][1] |= (tmp);
610 eepromBoardData[12][2] &= (~((u32_t)0x7ff));
611 eepromBoardData[12][2] |= (tmp);
612 //iqCall chain_2, iqCallQ chain_2
613 tmp = hpPriv->eepromImage[0x100+0x150*2/4];
614 tmp = tmp & 0x3f;
615 tmp1 = hpPriv->eepromImage[0x100+0x150*2/4];
616 tmp1 = (tmp1 >> 16) & 0x1f;
617 tmp = (tmp<<5) + tmp1;
618 eepromBoardData[13][1] &= (~((u32_t)0x7ff));
619 eepromBoardData[13][1] |= (tmp);
620 eepromBoardData[13][2] &= (~((u32_t)0x7ff));
621 eepromBoardData[13][2] |= (tmp);
622 //bsw_Margin chain_0
623 tmp = hpPriv->eepromImage[0x100+0x156*2/4];
624 tmp = (tmp >> 16) & 0xf;
625 eepromBoardData[10][1] &= (~((u32_t)0x3c00));
626 eepromBoardData[10][1] |= (tmp << 10);
627 eepromBoardData[10][2] &= (~((u32_t)0x3c00));
628 eepromBoardData[10][2] |= (tmp << 10);
629 //xpd gain mask
630 tmp = hpPriv->eepromImage[0x100+0x14e*2/4];
631 tmp = (tmp >> 8) & 0xf;
632 eepromBoardData[14][1] &= (~((u32_t)0xf0000));
633 eepromBoardData[14][1] |= (zcXpdToPd[tmp] << 16);
634 eepromBoardData[14][2] &= (~((u32_t)0xf0000));
635 eepromBoardData[14][2] |= (zcXpdToPd[tmp] << 16);
636 #if 0
637 //bsw_Atten chain_0
638 tmp = hpPriv->eepromImage[0x100+0x156*2/4];
639 tmp = (tmp) & 0x1f;
640 eepromBoardData[10][1] &= (~((u32_t)0x1f));
641 eepromBoardData[10][1] |= (tmp);
642 eepromBoardData[10][2] &= (~((u32_t)0x1f));
643 eepromBoardData[10][2] |= (tmp);
644 //bsw_Margin chain_2
645 tmp = hpPriv->eepromImage[0x100+0x156*2/4];
646 tmp = (tmp >> 24) & 0xf;
647 eepromBoardData[11][1] &= (~((u32_t)0x3c00));
648 eepromBoardData[11][1] |= (tmp << 10);
649 eepromBoardData[11][2] &= (~((u32_t)0x3c00));
650 eepromBoardData[11][2] |= (tmp << 10);
651 //bsw_Atten chain_2
652 tmp = hpPriv->eepromImage[0x100+0x156*2/4];
653 tmp = (tmp >> 8) & 0x1f;
654 eepromBoardData[11][1] &= (~((u32_t)0x1f));
655 eepromBoardData[11][1] |= (tmp);
656 eepromBoardData[11][2] &= (~((u32_t)0x1f));
657 eepromBoardData[11][2] |= (tmp);
658 #endif
659
660 /* Update 2.4G board data */
661 //Ant control common
662 tmp = hpPriv->eepromImage[0x100+0x170*2/4];
663 tmp = tmp >> 24;
664 tmp1 = hpPriv->eepromImage[0x100+0x172*2/4];
665 tmp = tmp + (tmp1 << 8);
666 eepromBoardData[0][3] = tmp;
667 eepromBoardData[0][4] = tmp;
668 //Ant control chain 0
669 tmp = hpPriv->eepromImage[0x100+0x16c*2/4];
670 tmp = tmp >> 24;
671 tmp1 = hpPriv->eepromImage[0x100+0x16e*2/4];
672 tmp = tmp + (tmp1 << 8);
673 eepromBoardData[1][3] = tmp;
674 eepromBoardData[1][4] = tmp;
675 //Ant control chain 2
676 tmp = hpPriv->eepromImage[0x100+0x16e*2/4];
677 tmp = tmp >> 24;
678 tmp1 = hpPriv->eepromImage[0x100+0x170*2/4];
679 tmp = tmp + (tmp1 << 8);
680 eepromBoardData[2][3] = tmp;
681 eepromBoardData[2][4] = tmp;
682 //SwSettle
683 tmp = hpPriv->eepromImage[0x100+0x174*2/4];
684 tmp = (tmp >> 8) & 0x7f;
685 eepromBoardData[3][4] &= (~((u32_t)0x3f80));
686 eepromBoardData[3][4] |= (tmp << 7);
687 #if 0
688 //swSettleHt40
689 tmp = hpPriv->eepromImage[0x100+0x184*2/4];
690 tmp = (tmp >> 24) & 0x7f;
691 eepromBoardData[3][3] &= (~((u32_t)0x3f80));
692 eepromBoardData[3][3] |= (tmp << 7);
693 #endif
694 //adcDesired, pdaDesired
695 tmp = hpPriv->eepromImage[0x100+0x176*2/4];
696 tmp = (tmp >> 16) & 0xff;
697 tmp1 = hpPriv->eepromImage[0x100+0x176*2/4];
698 tmp1 = tmp1 >> 24;
699 tmp = tmp + (tmp1<<8);
700 eepromBoardData[4][3] &= (~((u32_t)0xffff));
701 eepromBoardData[4][3] |= tmp;
702 eepromBoardData[4][4] &= (~((u32_t)0xffff));
703 eepromBoardData[4][4] |= tmp;
704 //TxEndToXpaOff, TxFrameToXpaOn
705 tmp = hpPriv->eepromImage[0x100+0x178*2/4];
706 tmp = (tmp >> 16) & 0xff;
707 tmp1 = hpPriv->eepromImage[0x100+0x17a*2/4];
708 tmp1 = tmp1 & 0xff;
709 tmp = (tmp << 24) + (tmp << 16) + (tmp1 << 8) + tmp1;
710 eepromBoardData[5][3] = tmp;
711 eepromBoardData[5][4] = tmp;
712 //TxEnaToRxOm
713 tmp = hpPriv->eepromImage[0x100+0x178*2/4];
714 tmp = (tmp >> 24);
715 eepromBoardData[6][3] &= (~((u32_t)0xff0000));
716 eepromBoardData[6][3] |= (tmp<<16);
717 eepromBoardData[6][4] &= (~((u32_t)0xff0000));
718 eepromBoardData[6][4] |= (tmp<<16);
719 //Thresh62
720 tmp = hpPriv->eepromImage[0x100+0x17a*2/4];
721 tmp = (tmp >> 8) & 0x7f;
722 eepromBoardData[7][3] &= (~((u32_t)0x7f000));
723 eepromBoardData[7][3] |= (tmp<<12);
724 eepromBoardData[7][4] &= (~((u32_t)0x7f000));
725 eepromBoardData[7][4] |= (tmp<<12);
726 //TxRxAtten chain_0
727 tmp = hpPriv->eepromImage[0x100+0x174*2/4];
728 tmp = (tmp >> 16) & 0x3f;
729 eepromBoardData[8][3] &= (~((u32_t)0x3f000));
730 eepromBoardData[8][3] |= (tmp<<12);
731 eepromBoardData[8][4] &= (~((u32_t)0x3f000));
732 eepromBoardData[8][4] |= (tmp<<12);
733 //TxRxAtten chain_2
734 tmp = hpPriv->eepromImage[0x100+0x174*2/4];
735 tmp = (tmp >> 24) & 0x3f;
736 eepromBoardData[9][3] &= (~((u32_t)0x3f000));
737 eepromBoardData[9][3] |= (tmp<<12);
738 eepromBoardData[9][4] &= (~((u32_t)0x3f000));
739 eepromBoardData[9][4] |= (tmp<<12);
740 //TxRxMargin chain_0
741 tmp = hpPriv->eepromImage[0x100+0x176*2/4];
742 tmp = (tmp) & 0x3f;
743 eepromBoardData[10][3] &= (~((u32_t)0xfc0000));
744 eepromBoardData[10][3] |= (tmp<<18);
745 eepromBoardData[10][4] &= (~((u32_t)0xfc0000));
746 eepromBoardData[10][4] |= (tmp<<18);
747 //TxRxMargin chain_2
748 tmp = hpPriv->eepromImage[0x100+0x176*2/4];
749 tmp = (tmp >> 8) & 0x3f;
750 eepromBoardData[11][3] &= (~((u32_t)0xfc0000));
751 eepromBoardData[11][3] |= (tmp<<18);
752 eepromBoardData[11][4] &= (~((u32_t)0xfc0000));
753 eepromBoardData[11][4] |= (tmp<<18);
754 //iqCall chain_0, iqCallQ chain_0
755 tmp = hpPriv->eepromImage[0x100+0x17c*2/4];
756 tmp = (tmp >> 16) & 0x3f;
757 tmp1 = hpPriv->eepromImage[0x100+0x17e*2/4];
758 tmp1 = (tmp1) & 0x1f;
759 tmp = (tmp<<5) + tmp1;
760 eepromBoardData[12][3] &= (~((u32_t)0x7ff));
761 eepromBoardData[12][3] |= (tmp);
762 eepromBoardData[12][4] &= (~((u32_t)0x7ff));
763 eepromBoardData[12][4] |= (tmp);
764 //iqCall chain_2, iqCallQ chain_2
765 tmp = hpPriv->eepromImage[0x100+0x17c*2/4];
766 tmp = (tmp>>24) & 0x3f;
767 tmp1 = hpPriv->eepromImage[0x100+0x17e*2/4];
768 tmp1 = (tmp1 >> 8) & 0x1f;
769 tmp = (tmp<<5) + tmp1;
770 eepromBoardData[13][3] &= (~((u32_t)0x7ff));
771 eepromBoardData[13][3] |= (tmp);
772 eepromBoardData[13][4] &= (~((u32_t)0x7ff));
773 eepromBoardData[13][4] |= (tmp);
774 //xpd gain mask
775 tmp = hpPriv->eepromImage[0x100+0x17c*2/4];
776 tmp = tmp & 0xf;
777 DbgPrint("xpd=0x%x, pd=0x%x\n", tmp, zcXpdToPd[tmp]);
778 eepromBoardData[14][3] &= (~((u32_t)0xf0000));
779 eepromBoardData[14][3] |= (zcXpdToPd[tmp] << 16);
780 eepromBoardData[14][4] &= (~((u32_t)0xf0000));
781 eepromBoardData[14][4] |= (zcXpdToPd[tmp] << 16);
782 #if 0
783 //bsw_Margin chain_0
784 tmp = hpPriv->eepromImage[0x100+0x184*2/4];
785 tmp = (tmp >> 8) & 0xf;
786 eepromBoardData[10][3] &= (~((u32_t)0x3c00));
787 eepromBoardData[10][3] |= (tmp << 10);
788 eepromBoardData[10][4] &= (~((u32_t)0x3c00));
789 eepromBoardData[10][4] |= (tmp << 10);
790 //bsw_Atten chain_0
791 tmp = hpPriv->eepromImage[0x100+0x182*2/4];
792 tmp = (tmp>>24) & 0x1f;
793 eepromBoardData[10][3] &= (~((u32_t)0x1f));
794 eepromBoardData[10][3] |= (tmp);
795 eepromBoardData[10][4] &= (~((u32_t)0x1f));
796 eepromBoardData[10][4] |= (tmp);
797 //bsw_Margin chain_2
798 tmp = hpPriv->eepromImage[0x100+0x184*2/4];
799 tmp = (tmp >> 16) & 0xf;
800 eepromBoardData[11][3] &= (~((u32_t)0x3c00));
801 eepromBoardData[11][3] |= (tmp << 10);
802 eepromBoardData[11][4] &= (~((u32_t)0x3c00));
803 eepromBoardData[11][4] |= (tmp << 10);
804 //bsw_Atten chain_2
805 tmp = hpPriv->eepromImage[0x100+0x184*2/4];
806 tmp = (tmp) & 0x1f;
807 eepromBoardData[11][3] &= (~((u32_t)0x1f));
808 eepromBoardData[11][3] |= (tmp);
809 eepromBoardData[11][4] &= (~((u32_t)0x1f));
810 eepromBoardData[11][4] |= (tmp);
811 #endif
812
813 #if 0
814 for (j=0; j<14; j++)
815 {
816 DbgPrint("%04x, %08x, %08x, %08x, %08x\n", eepromBoardData[j][0], eepromBoardData[j][1], eepromBoardData[j][2], eepromBoardData[j][3], eepromBoardData[j][4]);
817 }
818 #endif
819
820 if ((hpPriv->eepromImage[0x100+0x110*2/4]&0xff) == 0x80) //FEM TYPE
821 {
822 /* Update board data to registers */
823 for (j=0; j<15; j++)
824 {
825 reg_write(eepromBoardData[j][0], eepromBoardData[j][modesIndex]);
826
827 /* #1 Save the initial value of the related RIFS register settings */
828 //if( ((struct zsHpPriv*)wd->hpPrivate)->isInitialPhy == 1 )
829 {
830 switch(eepromBoardData[j][0])
831 {
832 case 0x9850 :
833 ((struct zsHpPriv*)wd->hpPrivate)->initDesiredSigSize = eepromBoardData[j][modesIndex];
834 break;
835 case 0x985c :
836 ((struct zsHpPriv*)wd->hpPrivate)->initAGC = eepromBoardData[j][modesIndex];
837 break;
838 case 0x9860 :
839 ((struct zsHpPriv*)wd->hpPrivate)->initAgcControl = eepromBoardData[j][modesIndex];
840 break;
841 case 0x9918 :
842 ((struct zsHpPriv*)wd->hpPrivate)->initSearchStartDelay = eepromBoardData[j][modesIndex];
843 break;
844 case 0x99ec :
845 ((struct zsHpPriv*)wd->hpPrivate)->initRIFSSearchParams = eepromBoardData[j][modesIndex];
846 break;
847 case 0xa388 :
848 ((struct zsHpPriv*)wd->hpPrivate)->initFastChannelChangeControl = eepromBoardData[j][modesIndex];
849 default :
850 break;
851 }
852 }
853 }
854 } /* if ((hpPriv->eepromImage[0x100+0x110*2/4]&0xff) == 0x80) //FEM TYPE */
855
856
857 /* Bringup issue : force tx gain */
858 //reg_write(0xa258, 0x0cc65381);
859 //reg_write(0xa274, 0x0a1a7c15);
860 zfInitPowerCal(dev);
861
862 if(frequency > ZM_CH_G_14)
863 {
864 zfDelayWriteInternalReg(dev, 0x1d4014, 0x5143);
865 }
866 else
867 {
868 zfDelayWriteInternalReg(dev, 0x1d4014, 0x5163);
869 }
870
871 zfFlushDelayWrite(dev);
872 }
873
874
875 void zfInitRf(zdev_t* dev, u32_t frequency)
876 {
877 u32_t cmd[8];
878 u16_t ret;
879 int delta_slope_coeff_exp;
880 int delta_slope_coeff_man;
881 int delta_slope_coeff_exp_shgi;
882 int delta_slope_coeff_man_shgi;
883
884 zmw_get_wlan_dev(dev);
885
886 zm_debug_msg1(" initRf frequency = ", frequency);
887
888 if (frequency == 0)
889 {
890 frequency = 2412;
891 }
892
893 /* Bank 0 1 2 3 5 6 7 */
894 zfSetRfRegs(dev, frequency);
895 /* Bank 4 */
896 zfSetBank4AndPowerTable(dev, frequency, 0, 0);
897
898 /* stroe frequency */
899 ((struct zsHpPriv*)wd->hpPrivate)->hwFrequency = (u16_t)frequency;
900
901 zfGetHwTurnOffdynParam(dev,
902 frequency, 0, 0,
903 &delta_slope_coeff_exp,
904 &delta_slope_coeff_man,
905 &delta_slope_coeff_exp_shgi,
906 &delta_slope_coeff_man_shgi);
907
908 /* related functions */
909 frequency = frequency*1000;
910 cmd[0] = 28 | (ZM_CMD_RF_INIT << 8);
911 cmd[1] = frequency;
912 cmd[2] = 0;//((struct zsHpPriv*)wd->hpPrivate)->hw_DYNAMIC_HT2040_EN;
913 cmd[3] = 1;//((wd->ExtOffset << 2) | ((struct zsHpPriv*)wd->hpPrivate)->hw_HT_ENABLE);
914 cmd[4] = delta_slope_coeff_exp;
915 cmd[5] = delta_slope_coeff_man;
916 cmd[6] = delta_slope_coeff_exp_shgi;
917 cmd[7] = delta_slope_coeff_man_shgi;
918
919 ret = zfIssueCmd(dev, cmd, 32, ZM_OID_INTERNAL_WRITE, 0);
920
921 // delay temporarily, wait for new PHY and RF
922 zfwSleep(dev, 1000);
923 }
924
925 int tn(int exp)
926 {
927 int i;
928 int tmp = 1;
929 for(i=0; i<exp; i++)
930 tmp = tmp*2;
931
932 return tmp;
933 }
934
935 /*int zfFloor(double indata)
936 {
937 if(indata<0)
938 return (int)indata-1;
939 else
940 return (int)indata;
941 }
942 */
943 u32_t reverse_bits(u32_t chan_sel)
944 {
945 /* reverse_bits */
946 u32_t chansel = 0;
947 u8_t i;
948
949 for (i=0; i<8; i++)
950 chansel |= ((chan_sel>>(7-i) & 0x1) << i);
951 return chansel;
952 }
953
954 /* Bank 0 1 2 3 5 6 7 */
955 void zfSetRfRegs(zdev_t* dev, u32_t frequency)
956 {
957 u16_t entries;
958 u16_t freqIndex = 0;
959 u16_t i;
960
961 //zmw_get_wlan_dev(dev);
962
963 if ( frequency > ZM_CH_G_14 )
964 {
965 /* 5G */
966 freqIndex = 1;
967 zm_msg0_scan(ZM_LV_2, "Set to 5GHz");
968
969 }
970 else
971 {
972 /* 2.4G */
973 freqIndex = 2;
974 zm_msg0_scan(ZM_LV_2, "Set to 2.4GHz");
975 }
976
977 #if 1
978 entries = sizeof(otusBank) / sizeof(*otusBank);
979 for (i=0; i<entries; i++)
980 {
981 reg_write(otusBank[i][0], otusBank[i][freqIndex]);
982 }
983 #else
984 /* Bank0 */
985 entries = sizeof(ar5416Bank0) / sizeof(*ar5416Bank0);
986 for (i=0; i<entries; i++)
987 {
988 reg_write(ar5416Bank0[i][0], ar5416Bank0[i][1]);
989 }
990 /* Bank1 */
991 entries = sizeof(ar5416Bank1) / sizeof(*ar5416Bank1);
992 for (i=0; i<entries; i++)
993 {
994 reg_write(ar5416Bank1[i][0], ar5416Bank1[i][1]);
995 }
996 /* Bank2 */
997 entries = sizeof(ar5416Bank2) / sizeof(*ar5416Bank2);
998 for (i=0; i<entries; i++)
999 {
1000 reg_write(ar5416Bank2[i][0], ar5416Bank2[i][1]);
1001 }
1002 /* Bank3 */
1003 entries = sizeof(ar5416Bank3) / sizeof(*ar5416Bank3);
1004 for (i=0; i<entries; i++)
1005 {
1006 reg_write(ar5416Bank3[i][0], ar5416Bank3[i][freqIndex]);
1007 }
1008 /* Bank5 */
1009 reg_write (0x98b0, 0x00000013);
1010 reg_write (0x98e4, 0x00000002);
1011 /* Bank6 */
1012 entries = sizeof(ar5416Bank6) / sizeof(*ar5416Bank6);
1013 for (i=0; i<entries; i++)
1014 {
1015 reg_write(ar5416Bank6[i][0], ar5416Bank6[i][freqIndex]);
1016 }
1017 /* Bank7 */
1018 entries = sizeof(ar5416Bank7) / sizeof(*ar5416Bank7);
1019 for (i=0; i<entries; i++)
1020 {
1021 reg_write(ar5416Bank7[i][0], ar5416Bank7[i][1]);
1022 }
1023 #endif
1024
1025 zfFlushDelayWrite(dev);
1026 }
1027
1028 /* Bank 4 */
1029 void zfSetBank4AndPowerTable(zdev_t* dev, u32_t frequency, u8_t bw40,
1030 u8_t extOffset)
1031 {
1032 u32_t chup = 1;
1033 u32_t bmode_LF_synth_freq = 0;
1034 u32_t amode_refsel_1 = 0;
1035 u32_t amode_refsel_0 = 1;
1036 u32_t addr2 = 1;
1037 u32_t addr1 = 0;
1038 u32_t addr0 = 0;
1039
1040 u32_t d1;
1041 u32_t d0;
1042 u32_t tmp_0;
1043 u32_t tmp_1;
1044 u32_t data0;
1045 u32_t data1;
1046
1047 u8_t chansel;
1048 u8_t chan_sel;
1049 u32_t temp_chan_sel;
1050
1051 u16_t i;
1052
1053 zmw_get_wlan_dev(dev);
1054
1055
1056 /* if enable 802.11h, need to record curent channel index in channel array */
1057 if (wd->sta.DFSEnable)
1058 {
1059 for (i = 0; i < wd->regulationTable.allowChannelCnt; i++)
1060 {
1061 if (wd->regulationTable.allowChannel[i].channel == frequency)
1062 break;
1063 }
1064 wd->regulationTable.CurChIndex = i;
1065 }
1066
1067 if (bw40 == 1)
1068 {
1069 if (extOffset == 1)
1070 {
1071 frequency += 10;
1072 }
1073 else
1074 {
1075 frequency -= 10;
1076 }
1077
1078 }
1079
1080
1081 if ( frequency > 3000 )
1082 {
1083 if ( frequency % 10 )
1084 {
1085 /* 5M */
1086 chan_sel = (u8_t)((frequency - 4800)/5);
1087 chan_sel = (u8_t)(chan_sel & 0xff);
1088 chansel = (u8_t)reverse_bits(chan_sel);
1089 }
1090 else
1091 {
1092 /* 10M : improve Tx EVM */
1093 chan_sel = (u8_t)((frequency - 4800)/10);
1094 chan_sel = (u8_t)(chan_sel & 0xff)<<1;
1095 chansel = (u8_t)reverse_bits(chan_sel);
1096
1097 amode_refsel_1 = 1;
1098 amode_refsel_0 = 0;
1099 }
1100 }
1101 else
1102 {
1103 //temp_chan_sel = (((frequency - 672)*2) - 3040)/10;
1104 if (frequency == 2484)
1105 {
1106 temp_chan_sel = 10 + (frequency - 2274)/5 ;
1107 bmode_LF_synth_freq = 1;
1108 }
1109 else
1110 {
1111 temp_chan_sel = 16 + (frequency - 2272)/5 ;
1112 bmode_LF_synth_freq = 0;
1113 }
1114 chan_sel = (u8_t)(temp_chan_sel << 2) & 0xff;
1115 chansel = (u8_t)reverse_bits(chan_sel);
1116 }
1117
1118 d1 = chansel; //# 8 bits of chan
1119 d0 = addr0<<7 | addr1<<6 | addr2<<5
1120 | amode_refsel_0<<3 | amode_refsel_1<<2
1121 | bmode_LF_synth_freq<<1 | chup;
1122
1123 tmp_0 = d0 & 0x1f; //# 5-1
1124 tmp_1 = d1 & 0x1f; //# 5-1
1125 data0 = tmp_1<<5 | tmp_0;
1126
1127 tmp_0 = d0>>5 & 0x7; //# 8-6
1128 tmp_1 = d1>>5 & 0x7; //# 8-6
1129 data1 = tmp_1<<5 | tmp_0;
1130
1131 /* Bank4 */
1132 reg_write (0x9800+(0x2c<<2), data0);
1133 reg_write (0x9800+(0x3a<<2), data1);
1134 //zm_debug_msg1("0x9800+(0x2c<<2 = ", data0);
1135 //zm_debug_msg1("0x9800+(0x3a<<2 = ", data1);
1136
1137
1138 zfFlushDelayWrite(dev);
1139
1140 zfwSleep(dev, 10);
1141
1142 return;
1143 }
1144
1145
1146 struct zsPhyFreqPara
1147 {
1148 u32_t coeff_exp;
1149 u32_t coeff_man;
1150 u32_t coeff_exp_shgi;
1151 u32_t coeff_man_shgi;
1152 };
1153
1154 struct zsPhyFreqTable
1155 {
1156 u32_t frequency;
1157 struct zsPhyFreqPara FpgaDynamicHT;
1158 struct zsPhyFreqPara FpgaStaticHT;
1159 struct zsPhyFreqPara ChipST20Mhz;
1160 struct zsPhyFreqPara Chip2040Mhz;
1161 struct zsPhyFreqPara Chip2040ExtAbove;
1162 };
1163
1164 const struct zsPhyFreqTable zgPhyFreqCoeff[] =
1165 {
1166 /*Index freq FPGA DYNAMIC_HT2040_EN FPGA STATIC_HT20 Real Chip static20MHz Real Chip 2040MHz Real Chip 2040Mhz */
1167 /* fclk = 10.8 21.6 40 ext below 40 ext above 40 */
1168 /* 0 */ {2412, {5, 23476, 5, 21128}, {4, 23476, 4, 21128}, {3, 21737, 3, 19563}, {3, 21827, 3, 19644}, {3, 21647, 3, 19482}},
1169 /* 1 */ {2417, {5, 23427, 5, 21084}, {4, 23427, 4, 21084}, {3, 21692, 3, 19523}, {3, 21782, 3, 19604}, {3, 21602, 3, 19442}},
1170 /* 2 */ {2422, {5, 23379, 5, 21041}, {4, 23379, 4, 21041}, {3, 21647, 3, 19482}, {3, 21737, 3, 19563}, {3, 21558, 3, 19402}},
1171 /* 3 */ {2427, {5, 23330, 5, 20997}, {4, 23330, 4, 20997}, {3, 21602, 3, 19442}, {3, 21692, 3, 19523}, {3, 21514, 3, 19362}},
1172 /* 4 */ {2432, {5, 23283, 5, 20954}, {4, 23283, 4, 20954}, {3, 21558, 3, 19402}, {3, 21647, 3, 19482}, {3, 21470, 3, 19323}},
1173 /* 5 */ {2437, {5, 23235, 5, 20911}, {4, 23235, 4, 20911}, {3, 21514, 3, 19362}, {3, 21602, 3, 19442}, {3, 21426, 3, 19283}},
1174 /* 6 */ {2442, {5, 23187, 5, 20868}, {4, 23187, 4, 20868}, {3, 21470, 3, 19323}, {3, 21558, 3, 19402}, {3, 21382, 3, 19244}},
1175 /* 7 */ {2447, {5, 23140, 5, 20826}, {4, 23140, 4, 20826}, {3, 21426, 3, 19283}, {3, 21514, 3, 19362}, {3, 21339, 3, 19205}},
1176 /* 8 */ {2452, {5, 23093, 5, 20783}, {4, 23093, 4, 20783}, {3, 21382, 3, 19244}, {3, 21470, 3, 19323}, {3, 21295, 3, 19166}},
1177 /* 9 */ {2457, {5, 23046, 5, 20741}, {4, 23046, 4, 20741}, {3, 21339, 3, 19205}, {3, 21426, 3, 19283}, {3, 21252, 3, 19127}},
1178 /* 10 */ {2462, {5, 22999, 5, 20699}, {4, 22999, 4, 20699}, {3, 21295, 3, 19166}, {3, 21382, 3, 19244}, {3, 21209, 3, 19088}},
1179 /* 11 */ {2467, {5, 22952, 5, 20657}, {4, 22952, 4, 20657}, {3, 21252, 3, 19127}, {3, 21339, 3, 19205}, {3, 21166, 3, 19050}},
1180 /* 12 */ {2472, {5, 22906, 5, 20615}, {4, 22906, 4, 20615}, {3, 21209, 3, 19088}, {3, 21295, 3, 19166}, {3, 21124, 3, 19011}},
1181 /* 13 */ {2484, {5, 22795, 5, 20516}, {4, 22795, 4, 20516}, {3, 21107, 3, 18996}, {3, 21192, 3, 19073}, {3, 21022, 3, 18920}},
1182 /* 14 */ {4920, {6, 23018, 6, 20716}, {5, 23018, 5, 20716}, {4, 21313, 4, 19181}, {4, 21356, 4, 19220}, {4, 21269, 4, 19142}},
1183 /* 15 */ {4940, {6, 22924, 6, 20632}, {5, 22924, 5, 20632}, {4, 21226, 4, 19104}, {4, 21269, 4, 19142}, {4, 21183, 4, 19065}},
1184 /* 16 */ {4960, {6, 22832, 6, 20549}, {5, 22832, 5, 20549}, {4, 21141, 4, 19027}, {4, 21183, 4, 19065}, {4, 21098, 4, 18988}},
1185 /* 17 */ {4980, {6, 22740, 6, 20466}, {5, 22740, 5, 20466}, {4, 21056, 4, 18950}, {4, 21098, 4, 18988}, {4, 21014, 4, 18912}},
1186 /* 18 */ {5040, {6, 22469, 6, 20223}, {5, 22469, 5, 20223}, {4, 20805, 4, 18725}, {4, 20846, 4, 18762}, {4, 20764, 4, 18687}},
1187 /* 19 */ {5060, {6, 22381, 6, 20143}, {5, 22381, 5, 20143}, {4, 20723, 4, 18651}, {4, 20764, 4, 18687}, {4, 20682, 4, 18614}},
1188 /* 20 */ {5080, {6, 22293, 6, 20063}, {5, 22293, 5, 20063}, {4, 20641, 4, 18577}, {4, 20682, 4, 18614}, {4, 20601, 4, 18541}},
1189 /* 21 */ {5180, {6, 21862, 6, 19676}, {5, 21862, 5, 19676}, {4, 20243, 4, 18219}, {4, 20282, 4, 18254}, {4, 20204, 4, 18183}},
1190 /* 22 */ {5200, {6, 21778, 6, 19600}, {5, 21778, 5, 19600}, {4, 20165, 4, 18148}, {4, 20204, 4, 18183}, {4, 20126, 4, 18114}},
1191 /* 23 */ {5220, {6, 21695, 6, 19525}, {5, 21695, 5, 19525}, {4, 20088, 4, 18079}, {4, 20126, 4, 18114}, {4, 20049, 4, 18044}},
1192 /* 24 */ {5240, {6, 21612, 6, 19451}, {5, 21612, 5, 19451}, {4, 20011, 4, 18010}, {4, 20049, 4, 18044}, {4, 19973, 4, 17976}},
1193 /* 25 */ {5260, {6, 21530, 6, 19377}, {5, 21530, 5, 19377}, {4, 19935, 4, 17941}, {4, 19973, 4, 17976}, {4, 19897, 4, 17907}},
1194 /* 26 */ {5280, {6, 21448, 6, 19303}, {5, 21448, 5, 19303}, {4, 19859, 4, 17873}, {4, 19897, 4, 17907}, {4, 19822, 4, 17840}},
1195 /* 27 */ {5300, {6, 21367, 6, 19230}, {5, 21367, 5, 19230}, {4, 19784, 4, 17806}, {4, 19822, 4, 17840}, {4, 19747, 4, 17772}},
1196 /* 28 */ {5320, {6, 21287, 6, 19158}, {5, 21287, 5, 19158}, {4, 19710, 4, 17739}, {4, 19747, 4, 17772}, {4, 19673, 4, 17706}},
1197 /* 29 */ {5500, {6, 20590, 6, 18531}, {5, 20590, 5, 18531}, {4, 19065, 4, 17159}, {4, 19100, 4, 17190}, {4, 19030, 4, 17127}},
1198 /* 30 */ {5520, {6, 20516, 6, 18464}, {5, 20516, 5, 18464}, {4, 18996, 4, 17096}, {4, 19030, 4, 17127}, {4, 18962, 4, 17065}},
1199 /* 31 */ {5540, {6, 20442, 6, 18397}, {5, 20442, 5, 18397}, {4, 18927, 4, 17035}, {4, 18962, 4, 17065}, {4, 18893, 4, 17004}},
1200 /* 32 */ {5560, {6, 20368, 6, 18331}, {5, 20368, 5, 18331}, {4, 18859, 4, 16973}, {4, 18893, 4, 17004}, {4, 18825, 4, 16943}},
1201 /* 33 */ {5580, {6, 20295, 6, 18266}, {5, 20295, 5, 18266}, {4, 18792, 4, 16913}, {4, 18825, 4, 16943}, {4, 18758, 4, 16882}},
1202 /* 34 */ {5600, {6, 20223, 6, 18200}, {5, 20223, 5, 18200}, {4, 18725, 4, 16852}, {4, 18758, 4, 16882}, {4, 18691, 4, 16822}},
1203 /* 35 */ {5620, {6, 20151, 6, 18136}, {5, 20151, 5, 18136}, {4, 18658, 4, 16792}, {4, 18691, 4, 16822}, {4, 18625, 4, 16762}},
1204 /* 36 */ {5640, {6, 20079, 6, 18071}, {5, 20079, 5, 18071}, {4, 18592, 4, 16733}, {4, 18625, 4, 16762}, {4, 18559, 4, 16703}},
1205 /* 37 */ {5660, {6, 20008, 6, 18007}, {5, 20008, 5, 18007}, {4, 18526, 4, 16673}, {4, 18559, 4, 16703}, {4, 18493, 4, 16644}},
1206 /* 38 */ {5680, {6, 19938, 6, 17944}, {5, 19938, 5, 17944}, {4, 18461, 4, 16615}, {4, 18493, 4, 16644}, {4, 18428, 4, 16586}},
1207 /* 39 */ {5700, {6, 19868, 6, 17881}, {5, 19868, 5, 17881}, {4, 18396, 4, 16556}, {4, 18428, 4, 16586}, {4, 18364, 4, 16527}},
1208 /* 40 */ {5745, {6, 19712, 6, 17741}, {5, 19712, 5, 17741}, {4, 18252, 4, 16427}, {4, 18284, 4, 16455}, {4, 18220, 4, 16398}},
1209 /* 41 */ {5765, {6, 19644, 6, 17679}, {5, 19644, 5, 17679}, {4, 18189, 5, 32740}, {4, 18220, 4, 16398}, {4, 18157, 5, 32683}},
1210 /* 42 */ {5785, {6, 19576, 6, 17618}, {5, 19576, 5, 17618}, {4, 18126, 5, 32626}, {4, 18157, 5, 32683}, {4, 18094, 5, 32570}},
1211 /* 43 */ {5805, {6, 19508, 6, 17558}, {5, 19508, 5, 17558}, {4, 18063, 5, 32514}, {4, 18094, 5, 32570}, {4, 18032, 5, 32458}},
1212 /* 44 */ {5825, {6, 19441, 6, 17497}, {5, 19441, 5, 17497}, {4, 18001, 5, 32402}, {4, 18032, 5, 32458}, {4, 17970, 5, 32347}},
1213 /* 45 */ {5170, {6, 21904, 6, 19714}, {5, 21904, 5, 19714}, {4, 20282, 4, 18254}, {4, 20321, 4, 18289}, {4, 20243, 4, 18219}},
1214 /* 46 */ {5190, {6, 21820, 6, 19638}, {5, 21820, 5, 19638}, {4, 20204, 4, 18183}, {4, 20243, 4, 18219}, {4, 20165, 4, 18148}},
1215 /* 47 */ {5210, {6, 21736, 6, 19563}, {5, 21736, 5, 19563}, {4, 20126, 4, 18114}, {4, 20165, 4, 18148}, {4, 20088, 4, 18079}},
1216 /* 48 */ {5230, {6, 21653, 6, 19488}, {5, 21653, 5, 19488}, {4, 20049, 4, 18044}, {4, 20088, 4, 18079}, {4, 20011, 4, 18010}}
1217 };
1218 /* to reduce search time, please modify this define if you add or delete channel in table */
1219 #define First5GChannelIndex 14
1220
1221 void zfGetHwTurnOffdynParam(zdev_t* dev,
1222 u32_t frequency, u8_t bw40, u8_t extOffset,
1223 int* delta_slope_coeff_exp,
1224 int* delta_slope_coeff_man,
1225 int* delta_slope_coeff_exp_shgi,
1226 int* delta_slope_coeff_man_shgi)
1227 {
1228 /* Get param for turnoffdyn */
1229 u16_t i, arraySize;
1230
1231 //zmw_get_wlan_dev(dev);
1232
1233 arraySize = sizeof(zgPhyFreqCoeff)/sizeof(struct zsPhyFreqTable);
1234 if (frequency < 3000)
1235 {
1236 /* 2.4GHz Channel */
1237 for (i = 0; i < First5GChannelIndex; i++)
1238 {
1239 if (frequency == zgPhyFreqCoeff[i].frequency)
1240 break;
1241 }
1242
1243 if (i < First5GChannelIndex)
1244 {
1245 }
1246 else
1247 {
1248 zm_msg1_scan(ZM_LV_0, "Unsupported 2.4G frequency = ", frequency);
1249 return;
1250 }
1251 }
1252 else
1253 {
1254 /* 5GHz Channel */
1255 for (i = First5GChannelIndex; i < arraySize; i++)
1256 {
1257 if (frequency == zgPhyFreqCoeff[i].frequency)
1258 break;
1259 }
1260
1261 if (i < arraySize)
1262 {
1263 }
1264 else
1265 {
1266 zm_msg1_scan(ZM_LV_0, "Unsupported 5G frequency = ", frequency);
1267 return;
1268 }
1269 }
1270
1271 /* FPGA DYNAMIC_HT2040_EN fclk = 10.8 */
1272 /* FPGA STATIC_HT20_ fclk = 21.6 */
1273 /* Real Chip fclk = 40 */
1274 #if ZM_FPGA_PHY == 1
1275 //fclk = 10.8;
1276 *delta_slope_coeff_exp = zgPhyFreqCoeff[i].FpgaDynamicHT.coeff_exp;
1277 *delta_slope_coeff_man = zgPhyFreqCoeff[i].FpgaDynamicHT.coeff_man;
1278 *delta_slope_coeff_exp_shgi = zgPhyFreqCoeff[i].FpgaDynamicHT.coeff_exp_shgi;
1279 *delta_slope_coeff_man_shgi = zgPhyFreqCoeff[i].FpgaDynamicHT.coeff_man_shgi;
1280 #else
1281 //fclk = 40;
1282 if (bw40)
1283 {
1284 /* ht2040 */
1285 if (extOffset == 1) {
1286 *delta_slope_coeff_exp = zgPhyFreqCoeff[i].Chip2040ExtAbove.coeff_exp;
1287 *delta_slope_coeff_man = zgPhyFreqCoeff[i].Chip2040ExtAbove.coeff_man;
1288 *delta_slope_coeff_exp_shgi = zgPhyFreqCoeff[i].Chip2040ExtAbove.coeff_exp_shgi;
1289 *delta_slope_coeff_man_shgi = zgPhyFreqCoeff[i].Chip2040ExtAbove.coeff_man_shgi;
1290 }
1291 else {
1292 *delta_slope_coeff_exp = zgPhyFreqCoeff[i].Chip2040Mhz.coeff_exp;
1293 *delta_slope_coeff_man = zgPhyFreqCoeff[i].Chip2040Mhz.coeff_man;
1294 *delta_slope_coeff_exp_shgi = zgPhyFreqCoeff[i].Chip2040Mhz.coeff_exp_shgi;
1295 *delta_slope_coeff_man_shgi = zgPhyFreqCoeff[i].Chip2040Mhz.coeff_man_shgi;
1296 }
1297 }
1298 else
1299 {
1300 /* static 20 */
1301 *delta_slope_coeff_exp = zgPhyFreqCoeff[i].ChipST20Mhz.coeff_exp;
1302 *delta_slope_coeff_man = zgPhyFreqCoeff[i].ChipST20Mhz.coeff_man;
1303 *delta_slope_coeff_exp_shgi = zgPhyFreqCoeff[i].ChipST20Mhz.coeff_exp_shgi;
1304 *delta_slope_coeff_man_shgi = zgPhyFreqCoeff[i].ChipST20Mhz.coeff_man_shgi;
1305 }
1306 #endif
1307 }
1308
1309 /* Main routin frequency setting function */
1310 /* If 2.4G/5G switch, PHY need resetting BB and RF for band switch */
1311 /* Do the setting switch in zfSendFrequencyCmd() */
1312 void zfHpSetFrequencyEx(zdev_t* dev, u32_t frequency, u8_t bw40,
1313 u8_t extOffset, u8_t initRF)
1314 {
1315 u32_t cmd[9];
1316 u32_t cmdB[3];
1317 u16_t ret;
1318 u8_t old_band;
1319 u8_t new_band;
1320 u32_t checkLoopCount;
1321 u32_t tmpValue;
1322
1323 int delta_slope_coeff_exp;
1324 int delta_slope_coeff_man;
1325 int delta_slope_coeff_exp_shgi;
1326 int delta_slope_coeff_man_shgi;
1327
1328 zmw_get_wlan_dev(dev);
1329 struct zsHpPriv* hpPriv = wd->hpPrivate;
1330
1331 zm_msg1_scan(ZM_LV_1, "Frequency = ", frequency);
1332 zm_msg1_scan(ZM_LV_1, "bw40 = ", bw40);
1333 zm_msg1_scan(ZM_LV_1, "extOffset = ", extOffset);
1334
1335 if ( hpPriv->coldResetNeedFreq )
1336 {
1337 hpPriv->coldResetNeedFreq = 0;
1338 initRF = 2;
1339 zm_debug_msg0("zfHpSetFrequencyEx: Do ColdReset ");
1340 }
1341 if ( hpPriv->isSiteSurvey == 2 )
1342 {
1343 /* wait time for AGC and noise calibration : not in sitesurvey and connected */
1344 checkLoopCount = 2000; /* 2000*100 = 200ms */
1345 }
1346 else
1347 {
1348 /* wait time for AGC and noise calibration : in sitesurvey */
1349 checkLoopCount = 1000; /* 1000*100 = 100ms */
1350 }
1351
1352 hpPriv->latestFrequency = frequency;
1353 hpPriv->latestBw40 = bw40;
1354 hpPriv->latestExtOffset = extOffset;
1355
1356 if ((hpPriv->dot11Mode == ZM_HAL_80211_MODE_IBSS_GENERAL) ||
1357 (hpPriv->dot11Mode == ZM_HAL_80211_MODE_IBSS_WPA2PSK))
1358 {
1359 if ( frequency <= ZM_CH_G_14 )
1360 {
1361 /* workaround for 11g Ad Hoc beacon distribution */
1362 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, 0x7f0007);
1363 //zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_AIFS, 0x1c04901c);
1364 }
1365 }
1366
1367 /* AHB, DAC, ADC clock selection by static20/ht2040 */
1368 zfSelAdcClk(dev, bw40, frequency);
1369
1370 /* clear bb_heavy_clip_enable */
1371 reg_write(0x99e0, 0x200);
1372 zfFlushDelayWrite(dev);
1373
1374 /* Set CTS/RTS rate */
1375 if ( frequency > ZM_CH_G_14 )
1376 {
1377 //zfHpSetRTSCTSRate(dev, 0x10b010b); /* OFDM 6M */
1378 new_band = 1;
1379 }
1380 else
1381 {
1382 //zfHpSetRTSCTSRate(dev, 0x30003); /* CCK 11M */
1383 new_band = 0;
1384 }
1385
1386 if (((struct zsHpPriv*)wd->hpPrivate)->hwFrequency > ZM_CH_G_14)
1387 old_band = 1;
1388 else
1389 old_band = 0;
1390
1391 //Workaround for 2.4GHz only device
1392 if ((hpPriv->OpFlags & 0x1) == 0)
1393 {
1394 if ((((struct zsHpPriv*)wd->hpPrivate)->hwFrequency == ZM_CH_G_1) && (frequency == ZM_CH_G_2))
1395 {
1396 /* Force to do band switching */
1397 old_band = 1;
1398 }
1399 }
1400
1401 /* Notify channel switch to firmware */
1402 /* TX/RX must be stopped by now */
1403 cmd[0] = 0 | (ZM_CMD_FREQ_STRAT << 8);
1404 ret = zfIssueCmd(dev, cmd, 8, ZM_OID_INTERNAL_WRITE, 0);
1405
1406 if ((initRF != 0) || (new_band != old_band)
1407 || (((struct zsHpPriv*)wd->hpPrivate)->hwBw40 != bw40))
1408 {
1409 /* band switch */
1410 zm_msg0_scan(ZM_LV_1, "=====band switch=====");
1411
1412 if (initRF == 2 )
1413 {
1414 //Cold reset BB/ADDA
1415 zfDelayWriteInternalReg(dev, 0x1d4004, 0x800);
1416 zfFlushDelayWrite(dev);
1417 zm_msg0_scan(ZM_LV_1, "Do cold reset BB/ADDA");
1418 }
1419 else
1420 {
1421 //Warm reset BB/ADDA
1422 zfDelayWriteInternalReg(dev, 0x1d4004, 0x400);
1423 zfFlushDelayWrite(dev);
1424 }
1425
1426 /* reset workaround state to default */
1427 hpPriv->rxStrongRSSI = 0;
1428 hpPriv->strongRSSI = 0;
1429
1430 zfDelayWriteInternalReg(dev, 0x1d4004, 0x0);
1431 zfFlushDelayWrite(dev);
1432
1433 zfInitPhy(dev, frequency, bw40);
1434
1435 // zfiCheckRifs(dev);
1436
1437 /* Bank 0 1 2 3 5 6 7 */
1438 zfSetRfRegs(dev, frequency);
1439 /* Bank 4 */
1440 zfSetBank4AndPowerTable(dev, frequency, bw40, extOffset);
1441
1442 cmd[0] = 32 | (ZM_CMD_RF_INIT << 8);
1443 }
1444 else //((new_band == old_band) && !initRF)
1445 {
1446 /* same band */
1447
1448 /* Force disable CR671 bit20 / 7823 */
1449 /* The bug has to do with the polarity of the pdadc offset calibration. There */
1450 /* is an initial calibration that is OK, and there is a continuous */
1451 /* calibration that updates the pddac with the wrong polarity. Fortunately */
1452 /* the second loop can be disabled with a bit called en_pd_dc_offset_thr. */
1453 #if 0
1454 cmdB[0] = 8 | (ZM_CMD_BITAND << 8);;
1455 cmdB[1] = (0xa27c + 0x1bc000);
1456 cmdB[2] = 0xffefffff;
1457 ret = zfIssueCmd(dev, cmdB, 12, ZM_OID_INTERNAL_WRITE, 0);
1458 #endif
1459
1460 /* Bank 4 */
1461 zfSetBank4AndPowerTable(dev, frequency, bw40, extOffset);
1462
1463
1464 cmd[0] = 32 | (ZM_CMD_FREQUENCY << 8);
1465 }
1466
1467 /* Compatibility for new layout UB83 */
1468 /* Setting code at CR1 here move from the func:zfHwHTEnable() in firmware */
1469 if (((struct zsHpPriv*)wd->hpPrivate)->halCapability & ZM_HP_CAP_11N_ONE_TX_STREAM)
1470 {
1471 /* UB83 : one stream */
1472 tmpValue = 0;
1473 }
1474 else
1475 {
1476 /* UB81, UB82 : two stream */
1477 tmpValue = 0x100;
1478 }
1479
1480 if (1) //if (((struct zsHpPriv*)wd->hpPrivate)->hw_HT_ENABLE == 1)
1481 {
1482 if (bw40 == 1)
1483 {
1484 if (extOffset == 1) {
1485 reg_write(0x9804, tmpValue | 0x2d4); //3d4 for real
1486 }
1487 else {
1488 reg_write(0x9804, tmpValue | 0x2c4); //3c4 for real
1489 }
1490 //# Dyn HT2040.Refer to Reg 1.
1491 //#[3]:single length (4us) 1st HT long training symbol; use Walsh spatial spreading for 2 chains 2 streams TX
1492 //#[c]:allow short GI for HT40 packets; enable HT detection.
1493 //#[4]:enable 20/40 MHz channel detection.
1494 }
1495 else
1496 {
1497 reg_write(0x9804, tmpValue | 0x240);
1498 //# Static HT20
1499 //#[3]:single length (4us) 1st HT long training symbol; use Walsh spatial spreading for 2 chains 2 streams TX
1500 //#[4]:Otus don't allow short GI for HT20 packets yet; enable HT detection.
1501 //#[0]:disable 20/40 MHz channel detection.
1502 }
1503 }
1504 else
1505 {
1506 reg_write(0x9804, 0x0);
1507 //# Legacy;# Direct Mapping for each chain.
1508 //#Be modified by Oligo to add dynanic for legacy.
1509 if (bw40 == 1)
1510 {
1511 reg_write(0x9804, 0x4); //# Dyn Legacy .Refer to reg 1.
1512 }
1513 else
1514 {
1515 reg_write(0x9804, 0x0); //# Static Legacy
1516 }
1517 }
1518 zfFlushDelayWrite(dev);
1519 /* end of ub83 compatibility */
1520
1521 /* Set Power, TPC, Gain table... */
1522 zfSetPowerCalTable(dev, frequency, bw40, extOffset);
1523
1524
1525 /* store frequency */
1526 ((struct zsHpPriv*)wd->hpPrivate)->hwFrequency = (u16_t)frequency;
1527 ((struct zsHpPriv*)wd->hpPrivate)->hwBw40 = bw40;
1528 ((struct zsHpPriv*)wd->hpPrivate)->hwExtOffset = extOffset;
1529
1530 zfGetHwTurnOffdynParam(dev,
1531 frequency, bw40, extOffset,
1532 &delta_slope_coeff_exp,
1533 &delta_slope_coeff_man,
1534 &delta_slope_coeff_exp_shgi,
1535 &delta_slope_coeff_man_shgi);
1536
1537 /* related functions */
1538 frequency = frequency*1000;
1539 /* len[36] : type[0x30] : seq[?] */
1540 // cmd[0] = 28 | (ZM_CMD_FREQUENCY << 8);
1541 cmd[1] = frequency;
1542 cmd[2] = bw40;//((struct zsHpPriv*)wd->hpPrivate)->hw_DYNAMIC_HT2040_EN;
1543 cmd[3] = (extOffset<<2)|0x1;//((wd->ExtOffset << 2) | ((struct zsHpPriv*)wd->hpPrivate)->hw_HT_ENABLE);
1544 cmd[4] = delta_slope_coeff_exp;
1545 cmd[5] = delta_slope_coeff_man;
1546 cmd[6] = delta_slope_coeff_exp_shgi;
1547 cmd[7] = delta_slope_coeff_man_shgi;
1548 cmd[8] = checkLoopCount;
1549
1550 ret = zfIssueCmd(dev, cmd, 36, ZM_CMD_SET_FREQUENCY, 0);
1551
1552 // delay temporarily, wait for new PHY and RF
1553 //zfwSleep(dev, 1000);
1554 }
1555
1556
1557 /******************** Key ********************/
1558
1559 u16_t zfHpResetKeyCache(zdev_t* dev)
1560 {
1561 u8_t i;
1562 u32_t key[4] = {0, 0, 0, 0};
1563
1564 zmw_get_wlan_dev(dev);
1565 struct zsHpPriv* hpPriv=wd->hpPrivate;
1566
1567 for(i=0;i<4;i++)
1568 {
1569 zfHpSetDefaultKey(dev, i, ZM_WEP64, key, NULL);
1570 }
1571 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ROLL_CALL_TBL_L, 0x00);
1572 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ROLL_CALL_TBL_H, 0x00);
1573 zfFlushDelayWrite(dev);
1574
1575 hpPriv->camRollCallTable = (u64_t) 0;
1576
1577 return 0;
1578 }
1579
1580
1581 /************************************************************************/
1582 /* */
1583 /* FUNCTION DESCRIPTION zfSetKey */
1584 /* Set key. */
1585 /* */
1586 /* INPUTS */
1587 /* dev : device pointer */
1588 /* */
1589 /* OUTPUTS */
1590 /* 0 : success */
1591 /* other : fail */
1592 /* */
1593 /* AUTHOR */
1594 /* Stephen Chen ZyDAS Technology Corporation 2006.1 */
1595 /* */
1596 /************************************************************************/
1597 /* ! please use zfCoreSetKey() in 80211Core for SetKey */
1598 u32_t zfHpSetKey(zdev_t* dev, u8_t user, u8_t keyId, u8_t type,
1599 u16_t* mac, u32_t* key)
1600 {
1601 u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
1602 u16_t ret;
1603 u16_t i;
1604
1605 zmw_get_wlan_dev(dev);
1606 struct zsHpPriv* hpPriv=wd->hpPrivate;
1607
1608 #if 0 /* remove to zfCoreSetKey() */
1609 zmw_declare_for_critical_section();
1610
1611 zmw_enter_critical_section(dev);
1612 wd->sta.flagKeyChanging++;
1613 zm_debug_msg1(" zfHpSetKey++++ ", wd->sta.flagKeyChanging);
1614 zmw_leave_critical_section(dev);
1615 #endif
1616
1617 cmd[0] = 0x0000281C;
1618 cmd[1] = ((u32_t)keyId<<16) + (u32_t)user;
1619 cmd[2] = ((u32_t)mac[0]<<16) + (u32_t)type;
1620 cmd[3] = ((u32_t)mac[2]<<16) + ((u32_t)mac[1]);
1621
1622 for (i=0; i<4; i++)
1623 {
1624 cmd[4+i] = key[i];
1625 }
1626
1627 if (user < 64)
1628 {
1629 hpPriv->camRollCallTable |= ((u64_t) 1) << user;
1630 }
1631
1632 //ret = zfIssueCmd(dev, cmd, 32, ZM_OID_INTERNAL_WRITE, NULL);
1633 ret = zfIssueCmd(dev, cmd, 32, ZM_CMD_SET_KEY, NULL);
1634 return ret;
1635 }
1636
1637
1638 u32_t zfHpSetApPairwiseKey(zdev_t* dev, u16_t* staMacAddr, u8_t type,
1639 u32_t* key, u32_t* micKey, u16_t staAid)
1640 {
1641 if ((staAid!=0) && (staAid<64))
1642 {
1643 zfHpSetKey(dev, (staAid-1), 0, type, staMacAddr, key);
1644 if ((type == ZM_TKIP)
1645 #ifdef ZM_ENABLE_CENC
1646 || (type == ZM_CENC)
1647 #endif //ZM_ENABLE_CENC
1648 )
1649 zfHpSetKey(dev, (staAid-1), 1, type, staMacAddr, micKey);
1650 return 0;
1651 }
1652 return 1;
1653 }
1654
1655 u32_t zfHpSetApGroupKey(zdev_t* dev, u16_t* apMacAddr, u8_t type,
1656 u32_t* key, u32_t* micKey, u16_t vapId)
1657 {
1658 zfHpSetKey(dev, ZM_USER_KEY_DEFAULT - 1 - vapId, 0, type, apMacAddr, key); // 6D18 modify from 0 to 1 ??
1659 if ((type == ZM_TKIP)
1660 #ifdef ZM_ENABLE_CENC
1661 || (type == ZM_CENC)
1662 #endif //ZM_ENABLE_CENC
1663 )
1664 zfHpSetKey(dev, ZM_USER_KEY_DEFAULT - 1 - vapId, 1, type, apMacAddr, micKey);
1665 return 0;
1666 }
1667
1668 u32_t zfHpSetDefaultKey(zdev_t* dev, u8_t keyId, u8_t type, u32_t* key, u32_t* micKey)
1669 {
1670 u16_t macAddr[3] = {0, 0, 0};
1671
1672 #ifdef ZM_ENABLE_IBSS_WPA2PSK
1673 zmw_get_wlan_dev(dev);
1674 struct zsHpPriv* hpPriv = wd->hpPrivate;
1675
1676 if ( hpPriv->dot11Mode == ZM_HAL_80211_MODE_IBSS_WPA2PSK )
1677 { /* If not wpa2psk , use traditional */
1678 /* Because the bug of chip , defaultkey should follow the key map rule in register 700 */
1679 if ( keyId == 0 )
1680 zfHpSetKey(dev, ZM_USER_KEY_DEFAULT+keyId, 0, type, macAddr, key);
1681 else
1682 zfHpSetKey(dev, ZM_USER_KEY_DEFAULT+keyId, 1, type, macAddr, key);
1683 }
1684 else
1685 zfHpSetKey(dev, ZM_USER_KEY_DEFAULT+keyId, 0, type, macAddr, key);
1686 #else
1687 zfHpSetKey(dev, ZM_USER_KEY_DEFAULT+keyId, 0, type, macAddr, key);
1688 #endif
1689 if ((type == ZM_TKIP)
1690
1691 #ifdef ZM_ENABLE_CENC
1692 || (type == ZM_CENC)
1693 #endif //ZM_ENABLE_CENC
1694 )
1695 {
1696 zfHpSetKey(dev, ZM_USER_KEY_DEFAULT+keyId, 1, type, macAddr, micKey);
1697 }
1698
1699 return 0;
1700 }
1701
1702 u32_t zfHpSetPerUserKey(zdev_t* dev, u8_t user, u8_t keyId, u8_t* mac, u8_t type, u32_t* key, u32_t* micKey)
1703 {
1704 #ifdef ZM_ENABLE_IBSS_WPA2PSK
1705 zmw_get_wlan_dev(dev);
1706 struct zsHpPriv* hpPriv = wd->hpPrivate;
1707
1708 if ( hpPriv->dot11Mode == ZM_HAL_80211_MODE_IBSS_WPA2PSK )
1709 { /* If not wpa2psk , use traditional */
1710 if(keyId)
1711 { /* Set Group Key */
1712 zfHpSetKey(dev, user, 1, type, (u16_t *)mac, key);
1713 }
1714 else if(keyId == 0)
1715 { /* Set Pairwise Key */
1716 zfHpSetKey(dev, user, 0, type, (u16_t *)mac, key);
1717 }
1718 }
1719 else
1720 {
1721 zfHpSetKey(dev, user, keyId, type, (u16_t *)mac, key);
1722 }
1723 #else
1724 zfHpSetKey(dev, user, keyId, type, (u16_t *)mac, key);
1725 #endif
1726
1727 if ((type == ZM_TKIP)
1728 #ifdef ZM_ENABLE_CENC
1729 || (type == ZM_CENC)
1730 #endif //ZM_ENABLE_CENC
1731 )
1732 {
1733 zfHpSetKey(dev, user, keyId + 1, type, (u16_t *)mac, micKey);
1734 }
1735 return 0;
1736 }
1737
1738 /************************************************************************/
1739 /* */
1740 /* FUNCTION DESCRIPTION zfHpRemoveKey */
1741 /* Remove key. */
1742 /* */
1743 /* INPUTS */
1744 /* dev : device pointer */
1745 /* */
1746 /* OUTPUTS */
1747 /* 0 : success */
1748 /* other : fail */
1749 /* */
1750 /* AUTHOR */
1751 /* Yuan-Gu Wei ZyDAS Technology Corporation 2006.6 */
1752 /* */
1753 /************************************************************************/
1754 u16_t zfHpRemoveKey(zdev_t* dev, u16_t user)
1755 {
1756 u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
1757 u16_t ret = 0;
1758
1759 cmd[0] = 0x00002904;
1760 cmd[1] = (u32_t)user;
1761
1762 ret = zfIssueCmd(dev, cmd, 8, ZM_OID_INTERNAL_WRITE, NULL);
1763 return ret;
1764 }
1765
1766
1767
1768 /******************** DMA ********************/
1769 u16_t zfHpStartRecv(zdev_t* dev)
1770 {
1771 zfDelayWriteInternalReg(dev, 0x1c3d30, 0x100);
1772 zfFlushDelayWrite(dev);
1773
1774 return 0;
1775 }
1776
1777 u16_t zfHpStopRecv(zdev_t* dev)
1778 {
1779 return 0;
1780 }
1781
1782
1783 /******************** MAC ********************/
1784 void zfInitMac(zdev_t* dev)
1785 {
1786 /* ACK extension register */
1787 // jhlee temp : change value 0x2c -> 0x40
1788 // honda resolve short preamble problem : 0x40 -> 0x75
1789 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ACK_EXTENSION, 0x40); // 0x28 -> 0x2c 6522:yflee
1790
1791 /* TxQ0/1/2/3 Retry MAX=2 => transmit 3 times and degrade rate for retry */
1792 /* PB42 AP crash issue: */
1793 /* Workaround the crash issue by CTS/RTS, set retry max to zero for */
1794 /* workaround tx underrun which enable CTS/RTS */
1795 zfDelayWriteInternalReg(dev, ZM_MAC_REG_RETRY_MAX, 0); // 0x11111 => 0
1796
1797 /* use hardware MIC check */
1798 zfDelayWriteInternalReg(dev, ZM_MAC_REG_SNIFFER, 0x2000000);
1799
1800 /* Set Rx threshold to 1600 */
1801 #if ZM_LARGEPAYLOAD_TEST == 1
1802 zfDelayWriteInternalReg(dev, ZM_MAC_REG_RX_THRESHOLD, 0xc4000);
1803 #else
1804 #ifndef ZM_DISABLE_AMSDU8K_SUPPORT
1805 /* The maximum A-MSDU length is 3839/7935 */
1806 zfDelayWriteInternalReg(dev, ZM_MAC_REG_RX_THRESHOLD, 0xc1f80);
1807 #else
1808 zfDelayWriteInternalReg(dev, ZM_MAC_REG_RX_THRESHOLD, 0xc0f80);
1809 #endif
1810 #endif
1811
1812 //zfDelayWriteInternalReg(dev, ZM_MAC_REG_DYNAMIC_SIFS_ACK, 0x10A);
1813 zfDelayWriteInternalReg(dev, ZM_MAC_REG_RX_PE_DELAY, 0x70);
1814 zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0xa144000);
1815 zfDelayWriteInternalReg(dev, ZM_MAC_REG_SLOT_TIME, 9<<10);
1816
1817 /* CF-END mode */
1818 zfDelayWriteInternalReg(dev, 0x1c3b2c, 0x19000000);
1819
1820 //NAV protects ACK only (in TXOP)
1821 zfDelayWriteInternalReg(dev, 0x1c3b38, 0x201);
1822
1823
1824 /* Set Beacon PHY CTRL's TPC to 0x7, TA1=1 */
1825 /* OTUS set AM to 0x1 */
1826 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_HT1, 0x8000170);
1827
1828 /* TODO : wep backoff protection 0x63c */
1829 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BACKOFF_PROTECT, 0x105);
1830
1831 /* AGG test code*/
1832 /* Aggregation MAX number and timeout */
1833 zfDelayWriteInternalReg(dev, 0x1c3b9c, 0x10000a);
1834 /* Filter any control frames, BAR is bit 24 */
1835 zfDelayWriteInternalReg(dev, 0x1c368c, 0x0500ffff);
1836 /* Enable deaggregator */
1837 zfDelayWriteInternalReg(dev, 0x1c3c40, 0x1);
1838
1839 /* Basic rate */
1840 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BASIC_RATE, 0x150f);
1841 zfDelayWriteInternalReg(dev, ZM_MAC_REG_MANDATORY_RATE, 0x150f);
1842 zfDelayWriteInternalReg(dev, ZM_MAC_REG_RTS_CTS_RATE, 0x10b01bb);
1843
1844 /* MIMO resposne control */
1845 zfDelayWriteInternalReg(dev, 0x1c3694, 0x4003C1E);/* bit 26~28 otus-AM */
1846
1847 /* Enable LED0 and LED1 */
1848 zfDelayWriteInternalReg(dev, 0x1d0100, 0x3);
1849 zfDelayWriteInternalReg(dev, 0x1d0104, 0x3);
1850
1851 /* switch MAC to OTUS interface */
1852 zfDelayWriteInternalReg(dev, 0x1c3600, 0x3);
1853
1854 /* RXMAC A-MPDU length threshold */
1855 zfDelayWriteInternalReg(dev, 0x1c3c50, 0xffff);
1856
1857 /* Phy register read timeout */
1858 zfDelayWriteInternalReg(dev, 0x1c3680, 0xf00008);
1859
1860 /* Disable Rx TimeOut : workaround for BB.
1861 * OTUS would interrupt the rx frame that sent by OWL TxUnderRun
1862 * because OTUS rx timeout behavior, then OTUS would not ack the BA for
1863 * this AMPDU from OWL.
1864 * Fix by Perry Hwang. 2007/05/10.
1865 * 0x1c362c : Rx timeout value : bit 27~16
1866 */
1867 zfDelayWriteInternalReg(dev, 0x1c362c, 0x0);
1868
1869 //Set USB Rx stream mode MAX packet number to 2
1870 // Max packet number = *0x1e1110 + 1
1871 zfDelayWriteInternalReg(dev, 0x1e1110, 0x4);
1872 //Set USB Rx stream mode timeout to 10us
1873 zfDelayWriteInternalReg(dev, 0x1e1114, 0x80);
1874
1875 //Set CPU clock frequency to 88/80MHz
1876 zfDelayWriteInternalReg(dev, 0x1D4008, 0x73);
1877
1878 //Set WLAN DMA interrupt mode : generate int per packet
1879 zfDelayWriteInternalReg(dev, 0x1c3d7c, 0x110011);
1880
1881 /* 7807 */
1882 /* enable func : Reset FIFO1 and FIFO2 when queue-gnt is low */
1883 /* 0x1c3bb0 Bit2 */
1884 /* Disable SwReset in firmware for TxHang, enable reset FIFO func. */
1885 zfDelayWriteInternalReg(dev, 0x1c3bb0, 0x4);
1886
1887 /* Disables the CF_END frame */
1888 zfDelayWriteInternalReg(dev, ZM_MAC_REG_TXOP_NOT_ENOUGH_INDICATION, 0x141E0F48);
1889
1890 /* Disable the SW Decrypt*/
1891 zfDelayWriteInternalReg(dev, 0x1c3678, 0x70);
1892 zfFlushDelayWrite(dev);
1893 //---------------------
1894
1895 /* Set TxQs CWMIN, CWMAX, AIFS and TXO to WME STA default. */
1896 zfUpdateDefaultQosParameter(dev, 0);
1897
1898 //zfSelAdcClk(dev, 0);
1899
1900 return;
1901 }
1902
1903
1904 u16_t zfHpSetSnifferMode(zdev_t* dev, u16_t on)
1905 {
1906 if (on != 0)
1907 {
1908 zfDelayWriteInternalReg(dev, ZM_MAC_REG_SNIFFER, 0x2000001);
1909 }
1910 else
1911 {
1912 zfDelayWriteInternalReg(dev, ZM_MAC_REG_SNIFFER, 0x2000000);
1913 }
1914 zfFlushDelayWrite(dev);
1915 return 0;
1916 }
1917
1918
1919 u16_t zfHpSetApStaMode(zdev_t* dev, u8_t mode)
1920 {
1921 zmw_get_wlan_dev(dev);
1922
1923 struct zsHpPriv* hpPriv = wd->hpPrivate;
1924 hpPriv->dot11Mode = mode;
1925
1926 switch(mode)
1927 {
1928 case ZM_HAL_80211_MODE_AP:
1929 zfDelayWriteInternalReg(dev, 0x1c3700, 0x0f0000a1);
1930 zfDelayWriteInternalReg(dev, 0x1c3c40, 0x1);
1931 break;
1932
1933 case ZM_HAL_80211_MODE_STA:
1934 zfDelayWriteInternalReg(dev, 0x1c3700, 0x0f000002);
1935 zfDelayWriteInternalReg(dev, 0x1c3c40, 0x1);
1936 break;
1937
1938 case ZM_HAL_80211_MODE_IBSS_GENERAL:
1939 zfDelayWriteInternalReg(dev, 0x1c3700, 0x0f000000);
1940 zfDelayWriteInternalReg(dev, 0x1c3c40, 0x1);
1941 break;
1942
1943 case ZM_HAL_80211_MODE_IBSS_WPA2PSK:
1944 zfDelayWriteInternalReg(dev, 0x1c3700, 0x0f0000e0);
1945 zfDelayWriteInternalReg(dev, 0x1c3c40, 0x41); // for multiple ( > 2 ) stations IBSS network
1946 break;
1947
1948 default:
1949 goto skip;
1950 }
1951
1952 zfFlushDelayWrite(dev);
1953
1954 skip:
1955 return 0;
1956 }
1957
1958
1959 u16_t zfHpSetBssid(zdev_t* dev, u8_t* bssidSrc)
1960 {
1961 u32_t address;
1962 u16_t *bssid = (u16_t *)bssidSrc;
1963
1964 address = bssid[0] + (((u32_t)bssid[1]) << 16);
1965 zfDelayWriteInternalReg(dev, 0x1c3618, address);
1966
1967 address = (u32_t)bssid[2];
1968 zfDelayWriteInternalReg(dev, 0x1c361C, address);
1969 zfFlushDelayWrite(dev);
1970 return 0;
1971 }
1972
1973
1974 /************************************************************************/
1975 /* */
1976 /* FUNCTION DESCRIPTION zfHpUpdateQosParameter */
1977 /* Update TxQs CWMIN, CWMAX, AIFS and TXOP. */
1978 /* */
1979 /* INPUTS */
1980 /* dev : device pointer */
1981 /* cwminTbl : CWMIN parameter for TxQs */
1982 /* cwmaxTbl : CWMAX parameter for TxQs */
1983 /* aifsTbl: AIFS parameter for TxQs */
1984 /* txopTbl : TXOP parameter for TxQs */
1985 /* */
1986 /* OUTPUTS */
1987 /* none */
1988 /* */
1989 /* AUTHOR */
1990 /* Stephen ZyDAS Technology Corporation 2006.6 */
1991 /* */
1992 /************************************************************************/
1993 u8_t zfHpUpdateQosParameter(zdev_t* dev, u16_t* cwminTbl, u16_t* cwmaxTbl,
1994 u16_t* aifsTbl, u16_t* txopTbl)
1995 {
1996 zmw_get_wlan_dev(dev);
1997 struct zsHpPriv* hpPriv = wd->hpPrivate;
1998
1999 zm_msg0_mm(ZM_LV_0, "zfHalUpdateQosParameter()");
2000
2001 /* Note : Do not change cwmin for Q0 in Ad Hoc mode */
2002 /* otherwise driver will fail in Wifi beacon distribution */
2003 if (hpPriv->dot11Mode == ZM_HAL_80211_MODE_STA)
2004 {
2005 #if 0 //Restore CWmin to improve down link throughput
2006 //cheating in BE traffic
2007 if (wd->sta.EnableHT == 1)
2008 {
2009 //cheating in BE traffic
2010 cwminTbl[0] = 7;//15;
2011 }
2012 #endif
2013 cwmaxTbl[0] = 127;//1023;
2014 aifsTbl[0] = 2*9+10;//3 * 9 + 10;
2015 }
2016
2017 /* CWMIN and CWMAX */
2018 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, cwminTbl[0]
2019 + ((u32_t)cwmaxTbl[0]<<16));
2020 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_CW, cwminTbl[1]
2021 + ((u32_t)cwmaxTbl[1]<<16));
2022 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC2_CW, cwminTbl[2]
2023 + ((u32_t)cwmaxTbl[2]<<16));
2024 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC3_CW, cwminTbl[3]
2025 + ((u32_t)cwmaxTbl[3]<<16));
2026 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC4_CW, cwminTbl[4]
2027 + ((u32_t)cwmaxTbl[4]<<16));
2028
2029 /* AIFS */
2030 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_AIFS, aifsTbl[0]
2031 +((u32_t)aifsTbl[0]<<12)+((u32_t)aifsTbl[0]<<24));
2032 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC3_AC2_AIFS, (aifsTbl[0]>>8)
2033 +((u32_t)aifsTbl[0]<<4)+((u32_t)aifsTbl[0]<<16));
2034
2035 /* TXOP */
2036 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_TXOP, txopTbl[0]
2037 + ((u32_t)txopTbl[1]<<16));
2038 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC3_AC2_TXOP, txopTbl[2]
2039 + ((u32_t)txopTbl[3]<<16));
2040
2041 zfFlushDelayWrite(dev);
2042
2043 hpPriv->txop[0] = txopTbl[0];
2044 hpPriv->txop[1] = txopTbl[1];
2045 hpPriv->txop[2] = txopTbl[2];
2046 hpPriv->txop[3] = txopTbl[3];
2047 hpPriv->cwmin[0] = cwminTbl[0];
2048 hpPriv->cwmax[0] = cwmaxTbl[0];
2049 hpPriv->cwmin[1] = cwminTbl[1];
2050 hpPriv->cwmax[1] = cwmaxTbl[1];
2051
2052 return 0;
2053 }
2054
2055
2056 void zfHpSetAtimWindow(zdev_t* dev, u16_t atimWin)
2057 {
2058 zm_msg1_mm(ZM_LV_0, "Set ATIM window to ", atimWin);
2059 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ATIM_WINDOW, atimWin);
2060 zfFlushDelayWrite(dev);
2061 }
2062
2063
2064 void zfHpSetBasicRateSet(zdev_t* dev, u16_t bRateBasic, u16_t gRateBasic)
2065 {
2066 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BASIC_RATE, bRateBasic
2067 | ((u16_t)gRateBasic<<8));
2068 zfFlushDelayWrite(dev);
2069 }
2070
2071
2072 /* HT40 send by OFDM 6M */
2073 /* otherwise use reg 0x638 */
2074 void zfHpSetRTSCTSRate(zdev_t* dev, u32_t rate)
2075 {
2076 zfDelayWriteInternalReg(dev, ZM_MAC_REG_RTS_CTS_RATE, rate);
2077 zfFlushDelayWrite(dev);
2078 }
2079
2080 void zfHpSetMacAddress(zdev_t* dev, u16_t* macAddr, u16_t macAddrId)
2081 {
2082 if (macAddrId == 0)
2083 {
2084 zfDelayWriteInternalReg(dev, ZM_MAC_REG_MAC_ADDR_L,
2085 (((u32_t)macAddr[1])<<16) | macAddr[0]);
2086 zfDelayWriteInternalReg(dev, ZM_MAC_REG_MAC_ADDR_H, macAddr[2]);
2087 }
2088 else if (macAddrId <= 7)
2089 {
2090 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ACK_TABLE+((macAddrId-1)*8),
2091 macAddr[0] + ((u32_t)macAddr[1]<<16));
2092 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ACK_TABLE+((macAddrId-1)*8)+4,
2093 macAddr[2]);
2094 }
2095 zfFlushDelayWrite(dev);
2096 }
2097
2098 void zfHpSetMulticastList(zdev_t* dev, u8_t size, u8_t* pList, u8_t bAllMulticast)
2099 {
2100 struct zsMulticastAddr* pMacList = (struct zsMulticastAddr*) pList;
2101 u8_t i;
2102 u32_t value;
2103 u32_t swRegMulHashValueH, swRegMulHashValueL;
2104
2105 swRegMulHashValueH = 0x80000000;
2106 swRegMulHashValueL = 0;
2107
2108 if ( bAllMulticast )
2109 {
2110 swRegMulHashValueH = swRegMulHashValueL = ~0;
2111 }
2112 else
2113 {
2114 for(i=0; i<size; i++)
2115 {
2116 value = pMacList[i].addr[5] >> 2;
2117
2118 if ( value < 32 )
2119 {
2120 swRegMulHashValueL |= (1 << value);
2121 }
2122 else
2123 {
2124 swRegMulHashValueH |= (1 << (value-32));
2125 }
2126 }
2127 }
2128
2129 zfDelayWriteInternalReg(dev, ZM_MAC_REG_GROUP_HASH_TBL_L,
2130 swRegMulHashValueL);
2131 zfDelayWriteInternalReg(dev, ZM_MAC_REG_GROUP_HASH_TBL_H,
2132 swRegMulHashValueH);
2133 zfFlushDelayWrite(dev);
2134 return;
2135 }
2136
2137 /******************** Beacon ********************/
2138 void zfHpEnableBeacon(zdev_t* dev, u16_t mode, u16_t bcnInterval, u16_t dtim, u8_t enableAtim)
2139 {
2140 u32_t value;
2141
2142 zmw_get_wlan_dev(dev);
2143
2144 /* Beacon Ready */
2145 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_CTRL, 0);
2146 /* Beacon DMA buffer address */
2147 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_ADDR, ZM_BEACON_BUFFER_ADDRESS);
2148
2149 value = bcnInterval;
2150
2151 value |= (((u32_t) dtim) << 16);
2152
2153 if (mode == ZM_MODE_AP)
2154 {
2155
2156 value |= 0x1000000;
2157 }
2158 else if (mode == ZM_MODE_IBSS)
2159 {
2160 value |= 0x2000000;
2161
2162 if ( enableAtim )
2163 {
2164 value |= 0x4000000;
2165 }
2166 ((struct zsHpPriv*)wd->hpPrivate)->ibssBcnEnabled = 1;
2167 ((struct zsHpPriv*)wd->hpPrivate)->ibssBcnInterval = value;
2168 }
2169 zfDelayWriteInternalReg(dev, ZM_MAC_REG_PRETBTT, (bcnInterval-6)<<16);
2170
2171 /* Beacon period and beacon enable */
2172 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, value);
2173 zfFlushDelayWrite(dev);
2174 }
2175
2176 void zfHpDisableBeacon(zdev_t* dev)
2177 {
2178 zmw_get_wlan_dev(dev);
2179
2180 ((struct zsHpPriv*)wd->hpPrivate)->ibssBcnEnabled = 0;
2181
2182 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, 0);
2183 zfFlushDelayWrite(dev);
2184 }
2185
2186 void zfHpLedCtrl(zdev_t* dev, u16_t ledId, u8_t mode)
2187 {
2188 u16_t state;
2189 zmw_get_wlan_dev(dev);
2190
2191 //zm_debug_msg1("LED ID=", ledId);
2192 //zm_debug_msg1("LED mode=", mode);
2193 if (ledId < 2)
2194 {
2195 if (((struct zsHpPriv*)wd->hpPrivate)->ledMode[ledId] != mode)
2196 {
2197 ((struct zsHpPriv*)wd->hpPrivate)->ledMode[ledId] = mode;
2198
2199 state = ((struct zsHpPriv*)wd->hpPrivate)->ledMode[0]
2200 | (((struct zsHpPriv*)wd->hpPrivate)->ledMode[1]<<1);
2201 zfDelayWriteInternalReg(dev, 0x1d0104, state);
2202 zfFlushDelayWrite(dev);
2203 //zm_debug_msg0("Update LED");
2204 }
2205 }
2206 }
2207
2208 /************************************************************************/
2209 /* */
2210 /* FUNCTION DESCRIPTION zfHpResetTxRx */
2211 /* Reset Tx and Rx Desc. */
2212 /* */
2213 /* INPUTS */
2214 /* dev : device pointer */
2215 /* */
2216 /* OUTPUTS */
2217 /* 0 : success */
2218 /* other : fail */
2219 /* */
2220 /* AUTHOR */
2221 /* Chao-Wen Yang ZyDAS Technology Corporation 2007.3 */
2222 /* */
2223 /************************************************************************/
2224 u16_t zfHpUsbReset(zdev_t* dev)
2225 {
2226 u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
2227 u16_t ret = 0;
2228
2229 //zm_debug_msg0("CWY - Reset Tx and Rx");
2230
2231 cmd[0] = 0 | (ZM_CMD_RESET << 8);
2232
2233 ret = zfIssueCmd(dev, cmd, 4, ZM_OID_INTERNAL_WRITE, NULL);
2234 return ret;
2235 }
2236
2237 u16_t zfHpDKReset(zdev_t* dev, u8_t flag)
2238 {
2239 u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
2240 u16_t ret = 0;
2241
2242 //zm_debug_msg0("CWY - Reset Tx and Rx");
2243
2244 cmd[0] = 4 | (ZM_CMD_DKRESET << 8);
2245 cmd[1] = flag;
2246
2247 ret = zfIssueCmd(dev, cmd, 8, ZM_OID_INTERNAL_WRITE, NULL);
2248 return ret;
2249 }
2250
2251 u32_t zfHpCwmUpdate(zdev_t* dev)
2252 {
2253 //u32_t cmd[3];
2254 //u16_t ret;
2255 //
2256 //cmd[0] = 0x00000008;
2257 //cmd[1] = 0x1c36e8;
2258 //cmd[2] = 0x1c36ec;
2259 //
2260 //ret = zfIssueCmd(dev, cmd, 12, ZM_CWM_READ, 0);
2261 //return ret;
2262 zmw_get_wlan_dev(dev);
2263
2264 struct zsHpPriv* hpPriv=wd->hpPrivate;
2265
2266 zfCoreCwmBusy(dev, zfCwmIsExtChanBusy(hpPriv->ctlBusy, hpPriv->extBusy));
2267
2268 hpPriv->ctlBusy = 0;
2269 hpPriv->extBusy = 0;
2270
2271 return 0;
2272 }
2273
2274 u32_t zfHpAniUpdate(zdev_t* dev)
2275 {
2276 u32_t cmd[5];
2277 u16_t ret;
2278
2279 cmd[0] = 0x00000010;
2280 cmd[1] = 0x1c36e8;
2281 cmd[2] = 0x1c36ec;
2282 cmd[3] = 0x1c3cb4;
2283 cmd[4] = 0x1c3cb8;
2284
2285 ret = zfIssueCmd(dev, cmd, 20, ZM_ANI_READ, 0);
2286 return ret;
2287 }
2288
2289 /*
2290 * Update Beacon RSSI in ANI
2291 */
2292 u32_t zfHpAniUpdateRssi(zdev_t* dev, u8_t rssi)
2293 {
2294 zmw_get_wlan_dev(dev);
2295
2296 struct zsHpPriv* hpPriv=wd->hpPrivate;
2297
2298 hpPriv->stats.ast_nodestats.ns_avgbrssi = rssi;
2299
2300 return 0;
2301 }
2302
2303 #define ZM_SEEPROM_MAC_ADDRESS_OFFSET (0x1400 + (0x106<<1))
2304 #define ZM_SEEPROM_REGDOMAIN_OFFSET (0x1400 + (0x104<<1))
2305 #define ZM_SEEPROM_VERISON_OFFSET (0x1400 + (0x102<<1))
2306 #define ZM_SEEPROM_HARDWARE_TYPE_OFFSET (0x1374)
2307 #define ZM_SEEPROM_HW_HEAVY_CLIP (0x161c)
2308
2309 u32_t zfHpGetMacAddress(zdev_t* dev)
2310 {
2311 u32_t cmd[7];
2312 u16_t ret;
2313
2314 cmd[0] = 0x00000000 | 24;
2315 cmd[1] = ZM_SEEPROM_MAC_ADDRESS_OFFSET;
2316 cmd[2] = ZM_SEEPROM_MAC_ADDRESS_OFFSET+4;
2317 cmd[3] = ZM_SEEPROM_REGDOMAIN_OFFSET;
2318 cmd[4] = ZM_SEEPROM_VERISON_OFFSET;
2319 cmd[5] = ZM_SEEPROM_HARDWARE_TYPE_OFFSET;
2320 cmd[6] = ZM_SEEPROM_HW_HEAVY_CLIP;
2321
2322 ret = zfIssueCmd(dev, cmd, 28, ZM_MAC_READ, 0);
2323 return ret;
2324 }
2325
2326 u32_t zfHpGetTransmitPower(zdev_t* dev)
2327 {
2328 zmw_get_wlan_dev(dev);
2329
2330 struct zsHpPriv* hpPriv = wd->hpPrivate;
2331 u16_t tpc = 0;
2332
2333 if (hpPriv->hwFrequency < 3000) {
2334 tpc = hpPriv->tPow2x2g[0] & 0x3f;
2335 wd->maxTxPower2 &= 0x3f;
2336 tpc = (tpc > wd->maxTxPower2)? wd->maxTxPower2 : tpc;
2337 } else {
2338 tpc = hpPriv->tPow2x5g[0] & 0x3f;
2339 wd->maxTxPower5 &= 0x3f;
2340 tpc = (tpc > wd->maxTxPower5)? wd->maxTxPower5 : tpc;
2341 }
2342
2343 return tpc;
2344 }
2345
2346 u8_t zfHpGetMinTxPower(zdev_t* dev)
2347 {
2348 zmw_get_wlan_dev(dev);
2349
2350 struct zsHpPriv* hpPriv = wd->hpPrivate;
2351 u8_t tpc = 0;
2352
2353 if (hpPriv->hwFrequency < 3000)
2354 {
2355 if(wd->BandWidth40)
2356 {
2357 //40M
2358 tpc = (hpPriv->tPow2x2gHt40[7]&0x3f);
2359 }
2360 else
2361 {
2362 //20M
2363 tpc = (hpPriv->tPow2x2gHt20[7]&0x3f);
2364 }
2365 }
2366 else
2367 {
2368 if(wd->BandWidth40)
2369 {
2370 //40M
2371 tpc = (hpPriv->tPow2x5gHt40[7]&0x3f);
2372 }
2373 else
2374 {
2375 //20M
2376 tpc = (hpPriv->tPow2x5gHt20[7]&0x3f);
2377 }
2378 }
2379
2380 return tpc;
2381 }
2382
2383 u8_t zfHpGetMaxTxPower(zdev_t* dev)
2384 {
2385 zmw_get_wlan_dev(dev);
2386
2387 struct zsHpPriv* hpPriv = wd->hpPrivate;
2388 u8_t tpc = 0;
2389
2390 if (hpPriv->hwFrequency < 3000)
2391 {
2392 tpc = (hpPriv->tPow2xCck[0]&0x3f);
2393 }
2394 else
2395 {
2396 tpc =(hpPriv->tPow2x5g[0]&0x3f);
2397 }
2398
2399 return tpc;
2400 }
2401
2402 u32_t zfHpLoadEEPROMFromFW(zdev_t* dev)
2403 {
2404 u32_t cmd[16];
2405 u32_t ret=0, i, j;
2406 zmw_get_wlan_dev(dev);
2407
2408 i = ((struct zsHpPriv*)wd->hpPrivate)->eepromImageRdReq;
2409
2410 cmd[0] = ZM_HAL_MAX_EEPROM_PRQ*4;
2411
2412 for (j=0; j<ZM_HAL_MAX_EEPROM_PRQ; j++)
2413 {
2414 cmd[j+1] = 0x1000 + (((i*ZM_HAL_MAX_EEPROM_PRQ) + j)*4);
2415 }
2416
2417 ret = zfIssueCmd(dev, cmd, (ZM_HAL_MAX_EEPROM_PRQ+1)*4, ZM_EEPROM_READ, 0);
2418
2419 return ret;
2420 }
2421
2422 void zfHpHeartBeat(zdev_t* dev)
2423 {
2424 zmw_get_wlan_dev(dev);
2425 struct zsHpPriv* hpPriv=wd->hpPrivate;
2426 u8_t polluted = 0;
2427 u8_t ackTpc;
2428
2429 /* Workaround : Make OTUS fire more beacon in ad hoc mode in 2.4GHz */
2430 if (hpPriv->ibssBcnEnabled != 0)
2431 {
2432 if (hpPriv->hwFrequency <= ZM_CH_G_14)
2433 {
2434 if ((wd->tick % 10) == 0)
2435 {
2436 if ((wd->tick % 40) == 0)
2437 {
2438 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, hpPriv->ibssBcnInterval-1);
2439 polluted = 1;
2440 }
2441 else
2442 {
2443 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, hpPriv->ibssBcnInterval);
2444 polluted = 1;
2445 }
2446 }
2447 }
2448 }
2449
2450 if ((wd->tick & 0x3f) == 0x25)
2451 {
2452 /* Workaround for beacon stuck after SW reset */
2453 if (hpPriv->ibssBcnEnabled != 0)
2454 {
2455 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_ADDR, ZM_BEACON_BUFFER_ADDRESS);
2456 polluted = 1;
2457 }
2458
2459 //DbgPrint("hpPriv->aggMaxDurationBE=%d", hpPriv->aggMaxDurationBE);
2460 //DbgPrint("wd->sta.avgSizeOfReceivePackets=%d", wd->sta.avgSizeOfReceivePackets);
2461 if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE )
2462 && (zfStaIsConnected(dev))
2463 && (wd->sta.EnableHT == 1) //11n mode
2464 && (wd->BandWidth40 == 1) //40MHz mode
2465 && (wd->sta.enableDrvBA ==0) //Marvel AP
2466 && (hpPriv->aggMaxDurationBE > 2000) //BE TXOP > 2ms
2467 && (wd->sta.avgSizeOfReceivePackets > 1420))
2468 {
2469 zfDelayWriteInternalReg(dev, 0x1c3b9c, 0x8000a);
2470 polluted = 1;
2471 }
2472 else
2473 {
2474 zfDelayWriteInternalReg(dev, 0x1c3b9c, hpPriv->aggPktNum);
2475 polluted = 1;
2476 }
2477
2478 if (wd->dynamicSIFSEnable == 0)
2479 {
2480 if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE )
2481 && (zfStaIsConnected(dev))
2482 && (wd->sta.EnableHT == 1) //11n mode
2483 && (wd->BandWidth40 == 0) //20MHz mode
2484 && (wd->sta.enableDrvBA ==0)) //Marvel AP
2485 {
2486 zfDelayWriteInternalReg(dev, 0x1c3698, 0x5144000);
2487 polluted = 1;
2488 }
2489 else
2490 {
2491 zfDelayWriteInternalReg(dev, 0x1c3698, 0xA144000);
2492 polluted = 1;
2493 }
2494 }
2495 else
2496 {
2497 if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE )
2498 && (zfStaIsConnected(dev))
2499 && (wd->sta.EnableHT == 1) //11n mode
2500 && (wd->sta.athOwlAp == 1)) //Atheros AP
2501 {
2502 if (hpPriv->retransmissionEvent)
2503 {
2504 switch(hpPriv->latestSIFS)
2505 {
2506 case 0:
2507 hpPriv->latestSIFS = 1;
2508 zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0x8144000);
2509 break;
2510 case 1:
2511 hpPriv->latestSIFS = 2;
2512 zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0xa144000);
2513 break;
2514 case 2:
2515 hpPriv->latestSIFS = 3;
2516 zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0xc144000);
2517 break;
2518 case 3:
2519 hpPriv->latestSIFS = 0;
2520 zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0xa144000);
2521 break;
2522 default:
2523 hpPriv->latestSIFS = 0;
2524 zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0xa144000);
2525 break;
2526 }
2527 polluted = 1;
2528 zm_debug_msg1("##### Correct Tx retransmission issue #####, ", hpPriv->latestSIFS);
2529 hpPriv->retransmissionEvent = 0;
2530 }
2531 }
2532 else
2533 {
2534 hpPriv->latestSIFS = 0;
2535 hpPriv->retransmissionEvent = 0;
2536 zfDelayWriteInternalReg(dev, 0x1c3698, 0xA144000);
2537 polluted = 1;
2538 }
2539 }
2540
2541 if ((wd->sta.bScheduleScan == FALSE) && (wd->sta.bChannelScan == FALSE))
2542 {
2543 #define ZM_SIGNAL_THRESHOLD 66
2544 if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE )
2545 && (zfStaIsConnected(dev))
2546 && (wd->SignalStrength > ZM_SIGNAL_THRESHOLD))
2547 {
2548 /* remove state handle, always rewrite register setting */
2549 //if (hpPriv->strongRSSI == 0)
2550 {
2551 hpPriv->strongRSSI = 1;
2552 /* Strong RSSI, set ACK to one Tx stream and lower Tx power 7dbm */
2553 if (hpPriv->currentAckRtsTpc > (14+10))
2554 {
2555 ackTpc = hpPriv->currentAckRtsTpc - 14;
2556 }
2557 else
2558 {
2559 ackTpc = 10;
2560 }
2561 zfDelayWriteInternalReg(dev, 0x1c3694, ((ackTpc) << 20) | (0x1<<26));
2562 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((ackTpc) << 5 ) | (0x1<<11) |
2563 ((ackTpc) << 21) | (0x1<<27) );
2564 polluted = 1;
2565 }
2566 }
2567 else
2568 {
2569 /* remove state handle, always rewrite register setting */
2570 //if (hpPriv->strongRSSI == 1)
2571 {
2572 hpPriv->strongRSSI = 0;
2573 if (hpPriv->halCapability & ZM_HP_CAP_11N_ONE_TX_STREAM)
2574 {
2575 zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->currentAckRtsTpc&0x3f) << 20) | (0x1<<26));
2576 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->currentAckRtsTpc&0x3f) << 5 ) | (0x1<<11) |
2577 ((hpPriv->currentAckRtsTpc&0x3f) << 21) | (0x1<<27) );
2578 }
2579 else
2580 {
2581 zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->currentAckRtsTpc&0x3f) << 20) | (0x5<<26));
2582 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->currentAckRtsTpc&0x3f) << 5 ) | (0x5<<11) |
2583 ((hpPriv->currentAckRtsTpc&0x3f) << 21) | (0x5<<27) );
2584 }
2585 polluted = 1;
2586 }
2587 }
2588 #undef ZM_SIGNAL_THRESHOLD
2589 }
2590
2591 if ((hpPriv->halCapability & ZM_HP_CAP_11N_ONE_TX_STREAM) == 0)
2592 {
2593 if ((wd->sta.bScheduleScan == FALSE) && (wd->sta.bChannelScan == FALSE))
2594 {
2595 #define ZM_RX_SIGNAL_THRESHOLD_H 71
2596 #define ZM_RX_SIGNAL_THRESHOLD_L 66
2597 u8_t rxSignalThresholdH = ZM_RX_SIGNAL_THRESHOLD_H;
2598 u8_t rxSignalThresholdL = ZM_RX_SIGNAL_THRESHOLD_L;
2599 #undef ZM_RX_SIGNAL_THRESHOLD_H
2600 #undef ZM_RX_SIGNAL_THRESHOLD_L
2601
2602 if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE )
2603 && (zfStaIsConnected(dev))
2604 && (wd->SignalStrength > rxSignalThresholdH)
2605 )//&& (hpPriv->rxStrongRSSI == 0))
2606 {
2607 hpPriv->rxStrongRSSI = 1;
2608 //zfDelayWriteInternalReg(dev, 0x1c5964, 0x1220);
2609 //zfDelayWriteInternalReg(dev, 0x1c5960, 0x900);
2610 //zfDelayWriteInternalReg(dev, 0x1c6960, 0x900);
2611 //zfDelayWriteInternalReg(dev, 0x1c7960, 0x900);
2612 if ((hpPriv->eepromImage[0x100+0x110*2/4]&0xff) == 0x80) //FEM TYPE
2613 {
2614 if (hpPriv->hwFrequency <= ZM_CH_G_14)
2615 {
2616 zfDelayWriteInternalReg(dev, 0x1c8960, 0x900);
2617 }
2618 else
2619 {
2620 zfDelayWriteInternalReg(dev, 0x1c8960, 0x9b49);
2621 }
2622 }
2623 else
2624 {
2625 zfDelayWriteInternalReg(dev, 0x1c8960, 0x0900);
2626 }
2627 polluted = 1;
2628 }
2629 else if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE )
2630 && (zfStaIsConnected(dev))
2631 && (wd->SignalStrength > rxSignalThresholdL)
2632 )//&& (hpPriv->rxStrongRSSI == 1))
2633 {
2634 //Do nothing to prevent frequently Rx switching
2635 }
2636 else
2637 {
2638 /* remove state handle, always rewrite register setting */
2639 //if (hpPriv->rxStrongRSSI == 1)
2640 {
2641 hpPriv->rxStrongRSSI = 0;
2642 //zfDelayWriteInternalReg(dev, 0x1c5964, 0x1120);
2643 //zfDelayWriteInternalReg(dev, 0x1c5960, 0x9b40);
2644 //zfDelayWriteInternalReg(dev, 0x1c6960, 0x9b40);
2645 //zfDelayWriteInternalReg(dev, 0x1c7960, 0x9b40);
2646 if ((hpPriv->eepromImage[0x100+0x110*2/4]&0xff) == 0x80) //FEM TYPE
2647 {
2648 if (hpPriv->hwFrequency <= ZM_CH_G_14)
2649 {
2650 zfDelayWriteInternalReg(dev, 0x1c8960, 0x9b49);
2651 }
2652 else
2653 {
2654 zfDelayWriteInternalReg(dev, 0x1c8960, 0x0900);
2655 }
2656 }
2657 else
2658 {
2659 zfDelayWriteInternalReg(dev, 0x1c8960, 0x9b40);
2660 }
2661 polluted = 1;
2662 }
2663 }
2664
2665 }
2666 }
2667
2668 if (hpPriv->usbAcSendBytes[3] > (hpPriv->usbAcSendBytes[0]*2))
2669 {
2670 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_TXOP, hpPriv->txop[3]);
2671 polluted = 1;
2672 }
2673 else if (hpPriv->usbAcSendBytes[2] > (hpPriv->usbAcSendBytes[0]*2))
2674 {
2675 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_TXOP, hpPriv->txop[2]);
2676 polluted = 1;
2677 }
2678 else if (hpPriv->usbAcSendBytes[1] > (hpPriv->usbAcSendBytes[0]*2))
2679 {
2680 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, hpPriv->cwmin[1]+((u32_t)hpPriv->cwmax[1]<<16));
2681 polluted = 1;
2682 }
2683 else
2684 {
2685 if (hpPriv->slotType == 1)
2686 {
2687 if ((wd->sta.enableDrvBA ==0) //Marvel AP
2688 && (hpPriv->aggMaxDurationBE > 2000)) //BE TXOP > 2ms
2689 {
2690 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, (hpPriv->cwmin[0]/2)+((u32_t)hpPriv->cwmax[0]<<16));
2691 }
2692 else
2693 {
2694 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, hpPriv->cwmin[0]+((u32_t)hpPriv->cwmax[0]<<16));
2695 }
2696 polluted = 1;
2697 }
2698 else
2699 {
2700 /* Compensation for 20us slot time */
2701 //zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, 58+((u32_t)hpPriv->cwmax[0]<<16));
2702 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, hpPriv->cwmin[0]+((u32_t)hpPriv->cwmax[0]<<16));
2703 polluted = 1;
2704 }
2705
2706 if ((wd->sta.SWEncryptEnable & (ZM_SW_TKIP_ENCRY_EN|ZM_SW_WEP_ENCRY_EN)) == 0)
2707 {
2708 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_TXOP, hpPriv->txop[0]);
2709 polluted = 1;
2710 }
2711 else
2712 {
2713 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_TXOP, 0x30);
2714 polluted = 1;
2715 }
2716
2717 }
2718 hpPriv->usbAcSendBytes[3] = 0;
2719 hpPriv->usbAcSendBytes[2] = 0;
2720 hpPriv->usbAcSendBytes[1] = 0;
2721 hpPriv->usbAcSendBytes[0] = 0;
2722 }
2723
2724 if (polluted == 1)
2725 {
2726 zfFlushDelayWrite(dev);
2727 }
2728
2729 return;
2730 }
2731
2732 /*
2733 * 0x1d4008 : AHB, DAC, ADC clock selection
2734 * bit1~0 AHB_CLK : AHB clock selection,
2735 * 00 : OSC 40MHz;
2736 * 01 : 20MHz in A mode, 22MHz in G mode;
2737 * 10 : 40MHz in A mode, 44MHz in G mode;
2738 * 11 : 80MHz in A mode, 88MHz in G mode.
2739 * bit3~2 CLK_SEL : Select the clock source of clk160 in ADDAC.
2740 * 00 : PLL divider's output;
2741 * 01 : PLL divider's output divided by 2;
2742 * 10 : PLL divider's output divided by 4;
2743 * 11 : REFCLK from XTALOSCPAD.
2744 */
2745 void zfSelAdcClk(zdev_t* dev, u8_t bw40, u32_t frequency)
2746 {
2747 if(bw40 == 1)
2748 {
2749 //zfDelayWriteInternalReg(dev, 0x1D4008, 0x73);
2750 zfDelayWriteInternalReg(dev, ZM_MAC_REG_DYNAMIC_SIFS_ACK, 0x10A);
2751 zfFlushDelayWrite(dev);
2752 }
2753 else
2754 {
2755 //zfDelayWriteInternalReg(dev, 0x1D4008, 0x70);
2756 if ( frequency <= ZM_CH_G_14 )
2757 {
2758 zfDelayWriteInternalReg(dev, ZM_MAC_REG_DYNAMIC_SIFS_ACK, 0x105);
2759 }
2760 else
2761 {
2762 zfDelayWriteInternalReg(dev, ZM_MAC_REG_DYNAMIC_SIFS_ACK, 0x104);
2763 }
2764 zfFlushDelayWrite(dev);
2765 }
2766 }
2767
2768 u32_t zfHpEchoCommand(zdev_t* dev, u32_t value)
2769 {
2770 u32_t cmd[2];
2771 u16_t ret;
2772
2773 cmd[0] = 0x00008004;
2774 cmd[1] = value;
2775
2776 ret = zfIssueCmd(dev, cmd, 8, ZM_CMD_ECHO, NULL);
2777 return ret;
2778 }
2779
2780 #ifdef ZM_DRV_INIT_USB_MODE
2781
2782 #define ZM_USB_US_STREAM_MODE 0x00000000
2783 #define ZM_USB_US_PACKET_MODE 0x00000008
2784 #define ZM_USB_DS_ENABLE 0x00000001
2785 #define ZM_USB_US_ENABLE 0x00000002
2786
2787 #define ZM_USB_RX_STREAM_4K 0x00000000
2788 #define ZM_USB_RX_STREAM_8K 0x00000010
2789 #define ZM_USB_RX_STREAM_16K 0x00000020
2790 #define ZM_USB_RX_STREAM_32K 0x00000030
2791
2792 #define ZM_USB_TX_STREAM_MODE 0x00000040
2793
2794 #define ZM_USB_MODE_CTRL_REG 0x001E1108
2795
2796 void zfInitUsbMode(zdev_t* dev)
2797 {
2798 u32_t mode;
2799 zmw_get_wlan_dev(dev);
2800
2801 /* TODO: Set USB mode by reading registery */
2802 mode = ZM_USB_DS_ENABLE | ZM_USB_US_ENABLE | ZM_USB_US_PACKET_MODE;
2803
2804 zfDelayWriteInternalReg(dev, ZM_USB_MODE_CTRL_REG, mode);
2805 zfFlushDelayWrite(dev);
2806 }
2807 #endif
2808
2809 void zfDumpEepBandEdges(struct ar5416Eeprom* eepromImage);
2810 void zfPrintTargetPower2G(u8_t* tPow2xCck, u8_t* tPow2x2g, u8_t* tPow2x2gHt20, u8_t* tPow2x2gHt40);
2811 void zfPrintTargetPower5G(u8_t* tPow2x5g, u8_t* tPow2x5gHt20, u8_t* tPow2x5gHt40);
2812
2813
2814 s32_t zfInterpolateFunc(s32_t x, s32_t x1, s32_t y1, s32_t x2, s32_t y2)
2815 {
2816 s32_t y;
2817
2818 if (y2 == y1)
2819 {
2820 y = y1;
2821 }
2822 else if (x == x1)
2823 {
2824 y = y1;
2825 }
2826 else if (x == x2)
2827 {
2828 y = y2;
2829 }
2830 else if (x2 != x1)
2831 {
2832 y = y1 + (((y2-y1) * (x-x1))/(x2-x1));
2833 }
2834 else
2835 {
2836 y = y1;
2837 }
2838
2839 return y;
2840 }
2841
2842 //#define ZM_ENABLE_TPC_WINDOWS_DEBUG
2843 //#define ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
2844
2845 /* the tx power offset workaround for ART vs NDIS/MDK */
2846 #define HALTX_POWER_OFFSET 0
2847
2848 u8_t zfInterpolateFuncX(u8_t x, u8_t x1, u8_t y1, u8_t x2, u8_t y2)
2849 {
2850 s32_t y;
2851 s32_t inc;
2852
2853 #define ZM_MULTIPLIER 8
2854 y = zfInterpolateFunc((s32_t)x<<ZM_MULTIPLIER,
2855 (s32_t)x1<<ZM_MULTIPLIER,
2856 (s32_t)y1<<ZM_MULTIPLIER,
2857 (s32_t)x2<<ZM_MULTIPLIER,
2858 (s32_t)y2<<ZM_MULTIPLIER);
2859
2860 inc = (y & (1<<(ZM_MULTIPLIER-1))) >> (ZM_MULTIPLIER-1);
2861 y = (y >> ZM_MULTIPLIER) + inc;
2862 #undef ZM_MULTIPLIER
2863
2864 return (u8_t)y;
2865 }
2866
2867 u8_t zfGetInterpolatedValue(u8_t x, u8_t* x_array, u8_t* y_array)
2868 {
2869 s32_t y;
2870 u16_t xIndex;
2871
2872 if (x <= x_array[1])
2873 {
2874 xIndex = 0;
2875 }
2876 else if (x <= x_array[2])
2877 {
2878 xIndex = 1;
2879 }
2880 else if (x <= x_array[3])
2881 {
2882 xIndex = 2;
2883 }
2884 else //(x > x_array[3])
2885 {
2886 xIndex = 3;
2887 }
2888
2889 y = zfInterpolateFuncX(x,
2890 x_array[xIndex],
2891 y_array[xIndex],
2892 x_array[xIndex+1],
2893 y_array[xIndex+1]);
2894
2895 return (u8_t)y;
2896 }
2897
2898 u8_t zfFindFreqIndex(u8_t f, u8_t* fArray, u8_t fArraySize)
2899 {
2900 u8_t i;
2901 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
2902 DbgPrint("f=%d ", f);
2903 for (i=0; i<fArraySize; i++)
2904 {
2905 DbgPrint("%d ", fArray[i]);
2906 }
2907 DbgPrint("\n");
2908 #endif
2909 i=fArraySize-2;
2910 while(1)
2911 {
2912 if (f >= fArray[i])
2913 {
2914 return i;
2915 }
2916 if (i!=0)
2917 {
2918 i--;
2919 }
2920 else
2921 {
2922 return 0;
2923 }
2924 }
2925 }
2926
2927
2928
2929
2930 void zfInitPowerCal(zdev_t* dev)
2931 {
2932 //Program PHY Tx power relatives registers
2933 #define zm_write_phy_reg(cr, val) reg_write((cr*4)+0x9800, val)
2934
2935 zm_write_phy_reg(79, 0x7f);
2936 zm_write_phy_reg(77, 0x3f3f3f3f);
2937 zm_write_phy_reg(78, 0x3f3f3f3f);
2938 zm_write_phy_reg(653, 0x3f3f3f3f);
2939 zm_write_phy_reg(654, 0x3f3f3f3f);
2940 zm_write_phy_reg(739, 0x3f3f3f3f);
2941 zm_write_phy_reg(740, 0x3f3f3f3f);
2942 zm_write_phy_reg(755, 0x3f3f3f3f);
2943 zm_write_phy_reg(756, 0x3f3f3f3f);
2944 zm_write_phy_reg(757, 0x3f3f3f3f);
2945
2946 #undef zm_write_phy_reg
2947 }
2948
2949
2950
2951 void zfPrintTp(u8_t* pwr0, u8_t* vpd0, u8_t* pwr1, u8_t* vpd1)
2952 {
2953 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
2954 DbgPrint("pwr0 : %d, %d, %d, %d ,%d\n", pwr0[0], pwr0[1], pwr0[2], pwr0[3], pwr0[4]);
2955 DbgPrint("vpd0 : %d, %d, %d, %d ,%d\n", vpd0[0], vpd0[1], vpd0[2], vpd0[3], vpd0[4]);
2956 DbgPrint("pwr1 : %d, %d, %d, %d ,%d\n", pwr1[0], pwr1[1], pwr1[2], pwr1[3], pwr1[4]);
2957 DbgPrint("vpd1 : %d, %d, %d, %d ,%d\n", vpd1[0], vpd1[1], vpd1[2], vpd1[3], vpd1[4]);
2958 #endif
2959 }
2960
2961
2962 /*
2963 * To find CTL index(0~23)
2964 * return 24(AR5416_NUM_CTLS)=>no desired index found
2965 */
2966 u8_t zfFindCtlEdgesIndex(zdev_t* dev, u8_t desired_CtlIndex)
2967 {
2968 u8_t i;
2969 struct zsHpPriv* hpPriv;
2970 struct ar5416Eeprom* eepromImage;
2971
2972 zmw_get_wlan_dev(dev);
2973
2974 hpPriv = wd->hpPrivate;
2975
2976 eepromImage = (struct ar5416Eeprom*)&(hpPriv->eepromImage[(1024+512)/4]);
2977
2978 //for (i = 0; (i < AR5416_NUM_CTLS) && eepromImage->ctlIndex[i]; i++)
2979 for (i = 0; i < AR5416_NUM_CTLS; i++)
2980 {
2981 if(desired_CtlIndex == eepromImage->ctlIndex[i])
2982 break;
2983 }
2984 return i;
2985 }
2986
2987 /**************************************************************************
2988 * fbin2freq
2989 *
2990 * Get channel value from binary representation held in eeprom
2991 * RETURNS: the frequency in MHz
2992 */
2993 u32_t
2994 fbin2freq(u8_t fbin, u8_t is2GHz)
2995 {
2996 /*
2997 * Reserved value 0xFF provides an empty definition both as
2998 * an fbin and as a frequency - do not convert
2999 */
3000 if (fbin == AR5416_BCHAN_UNUSED) {
3001 return fbin;
3002 }
3003
3004 return (u32_t)((is2GHz==1) ? (2300 + fbin) : (4800 + 5 * fbin));
3005 }
3006
3007
3008 u8_t zfGetMaxEdgePower(zdev_t* dev, CAL_CTL_EDGES *pCtlEdges, u32_t freq)
3009 {
3010 u8_t i;
3011 u8_t maxEdgePower;
3012 u8_t is2GHz;
3013 struct zsHpPriv* hpPriv;
3014 struct ar5416Eeprom* eepromImage;
3015
3016 zmw_get_wlan_dev(dev);
3017
3018 hpPriv = wd->hpPrivate;
3019
3020 eepromImage = (struct ar5416Eeprom*)&(hpPriv->eepromImage[(1024+512)/4]);
3021
3022 if(freq > ZM_CH_G_14)
3023 is2GHz = 0;
3024 else
3025 is2GHz = 1;
3026
3027 maxEdgePower = AR5416_MAX_RATE_POWER;
3028
3029 /* Get the edge power */
3030 for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pCtlEdges[i].bChannel != AR5416_BCHAN_UNUSED) ; i++)
3031 {
3032 /*
3033 * If there's an exact channel match or an inband flag set
3034 * on the lower channel use the given rdEdgePower
3035 */
3036 if (freq == fbin2freq(pCtlEdges[i].bChannel, is2GHz))
3037 {
3038 maxEdgePower = pCtlEdges[i].tPower;
3039 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3040 zm_dbg(("zfGetMaxEdgePower index i = %d \n", i));
3041 #endif
3042 break;
3043 }
3044 else if ((i > 0) && (freq < fbin2freq(pCtlEdges[i].bChannel, is2GHz)))
3045 {
3046 if (fbin2freq(pCtlEdges[i - 1].bChannel, is2GHz) < freq && pCtlEdges[i - 1].flag)
3047 {
3048 maxEdgePower = pCtlEdges[i - 1].tPower;
3049 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3050 zm_dbg(("zfGetMaxEdgePower index i-1 = %d \n", i-1));
3051 #endif
3052 }
3053 /* Leave loop - no more affecting edges possible in this monotonic increasing list */
3054 break;
3055 }
3056
3057 }
3058
3059 if( i == AR5416_NUM_BAND_EDGES )
3060 {
3061 if (freq > fbin2freq(pCtlEdges[i - 1].bChannel, is2GHz) && pCtlEdges[i - 1].flag)
3062 {
3063 maxEdgePower = pCtlEdges[i - 1].tPower;
3064 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3065 zm_dbg(("zfGetMaxEdgePower index=>i-1 = %d \n", i-1));
3066 #endif
3067 }
3068 }
3069
3070 zm_assert(maxEdgePower > 0);
3071
3072 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3073 if ( maxEdgePower == AR5416_MAX_RATE_POWER )
3074 {
3075 zm_dbg(("zfGetMaxEdgePower = %d !!!\n", AR5416_MAX_RATE_POWER));
3076 }
3077 #endif
3078 return maxEdgePower;
3079 }
3080
3081 u32_t zfAdjustHT40FreqOffset(zdev_t* dev, u32_t frequency, u8_t bw40, u8_t extOffset)
3082 {
3083 u32_t newFreq = frequency;
3084
3085 if (bw40 == 1)
3086 {
3087 if (extOffset == 1)
3088 {
3089 newFreq += 10;
3090 }
3091 else
3092 {
3093 newFreq -= 10;
3094 }
3095 }
3096 return newFreq;
3097 }
3098
3099 u32_t zfHpCheckDoHeavyClip(zdev_t* dev, u32_t freq, CAL_CTL_EDGES *pCtlEdges, u8_t bw40)
3100 {
3101 u32_t ret = 0;
3102 u8_t i;
3103 u8_t is2GHz;
3104 struct zsHpPriv* hpPriv;
3105
3106 zmw_get_wlan_dev(dev);
3107
3108 hpPriv = wd->hpPrivate;
3109
3110 if(freq > ZM_CH_G_14)
3111 is2GHz = 0;
3112 else
3113 is2GHz = 1;
3114
3115 /* HT40 force enable heavy clip */
3116 if (bw40)
3117 {
3118 ret |= 0xf0;
3119 }
3120 #if 1
3121 /* HT20 : frequency bandedge */
3122 for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pCtlEdges[i].bChannel != AR5416_BCHAN_UNUSED) ; i++)
3123 {
3124 if (freq == fbin2freq(pCtlEdges[i].bChannel, is2GHz))
3125 {
3126 if (pCtlEdges[i].flag == 0)
3127 {
3128 ret |= 0xf;
3129 }
3130 break;
3131 }
3132 }
3133 #endif
3134
3135 return ret;
3136 }
3137
3138
3139 void zfSetPowerCalTable(zdev_t* dev, u32_t frequency, u8_t bw40, u8_t extOffset)
3140 {
3141 struct ar5416Eeprom* eepromImage;
3142 u8_t pwr0[5];
3143 u8_t pwr1[5];
3144 u8_t vpd0[5];
3145 u8_t vpd1[5];
3146 u8_t vpd_chain1[128];
3147 u8_t vpd_chain3[128];
3148 u16_t boundary1 = 18; //CR 667
3149 u16_t powerTxMax = 63; //CR 79
3150 u8_t i;
3151 struct zsHpPriv* hpPriv;
3152 u8_t fbin;
3153 u8_t index, max2gIndex, max5gIndex;
3154 u8_t chain0pwrPdg0[5];
3155 u8_t chain0vpdPdg0[5];
3156 u8_t chain0pwrPdg1[5];
3157 u8_t chain0vpdPdg1[5];
3158 u8_t chain2pwrPdg0[5];
3159 u8_t chain2vpdPdg0[5];
3160 u8_t chain2pwrPdg1[5];
3161 u8_t chain2vpdPdg1[5];
3162 u8_t fbinArray[8];
3163
3164 /* 4 CTL */
3165 u8_t ctl_i;
3166 u8_t desired_CtlIndex;
3167
3168 u8_t ctlEdgesMaxPowerCCK = AR5416_MAX_RATE_POWER;
3169 u8_t ctlEdgesMaxPower2G = AR5416_MAX_RATE_POWER;
3170 u8_t ctlEdgesMaxPower2GHT20 = AR5416_MAX_RATE_POWER;
3171 u8_t ctlEdgesMaxPower2GHT40 = AR5416_MAX_RATE_POWER;
3172 u8_t ctlEdgesMaxPower5G = AR5416_MAX_RATE_POWER;
3173 u8_t ctlEdgesMaxPower5GHT20 = AR5416_MAX_RATE_POWER;
3174 u8_t ctlEdgesMaxPower5GHT40 = AR5416_MAX_RATE_POWER;
3175
3176 u8_t ctlOffset;
3177
3178 zmw_get_wlan_dev(dev);
3179
3180 hpPriv = wd->hpPrivate;
3181
3182 eepromImage = (struct ar5416Eeprom*)&(hpPriv->eepromImage[(1024+512)/4]);
3183
3184 // Check the total bytes of the EEPROM structure to see the dongle have been calibrated or not.
3185 if (eepromImage->baseEepHeader.length == 0xffff)
3186 {
3187 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3188 zm_dbg(("Warning! This dongle not been calibrated\n"));
3189 #endif
3190 return;
3191 }
3192
3193 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3194 DbgPrint("-----zfSetPowerCalTable : frequency=%d-----\n", frequency);
3195 #endif
3196 /* TODO : 1. boundary1 and powerTxMax should be refered to CR667 and CR79 */
3197 /* in otus.ini file */
3198
3199 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3200 /* 2. Interpolate pwr and vpd test points from frequency */
3201 DbgPrint("calFreqPier5G : %d, %d, %d, %d ,%d, %d, %d, %d\n",
3202 eepromImage->calFreqPier5G[0]*5+4800,
3203 eepromImage->calFreqPier5G[1]*5+4800,
3204 eepromImage->calFreqPier5G[2]*5+4800,
3205 eepromImage->calFreqPier5G[3]*5+4800,
3206 eepromImage->calFreqPier5G[4]*5+4800,
3207 eepromImage->calFreqPier5G[5]*5+4800,
3208 eepromImage->calFreqPier5G[6]*5+4800,
3209 eepromImage->calFreqPier5G[7]*5+4800
3210 );
3211 DbgPrint("calFreqPier2G : %d, %d, %d, %d\n",
3212 eepromImage->calFreqPier2G[0]+2300,
3213 eepromImage->calFreqPier2G[1]+2300,
3214 eepromImage->calFreqPier2G[2]+2300,
3215 eepromImage->calFreqPier2G[3]+2300
3216 );
3217 #endif
3218 if (frequency < 3000)
3219 {
3220 for (i=0; i<4; i++)
3221 {
3222 if (eepromImage->calFreqPier2G[i] == 0xff)
3223 {
3224 break;
3225 }
3226 }
3227 max2gIndex = i;
3228 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3229 DbgPrint("max2gIndex : %d\n", max2gIndex);
3230 #endif
3231 fbin = (u8_t)(frequency - 2300);
3232 index = zfFindFreqIndex(fbin, eepromImage->calFreqPier2G, max2gIndex);
3233 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3234 DbgPrint("2G index : %d\n", index);
3235 DbgPrint("chain 0 index\n");
3236 #endif
3237 zfPrintTp(&eepromImage->calPierData2G[0][index].pwrPdg[0][0],
3238 &eepromImage->calPierData2G[0][index].vpdPdg[0][0],
3239 &eepromImage->calPierData2G[0][index].pwrPdg[1][0],
3240 &eepromImage->calPierData2G[0][index].vpdPdg[1][0]
3241 );
3242 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3243 DbgPrint("chain 0 index+1\n");
3244 #endif
3245 zfPrintTp(&eepromImage->calPierData2G[0][index+1].pwrPdg[0][0],
3246 &eepromImage->calPierData2G[0][index+1].vpdPdg[0][0],
3247 &eepromImage->calPierData2G[0][index+1].pwrPdg[1][0],
3248 &eepromImage->calPierData2G[0][index+1].vpdPdg[1][0]
3249 );
3250
3251 for (i=0; i<5; i++)
3252 {
3253 chain0pwrPdg0[i] = zfInterpolateFuncX(fbin,
3254 eepromImage->calFreqPier2G[index],
3255 eepromImage->calPierData2G[0][index].pwrPdg[0][i],
3256 eepromImage->calFreqPier2G[index+1],
3257 eepromImage->calPierData2G[0][index+1].pwrPdg[0][i]
3258 );
3259 chain0vpdPdg0[i] = zfInterpolateFuncX(fbin,
3260 eepromImage->calFreqPier2G[index],
3261 eepromImage->calPierData2G[0][index].vpdPdg[0][i],
3262 eepromImage->calFreqPier2G[index+1],
3263 eepromImage->calPierData2G[0][index+1].vpdPdg[0][i]
3264 );
3265 chain0pwrPdg1[i] = zfInterpolateFuncX(fbin,
3266 eepromImage->calFreqPier2G[index],
3267 eepromImage->calPierData2G[0][index].pwrPdg[1][i],
3268 eepromImage->calFreqPier2G[index+1],
3269 eepromImage->calPierData2G[0][index+1].pwrPdg[1][i]
3270 );
3271 chain0vpdPdg1[i] = zfInterpolateFuncX(fbin,
3272 eepromImage->calFreqPier2G[index],
3273 eepromImage->calPierData2G[0][index].vpdPdg[1][i],
3274 eepromImage->calFreqPier2G[index+1],
3275 eepromImage->calPierData2G[0][index+1].vpdPdg[1][i]
3276 );
3277
3278 chain2pwrPdg0[i] = zfInterpolateFuncX(fbin,
3279 eepromImage->calFreqPier2G[index],
3280 eepromImage->calPierData2G[1][index].pwrPdg[0][i],
3281 eepromImage->calFreqPier2G[index+1],
3282 eepromImage->calPierData2G[1][index+1].pwrPdg[0][i]
3283 );
3284 chain2vpdPdg0[i] = zfInterpolateFuncX(fbin,
3285 eepromImage->calFreqPier2G[index],
3286 eepromImage->calPierData2G[1][index].vpdPdg[0][i],
3287 eepromImage->calFreqPier2G[index+1],
3288 eepromImage->calPierData2G[1][index+1].vpdPdg[0][i]
3289 );
3290 chain2pwrPdg1[i] = zfInterpolateFuncX(fbin,
3291 eepromImage->calFreqPier2G[index],
3292 eepromImage->calPierData2G[1][index].pwrPdg[1][i],
3293 eepromImage->calFreqPier2G[index+1],
3294 eepromImage->calPierData2G[1][index+1].pwrPdg[1][i]
3295 );
3296 chain2vpdPdg1[i] = zfInterpolateFuncX(fbin,
3297 eepromImage->calFreqPier2G[index],
3298 eepromImage->calPierData2G[1][index].vpdPdg[1][i],
3299 eepromImage->calFreqPier2G[index+1],
3300 eepromImage->calPierData2G[1][index+1].vpdPdg[1][i]
3301 );
3302 }
3303 }
3304 else
3305 {
3306 for (i=0; i<8; i++)
3307 {
3308 if (eepromImage->calFreqPier5G[i] == 0xff)
3309 {
3310 break;
3311 }
3312 }
3313 max5gIndex = i;
3314 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3315 DbgPrint("max5gIndex : %d\n", max5gIndex);
3316 #endif
3317 fbin = (u8_t)((frequency - 4800)/5);
3318 index = zfFindFreqIndex(fbin, eepromImage->calFreqPier5G, max5gIndex);
3319 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3320 DbgPrint("5G index : %d\n", index);
3321 #endif
3322
3323 for (i=0; i<5; i++)
3324 {
3325 chain0pwrPdg0[i] = zfInterpolateFuncX(fbin,
3326 eepromImage->calFreqPier5G[index],
3327 eepromImage->calPierData5G[0][index].pwrPdg[0][i],
3328 eepromImage->calFreqPier5G[index+1],
3329 eepromImage->calPierData5G[0][index+1].pwrPdg[0][i]
3330 );
3331 chain0vpdPdg0[i] = zfInterpolateFuncX(fbin,
3332 eepromImage->calFreqPier5G[index],
3333 eepromImage->calPierData5G[0][index].vpdPdg[0][i],
3334 eepromImage->calFreqPier5G[index+1],
3335 eepromImage->calPierData5G[0][index+1].vpdPdg[0][i]
3336 );
3337 chain0pwrPdg1[i] = zfInterpolateFuncX(fbin,
3338 eepromImage->calFreqPier5G[index],
3339 eepromImage->calPierData5G[0][index].pwrPdg[1][i],
3340 eepromImage->calFreqPier5G[index+1],
3341 eepromImage->calPierData5G[0][index+1].pwrPdg[1][i]
3342 );
3343 chain0vpdPdg1[i] = zfInterpolateFuncX(fbin,
3344 eepromImage->calFreqPier5G[index],
3345 eepromImage->calPierData5G[0][index].vpdPdg[1][i],
3346 eepromImage->calFreqPier5G[index+1],
3347 eepromImage->calPierData5G[0][index+1].vpdPdg[1][i]
3348 );
3349
3350 chain2pwrPdg0[i] = zfInterpolateFuncX(fbin,
3351 eepromImage->calFreqPier5G[index],
3352 eepromImage->calPierData5G[1][index].pwrPdg[0][i],
3353 eepromImage->calFreqPier5G[index+1],
3354 eepromImage->calPierData5G[1][index+1].pwrPdg[0][i]
3355 );
3356 chain2vpdPdg0[i] = zfInterpolateFuncX(fbin,
3357 eepromImage->calFreqPier5G[index],
3358 eepromImage->calPierData5G[1][index].vpdPdg[0][i],
3359 eepromImage->calFreqPier5G[index+1],
3360 eepromImage->calPierData5G[1][index+1].vpdPdg[0][i]
3361 );
3362 chain2pwrPdg1[i] = zfInterpolateFuncX(fbin,
3363 eepromImage->calFreqPier5G[index],
3364 eepromImage->calPierData5G[1][index].pwrPdg[1][i],
3365 eepromImage->calFreqPier5G[index+1],
3366 eepromImage->calPierData5G[1][index+1].pwrPdg[1][i]
3367 );
3368 chain2vpdPdg1[i] = zfInterpolateFuncX(fbin,
3369 eepromImage->calFreqPier5G[index],
3370 eepromImage->calPierData5G[1][index].vpdPdg[1][i],
3371 eepromImage->calFreqPier5G[index+1],
3372 eepromImage->calPierData5G[1][index+1].vpdPdg[1][i]
3373 );
3374 }
3375
3376 }
3377
3378
3379 /* Chain 1 */
3380 /* Get pwr and vpd test points from frequency */
3381 for (i=0; i<5; i++)
3382 {
3383 pwr0[i] = chain0pwrPdg0[i]>>1;
3384 vpd0[i] = chain0vpdPdg0[i];
3385 pwr1[i] = chain0pwrPdg1[i]>>1;
3386 vpd1[i] = chain0vpdPdg1[i];
3387 }
3388 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3389 DbgPrint("Test Points\n");
3390 DbgPrint("pwr0 : %d, %d, %d, %d ,%d\n", pwr0[0], pwr0[1], pwr0[2], pwr0[3], pwr0[4]);
3391 DbgPrint("vpd0 : %d, %d, %d, %d ,%d\n", vpd0[0], vpd0[1], vpd0[2], vpd0[3], vpd0[4]);
3392 DbgPrint("pwr1 : %d, %d, %d, %d ,%d\n", pwr1[0], pwr1[1], pwr1[2], pwr1[3], pwr1[4]);
3393 DbgPrint("vpd1 : %d, %d, %d, %d ,%d\n", vpd1[0], vpd1[1], vpd1[2], vpd1[3], vpd1[4]);
3394 #endif
3395 /* Generate the vpd arrays */
3396 for (i=0; i<boundary1+1+6; i++)
3397 {
3398 vpd_chain1[i] = zfGetInterpolatedValue(i, &pwr0[0], &vpd0[0]);
3399 }
3400 for (; i<powerTxMax+1+6+6; i++)
3401 {
3402 vpd_chain1[i] = zfGetInterpolatedValue(i-6-6, &pwr1[0], &vpd1[0]);
3403 }
3404 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3405 DbgPrint("vpd_chain1\n");
3406 for (i=0; i<powerTxMax+1+6+6; i+=10)
3407 {
3408 DbgPrint("%d, %d, %d, %d ,%d, %d, %d, %d, %d, %d\n",
3409 vpd_chain1[i+0], vpd_chain1[i+1], vpd_chain1[i+2], vpd_chain1[i+3], vpd_chain1[i+4],
3410 vpd_chain1[i+5], vpd_chain1[i+6], vpd_chain1[i+7], vpd_chain1[i+8], vpd_chain1[i+9]);
3411 }
3412 #endif
3413 /* Write PHY regs 672-703 */
3414 for (i=0; i<128; i+=4)
3415 {
3416 u32_t regAddr = 0x9800 + (672 * 4);
3417 u32_t val;
3418
3419 val = ((u32_t)vpd_chain1[i+3]<<24) |
3420 ((u32_t)vpd_chain1[i+2]<<16) |
3421 ((u32_t)vpd_chain1[i+1]<<8) |
3422 ((u32_t)vpd_chain1[i]);
3423
3424 #ifndef ZM_OTUS_LINUX_PHASE_2
3425 reg_write(regAddr + i, val); /* CR672 */
3426 #endif
3427 }
3428
3429 /* Chain 2 */
3430 /* Get pwr and vpd test points from frequency */
3431 for (i=0; i<5; i++)
3432 {
3433 pwr0[i] = chain2pwrPdg0[i]>>1;
3434 vpd0[i] = chain2vpdPdg0[i];
3435 pwr1[i] = chain2pwrPdg1[i]>>1;
3436 vpd1[i] = chain2vpdPdg1[i];
3437 }
3438 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3439 DbgPrint("Test Points\n");
3440 DbgPrint("pwr0 : %d, %d, %d, %d ,%d\n", pwr0[0], pwr0[1], pwr0[2], pwr0[3], pwr0[4]);
3441 DbgPrint("vpd0 : %d, %d, %d, %d ,%d\n", vpd0[0], vpd0[1], vpd0[2], vpd0[3], vpd0[4]);
3442 DbgPrint("pwr1 : %d, %d, %d, %d ,%d\n", pwr1[0], pwr1[1], pwr1[2], pwr1[3], pwr1[4]);
3443 DbgPrint("vpd1 : %d, %d, %d, %d ,%d\n", vpd1[0], vpd1[1], vpd1[2], vpd1[3], vpd1[4]);
3444 #endif
3445 /* Generate the vpd arrays */
3446 for (i=0; i<boundary1+1+6; i++)
3447 {
3448 vpd_chain3[i] = zfGetInterpolatedValue(i, &pwr0[0], &vpd0[0]);
3449 }
3450 for (; i<powerTxMax+1+6+6; i++)
3451 {
3452 vpd_chain3[i] = zfGetInterpolatedValue(i-6-6, &pwr1[0], &vpd1[0]);
3453 }
3454 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3455 DbgPrint("vpd_chain3\n");
3456 for (i=0; i<powerTxMax+1+6+6; i+=10)
3457 {
3458 DbgPrint("%d, %d, %d, %d ,%d, %d, %d, %d, %d, %d\n",
3459 vpd_chain3[i+0], vpd_chain3[i+1], vpd_chain3[i+2], vpd_chain3[i+3], vpd_chain3[i+4],
3460 vpd_chain3[i+5], vpd_chain3[i+6], vpd_chain3[i+7], vpd_chain3[i+8], vpd_chain3[i+9]);
3461 }
3462 #endif
3463
3464 /* Write PHY regs 672-703 + 0x1000 */
3465 for (i=0; i<128; i+=4)
3466 {
3467 u32_t regAddr = 0x9800 + (672 * 4) + 0x1000;
3468 u32_t val;
3469
3470 val = ((u32_t)vpd_chain3[i+3]<<24) |
3471 ((u32_t)vpd_chain3[i+2]<<16) |
3472 ((u32_t)vpd_chain3[i+1]<<8) |
3473 ((u32_t)vpd_chain3[i]);
3474
3475 #ifndef ZM_OTUS_LINUX_PHASE_2
3476 reg_write(regAddr + i, val); /* CR672 */
3477 #endif
3478 }
3479
3480 zfFlushDelayWrite(dev);
3481
3482 /* 3. Generate target power table */
3483 if (frequency < 3000)
3484 {
3485 for (i=0; i<3; i++)
3486 {
3487 if (eepromImage->calTargetPowerCck[i].bChannel != 0xff)
3488 {
3489 fbinArray[i] = eepromImage->calTargetPowerCck[i].bChannel;
3490 }
3491 else
3492 {
3493 break;
3494 }
3495
3496 }
3497 index = zfFindFreqIndex(fbin, fbinArray, i);
3498 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3499 DbgPrint("CCK index=%d\n", index);
3500 #endif
3501 for (i=0; i<4; i++)
3502 {
3503 hpPriv->tPow2xCck[i] = zfInterpolateFuncX(fbin,
3504 eepromImage->calTargetPowerCck[index].bChannel,
3505 eepromImage->calTargetPowerCck[index].tPow2x[i],
3506 eepromImage->calTargetPowerCck[index+1].bChannel,
3507 eepromImage->calTargetPowerCck[index+1].tPow2x[i]
3508 );
3509 }
3510
3511 for (i=0; i<4; i++)
3512 {
3513 if (eepromImage->calTargetPower2G[i].bChannel != 0xff)
3514 {
3515 fbinArray[i] = eepromImage->calTargetPower2G[i].bChannel;
3516 }
3517 else
3518 {
3519 break;
3520 }
3521
3522 }
3523 index = zfFindFreqIndex(fbin, fbinArray, i);
3524 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3525 DbgPrint("2G index=%d\n", index);
3526 #endif
3527 for (i=0; i<4; i++)
3528 {
3529 hpPriv->tPow2x2g[i] = zfInterpolateFuncX(fbin,
3530 eepromImage->calTargetPower2G[index].bChannel,
3531 eepromImage->calTargetPower2G[index].tPow2x[i],
3532 eepromImage->calTargetPower2G[index+1].bChannel,
3533 eepromImage->calTargetPower2G[index+1].tPow2x[i]
3534 );
3535 }
3536
3537 for (i=0; i<4; i++)
3538 {
3539 if (eepromImage->calTargetPower2GHT20[i].bChannel != 0xff)
3540 {
3541 fbinArray[i] = eepromImage->calTargetPower2GHT20[i].bChannel;
3542 }
3543 else
3544 {
3545 break;
3546 }
3547
3548 }
3549 index = zfFindFreqIndex(fbin, fbinArray, i);
3550 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3551 DbgPrint("2G HT20 index=%d\n", index);
3552 #endif
3553 for (i=0; i<8; i++)
3554 {
3555 hpPriv->tPow2x2gHt20[i] = zfInterpolateFuncX(fbin,
3556 eepromImage->calTargetPower2GHT20[index].bChannel,
3557 eepromImage->calTargetPower2GHT20[index].tPow2x[i],
3558 eepromImage->calTargetPower2GHT20[index+1].bChannel,
3559 eepromImage->calTargetPower2GHT20[index+1].tPow2x[i]
3560 );
3561 }
3562
3563 for (i=0; i<4; i++)
3564 {
3565 if (eepromImage->calTargetPower2GHT40[i].bChannel != 0xff)
3566 {
3567 fbinArray[i] = eepromImage->calTargetPower2GHT40[i].bChannel;
3568 }
3569 else
3570 {
3571 break;
3572 }
3573
3574 }
3575 index = zfFindFreqIndex( (u8_t)zfAdjustHT40FreqOffset(dev, fbin, bw40, extOffset), fbinArray, i);
3576 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3577 DbgPrint("2G HT40 index=%d\n", index);
3578 #endif
3579 for (i=0; i<8; i++)
3580 {
3581 hpPriv->tPow2x2gHt40[i] = zfInterpolateFuncX(
3582 (u8_t)zfAdjustHT40FreqOffset(dev, fbin, bw40, extOffset),
3583 eepromImage->calTargetPower2GHT40[index].bChannel,
3584 eepromImage->calTargetPower2GHT40[index].tPow2x[i],
3585 eepromImage->calTargetPower2GHT40[index+1].bChannel,
3586 eepromImage->calTargetPower2GHT40[index+1].tPow2x[i]
3587 );
3588 }
3589
3590 zfPrintTargetPower2G(hpPriv->tPow2xCck,
3591 hpPriv->tPow2x2g,
3592 hpPriv->tPow2x2gHt20,
3593 hpPriv->tPow2x2gHt40);
3594 }
3595 else
3596 {
3597 /* 5G */
3598 for (i=0; i<8; i++)
3599 {
3600 if (eepromImage->calTargetPower5G[i].bChannel != 0xff)
3601 {
3602 fbinArray[i] = eepromImage->calTargetPower5G[i].bChannel;
3603 }
3604 else
3605 {
3606 break;
3607 }
3608
3609 }
3610 index = zfFindFreqIndex(fbin, fbinArray, i);
3611 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3612 DbgPrint("5G index=%d\n", index);
3613 #endif
3614 for (i=0; i<4; i++)
3615 {
3616 hpPriv->tPow2x5g[i] = zfInterpolateFuncX(fbin,
3617 eepromImage->calTargetPower5G[index].bChannel,
3618 eepromImage->calTargetPower5G[index].tPow2x[i],
3619 eepromImage->calTargetPower5G[index+1].bChannel,
3620 eepromImage->calTargetPower5G[index+1].tPow2x[i]
3621 );
3622 }
3623
3624 for (i=0; i<8; i++)
3625 {
3626 if (eepromImage->calTargetPower5GHT20[i].bChannel != 0xff)
3627 {
3628 fbinArray[i] = eepromImage->calTargetPower5GHT20[i].bChannel;
3629 }
3630 else
3631 {
3632 break;
3633 }
3634
3635 }
3636 index = zfFindFreqIndex(fbin, fbinArray, i);
3637 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3638 DbgPrint("5G HT20 index=%d\n", index);
3639 #endif
3640 for (i=0; i<8; i++)
3641 {
3642 hpPriv->tPow2x5gHt20[i] = zfInterpolateFuncX(fbin,
3643 eepromImage->calTargetPower5GHT20[index].bChannel,
3644 eepromImage->calTargetPower5GHT20[index].tPow2x[i],
3645 eepromImage->calTargetPower5GHT20[index+1].bChannel,
3646 eepromImage->calTargetPower5GHT20[index+1].tPow2x[i]
3647 );
3648 }
3649
3650 for (i=0; i<8; i++)
3651 {
3652 if (eepromImage->calTargetPower5GHT40[i].bChannel != 0xff)
3653 {
3654 fbinArray[i] = eepromImage->calTargetPower5GHT40[i].bChannel;
3655 }
3656 else
3657 {
3658 break;
3659 }
3660
3661 }
3662 index = zfFindFreqIndex((u8_t)zfAdjustHT40FreqOffset(dev, fbin, bw40, extOffset), fbinArray, i);
3663 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3664 DbgPrint("5G HT40 index=%d\n", index);
3665 #endif
3666 for (i=0; i<8; i++)
3667 {
3668 hpPriv->tPow2x5gHt40[i] = zfInterpolateFuncX(
3669 (u8_t)zfAdjustHT40FreqOffset(dev, fbin, bw40, extOffset),
3670 eepromImage->calTargetPower5GHT40[index].bChannel,
3671 eepromImage->calTargetPower5GHT40[index].tPow2x[i],
3672 eepromImage->calTargetPower5GHT40[index+1].bChannel,
3673 eepromImage->calTargetPower5GHT40[index+1].tPow2x[i]
3674 );
3675 }
3676
3677 zfPrintTargetPower5G(
3678 hpPriv->tPow2x5g,
3679 hpPriv->tPow2x5gHt20,
3680 hpPriv->tPow2x5gHt40);
3681 }
3682
3683
3684
3685 /* 4. CTL */
3686 /*
3687 * 4.1 Get the bandedges tx power by frequency
3688 * 2.4G we get ctlEdgesMaxPowerCCK
3689 * ctlEdgesMaxPower2G
3690 * ctlEdgesMaxPower2GHT20
3691 * ctlEdgesMaxPower2GHT40
3692 * 5G we get ctlEdgesMaxPower5G
3693 * ctlEdgesMaxPower5GHT20
3694 * ctlEdgesMaxPower5GHT40
3695 * 4.2 Update (3.) target power table by 4.1
3696 * 4.3 Tx power offset for ART - NDIS/MDK
3697 * 4.4 Write MAC reg 0x694 for ACK's TPC
3698 *
3699 */
3700
3701 //zfDumpEepBandEdges(eepromImage);
3702
3703 /* get the cfg from Eeprom: regionCode => RegulatoryDomain : 0x10-FFC 0x30-eu 0x40-jap */
3704 desired_CtlIndex = zfHpGetRegulatoryDomain(dev);
3705 if ((desired_CtlIndex == 0x30) || (desired_CtlIndex == 0x40) || (desired_CtlIndex == 0x0))
3706 {
3707 /* skip CTL and heavy clip */
3708 hpPriv->enableBBHeavyClip = 0;
3709 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3710 zm_dbg(("RegulatoryDomain = 0, skip CTL and heavy clip\n"));
3711 #endif
3712 }
3713 else
3714 {
3715 hpPriv->enableBBHeavyClip = 1;
3716
3717 if (desired_CtlIndex == 0xff)
3718 {
3719 /* desired index not found */
3720 desired_CtlIndex = 0x10;
3721 }
3722
3723 /* first part : 2.4G */
3724 if (frequency <= ZM_CH_G_14)
3725 {
3726 /* 2.4G - CTL_11B */
3727 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_11B);
3728 if(ctl_i<AR5416_NUM_CTLS)
3729 {
3730 ctlEdgesMaxPowerCCK = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], frequency);
3731 }
3732 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3733 zm_dbg(("CTL_11B ctl_i = %d\n", ctl_i));
3734 #endif
3735
3736 /* 2.4G - CTL_11G */
3737 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_11G);
3738 if(ctl_i<AR5416_NUM_CTLS)
3739 {
3740 ctlEdgesMaxPower2G = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], frequency);
3741 }
3742 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3743 zm_dbg(("CTL_11G ctl_i = %d\n", ctl_i));
3744 #endif
3745
3746 /* 2.4G - CTL_2GHT20 */
3747 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_2GHT20);
3748 if(ctl_i<AR5416_NUM_CTLS)
3749 {
3750 ctlEdgesMaxPower2GHT20 = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], frequency);
3751 }
3752 else
3753 {
3754 /* workaround for no data in Eeprom, replace by normal 2G */
3755 ctlEdgesMaxPower2GHT20 = ctlEdgesMaxPower2G;
3756 }
3757 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3758 zm_dbg(("CTL_2GHT20 ctl_i = %d\n", ctl_i));
3759 #endif
3760
3761 /* 2.4G - CTL_2GHT40 */
3762 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_2GHT40);
3763 if(ctl_i<AR5416_NUM_CTLS)
3764 {
3765 ctlEdgesMaxPower2GHT40 = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1],
3766 zfAdjustHT40FreqOffset(dev, frequency, bw40, extOffset));
3767 }
3768 else
3769 {
3770 /* workaround for no data in Eeprom, replace by normal 2G */
3771 ctlEdgesMaxPower2GHT40 = ctlEdgesMaxPower2G;
3772 }
3773 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3774 zm_dbg(("CTL_2GHT40 ctl_i = %d\n", ctl_i));
3775 #endif
3776
3777
3778 /* 7a17 : */
3779 /* Max power (dBm) for channel range when using DFS define by madwifi*/
3780 for (i=0; i<wd->regulationTable.allowChannelCnt; i++)
3781 {
3782 if (wd->regulationTable.allowChannel[i].channel == frequency)
3783 {
3784 if (zfHpIsDfsChannel(dev, (u16_t)frequency))
3785 {
3786 zm_debug_msg1("frequency use DFS -- ", frequency);
3787 ctlEdgesMaxPowerCCK = zm_min(ctlEdgesMaxPowerCCK, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3788 ctlEdgesMaxPower2G = zm_min(ctlEdgesMaxPower2G, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3789 ctlEdgesMaxPower2GHT20 = zm_min(ctlEdgesMaxPower2GHT20, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3790 ctlEdgesMaxPower2GHT40 = zm_min(ctlEdgesMaxPower2GHT40, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3791 }
3792 break;
3793 }
3794 }
3795
3796 /* Apply ctl mode to correct target power set */
3797 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3798 zm_debug_msg1("ctlEdgesMaxPowerCCK = ", ctlEdgesMaxPowerCCK);
3799 zm_debug_msg1("ctlEdgesMaxPower2G = ", ctlEdgesMaxPower2G);
3800 zm_debug_msg1("ctlEdgesMaxPower2GHT20 = ", ctlEdgesMaxPower2GHT20);
3801 zm_debug_msg1("ctlEdgesMaxPower2GHT40 = ", ctlEdgesMaxPower2GHT40);
3802 #endif
3803 for (i=0; i<4; i++)
3804 {
3805 hpPriv->tPow2xCck[i] = zm_min(hpPriv->tPow2xCck[i], ctlEdgesMaxPowerCCK) + HALTX_POWER_OFFSET;
3806 }
3807 hpPriv->tPow2x2g24HeavyClipOffset = 0;
3808 if (hpPriv->enableBBHeavyClip)
3809 {
3810 ctlOffset = 2;
3811 }
3812 else
3813 {
3814 ctlOffset = 0;
3815 }
3816 for (i=0; i<4; i++)
3817 {
3818 if (((frequency == 2412) || (frequency == 2462)))
3819 {
3820 if (i != 0)
3821 {
3822 hpPriv->tPow2x2g[i] = zm_min(hpPriv->tPow2x2g[i], ctlEdgesMaxPower2G-ctlOffset) + HALTX_POWER_OFFSET;
3823 }
3824 else
3825 {
3826 hpPriv->tPow2x2g[i] = zm_min(hpPriv->tPow2x2g[i], ctlEdgesMaxPower2G) + HALTX_POWER_OFFSET;
3827 if (hpPriv->tPow2x2g[i] > (ctlEdgesMaxPower2G-ctlOffset))
3828 {
3829 hpPriv->tPow2x2g24HeavyClipOffset = hpPriv->tPow2x2g[i] - (ctlEdgesMaxPower2G-ctlOffset);
3830 }
3831 }
3832 }
3833 else
3834 {
3835 hpPriv->tPow2x2g[i] = zm_min(hpPriv->tPow2x2g[i], ctlEdgesMaxPower2G) + HALTX_POWER_OFFSET;
3836 }
3837 }
3838 for (i=0; i<8; i++)
3839 {
3840 if (((frequency == 2412) || (frequency == 2462)) && (i>=3))
3841 {
3842 hpPriv->tPow2x2gHt20[i] = zm_min(hpPriv->tPow2x2gHt20[i], ctlEdgesMaxPower2GHT20-ctlOffset) + HALTX_POWER_OFFSET;
3843 }
3844 else
3845 {
3846 hpPriv->tPow2x2gHt20[i] = zm_min(hpPriv->tPow2x2gHt20[i], ctlEdgesMaxPower2GHT20) + HALTX_POWER_OFFSET;
3847 }
3848 }
3849 for (i=0; i<8; i++)
3850 {
3851 if ((frequency == 2412) && (i>=3))
3852 {
3853 hpPriv->tPow2x2gHt40[i] = zm_min(hpPriv->tPow2x2gHt40[i], ctlEdgesMaxPower2GHT40-ctlOffset) + HALTX_POWER_OFFSET;
3854 }
3855 else if ((frequency == 2462) && (i>=3))
3856 {
3857 hpPriv->tPow2x2gHt40[i] = zm_min(hpPriv->tPow2x2gHt40[i], ctlEdgesMaxPower2GHT40-(ctlOffset*2)) + HALTX_POWER_OFFSET;
3858 }
3859 else
3860 {
3861 hpPriv->tPow2x2gHt40[i] = zm_min(hpPriv->tPow2x2gHt40[i], ctlEdgesMaxPower2GHT40) + HALTX_POWER_OFFSET;
3862 }
3863 }
3864 }
3865 else
3866 {
3867 /* 5G - CTL_11A */
3868 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_11A);
3869 if(ctl_i<AR5416_NUM_CTLS)
3870 {
3871 ctlEdgesMaxPower5G = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], frequency);
3872 }
3873 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3874 zm_dbg(("CTL_11A ctl_i = %d\n", ctl_i));
3875 #endif
3876
3877 /* 5G - CTL_5GHT20 */
3878 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_5GHT20);
3879 if(ctl_i<AR5416_NUM_CTLS)
3880 {
3881 ctlEdgesMaxPower5GHT20 = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], frequency);
3882 }
3883 else
3884 {
3885 /* workaround for no data in Eeprom, replace by normal 5G */
3886 ctlEdgesMaxPower5GHT20 = ctlEdgesMaxPower5G;
3887 }
3888 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3889 zm_dbg(("CTL_5GHT20 ctl_i = %d\n", ctl_i));
3890 #endif
3891
3892 /* 5G - CTL_5GHT40 */
3893 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_5GHT40);
3894 if(ctl_i<AR5416_NUM_CTLS)
3895 {
3896 ctlEdgesMaxPower5GHT40 = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1],
3897 zfAdjustHT40FreqOffset(dev, frequency, bw40, extOffset));
3898 }
3899 else
3900 {
3901 /* workaround for no data in Eeprom, replace by normal 5G */
3902 ctlEdgesMaxPower5GHT40 = ctlEdgesMaxPower5G;
3903 }
3904 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3905 zm_dbg(("CTL_5GHT40 ctl_i = %d\n", ctl_i));
3906 #endif
3907
3908 /* 7a17 : */
3909 /* Max power (dBm) for channel range when using DFS define by madwifi*/
3910 for (i=0; i<wd->regulationTable.allowChannelCnt; i++)
3911 {
3912 if (wd->regulationTable.allowChannel[i].channel == frequency)
3913 {
3914 if (zfHpIsDfsChannel(dev, (u16_t)frequency))
3915 {
3916 zm_debug_msg1("frequency use DFS -- ", frequency);
3917 ctlEdgesMaxPower5G = zm_min(ctlEdgesMaxPower5G, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3918 ctlEdgesMaxPower5GHT20 = zm_min(ctlEdgesMaxPower5GHT20, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3919 ctlEdgesMaxPower5GHT40 = zm_min(ctlEdgesMaxPower5GHT40, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3920 }
3921 break;
3922 }
3923 }
3924
3925
3926 /* Apply ctl mode to correct target power set */
3927 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3928 zm_debug_msg1("ctlEdgesMaxPower5G = ", ctlEdgesMaxPower5G);
3929 zm_debug_msg1("ctlEdgesMaxPower5GHT20 = ", ctlEdgesMaxPower5GHT20);
3930 zm_debug_msg1("ctlEdgesMaxPower5GHT40 = ", ctlEdgesMaxPower5GHT40);
3931 #endif
3932 for (i=0; i<4; i++)
3933 {
3934 hpPriv->tPow2x5g[i] = zm_min(hpPriv->tPow2x5g[i], ctlEdgesMaxPower5G) + HALTX_POWER_OFFSET;
3935 }
3936 for (i=0; i<8; i++)
3937 {
3938 hpPriv->tPow2x5gHt20[i] = zm_min(hpPriv->tPow2x5gHt20[i], ctlEdgesMaxPower5GHT20) + HALTX_POWER_OFFSET;
3939 }
3940 for (i=0; i<8; i++)
3941 {
3942 hpPriv->tPow2x5gHt40[i] = zm_min(hpPriv->tPow2x5gHt40[i], ctlEdgesMaxPower5GHT40) + HALTX_POWER_OFFSET;
3943 }
3944
3945 }/* end of bandedges of 5G */
3946 }/* end of if ((desired_CtlIndex = zfHpGetRegulatoryDomain(dev)) == 0) */
3947
3948 /* workaround */
3949 /* 5. BB heavy clip */
3950 /* only 2.4G do heavy clip */
3951 if (hpPriv->enableBBHeavyClip && hpPriv->hwBBHeavyClip && (frequency <= ZM_CH_G_14))
3952 {
3953 if (frequency <= ZM_CH_G_14)
3954 {
3955 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_11G);
3956 }
3957 else
3958 {
3959 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_11A);
3960 }
3961
3962 hpPriv->setValueHeavyClip = zfHpCheckDoHeavyClip(dev, frequency, eepromImage->ctlData[ctl_i].ctlEdges[1], bw40);
3963
3964 if (hpPriv->setValueHeavyClip)
3965 {
3966 hpPriv->doBBHeavyClip = 1;
3967 }
3968 else
3969 {
3970 hpPriv->doBBHeavyClip = 0;
3971 }
3972 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3973 zm_dbg(("zfHpCheckDoHeavyClip ret = %02x, doBBHeavyClip = %d\n",
3974 hpPriv->setValueHeavyClip, hpPriv->doBBHeavyClip));
3975 #endif
3976
3977 if (hpPriv->doBBHeavyClip)
3978 {
3979 if (hpPriv->setValueHeavyClip & 0xf0)
3980 {
3981 hpPriv->tPow2x2gHt40[0] -= 1;
3982 hpPriv->tPow2x2gHt40[1] -= 1;
3983 hpPriv->tPow2x2gHt40[2] -= 1;
3984 }
3985
3986 if (hpPriv->setValueHeavyClip & 0xf)
3987 {
3988 hpPriv->tPow2x2gHt20[0] += 1;
3989 hpPriv->tPow2x2gHt20[1] += 1;
3990 hpPriv->tPow2x2gHt20[2] += 1;
3991 }
3992 }
3993 }
3994 else
3995 {
3996 hpPriv->doBBHeavyClip = 0;
3997 hpPriv->setValueHeavyClip = 0;
3998 }
3999
4000 /* Final : write MAC register for some ctrl frame Tx power */
4001 /* first part : 2.4G */
4002 if (frequency <= ZM_CH_G_14)
4003 {
4004 /* Write MAC reg 0x694 for ACK's TPC */
4005 /* Write MAC reg 0xbb4 RTS and SF-CTS frame power control */
4006 /* Always use two stream for low legacy rate */
4007 #if 0
4008 //if (hpPriv->halCapability & ZM_HP_CAP_11N_ONE_TX_STREAM)
4009 //{
4010 zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->tPow2x2g[0]&0x3f) << 20) | (0x1<<26));
4011 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->tPow2x2g[0]&0x3f) << 5 ) | (0x1<<11) |
4012 ((hpPriv->tPow2x2g[0]&0x3f) << 21) | (0x1<<27) );
4013 //}
4014 #endif
4015 #if 1
4016 //else
4017 {
4018 #ifndef ZM_OTUS_LINUX_PHASE_2
4019 zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->tPow2x2g[0]&0x3f) << 20) | (0x5<<26));
4020 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->tPow2x2g[0]&0x3f) << 5 ) | (0x5<<11) |
4021 ((hpPriv->tPow2x2g[0]&0x3f) << 21) | (0x5<<27) );
4022 #endif
4023 hpPriv->currentAckRtsTpc = hpPriv->tPow2x2g[0];
4024 }
4025 #endif
4026 zfFlushDelayWrite(dev);
4027
4028 zfPrintTargetPower2G(hpPriv->tPow2xCck,
4029 hpPriv->tPow2x2g,
4030 hpPriv->tPow2x2gHt20,
4031 hpPriv->tPow2x2gHt40);
4032 }
4033 else
4034 {
4035 /* Write MAC reg 0x694 for ACK's TPC */
4036 /* Write MAC reg 0xbb4 RTS and SF-CTS frame power control */
4037 /* Always use two stream for low legacy rate */
4038 if (hpPriv->halCapability & ZM_HP_CAP_11N_ONE_TX_STREAM)
4039 {
4040 #ifndef ZM_OTUS_LINUX_PHASE_2
4041 zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->tPow2x5g[0]&0x3f) << 20) | (0x1<<26));
4042 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->tPow2x5g[0]&0x3f) << 5 ) | (0x1<<11) |
4043 ((hpPriv->tPow2x5g[0]&0x3f) << 21) | (0x1<<27) );
4044 #endif
4045 }
4046 else
4047 {
4048 #ifndef ZM_OTUS_LINUX_PHASE_2
4049 zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->tPow2x5g[0]&0x3f) << 20) | (0x5<<26));
4050 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->tPow2x5g[0]&0x3f) << 5 ) | (0x5<<11) |
4051 ((hpPriv->tPow2x5g[0]&0x3f) << 21) | (0x5<<27) );
4052 #endif
4053 hpPriv->currentAckRtsTpc = hpPriv->tPow2x2g[0];
4054 }
4055
4056
4057 zfFlushDelayWrite(dev);
4058
4059 zfPrintTargetPower5G(
4060 hpPriv->tPow2x5g,
4061 hpPriv->tPow2x5gHt20,
4062 hpPriv->tPow2x5gHt40);
4063 }/* end of bandedges of 5G */
4064
4065 }
4066
4067 void zfDumpEepBandEdges(struct ar5416Eeprom* eepromImage)
4068 {
4069 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
4070 u8_t i, j, k;
4071
4072 #if 0
4073 zm_dbg(("\n === BandEdges index dump ==== \n"));
4074
4075 for (i = 0; i < AR5416_NUM_CTLS; i++)
4076 {
4077 zm_dbg(("%02x ", eepromImage->ctlIndex[i]));
4078 }
4079
4080 zm_dbg(("\n === BandEdges data dump ==== \n"));
4081
4082 for (i = 0; i < AR5416_NUM_CTLS; i++)
4083 {
4084 for (j = 0; j < 2; j++)
4085 {
4086 for(k = 0; k < AR5416_NUM_BAND_EDGES; k++)
4087 {
4088 u8_t *pdata = (u8_t*)&(eepromImage->ctlData[i].ctlEdges[j][k]);
4089 zm_dbg(("(%02x %02x)", pdata[0], pdata[1]));
4090 }
4091 zm_dbg(("\n"));
4092 }
4093 }
4094 #else
4095 zm_dbg(("\n === BandEdges index dump ==== \n"));
4096 for (i = 0; i < 24; i+=8)
4097 {
4098 zm_dbg(("%02x %02x %02x %02x %02x %02x %02x %02x",
4099 eepromImage->ctlIndex[i+0], eepromImage->ctlIndex[i+1], eepromImage->ctlIndex[i+2], eepromImage->ctlIndex[i+3],
4100 eepromImage->ctlIndex[i+4], eepromImage->ctlIndex[i+5], eepromImage->ctlIndex[i+6], eepromImage->ctlIndex[i+7]
4101 ));
4102 }
4103
4104 zm_dbg(("\n === BandEdges data dump ==== \n"));
4105
4106 for (i = 0; i < AR5416_NUM_CTLS; i++)
4107 {
4108 for (j = 0; j < 2; j++)
4109 {
4110 u8_t *pdata = (u8_t*)&(eepromImage->ctlData[i].ctlEdges[j]);
4111 zm_dbg(("(%03d %02x) (%03d %02x) (%03d %02x) (%03d %02x) \n",
4112 pdata[0], pdata[1], pdata[2], pdata[3],
4113 pdata[4], pdata[5], pdata[6], pdata[7]
4114 ));
4115 zm_dbg(("(%03d %02x) (%03d %02x) (%03d %02x) (%03d %02x) \n",
4116 pdata[8], pdata[9], pdata[10], pdata[11],
4117 pdata[12], pdata[13], pdata[14], pdata[15]
4118 ));
4119 }
4120 }
4121 #endif
4122 #endif
4123 }
4124
4125 void zfPrintTargetPower2G(u8_t* tPow2xCck, u8_t* tPow2x2g, u8_t* tPow2x2gHt20, u8_t* tPow2x2gHt40)
4126 {
4127 //#ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
4128 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
4129 DbgPrint("targetPwr CCK : %d, %d, %d, %d\n",
4130 tPow2xCck[0],
4131 tPow2xCck[1],
4132 tPow2xCck[2],
4133 tPow2xCck[3]
4134 );
4135 DbgPrint("targetPwr 2G : %d, %d, %d, %d\n",
4136 tPow2x2g[0],
4137 tPow2x2g[1],
4138 tPow2x2g[2],
4139 tPow2x2g[3]
4140 );
4141 DbgPrint("targetPwr 2GHT20 : %d, %d, %d, %d, %d, %d, %d, %d\n",
4142 tPow2x2gHt20[0],
4143 tPow2x2gHt20[1],
4144 tPow2x2gHt20[2],
4145 tPow2x2gHt20[3],
4146 tPow2x2gHt20[4],
4147 tPow2x2gHt20[5],
4148 tPow2x2gHt20[6],
4149 tPow2x2gHt20[7]
4150 );
4151 DbgPrint("targetPwr 2GHT40 : %d, %d, %d, %d, %d, %d, %d, %d\n",
4152 tPow2x2gHt40[0],
4153 tPow2x2gHt40[1],
4154 tPow2x2gHt40[2],
4155 tPow2x2gHt40[3],
4156 tPow2x2gHt40[4],
4157 tPow2x2gHt40[5],
4158 tPow2x2gHt40[6],
4159 tPow2x2gHt40[7]
4160 );
4161 #endif
4162 return;
4163 }
4164
4165 void zfPrintTargetPower5G(u8_t* tPow2x5g, u8_t* tPow2x5gHt20, u8_t* tPow2x5gHt40)
4166 {
4167 //#ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
4168 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
4169 DbgPrint("targetPwr 5G : %d, %d, %d, %d\n",
4170 tPow2x5g[0],
4171 tPow2x5g[1],
4172 tPow2x5g[2],
4173 tPow2x5g[3]
4174 );
4175 DbgPrint("targetPwr 5GHT20 : %d, %d, %d, %d, %d, %d, %d, %d\n",
4176 tPow2x5gHt20[0],
4177 tPow2x5gHt20[1],
4178 tPow2x5gHt20[2],
4179 tPow2x5gHt20[3],
4180 tPow2x5gHt20[4],
4181 tPow2x5gHt20[5],
4182 tPow2x5gHt20[6],
4183 tPow2x5gHt20[7]
4184 );
4185 DbgPrint("targetPwr 5GHT40 : %d, %d, %d, %d, %d, %d, %d, %d\n",
4186 tPow2x5gHt40[0],
4187 tPow2x5gHt40[1],
4188 tPow2x5gHt40[2],
4189 tPow2x5gHt40[3],
4190 tPow2x5gHt40[4],
4191 tPow2x5gHt40[5],
4192 tPow2x5gHt40[6],
4193 tPow2x5gHt40[7]
4194 );
4195 #endif
4196 return;
4197 }
4198
4199 void zfHpPowerSaveSetMode(zdev_t* dev, u8_t staMode, u8_t psMode, u16_t bcnInterval)
4200 {
4201 if ( staMode == 0 )
4202 {
4203 if ( psMode == 0 )
4204 {
4205 // Turn off pre-TBTT interrupt
4206 zfDelayWriteInternalReg(dev, ZM_MAC_REG_PRETBTT, 0);
4207 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, 0);
4208 zfFlushDelayWrite(dev);
4209 }
4210 else
4211 {
4212 // Turn on pre-TBTT interrupt
4213 zfDelayWriteInternalReg(dev, ZM_MAC_REG_PRETBTT, (bcnInterval-6)<<16);
4214 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, bcnInterval);
4215 zfFlushDelayWrite(dev);
4216 }
4217 }
4218 }
4219
4220 void zfHpPowerSaveSetState(zdev_t* dev, u8_t psState)
4221 {
4222 zmw_get_wlan_dev(dev);
4223 struct zsHpPriv* hpPriv = wd->hpPrivate;
4224
4225 //DbgPrint("INTO zfHpPowerSaveSetState");
4226
4227 if ( psState == 0 ) //power up
4228 {
4229 //DbgPrint("zfHpPowerSaveSetState Wake up from PS\n");
4230 reg_write(0x982C, 0x0000a000); //wake up ADDAC
4231 reg_write(0x9808, 0x0); //enable all agc gain and offset updates to a2
4232 //# bank 3
4233 if (((struct zsHpPriv*)wd->hpPrivate)->hwFrequency <= ZM_CH_G_14)
4234 {
4235 /* 11g */
4236 //reg_write (0x98f0, 0x01c00018);
4237 reg_write (0x98f0, 0x01c20098);//syn_on+RX_ON
4238 }
4239 else
4240 {
4241 /* 11a */
4242 //reg_write (0x98f0, 0x01400018);
4243 reg_write (0x98f0, 0x01420098);//syn_on+RX_ON
4244 }
4245
4246 ////#bank 5
4247 //reg_write(0x98b0, 0x00000013);
4248 //reg_write(0x98e4, 0x00000002);
4249
4250
4251 zfFlushDelayWrite(dev);
4252 }
4253 else //power down
4254 {
4255 //DbgPrint("zfHpPowerSaveSetState Go to PS\n");
4256 //reg_write(0x982C, 0xa000a000);
4257 reg_write(0x9808, 0x8000000); //disable all agc gain and offset updates to a2
4258 reg_write(0x982C, 0xa000a000); //power down ADDAC
4259 //# bank 3
4260 if (((struct zsHpPriv*)wd->hpPrivate)->hwFrequency <= ZM_CH_G_14)
4261 {
4262 /* 11g */
4263 reg_write (0x98f0, 0x00c00018);//syn_off+RX_off
4264 }
4265 else
4266 {
4267 /* 11a */
4268 reg_write (0x98f0, 0x00400018);//syn_off+RX_off
4269 }
4270
4271 ////#bank 5
4272 //reg_write(0x98b0, 0x000e0013);
4273 //reg_write(0x98e4, 0x00018002);
4274
4275
4276 zfFlushDelayWrite(dev);
4277 }
4278 }
4279
4280 void zfHpSetAggPktNum(zdev_t* dev, u32_t num)
4281 {
4282 zmw_get_wlan_dev(dev);
4283 struct zsHpPriv* hpPriv = wd->hpPrivate;
4284
4285 num = (num << 16) | (0xa);
4286
4287 hpPriv->aggPktNum = num;
4288
4289 //aggregation number will be update in HAL heart beat
4290 //zfDelayWriteInternalReg(dev, 0x1c3b9c, num);
4291 //zfFlushDelayWrite(dev);
4292 }
4293
4294 void zfHpSetMPDUDensity(zdev_t* dev, u8_t density)
4295 {
4296 u32_t value;
4297
4298 if (density > ZM_MPDU_DENSITY_8US)
4299 {
4300 return;
4301 }
4302
4303 /* Default value in this register */
4304 value = 0x140A00 | density;
4305
4306 zfDelayWriteInternalReg(dev, 0x1c3ba0, value);
4307 zfFlushDelayWrite(dev);
4308 return;
4309 }
4310
4311 void zfHpSetSlotTime(zdev_t* dev, u8_t type)
4312 {
4313 zmw_get_wlan_dev(dev);
4314 struct zsHpPriv* hpPriv = wd->hpPrivate;
4315
4316 if (type == 0)
4317 {
4318 //normal slot = 20us
4319 hpPriv->slotType = 0;
4320 }
4321 else //if (type == 1)
4322 {
4323 //short slot = 9us
4324 hpPriv->slotType = 1;
4325 }
4326
4327 return;
4328 }
4329
4330 void zfHpSetSlotTimeRegister(zdev_t* dev, u8_t type)
4331 {
4332 if(type == 0)
4333 {
4334 //normal slot = 20us
4335 zfDelayWriteInternalReg(dev, ZM_MAC_REG_SLOT_TIME, 20<<10);
4336 }
4337 else
4338 {
4339 //short slot = 9us
4340 zfDelayWriteInternalReg(dev, ZM_MAC_REG_SLOT_TIME, 9<<10);
4341 }
4342 }
4343
4344 void zfHpSetRifs(zdev_t* dev, u8_t ht_enable, u8_t ht2040, u8_t g_mode)
4345 {
4346 zfDelayWriteInternalReg(dev, 0x1c6388, 0x0c000000);
4347
4348 zfDelayWriteInternalReg(dev, 0x1c59ec, 0x0cc80caa);
4349
4350 if (ht_enable)
4351 {
4352 if (ht2040)
4353 {
4354 zfDelayWriteInternalReg(dev, 0x1c5918, 40);
4355 }
4356 else
4357 {
4358 zfDelayWriteInternalReg(dev, 0x1c5918, 20);
4359 }
4360 }
4361
4362 if (g_mode)
4363 {
4364 zfDelayWriteInternalReg(dev, 0x1c5850, 0xec08b4e2);
4365 zfDelayWriteInternalReg(dev, 0x1c585c, 0x313a5d5e);
4366 }
4367 else
4368 {
4369 zfDelayWriteInternalReg(dev, 0x1c5850, 0xede8b4e0);
4370 zfDelayWriteInternalReg(dev, 0x1c585c, 0x3139605e);
4371 }
4372
4373 zfFlushDelayWrite(dev);
4374 return;
4375 }
4376
4377 void zfHpBeginSiteSurvey(zdev_t* dev, u8_t status)
4378 {
4379 zmw_get_wlan_dev(dev);
4380 struct zsHpPriv* hpPriv=wd->hpPrivate;
4381
4382 if ( status == 1 )
4383 { // Connected
4384 hpPriv->isSiteSurvey = 1;
4385 }
4386 else
4387 { // Not connected
4388 hpPriv->isSiteSurvey = 0;
4389 }
4390
4391 /* reset workaround state to default */
4392 // if (hpPriv->rxStrongRSSI == 1)
4393 {
4394 hpPriv->rxStrongRSSI = 0;
4395 if ((hpPriv->eepromImage[0x100+0x110*2/4]&0xff) == 0x80) //FEM TYPE
4396 {
4397 if (hpPriv->hwFrequency <= ZM_CH_G_14)
4398 {
4399 zfDelayWriteInternalReg(dev, 0x1c8960, 0x9b49);
4400 }
4401 else
4402 {
4403 zfDelayWriteInternalReg(dev, 0x1c8960, 0x0900);
4404 }
4405 }
4406 else
4407 {
4408 zfDelayWriteInternalReg(dev, 0x1c8960, 0x9b40);
4409 }
4410 zfFlushDelayWrite(dev);
4411 }
4412 // if (hpPriv->strongRSSI == 1)
4413 {
4414 hpPriv->strongRSSI = 0;
4415 zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->currentAckRtsTpc&0x3f) << 20) | (0x5<<26));
4416 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->currentAckRtsTpc&0x3f) << 5 ) | (0x5<<11) |
4417 ((hpPriv->currentAckRtsTpc&0x3f) << 21) | (0x5<<27) );
4418 zfFlushDelayWrite(dev);
4419 }
4420 }
4421
4422 void zfHpFinishSiteSurvey(zdev_t* dev, u8_t status)
4423 {
4424 zmw_get_wlan_dev(dev);
4425 struct zsHpPriv* hpPriv=wd->hpPrivate;
4426
4427 zmw_declare_for_critical_section();
4428
4429 zmw_enter_critical_section(dev);
4430 if ( status == 1 )
4431 {
4432 hpPriv->isSiteSurvey = 2;
4433 }
4434 else
4435 {
4436 hpPriv->isSiteSurvey = 0;
4437 }
4438 zmw_leave_critical_section(dev);
4439 }
4440
4441 u16_t zfFwRetry(zdev_t* dev, u8_t enable)
4442 {
4443 u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
4444 u16_t ret = 0;
4445
4446 cmd[0] = 4 | (0x92 << 8);
4447 cmd[1] = (enable == 1) ? 0x01 : 0x00;
4448
4449 ret = zfIssueCmd(dev, cmd, 8, ZM_OID_INTERNAL_WRITE, NULL);
4450 return ret;
4451 }
4452
4453 u16_t zfHpEnableHwRetry(zdev_t* dev)
4454 {
4455 u16_t ret;
4456
4457 ret = zfFwRetry(dev, 0);
4458
4459 zfDelayWriteInternalReg(dev, 0x1c3b28, 0x33333);
4460 zfFlushDelayWrite(dev);
4461
4462 return ret;
4463 }
4464
4465 u16_t zfHpDisableHwRetry(zdev_t* dev)
4466 {
4467 u16_t ret;
4468
4469 ret = zfFwRetry(dev, 1);
4470
4471 zfDelayWriteInternalReg(dev, 0x1c3b28, 0x00000);
4472 zfFlushDelayWrite(dev);
4473
4474 return ret;
4475 }
4476
4477 /* Download SPI Fw */
4478 #define ZM_FIRMWARE_WLAN 0
4479 #define ZM_FIRMWARE_SPI_FLASH 1
4480
4481
4482 u16_t zfHpFirmwareDownload(zdev_t* dev, u8_t fwType)
4483 {
4484 u16_t ret = ZM_SUCCESS;
4485
4486 if (fwType == ZM_FIRMWARE_WLAN)
4487 {
4488 ret = zfFirmwareDownload(dev, (u32_t*)zcFwImage,
4489 (u32_t)zcFwImageSize, ZM_FIRMWARE_WLAN_ADDR);
4490 }
4491 else if (fwType == ZM_FIRMWARE_SPI_FLASH)
4492 {
4493 ret = zfFirmwareDownload(dev, (u32_t*)zcFwImageSPI,
4494 (u32_t)zcFwImageSPISize, ZM_FIRMWARE_SPI_ADDR);
4495 }
4496 else
4497 {
4498 zm_debug_msg1("Unknown firmware type = ", fwType);
4499 ret = ZM_ERR_FIRMWARE_WRONG_TYPE;
4500 }
4501
4502 return ret;
4503 }
4504
4505 /* Enable software decryption */
4506 void zfHpSWDecrypt(zdev_t* dev, u8_t enable)
4507 {
4508 u32_t value = 0x70;
4509
4510 /* Bit 4 for enable software decryption */
4511 if (enable == 1)
4512 {
4513 value = 0x78;
4514 }
4515
4516 zfDelayWriteInternalReg(dev, 0x1c3678, value);
4517 zfFlushDelayWrite(dev);
4518 }
4519
4520 /* Enable software encryption */
4521 void zfHpSWEncrypt(zdev_t* dev, u8_t enable)
4522 {
4523 /* Because encryption by software or hardware is judged by driver in Otus,
4524 we don't need to do anything in the HAL layer.
4525 */
4526 }
4527
4528 u32_t zfHpCapability(zdev_t* dev)
4529 {
4530 zmw_get_wlan_dev(dev);
4531 struct zsHpPriv* hpPriv=wd->hpPrivate;
4532
4533 return hpPriv->halCapability;
4534 }
4535
4536 void zfHpSetRollCallTable(zdev_t* dev)
4537 {
4538 zmw_get_wlan_dev(dev);
4539 struct zsHpPriv* hpPriv=wd->hpPrivate;
4540
4541 if (hpPriv->camRollCallTable != (u64_t) 0)
4542 {
4543 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ROLL_CALL_TBL_L, (u32_t)(hpPriv->camRollCallTable & 0xffffffff));
4544 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ROLL_CALL_TBL_H, (u32_t)((hpPriv->camRollCallTable >> 32) & 0xffffffff));
4545 zfFlushDelayWrite(dev);
4546 }
4547 }
4548
4549 void zfHpSetTTSIFSTime(zdev_t* dev, u8_t sifs_time)
4550 {
4551 u32_t reg_value = 0;
4552 zmw_get_wlan_dev(dev);
4553
4554 sifs_time &= 0x3f;
4555 reg_value = 0x14400b | (((u32_t)sifs_time)<<24);
4556
4557 zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, reg_value);
4558 zfFlushDelayWrite(dev);
4559 }
4560
4561 /* #3 Enable RIFS function if the RIFS pattern matched ! */
4562 void zfHpEnableRifs(zdev_t* dev, u8_t mode24g, u8_t modeHt, u8_t modeHt2040)
4563 {
4564
4565 /* # Enable Reset TDOMAIN
4566 * $rddata = &$phyreg_read(0x9800+(738<<2));
4567 * $wrdata = $rddata | (0x1 << 26) | (0x1 << 27);
4568 * &$phyreg_write(0x9800+(738<<2), $wrdata);
4569 */
4570 reg_write (0x9800+(738<<2), 0x08000000 | (0x1 << 26) | (0x1 << 27));
4571 //reg_write (0x9800+(738<<2), 0x08000000 | (0x1 << 26));
4572
4573 /* # reg 123: heavy clip factor, xr / RIFS search parameters */
4574 reg_write (0x99ec, 0x0cc80caa);
4575
4576 /* # Reduce Search Start Delay for RIFS */
4577 if (modeHt == 1) /* ($HT_ENABLE == 1) */
4578 {
4579 if (modeHt2040 == 0x1) /* ($DYNAMIC_HT2040_EN == 0x1) */
4580 {
4581 reg_write(0x9800+(70<<2), 40);/*40*/
4582 }
4583 else
4584 {
4585 reg_write(0x9800+(70<<2), 20);
4586 if(mode24g == 0x0)
4587 {
4588 /* $rddata = &$phyreg_read(0x9800+(24<<2));#0x9860;0x1c5860
4589 *$wrdata = ($rddata & 0xffffffc7) | (0x4 << 3);
4590 * &$phyreg_write(0x9800+(24<<2), $wrdata);
4591 */
4592 reg_write(0x9800+(24<<2), (0x0004dd10 & 0xffffffc7) | (0x4 << 3));
4593 }
4594 }
4595 }
4596
4597 if (mode24g == 0x1)
4598 {
4599 reg_write(0x9850, 0xece8b4e4);/*org*/
4600 //reg_write(0x9850, 0xece8b4e2);
4601 reg_write(0x985c, 0x313a5d5e);
4602 }
4603 else
4604 {
4605 reg_write(0x9850, 0xede8b4e4);
4606 reg_write(0x985c, 0x3139605e);
4607 }
4608
4609 zfFlushDelayWrite(dev);
4610
4611 return;
4612 }
4613
4614 /* #4 Disable RIFS function if the RIFS timer is timeout ! */
4615 void zfHpDisableRifs(zdev_t* dev)
4616 {
4617 zmw_get_wlan_dev(dev);
4618
4619 /* Disable RIFS function is to store these HW register initial value while the device plug-in and
4620 re-write to these register if the RIFS function is disabled */
4621
4622 // reg : 9850
4623 reg_write(0x9850, ((struct zsHpPriv*)wd->hpPrivate)->initDesiredSigSize);
4624
4625 // reg : 985c
4626 reg_write(0x985c, ((struct zsHpPriv*)wd->hpPrivate)->initAGC);
4627
4628 // reg : 9860
4629 reg_write(0x9800+(24<<2), ((struct zsHpPriv*)wd->hpPrivate)->initAgcControl);
4630
4631 // reg : 9918
4632 reg_write(0x9800+(70<<2), ((struct zsHpPriv*)wd->hpPrivate)->initSearchStartDelay);
4633
4634 // reg : 991c
4635 reg_write (0x99ec, ((struct zsHpPriv*)wd->hpPrivate)->initRIFSSearchParams);
4636
4637 // reg : a388
4638 reg_write (0x9800+(738<<2), ((struct zsHpPriv*)wd->hpPrivate)->initFastChannelChangeControl);
4639
4640 zfFlushDelayWrite(dev);
4641
4642 return;
4643 }
Linux kernel - Deliverables
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