drivers/staging/rdma/hfi1/chip.h

   1 #ifndef _CHIP_H
   2 #define _CHIP_H
   3 /*
   4  *
   5  * This file is provided under a dual BSD/GPLv2 license.  When using or
   6  * redistributing this file, you may do so under either license.
   7  *
   8  * GPL LICENSE SUMMARY
   9  *
  10  * Copyright(c) 2015 Intel Corporation.
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of version 2 of the GNU General Public License as
  14  * published by the Free Software Foundation.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  19  * General Public License for more details.
  20  *
  21  * BSD LICENSE
  22  *
  23  * Copyright(c) 2015 Intel Corporation.
  24  *
  25  * Redistribution and use in source and binary forms, with or without
  26  * modification, are permitted provided that the following conditions
  27  * are met:
  28  *
  29  *  - Redistributions of source code must retain the above copyright
  30  *    notice, this list of conditions and the following disclaimer.
  31  *  - Redistributions in binary form must reproduce the above copyright
  32  *    notice, this list of conditions and the following disclaimer in
  33  *    the documentation and/or other materials provided with the
  34  *    distribution.
  35  *  - Neither the name of Intel Corporation nor the names of its
  36  *    contributors may be used to endorse or promote products derived
  37  *    from this software without specific prior written permission.
  38  *
  39  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  40  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  41  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  42  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  43  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  44  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  45  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  46  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  47  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  48  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  49  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  50  *
  51  */
  52
  53 /*
  54  * This file contains all of the defines that is specific to the HFI chip
  55  */
  56
  57 /* sizes */
  58 #define CCE_NUM_MSIX_VECTORS 256
  59 #define CCE_NUM_INT_CSRS 12
  60 #define CCE_NUM_INT_MAP_CSRS 96
  61 #define NUM_INTERRUPT_SOURCES 768
  62 #define RXE_NUM_CONTEXTS 160
  63 #define RXE_PER_CONTEXT_SIZE 0x1000     /* 4k */
  64 #define RXE_NUM_TID_FLOWS 32
  65 #define RXE_NUM_DATA_VL 8
  66 #define TXE_NUM_CONTEXTS 160
  67 #define TXE_NUM_SDMA_ENGINES 16
  68 #define NUM_CONTEXTS_PER_SET 8
  69 #define VL_ARB_HIGH_PRIO_TABLE_SIZE 16
  70 #define VL_ARB_LOW_PRIO_TABLE_SIZE 16
  71 #define VL_ARB_TABLE_SIZE 16
  72 #define TXE_NUM_32_BIT_COUNTER 7
  73 #define TXE_NUM_64_BIT_COUNTER 30
  74 #define TXE_NUM_DATA_VL 8
  75 #define TXE_PIO_SIZE (32 * 0x100000)    /* 32 MB */
  76 #define PIO_BLOCK_SIZE 64                       /* bytes */
  77 #define SDMA_BLOCK_SIZE 64                      /* bytes */
  78 #define RCV_BUF_BLOCK_SIZE 64               /* bytes */
  79 #define PIO_CMASK 0x7ff /* counter mask for free and fill counters */
  80 #define MAX_EAGER_ENTRIES    2048       /* max receive eager entries */
  81 #define MAX_TID_PAIR_ENTRIES 1024       /* max receive expected pairs */
  82 /* Virtual? Allocation Unit, defined as AU = 8*2^vAU, 64 bytes, AU is fixed
  83    at 64 bytes for all generation one devices */
  84 #define CM_VAU 3
  85 /* HFI link credit count, AKA receive buffer depth (RBUF_DEPTH) */
  86 #define CM_GLOBAL_CREDITS 0x940
  87 /* Number of PKey entries in the HW */
  88 #define MAX_PKEY_VALUES 16
  89
  90 #include "chip_registers.h"
  91
  92 #define RXE_PER_CONTEXT_USER   (RXE + RXE_PER_CONTEXT_OFFSET)
  93 #define TXE_PIO_SEND (TXE + TXE_PIO_SEND_OFFSET)
  94
  95 /* PBC flags */
  96 #define PBC_INTR                (1ull << 31)
  97 #define PBC_DC_INFO_SHIFT       (30)
  98 #define PBC_DC_INFO             (1ull << PBC_DC_INFO_SHIFT)
  99 #define PBC_TEST_EBP    (1ull << 29)
 100 #define PBC_PACKET_BYPASS       (1ull << 28)
 101 #define PBC_CREDIT_RETURN       (1ull << 25)
 102 #define PBC_INSERT_BYPASS_ICRC (1ull << 24)
 103 #define PBC_TEST_BAD_ICRC       (1ull << 23)
 104 #define PBC_FECN                (1ull << 22)
 105
 106 /* PbcInsertHcrc field settings */
 107 #define PBC_IHCRC_LKDETH 0x0    /* insert @ local KDETH offset */
 108 #define PBC_IHCRC_GKDETH 0x1    /* insert @ global KDETH offset */
 109 #define PBC_IHCRC_NONE   0x2    /* no HCRC inserted */
 110
 111 /* PBC fields */
 112 #define PBC_STATIC_RATE_CONTROL_COUNT_SHIFT 32
 113 #define PBC_STATIC_RATE_CONTROL_COUNT_MASK 0xffffull
 114 #define PBC_STATIC_RATE_CONTROL_COUNT_SMASK \
 115         (PBC_STATIC_RATE_CONTROL_COUNT_MASK << \
 116         PBC_STATIC_RATE_CONTROL_COUNT_SHIFT)
 117
 118 #define PBC_INSERT_HCRC_SHIFT 26
 119 #define PBC_INSERT_HCRC_MASK 0x3ull
 120 #define PBC_INSERT_HCRC_SMASK \
 121         (PBC_INSERT_HCRC_MASK << PBC_INSERT_HCRC_SHIFT)
 122
 123 #define PBC_VL_SHIFT 12
 124 #define PBC_VL_MASK 0xfull
 125 #define PBC_VL_SMASK (PBC_VL_MASK << PBC_VL_SHIFT)
 126
 127 #define PBC_LENGTH_DWS_SHIFT 0
 128 #define PBC_LENGTH_DWS_MASK 0xfffull
 129 #define PBC_LENGTH_DWS_SMASK \
 130         (PBC_LENGTH_DWS_MASK << PBC_LENGTH_DWS_SHIFT)
 131
 132 /* Credit Return Fields */
 133 #define CR_COUNTER_SHIFT 0
 134 #define CR_COUNTER_MASK 0x7ffull
 135 #define CR_COUNTER_SMASK (CR_COUNTER_MASK << CR_COUNTER_SHIFT)
 136
 137 #define CR_STATUS_SHIFT 11
 138 #define CR_STATUS_MASK 0x1ull
 139 #define CR_STATUS_SMASK (CR_STATUS_MASK << CR_STATUS_SHIFT)
 140
 141 #define CR_CREDIT_RETURN_DUE_TO_PBC_SHIFT 12
 142 #define CR_CREDIT_RETURN_DUE_TO_PBC_MASK 0x1ull
 143 #define CR_CREDIT_RETURN_DUE_TO_PBC_SMASK \
 144         (CR_CREDIT_RETURN_DUE_TO_PBC_MASK << \
 145         CR_CREDIT_RETURN_DUE_TO_PBC_SHIFT)
 146
 147 #define CR_CREDIT_RETURN_DUE_TO_THRESHOLD_SHIFT 13
 148 #define CR_CREDIT_RETURN_DUE_TO_THRESHOLD_MASK 0x1ull
 149 #define CR_CREDIT_RETURN_DUE_TO_THRESHOLD_SMASK \
 150         (CR_CREDIT_RETURN_DUE_TO_THRESHOLD_MASK << \
 151         CR_CREDIT_RETURN_DUE_TO_THRESHOLD_SHIFT)
 152
 153 #define CR_CREDIT_RETURN_DUE_TO_ERR_SHIFT 14
 154 #define CR_CREDIT_RETURN_DUE_TO_ERR_MASK 0x1ull
 155 #define CR_CREDIT_RETURN_DUE_TO_ERR_SMASK \
 156         (CR_CREDIT_RETURN_DUE_TO_ERR_MASK << \
 157         CR_CREDIT_RETURN_DUE_TO_ERR_SHIFT)
 158
 159 #define CR_CREDIT_RETURN_DUE_TO_FORCE_SHIFT 15
 160 #define CR_CREDIT_RETURN_DUE_TO_FORCE_MASK 0x1ull
 161 #define CR_CREDIT_RETURN_DUE_TO_FORCE_SMASK \
 162         (CR_CREDIT_RETURN_DUE_TO_FORCE_MASK << \
 163         CR_CREDIT_RETURN_DUE_TO_FORCE_SHIFT)
 164
 165 /* interrupt source numbers */
 166 #define IS_GENERAL_ERR_START      0
 167 #define IS_SDMAENG_ERR_START     16
 168 #define IS_SENDCTXT_ERR_START    32
 169 #define IS_SDMA_START           192 /* includes SDmaProgress,SDmaIdle */
 170 #define IS_VARIOUS_START                240
 171 #define IS_DC_START                     248
 172 #define IS_RCVAVAIL_START               256
 173 #define IS_RCVURGENT_START              416
 174 #define IS_SENDCREDIT_START             576
 175 #define IS_RESERVED_START               736
 176 #define IS_MAX_SOURCES          768
 177
 178 /* derived interrupt source values */
 179 #define IS_GENERAL_ERR_END              IS_SDMAENG_ERR_START
 180 #define IS_SDMAENG_ERR_END              IS_SENDCTXT_ERR_START
 181 #define IS_SENDCTXT_ERR_END             IS_SDMA_START
 182 #define IS_SDMA_END                     IS_VARIOUS_START
 183 #define IS_VARIOUS_END          IS_DC_START
 184 #define IS_DC_END                       IS_RCVAVAIL_START
 185 #define IS_RCVAVAIL_END         IS_RCVURGENT_START
 186 #define IS_RCVURGENT_END                IS_SENDCREDIT_START
 187 #define IS_SENDCREDIT_END               IS_RESERVED_START
 188 #define IS_RESERVED_END         IS_MAX_SOURCES
 189
 190 /* absolute interrupt numbers for QSFP1Int and QSFP2Int */
 191 #define QSFP1_INT               242
 192 #define QSFP2_INT               243
 193
 194 /* DCC_CFG_PORT_CONFIG logical link states */
 195 #define LSTATE_DOWN    0x1
 196 #define LSTATE_INIT    0x2
 197 #define LSTATE_ARMED   0x3
 198 #define LSTATE_ACTIVE  0x4
 199
 200 /* DC8051_STS_CUR_STATE port values (physical link states) */
 201 #define PLS_DISABLED                       0x30
 202 #define PLS_OFFLINE                                0x90
 203 #define PLS_OFFLINE_QUIET                          0x90
 204 #define PLS_OFFLINE_PLANNED_DOWN_INFORM    0x91
 205 #define PLS_OFFLINE_READY_TO_QUIET_LT      0x92
 206 #define PLS_OFFLINE_REPORT_FAILURE                 0x93
 207 #define PLS_OFFLINE_READY_TO_QUIET_BCC     0x94
 208 #define PLS_POLLING                                0x20
 209 #define PLS_POLLING_QUIET                          0x20
 210 #define PLS_POLLING_ACTIVE                         0x21
 211 #define PLS_CONFIGPHY                      0x40
 212 #define PLS_CONFIGPHY_DEBOUCE              0x40
 213 #define PLS_CONFIGPHY_ESTCOMM              0x41
 214 #define PLS_CONFIGPHY_ESTCOMM_TXRX_HUNT    0x42
 215 #define PLS_CONFIGPHY_ESTcOMM_LOCAL_COMPLETE   0x43
 216 #define PLS_CONFIGPHY_OPTEQ                        0x44
 217 #define PLS_CONFIGPHY_OPTEQ_OPTIMIZING     0x44
 218 #define PLS_CONFIGPHY_OPTEQ_LOCAL_COMPLETE         0x45
 219 #define PLS_CONFIGPHY_VERIFYCAP            0x46
 220 #define PLS_CONFIGPHY_VERIFYCAP_EXCHANGE           0x46
 221 #define PLS_CONFIGPHY_VERIFYCAP_LOCAL_COMPLETE 0x47
 222 #define PLS_CONFIGLT                       0x48
 223 #define PLS_CONFIGLT_CONFIGURE             0x48
 224 #define PLS_CONFIGLT_LINK_TRANSFER_ACTIVE          0x49
 225 #define PLS_LINKUP                                 0x50
 226 #define PLS_PHYTEST                                0xB0
 227 #define PLS_INTERNAL_SERDES_LOOPBACK       0xe1
 228 #define PLS_QUICK_LINKUP                           0xe2
 229
 230 /* DC_DC8051_CFG_HOST_CMD_0.REQ_TYPE - 8051 host commands */
 231 #define HCMD_LOAD_CONFIG_DATA  0x01
 232 #define HCMD_READ_CONFIG_DATA  0x02
 233 #define HCMD_CHANGE_PHY_STATE  0x03
 234 #define HCMD_SEND_LCB_IDLE_MSG 0x04
 235 #define HCMD_MISC                  0x05
 236 #define HCMD_READ_LCB_IDLE_MSG 0x06
 237 #define HCMD_READ_LCB_CSR      0x07
 238 #define HCMD_INTERFACE_TEST        0xff
 239
 240 /* DC_DC8051_CFG_HOST_CMD_1.RETURN_CODE - 8051 host command return */
 241 #define HCMD_SUCCESS 2
 242
 243 /* DC_DC8051_DBG_ERR_INFO_SET_BY_8051.ERROR - error flags */
 244 #define SPICO_ROM_FAILED                    (1 <<  0)
 245 #define UNKNOWN_FRAME               (1 <<  1)
 246 #define TARGET_BER_NOT_MET                  (1 <<  2)
 247 #define FAILED_SERDES_INTERNAL_LOOPBACK (1 <<  3)
 248 #define FAILED_SERDES_INIT                  (1 <<  4)
 249 #define FAILED_LNI_POLLING                  (1 <<  5)
 250 #define FAILED_LNI_DEBOUNCE                 (1 <<  6)
 251 #define FAILED_LNI_ESTBCOMM                 (1 <<  7)
 252 #define FAILED_LNI_OPTEQ                    (1 <<  8)
 253 #define FAILED_LNI_VERIFY_CAP1      (1 <<  9)
 254 #define FAILED_LNI_VERIFY_CAP2      (1 << 10)
 255 #define FAILED_LNI_CONFIGLT                 (1 << 11)
 256
 257 #define FAILED_LNI (FAILED_LNI_POLLING | FAILED_LNI_DEBOUNCE \
 258                         | FAILED_LNI_ESTBCOMM | FAILED_LNI_OPTEQ \
 259                         | FAILED_LNI_VERIFY_CAP1 \
 260                         | FAILED_LNI_VERIFY_CAP2 \
 261                         | FAILED_LNI_CONFIGLT)
 262
 263 /* DC_DC8051_DBG_ERR_INFO_SET_BY_8051.HOST_MSG - host message flags */
 264 #define HOST_REQ_DONE      (1 << 0)
 265 #define BC_PWR_MGM_MSG     (1 << 1)
 266 #define BC_SMA_MSG                 (1 << 2)
 267 #define BC_BCC_UNKOWN_MSG          (1 << 3)
 268 #define BC_IDLE_UNKNOWN_MSG        (1 << 4)
 269 #define EXT_DEVICE_CFG_REQ         (1 << 5)
 270 #define VERIFY_CAP_FRAME           (1 << 6)
 271 #define LINKUP_ACHIEVED    (1 << 7)
 272 #define LINK_GOING_DOWN    (1 << 8)
 273 #define LINK_WIDTH_DOWNGRADED  (1 << 9)
 274
 275 /* DC_DC8051_CFG_EXT_DEV_1.REQ_TYPE - 8051 host requests */
 276 #define HREQ_LOAD_CONFIG        0x01
 277 #define HREQ_SAVE_CONFIG        0x02
 278 #define HREQ_READ_CONFIG        0x03
 279 #define HREQ_SET_TX_EQ_ABS      0x04
 280 #define HREQ_SET_TX_EQ_REL      0x05
 281 #define HREQ_ENABLE             0x06
 282 #define HREQ_CONFIG_DONE        0xfe
 283 #define HREQ_INTERFACE_TEST     0xff
 284
 285 /* DC_DC8051_CFG_EXT_DEV_0.RETURN_CODE - 8051 host request return codes */
 286 #define HREQ_INVALID            0x01
 287 #define HREQ_SUCCESS            0x02
 288 #define HREQ_NOT_SUPPORTED              0x03
 289 #define HREQ_FEATURE_NOT_SUPPORTED      0x04 /* request specific feature */
 290 #define HREQ_REQUEST_REJECTED   0xfe
 291 #define HREQ_EXECUTION_ONGOING  0xff
 292
 293 /* MISC host command functions */
 294 #define HCMD_MISC_REQUEST_LCB_ACCESS 0x1
 295 #define HCMD_MISC_GRANT_LCB_ACCESS   0x2
 296
 297 /* idle flit message types */
 298 #define IDLE_PHYSICAL_LINK_MGMT 0x1
 299 #define IDLE_CRU                    0x2
 300 #define IDLE_SMA                    0x3
 301 #define IDLE_POWER_MGMT     0x4
 302
 303 /* idle flit message send fields (both send and read) */
 304 #define IDLE_PAYLOAD_MASK 0xffffffffffull /* 40 bits */
 305 #define IDLE_PAYLOAD_SHIFT 8
 306 #define IDLE_MSG_TYPE_MASK 0xf
 307 #define IDLE_MSG_TYPE_SHIFT 0
 308
 309 /* idle flit message read fields */
 310 #define READ_IDLE_MSG_TYPE_MASK 0xf
 311 #define READ_IDLE_MSG_TYPE_SHIFT 0
 312
 313 /* SMA idle flit payload commands */
 314 #define SMA_IDLE_ARM    1
 315 #define SMA_IDLE_ACTIVE 2
 316
 317 /* DC_DC8051_CFG_MODE.GENERAL bits */
 318 #define DISABLE_SELF_GUID_CHECK 0x2
 319
 320 /*
 321  * Eager buffer minimum and maximum sizes supported by the hardware.
 322  * All power-of-two sizes in between are supported as well.
 323  * MAX_EAGER_BUFFER_TOTAL is the maximum size of memory
 324  * allocatable for Eager buffer to a single context. All others
 325  * are limits for the RcvArray entries.
 326  */
 327 #define MIN_EAGER_BUFFER       (4 * 1024)
 328 #define MAX_EAGER_BUFFER       (256 * 1024)
 329 #define MAX_EAGER_BUFFER_TOTAL (64 * (1 << 20)) /* max per ctxt 64MB */
 330 #define MAX_EXPECTED_BUFFER    (2048 * 1024)
 331
 332 /*
 333  * Receive expected base and count and eager base and count increment -
 334  * the CSR fields hold multiples of this value.
 335  */
 336 #define RCV_SHIFT 3
 337 #define RCV_INCREMENT (1 << RCV_SHIFT)
 338
 339 /*
 340  * Receive header queue entry increment - the CSR holds multiples of
 341  * this value.
 342  */
 343 #define HDRQ_SIZE_SHIFT 5
 344 #define HDRQ_INCREMENT (1 << HDRQ_SIZE_SHIFT)
 345
 346 /*
 347  * Freeze handling flags
 348  */
 349 #define FREEZE_ABORT     0x01   /* do not do recovery */
 350 #define FREEZE_SELF          0x02       /* initiate the freeze */
 351 #define FREEZE_LINK_DOWN 0x04   /* link is down */
 352
 353 /*
 354  * Chip implementation codes.
 355  */
 356 #define ICODE_RTL_SILICON               0x00
 357 #define ICODE_RTL_VCS_SIMULATION        0x01
 358 #define ICODE_FPGA_EMULATION    0x02
 359 #define ICODE_FUNCTIONAL_SIMULATOR      0x03
 360
 361 /*
 362  * 8051 data memory size.
 363  */
 364 #define DC8051_DATA_MEM_SIZE 0x1000
 365
 366 /*
 367  * 8051 firmware registers
 368  */
 369 #define NUM_GENERAL_FIELDS 0x17
 370 #define NUM_LANE_FIELDS    0x8
 371
 372 /* 8051 general register Field IDs */
 373 #define TX_SETTINGS                  0x06
 374 #define VERIFY_CAP_LOCAL_PHY         0x07
 375 #define VERIFY_CAP_LOCAL_FABRIC      0x08
 376 #define VERIFY_CAP_LOCAL_LINK_WIDTH  0x09
 377 #define LOCAL_DEVICE_ID              0x0a
 378 #define LOCAL_LNI_INFO               0x0c
 379 #define REMOTE_LNI_INFO              0x0d
 380 #define MISC_STATUS                  0x0e
 381 #define VERIFY_CAP_REMOTE_PHY        0x0f
 382 #define VERIFY_CAP_REMOTE_FABRIC     0x10
 383 #define VERIFY_CAP_REMOTE_LINK_WIDTH 0x11
 384 #define LAST_LOCAL_STATE_COMPLETE    0x12
 385 #define LAST_REMOTE_STATE_COMPLETE   0x13
 386 #define LINK_QUALITY_INFO            0x14
 387 #define REMOTE_DEVICE_ID             0x15
 388
 389 /* Lane ID for general configuration registers */
 390 #define GENERAL_CONFIG 4
 391
 392 /* LOAD_DATA 8051 command shifts and fields */
 393 #define LOAD_DATA_FIELD_ID_SHIFT 40
 394 #define LOAD_DATA_FIELD_ID_MASK 0xfull
 395 #define LOAD_DATA_LANE_ID_SHIFT 32
 396 #define LOAD_DATA_LANE_ID_MASK 0xfull
 397 #define LOAD_DATA_DATA_SHIFT   0x0
 398 #define LOAD_DATA_DATA_MASK   0xffffffffull
 399
 400 /* READ_DATA 8051 command shifts and fields */
 401 #define READ_DATA_FIELD_ID_SHIFT 40
 402 #define READ_DATA_FIELD_ID_MASK 0xffull
 403 #define READ_DATA_LANE_ID_SHIFT 32
 404 #define READ_DATA_LANE_ID_MASK 0xffull
 405 #define READ_DATA_DATA_SHIFT   0x0
 406 #define READ_DATA_DATA_MASK   0xffffffffull
 407
 408 /* TX settings fields */
 409 #define ENABLE_LANE_TX_SHIFT            0
 410 #define ENABLE_LANE_TX_MASK             0xff
 411 #define TX_POLARITY_INVERSION_SHIFT     8
 412 #define TX_POLARITY_INVERSION_MASK      0xff
 413 #define RX_POLARITY_INVERSION_SHIFT     16
 414 #define RX_POLARITY_INVERSION_MASK      0xff
 415 #define MAX_RATE_SHIFT                  24
 416 #define MAX_RATE_MASK                   0xff
 417
 418 /* verify capability PHY fields */
 419 #define CONTINIOUS_REMOTE_UPDATE_SUPPORT_SHIFT  0x4
 420 #define CONTINIOUS_REMOTE_UPDATE_SUPPORT_MASK   0x1
 421 #define POWER_MANAGEMENT_SHIFT                  0x0
 422 #define POWER_MANAGEMENT_MASK                   0xf
 423
 424 /* 8051 lane register Field IDs */
 425 #define SPICO_FW_VERSION 0x7    /* SPICO firmware version */
 426
 427 /* SPICO firmware version fields */
 428 #define SPICO_ROM_VERSION_SHIFT 0
 429 #define SPICO_ROM_VERSION_MASK 0xffff
 430 #define SPICO_ROM_PROD_ID_SHIFT 16
 431 #define SPICO_ROM_PROD_ID_MASK 0xffff
 432
 433 /* verify capability fabric fields */
 434 #define VAU_SHIFT       0
 435 #define VAU_MASK        0x0007
 436 #define Z_SHIFT         3
 437 #define Z_MASK          0x0001
 438 #define VCU_SHIFT       4
 439 #define VCU_MASK        0x0007
 440 #define VL15BUF_SHIFT   8
 441 #define VL15BUF_MASK    0x0fff
 442 #define CRC_SIZES_SHIFT 20
 443 #define CRC_SIZES_MASK  0x7
 444
 445 /* verify capability local link width fields */
 446 #define LINK_WIDTH_SHIFT 0              /* also for remote link width */
 447 #define LINK_WIDTH_MASK 0xffff          /* also for remote link width */
 448 #define LOCAL_FLAG_BITS_SHIFT 16
 449 #define LOCAL_FLAG_BITS_MASK 0xff
 450 #define MISC_CONFIG_BITS_SHIFT 24
 451 #define MISC_CONFIG_BITS_MASK 0xff
 452
 453 /* verify capability remote link width fields */
 454 #define REMOTE_TX_RATE_SHIFT 16
 455 #define REMOTE_TX_RATE_MASK 0xff
 456
 457 /* LOCAL_DEVICE_ID fields */
 458 #define LOCAL_DEVICE_REV_SHIFT 0
 459 #define LOCAL_DEVICE_REV_MASK 0xff
 460 #define LOCAL_DEVICE_ID_SHIFT 8
 461 #define LOCAL_DEVICE_ID_MASK 0xffff
 462
 463 /* REMOTE_DEVICE_ID fields */
 464 #define REMOTE_DEVICE_REV_SHIFT 0
 465 #define REMOTE_DEVICE_REV_MASK 0xff
 466 #define REMOTE_DEVICE_ID_SHIFT 8
 467 #define REMOTE_DEVICE_ID_MASK 0xffff
 468
 469 /* local LNI link width fields */
 470 #define ENABLE_LANE_RX_SHIFT 16
 471 #define ENABLE_LANE_RX_MASK  0xff
 472
 473 /* mask, shift for reading 'mgmt_enabled' value from REMOTE_LNI_INFO field */
 474 #define MGMT_ALLOWED_SHIFT 23
 475 #define MGMT_ALLOWED_MASK 0x1
 476
 477 /* mask, shift for 'link_quality' within LINK_QUALITY_INFO field */
 478 #define LINK_QUALITY_SHIFT 24
 479 #define LINK_QUALITY_MASK  0x7
 480
 481 /*
 482  * mask, shift for reading 'planned_down_remote_reason_code'
 483  * from LINK_QUALITY_INFO field
 484  */
 485 #define DOWN_REMOTE_REASON_SHIFT 16
 486 #define DOWN_REMOTE_REASON_MASK  0xff
 487
 488 /* verify capability PHY power management bits */
 489 #define PWRM_BER_CONTROL        0x1
 490 #define PWRM_BANDWIDTH_CONTROL  0x2
 491
 492 /* verify capability fabric CRC size bits */
 493 enum {
 494         CAP_CRC_14B = (1 << 0), /* 14b CRC */
 495         CAP_CRC_48B = (1 << 1), /* 48b CRC */
 496         CAP_CRC_12B_16B_PER_LANE = (1 << 2) /* 12b-16b per lane CRC */
 497 };
 498
 499 #define SUPPORTED_CRCS (CAP_CRC_14B | CAP_CRC_48B)
 500
 501 /* misc status version fields */
 502 #define STS_FM_VERSION_A_SHIFT 16
 503 #define STS_FM_VERSION_A_MASK  0xff
 504 #define STS_FM_VERSION_B_SHIFT 24
 505 #define STS_FM_VERSION_B_MASK  0xff
 506
 507 /* LCB_CFG_CRC_MODE TX_VAL and RX_VAL CRC mode values */
 508 #define LCB_CRC_16B                     0x0     /* 16b CRC */
 509 #define LCB_CRC_14B                     0x1     /* 14b CRC */
 510 #define LCB_CRC_48B                     0x2     /* 48b CRC */
 511 #define LCB_CRC_12B_16B_PER_LANE        0x3     /* 12b-16b per lane CRC */
 512
 513 /* the following enum is (almost) a copy/paste of the definition
 514  * in the OPA spec, section 20.2.2.6.8 (PortInfo) */
 515 enum {
 516         PORT_LTP_CRC_MODE_NONE = 0,
 517         PORT_LTP_CRC_MODE_14 = 1, /* 14-bit LTP CRC mode (optional) */
 518         PORT_LTP_CRC_MODE_16 = 2, /* 16-bit LTP CRC mode */
 519         PORT_LTP_CRC_MODE_48 = 4,
 520                 /* 48-bit overlapping LTP CRC mode (optional) */
 521         PORT_LTP_CRC_MODE_PER_LANE = 8
 522                 /* 12 to 16 bit per lane LTP CRC mode (optional) */
 523 };
 524
 525 /* timeouts */
 526 #define LINK_RESTART_DELAY 1000         /* link restart delay, in ms */
 527 #define TIMEOUT_8051_START 5000         /* 8051 start timeout, in ms */
 528 #define DC8051_COMMAND_TIMEOUT 20000    /* DC8051 command timeout, in ms */
 529 #define FREEZE_STATUS_TIMEOUT 20        /* wait for freeze indicators, in ms */
 530 #define VL_STATUS_CLEAR_TIMEOUT 5000    /* per-VL status clear, in ms */
 531 #define CCE_STATUS_TIMEOUT 10           /* time to clear CCE Status, in ms */
 532
 533 /* cclock tick time, in picoseconds per tick: 1/speed * 10^12  */
 534 #define ASIC_CCLOCK_PS  1242    /* 805 MHz */
 535 #define FPGA_CCLOCK_PS 30300    /*  33 MHz */
 536
 537 /*
 538  * Mask of enabled MISC errors.  Do not enable the two RSA engine errors -
 539  * see firmware.c:run_rsa() for details.
 540  */
 541 #define DRIVER_MISC_MASK \
 542         (~(MISC_ERR_STATUS_MISC_FW_AUTH_FAILED_ERR_SMASK \
 543                 | MISC_ERR_STATUS_MISC_KEY_MISMATCH_ERR_SMASK))
 544
 545 /* valid values for the loopback module parameter */
 546 #define LOOPBACK_NONE   0       /* no loopback - default */
 547 #define LOOPBACK_SERDES 1
 548 #define LOOPBACK_LCB    2
 549 #define LOOPBACK_CABLE  3       /* external cable */
 550
 551 /* read and write hardware registers */
 552 u64 read_csr(const struct hfi1_devdata *dd, u32 offset);
 553 void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value);
 554
 555 /*
 556  * The *_kctxt_* flavor of the CSR read/write functions are for
 557  * per-context or per-SDMA CSRs that are not mappable to user-space.
 558  * Their spacing is not a PAGE_SIZE multiple.
 559  */
 560 static inline u64 read_kctxt_csr(const struct hfi1_devdata *dd, int ctxt,
 561                                  u32 offset0)
 562 {
 563         /* kernel per-context CSRs are separated by 0x100 */
 564         return read_csr(dd, offset0 + (0x100 * ctxt));
 565 }
 566
 567 static inline void write_kctxt_csr(struct hfi1_devdata *dd, int ctxt,
 568                                    u32 offset0, u64 value)
 569 {
 570         /* kernel per-context CSRs are separated by 0x100 */
 571         write_csr(dd, offset0 + (0x100 * ctxt), value);
 572 }
 573
 574 int read_lcb_csr(struct hfi1_devdata *dd, u32 offset, u64 *data);
 575 int write_lcb_csr(struct hfi1_devdata *dd, u32 offset, u64 data);
 576
 577 void __iomem *get_csr_addr(
 578         struct hfi1_devdata *dd,
 579         u32 offset);
 580
 581 static inline void __iomem *get_kctxt_csr_addr(
 582         struct hfi1_devdata *dd,
 583         int ctxt,
 584         u32 offset0)
 585 {
 586         return get_csr_addr(dd, offset0 + (0x100 * ctxt));
 587 }
 588
 589 /*
 590  * The *_uctxt_* flavor of the CSR read/write functions are for
 591  * per-context CSRs that are mappable to user space. All these CSRs
 592  * are spaced by a PAGE_SIZE multiple in order to be mappable to
 593  * different processes without exposing other contexts' CSRs
 594  */
 595 static inline u64 read_uctxt_csr(const struct hfi1_devdata *dd, int ctxt,
 596                                  u32 offset0)
 597 {
 598         /* user per-context CSRs are separated by 0x1000 */
 599         return read_csr(dd, offset0 + (0x1000 * ctxt));
 600 }
 601
 602 static inline void write_uctxt_csr(struct hfi1_devdata *dd, int ctxt,
 603                                    u32 offset0, u64 value)
 604 {
 605         /* user per-context CSRs are separated by 0x1000 */
 606         write_csr(dd, offset0 + (0x1000 * ctxt), value);
 607 }
 608
 609 u64 create_pbc(struct hfi1_pportdata *ppd, u64, int, u32, u32);
 610
 611 /* firmware.c */
 612 #define NUM_PCIE_SERDES 16      /* number of PCIe serdes on the SBus */
 613 extern const u8 pcie_serdes_broadcast[];
 614 extern const u8 pcie_pcs_addrs[2][NUM_PCIE_SERDES];
 615 /* SBus commands */
 616 #define RESET_SBUS_RECEIVER 0x20
 617 #define WRITE_SBUS_RECEIVER 0x21
 618 void sbus_request(struct hfi1_devdata *dd,
 619                   u8 receiver_addr, u8 data_addr, u8 command, u32 data_in);
 620 int sbus_request_slow(struct hfi1_devdata *dd,
 621                       u8 receiver_addr, u8 data_addr, u8 command, u32 data_in);
 622 void set_sbus_fast_mode(struct hfi1_devdata *dd);
 623 void clear_sbus_fast_mode(struct hfi1_devdata *dd);
 624 int hfi1_firmware_init(struct hfi1_devdata *dd);
 625 int load_pcie_firmware(struct hfi1_devdata *dd);
 626 int load_firmware(struct hfi1_devdata *dd);
 627 void dispose_firmware(void);
 628 int acquire_hw_mutex(struct hfi1_devdata *dd);
 629 void release_hw_mutex(struct hfi1_devdata *dd);
 630 void fabric_serdes_reset(struct hfi1_devdata *dd);
 631 int read_8051_data(struct hfi1_devdata *dd, u32 addr, u32 len, u64 *result);
 632
 633 /* chip.c */
 634 void read_misc_status(struct hfi1_devdata *dd, u8 *ver_a, u8 *ver_b);
 635 void read_guid(struct hfi1_devdata *dd);
 636 int wait_fm_ready(struct hfi1_devdata *dd, u32 mstimeout);
 637 void set_link_down_reason(struct hfi1_pportdata *ppd, u8 lcl_reason,
 638                           u8 neigh_reason, u8 rem_reason);
 639 int set_link_state(struct hfi1_pportdata *, u32 state);
 640 int port_ltp_to_cap(int port_ltp);
 641 void handle_verify_cap(struct work_struct *work);
 642 void handle_freeze(struct work_struct *work);
 643 void handle_link_up(struct work_struct *work);
 644 void handle_link_down(struct work_struct *work);
 645 void handle_link_downgrade(struct work_struct *work);
 646 void handle_link_bounce(struct work_struct *work);
 647 void handle_sma_message(struct work_struct *work);
 648 void start_freeze_handling(struct hfi1_pportdata *ppd, int flags);
 649 int send_idle_sma(struct hfi1_devdata *dd, u64 message);
 650 int start_link(struct hfi1_pportdata *ppd);
 651 void init_qsfp(struct hfi1_pportdata *ppd);
 652 int bringup_serdes(struct hfi1_pportdata *ppd);
 653 void set_intr_state(struct hfi1_devdata *dd, u32 enable);
 654 void apply_link_downgrade_policy(struct hfi1_pportdata *ppd,
 655                                  int refresh_widths);
 656 void update_usrhead(struct hfi1_ctxtdata *, u32, u32, u32, u32, u32);
 657 int stop_drain_data_vls(struct hfi1_devdata *dd);
 658 int open_fill_data_vls(struct hfi1_devdata *dd);
 659 u32 ns_to_cclock(struct hfi1_devdata *dd, u32 ns);
 660 u32 cclock_to_ns(struct hfi1_devdata *dd, u32 cclock);
 661 void get_linkup_link_widths(struct hfi1_pportdata *ppd);
 662 void read_ltp_rtt(struct hfi1_devdata *dd);
 663 void clear_linkup_counters(struct hfi1_devdata *dd);
 664 u32 hdrqempty(struct hfi1_ctxtdata *rcd);
 665 int is_a0(struct hfi1_devdata *dd);
 666 int is_ax(struct hfi1_devdata *dd);
 667 int is_bx(struct hfi1_devdata *dd);
 668 u32 read_physical_state(struct hfi1_devdata *dd);
 669 u32 chip_to_opa_pstate(struct hfi1_devdata *dd, u32 chip_pstate);
 670 u32 get_logical_state(struct hfi1_pportdata *ppd);
 671 const char *opa_lstate_name(u32 lstate);
 672 const char *opa_pstate_name(u32 pstate);
 673 u32 driver_physical_state(struct hfi1_pportdata *ppd);
 674 u32 driver_logical_state(struct hfi1_pportdata *ppd);
 675
 676 int acquire_lcb_access(struct hfi1_devdata *dd, int sleep_ok);
 677 int release_lcb_access(struct hfi1_devdata *dd, int sleep_ok);
 678 #define LCB_START DC_LCB_CSRS
 679 #define LCB_END   DC_8051_CSRS /* next block is 8051 */
 680 static inline int is_lcb_offset(u32 offset)
 681 {
 682         return (offset >= LCB_START && offset < LCB_END);
 683 }
 684
 685 extern uint num_vls;
 686
 687 extern uint disable_integrity;
 688 u64 read_dev_cntr(struct hfi1_devdata *dd, int index, int vl);
 689 u64 write_dev_cntr(struct hfi1_devdata *dd, int index, int vl, u64 data);
 690 u64 read_port_cntr(struct hfi1_pportdata *ppd, int index, int vl);
 691 u64 write_port_cntr(struct hfi1_pportdata *ppd, int index, int vl, u64 data);
 692
 693 /* Per VL indexes */
 694 enum {
 695         C_VL_0 = 0,
 696         C_VL_1,
 697         C_VL_2,
 698         C_VL_3,
 699         C_VL_4,
 700         C_VL_5,
 701         C_VL_6,
 702         C_VL_7,
 703         C_VL_15,
 704         C_VL_COUNT
 705 };
 706
 707 static inline int vl_from_idx(int idx)
 708 {
 709         return (idx == C_VL_15 ? 15 : idx);
 710 }
 711
 712 static inline int idx_from_vl(int vl)
 713 {
 714         return (vl == 15 ? C_VL_15 : vl);
 715 }
 716
 717 /* Per device counter indexes */
 718 enum {
 719         C_RCV_OVF = 0,
 720         C_RX_TID_FULL,
 721         C_RX_TID_INVALID,
 722         C_RX_TID_FLGMS,
 723         C_RX_CTX_RHQS,
 724         C_RX_CTX_EGRS,
 725         C_RCV_TID_FLSMS,
 726         C_CCE_PCI_CR_ST,
 727         C_CCE_PCI_TR_ST,
 728         C_CCE_PIO_WR_ST,
 729         C_CCE_ERR_INT,
 730         C_CCE_SDMA_INT,
 731         C_CCE_MISC_INT,
 732         C_CCE_RCV_AV_INT,
 733         C_CCE_RCV_URG_INT,
 734         C_CCE_SEND_CR_INT,
 735         C_DC_UNC_ERR,
 736         C_DC_RCV_ERR,
 737         C_DC_FM_CFG_ERR,
 738         C_DC_RMT_PHY_ERR,
 739         C_DC_DROPPED_PKT,
 740         C_DC_MC_XMIT_PKTS,
 741         C_DC_MC_RCV_PKTS,
 742         C_DC_XMIT_CERR,
 743         C_DC_RCV_CERR,
 744         C_DC_RCV_FCC,
 745         C_DC_XMIT_FCC,
 746         C_DC_XMIT_FLITS,
 747         C_DC_RCV_FLITS,
 748         C_DC_XMIT_PKTS,
 749         C_DC_RCV_PKTS,
 750         C_DC_RX_FLIT_VL,
 751         C_DC_RX_PKT_VL,
 752         C_DC_RCV_FCN,
 753         C_DC_RCV_FCN_VL,
 754         C_DC_RCV_BCN,
 755         C_DC_RCV_BCN_VL,
 756         C_DC_RCV_BBL,
 757         C_DC_RCV_BBL_VL,
 758         C_DC_MARK_FECN,
 759         C_DC_MARK_FECN_VL,
 760         C_DC_TOTAL_CRC,
 761         C_DC_CRC_LN0,
 762         C_DC_CRC_LN1,
 763         C_DC_CRC_LN2,
 764         C_DC_CRC_LN3,
 765         C_DC_CRC_MULT_LN,
 766         C_DC_TX_REPLAY,
 767         C_DC_RX_REPLAY,
 768         C_DC_SEQ_CRC_CNT,
 769         C_DC_ESC0_ONLY_CNT,
 770         C_DC_ESC0_PLUS1_CNT,
 771         C_DC_ESC0_PLUS2_CNT,
 772         C_DC_REINIT_FROM_PEER_CNT,
 773         C_DC_SBE_CNT,
 774         C_DC_MISC_FLG_CNT,
 775         C_DC_PRF_GOOD_LTP_CNT,
 776         C_DC_PRF_ACCEPTED_LTP_CNT,
 777         C_DC_PRF_RX_FLIT_CNT,
 778         C_DC_PRF_TX_FLIT_CNT,
 779         C_DC_PRF_CLK_CNTR,
 780         C_DC_PG_DBG_FLIT_CRDTS_CNT,
 781         C_DC_PG_STS_PAUSE_COMPLETE_CNT,
 782         C_DC_PG_STS_TX_SBE_CNT,
 783         C_DC_PG_STS_TX_MBE_CNT,
 784         C_SW_CPU_INTR,
 785         C_SW_CPU_RCV_LIM,
 786         C_SW_VTX_WAIT,
 787         C_SW_PIO_WAIT,
 788         C_SW_KMEM_WAIT,
 789         DEV_CNTR_LAST  /* Must be kept last */
 790 };
 791
 792 /* Per port counter indexes */
 793 enum {
 794         C_TX_UNSUP_VL = 0,
 795         C_TX_INVAL_LEN,
 796         C_TX_MM_LEN_ERR,
 797         C_TX_UNDERRUN,
 798         C_TX_FLOW_STALL,
 799         C_TX_DROPPED,
 800         C_TX_HDR_ERR,
 801         C_TX_PKT,
 802         C_TX_WORDS,
 803         C_TX_WAIT,
 804         C_TX_FLIT_VL,
 805         C_TX_PKT_VL,
 806         C_TX_WAIT_VL,
 807         C_RX_PKT,
 808         C_RX_WORDS,
 809         C_SW_LINK_DOWN,
 810         C_SW_LINK_UP,
 811         C_SW_XMIT_DSCD,
 812         C_SW_XMIT_DSCD_VL,
 813         C_SW_XMIT_CSTR_ERR,
 814         C_SW_RCV_CSTR_ERR,
 815         C_SW_IBP_LOOP_PKTS,
 816         C_SW_IBP_RC_RESENDS,
 817         C_SW_IBP_RNR_NAKS,
 818         C_SW_IBP_OTHER_NAKS,
 819         C_SW_IBP_RC_TIMEOUTS,
 820         C_SW_IBP_PKT_DROPS,
 821         C_SW_IBP_DMA_WAIT,
 822         C_SW_IBP_RC_SEQNAK,
 823         C_SW_IBP_RC_DUPREQ,
 824         C_SW_IBP_RDMA_SEQ,
 825         C_SW_IBP_UNALIGNED,
 826         C_SW_IBP_SEQ_NAK,
 827         C_SW_CPU_RC_ACKS,
 828         C_SW_CPU_RC_QACKS,
 829         C_SW_CPU_RC_DELAYED_COMP,
 830         C_RCV_HDR_OVF_0,
 831         C_RCV_HDR_OVF_1,
 832         C_RCV_HDR_OVF_2,
 833         C_RCV_HDR_OVF_3,
 834         C_RCV_HDR_OVF_4,
 835         C_RCV_HDR_OVF_5,
 836         C_RCV_HDR_OVF_6,
 837         C_RCV_HDR_OVF_7,
 838         C_RCV_HDR_OVF_8,
 839         C_RCV_HDR_OVF_9,
 840         C_RCV_HDR_OVF_10,
 841         C_RCV_HDR_OVF_11,
 842         C_RCV_HDR_OVF_12,
 843         C_RCV_HDR_OVF_13,
 844         C_RCV_HDR_OVF_14,
 845         C_RCV_HDR_OVF_15,
 846         C_RCV_HDR_OVF_16,
 847         C_RCV_HDR_OVF_17,
 848         C_RCV_HDR_OVF_18,
 849         C_RCV_HDR_OVF_19,
 850         C_RCV_HDR_OVF_20,
 851         C_RCV_HDR_OVF_21,
 852         C_RCV_HDR_OVF_22,
 853         C_RCV_HDR_OVF_23,
 854         C_RCV_HDR_OVF_24,
 855         C_RCV_HDR_OVF_25,
 856         C_RCV_HDR_OVF_26,
 857         C_RCV_HDR_OVF_27,
 858         C_RCV_HDR_OVF_28,
 859         C_RCV_HDR_OVF_29,
 860         C_RCV_HDR_OVF_30,
 861         C_RCV_HDR_OVF_31,
 862         C_RCV_HDR_OVF_32,
 863         C_RCV_HDR_OVF_33,
 864         C_RCV_HDR_OVF_34,
 865         C_RCV_HDR_OVF_35,
 866         C_RCV_HDR_OVF_36,
 867         C_RCV_HDR_OVF_37,
 868         C_RCV_HDR_OVF_38,
 869         C_RCV_HDR_OVF_39,
 870         C_RCV_HDR_OVF_40,
 871         C_RCV_HDR_OVF_41,
 872         C_RCV_HDR_OVF_42,
 873         C_RCV_HDR_OVF_43,
 874         C_RCV_HDR_OVF_44,
 875         C_RCV_HDR_OVF_45,
 876         C_RCV_HDR_OVF_46,
 877         C_RCV_HDR_OVF_47,
 878         C_RCV_HDR_OVF_48,
 879         C_RCV_HDR_OVF_49,
 880         C_RCV_HDR_OVF_50,
 881         C_RCV_HDR_OVF_51,
 882         C_RCV_HDR_OVF_52,
 883         C_RCV_HDR_OVF_53,
 884         C_RCV_HDR_OVF_54,
 885         C_RCV_HDR_OVF_55,
 886         C_RCV_HDR_OVF_56,
 887         C_RCV_HDR_OVF_57,
 888         C_RCV_HDR_OVF_58,
 889         C_RCV_HDR_OVF_59,
 890         C_RCV_HDR_OVF_60,
 891         C_RCV_HDR_OVF_61,
 892         C_RCV_HDR_OVF_62,
 893         C_RCV_HDR_OVF_63,
 894         C_RCV_HDR_OVF_64,
 895         C_RCV_HDR_OVF_65,
 896         C_RCV_HDR_OVF_66,
 897         C_RCV_HDR_OVF_67,
 898         C_RCV_HDR_OVF_68,
 899         C_RCV_HDR_OVF_69,
 900         C_RCV_HDR_OVF_70,
 901         C_RCV_HDR_OVF_71,
 902         C_RCV_HDR_OVF_72,
 903         C_RCV_HDR_OVF_73,
 904         C_RCV_HDR_OVF_74,
 905         C_RCV_HDR_OVF_75,
 906         C_RCV_HDR_OVF_76,
 907         C_RCV_HDR_OVF_77,
 908         C_RCV_HDR_OVF_78,
 909         C_RCV_HDR_OVF_79,
 910         C_RCV_HDR_OVF_80,
 911         C_RCV_HDR_OVF_81,
 912         C_RCV_HDR_OVF_82,
 913         C_RCV_HDR_OVF_83,
 914         C_RCV_HDR_OVF_84,
 915         C_RCV_HDR_OVF_85,
 916         C_RCV_HDR_OVF_86,
 917         C_RCV_HDR_OVF_87,
 918         C_RCV_HDR_OVF_88,
 919         C_RCV_HDR_OVF_89,
 920         C_RCV_HDR_OVF_90,
 921         C_RCV_HDR_OVF_91,
 922         C_RCV_HDR_OVF_92,
 923         C_RCV_HDR_OVF_93,
 924         C_RCV_HDR_OVF_94,
 925         C_RCV_HDR_OVF_95,
 926         C_RCV_HDR_OVF_96,
 927         C_RCV_HDR_OVF_97,
 928         C_RCV_HDR_OVF_98,
 929         C_RCV_HDR_OVF_99,
 930         C_RCV_HDR_OVF_100,
 931         C_RCV_HDR_OVF_101,
 932         C_RCV_HDR_OVF_102,
 933         C_RCV_HDR_OVF_103,
 934         C_RCV_HDR_OVF_104,
 935         C_RCV_HDR_OVF_105,
 936         C_RCV_HDR_OVF_106,
 937         C_RCV_HDR_OVF_107,
 938         C_RCV_HDR_OVF_108,
 939         C_RCV_HDR_OVF_109,
 940         C_RCV_HDR_OVF_110,
 941         C_RCV_HDR_OVF_111,
 942         C_RCV_HDR_OVF_112,
 943         C_RCV_HDR_OVF_113,
 944         C_RCV_HDR_OVF_114,
 945         C_RCV_HDR_OVF_115,
 946         C_RCV_HDR_OVF_116,
 947         C_RCV_HDR_OVF_117,
 948         C_RCV_HDR_OVF_118,
 949         C_RCV_HDR_OVF_119,
 950         C_RCV_HDR_OVF_120,
 951         C_RCV_HDR_OVF_121,
 952         C_RCV_HDR_OVF_122,
 953         C_RCV_HDR_OVF_123,
 954         C_RCV_HDR_OVF_124,
 955         C_RCV_HDR_OVF_125,
 956         C_RCV_HDR_OVF_126,
 957         C_RCV_HDR_OVF_127,
 958         C_RCV_HDR_OVF_128,
 959         C_RCV_HDR_OVF_129,
 960         C_RCV_HDR_OVF_130,
 961         C_RCV_HDR_OVF_131,
 962         C_RCV_HDR_OVF_132,
 963         C_RCV_HDR_OVF_133,
 964         C_RCV_HDR_OVF_134,
 965         C_RCV_HDR_OVF_135,
 966         C_RCV_HDR_OVF_136,
 967         C_RCV_HDR_OVF_137,
 968         C_RCV_HDR_OVF_138,
 969         C_RCV_HDR_OVF_139,
 970         C_RCV_HDR_OVF_140,
 971         C_RCV_HDR_OVF_141,
 972         C_RCV_HDR_OVF_142,
 973         C_RCV_HDR_OVF_143,
 974         C_RCV_HDR_OVF_144,
 975         C_RCV_HDR_OVF_145,
 976         C_RCV_HDR_OVF_146,
 977         C_RCV_HDR_OVF_147,
 978         C_RCV_HDR_OVF_148,
 979         C_RCV_HDR_OVF_149,
 980         C_RCV_HDR_OVF_150,
 981         C_RCV_HDR_OVF_151,
 982         C_RCV_HDR_OVF_152,
 983         C_RCV_HDR_OVF_153,
 984         C_RCV_HDR_OVF_154,
 985         C_RCV_HDR_OVF_155,
 986         C_RCV_HDR_OVF_156,
 987         C_RCV_HDR_OVF_157,
 988         C_RCV_HDR_OVF_158,
 989         C_RCV_HDR_OVF_159,
 990         PORT_CNTR_LAST /* Must be kept last */
 991 };
 992
 993 u64 get_all_cpu_total(u64 __percpu *cntr);
 994 void hfi1_start_cleanup(struct hfi1_devdata *dd);
 995 void hfi1_clear_tids(struct hfi1_ctxtdata *rcd);
 996 struct hfi1_message_header *hfi1_get_msgheader(
 997                                 struct hfi1_devdata *dd, __le32 *rhf_addr);
 998 int hfi1_get_base_kinfo(struct hfi1_ctxtdata *rcd,
 999                         struct hfi1_ctxt_info *kinfo);
1000 u64 hfi1_gpio_mod(struct hfi1_devdata *dd, u32 target, u32 data, u32 dir,
1001                   u32 mask);
1002 int hfi1_init_ctxt(struct send_context *sc);
1003 void hfi1_put_tid(struct hfi1_devdata *dd, u32 index,
1004                   u32 type, unsigned long pa, u16 order);
1005 void hfi1_quiet_serdes(struct hfi1_pportdata *ppd);
1006 void hfi1_rcvctrl(struct hfi1_devdata *dd, unsigned int op, int ctxt);
1007 u32 hfi1_read_cntrs(struct hfi1_devdata *dd, loff_t pos, char **namep,
1008                     u64 **cntrp);
1009 u32 hfi1_read_portcntrs(struct hfi1_devdata *dd, loff_t pos, u32 port,
1010                         char **namep, u64 **cntrp);
1011 u8 hfi1_ibphys_portstate(struct hfi1_pportdata *ppd);
1012 int hfi1_get_ib_cfg(struct hfi1_pportdata *ppd, int which);
1013 int hfi1_set_ib_cfg(struct hfi1_pportdata *ppd, int which, u32 val);
1014 int hfi1_set_ctxt_jkey(struct hfi1_devdata *dd, unsigned ctxt, u16 jkey);
1015 int hfi1_clear_ctxt_jkey(struct hfi1_devdata *dd, unsigned ctxt);
1016 int hfi1_set_ctxt_pkey(struct hfi1_devdata *dd, unsigned ctxt, u16 pkey);
1017 int hfi1_clear_ctxt_pkey(struct hfi1_devdata *dd, unsigned ctxt);
1018 void hfi1_read_link_quality(struct hfi1_devdata *dd, u8 *link_quality);
1019
1020 /*
1021  * Interrupt source table.
1022  *
1023  * Each entry is an interrupt source "type".  It is ordered by increasing
1024  * number.
1025  */
1026 struct is_table {
1027         int start;       /* interrupt source type start */
1028         int end;         /* interrupt source type end */
1029         /* routine that returns the name of the interrupt source */
1030         char *(*is_name)(char *name, size_t size, unsigned int source);
1031         /* routine to call when receiving an interrupt */
1032         void (*is_int)(struct hfi1_devdata *dd, unsigned int source);
1033 };
1034
1035 #endif /* _CHIP_H */