3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2015 Intel Corporation.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
21 * Copyright(c) 2015 Intel Corporation.
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24 * modification, are permitted provided that the following conditions
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34 * contributors may be used to endorse or promote products derived
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37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51 #include <linux/delay.h>
52 #include <linux/pci.h>
53 #include <linux/vmalloc.h>
59 * "Two Wire Serial Interface" support.
61 * Originally written for a not-quite-i2c serial eeprom, which is
62 * still used on some supported boards. Later boards have added a
63 * variety of other uses, most board-specific, so the bit-boffing
64 * part has been split off to this file, while the other parts
65 * have been moved to chip-specific files.
67 * We have also dropped all pretense of fully generic (e.g. pretend
68 * we don't know whether '1' is the higher voltage) interface, as
69 * the restrictions of the generic i2c interface (e.g. no access from
70 * driver itself) make it unsuitable for this use.
77 * i2c_wait_for_writes - wait for a write
78 * @dd: the hfi1_ib device
80 * We use this instead of udelay directly, so we can make sure
81 * that previous register writes have been flushed all the way
82 * to the chip. Since we are delaying anyway, the cost doesn't
83 * hurt, and makes the bit twiddling more regular
85 static void i2c_wait_for_writes(struct hfi1_devdata
*dd
, u32 target
)
88 * implicit read of EXTStatus is as good as explicit
89 * read of scratch, if all we want to do is flush
92 hfi1_gpio_mod(dd
, target
, 0, 0, 0);
93 rmb(); /* inlined, so prevent compiler reordering */
97 * QSFP modules are allowed to hold SCL low for 500uSec. Allow twice that
98 * for "almost compliant" modules
100 #define SCL_WAIT_USEC 1000
102 /* BUF_WAIT is time bus must be free between STOP or ACK and to next START.
103 * Should be 20, but some chips need more.
105 #define TWSI_BUF_WAIT_USEC 60
107 static void scl_out(struct hfi1_devdata
*dd
, u32 target
, u8 bit
)
113 mask
= QSFP_HFI0_I2CCLK
;
115 /* SCL is meant to be bare-drain, so never set "OUT", just DIR */
116 hfi1_gpio_mod(dd
, target
, 0, bit
? 0 : mask
, mask
);
119 * Allow for slow slaves by simple
120 * delay for falling edge, sampling on rise.
127 for (rise_usec
= SCL_WAIT_USEC
; rise_usec
> 0; rise_usec
-= 2) {
128 if (mask
& hfi1_gpio_mod(dd
, target
, 0, 0, 0))
133 dd_dev_err(dd
, "SCL interface stuck low > %d uSec\n",
136 i2c_wait_for_writes(dd
, target
);
139 static void sda_out(struct hfi1_devdata
*dd
, u32 target
, u8 bit
)
143 mask
= QSFP_HFI0_I2CDAT
;
145 /* SDA is meant to be bare-drain, so never set "OUT", just DIR */
146 hfi1_gpio_mod(dd
, target
, 0, bit
? 0 : mask
, mask
);
148 i2c_wait_for_writes(dd
, target
);
152 static u8
sda_in(struct hfi1_devdata
*dd
, u32 target
, int wait
)
156 mask
= QSFP_HFI0_I2CDAT
;
157 /* SDA is meant to be bare-drain, so never set "OUT", just DIR */
158 hfi1_gpio_mod(dd
, target
, 0, 0, mask
);
159 read_val
= hfi1_gpio_mod(dd
, target
, 0, 0, 0);
161 i2c_wait_for_writes(dd
, target
);
162 return (read_val
& mask
) >> GPIO_SDA_NUM
;
166 * i2c_ackrcv - see if ack following write is true
167 * @dd: the hfi1_ib device
169 static int i2c_ackrcv(struct hfi1_devdata
*dd
, u32 target
)
173 /* AT ENTRY SCL = LOW */
174 /* change direction, ignore data */
175 ack_received
= sda_in(dd
, target
, 1);
176 scl_out(dd
, target
, 1);
177 ack_received
= sda_in(dd
, target
, 1) == 0;
178 scl_out(dd
, target
, 0);
182 static void stop_cmd(struct hfi1_devdata
*dd
, u32 target
);
185 * rd_byte - read a byte, sending STOP on last, else ACK
186 * @dd: the hfi1_ib device
188 * Returns byte shifted out of device
190 static int rd_byte(struct hfi1_devdata
*dd
, u32 target
, int last
)
196 for (bit_cntr
= 7; bit_cntr
>= 0; --bit_cntr
) {
198 scl_out(dd
, target
, 1);
199 data
|= sda_in(dd
, target
, 0);
200 scl_out(dd
, target
, 0);
203 scl_out(dd
, target
, 1);
204 stop_cmd(dd
, target
);
206 sda_out(dd
, target
, 0);
207 scl_out(dd
, target
, 1);
208 scl_out(dd
, target
, 0);
209 sda_out(dd
, target
, 1);
215 * wr_byte - write a byte, one bit at a time
216 * @dd: the hfi1_ib device
217 * @data: the byte to write
219 * Returns 0 if we got the following ack, otherwise 1
221 static int wr_byte(struct hfi1_devdata
*dd
, u32 target
, u8 data
)
226 for (bit_cntr
= 7; bit_cntr
>= 0; bit_cntr
--) {
227 bit
= (data
>> bit_cntr
) & 1;
228 sda_out(dd
, target
, bit
);
229 scl_out(dd
, target
, 1);
230 scl_out(dd
, target
, 0);
232 return (!i2c_ackrcv(dd
, target
)) ? 1 : 0;
236 * issue TWSI start sequence:
237 * (both clock/data high, clock high, data low while clock is high)
239 static void start_seq(struct hfi1_devdata
*dd
, u32 target
)
241 sda_out(dd
, target
, 1);
242 scl_out(dd
, target
, 1);
243 sda_out(dd
, target
, 0);
245 scl_out(dd
, target
, 0);
249 * stop_seq - transmit the stop sequence
250 * @dd: the hfi1_ib device
252 * (both clock/data low, clock high, data high while clock is high)
254 static void stop_seq(struct hfi1_devdata
*dd
, u32 target
)
256 scl_out(dd
, target
, 0);
257 sda_out(dd
, target
, 0);
258 scl_out(dd
, target
, 1);
259 sda_out(dd
, target
, 1);
263 * stop_cmd - transmit the stop condition
264 * @dd: the hfi1_ib device
266 * (both clock/data low, clock high, data high while clock is high)
268 static void stop_cmd(struct hfi1_devdata
*dd
, u32 target
)
270 stop_seq(dd
, target
);
271 udelay(TWSI_BUF_WAIT_USEC
);
275 * hfi1_twsi_reset - reset I2C communication
276 * @dd: the hfi1_ib device
279 int hfi1_twsi_reset(struct hfi1_devdata
*dd
, u32 target
)
281 int clock_cycles_left
= 9;
285 /* Both SCL and SDA should be high. If not, there
286 * is something wrong.
288 mask
= QSFP_HFI0_I2CCLK
| QSFP_HFI0_I2CDAT
;
291 * Force pins to desired innocuous state.
292 * This is the default power-on state with out=0 and dir=0,
293 * So tri-stated and should be floating high (barring HW problems)
295 hfi1_gpio_mod(dd
, target
, 0, 0, mask
);
298 * Clock nine times to get all listeners into a sane state.
299 * If SDA does not go high at any point, we are wedged.
300 * One vendor recommends then issuing START followed by STOP.
301 * we cannot use our "normal" functions to do that, because
302 * if SCL drops between them, another vendor's part will
303 * wedge, dropping SDA and keeping it low forever, at the end of
304 * the next transaction (even if it was not the device addressed).
305 * So our START and STOP take place with SCL held high.
307 while (clock_cycles_left
--) {
308 scl_out(dd
, target
, 0);
309 scl_out(dd
, target
, 1);
310 /* Note if SDA is high, but keep clocking to sync slave */
311 was_high
|= sda_in(dd
, target
, 0);
316 * We saw a high, which we hope means the slave is sync'd.
317 * Issue START, STOP, pause for T_BUF.
320 pins
= hfi1_gpio_mod(dd
, target
, 0, 0, 0);
321 if ((pins
& mask
) != mask
)
322 dd_dev_err(dd
, "GPIO pins not at rest: %d\n",
324 /* Drop SDA to issue START */
325 udelay(1); /* Guarantee .6 uSec setup */
326 sda_out(dd
, target
, 0);
327 udelay(1); /* Guarantee .6 uSec hold */
328 /* At this point, SCL is high, SDA low. Raise SDA for STOP */
329 sda_out(dd
, target
, 1);
330 udelay(TWSI_BUF_WAIT_USEC
);
336 #define HFI1_TWSI_START 0x100
337 #define HFI1_TWSI_STOP 0x200
339 /* Write byte to TWSI, optionally prefixed with START or suffixed with
341 * returns 0 if OK (ACK received), else != 0
343 static int twsi_wr(struct hfi1_devdata
*dd
, u32 target
, int data
, int flags
)
347 if (flags
& HFI1_TWSI_START
)
348 start_seq(dd
, target
);
350 /* Leaves SCL low (from i2c_ackrcv()) */
351 ret
= wr_byte(dd
, target
, data
);
353 if (flags
& HFI1_TWSI_STOP
)
354 stop_cmd(dd
, target
);
358 /* Added functionality for IBA7220-based cards */
359 #define HFI1_TEMP_DEV 0x98
363 * General interface for data transfer from twsi devices.
364 * One vestige of its former role is that it recognizes a device
365 * HFI1_TWSI_NO_DEV and does the correct operation for the legacy part,
366 * which responded to all TWSI device codes, interpreting them as
367 * address within device. On all other devices found on board handled by
368 * this driver, the device is followed by a one-byte "address" which selects
369 * the "register" or "offset" within the device from which data should
372 int hfi1_twsi_blk_rd(struct hfi1_devdata
*dd
, u32 target
, int dev
, int addr
,
373 void *buffer
, int len
)
380 if (dev
== HFI1_TWSI_NO_DEV
) {
381 /* legacy not-really-I2C */
382 addr
= (addr
<< 1) | READ_CMD
;
383 ret
= twsi_wr(dd
, target
, addr
, HFI1_TWSI_START
);
386 ret
= twsi_wr(dd
, target
, dev
| WRITE_CMD
, HFI1_TWSI_START
);
388 stop_cmd(dd
, target
);
393 * SFF spec claims we do _not_ stop after the addr
394 * but simply issue a start with the "read" dev-addr.
395 * Since we are implicitly waiting for ACK here,
396 * we need t_buf (nominally 20uSec) before that start,
397 * and cannot rely on the delay built in to the STOP
399 ret
= twsi_wr(dd
, target
, addr
, 0);
400 udelay(TWSI_BUF_WAIT_USEC
);
404 "Failed to write interface read addr %02X\n",
409 ret
= twsi_wr(dd
, target
, dev
| READ_CMD
, HFI1_TWSI_START
);
412 stop_cmd(dd
, target
);
418 * block devices keeps clocking data out as long as we ack,
419 * automatically incrementing the address. Some have "pages"
420 * whose boundaries will not be crossed, but the handling
421 * of these is left to the caller, who is in a better
426 * Get and store data, sending ACK if length remaining,
429 *bp
++ = rd_byte(dd
, target
, !len
);
440 * General interface for data transfer to twsi devices.
441 * One vestige of its former role is that it recognizes a device
442 * HFI1_TWSI_NO_DEV and does the correct operation for the legacy part,
443 * which responded to all TWSI device codes, interpreting them as
444 * address within device. On all other devices found on board handled by
445 * this driver, the device is followed by a one-byte "address" which selects
446 * the "register" or "offset" within the device to which data should
449 int hfi1_twsi_blk_wr(struct hfi1_devdata
*dd
, u32 target
, int dev
, int addr
,
450 const void *buffer
, int len
)
453 const u8
*bp
= buffer
;
454 int max_wait_time
, i
;
458 if (dev
== HFI1_TWSI_NO_DEV
) {
459 if (twsi_wr(dd
, target
, (addr
<< 1) | WRITE_CMD
,
465 if (twsi_wr(dd
, target
,
466 dev
| WRITE_CMD
, HFI1_TWSI_START
))
468 ret
= twsi_wr(dd
, target
, addr
, 0);
471 "Failed to write interface write addr %02X\n",
477 sub_len
= min(len
, 4);
481 for (i
= 0; i
< sub_len
; i
++)
482 if (twsi_wr(dd
, target
, *bp
++, 0))
485 stop_cmd(dd
, target
);
488 * Wait for write complete by waiting for a successful
489 * read (the chip replies with a zero after the write
490 * cmd completes, and before it writes to the eeprom.
491 * The startcmd for the read will fail the ack until
492 * the writes have completed. We do this inline to avoid
493 * the debug prints that are in the real read routine
494 * if the startcmd fails.
495 * We also use the proper device address, so it doesn't matter
496 * whether we have real eeprom_dev. Legacy likes any address.
499 while (twsi_wr(dd
, target
,
500 dev
| READ_CMD
, HFI1_TWSI_START
)) {
501 stop_cmd(dd
, target
);
502 if (!--max_wait_time
)
505 /* now read (and ignore) the resulting byte */
506 rd_byte(dd
, target
, 1);
513 stop_cmd(dd
, target
);
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