3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2015 Intel Corporation.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
21 * Copyright(c) 2015 Intel Corporation.
23 * Redistribution and use in source and binary forms, with or without
24 * modification, are permitted provided that the following conditions
27 * - Redistributions of source code must retain the above copyright
28 * notice, this list of conditions and the following disclaimer.
29 * - Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in
31 * the documentation and/or other materials provided with the
33 * - Neither the name of Intel Corporation nor the names of its
34 * contributors may be used to endorse or promote products derived
35 * from this software without specific prior written permission.
37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
40 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
46 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 #include <linux/types.h>
55 #include <linux/seqlock.h>
56 #include <linux/kernel.h>
57 #include <linux/interrupt.h>
58 #include <linux/kref.h>
59 #include <linux/workqueue.h>
60 #include <linux/kthread.h>
61 #include <linux/completion.h>
62 #include <rdma/ib_pack.h>
63 #include <rdma/ib_user_verbs.h>
64 #include <rdma/ib_mad.h>
67 struct hfi1_pportdata
;
73 #define HFI1_MAX_RDMA_ATOMIC 16
74 #define HFI1_GUIDS_PER_PORT 5
77 * Increment this value if any changes that break userspace ABI
78 * compatibility are made.
80 #define HFI1_UVERBS_ABI_VERSION 2
83 * Define an ib_cq_notify value that is not valid so we know when CQ
84 * notifications are armed.
86 #define IB_CQ_NONE (IB_CQ_NEXT_COMP + 1)
88 #define IB_SEQ_NAK (3 << 29)
90 /* AETH NAK opcode values */
91 #define IB_RNR_NAK 0x20
92 #define IB_NAK_PSN_ERROR 0x60
93 #define IB_NAK_INVALID_REQUEST 0x61
94 #define IB_NAK_REMOTE_ACCESS_ERROR 0x62
95 #define IB_NAK_REMOTE_OPERATIONAL_ERROR 0x63
96 #define IB_NAK_INVALID_RD_REQUEST 0x64
98 /* Flags for checking QP state (see ib_hfi1_state_ops[]) */
99 #define HFI1_POST_SEND_OK 0x01
100 #define HFI1_POST_RECV_OK 0x02
101 #define HFI1_PROCESS_RECV_OK 0x04
102 #define HFI1_PROCESS_SEND_OK 0x08
103 #define HFI1_PROCESS_NEXT_SEND_OK 0x10
104 #define HFI1_FLUSH_SEND 0x20
105 #define HFI1_FLUSH_RECV 0x40
106 #define HFI1_PROCESS_OR_FLUSH_SEND \
107 (HFI1_PROCESS_SEND_OK | HFI1_FLUSH_SEND)
109 /* IB Performance Manager status values */
110 #define IB_PMA_SAMPLE_STATUS_DONE 0x00
111 #define IB_PMA_SAMPLE_STATUS_STARTED 0x01
112 #define IB_PMA_SAMPLE_STATUS_RUNNING 0x02
114 /* Mandatory IB performance counter select values. */
115 #define IB_PMA_PORT_XMIT_DATA cpu_to_be16(0x0001)
116 #define IB_PMA_PORT_RCV_DATA cpu_to_be16(0x0002)
117 #define IB_PMA_PORT_XMIT_PKTS cpu_to_be16(0x0003)
118 #define IB_PMA_PORT_RCV_PKTS cpu_to_be16(0x0004)
119 #define IB_PMA_PORT_XMIT_WAIT cpu_to_be16(0x0005)
121 #define HFI1_VENDOR_IPG cpu_to_be16(0xFFA0)
123 #define IB_BTH_REQ_ACK BIT(31)
124 #define IB_BTH_SOLICITED BIT(23)
125 #define IB_BTH_MIG_REQ BIT(22)
127 #define IB_GRH_VERSION 6
128 #define IB_GRH_VERSION_MASK 0xF
129 #define IB_GRH_VERSION_SHIFT 28
130 #define IB_GRH_TCLASS_MASK 0xFF
131 #define IB_GRH_TCLASS_SHIFT 20
132 #define IB_GRH_FLOW_MASK 0xFFFFF
133 #define IB_GRH_FLOW_SHIFT 0
134 #define IB_GRH_NEXT_HDR 0x1B
136 #define IB_DEFAULT_GID_PREFIX cpu_to_be64(0xfe80000000000000ULL)
138 /* flags passed by hfi1_ib_rcv() */
140 HFI1_HAS_GRH
= (1 << 0),
149 struct ib_atomic_eth
{
150 __be32 vaddr
[2]; /* unaligned so access as 2 32-bit words */
167 __be32 atomic_ack_eth
[2];
171 struct ib_atomic_eth atomic_eth
;
174 struct hfi1_other_headers
{
180 * Note that UD packets with a GRH header are 8+40+12+8 = 68 bytes
181 * long (72 w/ imm_data). Only the first 56 bytes of the IB header
182 * will be in the eager header buffer. The remaining 12 or 16 bytes
183 * are in the data buffer.
185 struct hfi1_ib_header
{
190 struct hfi1_other_headers oth
;
192 struct hfi1_other_headers oth
;
196 struct ahg_ib_header
{
197 struct sdma_engine
*sde
;
202 struct hfi1_ib_header ibh
;
205 struct hfi1_pio_header
{
207 struct hfi1_ib_header hdr
;
211 * used for force cacheline alignment for AHG
213 struct tx_pio_header
{
214 struct hfi1_pio_header phdr
;
215 } ____cacheline_aligned
;
218 * There is one struct hfi1_mcast for each multicast GID.
219 * All attached QPs are then stored as a list of
220 * struct hfi1_mcast_qp.
222 struct hfi1_mcast_qp
{
223 struct list_head list
;
228 struct rb_node rb_node
;
230 struct list_head qp_list
;
231 wait_queue_head_t wait
;
236 /* Protection domain */
239 int user
; /* non-zero if created from user space */
245 struct ib_ah_attr attr
;
250 * This structure is used by hfi1_mmap() to validate an offset
251 * when an mmap() request is made. The vm_area_struct then uses
252 * this as its vm_private_data.
254 struct hfi1_mmap_info
{
255 struct list_head pending_mmaps
;
256 struct ib_ucontext
*context
;
264 * This structure is used to contain the head pointer, tail pointer,
265 * and completion queue entries as a single memory allocation so
266 * it can be mmap'ed into user space.
269 u32 head
; /* index of next entry to fill */
270 u32 tail
; /* index of next ib_poll_cq() entry */
272 /* these are actually size ibcq.cqe + 1 */
273 struct ib_uverbs_wc uqueue
[0];
274 struct ib_wc kqueue
[0];
279 * The completion queue structure.
283 struct kthread_work comptask
;
284 struct hfi1_devdata
*dd
;
285 spinlock_t lock
; /* protect changes in this struct */
288 struct hfi1_cq_wc
*queue
;
289 struct hfi1_mmap_info
*ip
;
293 * A segment is a linear region of low physical memory.
294 * Used by the verbs layer.
301 /* The number of hfi1_segs that fit in a page. */
302 #define HFI1_SEGSZ (PAGE_SIZE / sizeof(struct hfi1_seg))
304 struct hfi1_segarray
{
305 struct hfi1_seg segs
[HFI1_SEGSZ
];
308 struct hfi1_mregion
{
309 struct ib_pd
*pd
; /* shares refcnt of ibmr.pd */
310 u64 user_base
; /* User's address for this region */
311 u64 iova
; /* IB start address of this region */
314 u32 offset
; /* offset (bytes) to start of region */
316 u32 max_segs
; /* number of hfi1_segs in all the arrays */
317 u32 mapsz
; /* size of the map array */
318 u8 page_shift
; /* 0 - non unform/non powerof2 sizes */
319 u8 lkey_published
; /* in global table */
320 struct completion comp
; /* complete when refcount goes to zero */
322 struct hfi1_segarray
*map
[0]; /* the segments */
326 * These keep track of the copy progress within a memory region.
327 * Used by the verbs layer.
330 struct hfi1_mregion
*mr
;
331 void *vaddr
; /* kernel virtual address of segment */
332 u32 sge_length
; /* length of the SGE */
333 u32 length
; /* remaining length of the segment */
334 u16 m
; /* current index: mr->map[m] */
335 u16 n
; /* current index: mr->map[m]->segs[n] */
341 struct ib_umem
*umem
;
342 struct hfi1_mregion mr
; /* must be last */
346 * Send work request queue entry.
347 * The size of the sg_list is determined when the QP is created and stored
352 struct ib_send_wr wr
; /* don't use wr.sg_list */
353 struct ib_rdma_wr rdma_wr
;
354 struct ib_atomic_wr atomic_wr
;
355 struct ib_ud_wr ud_wr
;
357 u32 psn
; /* first packet sequence number */
358 u32 lpsn
; /* last packet sequence number */
359 u32 ssn
; /* send sequence number */
360 u32 length
; /* total length of data in sg_list */
361 struct hfi1_sge sg_list
[0];
365 * Receive work request queue entry.
366 * The size of the sg_list is determined when the QP (or SRQ) is created
367 * and stored in qp->r_rq.max_sge (or srq->rq.max_sge).
372 struct ib_sge sg_list
[0];
376 * This structure is used to contain the head pointer, tail pointer,
377 * and receive work queue entries as a single memory allocation so
378 * it can be mmap'ed into user space.
379 * Note that the wq array elements are variable size so you can't
380 * just index into the array to get the N'th element;
381 * use get_rwqe_ptr() instead.
384 u32 head
; /* new work requests posted to the head */
385 u32 tail
; /* receives pull requests from here. */
386 struct hfi1_rwqe wq
[0];
391 u32 size
; /* size of RWQE array */
393 /* protect changes in this struct */
394 spinlock_t lock ____cacheline_aligned_in_smp
;
400 struct hfi1_mmap_info
*ip
;
401 /* send signal when number of RWQEs < limit */
405 struct hfi1_sge_state
{
406 struct hfi1_sge
*sg_list
; /* next SGE to be used if any */
407 struct hfi1_sge sge
; /* progress state for the current SGE */
413 * This structure holds the information that the send tasklet needs
414 * to send a RDMA read response or atomic operation.
416 struct hfi1_ack_entry
{
422 struct hfi1_sge rdma_sge
;
428 * Variables prefixed with s_ are for the requester (sender).
429 * Variables prefixed with r_ are for the responder (receiver).
430 * Variables prefixed with ack_ are for responder replies.
432 * Common variables are protected by both r_rq.lock and s_lock in that order
433 * which only happens in modify_qp() or changing the QP 'state'.
437 /* read mostly fields above and below */
438 struct ib_ah_attr remote_ah_attr
;
439 struct ib_ah_attr alt_ah_attr
;
440 struct hfi1_qp __rcu
*next
; /* link list for QPN hash table */
441 struct hfi1_swqe
*s_wq
; /* send work queue */
442 struct hfi1_mmap_info
*ip
;
443 struct ahg_ib_header
*s_hdr
; /* next packet header to send */
444 struct sdma_engine
*s_sde
; /* current sde */
445 /* sc for UC/RC QPs - based on ah for UD */
447 unsigned long timeout_jiffies
; /* computed from timeout */
449 enum ib_mtu path_mtu
;
450 int srate_mbps
; /* s_srate (below) converted to Mbit/s */
452 u32 pmtu
; /* decoded from path_mtu */
453 u32 qkey
; /* QKEY for this QP (for UD or RD) */
454 u32 s_size
; /* send work queue size */
455 u32 s_rnr_timeout
; /* number of milliseconds for RNR timeout */
456 u32 s_ahgpsn
; /* set to the psn in the copy of the header */
458 u8 state
; /* QP state */
459 u8 allowed_ops
; /* high order bits of allowed opcodes */
461 u8 alt_timeout
; /* Alternate path timeout for this QP */
462 u8 timeout
; /* Timeout for this QP */
466 u8 s_pkey_index
; /* PKEY index to use */
467 u8 s_alt_pkey_index
; /* Alternate path PKEY index to use */
468 u8 r_max_rd_atomic
; /* max number of RDMA read/atomic to receive */
469 u8 s_max_rd_atomic
; /* max number of RDMA read/atomic to send */
470 u8 s_retry_cnt
; /* number of times to retry */
472 u8 r_min_rnr_timer
; /* retry timeout value for RNR NAKs */
473 u8 s_max_sge
; /* size of s_wq->sg_list */
476 /* start of read/write fields */
477 atomic_t refcount ____cacheline_aligned_in_smp
;
478 wait_queue_head_t wait
;
481 struct hfi1_ack_entry s_ack_queue
[HFI1_MAX_RDMA_ATOMIC
+ 1]
482 ____cacheline_aligned_in_smp
;
483 struct hfi1_sge_state s_rdma_read_sge
;
485 spinlock_t r_lock ____cacheline_aligned_in_smp
; /* used for APM */
486 unsigned long r_aflags
;
487 u64 r_wr_id
; /* ID for current receive WQE */
488 u32 r_ack_psn
; /* PSN for next ACK or atomic ACK */
489 u32 r_len
; /* total length of r_sge */
490 u32 r_rcv_len
; /* receive data len processed */
491 u32 r_psn
; /* expected rcv packet sequence number */
492 u32 r_msn
; /* message sequence number */
494 u8 r_adefered
; /* number of acks defered */
495 u8 r_state
; /* opcode of last packet received */
497 u8 r_head_ack_queue
; /* index into s_ack_queue[] */
499 struct list_head rspwait
; /* link for waiting to respond */
501 struct hfi1_sge_state r_sge
; /* current receive data */
502 struct hfi1_rq r_rq
; /* receive work queue */
504 spinlock_t s_lock ____cacheline_aligned_in_smp
;
505 struct hfi1_sge_state
*s_cur_sge
;
507 struct hfi1_swqe
*s_wqe
;
508 struct hfi1_sge_state s_sge
; /* current send request data */
509 struct hfi1_mregion
*s_rdma_mr
;
510 u32 s_cur_size
; /* size of send packet in bytes */
511 u32 s_len
; /* total length of s_sge */
512 u32 s_rdma_read_len
; /* total length of s_rdma_read_sge */
513 u32 s_next_psn
; /* PSN for next request */
514 u32 s_last_psn
; /* last response PSN processed */
515 u32 s_sending_psn
; /* lowest PSN that is being sent */
516 u32 s_sending_hpsn
; /* highest PSN that is being sent */
517 u32 s_psn
; /* current packet sequence number */
518 u32 s_ack_rdma_psn
; /* PSN for sending RDMA read responses */
519 u32 s_ack_psn
; /* PSN for acking sends and RDMA writes */
520 u32 s_head
; /* new entries added here */
521 u32 s_tail
; /* next entry to process */
522 u32 s_cur
; /* current work queue entry */
523 u32 s_acked
; /* last un-ACK'ed entry */
524 u32 s_last
; /* last completed entry */
525 u32 s_ssn
; /* SSN of tail entry */
526 u32 s_lsn
; /* limit sequence number (credit) */
527 u16 s_hdrwords
; /* size of s_hdr in 32 bit words */
530 u8 s_state
; /* opcode of last packet sent */
531 u8 s_ack_state
; /* opcode of packet to ACK */
532 u8 s_nak_state
; /* non-zero if NAK is pending */
533 u8 r_nak_state
; /* non-zero if NAK is pending */
534 u8 s_retry
; /* requester retry counter */
535 u8 s_rnr_retry
; /* requester RNR retry counter */
536 u8 s_num_rd_atomic
; /* number of RDMA read/atomic pending */
537 u8 s_tail_ack_queue
; /* index into s_ack_queue[] */
539 struct hfi1_sge_state s_ack_rdma_sge
;
540 struct timer_list s_timer
;
542 struct iowait s_iowait
;
544 struct hfi1_sge r_sg_list
[0] /* verified SGEs */
545 ____cacheline_aligned_in_smp
;
549 * This structure is used to hold commonly lookedup and computed values during
550 * the send engine progress.
552 struct hfi1_pkt_state
{
553 struct hfi1_ibdev
*dev
;
554 struct hfi1_ibport
*ibp
;
555 struct hfi1_pportdata
*ppd
;
559 * Atomic bit definitions for r_aflags.
561 #define HFI1_R_WRID_VALID 0
562 #define HFI1_R_REWIND_SGE 1
565 * Bit definitions for r_flags.
567 #define HFI1_R_REUSE_SGE 0x01
568 #define HFI1_R_RDMAR_SEQ 0x02
569 /* defer ack until end of interrupt session */
570 #define HFI1_R_RSP_DEFERED_ACK 0x04
571 /* relay ack to send engine */
572 #define HFI1_R_RSP_SEND 0x08
573 #define HFI1_R_COMM_EST 0x10
576 * Bit definitions for s_flags.
578 * HFI1_S_SIGNAL_REQ_WR - set if QP send WRs contain completion signaled
579 * HFI1_S_BUSY - send tasklet is processing the QP
580 * HFI1_S_TIMER - the RC retry timer is active
581 * HFI1_S_ACK_PENDING - an ACK is waiting to be sent after RDMA read/atomics
582 * HFI1_S_WAIT_FENCE - waiting for all prior RDMA read or atomic SWQEs
583 * before processing the next SWQE
584 * HFI1_S_WAIT_RDMAR - waiting for a RDMA read or atomic SWQE to complete
585 * before processing the next SWQE
586 * HFI1_S_WAIT_RNR - waiting for RNR timeout
587 * HFI1_S_WAIT_SSN_CREDIT - waiting for RC credits to process next SWQE
588 * HFI1_S_WAIT_DMA - waiting for send DMA queue to drain before generating
589 * next send completion entry not via send DMA
590 * HFI1_S_WAIT_PIO - waiting for a send buffer to be available
591 * HFI1_S_WAIT_TX - waiting for a struct verbs_txreq to be available
592 * HFI1_S_WAIT_DMA_DESC - waiting for DMA descriptors to be available
593 * HFI1_S_WAIT_KMEM - waiting for kernel memory to be available
594 * HFI1_S_WAIT_PSN - waiting for a packet to exit the send DMA queue
595 * HFI1_S_WAIT_ACK - waiting for an ACK packet before sending more requests
596 * HFI1_S_SEND_ONE - send one packet, request ACK, then wait for ACK
597 * HFI1_S_ECN - a BECN was queued to the send engine
599 #define HFI1_S_SIGNAL_REQ_WR 0x0001
600 #define HFI1_S_BUSY 0x0002
601 #define HFI1_S_TIMER 0x0004
602 #define HFI1_S_RESP_PENDING 0x0008
603 #define HFI1_S_ACK_PENDING 0x0010
604 #define HFI1_S_WAIT_FENCE 0x0020
605 #define HFI1_S_WAIT_RDMAR 0x0040
606 #define HFI1_S_WAIT_RNR 0x0080
607 #define HFI1_S_WAIT_SSN_CREDIT 0x0100
608 #define HFI1_S_WAIT_DMA 0x0200
609 #define HFI1_S_WAIT_PIO 0x0400
610 #define HFI1_S_WAIT_TX 0x0800
611 #define HFI1_S_WAIT_DMA_DESC 0x1000
612 #define HFI1_S_WAIT_KMEM 0x2000
613 #define HFI1_S_WAIT_PSN 0x4000
614 #define HFI1_S_WAIT_ACK 0x8000
615 #define HFI1_S_SEND_ONE 0x10000
616 #define HFI1_S_UNLIMITED_CREDIT 0x20000
617 #define HFI1_S_AHG_VALID 0x40000
618 #define HFI1_S_AHG_CLEAR 0x80000
619 #define HFI1_S_ECN 0x100000
622 * Wait flags that would prevent any packet type from being sent.
624 #define HFI1_S_ANY_WAIT_IO (HFI1_S_WAIT_PIO | HFI1_S_WAIT_TX | \
625 HFI1_S_WAIT_DMA_DESC | HFI1_S_WAIT_KMEM)
628 * Wait flags that would prevent send work requests from making progress.
630 #define HFI1_S_ANY_WAIT_SEND (HFI1_S_WAIT_FENCE | HFI1_S_WAIT_RDMAR | \
631 HFI1_S_WAIT_RNR | HFI1_S_WAIT_SSN_CREDIT | HFI1_S_WAIT_DMA | \
632 HFI1_S_WAIT_PSN | HFI1_S_WAIT_ACK)
634 #define HFI1_S_ANY_WAIT (HFI1_S_ANY_WAIT_IO | HFI1_S_ANY_WAIT_SEND)
636 #define HFI1_PSN_CREDIT 16
639 * Since struct hfi1_swqe is not a fixed size, we can't simply index into
640 * struct hfi1_qp.s_wq. This function does the array index computation.
642 static inline struct hfi1_swqe
*get_swqe_ptr(struct hfi1_qp
*qp
,
645 return (struct hfi1_swqe
*)((char *)qp
->s_wq
+
646 (sizeof(struct hfi1_swqe
) +
648 sizeof(struct hfi1_sge
)) * n
);
652 * Since struct hfi1_rwqe is not a fixed size, we can't simply index into
653 * struct hfi1_rwq.wq. This function does the array index computation.
655 static inline struct hfi1_rwqe
*get_rwqe_ptr(struct hfi1_rq
*rq
, unsigned n
)
657 return (struct hfi1_rwqe
*)
658 ((char *) rq
->wq
->wq
+
659 (sizeof(struct hfi1_rwqe
) +
660 rq
->max_sge
* sizeof(struct ib_sge
)) * n
);
663 #define MAX_LKEY_TABLE_BITS 23
665 struct hfi1_lkey_table
{
666 spinlock_t lock
; /* protect changes in this struct */
667 u32 next
; /* next unused index (speeds search) */
668 u32 gen
; /* generation count */
669 u32 max
; /* size of the table */
670 struct hfi1_mregion __rcu
**table
;
673 struct hfi1_opcode_stats
{
674 u64 n_packets
; /* number of packets */
675 u64 n_bytes
; /* total number of bytes */
678 struct hfi1_opcode_stats_perctx
{
679 struct hfi1_opcode_stats stats
[256];
682 static inline void inc_opstats(
684 struct hfi1_opcode_stats
*stats
)
686 #ifdef CONFIG_DEBUG_FS
687 stats
->n_bytes
+= tlen
;
693 struct hfi1_qp __rcu
*qp
[2];
694 struct ib_mad_agent
*send_agent
; /* agent for SMI (traps) */
695 struct hfi1_ah
*sm_ah
;
696 struct hfi1_ah
*smi_ah
;
697 struct rb_root mcast_tree
;
698 spinlock_t lock
; /* protect changes in this struct */
700 /* non-zero when timer is set */
701 unsigned long mkey_lease_timeout
;
702 unsigned long trap_timeout
;
703 __be64 gid_prefix
; /* in network order */
705 __be64 guids
[HFI1_GUIDS_PER_PORT
- 1]; /* writable GUIDs */
706 u64 tid
; /* TID for traps */
721 /* Hot-path per CPU counters to avoid cacheline trading to update */
724 u64 z_rc_delayed_comp
;
725 u64 __percpu
*rc_acks
;
726 u64 __percpu
*rc_qacks
;
727 u64 __percpu
*rc_delayed_comp
;
730 u32 pma_sample_start
;
731 u32 pma_sample_interval
;
732 __be16 pma_counter_select
[5];
737 u16 mkey_lease_period
;
744 /* the first 16 entries are sl_to_vl for !OPA */
750 struct hfi1_qp_ibdev
;
752 struct ib_device ibdev
;
753 struct list_head pending_mmaps
;
754 spinlock_t mmap_offset_lock
; /* protect mmap_offset */
756 struct hfi1_mregion __rcu
*dma_mr
;
758 struct hfi1_qp_ibdev
*qp_dev
;
760 /* QP numbers are shared by all IB ports */
761 struct hfi1_lkey_table lk_table
;
762 /* protect wait lists */
763 seqlock_t iowait_lock
;
764 struct list_head txwait
; /* list for wait verbs_txreq */
765 struct list_head memwait
; /* list for wait kernel memory */
766 struct list_head txreq_free
;
767 struct kmem_cache
*verbs_txreq_cache
;
768 struct timer_list mem_timer
;
771 spinlock_t pending_lock
;
778 u32 n_pds_allocated
; /* number of PDs allocated for device */
779 spinlock_t n_pds_lock
;
780 u32 n_ahs_allocated
; /* number of AHs allocated for device */
781 spinlock_t n_ahs_lock
;
782 u32 n_cqs_allocated
; /* number of CQs allocated for device */
783 spinlock_t n_cqs_lock
;
784 u32 n_qps_allocated
; /* number of QPs allocated for device */
785 spinlock_t n_qps_lock
;
786 u32 n_srqs_allocated
; /* number of SRQs allocated for device */
787 spinlock_t n_srqs_lock
;
788 u32 n_mcast_grps_allocated
; /* number of mcast groups allocated */
789 spinlock_t n_mcast_grps_lock
;
790 #ifdef CONFIG_DEBUG_FS
791 /* per HFI debugfs */
792 struct dentry
*hfi1_ibdev_dbg
;
793 /* per HFI symlinks to above */
794 struct dentry
*hfi1_ibdev_link
;
798 struct hfi1_verbs_counters
{
799 u64 symbol_error_counter
;
800 u64 link_error_recovery_counter
;
801 u64 link_downed_counter
;
803 u64 port_rcv_remphys_errors
;
804 u64 port_xmit_discards
;
807 u64 port_xmit_packets
;
808 u64 port_rcv_packets
;
809 u32 local_link_integrity_errors
;
810 u32 excessive_buffer_overrun_errors
;
814 static inline struct hfi1_mr
*to_imr(struct ib_mr
*ibmr
)
816 return container_of(ibmr
, struct hfi1_mr
, ibmr
);
819 static inline struct hfi1_pd
*to_ipd(struct ib_pd
*ibpd
)
821 return container_of(ibpd
, struct hfi1_pd
, ibpd
);
824 static inline struct hfi1_ah
*to_iah(struct ib_ah
*ibah
)
826 return container_of(ibah
, struct hfi1_ah
, ibah
);
829 static inline struct hfi1_cq
*to_icq(struct ib_cq
*ibcq
)
831 return container_of(ibcq
, struct hfi1_cq
, ibcq
);
834 static inline struct hfi1_srq
*to_isrq(struct ib_srq
*ibsrq
)
836 return container_of(ibsrq
, struct hfi1_srq
, ibsrq
);
839 static inline struct hfi1_qp
*to_iqp(struct ib_qp
*ibqp
)
841 return container_of(ibqp
, struct hfi1_qp
, ibqp
);
844 static inline struct hfi1_ibdev
*to_idev(struct ib_device
*ibdev
)
846 return container_of(ibdev
, struct hfi1_ibdev
, ibdev
);
850 * Send if not busy or waiting for I/O and either
851 * a RC response is pending or we can process send work requests.
853 static inline int hfi1_send_ok(struct hfi1_qp
*qp
)
855 return !(qp
->s_flags
& (HFI1_S_BUSY
| HFI1_S_ANY_WAIT_IO
)) &&
856 (qp
->s_hdrwords
|| (qp
->s_flags
& HFI1_S_RESP_PENDING
) ||
857 !(qp
->s_flags
& HFI1_S_ANY_WAIT_SEND
));
861 * This must be called with s_lock held.
863 void hfi1_bad_pqkey(struct hfi1_ibport
*ibp
, __be16 trap_num
, u32 key
, u32 sl
,
864 u32 qp1
, u32 qp2
, u16 lid1
, u16 lid2
);
865 void hfi1_cap_mask_chg(struct hfi1_ibport
*ibp
);
866 void hfi1_sys_guid_chg(struct hfi1_ibport
*ibp
);
867 void hfi1_node_desc_chg(struct hfi1_ibport
*ibp
);
868 int hfi1_process_mad(struct ib_device
*ibdev
, int mad_flags
, u8 port
,
869 const struct ib_wc
*in_wc
, const struct ib_grh
*in_grh
,
870 const struct ib_mad_hdr
*in_mad
, size_t in_mad_size
,
871 struct ib_mad_hdr
*out_mad
, size_t *out_mad_size
,
872 u16
*out_mad_pkey_index
);
873 int hfi1_create_agents(struct hfi1_ibdev
*dev
);
874 void hfi1_free_agents(struct hfi1_ibdev
*dev
);
877 * The PSN_MASK and PSN_SHIFT allow for
878 * 1) comparing two PSNs
879 * 2) returning the PSN with any upper bits masked
880 * 3) returning the difference between to PSNs
882 * The number of significant bits in the PSN must
883 * necessarily be at least one bit less than
884 * the container holding the PSN.
886 #ifndef CONFIG_HFI1_VERBS_31BIT_PSN
887 #define PSN_MASK 0xFFFFFF
890 #define PSN_MASK 0x7FFFFFFF
893 #define PSN_MODIFY_MASK 0xFFFFFF
895 /* Number of bits to pay attention to in the opcode for checking qp type */
896 #define OPCODE_QP_MASK 0xE0
899 * Compare the lower 24 bits of the msn values.
900 * Returns an integer <, ==, or > than zero.
902 static inline int cmp_msn(u32 a
, u32 b
)
904 return (((int) a
) - ((int) b
)) << 8;
909 * Returns an integer <, ==, or > than zero.
911 static inline int cmp_psn(u32 a
, u32 b
)
913 return (((int) a
) - ((int) b
)) << PSN_SHIFT
;
919 static inline u32
mask_psn(u32 a
)
925 * Return delta between two PSNs
927 static inline u32
delta_psn(u32 a
, u32 b
)
929 return (((int)a
- (int)b
) << PSN_SHIFT
) >> PSN_SHIFT
;
932 struct hfi1_mcast
*hfi1_mcast_find(struct hfi1_ibport
*ibp
, union ib_gid
*mgid
);
934 int hfi1_multicast_attach(struct ib_qp
*ibqp
, union ib_gid
*gid
, u16 lid
);
936 int hfi1_multicast_detach(struct ib_qp
*ibqp
, union ib_gid
*gid
, u16 lid
);
938 int hfi1_mcast_tree_empty(struct hfi1_ibport
*ibp
);
941 void hfi1_put_txreq(struct verbs_txreq
*tx
);
943 int hfi1_verbs_send(struct hfi1_qp
*qp
, struct hfi1_pkt_state
*ps
);
945 void hfi1_copy_sge(struct hfi1_sge_state
*ss
, void *data
, u32 length
,
948 void hfi1_skip_sge(struct hfi1_sge_state
*ss
, u32 length
, int release
);
950 void hfi1_cnp_rcv(struct hfi1_packet
*packet
);
952 void hfi1_uc_rcv(struct hfi1_packet
*packet
);
954 void hfi1_rc_rcv(struct hfi1_packet
*packet
);
957 struct hfi1_ctxtdata
*rcd
,
958 struct hfi1_ib_header
*hdr
,
962 u8
ah_to_sc(struct ib_device
*ibdev
, struct ib_ah_attr
*ah_attr
);
964 int hfi1_check_ah(struct ib_device
*ibdev
, struct ib_ah_attr
*ah_attr
);
966 struct ib_ah
*hfi1_create_qp0_ah(struct hfi1_ibport
*ibp
, u16 dlid
);
968 void hfi1_rc_rnr_retry(unsigned long arg
);
970 void hfi1_rc_send_complete(struct hfi1_qp
*qp
, struct hfi1_ib_header
*hdr
);
972 void hfi1_rc_error(struct hfi1_qp
*qp
, enum ib_wc_status err
);
974 void hfi1_ud_rcv(struct hfi1_packet
*packet
);
976 int hfi1_lookup_pkey_idx(struct hfi1_ibport
*ibp
, u16 pkey
);
978 int hfi1_alloc_lkey(struct hfi1_mregion
*mr
, int dma_region
);
980 void hfi1_free_lkey(struct hfi1_mregion
*mr
);
982 int hfi1_lkey_ok(struct hfi1_lkey_table
*rkt
, struct hfi1_pd
*pd
,
983 struct hfi1_sge
*isge
, struct ib_sge
*sge
, int acc
);
985 int hfi1_rkey_ok(struct hfi1_qp
*qp
, struct hfi1_sge
*sge
,
986 u32 len
, u64 vaddr
, u32 rkey
, int acc
);
988 int hfi1_post_srq_receive(struct ib_srq
*ibsrq
, struct ib_recv_wr
*wr
,
989 struct ib_recv_wr
**bad_wr
);
991 struct ib_srq
*hfi1_create_srq(struct ib_pd
*ibpd
,
992 struct ib_srq_init_attr
*srq_init_attr
,
993 struct ib_udata
*udata
);
995 int hfi1_modify_srq(struct ib_srq
*ibsrq
, struct ib_srq_attr
*attr
,
996 enum ib_srq_attr_mask attr_mask
,
997 struct ib_udata
*udata
);
999 int hfi1_query_srq(struct ib_srq
*ibsrq
, struct ib_srq_attr
*attr
);
1001 int hfi1_destroy_srq(struct ib_srq
*ibsrq
);
1003 int hfi1_cq_init(struct hfi1_devdata
*dd
);
1005 void hfi1_cq_exit(struct hfi1_devdata
*dd
);
1007 void hfi1_cq_enter(struct hfi1_cq
*cq
, struct ib_wc
*entry
, int sig
);
1009 int hfi1_poll_cq(struct ib_cq
*ibcq
, int num_entries
, struct ib_wc
*entry
);
1011 struct ib_cq
*hfi1_create_cq(
1012 struct ib_device
*ibdev
,
1013 const struct ib_cq_init_attr
*attr
,
1014 struct ib_ucontext
*context
,
1015 struct ib_udata
*udata
);
1017 int hfi1_destroy_cq(struct ib_cq
*ibcq
);
1019 int hfi1_req_notify_cq(
1021 enum ib_cq_notify_flags notify_flags
);
1023 int hfi1_resize_cq(struct ib_cq
*ibcq
, int cqe
, struct ib_udata
*udata
);
1025 struct ib_mr
*hfi1_get_dma_mr(struct ib_pd
*pd
, int acc
);
1027 struct ib_mr
*hfi1_reg_user_mr(struct ib_pd
*pd
, u64 start
, u64 length
,
1028 u64 virt_addr
, int mr_access_flags
,
1029 struct ib_udata
*udata
);
1031 int hfi1_dereg_mr(struct ib_mr
*ibmr
);
1033 struct ib_mr
*hfi1_alloc_mr(struct ib_pd
*pd
,
1034 enum ib_mr_type mr_type
,
1037 struct ib_fmr
*hfi1_alloc_fmr(struct ib_pd
*pd
, int mr_access_flags
,
1038 struct ib_fmr_attr
*fmr_attr
);
1040 int hfi1_map_phys_fmr(struct ib_fmr
*ibfmr
, u64
*page_list
,
1041 int list_len
, u64 iova
);
1043 int hfi1_unmap_fmr(struct list_head
*fmr_list
);
1045 int hfi1_dealloc_fmr(struct ib_fmr
*ibfmr
);
1047 static inline void hfi1_get_mr(struct hfi1_mregion
*mr
)
1049 atomic_inc(&mr
->refcount
);
1052 static inline void hfi1_put_mr(struct hfi1_mregion
*mr
)
1054 if (unlikely(atomic_dec_and_test(&mr
->refcount
)))
1055 complete(&mr
->comp
);
1058 static inline void hfi1_put_ss(struct hfi1_sge_state
*ss
)
1060 while (ss
->num_sge
) {
1061 hfi1_put_mr(ss
->sge
.mr
);
1063 ss
->sge
= *ss
->sg_list
++;
1067 void hfi1_release_mmap_info(struct kref
*ref
);
1069 struct hfi1_mmap_info
*hfi1_create_mmap_info(struct hfi1_ibdev
*dev
, u32 size
,
1070 struct ib_ucontext
*context
,
1073 void hfi1_update_mmap_info(struct hfi1_ibdev
*dev
, struct hfi1_mmap_info
*ip
,
1074 u32 size
, void *obj
);
1076 int hfi1_mmap(struct ib_ucontext
*context
, struct vm_area_struct
*vma
);
1078 int hfi1_get_rwqe(struct hfi1_qp
*qp
, int wr_id_only
);
1080 int hfi1_ruc_check_hdr(struct hfi1_ibport
*ibp
, struct hfi1_ib_header
*hdr
,
1081 int has_grh
, struct hfi1_qp
*qp
, u32 bth0
);
1083 u32
hfi1_make_grh(struct hfi1_ibport
*ibp
, struct ib_grh
*hdr
,
1084 struct ib_global_route
*grh
, u32 hwords
, u32 nwords
);
1086 void hfi1_make_ruc_header(struct hfi1_qp
*qp
, struct hfi1_other_headers
*ohdr
,
1087 u32 bth0
, u32 bth2
, int middle
);
1089 void hfi1_do_send(struct work_struct
*work
);
1091 void hfi1_send_complete(struct hfi1_qp
*qp
, struct hfi1_swqe
*wqe
,
1092 enum ib_wc_status status
);
1094 void hfi1_send_rc_ack(struct hfi1_ctxtdata
*, struct hfi1_qp
*qp
, int is_fecn
);
1096 int hfi1_make_rc_req(struct hfi1_qp
*qp
);
1098 int hfi1_make_uc_req(struct hfi1_qp
*qp
);
1100 int hfi1_make_ud_req(struct hfi1_qp
*qp
);
1102 int hfi1_register_ib_device(struct hfi1_devdata
*);
1104 void hfi1_unregister_ib_device(struct hfi1_devdata
*);
1106 void hfi1_ib_rcv(struct hfi1_packet
*packet
);
1108 unsigned hfi1_get_npkeys(struct hfi1_devdata
*);
1110 int hfi1_verbs_send_dma(struct hfi1_qp
*qp
, struct hfi1_pkt_state
*ps
,
1113 int hfi1_verbs_send_pio(struct hfi1_qp
*qp
, struct hfi1_pkt_state
*ps
,
1116 struct send_context
*qp_to_send_context(struct hfi1_qp
*qp
, u8 sc5
);
1118 extern const enum ib_wc_opcode ib_hfi1_wc_opcode
[];
1120 extern const u8 hdr_len_by_opcode
[];
1122 extern const int ib_hfi1_state_ops
[];
1124 extern __be64 ib_hfi1_sys_image_guid
; /* in network order */
1126 extern unsigned int hfi1_lkey_table_size
;
1128 extern unsigned int hfi1_max_cqes
;
1130 extern unsigned int hfi1_max_cqs
;
1132 extern unsigned int hfi1_max_qp_wrs
;
1134 extern unsigned int hfi1_max_qps
;
1136 extern unsigned int hfi1_max_sges
;
1138 extern unsigned int hfi1_max_mcast_grps
;
1140 extern unsigned int hfi1_max_mcast_qp_attached
;
1142 extern unsigned int hfi1_max_srqs
;
1144 extern unsigned int hfi1_max_srq_sges
;
1146 extern unsigned int hfi1_max_srq_wrs
;
1148 extern const u32 ib_hfi1_rnr_table
[];
1150 extern struct ib_dma_mapping_ops hfi1_dma_mapping_ops
;
1152 #endif /* HFI1_VERBS_H */