drivers/staging/rtl8188eu/include/rtl8188e_hal.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 #ifndef __RTL8188E_HAL_H__
  21 #define __RTL8188E_HAL_H__
  22
  23
  24 /* include HAL Related header after HAL Related compiling flags */
  25 #include "rtl8188e_spec.h"
  26 #include "Hal8188EPhyReg.h"
  27 #include "Hal8188EPhyCfg.h"
  28 #include "rtl8188e_rf.h"
  29 #include "rtl8188e_dm.h"
  30 #include "rtl8188e_recv.h"
  31 #include "rtl8188e_xmit.h"
  32 #include "rtl8188e_cmd.h"
  33 #include "Hal8188EPwrSeq.h"
  34 #include "rtl8188e_sreset.h"
  35 #include "rtw_efuse.h"
  36
  37 #include "odm_precomp.h"
  38
  39 /*  Fw Array */
  40 #define Rtl8188E_FwImageArray           Rtl8188EFwImgArray
  41 #define Rtl8188E_FWImgArrayLength       Rtl8188EFWImgArrayLength
  42
  43 #define RTL8188E_FW_UMC_IMG                     "rtl8188E\\rtl8188efw.bin"
  44 #define RTL8188E_PHY_REG                        "rtl8188E\\PHY_REG_1T.txt"
  45 #define RTL8188E_PHY_RADIO_A                    "rtl8188E\\radio_a_1T.txt"
  46 #define RTL8188E_PHY_RADIO_B                    "rtl8188E\\radio_b_1T.txt"
  47 #define RTL8188E_AGC_TAB                        "rtl8188E\\AGC_TAB_1T.txt"
  48 #define RTL8188E_PHY_MACREG                     "rtl8188E\\MAC_REG.txt"
  49 #define RTL8188E_PHY_REG_PG                     "rtl8188E\\PHY_REG_PG.txt"
  50 #define RTL8188E_PHY_REG_MP                     "rtl8188E\\PHY_REG_MP.txt"
  51
  52 /*              RTL8188E Power Configuration CMDs for USB/SDIO interfaces */
  53 #define Rtl8188E_NIC_PWR_ON_FLOW                rtl8188E_power_on_flow
  54 #define Rtl8188E_NIC_RF_OFF_FLOW                rtl8188E_radio_off_flow
  55 #define Rtl8188E_NIC_DISABLE_FLOW               rtl8188E_card_disable_flow
  56 #define Rtl8188E_NIC_ENABLE_FLOW                rtl8188E_card_enable_flow
  57 #define Rtl8188E_NIC_SUSPEND_FLOW               rtl8188E_suspend_flow
  58 #define Rtl8188E_NIC_RESUME_FLOW                rtl8188E_resume_flow
  59 #define Rtl8188E_NIC_PDN_FLOW                   rtl8188E_hwpdn_flow
  60 #define Rtl8188E_NIC_LPS_ENTER_FLOW             rtl8188E_enter_lps_flow
  61 #define Rtl8188E_NIC_LPS_LEAVE_FLOW             rtl8188E_leave_lps_flow
  62
  63 #define DRVINFO_SZ      4 /*  unit is 8bytes */
  64 #define PageNum_128(_Len)       (u32)(((_Len)>>7) + ((_Len) & 0x7F ? 1 : 0))
  65
  66 /*  download firmware related data structure */
  67 #define FW_8188E_SIZE                   0x4000 /* 16384,16k */
  68 #define FW_8188E_START_ADDRESS          0x1000
  69 #define FW_8188E_END_ADDRESS            0x1FFF /* 0x5FFF */
  70
  71 #define MAX_PAGE_SIZE                   4096    /*  @ page : 4k bytes */
  72
  73 #define IS_FW_HEADER_EXIST(_pFwHdr)                             \
  74         ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||  \
  75         (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||   \
  76         (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x2300 ||   \
  77         (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88E0)
  78
  79 enum firmware_source {
  80         FW_SOURCE_IMG_FILE = 0,
  81         FW_SOURCE_HEADER_FILE = 1,              /* from header file */
  82 };
  83
  84 struct rt_firmware {
  85         enum firmware_source    eFWSource;
  86         u8                      *szFwBuffer;
  87         u32                     ulFwLength;
  88 };
  89
  90 /*  This structure must be careful with byte-ordering */
  91
  92 struct rt_firmware_hdr {
  93         /*  8-byte alinment required */
  94         /*  LONG WORD 0 ---- */
  95         __le16          Signature;      /* 92C0: test chip; 92C,
  96                                          * 88C0: test chip; 88C1: MP A-cut;
  97                                          * 92C1: MP A-cut */
  98         u8              Category;       /*  AP/NIC and USB/PCI */
  99         u8              Function;       /*  Reserved for different FW function
 100                                          *  indcation, for further use when
 101                                          *  driver needs to download different
 102                                          *  FW for different conditions */
 103         __le16          Version;        /*  FW Version */
 104         u8              Subversion;     /*  FW Subversion, default 0x00 */
 105         u16             Rsvd1;
 106
 107         /*  LONG WORD 1 ---- */
 108         u8              Month;  /*  Release time Month field */
 109         u8              Date;   /*  Release time Date field */
 110         u8              Hour;   /*  Release time Hour field */
 111         u8              Minute; /*  Release time Minute field */
 112         __le16          RamCodeSize;    /*  The size of RAM code */
 113         u8              Foundry;
 114         u8              Rsvd2;
 115
 116         /*  LONG WORD 2 ---- */
 117         __le32          SvnIdx; /*  The SVN entry index */
 118         u32             Rsvd3;
 119
 120         /*  LONG WORD 3 ---- */
 121         u32             Rsvd4;
 122         u32             Rsvd5;
 123 };
 124
 125 #define DRIVER_EARLY_INT_TIME           0x05
 126 #define BCN_DMA_ATIME_INT_TIME          0x02
 127
 128 enum usb_rx_agg_mode {
 129         USB_RX_AGG_DISABLE,
 130         USB_RX_AGG_DMA,
 131         USB_RX_AGG_USB,
 132         USB_RX_AGG_MIX
 133 };
 134
 135 #define MAX_RX_DMA_BUFFER_SIZE_88E                              \
 136       0x2400 /* 9k for 88E nornal chip , MaxRxBuff=10k-max(TxReportSize(64*8),
 137               * WOLPattern(16*24)) */
 138
 139 #define MAX_TX_REPORT_BUFFER_SIZE               0x0400 /*  1k */
 140
 141
 142 /*  BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON. */
 143 #define MAX_TX_QUEUE                    9
 144
 145 #define TX_SELE_HQ                      BIT(0)          /*  High Queue */
 146 #define TX_SELE_LQ                      BIT(1)          /*  Low Queue */
 147 #define TX_SELE_NQ                      BIT(2)          /*  Normal Queue */
 148
 149 /*  Note: We will divide number of page equally for each queue other
 150  *  than public queue! */
 151 /*  22k = 22528 bytes = 176 pages (@page =  128 bytes) */
 152 /*  must reserved about 7 pages for LPS =>  176-7 = 169 (0xA9) */
 153 /*  2*BCN / 1*ps-poll / 1*null-data /1*prob_rsp /1*QOS null-data /1*BT QOS
 154  *  null-data */
 155
 156 #define TX_TOTAL_PAGE_NUMBER_88E                0xA9/*   169 (21632=> 21k) */
 157
 158 #define TX_PAGE_BOUNDARY_88E (TX_TOTAL_PAGE_NUMBER_88E + 1)
 159
 160 /* Note: For Normal Chip Setting ,modify later */
 161 #define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER                 \
 162         TX_TOTAL_PAGE_NUMBER_88E  /* 0xA9 , 0xb0=>176=>22k */
 163 #define WMM_NORMAL_TX_PAGE_BOUNDARY_88E                 \
 164         (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER + 1) /* 0xA9 */
 165
 166 /*      Chip specific */
 167 #define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
 168 #define CHIP_BONDING_92C_1T2R   0x1
 169 #define CHIP_BONDING_88C_USB_MCARD      0x2
 170 #define CHIP_BONDING_88C_USB_HP 0x1
 171 #include "HalVerDef.h"
 172 #include "hal_com.h"
 173
 174 /*      Channel Plan */
 175 enum ChannelPlan {
 176         CHPL_FCC        = 0,
 177         CHPL_IC         = 1,
 178         CHPL_ETSI       = 2,
 179         CHPL_SPA        = 3,
 180         CHPL_FRANCE     = 4,
 181         CHPL_MKK        = 5,
 182         CHPL_MKK1       = 6,
 183         CHPL_ISRAEL     = 7,
 184         CHPL_TELEC      = 8,
 185         CHPL_GLOBAL     = 9,
 186         CHPL_WORLD      = 10,
 187 };
 188
 189 struct txpowerinfo24g {
 190         u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
 191         u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
 192         /* If only one tx, only BW20 and OFDM are used. */
 193         s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 194         s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 195         s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 196         s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 197 };
 198
 199 #define EFUSE_REAL_CONTENT_LEN          512
 200 #define EFUSE_MAX_SECTION               16
 201 #define EFUSE_IC_ID_OFFSET              506 /* For some inferior IC purpose*/
 202 #define AVAILABLE_EFUSE_ADDR(addr)      (addr < EFUSE_REAL_CONTENT_LEN)
 203 /*  To prevent out of boundary programming case, */
 204 /*  leave 1byte and program full section */
 205 /*  9bytes + 1byt + 5bytes and pre 1byte. */
 206 /*  For worst case: */
 207 /*  | 1byte|----8bytes----|1byte|--5bytes--| */
 208 /*  |         |            Reserved(14bytes)          | */
 209
 210 /*  PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. */
 211 #define EFUSE_OOB_PROTECT_BYTES                 15
 212
 213 #define         HWSET_MAX_SIZE_88E              512
 214
 215 #define         EFUSE_REAL_CONTENT_LEN_88E      256
 216 #define         EFUSE_MAP_LEN_88E               512
 217 #define EFUSE_MAP_LEN                   EFUSE_MAP_LEN_88E
 218 #define         EFUSE_MAX_SECTION_88E           64
 219 #define         EFUSE_MAX_WORD_UNIT_88E         4
 220 #define         EFUSE_IC_ID_OFFSET_88E          506
 221 #define         AVAILABLE_EFUSE_ADDR_88E(addr)                  \
 222         (addr < EFUSE_REAL_CONTENT_LEN_88E)
 223 /*  To prevent out of boundary programming case, leave 1byte and program
 224  *  full section */
 225 /*  9bytes + 1byt + 5bytes and pre 1byte. */
 226 /*  For worst case: */
 227 /*  | 2byte|----8bytes----|1byte|--7bytes--| 92D */
 228 /*  PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte. */
 229 #define         EFUSE_OOB_PROTECT_BYTES_88E     18
 230 #define         EFUSE_PROTECT_BYTES_BANK_88E    16
 231
 232 /*                      EFUSE for BT definition */
 233 #define EFUSE_BT_REAL_CONTENT_LEN       1536    /*  512*3 */
 234 #define EFUSE_BT_MAP_LEN                1024    /*  1k bytes */
 235 #define EFUSE_BT_MAX_SECTION            128     /*  1024/8 */
 236
 237 #define EFUSE_PROTECT_BYTES_BANK        16
 238
 239 /*  For RTL8723 WiFi/BT/GPS multi-function configuration. */
 240 enum rt_multi_func {
 241         RT_MULTI_FUNC_NONE = 0x00,
 242         RT_MULTI_FUNC_WIFI = 0x01,
 243         RT_MULTI_FUNC_BT = 0x02,
 244         RT_MULTI_FUNC_GPS = 0x04,
 245 };
 246
 247 /*  For RTL8723 regulator mode. */
 248 enum rt_regulator_mode {
 249         RT_SWITCHING_REGULATOR = 0,
 250         RT_LDO_REGULATOR = 1,
 251 };
 252
 253 struct hal_data_8188e {
 254         struct HAL_VERSION      VersionID;
 255         enum rt_multi_func MultiFunc; /*  For multi-function consideration. */
 256         enum rt_regulator_mode RegulatorMode; /*  switching regulator or LDO */
 257         u16     CustomerID;
 258
 259         u16     FirmwareVersion;
 260         u16     FirmwareVersionRev;
 261         u16     FirmwareSubVersion;
 262         u16     FirmwareSignature;
 263         u8      PGMaxGroup;
 264         /* current WIFI_PHY values */
 265         u32     ReceiveConfig;
 266         enum wireless_mode CurrentWirelessMode;
 267         enum ht_channel_width CurrentChannelBW;
 268         u8      CurrentChannel;
 269         u8      nCur40MhzPrimeSC;/*  Control channel sub-carrier */
 270
 271         u16     BasicRateSet;
 272
 273         /* rf_ctrl */
 274         u8      rf_chip;
 275         u8      rf_type;
 276         u8      NumTotalRFPath;
 277
 278         u8      BoardType;
 279
 280         /*  EEPROM setting. */
 281         u16     EEPROMVID;
 282         u16     EEPROMPID;
 283         u16     EEPROMSVID;
 284         u16     EEPROMSDID;
 285         u8      EEPROMCustomerID;
 286         u8      EEPROMSubCustomerID;
 287         u8      EEPROMVersion;
 288         u8      EEPROMRegulatory;
 289
 290         u8      bTXPowerDataReadFromEEPORM;
 291         u8      EEPROMThermalMeter;
 292         u8      bAPKThermalMeterIgnore;
 293
 294         bool    EepromOrEfuse;
 295         /* 92C:256bytes, 88E:512bytes, we use union set (512bytes) */
 296         u8      EfuseMap[2][HWSET_MAX_SIZE_512];
 297         u8      EfuseUsedPercentage;
 298         struct efuse_hal        EfuseHal;
 299
 300         u8      Index24G_CCK_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
 301         u8      Index24G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
 302         /* If only one tx, only BW20 and OFDM are used. */
 303         s8      CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 304         s8      OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 305         s8      BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 306         s8      BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 307
 308         u8      TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 309         /*  For HT 40MHZ pwr */
 310         u8      TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 311         /*  For HT 40MHZ pwr */
 312         u8      TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 313         /*  HT 20<->40 Pwr diff */
 314         u8      TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 315         /*  For HT<->legacy pwr diff */
 316         u8      TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 317         /*  For power group */
 318         u8      PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 319         u8      PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 320
 321         u8      LegacyHTTxPowerDiff;/*  Legacy to HT rate power diff */
 322         /*  The current Tx Power Level */
 323         u8      CurrentCckTxPwrIdx;
 324         u8      CurrentOfdm24GTxPwrIdx;
 325         u8      CurrentBW2024GTxPwrIdx;
 326         u8      CurrentBW4024GTxPwrIdx;
 327
 328
 329         /*  Read/write are allow for following hardware information variables */
 330         u8      framesync;
 331         u32     framesyncC34;
 332         u8      framesyncMonitor;
 333         u8      DefaultInitialGain[4];
 334         u8      pwrGroupCnt;
 335         u32     MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16];
 336         u32     CCKTxPowerLevelOriginalOffset;
 337
 338         u8      CrystalCap;
 339         u32     AntennaTxPath;                  /*  Antenna path Tx */
 340         u32     AntennaRxPath;                  /*  Antenna path Rx */
 341         u8      BluetoothCoexist;
 342         u8      ExternalPA;
 343
 344         u8      bLedOpenDrain; /* Open-drain support for controlling the LED.*/
 345
 346         u8      b1x1RecvCombine;        /*  for 1T1R receive combining */
 347
 348         u32     AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */
 349
 350         struct bb_reg_def PHYRegDef[4]; /* Radio A/B/C/D */
 351
 352         u32     RfRegChnlVal[2];
 353
 354         /* RDG enable */
 355         bool     bRDGEnable;
 356
 357         /* for host message to fw */
 358         u8      LastHMEBoxNum;
 359
 360         u8      fw_ractrl;
 361         u8      RegTxPause;
 362         /*  Beacon function related global variable. */
 363         u32     RegBcnCtrlVal;
 364         u8      RegFwHwTxQCtrl;
 365         u8      RegReg542;
 366         u8      RegCR_1;
 367
 368         struct dm_priv  dmpriv;
 369         struct odm_dm_struct odmpriv;
 370         struct sreset_priv srestpriv;
 371
 372         u8      CurAntenna;
 373         u8      AntDivCfg;
 374         u8      TRxAntDivType;
 375
 376
 377         u8      bDumpRxPkt;/* for debug */
 378         u8      bDumpTxPkt;/* for debug */
 379         u8      FwRsvdPageStartOffset; /* Reserve page start offset except
 380                                         *  beacon in TxQ. */
 381
 382         /*  2010/08/09 MH Add CU power down mode. */
 383         bool            pwrdown;
 384
 385         /*  Add for dual MAC  0--Mac0 1--Mac1 */
 386         u32     interfaceIndex;
 387
 388         u8      OutEpQueueSel;
 389         u8      OutEpNumber;
 390
 391         /*  Add for USB aggreation mode dynamic shceme. */
 392         bool            UsbRxHighSpeedMode;
 393
 394         /*  2010/11/22 MH Add for slim combo debug mode selective. */
 395         /*  This is used for fix the drawback of CU TSMC-A/UMC-A cut.
 396          * HW auto suspend ability. Close BT clock. */
 397         bool            SlimComboDbg;
 398
 399         u16     EfuseUsedBytes;
 400
 401 #ifdef CONFIG_88EU_P2P
 402         struct P2P_PS_Offload_t p2p_ps_offload;
 403 #endif
 404
 405         /*  Auto FSM to Turn On, include clock, isolation, power control
 406          *  for MAC only */
 407         u8      bMacPwrCtrlOn;
 408
 409         u32     UsbBulkOutSize;
 410
 411         /*  Interrupt relatd register information. */
 412         u32     IntArray[3];/* HISR0,HISR1,HSISR */
 413         u32     IntrMask[3];
 414         u8      C2hArray[16];
 415         u8      UsbTxAggMode;
 416         u8      UsbTxAggDescNum;
 417         u16     HwRxPageSize;           /*  Hardware setting */
 418         u32     MaxUsbRxAggBlock;
 419
 420         enum usb_rx_agg_mode UsbRxAggMode;
 421         u8      UsbRxAggBlockCount;     /*  USB Block count. Block size is
 422                                          * 512-byte in high speed and 64-byte
 423                                          * in full speed */
 424         u8      UsbRxAggBlockTimeout;
 425         u8      UsbRxAggPageCount;      /*  8192C DMA page count */
 426         u8      UsbRxAggPageTimeout;
 427 };
 428
 429 #define GET_HAL_DATA(__pAdapter)                                \
 430         ((struct hal_data_8188e *)((__pAdapter)->HalData))
 431 #define GET_RF_TYPE(priv)               (GET_HAL_DATA(priv)->rf_type)
 432
 433 #define INCLUDE_MULTI_FUNC_BT(_Adapter)                         \
 434         (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT)
 435 #define INCLUDE_MULTI_FUNC_GPS(_Adapter)                        \
 436         (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS)
 437
 438 /*  rtl8188e_hal_init.c */
 439 s32 rtl8188e_FirmwareDownload(struct adapter *padapter);
 440 void _8051Reset88E(struct adapter *padapter);
 441 void rtl8188e_InitializeFirmwareVars(struct adapter *padapter);
 442
 443
 444 s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy);
 445
 446 /*  EFuse */
 447 u8 GetEEPROMSize8188E(struct adapter *padapter);
 448 void Hal_InitPGData88E(struct adapter *padapter);
 449 void Hal_EfuseParseIDCode88E(struct adapter *padapter, u8 *hwinfo);
 450 void Hal_ReadTxPowerInfo88E(struct adapter *padapter, u8 *hwinfo,
 451                             bool AutoLoadFail);
 452
 453 void Hal_EfuseParseEEPROMVer88E(struct adapter *padapter, u8 *hwinfo,
 454                                 bool AutoLoadFail);
 455 void rtl8188e_EfuseParseChnlPlan(struct adapter *padapter, u8 *hwinfo,
 456                                  bool AutoLoadFail);
 457 void Hal_EfuseParseCustomerID88E(struct adapter *padapter, u8 *hwinfo,
 458                                  bool AutoLoadFail);
 459 void Hal_ReadAntennaDiversity88E(struct adapter *pAdapter,u8 *PROMContent,
 460                                  bool AutoLoadFail);
 461 void Hal_ReadThermalMeter_88E(struct adapter *  dapter, u8 *PROMContent,
 462                               bool AutoloadFail);
 463 void Hal_EfuseParseXtal_8188E(struct adapter *pAdapter, u8 *hwinfo,
 464                               bool AutoLoadFail);
 465 void Hal_EfuseParseBoardType88E(struct adapter *pAdapter, u8 *hwinfo,
 466                                 bool AutoLoadFail);
 467 void Hal_ReadPowerSavingMode88E(struct adapter *pAdapter, u8 *hwinfo,
 468                                 bool AutoLoadFail);
 469
 470 bool HalDetectPwrDownMode88E(struct adapter *Adapter);
 471
 472 void Hal_InitChannelPlan(struct adapter *padapter);
 473 void rtl8188e_set_hal_ops(struct hal_ops *pHalFunc);
 474
 475 /*  register */
 476 void SetBcnCtrlReg(struct adapter *padapter, u8 SetBits, u8 ClearBits);
 477
 478 void rtl8188e_clone_haldata(struct adapter *dst, struct adapter *src);
 479 void rtl8188e_start_thread(struct adapter *padapter);
 480 void rtl8188e_stop_thread(struct adapter *padapter);
 481
 482 void rtw_IOL_cmd_tx_pkt_buf_dump(struct adapter  *Adapter, int len);
 483 s32 rtl8188e_iol_efuse_patch(struct adapter *padapter);
 484 void rtw_cancel_all_timer(struct adapter *padapter);
 485 void _ps_open_RF(struct adapter *adapt);
 486
 487 #endif /* __RTL8188E_HAL_H__ */