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staging: rtl8192ee: Pass large struct by const reference
[deliverable/linux.git] / drivers / staging / rtl8192ee / rtl8192ee / trx.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 #include "../wifi.h"
27 #include "../pci.h"
28 #include "../base.h"
29 #include "../stats.h"
30 #include "reg.h"
31 #include "def.h"
32 #include "phy.h"
33 #include "trx.h"
34 #include "led.h"
35 #include "dm.h"
36 #include "fw.h"
37
38 static u8 _rtl92ee_map_hwqueue_to_fwqueue(struct sk_buff *skb, u8 hw_queue)
39 {
40 __le16 fc = rtl_get_fc(skb);
41
42 if (unlikely(ieee80211_is_beacon(fc)))
43 return QSLT_BEACON;
44 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
45 return QSLT_MGNT;
46
47 return skb->priority;
48 }
49
50 /* mac80211's rate_idx is like this:
51 *
52 * 2.4G band:rx_status->band == IEEE80211_BAND_2GHZ
53 *
54 * B/G rate:
55 * (rx_status->flag & RX_FLAG_HT) = 0,
56 * DESC92C_RATE1M-->DESC92C_RATE54M ==> idx is 0-->11,
57 *
58 * N rate:
59 * (rx_status->flag & RX_FLAG_HT) = 1,
60 * DESC92C_RATEMCS0-->DESC92C_RATEMCS15 ==> idx is 0-->15
61 *
62 * 5G band:rx_status->band == IEEE80211_BAND_5GHZ
63 * A rate:
64 * (rx_status->flag & RX_FLAG_HT) = 0,
65 * DESC92C_RATE6M-->DESC92C_RATE54M ==> idx is 0-->7,
66 *
67 * N rate:
68 * (rx_status->flag & RX_FLAG_HT) = 1,
69 * DESC92C_RATEMCS0-->DESC92C_RATEMCS15 ==> idx is 0-->15
70 */
71 static int _rtl92ee_rate_mapping(struct ieee80211_hw *hw,
72 bool isht, u8 desc_rate)
73 {
74 int rate_idx;
75
76 if (!false) {
77 if (IEEE80211_BAND_2GHZ == hw->conf.chandef.chan->band) {
78 switch (desc_rate) {
79 case DESC92C_RATE1M:
80 rate_idx = 0;
81 break;
82 case DESC92C_RATE2M:
83 rate_idx = 1;
84 break;
85 case DESC92C_RATE5_5M:
86 rate_idx = 2;
87 break;
88 case DESC92C_RATE11M:
89 rate_idx = 3;
90 break;
91 case DESC92C_RATE6M:
92 rate_idx = 4;
93 break;
94 case DESC92C_RATE9M:
95 rate_idx = 5;
96 break;
97 case DESC92C_RATE12M:
98 rate_idx = 6;
99 break;
100 case DESC92C_RATE18M:
101 rate_idx = 7;
102 break;
103 case DESC92C_RATE24M:
104 rate_idx = 8;
105 break;
106 case DESC92C_RATE36M:
107 rate_idx = 9;
108 break;
109 case DESC92C_RATE48M:
110 rate_idx = 10;
111 break;
112 case DESC92C_RATE54M:
113 rate_idx = 11;
114 break;
115 default:
116 rate_idx = 0;
117 break;
118 }
119 } else {
120 switch (desc_rate) {
121 case DESC92C_RATE6M:
122 rate_idx = 0;
123 break;
124 case DESC92C_RATE9M:
125 rate_idx = 1;
126 break;
127 case DESC92C_RATE12M:
128 rate_idx = 2;
129 break;
130 case DESC92C_RATE18M:
131 rate_idx = 3;
132 break;
133 case DESC92C_RATE24M:
134 rate_idx = 4;
135 break;
136 case DESC92C_RATE36M:
137 rate_idx = 5;
138 break;
139 case DESC92C_RATE48M:
140 rate_idx = 6;
141 break;
142 case DESC92C_RATE54M:
143 rate_idx = 7;
144 break;
145 default:
146 rate_idx = 0;
147 break;
148 }
149 }
150 } else {
151 switch (desc_rate) {
152 case DESC92C_RATEMCS0:
153 rate_idx = 0;
154 break;
155 case DESC92C_RATEMCS1:
156 rate_idx = 1;
157 break;
158 case DESC92C_RATEMCS2:
159 rate_idx = 2;
160 break;
161 case DESC92C_RATEMCS3:
162 rate_idx = 3;
163 break;
164 case DESC92C_RATEMCS4:
165 rate_idx = 4;
166 break;
167 case DESC92C_RATEMCS5:
168 rate_idx = 5;
169 break;
170 case DESC92C_RATEMCS6:
171 rate_idx = 6;
172 break;
173 case DESC92C_RATEMCS7:
174 rate_idx = 7;
175 break;
176 case DESC92C_RATEMCS8:
177 rate_idx = 8;
178 break;
179 case DESC92C_RATEMCS9:
180 rate_idx = 9;
181 break;
182 case DESC92C_RATEMCS10:
183 rate_idx = 10;
184 break;
185 case DESC92C_RATEMCS11:
186 rate_idx = 11;
187 break;
188 case DESC92C_RATEMCS12:
189 rate_idx = 12;
190 break;
191 case DESC92C_RATEMCS13:
192 rate_idx = 13;
193 break;
194 case DESC92C_RATEMCS14:
195 rate_idx = 14;
196 break;
197 case DESC92C_RATEMCS15:
198 rate_idx = 15;
199 break;
200 default:
201 rate_idx = 0;
202 break;
203 }
204 }
205 return rate_idx;
206 }
207
208 static void _rtl92ee_query_rxphystatus(struct ieee80211_hw *hw,
209 struct rtl_stats *pstatus, u8 *pdesc,
210 struct rx_fwinfo *p_drvinfo,
211 bool bpacket_match_bssid,
212 bool bpacket_toself,
213 bool b_packet_beacon)
214 {
215 struct rtl_priv *rtlpriv = rtl_priv(hw);
216 struct phy_status_rpt *p_phystrpt = (struct phy_status_rpt *)p_drvinfo;
217 char rx_pwr_all = 0, rx_pwr[4];
218 u8 rf_rx_num = 0, evm, pwdb_all;
219 u8 i, max_spatial_stream;
220 u32 rssi, total_rssi = 0;
221 bool b_is_cck = pstatus->b_is_cck;
222 u8 lan_idx , vga_idx;
223
224 /* Record it for next packet processing */
225 pstatus->b_packet_matchbssid = bpacket_match_bssid;
226 pstatus->b_packet_toself = bpacket_toself;
227 pstatus->b_packet_beacon = b_packet_beacon;
228 pstatus->rx_mimo_signalquality[0] = -1;
229 pstatus->rx_mimo_signalquality[1] = -1;
230
231 if (b_is_cck) {
232 u8 cck_highpwr;
233 u8 cck_agc_rpt;
234 /* CCK Driver info Structure is not the same as OFDM packet. */
235 cck_agc_rpt = p_phystrpt->cck_agc_rpt_ofdm_cfosho_a;
236
237 /* (1)Hardware does not provide RSSI for CCK */
238 /* (2)PWDB, Average PWDB cacluated by
239 * hardware (for rate adaptive) */
240 cck_highpwr = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2,
241 BIT(9));
242
243 lan_idx = ((cck_agc_rpt & 0xE0) >> 5);
244 vga_idx = (cck_agc_rpt & 0x1f);
245 switch (lan_idx) {
246 case 7: /*VGA_idx = 27~2*/
247 if (vga_idx <= 27)
248 rx_pwr_all = -100 + 2 * (27 - vga_idx);
249 else
250 rx_pwr_all = -100;
251 break;
252 case 6: /*VGA_idx = 2~0*/
253 rx_pwr_all = -48 + 2 * (2 - vga_idx);
254 break;
255 case 5: /*VGA_idx = 7~5*/
256 rx_pwr_all = -42 + 2 * (7 - vga_idx);
257 break;
258 case 4: /*VGA_idx = 7~4*/
259 rx_pwr_all = -36 + 2 * (7 - vga_idx);
260 break;
261 case 3: /*VGA_idx = 7~0*/
262 rx_pwr_all = -24 + 2 * (7 - vga_idx);
263 break;
264 case 2: /*VGA_idx = 5~0*/
265 if (cck_highpwr)
266 rx_pwr_all = -12 + 2 * (5 - vga_idx);
267 else
268 rx_pwr_all = -6 + 2 * (5 - vga_idx);
269 break;
270 case 1:
271 rx_pwr_all = 8 - 2 * vga_idx;
272 break;
273 case 0:
274 rx_pwr_all = 14 - 2 * vga_idx;
275 break;
276 default:
277 break;
278 }
279 rx_pwr_all += 16;
280 pwdb_all = stg_rtl_query_rxpwrpercentage(rx_pwr_all);
281
282 if (!cck_highpwr) {
283 if (pwdb_all >= 80)
284 pwdb_all = ((pwdb_all - 80) << 1) +
285 ((pwdb_all - 80) >> 1) + 80;
286 else if ((pwdb_all <= 78) && (pwdb_all >= 20))
287 pwdb_all += 3;
288 if (pwdb_all > 100)
289 pwdb_all = 100;
290 }
291
292 pstatus->rx_pwdb_all = pwdb_all;
293 pstatus->bt_rx_rssi_percentage = pwdb_all;
294 pstatus->recvsignalpower = rx_pwr_all;
295
296 /* (3) Get Signal Quality (EVM) */
297 if (bpacket_match_bssid) {
298 u8 sq, sq_rpt;
299
300 if (pstatus->rx_pwdb_all > 40) {
301 sq = 100;
302 } else {
303 sq_rpt = p_phystrpt->cck_sig_qual_ofdm_pwdb_all;
304 if (sq_rpt > 64)
305 sq = 0;
306 else if (sq_rpt < 20)
307 sq = 100;
308 else
309 sq = ((64 - sq_rpt) * 100) / 44;
310 }
311
312 pstatus->signalquality = sq;
313 pstatus->rx_mimo_signalquality[0] = sq;
314 pstatus->rx_mimo_signalquality[1] = -1;
315 }
316 } else {
317 /* (1)Get RSSI for HT rate */
318 for (i = RF90_PATH_A; i < RF6052_MAX_PATH; i++) {
319 /* we will judge RF RX path now. */
320 if (rtlpriv->dm.brfpath_rxenable[i])
321 rf_rx_num++;
322
323 rx_pwr[i] = ((p_phystrpt->path_agc[i].gain & 0x3f) * 2)
324 - 110;
325
326 pstatus->rx_pwr[i] = rx_pwr[i];
327 /* Translate DBM to percentage. */
328 rssi = stg_rtl_query_rxpwrpercentage(rx_pwr[i]);
329 total_rssi += rssi;
330
331 pstatus->rx_mimo_signalstrength[i] = (u8)rssi;
332 }
333
334 /* (2)PWDB, Average PWDB cacluated by
335 * hardware (for rate adaptive) */
336 rx_pwr_all = ((p_phystrpt->cck_sig_qual_ofdm_pwdb_all >> 1)
337 & 0x7f) - 110;
338
339 pwdb_all = stg_rtl_query_rxpwrpercentage(rx_pwr_all);
340 pstatus->rx_pwdb_all = pwdb_all;
341 pstatus->bt_rx_rssi_percentage = pwdb_all;
342 pstatus->rxpower = rx_pwr_all;
343 pstatus->recvsignalpower = rx_pwr_all;
344
345 /* (3)EVM of HT rate */
346 if (pstatus->rate >= DESC92C_RATEMCS8 &&
347 pstatus->rate <= DESC92C_RATEMCS15)
348 max_spatial_stream = 2;
349 else
350 max_spatial_stream = 1;
351
352 for (i = 0; i < max_spatial_stream; i++) {
353 evm = stg_rtl_evm_db_to_percentage(
354 p_phystrpt->stream_rxevm[i]);
355
356 if (bpacket_match_bssid) {
357 /* Fill value in RFD, Get the first
358 * spatial stream only */
359 if (i == 0)
360 pstatus->signalquality = (u8)(evm &
361 0xff);
362 pstatus->rx_mimo_signalquality[i] = (u8)(evm &
363 0xff);
364 }
365 }
366
367 if (bpacket_match_bssid) {
368 for (i = RF90_PATH_A; i <= RF90_PATH_B; i++)
369 rtl_priv(hw)->dm.cfo_tail[i] =
370 (int)p_phystrpt->path_cfotail[i];
371
372 if (rtl_priv(hw)->dm.packet_count == 0xffffffff)
373 rtl_priv(hw)->dm.packet_count = 0;
374 else
375 rtl_priv(hw)->dm.packet_count++;
376 }
377 }
378
379 /* UI BSS List signal strength(in percentage),
380 * make it good looking, from 0~100. */
381 if (b_is_cck)
382 pstatus->signalstrength = (u8)(stg_rtl_signal_scale_mapping(hw,
383 pwdb_all));
384 else if (rf_rx_num != 0)
385 pstatus->signalstrength = (u8)(stg_rtl_signal_scale_mapping(hw,
386 total_rssi /= rf_rx_num));
387 }
388
389 static void _rtl92ee_translate_rx_signal_stuff(struct ieee80211_hw *hw,
390 struct sk_buff *skb,
391 struct rtl_stats *pstatus,
392 u8 *pdesc,
393 struct rx_fwinfo *p_drvinfo)
394 {
395 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
396 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
397 struct ieee80211_hdr *hdr;
398 u8 *tmp_buf;
399 u8 *praddr;
400 u8 *psaddr;
401 __le16 fc;
402 u16 cpu_fc, type;
403 bool b_packet_matchbssid, b_packet_toself, b_packet_beacon;
404
405 tmp_buf = skb->data + pstatus->rx_drvinfo_size +
406 pstatus->rx_bufshift + 24;
407
408 hdr = (struct ieee80211_hdr *)tmp_buf;
409 fc = hdr->frame_control;
410 cpu_fc = le16_to_cpu(fc);
411 type = WLAN_FC_GET_TYPE(fc);
412 praddr = hdr->addr1;
413 psaddr = ieee80211_get_SA(hdr);
414 ether_addr_copy(pstatus->psaddr, psaddr);
415
416 b_packet_matchbssid = ((IEEE80211_FTYPE_CTL != type) &&
417 (ether_addr_equal(mac->bssid,
418 (cpu_fc & IEEE80211_FCTL_TODS) ?
419 hdr->addr1 :
420 (cpu_fc & IEEE80211_FCTL_FROMDS) ?
421 hdr->addr2 : hdr->addr3)) &&
422 (!pstatus->b_hwerror) && (!pstatus->b_crc) &&
423 (!pstatus->b_icv));
424
425 b_packet_toself = b_packet_matchbssid &&
426 (ether_addr_equal(praddr, rtlefuse->dev_addr));
427
428 if (ieee80211_is_beacon(fc))
429 b_packet_beacon = true;
430 else
431 b_packet_beacon = false;
432
433 if (b_packet_beacon && b_packet_matchbssid)
434 rtl_priv(hw)->dm.dbginfo.num_qry_beacon_pkt++;
435
436 if (b_packet_matchbssid && ieee80211_is_data_qos(fc) &&
437 !is_multicast_ether_addr(ieee80211_get_DA(hdr))) {
438 struct ieee80211_qos_hdr *hdr_qos =
439 (struct ieee80211_qos_hdr *)tmp_buf;
440 u16 tid = le16_to_cpu(hdr_qos->qos_ctrl) & 0xf;
441 if (tid != 0 && tid != 3)
442 rtl_priv(hw)->dm.dbginfo.num_non_be_pkt++;
443 }
444 _rtl92ee_query_rxphystatus(hw, pstatus, pdesc, p_drvinfo,
445 b_packet_matchbssid, b_packet_toself,
446 b_packet_beacon);
447 stg_rtl_process_phyinfo(hw, tmp_buf, pstatus);
448 }
449
450 static void _rtl92ee_insert_emcontent(struct rtl_tcb_desc *ptcb_desc,
451 u8 *virtualaddress)
452 {
453 u32 dwtmp = 0;
454 memset(virtualaddress, 0, 8);
455
456 SET_EARLYMODE_PKTNUM(virtualaddress, ptcb_desc->empkt_num);
457 if (ptcb_desc->empkt_num == 1) {
458 dwtmp = ptcb_desc->empkt_len[0];
459 } else {
460 dwtmp = ptcb_desc->empkt_len[0];
461 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
462 dwtmp += ptcb_desc->empkt_len[1];
463 }
464 SET_EARLYMODE_LEN0(virtualaddress, dwtmp);
465
466 if (ptcb_desc->empkt_num <= 3) {
467 dwtmp = ptcb_desc->empkt_len[2];
468 } else {
469 dwtmp = ptcb_desc->empkt_len[2];
470 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
471 dwtmp += ptcb_desc->empkt_len[3];
472 }
473 SET_EARLYMODE_LEN1(virtualaddress, dwtmp);
474 if (ptcb_desc->empkt_num <= 5) {
475 dwtmp = ptcb_desc->empkt_len[4];
476 } else {
477 dwtmp = ptcb_desc->empkt_len[4];
478 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
479 dwtmp += ptcb_desc->empkt_len[5];
480 }
481 SET_EARLYMODE_LEN2_1(virtualaddress, dwtmp & 0xF);
482 SET_EARLYMODE_LEN2_2(virtualaddress, dwtmp >> 4);
483 if (ptcb_desc->empkt_num <= 7) {
484 dwtmp = ptcb_desc->empkt_len[6];
485 } else {
486 dwtmp = ptcb_desc->empkt_len[6];
487 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
488 dwtmp += ptcb_desc->empkt_len[7];
489 }
490 SET_EARLYMODE_LEN3(virtualaddress, dwtmp);
491 if (ptcb_desc->empkt_num <= 9) {
492 dwtmp = ptcb_desc->empkt_len[8];
493 } else {
494 dwtmp = ptcb_desc->empkt_len[8];
495 dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
496 dwtmp += ptcb_desc->empkt_len[9];
497 }
498 SET_EARLYMODE_LEN4(virtualaddress, dwtmp);
499 }
500
501 bool rtl92ee_rx_query_desc(struct ieee80211_hw *hw,
502 struct rtl_stats *status,
503 struct ieee80211_rx_status *rx_status,
504 u8 *pdesc, struct sk_buff *skb)
505 {
506 struct rtl_priv *rtlpriv = rtl_priv(hw);
507 struct rx_fwinfo *p_drvinfo;
508 struct ieee80211_hdr *hdr;
509
510 u32 phystatus = GET_RX_DESC_PHYST(pdesc);
511 status->length = (u16) GET_RX_DESC_PKT_LEN(pdesc);
512 status->rx_drvinfo_size = (u8) GET_RX_DESC_DRV_INFO_SIZE(pdesc) *
513 RX_DRV_INFO_SIZE_UNIT;
514 status->rx_bufshift = (u8)(GET_RX_DESC_SHIFT(pdesc) & 0x03);
515 status->b_icv = (u16) GET_RX_DESC_ICV(pdesc);
516 status->b_crc = (u16) GET_RX_DESC_CRC32(pdesc);
517 status->b_hwerror = (status->b_crc | status->b_icv);
518 status->decrypted = !GET_RX_DESC_SWDEC(pdesc);
519 status->rate = (u8) GET_RX_DESC_RXMCS(pdesc);
520 status->b_isampdu = (bool)(GET_RX_DESC_PAGGR(pdesc) == 1);
521 status->timestamp_low = GET_RX_DESC_TSFL(pdesc);
522 status->b_is_cck = RX_HAL_IS_CCK_RATE(status->rate);
523
524 status->macid = GET_RX_DESC_MACID(pdesc);
525 if (GET_RX_STATUS_DESC_MAGIC_MATCH(pdesc))
526 status->wake_match = BIT(2);
527 else if (GET_RX_STATUS_DESC_MAGIC_MATCH(pdesc))
528 status->wake_match = BIT(1);
529 else if (GET_RX_STATUS_DESC_UNICAST_MATCH(pdesc))
530 status->wake_match = BIT(0);
531 else
532 status->wake_match = 0;
533 if (status->wake_match)
534 RT_TRACE(COMP_RXDESC , DBG_LOUD,
535 ("GGGGGGGGGGGGGet Wakeup Packet!! WakeMatch =%d\n",
536 status->wake_match));
537 rx_status->freq = hw->conf.chandef.chan->center_freq;
538 rx_status->band = hw->conf.chandef.chan->band;
539
540 hdr = (struct ieee80211_hdr *)(skb->data + status->rx_drvinfo_size +
541 status->rx_bufshift + 24);
542
543 if (status->b_crc)
544 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
545
546 if (status->rx_is40Mhzpacket)
547 rx_status->flag |= RX_FLAG_40MHZ;
548
549 if (status->b_is_ht)
550 rx_status->flag |= RX_FLAG_HT;
551
552 rx_status->flag |= RX_FLAG_MACTIME_MPDU;
553
554 /* hw will set status->decrypted true, if it finds the
555 * frame is open data frame or mgmt frame. */
556 /* So hw will not decryption robust managment frame
557 * for IEEE80211w but still set status->decrypted
558 * true, so here we should set it back to undecrypted
559 * for IEEE80211w frame, and mac80211 sw will help
560 * to decrypt it */
561 if (status->decrypted) {
562 if (!hdr) {
563 WARN_ON_ONCE(true);
564 pr_err("decrypted is true but hdr NULL, from skb %p\n",
565 rtl_get_hdr(skb));
566 return false;
567 }
568
569 if ((!_ieee80211_is_robust_mgmt_frame(hdr)) &&
570 (ieee80211_has_protected(hdr->frame_control)))
571 rx_status->flag |= RX_FLAG_DECRYPTED;
572 else
573 rx_status->flag &= ~RX_FLAG_DECRYPTED;
574 }
575
576 /* rate_idx: index of data rate into band's
577 * supported rates or MCS index if HT rates
578 * are use (RX_FLAG_HT)*/
579 /* Notice: this is diff with windows define */
580 rx_status->rate_idx = _rtl92ee_rate_mapping(hw,
581 status->b_is_ht,
582 status->rate);
583
584 rx_status->mactime = status->timestamp_low;
585 if (phystatus) {
586 p_drvinfo = (struct rx_fwinfo *)(skb->data +
587 status->rx_bufshift + 24);
588
589 _rtl92ee_translate_rx_signal_stuff(hw, skb, status, pdesc,
590 p_drvinfo);
591 }
592
593 /*rx_status->qual = status->signal; */
594 rx_status->signal = status->recvsignalpower + 10;
595 /*rx_status->noise = -status->noise; */
596 if (status->packet_report_type == TX_REPORT2) {
597 status->macid_valid_entry[0] =
598 GET_RX_RPT2_DESC_MACID_VALID_1(pdesc);
599 status->macid_valid_entry[1] =
600 GET_RX_RPT2_DESC_MACID_VALID_2(pdesc);
601 }
602 return true;
603 }
604
605 /*in Windows, this == Rx_92EE_Interrupt*/
606 void rtl92ee_rx_check_dma_ok(struct ieee80211_hw *hw, u8 *header_desc,
607 u8 queue_index)
608 {
609 u8 first_seg;
610 u8 last_seg;
611 u16 total_len;
612 u16 read_cnt = 0;
613 if (header_desc == NULL)
614 return;
615
616 total_len = (u16)GET_RX_BUFFER_DESC_TOTAL_LENGTH(header_desc);
617
618 first_seg = (u8)GET_RX_BUFFER_DESC_FS(header_desc);
619
620 last_seg = (u8)GET_RX_BUFFER_DESC_LS(header_desc);
621
622 while (total_len == 0 && first_seg == 0 && last_seg == 0) {
623 read_cnt++;
624 total_len = (u16)GET_RX_BUFFER_DESC_TOTAL_LENGTH(header_desc);
625 first_seg = (u8)GET_RX_BUFFER_DESC_FS(header_desc);
626 last_seg = (u8)GET_RX_BUFFER_DESC_LS(header_desc);
627
628 if (read_cnt > 20)
629 break;
630 }
631 }
632
633 u16 rtl92ee_rx_desc_buff_remained_cnt(struct ieee80211_hw *hw , u8 queue_index)
634 {
635 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
636 struct rtl_priv *rtlpriv = rtl_priv(hw);
637 u16 read_point = 0 , write_point = 0 , remind_cnt = 0;
638 u32 tmp_4byte = 0;
639 static u16 last_read_point;
640 static bool start_rx;
641
642 tmp_4byte = rtl_read_dword(rtlpriv, REG_RXQ_TXBD_IDX);
643 read_point = (u16)((tmp_4byte>>16) & 0x7ff);
644 write_point = (u16)(tmp_4byte & 0x7ff);
645
646 if (write_point != rtlpci->rx_ring[queue_index].next_rx_rp) {
647 RT_TRACE(COMP_RXDESC, DBG_DMESG,
648 ("!!!write point is 0x%x, reg 0x3B4 value is 0x%x\n",
649 write_point, tmp_4byte));
650 tmp_4byte = rtl_read_dword(rtlpriv, REG_RXQ_TXBD_IDX);
651 read_point = (u16)((tmp_4byte>>16) & 0x7ff);
652 write_point = (u16)(tmp_4byte & 0x7ff);
653 }
654
655 if (read_point > 0)
656 start_rx = true;
657 if (!start_rx)
658 return 0;
659
660 if ((last_read_point > (RX_DESC_NUM_92E / 2)) &&
661 (read_point <= (RX_DESC_NUM_92E / 2))) {
662 remind_cnt = RX_DESC_NUM_92E - write_point;
663 } else {
664 remind_cnt = (read_point >= write_point) ?
665 (read_point - write_point) :
666 (RX_DESC_NUM_92E - write_point + read_point);
667 }
668
669 if (remind_cnt == 0)
670 return 0;
671
672 rtlpci->rx_ring[queue_index].next_rx_rp = write_point;
673
674 last_read_point = read_point;
675 return remind_cnt;
676 }
677
678 static u16 get_desc_addr_fr_q(u16 queue_index)
679 {
680 u16 desc_address = REG_BEQ_TXBD_IDX;
681
682 switch (queue_index) {
683 case BK_QUEUE:
684 desc_address = REG_BKQ_TXBD_IDX;
685 break;
686 case BE_QUEUE:
687 desc_address = REG_BEQ_TXBD_IDX;
688 break;
689 case VI_QUEUE:
690 desc_address = REG_VIQ_TXBD_IDX;
691 break;
692 case VO_QUEUE:
693 desc_address = REG_VOQ_TXBD_IDX;
694 break;
695 case BEACON_QUEUE:
696 desc_address = REG_BEQ_TXBD_IDX;
697 break;
698 case TXCMD_QUEUE:
699 desc_address = REG_BEQ_TXBD_IDX;
700 break;
701 case MGNT_QUEUE:
702 desc_address = REG_MGQ_TXBD_IDX;
703 break;
704 case HIGH_QUEUE:
705 desc_address = REG_HI0Q_TXBD_IDX;
706 break;
707 case HCCA_QUEUE:
708 desc_address = REG_BEQ_TXBD_IDX;
709 break;
710 default:
711 break;
712 }
713 return desc_address;
714 }
715
716 void rtl92ee_get_available_desc(struct ieee80211_hw *hw , u8 q_idx)
717 {
718 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
719 struct rtl_priv *rtlpriv = rtl_priv(hw);
720 u16 point_diff = 0;
721 u16 current_tx_read_point = 0, current_tx_write_point = 0;
722 u32 tmp_4byte;
723 tmp_4byte = rtl_read_dword(rtlpriv,
724 get_desc_addr_fr_q(q_idx));
725 current_tx_read_point = (u16)((tmp_4byte >> 16) & 0x0fff);
726 current_tx_write_point = (u16)((tmp_4byte) & 0x0fff);
727
728 point_diff = ((current_tx_read_point > current_tx_write_point) ?
729 (current_tx_read_point - current_tx_write_point) :
730 (TX_DESC_NUM_92E - current_tx_write_point +
731 current_tx_read_point));
732
733 rtlpci->tx_ring[q_idx].avl_desc = point_diff;
734 }
735
736 void rtl92ee_pre_fill_tx_bd_desc(struct ieee80211_hw *hw,
737 u8 *tx_bd_desc, u8 *desc, u8 queue_index,
738 struct sk_buff *skb, dma_addr_t addr)
739 {
740 struct rtl_priv *rtlpriv = rtl_priv(hw);
741 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
742 u32 pkt_len = skb->len;
743 u16 desc_size = 40; /*tx desc size*/
744 u32 psblen = 0;
745 u16 tx_page_size = 0;
746 u32 total_packet_size = 0;
747 u16 current_bd_desc;
748 u8 i = 0;
749 u16 real_desc_size = 0x28;
750 u16 append_early_mode_size = 0;
751 #if (RTL8192EE_SEG_NUM == 0)
752 u8 segmentnum = 2;
753 #elif (RTL8192EE_SEG_NUM == 1)
754 u8 segmentnum = 4;
755 #elif (RTL8192EE_SEG_NUM == 2)
756 u8 segmentnum = 8;
757 #endif
758
759 tx_page_size = 2;
760 current_bd_desc = rtlpci->tx_ring[queue_index].cur_tx_wp;
761
762
763 total_packet_size = desc_size+pkt_len;
764
765 if (rtlpriv->rtlhal.b_earlymode_enable) {
766 if (queue_index < BEACON_QUEUE) {
767 append_early_mode_size = 8;
768 total_packet_size += append_early_mode_size;
769 }
770 }
771
772 if (tx_page_size > 0) {
773 psblen = (pkt_len + real_desc_size + append_early_mode_size) /
774 (tx_page_size * 128);
775
776 if (psblen * (tx_page_size * 128) < total_packet_size)
777 psblen += 1;
778 }
779
780 /* Reset */
781 SET_TX_BUFF_DESC_LEN_0(tx_bd_desc , 0);
782 SET_TX_BUFF_DESC_PSB(tx_bd_desc , 0);
783 SET_TX_BUFF_DESC_OWN(tx_bd_desc , 0);
784
785 for (i = 1; i < segmentnum; i++) {
786 SET_TXBUFFER_DESC_LEN_WITH_OFFSET(tx_bd_desc, i, 0);
787 SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(tx_bd_desc, i, 0);
788 SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(tx_bd_desc, i, 0);
789 #if (DMA_IS_64BIT == 1)
790 SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(tx_bd_desc, i, 0);
791 #endif
792 }
793 SET_TX_BUFF_DESC_LEN_1(tx_bd_desc, 0);
794 SET_TX_BUFF_DESC_AMSDU_1(tx_bd_desc, 0);
795
796 SET_TX_BUFF_DESC_LEN_2(tx_bd_desc, 0);
797 SET_TX_BUFF_DESC_AMSDU_2(tx_bd_desc, 0);
798 SET_TX_BUFF_DESC_LEN_3(tx_bd_desc, 0);
799 SET_TX_BUFF_DESC_AMSDU_3(tx_bd_desc, 0);
800 /* Clear all status */
801 CLEAR_PCI_TX_DESC_CONTENT(desc, TX_DESC_SIZE);
802
803 if (rtlpriv->rtlhal.b_earlymode_enable) {
804 if (queue_index < BEACON_QUEUE) {
805 /* These macros need braces */
806 SET_TX_BUFF_DESC_LEN_0(tx_bd_desc , desc_size + 8);
807 } else {
808 SET_TX_BUFF_DESC_LEN_0(tx_bd_desc , desc_size);
809 }
810 } else {
811 SET_TX_BUFF_DESC_LEN_0(tx_bd_desc , desc_size);
812 }
813 SET_TX_BUFF_DESC_PSB(tx_bd_desc , psblen);
814 SET_TX_BUFF_DESC_ADDR_LOW_0(tx_bd_desc,
815 rtlpci->tx_ring[queue_index].dma +
816 (current_bd_desc * TX_DESC_SIZE));
817
818 SET_TXBUFFER_DESC_LEN_WITH_OFFSET(tx_bd_desc, 1, pkt_len);
819 /* don't using extendsion mode. */
820 SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(tx_bd_desc, 1, 0);
821 SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(tx_bd_desc, 1, addr);
822
823 SET_TX_DESC_PKT_SIZE(desc, (u16)(pkt_len));
824 SET_TX_DESC_TX_BUFFER_SIZE(desc, (u16)(pkt_len));
825 }
826
827 void rtl92ee_tx_fill_desc(struct ieee80211_hw *hw,
828 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
829 u8 *pbd_desc_tx,
830 struct ieee80211_tx_info *info,
831 struct ieee80211_sta *sta,
832 struct sk_buff *skb,
833 u8 hw_queue, struct rtl_tcb_desc *ptcb_desc)
834 {
835 struct rtl_priv *rtlpriv = rtl_priv(hw);
836 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
837 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
838 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
839 u8 *pdesc = (u8 *)pdesc_tx;
840 u16 seq_number;
841 __le16 fc = hdr->frame_control;
842 unsigned int buf_len = 0;
843 u8 fw_qsel = _rtl92ee_map_hwqueue_to_fwqueue(skb, hw_queue);
844 bool b_firstseg = ((hdr->seq_ctrl &
845 cpu_to_le16(IEEE80211_SCTL_FRAG)) == 0);
846 bool b_lastseg = ((hdr->frame_control &
847 cpu_to_le16(IEEE80211_FCTL_MOREFRAGS)) == 0);
848 dma_addr_t mapping;
849 u8 bw_40 = 0;
850 u8 short_gi = 0;
851
852 if (mac->opmode == NL80211_IFTYPE_STATION) {
853 bw_40 = mac->bw_40;
854 } else if (mac->opmode == NL80211_IFTYPE_AP ||
855 mac->opmode == NL80211_IFTYPE_ADHOC) {
856 if (sta)
857 bw_40 = sta->ht_cap.cap &
858 IEEE80211_HT_CAP_SUP_WIDTH_20_40;
859 }
860 seq_number = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
861 stg_rtl_get_tcb_desc(hw, info, sta, skb, ptcb_desc);
862 /* reserve 8 byte for AMPDU early mode */
863 if (rtlhal->b_earlymode_enable) {
864 skb_push(skb, EM_HDR_LEN);
865 memset(skb->data, 0, EM_HDR_LEN);
866 }
867 buf_len = skb->len;
868 mapping = pci_map_single(rtlpci->pdev, skb->data, skb->len,
869 PCI_DMA_TODEVICE);
870 if (pci_dma_mapping_error(rtlpci->pdev, mapping)) {
871 RT_TRACE(COMP_SEND, DBG_TRACE,
872 ("DMA mapping error"));
873 return;
874 }
875 if (pbd_desc_tx != NULL)
876 rtl92ee_pre_fill_tx_bd_desc(hw, pbd_desc_tx, pdesc, hw_queue,
877 skb, mapping);
878
879 if (ieee80211_is_nullfunc(fc) || ieee80211_is_ctl(fc)) {
880 b_firstseg = true;
881 b_lastseg = true;
882 }
883 if (b_firstseg) {
884 if (rtlhal->b_earlymode_enable) {
885 SET_TX_DESC_PKT_OFFSET(pdesc, 1);
886 SET_TX_DESC_OFFSET(pdesc,
887 USB_HWDESC_HEADER_LEN + EM_HDR_LEN);
888 if (ptcb_desc->empkt_num) {
889 RT_TRACE(COMP_SEND, DBG_TRACE,
890 ("Insert 8 byte.pTcb->EMPktNum:%d\n",
891 ptcb_desc->empkt_num));
892 _rtl92ee_insert_emcontent(ptcb_desc,
893 (u8 *)(skb->data));
894 }
895 } else {
896 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
897 }
898
899 SET_TX_DESC_TX_RATE(pdesc, ptcb_desc->hw_rate);
900
901 if (ieee80211_is_mgmt(fc)) {
902 ptcb_desc->use_driver_rate = true;
903 } else {
904 if (rtlpriv->ra.is_special_data) {
905 ptcb_desc->use_driver_rate = true;
906 SET_TX_DESC_TX_RATE(pdesc, DESC92C_RATE11M);
907 } else {
908 ptcb_desc->use_driver_rate = false;
909 }
910 }
911
912 if (ptcb_desc->hw_rate > DESC92C_RATEMCS0)
913 short_gi = (ptcb_desc->use_shortgi) ? 1 : 0;
914 else
915 short_gi = (ptcb_desc->use_shortpreamble) ? 1 : 0;
916
917 if (info->flags & IEEE80211_TX_CTL_AMPDU) {
918 SET_TX_DESC_AGG_ENABLE(pdesc, 1);
919 SET_TX_DESC_MAX_AGG_NUM(pdesc, 0x14);
920 }
921 SET_TX_DESC_SEQ(pdesc, seq_number);
922 SET_TX_DESC_RTS_ENABLE(pdesc,
923 ((ptcb_desc->b_rts_enable &&
924 !ptcb_desc->b_cts_enable) ? 1 : 0));
925 SET_TX_DESC_HW_RTS_ENABLE(pdesc , 0);
926 SET_TX_DESC_CTS2SELF(pdesc,
927 ((ptcb_desc->b_cts_enable) ? 1 : 0));
928
929 SET_TX_DESC_RTS_RATE(pdesc, ptcb_desc->rts_rate);
930 SET_TX_DESC_RTS_SC(pdesc, ptcb_desc->rts_sc);
931 SET_TX_DESC_RTS_SHORT(pdesc,
932 ((ptcb_desc->rts_rate <= DESC92C_RATE54M) ?
933 (ptcb_desc->b_rts_use_shortpreamble ? 1 : 0) :
934 (ptcb_desc->b_rts_use_shortgi ? 1 : 0)));
935
936 if (ptcb_desc->btx_enable_sw_calc_duration)
937 SET_TX_DESC_NAV_USE_HDR(pdesc, 1);
938
939 if (bw_40) {
940 if (ptcb_desc->packet_bw == HT_CHANNEL_WIDTH_20_40) {
941 SET_TX_DESC_DATA_BW(pdesc, 1);
942 SET_TX_DESC_TX_SUB_CARRIER(pdesc, 3);
943 } else {
944 SET_TX_DESC_DATA_BW(pdesc, 0);
945 SET_TX_DESC_TX_SUB_CARRIER(pdesc,
946 mac->cur_40_prime_sc);
947 }
948 } else {
949 SET_TX_DESC_DATA_BW(pdesc, 0);
950 SET_TX_DESC_TX_SUB_CARRIER(pdesc, 0);
951 }
952
953 SET_TX_DESC_LINIP(pdesc, 0);
954 if (sta) {
955 u8 ampdu_density = sta->ht_cap.ampdu_density;
956 SET_TX_DESC_AMPDU_DENSITY(pdesc, ampdu_density);
957 }
958 if (info->control.hw_key) {
959 struct ieee80211_key_conf *key = info->control.hw_key;
960 switch (key->cipher) {
961 case WLAN_CIPHER_SUITE_WEP40:
962 case WLAN_CIPHER_SUITE_WEP104:
963 case WLAN_CIPHER_SUITE_TKIP:
964 SET_TX_DESC_SEC_TYPE(pdesc, 0x1);
965 break;
966 case WLAN_CIPHER_SUITE_CCMP:
967 SET_TX_DESC_SEC_TYPE(pdesc, 0x3);
968 break;
969 default:
970 SET_TX_DESC_SEC_TYPE(pdesc, 0x0);
971 break;
972 }
973 }
974
975 SET_TX_DESC_QUEUE_SEL(pdesc, fw_qsel);
976 SET_TX_DESC_DATA_RATE_FB_LIMIT(pdesc, 0x1F);
977 SET_TX_DESC_RTS_RATE_FB_LIMIT(pdesc, 0xF);
978 SET_TX_DESC_DISABLE_FB(pdesc,
979 ptcb_desc->disable_ratefallback ? 1 : 0);
980 SET_TX_DESC_USE_RATE(pdesc, ptcb_desc->use_driver_rate ? 1 : 0);
981
982 /*SET_TX_DESC_PWR_STATUS(pdesc, pwr_status);*/
983 /* Set TxRate and RTSRate in TxDesc */
984 /* This prevent Tx initial rate of new-coming packets */
985 /* from being overwritten by retried packet rate.*/
986 if (!ptcb_desc->use_driver_rate) {
987 /*SET_TX_DESC_RTS_RATE(pdesc, 0x08); */
988 /* SET_TX_DESC_TX_RATE(pdesc, 0x0b); */
989 }
990 if (ieee80211_is_data_qos(fc)) {
991 if (mac->rdg_en) {
992 RT_TRACE(COMP_SEND, DBG_TRACE,
993 ("Enable RDG function.\n"));
994 SET_TX_DESC_RDG_ENABLE(pdesc, 1);
995 SET_TX_DESC_HTC(pdesc, 1);
996 }
997 }
998 }
999
1000 SET_TX_DESC_FIRST_SEG(pdesc, (b_firstseg ? 1 : 0));
1001 SET_TX_DESC_LAST_SEG(pdesc, (b_lastseg ? 1 : 0));
1002 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
1003 if (rtlpriv->dm.b_useramask) {
1004 SET_TX_DESC_RATE_ID(pdesc, ptcb_desc->ratr_index);
1005 SET_TX_DESC_MACID(pdesc, ptcb_desc->mac_id);
1006 } else {
1007 SET_TX_DESC_RATE_ID(pdesc, 0xC + ptcb_desc->ratr_index);
1008 SET_TX_DESC_MACID(pdesc, ptcb_desc->ratr_index);
1009 }
1010
1011 SET_TX_DESC_MORE_FRAG(pdesc, (b_lastseg ? 0 : 1));
1012 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
1013 is_broadcast_ether_addr(ieee80211_get_DA(hdr))) {
1014 SET_TX_DESC_BMC(pdesc, 1);
1015 }
1016 RT_TRACE(COMP_SEND, DBG_TRACE, ("\n"));
1017 }
1018
1019 void rtl92ee_tx_fill_cmddesc(struct ieee80211_hw *hw,
1020 u8 *pdesc, bool b_firstseg,
1021 bool b_lastseg, struct sk_buff *skb)
1022 {
1023 struct rtl_priv *rtlpriv = rtl_priv(hw);
1024 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1025 u8 fw_queue = QSLT_BEACON;
1026
1027 dma_addr_t mapping = pci_map_single(rtlpci->pdev,
1028 skb->data, skb->len,
1029 PCI_DMA_TODEVICE);
1030
1031
1032 u8 txdesc_len = 40;
1033
1034 if (pci_dma_mapping_error(rtlpci->pdev, mapping)) {
1035 RT_TRACE(COMP_SEND, DBG_TRACE,
1036 ("DMA mapping error"));
1037 return;
1038 }
1039 CLEAR_PCI_TX_DESC_CONTENT(pdesc, txdesc_len);
1040
1041 if (b_firstseg)
1042 SET_TX_DESC_OFFSET(pdesc, txdesc_len);
1043
1044 SET_TX_DESC_TX_RATE(pdesc, DESC92C_RATE1M);
1045
1046 SET_TX_DESC_SEQ(pdesc, 0);
1047
1048 SET_TX_DESC_LINIP(pdesc, 0);
1049
1050 SET_TX_DESC_QUEUE_SEL(pdesc, fw_queue);
1051
1052 SET_TX_DESC_FIRST_SEG(pdesc, 1);
1053 SET_TX_DESC_LAST_SEG(pdesc, 1);
1054
1055 SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16)(skb->len));
1056
1057 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
1058
1059 SET_TX_DESC_RATE_ID(pdesc, 7);
1060 SET_TX_DESC_MACID(pdesc, 0);
1061
1062 SET_TX_DESC_OWN(pdesc, 1);
1063
1064 SET_TX_DESC_PKT_SIZE((u8 *)pdesc, (u16)(skb->len));
1065
1066 SET_TX_DESC_FIRST_SEG(pdesc, 1);
1067 SET_TX_DESC_LAST_SEG(pdesc, 1);
1068
1069 SET_TX_DESC_OFFSET(pdesc, 40);
1070
1071 SET_TX_DESC_USE_RATE(pdesc, 1);
1072
1073 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
1074 "H2C Tx Cmd Content\n", pdesc, txdesc_len);
1075 }
1076
1077
1078 void rtl92ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
1079 u8 desc_name, u8 *val)
1080 {
1081 struct rtl_priv *rtlpriv = rtl_priv(hw);
1082 u16 cur_tx_rp = 0;
1083 u16 cur_tx_wp = 0;
1084 static u16 last_txw_point;
1085 static bool over_run;
1086 u32 tmp = 0;
1087 u8 q_idx = *val;
1088
1089 if (istx) {
1090 switch (desc_name) {
1091 case HW_DESC_TX_NEXTDESC_ADDR:
1092 SET_TX_DESC_NEXT_DESC_ADDRESS(pdesc, *(u32 *)val);
1093 break;
1094 case HW_DESC_OWN:{
1095 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1096 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[q_idx];
1097 u16 max_tx_desc = ring->entries;
1098 if (q_idx == BEACON_QUEUE) {
1099 ring->cur_tx_wp = 0;
1100 ring->cur_tx_rp = 0;
1101 SET_TX_BUFF_DESC_OWN(pdesc, 1);
1102 return;
1103 }
1104 ring->cur_tx_wp = ((ring->cur_tx_wp + 1) % max_tx_desc);
1105
1106 if (over_run) {
1107 ring->cur_tx_wp = 0;
1108 over_run = false;
1109 }
1110 if (ring->avl_desc > 1) {
1111 ring->avl_desc--;
1112
1113 rtl_write_word(rtlpriv,
1114 get_desc_addr_fr_q(q_idx),
1115 ring->cur_tx_wp);
1116
1117 if (q_idx == 1)
1118 last_txw_point = cur_tx_wp;
1119 }
1120
1121 if (ring->avl_desc < (max_tx_desc - 15)) {
1122 u16 point_diff = 0;
1123 tmp = rtl_read_dword(rtlpriv,
1124 get_desc_addr_fr_q(q_idx));
1125 cur_tx_rp = (u16)((tmp >> 16) & 0x0fff);
1126 cur_tx_wp = (u16)(tmp & 0x0fff);
1127
1128 ring->cur_tx_wp = cur_tx_wp;
1129 ring->cur_tx_rp = cur_tx_rp;
1130 point_diff = ((cur_tx_rp > cur_tx_wp) ?
1131 (cur_tx_rp - cur_tx_wp) :
1132 (TX_DESC_NUM_92E - 1 -
1133 cur_tx_wp + cur_tx_rp));
1134
1135 ring->avl_desc = point_diff;
1136 }
1137 }
1138 break;
1139 }
1140 } else {
1141 switch (desc_name) {
1142 case HW_DESC_RX_PREPARE:
1143 SET_RX_BUFFER_DESC_LS(pdesc , 0);
1144 SET_RX_BUFFER_DESC_FS(pdesc , 0);
1145 SET_RX_BUFFER_DESC_TOTAL_LENGTH(pdesc , 0);
1146
1147 SET_RX_BUFFER_DESC_DATA_LENGTH(pdesc,
1148 MAX_RECEIVE_BUFFER_SIZE +
1149 RX_DESC_SIZE);
1150
1151 SET_RX_BUFFER_PHYSICAL_LOW(pdesc, *(u32 *)val);
1152 break;
1153 case HW_DESC_RXERO:
1154 SET_RX_DESC_EOR(pdesc, 1);
1155 break;
1156 default:
1157 RT_ASSERT(false,
1158 ("ERR rxdesc :%d not process\n", desc_name));
1159 break;
1160 }
1161 }
1162 }
1163
1164 u32 rtl92ee_get_desc(u8 *pdesc, bool istx, u8 desc_name)
1165 {
1166 u32 ret = 0;
1167
1168 if (istx) {
1169 switch (desc_name) {
1170 case HW_DESC_OWN:
1171 ret = GET_TX_DESC_OWN(pdesc);
1172 break;
1173 case HW_DESC_TXBUFF_ADDR:
1174 ret = GET_TXBUFFER_DESC_ADDR_LOW(pdesc, 1);
1175 break;
1176 default:
1177 RT_ASSERT(false,
1178 ("ERR txdesc :%d not process\n", desc_name));
1179 break;
1180 }
1181 } else {
1182 switch (desc_name) {
1183 case HW_DESC_OWN:
1184 ret = GET_RX_DESC_OWN(pdesc);
1185 break;
1186 case HW_DESC_RXPKT_LEN:
1187 ret = GET_RX_DESC_PKT_LEN(pdesc);
1188 break;
1189 case HW_DESC_RXBUFF_ADDR:
1190 ret = GET_RX_DESC_BUFF_ADDR(pdesc);
1191 break;
1192 default:
1193 RT_ASSERT(false,
1194 ("ERR rxdesc :%d not process\n", desc_name));
1195 break;
1196 }
1197 }
1198 return ret;
1199 }
1200
1201 bool rtl92ee_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue, u16 index)
1202 {
1203 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1204 struct rtl_priv *rtlpriv = rtl_priv(hw);
1205 u16 read_point, write_point, available_desc_num;
1206 bool ret = false;
1207 static u8 stop_report_cnt;
1208 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
1209
1210 /*checking Read/Write Point each interrupt wastes CPU utilization.*/
1211 if (stop_report_cnt > 15 || !rtlpriv->link_info.b_busytraffic) {
1212 u16 point_diff = 0;
1213 u16 cur_tx_rp, cur_tx_wp;
1214 u32 tmpu32;
1215
1216 tmpu32 = rtl_read_dword(rtlpriv, get_desc_addr_fr_q(hw_queue));
1217 cur_tx_rp = (u16)((tmpu32 >> 16) & 0x0fff);
1218 cur_tx_wp = (u16)(tmpu32 & 0x0fff);
1219
1220 ring->cur_tx_wp = cur_tx_wp;
1221 ring->cur_tx_rp = cur_tx_rp;
1222 point_diff = ((cur_tx_rp > cur_tx_wp) ?
1223 (cur_tx_rp - cur_tx_wp) :
1224 (TX_DESC_NUM_92E - cur_tx_wp + cur_tx_rp));
1225
1226 ring->avl_desc = point_diff;
1227 }
1228
1229 read_point = ring->cur_tx_rp;
1230 write_point = ring->cur_tx_wp;
1231 available_desc_num = ring->avl_desc;
1232
1233 if (write_point > read_point) {
1234 if (index < write_point && index >= read_point)
1235 ret = false;
1236 else
1237 ret = true;
1238 } else if (write_point < read_point) {
1239 if (index > write_point && index < read_point)
1240 ret = true;
1241 else
1242 ret = false;
1243 } else {
1244 if (index != read_point)
1245 ret = true;
1246 }
1247
1248 if (hw_queue == BEACON_QUEUE)
1249 ret = true;
1250
1251 if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1252 rtlpriv->psc.rfoff_reason > RF_CHANGE_BY_PS)
1253 ret = true;
1254
1255 if (hw_queue < BEACON_QUEUE) {
1256 if (!ret)
1257 stop_report_cnt++;
1258 else
1259 stop_report_cnt = 0;
1260 }
1261
1262 return ret;
1263 }
1264
1265 u32 rtl92ee_rx_command_packet(struct ieee80211_hw *hw,
1266 const struct rtl_stats *status,
1267 struct sk_buff *skb)
1268 {
1269 u32 result = 0;
1270 struct rtl_priv *rtlpriv = rtl_priv(hw);
1271
1272 switch (status->packet_report_type) {
1273 case NORMAL_RX:
1274 result = 0;
1275 break;
1276 case C2H_PACKET:
1277 rtl92ee_c2h_packet_handler(hw, skb->data, (u8) skb->len);
1278 result = 1;
1279 break;
1280 default:
1281 RT_TRACE(COMP_RECV, DBG_TRACE, ("No this packet type!!\n"));
1282 break;
1283 }
1284
1285 return result;
1286 }
Linux kernel - Deliverables
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