3 #include "r819xU_phy.h"
4 #include "r819xU_phyreg.h"
5 #include "r8190_rtl8256.h"
7 #include "r819xU_firmware_img.h"
10 #include <linux/bitops.h>
12 static u32 RF_CHANNEL_TABLE_ZEBRA
[] = {
31 #define rtl819XPHY_REG_1T2RArray Rtl8192UsbPHY_REG_1T2RArray
32 #define rtl819XMACPHY_Array_PG Rtl8192UsbMACPHY_Array_PG
33 #define rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array
34 #define rtl819XRadioA_Array Rtl8192UsbRadioA_Array
35 #define rtl819XRadioB_Array Rtl8192UsbRadioB_Array
36 #define rtl819XRadioC_Array Rtl8192UsbRadioC_Array
37 #define rtl819XRadioD_Array Rtl8192UsbRadioD_Array
38 #define rtl819XAGCTAB_Array Rtl8192UsbAGCTAB_Array
40 /******************************************************************************
41 * function: This function checks different RF type to execute legal judgement.
42 * If RF Path is illegal, we will return false.
43 * input: net_device *dev
46 * return: 0(illegal, false), 1(legal, true)
47 *****************************************************************************/
48 u8
rtl8192_phy_CheckIsLegalRFPath(struct net_device
*dev
, u32 eRFPath
)
51 struct r8192_priv
*priv
= ieee80211_priv(dev
);
53 if (priv
->rf_type
== RF_2T4R
) {
55 } else if (priv
->rf_type
== RF_1T2R
) {
56 if (eRFPath
== RF90_PATH_A
|| eRFPath
== RF90_PATH_B
)
58 else if (eRFPath
== RF90_PATH_C
|| eRFPath
== RF90_PATH_D
)
64 /******************************************************************************
65 * function: This function sets specific bits to BB register
66 * input: net_device *dev
67 * u32 reg_addr //target addr to be modified
68 * u32 bitmask //taget bit pos to be modified
69 * u32 data //value to be write
73 ******************************************************************************/
74 void rtl8192_setBBreg(struct net_device
*dev
, u32 reg_addr
, u32 bitmask
,
80 if (bitmask
!= bMaskDWord
) {
81 read_nic_dword(dev
, reg_addr
, ®
);
82 bitshift
= ffs(bitmask
) - 1;
84 reg
|= data
<< bitshift
;
85 write_nic_dword(dev
, reg_addr
, reg
);
87 write_nic_dword(dev
, reg_addr
, data
);
91 /******************************************************************************
92 * function: This function reads specific bits from BB register
93 * input: net_device *dev
94 * u32 reg_addr //target addr to be readback
95 * u32 bitmask //taget bit pos to be readback
97 * return: u32 data //the readback register value
99 ******************************************************************************/
100 u32
rtl8192_QueryBBReg(struct net_device
*dev
, u32 reg_addr
, u32 bitmask
)
104 read_nic_dword(dev
, reg_addr
, ®
);
105 bitshift
= ffs(bitmask
) - 1;
107 return (reg
& bitmask
) >> bitshift
;
110 static u32
phy_FwRFSerialRead(struct net_device
*dev
, RF90_RADIO_PATH_E eRFPath
,
113 static void phy_FwRFSerialWrite(struct net_device
*dev
,
114 RF90_RADIO_PATH_E eRFPath
, u32 offset
,
117 /******************************************************************************
118 * function: This function reads register from RF chip
119 * input: net_device *dev
120 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
121 * u32 offset //target address to be read
123 * return: u32 readback value
124 * notice: There are three types of serial operations:
125 * (1) Software serial write.
126 * (2)Hardware LSSI-Low Speed Serial Interface.
127 * (3)Hardware HSSI-High speed serial write.
128 * Driver here need to implement (1) and (2)
129 * ---need more spec for this information.
130 ******************************************************************************/
131 static u32
rtl8192_phy_RFSerialRead(struct net_device
*dev
,
132 RF90_RADIO_PATH_E eRFPath
, u32 offset
)
134 struct r8192_priv
*priv
= ieee80211_priv(dev
);
137 BB_REGISTER_DEFINITION_T
*pPhyReg
= &priv
->PHYRegDef
[eRFPath
];
139 rtl8192_setBBreg(dev
, pPhyReg
->rfLSSIReadBack
, bLSSIReadBackData
, 0);
140 /* Make sure RF register offset is correct */
143 /* Switch page for 8256 RF IC */
144 if (priv
->rf_chip
== RF_8256
) {
146 priv
->RfReg0Value
[eRFPath
] |= 0x140;
147 /* Switch to Reg_Mode2 for Reg 31-45 */
148 rtl8192_setBBreg(dev
, pPhyReg
->rf3wireOffset
,
150 priv
->RfReg0Value
[eRFPath
]<<16);
152 new_offset
= offset
- 30;
153 } else if (offset
>= 16) {
154 priv
->RfReg0Value
[eRFPath
] |= 0x100;
155 priv
->RfReg0Value
[eRFPath
] &= (~0x40);
156 /* Switch to Reg_Mode1 for Reg16-30 */
157 rtl8192_setBBreg(dev
, pPhyReg
->rf3wireOffset
,
159 priv
->RfReg0Value
[eRFPath
]<<16);
161 new_offset
= offset
- 15;
166 RT_TRACE((COMP_PHY
|COMP_ERR
),
167 "check RF type here, need to be 8256\n");
170 /* Put desired read addr to LSSI control Register */
171 rtl8192_setBBreg(dev
, pPhyReg
->rfHSSIPara2
, bLSSIReadAddress
,
173 /* Issue a posedge trigger */
174 rtl8192_setBBreg(dev
, pPhyReg
->rfHSSIPara2
, bLSSIReadEdge
, 0x0);
175 rtl8192_setBBreg(dev
, pPhyReg
->rfHSSIPara2
, bLSSIReadEdge
, 0x1);
178 /* TODO: we should not delay such a long time. Ask for help from SD3 */
179 usleep_range(1000, 1000);
181 ret
= rtl8192_QueryBBReg(dev
, pPhyReg
->rfLSSIReadBack
,
185 /* Switch back to Reg_Mode0 */
186 if (priv
->rf_chip
== RF_8256
) {
187 priv
->RfReg0Value
[eRFPath
] &= 0xebf;
189 rtl8192_setBBreg(dev
, pPhyReg
->rf3wireOffset
, bMaskDWord
,
190 priv
->RfReg0Value
[eRFPath
] << 16);
196 /******************************************************************************
197 * function: This function writes data to RF register
198 * input: net_device *dev
199 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
200 * u32 offset //target address to be written
201 * u32 data //the new register data to be written
204 * notice: For RF8256 only.
205 * ===========================================================================
206 * Reg Mode RegCTL[1] RegCTL[0] Note
207 * (Reg00[12]) (Reg00[10])
208 * ===========================================================================
209 * Reg_Mode0 0 x Reg 0 ~ 15(0x0 ~ 0xf)
210 * ---------------------------------------------------------------------------
211 * Reg_Mode1 1 0 Reg 16 ~ 30(0x1 ~ 0xf)
212 * ---------------------------------------------------------------------------
213 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
214 * ---------------------------------------------------------------------------
215 *****************************************************************************/
216 static void rtl8192_phy_RFSerialWrite(struct net_device
*dev
,
217 RF90_RADIO_PATH_E eRFPath
, u32 offset
,
220 struct r8192_priv
*priv
= ieee80211_priv(dev
);
221 u32 DataAndAddr
= 0, new_offset
= 0;
222 BB_REGISTER_DEFINITION_T
*pPhyReg
= &priv
->PHYRegDef
[eRFPath
];
225 if (priv
->rf_chip
== RF_8256
) {
228 priv
->RfReg0Value
[eRFPath
] |= 0x140;
229 rtl8192_setBBreg(dev
, pPhyReg
->rf3wireOffset
,
231 priv
->RfReg0Value
[eRFPath
] << 16);
232 new_offset
= offset
- 30;
233 } else if (offset
>= 16) {
234 priv
->RfReg0Value
[eRFPath
] |= 0x100;
235 priv
->RfReg0Value
[eRFPath
] &= (~0x40);
236 rtl8192_setBBreg(dev
, pPhyReg
->rf3wireOffset
,
238 priv
->RfReg0Value
[eRFPath
]<<16);
239 new_offset
= offset
- 15;
244 RT_TRACE((COMP_PHY
|COMP_ERR
),
245 "check RF type here, need to be 8256\n");
249 /* Put write addr in [5:0] and write data in [31:16] */
250 DataAndAddr
= (data
<<16) | (new_offset
&0x3f);
252 /* Write operation */
253 rtl8192_setBBreg(dev
, pPhyReg
->rf3wireOffset
, bMaskDWord
, DataAndAddr
);
257 priv
->RfReg0Value
[eRFPath
] = data
;
259 /* Switch back to Reg_Mode0 */
260 if (priv
->rf_chip
== RF_8256
) {
262 priv
->RfReg0Value
[eRFPath
] &= 0xebf;
263 rtl8192_setBBreg(dev
, pPhyReg
->rf3wireOffset
,
265 priv
->RfReg0Value
[eRFPath
] << 16);
270 /******************************************************************************
271 * function: This function set specific bits to RF register
272 * input: net_device dev
273 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
274 * u32 reg_addr //target addr to be modified
275 * u32 bitmask //taget bit pos to be modified
276 * u32 data //value to be written
280 *****************************************************************************/
281 void rtl8192_phy_SetRFReg(struct net_device
*dev
, RF90_RADIO_PATH_E eRFPath
,
282 u32 reg_addr
, u32 bitmask
, u32 data
)
284 struct r8192_priv
*priv
= ieee80211_priv(dev
);
287 if (!rtl8192_phy_CheckIsLegalRFPath(dev
, eRFPath
))
290 if (priv
->Rf_Mode
== RF_OP_By_FW
) {
291 if (bitmask
!= bMask12Bits
) {
292 /* RF data is 12 bits only */
293 reg
= phy_FwRFSerialRead(dev
, eRFPath
, reg_addr
);
294 bitshift
= ffs(bitmask
) - 1;
296 reg
|= data
<< bitshift
;
298 phy_FwRFSerialWrite(dev
, eRFPath
, reg_addr
, reg
);
300 phy_FwRFSerialWrite(dev
, eRFPath
, reg_addr
, data
);
306 if (bitmask
!= bMask12Bits
) {
307 /* RF data is 12 bits only */
308 reg
= rtl8192_phy_RFSerialRead(dev
, eRFPath
, reg_addr
);
309 bitshift
= ffs(bitmask
) - 1;
311 reg
|= data
<< bitshift
;
313 rtl8192_phy_RFSerialWrite(dev
, eRFPath
, reg_addr
, reg
);
315 rtl8192_phy_RFSerialWrite(dev
, eRFPath
, reg_addr
, data
);
320 /******************************************************************************
321 * function: This function reads specific bits from RF register
322 * input: net_device *dev
323 * u32 reg_addr //target addr to be readback
324 * u32 bitmask //taget bit pos to be readback
326 * return: u32 data //the readback register value
328 *****************************************************************************/
329 u32
rtl8192_phy_QueryRFReg(struct net_device
*dev
, RF90_RADIO_PATH_E eRFPath
,
330 u32 reg_addr
, u32 bitmask
)
333 struct r8192_priv
*priv
= ieee80211_priv(dev
);
336 if (!rtl8192_phy_CheckIsLegalRFPath(dev
, eRFPath
))
338 if (priv
->Rf_Mode
== RF_OP_By_FW
) {
339 reg
= phy_FwRFSerialRead(dev
, eRFPath
, reg_addr
);
342 reg
= rtl8192_phy_RFSerialRead(dev
, eRFPath
, reg_addr
);
344 bitshift
= ffs(bitmask
) - 1;
345 reg
= (reg
& bitmask
) >> bitshift
;
350 /******************************************************************************
351 * function: We support firmware to execute RF-R/W.
352 * input: net_device *dev
353 * RF90_RADIO_PATH_E eRFPath
358 ****************************************************************************/
359 static u32
phy_FwRFSerialRead(struct net_device
*dev
, RF90_RADIO_PATH_E eRFPath
,
367 /* Firmware RF Write control.
368 * We can not execute the scheme in the initial step.
369 * Otherwise, RF-R/W will waste much time.
370 * This is only for site survey. */
371 /* 1. Read operation need not insert data. bit 0-11 */
372 /* 2. Write RF register address. bit 12-19 */
373 data
|= ((offset
&0xFF)<<12);
374 /* 3. Write RF path. bit 20-21 */
375 data
|= ((eRFPath
&0x3)<<20);
376 /* 4. Set RF read indicator. bit 22=0 */
377 /* 5. Trigger Fw to operate the command. bit 31 */
379 /* 6. We can not execute read operation if bit 31 is 1. */
380 read_nic_dword(dev
, QPNR
, &tmp
);
381 while (tmp
& 0x80000000) {
382 /* If FW can not finish RF-R/W for more than ?? times.
386 read_nic_dword(dev
, QPNR
, &tmp
);
391 /* 7. Execute read operation. */
392 write_nic_dword(dev
, QPNR
, data
);
393 /* 8. Check if firmware send back RF content. */
394 read_nic_dword(dev
, QPNR
, &tmp
);
395 while (tmp
& 0x80000000) {
396 /* If FW can not finish RF-R/W for more than ?? times.
400 read_nic_dword(dev
, QPNR
, &tmp
);
405 read_nic_dword(dev
, RF_DATA
, ®
);
410 /******************************************************************************
411 * function: We support firmware to execute RF-R/W.
412 * input: net_device *dev
413 * RF90_RADIO_PATH_E eRFPath
419 ****************************************************************************/
420 static void phy_FwRFSerialWrite(struct net_device
*dev
,
421 RF90_RADIO_PATH_E eRFPath
, u32 offset
, u32 data
)
426 /* Firmware RF Write control.
427 * We can not execute the scheme in the initial step.
428 * Otherwise, RF-R/W will waste much time.
429 * This is only for site survey. */
431 /* 1. Set driver write bit and 12 bit data. bit 0-11 */
432 /* 2. Write RF register address. bit 12-19 */
433 data
|= ((offset
&0xFF)<<12);
434 /* 3. Write RF path. bit 20-21 */
435 data
|= ((eRFPath
&0x3)<<20);
436 /* 4. Set RF write indicator. bit 22=1 */
438 /* 5. Trigger Fw to operate the command. bit 31=1 */
441 /* 6. Write operation. We can not write if bit 31 is 1. */
442 read_nic_dword(dev
, QPNR
, &tmp
);
443 while (tmp
& 0x80000000) {
444 /* If FW can not finish RF-R/W for more than ?? times.
448 read_nic_dword(dev
, QPNR
, &tmp
);
453 /* 7. No matter check bit. We always force the write.
454 Because FW will not accept the command. */
455 write_nic_dword(dev
, QPNR
, data
);
456 /* According to test, we must delay 20us to wait firmware
457 to finish RF write operation. */
458 /* We support delay in firmware side now. */
461 /******************************************************************************
462 * function: This function reads BB parameters from header file we generate,
463 * and do register read/write
464 * input: net_device *dev
467 * notice: BB parameters may change all the time, so please make
468 * sure it has been synced with the newest.
469 *****************************************************************************/
470 void rtl8192_phy_configmac(struct net_device
*dev
)
472 u32 dwArrayLen
= 0, i
;
473 u32
*pdwArray
= NULL
;
474 struct r8192_priv
*priv
= ieee80211_priv(dev
);
476 if (priv
->btxpowerdata_readfromEEPORM
) {
477 RT_TRACE(COMP_PHY
, "Rtl819XMACPHY_Array_PG\n");
478 dwArrayLen
= MACPHY_Array_PGLength
;
479 pdwArray
= rtl819XMACPHY_Array_PG
;
482 RT_TRACE(COMP_PHY
, "Rtl819XMACPHY_Array\n");
483 dwArrayLen
= MACPHY_ArrayLength
;
484 pdwArray
= rtl819XMACPHY_Array
;
486 for (i
= 0; i
< dwArrayLen
; i
= i
+3) {
487 if (pdwArray
[i
] == 0x318)
488 pdwArray
[i
+2] = 0x00000800;
491 "Rtl8190MACPHY_Array[0]=%x Rtl8190MACPHY_Array[1]=%x Rtl8190MACPHY_Array[2]=%x\n",
492 pdwArray
[i
], pdwArray
[i
+1], pdwArray
[i
+2]);
493 rtl8192_setBBreg(dev
, pdwArray
[i
], pdwArray
[i
+1],
498 /******************************************************************************
499 * function: This function does dirty work
500 * input: net_device *dev
504 * notice: BB parameters may change all the time, so please make
505 * sure it has been synced with the newest.
506 *****************************************************************************/
507 void rtl8192_phyConfigBB(struct net_device
*dev
, u8 ConfigType
)
512 u32
*rtl8192PhyRegArrayTable
= NULL
, *rtl8192AgcTabArrayTable
= NULL
;
514 if (Adapter
->bInHctTest
) {
515 PHY_REGArrayLen
= PHY_REGArrayLengthDTM
;
516 AGCTAB_ArrayLen
= AGCTAB_ArrayLengthDTM
;
517 Rtl8190PHY_REGArray_Table
= Rtl819XPHY_REGArrayDTM
;
518 Rtl8190AGCTAB_Array_Table
= Rtl819XAGCTAB_ArrayDTM
;
521 if (ConfigType
== BaseBand_Config_PHY_REG
) {
522 for (i
= 0; i
< PHY_REG_1T2RArrayLength
; i
+= 2) {
523 rtl8192_setBBreg(dev
, rtl819XPHY_REG_1T2RArray
[i
],
525 rtl819XPHY_REG_1T2RArray
[i
+1]);
527 "i: %x, Rtl819xUsbPHY_REGArray[0]=%x Rtl819xUsbPHY_REGArray[1]=%x\n",
528 i
, rtl819XPHY_REG_1T2RArray
[i
],
529 rtl819XPHY_REG_1T2RArray
[i
+1]);
531 } else if (ConfigType
== BaseBand_Config_AGC_TAB
) {
532 for (i
= 0; i
< AGCTAB_ArrayLength
; i
+= 2) {
533 rtl8192_setBBreg(dev
, rtl819XAGCTAB_Array
[i
],
534 bMaskDWord
, rtl819XAGCTAB_Array
[i
+1]);
536 "i: %x, rtl819XAGCTAB_Array[0]=%x rtl819XAGCTAB_Array[1]=%x\n",
537 i
, rtl819XAGCTAB_Array
[i
],
538 rtl819XAGCTAB_Array
[i
+1]);
543 /******************************************************************************
544 * function: This function initializes Register definition offset for
546 * input: net_device *dev
549 * notice: Initialization value here is constant and it should never
551 *****************************************************************************/
552 static void rtl8192_InitBBRFRegDef(struct net_device
*dev
)
554 struct r8192_priv
*priv
= ieee80211_priv(dev
);
556 /* RF Interface Software Control */
557 /* 16 LSBs if read 32-bit from 0x870 */
558 priv
->PHYRegDef
[RF90_PATH_A
].rfintfs
= rFPGA0_XAB_RFInterfaceSW
;
559 /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
560 priv
->PHYRegDef
[RF90_PATH_B
].rfintfs
= rFPGA0_XAB_RFInterfaceSW
;
561 /* 16 LSBs if read 32-bit from 0x874 */
562 priv
->PHYRegDef
[RF90_PATH_C
].rfintfs
= rFPGA0_XCD_RFInterfaceSW
;
563 /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */
564 priv
->PHYRegDef
[RF90_PATH_D
].rfintfs
= rFPGA0_XCD_RFInterfaceSW
;
566 /* RF Interface Readback Value */
567 /* 16 LSBs if read 32-bit from 0x8E0 */
568 priv
->PHYRegDef
[RF90_PATH_A
].rfintfi
= rFPGA0_XAB_RFInterfaceRB
;
569 /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */
570 priv
->PHYRegDef
[RF90_PATH_B
].rfintfi
= rFPGA0_XAB_RFInterfaceRB
;
571 /* 16 LSBs if read 32-bit from 0x8E4 */
572 priv
->PHYRegDef
[RF90_PATH_C
].rfintfi
= rFPGA0_XCD_RFInterfaceRB
;
573 /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */
574 priv
->PHYRegDef
[RF90_PATH_D
].rfintfi
= rFPGA0_XCD_RFInterfaceRB
;
576 /* RF Interface Output (and Enable) */
577 /* 16 LSBs if read 32-bit from 0x860 */
578 priv
->PHYRegDef
[RF90_PATH_A
].rfintfo
= rFPGA0_XA_RFInterfaceOE
;
579 /* 16 LSBs if read 32-bit from 0x864 */
580 priv
->PHYRegDef
[RF90_PATH_B
].rfintfo
= rFPGA0_XB_RFInterfaceOE
;
581 /* 16 LSBs if read 32-bit from 0x868 */
582 priv
->PHYRegDef
[RF90_PATH_C
].rfintfo
= rFPGA0_XC_RFInterfaceOE
;
583 /* 16 LSBs if read 32-bit from 0x86C */
584 priv
->PHYRegDef
[RF90_PATH_D
].rfintfo
= rFPGA0_XD_RFInterfaceOE
;
586 /* RF Interface (Output and) Enable */
587 /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
588 priv
->PHYRegDef
[RF90_PATH_A
].rfintfe
= rFPGA0_XA_RFInterfaceOE
;
589 /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
590 priv
->PHYRegDef
[RF90_PATH_B
].rfintfe
= rFPGA0_XB_RFInterfaceOE
;
591 /* 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A) */
592 priv
->PHYRegDef
[RF90_PATH_C
].rfintfe
= rFPGA0_XC_RFInterfaceOE
;
593 /* 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E) */
594 priv
->PHYRegDef
[RF90_PATH_D
].rfintfe
= rFPGA0_XD_RFInterfaceOE
;
596 /* Addr of LSSI. Write RF register by driver */
597 priv
->PHYRegDef
[RF90_PATH_A
].rf3wireOffset
= rFPGA0_XA_LSSIParameter
;
598 priv
->PHYRegDef
[RF90_PATH_B
].rf3wireOffset
= rFPGA0_XB_LSSIParameter
;
599 priv
->PHYRegDef
[RF90_PATH_C
].rf3wireOffset
= rFPGA0_XC_LSSIParameter
;
600 priv
->PHYRegDef
[RF90_PATH_D
].rf3wireOffset
= rFPGA0_XD_LSSIParameter
;
604 priv
->PHYRegDef
[RF90_PATH_A
].rfLSSI_Select
= rFPGA0_XAB_RFParameter
;
605 priv
->PHYRegDef
[RF90_PATH_B
].rfLSSI_Select
= rFPGA0_XAB_RFParameter
;
606 priv
->PHYRegDef
[RF90_PATH_C
].rfLSSI_Select
= rFPGA0_XCD_RFParameter
;
607 priv
->PHYRegDef
[RF90_PATH_D
].rfLSSI_Select
= rFPGA0_XCD_RFParameter
;
609 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
610 priv
->PHYRegDef
[RF90_PATH_A
].rfTxGainStage
= rFPGA0_TxGainStage
;
611 priv
->PHYRegDef
[RF90_PATH_B
].rfTxGainStage
= rFPGA0_TxGainStage
;
612 priv
->PHYRegDef
[RF90_PATH_C
].rfTxGainStage
= rFPGA0_TxGainStage
;
613 priv
->PHYRegDef
[RF90_PATH_D
].rfTxGainStage
= rFPGA0_TxGainStage
;
615 /* Tranceiver A~D HSSI Parameter-1 */
616 /* wire control parameter1 */
617 priv
->PHYRegDef
[RF90_PATH_A
].rfHSSIPara1
= rFPGA0_XA_HSSIParameter1
;
618 priv
->PHYRegDef
[RF90_PATH_B
].rfHSSIPara1
= rFPGA0_XB_HSSIParameter1
;
619 priv
->PHYRegDef
[RF90_PATH_C
].rfHSSIPara1
= rFPGA0_XC_HSSIParameter1
;
620 priv
->PHYRegDef
[RF90_PATH_D
].rfHSSIPara1
= rFPGA0_XD_HSSIParameter1
;
622 /* Tranceiver A~D HSSI Parameter-2 */
623 /* wire control parameter2 */
624 priv
->PHYRegDef
[RF90_PATH_A
].rfHSSIPara2
= rFPGA0_XA_HSSIParameter2
;
625 priv
->PHYRegDef
[RF90_PATH_B
].rfHSSIPara2
= rFPGA0_XB_HSSIParameter2
;
626 priv
->PHYRegDef
[RF90_PATH_C
].rfHSSIPara2
= rFPGA0_XC_HSSIParameter2
;
627 priv
->PHYRegDef
[RF90_PATH_D
].rfHSSIPara2
= rFPGA0_XD_HSSIParameter2
;
629 /* RF Switch Control */
630 /* TR/Ant switch control */
631 priv
->PHYRegDef
[RF90_PATH_A
].rfSwitchControl
= rFPGA0_XAB_SwitchControl
;
632 priv
->PHYRegDef
[RF90_PATH_B
].rfSwitchControl
= rFPGA0_XAB_SwitchControl
;
633 priv
->PHYRegDef
[RF90_PATH_C
].rfSwitchControl
= rFPGA0_XCD_SwitchControl
;
634 priv
->PHYRegDef
[RF90_PATH_D
].rfSwitchControl
= rFPGA0_XCD_SwitchControl
;
637 priv
->PHYRegDef
[RF90_PATH_A
].rfAGCControl1
= rOFDM0_XAAGCCore1
;
638 priv
->PHYRegDef
[RF90_PATH_B
].rfAGCControl1
= rOFDM0_XBAGCCore1
;
639 priv
->PHYRegDef
[RF90_PATH_C
].rfAGCControl1
= rOFDM0_XCAGCCore1
;
640 priv
->PHYRegDef
[RF90_PATH_D
].rfAGCControl1
= rOFDM0_XDAGCCore1
;
643 priv
->PHYRegDef
[RF90_PATH_A
].rfAGCControl2
= rOFDM0_XAAGCCore2
;
644 priv
->PHYRegDef
[RF90_PATH_B
].rfAGCControl2
= rOFDM0_XBAGCCore2
;
645 priv
->PHYRegDef
[RF90_PATH_C
].rfAGCControl2
= rOFDM0_XCAGCCore2
;
646 priv
->PHYRegDef
[RF90_PATH_D
].rfAGCControl2
= rOFDM0_XDAGCCore2
;
648 /* RX AFE control 1 */
649 priv
->PHYRegDef
[RF90_PATH_A
].rfRxIQImbalance
= rOFDM0_XARxIQImbalance
;
650 priv
->PHYRegDef
[RF90_PATH_B
].rfRxIQImbalance
= rOFDM0_XBRxIQImbalance
;
651 priv
->PHYRegDef
[RF90_PATH_C
].rfRxIQImbalance
= rOFDM0_XCRxIQImbalance
;
652 priv
->PHYRegDef
[RF90_PATH_D
].rfRxIQImbalance
= rOFDM0_XDRxIQImbalance
;
654 /* RX AFE control 1 */
655 priv
->PHYRegDef
[RF90_PATH_A
].rfRxAFE
= rOFDM0_XARxAFE
;
656 priv
->PHYRegDef
[RF90_PATH_B
].rfRxAFE
= rOFDM0_XBRxAFE
;
657 priv
->PHYRegDef
[RF90_PATH_C
].rfRxAFE
= rOFDM0_XCRxAFE
;
658 priv
->PHYRegDef
[RF90_PATH_D
].rfRxAFE
= rOFDM0_XDRxAFE
;
660 /* Tx AFE control 1 */
661 priv
->PHYRegDef
[RF90_PATH_A
].rfTxIQImbalance
= rOFDM0_XATxIQImbalance
;
662 priv
->PHYRegDef
[RF90_PATH_B
].rfTxIQImbalance
= rOFDM0_XBTxIQImbalance
;
663 priv
->PHYRegDef
[RF90_PATH_C
].rfTxIQImbalance
= rOFDM0_XCTxIQImbalance
;
664 priv
->PHYRegDef
[RF90_PATH_D
].rfTxIQImbalance
= rOFDM0_XDTxIQImbalance
;
666 /* Tx AFE control 2 */
667 priv
->PHYRegDef
[RF90_PATH_A
].rfTxAFE
= rOFDM0_XATxAFE
;
668 priv
->PHYRegDef
[RF90_PATH_B
].rfTxAFE
= rOFDM0_XBTxAFE
;
669 priv
->PHYRegDef
[RF90_PATH_C
].rfTxAFE
= rOFDM0_XCTxAFE
;
670 priv
->PHYRegDef
[RF90_PATH_D
].rfTxAFE
= rOFDM0_XDTxAFE
;
672 /* Tranceiver LSSI Readback */
673 priv
->PHYRegDef
[RF90_PATH_A
].rfLSSIReadBack
= rFPGA0_XA_LSSIReadBack
;
674 priv
->PHYRegDef
[RF90_PATH_B
].rfLSSIReadBack
= rFPGA0_XB_LSSIReadBack
;
675 priv
->PHYRegDef
[RF90_PATH_C
].rfLSSIReadBack
= rFPGA0_XC_LSSIReadBack
;
676 priv
->PHYRegDef
[RF90_PATH_D
].rfLSSIReadBack
= rFPGA0_XD_LSSIReadBack
;
679 /******************************************************************************
680 * function: This function is to write register and then readback to make
681 * sure whether BB and RF is OK
682 * input: net_device *dev
683 * HW90_BLOCK_E CheckBlock
684 * RF90_RADIO_PATH_E eRFPath //only used when checkblock is
687 * return: return whether BB and RF is ok (0:OK, 1:Fail)
688 * notice: This function may be removed in the ASIC
689 ******************************************************************************/
690 u8
rtl8192_phy_checkBBAndRF(struct net_device
*dev
, HW90_BLOCK_E CheckBlock
,
691 RF90_RADIO_PATH_E eRFPath
)
694 u32 i
, CheckTimes
= 4, reg
= 0;
696 u32 WriteData
[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
698 /* Initialize register address offset to be checked */
699 WriteAddr
[HW90_BLOCK_MAC
] = 0x100;
700 WriteAddr
[HW90_BLOCK_PHY0
] = 0x900;
701 WriteAddr
[HW90_BLOCK_PHY1
] = 0x800;
702 WriteAddr
[HW90_BLOCK_RF
] = 0x3;
703 RT_TRACE(COMP_PHY
, "%s(), CheckBlock: %d\n", __func__
, CheckBlock
);
704 for (i
= 0; i
< CheckTimes
; i
++) {
706 /* Write data to register and readback */
707 switch (CheckBlock
) {
710 "PHY_CheckBBRFOK(): Never Write 0x100 here!\n");
713 case HW90_BLOCK_PHY0
:
714 case HW90_BLOCK_PHY1
:
715 write_nic_dword(dev
, WriteAddr
[CheckBlock
],
717 read_nic_dword(dev
, WriteAddr
[CheckBlock
], ®
);
721 WriteData
[i
] &= 0xfff;
722 rtl8192_phy_SetRFReg(dev
, eRFPath
,
723 WriteAddr
[HW90_BLOCK_RF
],
724 bMask12Bits
, WriteData
[i
]);
725 /* TODO: we should not delay for such a long time.
727 usleep_range(1000, 1000);
728 reg
= rtl8192_phy_QueryRFReg(dev
, eRFPath
,
729 WriteAddr
[HW90_BLOCK_RF
],
731 usleep_range(1000, 1000);
740 /* Check whether readback data is correct */
741 if (reg
!= WriteData
[i
]) {
742 RT_TRACE((COMP_PHY
|COMP_ERR
),
743 "error reg: %x, WriteData: %x\n",
753 /******************************************************************************
754 * function: This function initializes BB&RF
755 * input: net_device *dev
758 * notice: Initialization value may change all the time, so please make
759 * sure it has been synced with the newest.
760 ******************************************************************************/
761 static void rtl8192_BB_Config_ParaFile(struct net_device
*dev
)
763 struct r8192_priv
*priv
= ieee80211_priv(dev
);
764 u8 reg_u8
= 0, eCheckItem
= 0, status
= 0;
767 /**************************************
768 * <1> Initialize BaseBand
769 *************************************/
771 /* --set BB Global Reset-- */
772 read_nic_byte(dev
, BB_GLOBAL_RESET
, ®_u8
);
773 write_nic_byte(dev
, BB_GLOBAL_RESET
, (reg_u8
|BB_GLOBAL_RESET_BIT
));
775 /* ---set BB reset Active--- */
776 read_nic_dword(dev
, CPU_GEN
, ®_u32
);
777 write_nic_dword(dev
, CPU_GEN
, (reg_u32
&(~CPU_GEN_BB_RST
)));
779 /* ----Ckeck FPGAPHY0 and PHY1 board is OK---- */
780 /* TODO: this function should be removed on ASIC */
781 for (eCheckItem
= (HW90_BLOCK_E
)HW90_BLOCK_PHY0
;
782 eCheckItem
<= HW90_BLOCK_PHY1
; eCheckItem
++) {
783 /* don't care RF path */
784 status
= rtl8192_phy_checkBBAndRF(dev
, (HW90_BLOCK_E
)eCheckItem
,
785 (RF90_RADIO_PATH_E
)0);
787 RT_TRACE((COMP_ERR
| COMP_PHY
),
788 "PHY_RF8256_Config(): Check PHY%d Fail!!\n",
793 /* ---- Set CCK and OFDM Block "OFF"---- */
794 rtl8192_setBBreg(dev
, rFPGA0_RFMOD
, bCCKEn
|bOFDMEn
, 0x0);
795 /* ----BB Register Initilazation---- */
796 /* ==m==>Set PHY REG From Header<==m== */
797 rtl8192_phyConfigBB(dev
, BaseBand_Config_PHY_REG
);
799 /* ----Set BB reset de-Active---- */
800 read_nic_dword(dev
, CPU_GEN
, ®_u32
);
801 write_nic_dword(dev
, CPU_GEN
, (reg_u32
|CPU_GEN_BB_RST
));
803 /* ----BB AGC table Initialization---- */
804 /* ==m==>Set PHY REG From Header<==m== */
805 rtl8192_phyConfigBB(dev
, BaseBand_Config_AGC_TAB
);
807 /* ----Enable XSTAL ---- */
808 write_nic_byte_E(dev
, 0x5e, 0x00);
809 if (priv
->card_8192_version
== (u8
)VERSION_819xU_A
) {
810 /* Antenna gain offset from B/C/D to A */
811 reg_u32
= priv
->AntennaTxPwDiff
[1]<<4 |
812 priv
->AntennaTxPwDiff
[0];
813 rtl8192_setBBreg(dev
, rFPGA0_TxGainStage
, (bXBTxAGC
|bXCTxAGC
),
817 reg_u32
= priv
->CrystalCap
& 0xf;
818 rtl8192_setBBreg(dev
, rFPGA0_AnalogParameter1
, bXtalCap
,
822 /* Check if the CCK HighPower is turned ON.
823 This is used to calculate PWDB. */
824 priv
->bCckHighPower
= (u8
)rtl8192_QueryBBReg(dev
,
825 rFPGA0_XA_HSSIParameter2
,
829 /******************************************************************************
830 * function: This function initializes BB&RF
831 * input: net_device *dev
834 * notice: Initialization value may change all the time, so please make
835 * sure it has been synced with the newest.
836 *****************************************************************************/
837 void rtl8192_BBConfig(struct net_device
*dev
)
839 rtl8192_InitBBRFRegDef(dev
);
840 /* config BB&RF. As hardCode based initialization has not been well
841 * implemented, so use file first.
842 * FIXME: should implement it for hardcode? */
843 rtl8192_BB_Config_ParaFile(dev
);
847 /******************************************************************************
848 * function: This function obtains the initialization value of Tx power Level
850 * input: net_device *dev
853 *****************************************************************************/
854 void rtl8192_phy_getTxPower(struct net_device
*dev
)
856 struct r8192_priv
*priv
= ieee80211_priv(dev
);
859 read_nic_dword(dev
, rTxAGC_Rate18_06
,
860 &priv
->MCSTxPowerLevelOriginalOffset
[0]);
861 read_nic_dword(dev
, rTxAGC_Rate54_24
,
862 &priv
->MCSTxPowerLevelOriginalOffset
[1]);
863 read_nic_dword(dev
, rTxAGC_Mcs03_Mcs00
,
864 &priv
->MCSTxPowerLevelOriginalOffset
[2]);
865 read_nic_dword(dev
, rTxAGC_Mcs07_Mcs04
,
866 &priv
->MCSTxPowerLevelOriginalOffset
[3]);
867 read_nic_dword(dev
, rTxAGC_Mcs11_Mcs08
,
868 &priv
->MCSTxPowerLevelOriginalOffset
[4]);
869 read_nic_dword(dev
, rTxAGC_Mcs15_Mcs12
,
870 &priv
->MCSTxPowerLevelOriginalOffset
[5]);
872 /* Read rx initial gain */
873 read_nic_byte(dev
, rOFDM0_XAAGCCore1
, &priv
->DefaultInitialGain
[0]);
874 read_nic_byte(dev
, rOFDM0_XBAGCCore1
, &priv
->DefaultInitialGain
[1]);
875 read_nic_byte(dev
, rOFDM0_XCAGCCore1
, &priv
->DefaultInitialGain
[2]);
876 read_nic_byte(dev
, rOFDM0_XDAGCCore1
, &priv
->DefaultInitialGain
[3]);
878 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n",
879 priv
->DefaultInitialGain
[0], priv
->DefaultInitialGain
[1],
880 priv
->DefaultInitialGain
[2], priv
->DefaultInitialGain
[3]);
883 read_nic_byte(dev
, rOFDM0_RxDetector3
, &priv
->framesync
);
884 read_nic_byte(dev
, rOFDM0_RxDetector2
, &tmp
);
885 priv
->framesyncC34
= tmp
;
886 RT_TRACE(COMP_INIT
, "Default framesync (0x%x) = 0x%x\n",
887 rOFDM0_RxDetector3
, priv
->framesync
);
889 /* Read SIFS (save the value read fome MACPHY_REG.txt) */
890 read_nic_word(dev
, SIFS
, &priv
->SifsTime
);
893 /******************************************************************************
894 * function: This function sets the initialization value of Tx power Level
896 * input: net_device *dev
900 ******************************************************************************/
901 void rtl8192_phy_setTxPower(struct net_device
*dev
, u8 channel
)
903 struct r8192_priv
*priv
= ieee80211_priv(dev
);
904 u8 powerlevel
= priv
->TxPowerLevelCCK
[channel
-1];
905 u8 powerlevelOFDM24G
= priv
->TxPowerLevelOFDM24G
[channel
-1];
907 switch (priv
->rf_chip
) {
909 /* need further implement */
910 PHY_SetRF8256CCKTxPower(dev
, powerlevel
);
911 PHY_SetRF8256OFDMTxPower(dev
, powerlevelOFDM24G
);
914 RT_TRACE((COMP_PHY
|COMP_ERR
),
915 "error RF chipID(8225 or 8258) in function %s()\n",
921 /******************************************************************************
922 * function: This function checks Rf chip to do RF config
923 * input: net_device *dev
925 * return: only 8256 is supported
926 ******************************************************************************/
927 void rtl8192_phy_RFConfig(struct net_device
*dev
)
929 struct r8192_priv
*priv
= ieee80211_priv(dev
);
931 switch (priv
->rf_chip
) {
933 PHY_RF8256_Config(dev
);
936 RT_TRACE(COMP_ERR
, "error chip id\n");
941 /******************************************************************************
942 * function: This function updates Initial gain
943 * input: net_device *dev
945 * return: As Windows has not implemented this, wait for complement
946 ******************************************************************************/
947 void rtl8192_phy_updateInitGain(struct net_device
*dev
)
951 /******************************************************************************
952 * function: This function read RF parameters from general head file,
954 * input: net_device *dev
955 * RF90_RADIO_PATH_E eRFPath
957 * return: return code show if RF configuration is successful(0:pass, 1:fail)
958 * notice: Delay may be required for RF configuration
959 *****************************************************************************/
960 u8
rtl8192_phy_ConfigRFWithHeaderFile(struct net_device
*dev
,
961 RF90_RADIO_PATH_E eRFPath
)
968 for (i
= 0; i
< RadioA_ArrayLength
; i
= i
+2) {
970 if (rtl819XRadioA_Array
[i
] == 0xfe) {
974 rtl8192_phy_SetRFReg(dev
, eRFPath
,
975 rtl819XRadioA_Array
[i
],
977 rtl819XRadioA_Array
[i
+1]);
983 for (i
= 0; i
< RadioB_ArrayLength
; i
= i
+2) {
985 if (rtl819XRadioB_Array
[i
] == 0xfe) {
989 rtl8192_phy_SetRFReg(dev
, eRFPath
,
990 rtl819XRadioB_Array
[i
],
992 rtl819XRadioB_Array
[i
+1]);
998 for (i
= 0; i
< RadioC_ArrayLength
; i
= i
+2) {
1000 if (rtl819XRadioC_Array
[i
] == 0xfe) {
1004 rtl8192_phy_SetRFReg(dev
, eRFPath
,
1005 rtl819XRadioC_Array
[i
],
1007 rtl819XRadioC_Array
[i
+1]);
1013 for (i
= 0; i
< RadioD_ArrayLength
; i
= i
+2) {
1015 if (rtl819XRadioD_Array
[i
] == 0xfe) {
1019 rtl8192_phy_SetRFReg(dev
, eRFPath
,
1020 rtl819XRadioD_Array
[i
],
1022 rtl819XRadioD_Array
[i
+1]);
1035 /******************************************************************************
1036 * function: This function sets Tx Power of the channel
1037 * input: net_device *dev
1042 ******************************************************************************/
1043 static void rtl8192_SetTxPowerLevel(struct net_device
*dev
, u8 channel
)
1045 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1046 u8 powerlevel
= priv
->TxPowerLevelCCK
[channel
-1];
1047 u8 powerlevelOFDM24G
= priv
->TxPowerLevelOFDM24G
[channel
-1];
1049 switch (priv
->rf_chip
) {
1052 PHY_SetRF8225CckTxPower(Adapter
, powerlevel
);
1053 PHY_SetRF8225OfdmTxPower(Adapter
, powerlevelOFDM24G
);
1058 PHY_SetRF8256CCKTxPower(dev
, powerlevel
);
1059 PHY_SetRF8256OFDMTxPower(dev
, powerlevelOFDM24G
);
1065 RT_TRACE(COMP_ERR
, "unknown rf chip ID in %s()\n", __func__
);
1070 /******************************************************************************
1071 * function: This function sets RF state on or off
1072 * input: net_device *dev
1073 * RT_RF_POWER_STATE eRFPowerState //Power State to set
1077 *****************************************************************************/
1078 bool rtl8192_SetRFPowerState(struct net_device
*dev
,
1079 RT_RF_POWER_STATE eRFPowerState
)
1081 bool bResult
= true;
1082 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1084 if (eRFPowerState
== priv
->ieee80211
->eRFPowerState
)
1087 if (priv
->SetRFPowerStateInProgress
)
1090 priv
->SetRFPowerStateInProgress
= true;
1092 switch (priv
->rf_chip
) {
1094 switch (eRFPowerState
) {
1097 /* enable RF-Chip A/B - 0x860[4] */
1098 rtl8192_setBBreg(dev
, rFPGA0_XA_RFInterfaceOE
, BIT(4),
1100 /* analog to digital on - 0x88c[9:8] */
1101 rtl8192_setBBreg(dev
, rFPGA0_AnalogParameter4
, 0x300,
1103 /* digital to analog on - 0x880[4:3] */
1104 rtl8192_setBBreg(dev
, rFPGA0_AnalogParameter1
, 0x18,
1106 /* rx antenna on - 0xc04[1:0] */
1107 rtl8192_setBBreg(dev
, rOFDM0_TRxPathEnable
, 0x3, 0x3);
1108 /* rx antenna on - 0xd04[1:0] */
1109 rtl8192_setBBreg(dev
, rOFDM1_TRxPathEnable
, 0x3, 0x3);
1110 /* analog to digital part2 on - 0x880[6:5] */
1111 rtl8192_setBBreg(dev
, rFPGA0_AnalogParameter1
, 0x60,
1122 /* disable RF-Chip A/B - 0x860[4] */
1123 rtl8192_setBBreg(dev
, rFPGA0_XA_RFInterfaceOE
, BIT(4),
1125 /* analog to digital off, for power save */
1126 rtl8192_setBBreg(dev
, rFPGA0_AnalogParameter4
, 0xf00,
1127 0x0); /* 0x88c[11:8] */
1128 /* digital to analog off, for power save - 0x880[4:3] */
1129 rtl8192_setBBreg(dev
, rFPGA0_AnalogParameter1
, 0x18,
1131 /* rx antenna off - 0xc04[3:0] */
1132 rtl8192_setBBreg(dev
, rOFDM0_TRxPathEnable
, 0xf, 0x0);
1133 /* rx antenna off - 0xd04[3:0] */
1134 rtl8192_setBBreg(dev
, rOFDM1_TRxPathEnable
, 0xf, 0x0);
1135 /* analog to digital part2 off, for power save */
1136 rtl8192_setBBreg(dev
, rFPGA0_AnalogParameter1
, 0x60,
1137 0x0); /* 0x880[6:5] */
1143 RT_TRACE(COMP_ERR
, "%s(): unknown state to set: 0x%X\n",
1144 __func__
, eRFPowerState
);
1149 RT_TRACE(COMP_ERR
, "Not support rf_chip(%x)\n", priv
->rf_chip
);
1154 /* Update current RF state variable. */
1155 pHalData
->eRFPowerState
= eRFPowerState
;
1156 switch (pHalData
->RFChipID
) {
1158 switch (pHalData
->eRFPowerState
) {
1160 /* If Rf off reason is from IPS,
1161 LED should blink with no link */
1162 if (pMgntInfo
->RfOffReason
== RF_CHANGE_BY_IPS
)
1163 Adapter
->HalFunc
.LedControlHandler(Adapter
, LED_CTL_NO_LINK
);
1165 /* Turn off LED if RF is not ON. */
1166 Adapter
->HalFunc
.LedControlHandler(Adapter
, LED_CTL_POWER_OFF
);
1170 /* Turn on RF we are still linked, which might
1171 happen when we quickly turn off and on HW RF.
1173 if (pMgntInfo
->bMediaConnect
)
1174 Adapter
->HalFunc
.LedControlHandler(Adapter
, LED_CTL_LINK
);
1176 /* Turn off LED if RF is not ON. */
1177 Adapter
->HalFunc
.LedControlHandler(Adapter
, LED_CTL_NO_LINK
);
1186 RT_TRACE(COMP_RF
, DBG_LOUD
, "%s(): Unknown RF type\n",
1193 priv
->SetRFPowerStateInProgress
= false;
1198 /******************************************************************************
1199 * function: This function sets command table variable (struct SwChnlCmd).
1200 * input: SwChnlCmd *CmdTable //table to be set
1201 * u32 CmdTableIdx //variable index in table to be set
1202 * u32 CmdTableSz //table size
1203 * SwChnlCmdID CmdID //command ID to set
1208 * return: true if finished, false otherwise
1210 ******************************************************************************/
1211 static u8
rtl8192_phy_SetSwChnlCmdArray(SwChnlCmd
*CmdTable
, u32 CmdTableIdx
,
1212 u32 CmdTableSz
, SwChnlCmdID CmdID
,
1213 u32 Para1
, u32 Para2
, u32 msDelay
)
1217 if (CmdTable
== NULL
) {
1218 RT_TRACE(COMP_ERR
, "%s(): CmdTable cannot be NULL\n", __func__
);
1221 if (CmdTableIdx
>= CmdTableSz
) {
1222 RT_TRACE(COMP_ERR
, "%s(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
1223 __func__
, CmdTableIdx
, CmdTableSz
);
1227 pCmd
= CmdTable
+ CmdTableIdx
;
1228 pCmd
->CmdID
= CmdID
;
1229 pCmd
->Para1
= Para1
;
1230 pCmd
->Para2
= Para2
;
1231 pCmd
->msDelay
= msDelay
;
1236 /******************************************************************************
1237 * function: This function sets channel step by step
1238 * input: net_device *dev
1240 * u8 *stage //3 stages
1242 * u32 *delay //whether need to delay
1243 * output: store new stage, step and delay for next step
1244 * (combine with function above)
1245 * return: true if finished, false otherwise
1246 * notice: Wait for simpler function to replace it
1247 *****************************************************************************/
1248 static u8
rtl8192_phy_SwChnlStepByStep(struct net_device
*dev
, u8 channel
,
1249 u8
*stage
, u8
*step
, u32
*delay
)
1251 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1252 SwChnlCmd PreCommonCmd
[MAX_PRECMD_CNT
];
1253 u32 PreCommonCmdCnt
;
1254 SwChnlCmd PostCommonCmd
[MAX_POSTCMD_CNT
];
1255 u32 PostCommonCmdCnt
;
1256 SwChnlCmd RfDependCmd
[MAX_RFDEPENDCMD_CNT
];
1258 SwChnlCmd
*CurrentCmd
= NULL
;
1261 RT_TRACE(COMP_CH
, "%s() stage: %d, step: %d, channel: %d\n",
1262 __func__
, *stage
, *step
, channel
);
1263 if (!IsLegalChannel(priv
->ieee80211
, channel
)) {
1264 RT_TRACE(COMP_ERR
, "set to illegal channel: %d\n", channel
);
1265 /* return true to tell upper caller function this channel
1266 setting is finished! Or it will in while loop. */
1269 /* FIXME: need to check whether channel is legal or not here */
1272 /* <1> Fill up pre common command. */
1273 PreCommonCmdCnt
= 0;
1274 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd
, PreCommonCmdCnt
++,
1275 MAX_PRECMD_CNT
, CmdID_SetTxPowerLevel
,
1277 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd
, PreCommonCmdCnt
++,
1278 MAX_PRECMD_CNT
, CmdID_End
, 0, 0, 0);
1280 /* <2> Fill up post common command. */
1281 PostCommonCmdCnt
= 0;
1283 rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd
, PostCommonCmdCnt
++,
1284 MAX_POSTCMD_CNT
, CmdID_End
, 0, 0, 0);
1286 /* <3> Fill up RF dependent command. */
1288 switch (priv
->rf_chip
) {
1290 if (!(channel
>= 1 && channel
<= 14)) {
1292 "illegal channel for Zebra 8225: %d\n",
1296 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd
, RfDependCmdCnt
++,
1297 MAX_RFDEPENDCMD_CNT
,
1300 RF_CHANNEL_TABLE_ZEBRA
[channel
],
1302 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd
, RfDependCmdCnt
++,
1303 MAX_RFDEPENDCMD_CNT
,
1304 CmdID_End
, 0, 0, 0);
1308 /* TEST!! This is not the table for 8256!! */
1309 if (!(channel
>= 1 && channel
<= 14)) {
1311 "illegal channel for Zebra 8256: %d\n",
1315 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd
, RfDependCmdCnt
++,
1316 MAX_RFDEPENDCMD_CNT
,
1318 rZebra1_Channel
, channel
, 10);
1319 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd
, RfDependCmdCnt
++,
1320 MAX_RFDEPENDCMD_CNT
,
1321 CmdID_End
, 0, 0, 0);
1328 RT_TRACE(COMP_ERR
, "Unknown RFChipID: %d\n", priv
->rf_chip
);
1336 CurrentCmd
= &PreCommonCmd
[*step
];
1339 CurrentCmd
= &RfDependCmd
[*step
];
1342 CurrentCmd
= &PostCommonCmd
[*step
];
1346 if (CurrentCmd
->CmdID
== CmdID_End
) {
1347 if ((*stage
) == 2) {
1348 (*delay
) = CurrentCmd
->msDelay
;
1356 switch (CurrentCmd
->CmdID
) {
1357 case CmdID_SetTxPowerLevel
:
1358 if (priv
->card_8192_version
== (u8
)VERSION_819xU_A
)
1359 /* consider it later! */
1360 rtl8192_SetTxPowerLevel(dev
, channel
);
1362 case CmdID_WritePortUlong
:
1363 write_nic_dword(dev
, CurrentCmd
->Para1
,
1366 case CmdID_WritePortUshort
:
1367 write_nic_word(dev
, CurrentCmd
->Para1
,
1368 (u16
)CurrentCmd
->Para2
);
1370 case CmdID_WritePortUchar
:
1371 write_nic_byte(dev
, CurrentCmd
->Para1
,
1372 (u8
)CurrentCmd
->Para2
);
1374 case CmdID_RF_WriteReg
:
1375 for (eRFPath
= 0; eRFPath
< RF90_PATH_MAX
; eRFPath
++) {
1376 rtl8192_phy_SetRFReg(dev
,
1377 (RF90_RADIO_PATH_E
)eRFPath
,
1390 (*delay
) = CurrentCmd
->msDelay
;
1395 /******************************************************************************
1396 * function: This function does actually set channel work
1397 * input: net_device *dev
1401 * notice: We should not call this function directly
1402 *****************************************************************************/
1403 static void rtl8192_phy_FinishSwChnlNow(struct net_device
*dev
, u8 channel
)
1405 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1408 while (!rtl8192_phy_SwChnlStepByStep(dev
, channel
, &priv
->SwChnlStage
,
1409 &priv
->SwChnlStep
, &delay
)) {
1415 /******************************************************************************
1416 * function: Callback routine of the work item for switch channel.
1417 * input: net_device *dev
1421 *****************************************************************************/
1422 void rtl8192_SwChnl_WorkItem(struct net_device
*dev
)
1425 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1427 RT_TRACE(COMP_CH
, "==> SwChnlCallback819xUsbWorkItem(), chan:%d\n",
1431 rtl8192_phy_FinishSwChnlNow(dev
, priv
->chan
);
1433 RT_TRACE(COMP_CH
, "<== SwChnlCallback819xUsbWorkItem()\n");
1436 /******************************************************************************
1437 * function: This function scheduled actual work item to set channel
1438 * input: net_device *dev
1439 * u8 channel //channel to set
1441 * return: return code show if workitem is scheduled (1:pass, 0:fail)
1442 * notice: Delay may be required for RF configuration
1443 ******************************************************************************/
1444 u8
rtl8192_phy_SwChnl(struct net_device
*dev
, u8 channel
)
1446 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1448 RT_TRACE(COMP_CH
, "%s(), SwChnlInProgress: %d\n", __func__
,
1449 priv
->SwChnlInProgress
);
1452 if (priv
->SwChnlInProgress
)
1455 /* -------------------------------------------- */
1456 switch (priv
->ieee80211
->mode
) {
1457 case WIRELESS_MODE_A
:
1458 case WIRELESS_MODE_N_5G
:
1459 if (channel
<= 14) {
1460 RT_TRACE(COMP_ERR
, "WIRELESS_MODE_A but channel<=14\n");
1464 case WIRELESS_MODE_B
:
1466 RT_TRACE(COMP_ERR
, "WIRELESS_MODE_B but channel>14\n");
1470 case WIRELESS_MODE_G
:
1471 case WIRELESS_MODE_N_24G
:
1473 RT_TRACE(COMP_ERR
, "WIRELESS_MODE_G but channel>14\n");
1478 /* -------------------------------------------- */
1480 priv
->SwChnlInProgress
= true;
1484 priv
->chan
= channel
;
1486 priv
->SwChnlStage
= 0;
1487 priv
->SwChnlStep
= 0;
1489 rtl8192_SwChnl_WorkItem(dev
);
1491 priv
->SwChnlInProgress
= false;
1495 /******************************************************************************
1496 * function: Callback routine of the work item for set bandwidth mode.
1497 * input: net_device *dev
1500 * notice: I doubt whether SetBWModeInProgress flag is necessary as we can
1501 * test whether current work in the queue or not.//do I?
1502 *****************************************************************************/
1503 void rtl8192_SetBWModeWorkItem(struct net_device
*dev
)
1506 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1509 RT_TRACE(COMP_SWBW
, "%s() Switch to %s bandwidth\n", __func__
,
1510 priv
->CurrentChannelBW
== HT_CHANNEL_WIDTH_20
?"20MHz":"40MHz");
1513 if (priv
->rf_chip
== RF_PSEUDO_11N
) {
1514 priv
->SetBWModeInProgress
= false;
1518 /* <1> Set MAC register */
1519 read_nic_byte(dev
, BW_OPMODE
, ®BwOpMode
);
1521 switch (priv
->CurrentChannelBW
) {
1522 case HT_CHANNEL_WIDTH_20
:
1523 regBwOpMode
|= BW_OPMODE_20MHZ
;
1524 /* We have not verify whether this register works */
1525 write_nic_byte(dev
, BW_OPMODE
, regBwOpMode
);
1528 case HT_CHANNEL_WIDTH_20_40
:
1529 regBwOpMode
&= ~BW_OPMODE_20MHZ
;
1530 /* We have not verify whether this register works */
1531 write_nic_byte(dev
, BW_OPMODE
, regBwOpMode
);
1536 "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",
1537 priv
->CurrentChannelBW
);
1541 /* <2> Set PHY related register */
1542 switch (priv
->CurrentChannelBW
) {
1543 case HT_CHANNEL_WIDTH_20
:
1544 rtl8192_setBBreg(dev
, rFPGA0_RFMOD
, bRFMOD
, 0x0);
1545 rtl8192_setBBreg(dev
, rFPGA1_RFMOD
, bRFMOD
, 0x0);
1546 rtl8192_setBBreg(dev
, rFPGA0_AnalogParameter1
,
1549 /* Correct the tx power for CCK rate in 20M. */
1550 priv
->cck_present_attentuation
=
1551 priv
->cck_present_attentuation_20Mdefault
+
1552 priv
->cck_present_attentuation_difference
;
1554 if (priv
->cck_present_attentuation
> 22)
1555 priv
->cck_present_attentuation
= 22;
1556 if (priv
->cck_present_attentuation
< 0)
1557 priv
->cck_present_attentuation
= 0;
1559 "20M, pHalData->CCKPresentAttentuation = %d\n",
1560 priv
->cck_present_attentuation
);
1562 if (priv
->chan
== 14 && !priv
->bcck_in_ch14
) {
1563 priv
->bcck_in_ch14
= true;
1564 dm_cck_txpower_adjust(dev
, priv
->bcck_in_ch14
);
1565 } else if (priv
->chan
!= 14 && priv
->bcck_in_ch14
) {
1566 priv
->bcck_in_ch14
= false;
1567 dm_cck_txpower_adjust(dev
, priv
->bcck_in_ch14
);
1569 dm_cck_txpower_adjust(dev
, priv
->bcck_in_ch14
);
1573 case HT_CHANNEL_WIDTH_20_40
:
1574 rtl8192_setBBreg(dev
, rFPGA0_RFMOD
, bRFMOD
, 0x1);
1575 rtl8192_setBBreg(dev
, rFPGA1_RFMOD
, bRFMOD
, 0x1);
1576 rtl8192_setBBreg(dev
, rCCK0_System
, bCCKSideBand
,
1577 priv
->nCur40MhzPrimeSC
>>1);
1578 rtl8192_setBBreg(dev
, rFPGA0_AnalogParameter1
, 0x00100000, 0);
1579 rtl8192_setBBreg(dev
, rOFDM1_LSTF
, 0xC00,
1580 priv
->nCur40MhzPrimeSC
);
1581 priv
->cck_present_attentuation
=
1582 priv
->cck_present_attentuation_40Mdefault
+
1583 priv
->cck_present_attentuation_difference
;
1585 if (priv
->cck_present_attentuation
> 22)
1586 priv
->cck_present_attentuation
= 22;
1587 if (priv
->cck_present_attentuation
< 0)
1588 priv
->cck_present_attentuation
= 0;
1591 "40M, pHalData->CCKPresentAttentuation = %d\n",
1592 priv
->cck_present_attentuation
);
1593 if (priv
->chan
== 14 && !priv
->bcck_in_ch14
) {
1594 priv
->bcck_in_ch14
= true;
1595 dm_cck_txpower_adjust(dev
, priv
->bcck_in_ch14
);
1596 } else if (priv
->chan
!= 14 && priv
->bcck_in_ch14
) {
1597 priv
->bcck_in_ch14
= false;
1598 dm_cck_txpower_adjust(dev
, priv
->bcck_in_ch14
);
1600 dm_cck_txpower_adjust(dev
, priv
->bcck_in_ch14
);
1606 "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",
1607 priv
->CurrentChannelBW
);
1611 /* Skip over setting of J-mode in BB register here.
1612 Default value is "None J mode". */
1614 /* <3> Set RF related register */
1615 switch (priv
->rf_chip
) {
1618 PHY_SetRF8225Bandwidth(Adapter
, pHalData
->CurrentChannelBW
);
1623 PHY_SetRF8256Bandwidth(dev
, priv
->CurrentChannelBW
);
1633 RT_TRACE(COMP_ERR
, "Unknown RFChipID: %d\n", priv
->rf_chip
);
1636 priv
->SetBWModeInProgress
= false;
1638 RT_TRACE(COMP_SWBW
, "<==SetBWMode819xUsb(), %d\n",
1639 atomic_read(&priv
->ieee80211
->atm_swbw
));
1642 /******************************************************************************
1643 * function: This function schedules bandwidth switch work.
1644 * input: struct net_deviceq *dev
1645 * HT_CHANNEL_WIDTH bandwidth //20M or 40M
1646 * HT_EXTCHNL_OFFSET offset //Upper, Lower, or Don't care
1649 * notice: I doubt whether SetBWModeInProgress flag is necessary as we can
1650 * test whether current work in the queue or not.//do I?
1651 *****************************************************************************/
1652 void rtl8192_SetBWMode(struct net_device
*dev
, HT_CHANNEL_WIDTH bandwidth
,
1653 HT_EXTCHNL_OFFSET offset
)
1655 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1657 if (priv
->SetBWModeInProgress
)
1659 priv
->SetBWModeInProgress
= true;
1661 priv
->CurrentChannelBW
= bandwidth
;
1663 if (offset
== HT_EXTCHNL_OFFSET_LOWER
)
1664 priv
->nCur40MhzPrimeSC
= HAL_PRIME_CHNL_OFFSET_UPPER
;
1665 else if (offset
== HT_EXTCHNL_OFFSET_UPPER
)
1666 priv
->nCur40MhzPrimeSC
= HAL_PRIME_CHNL_OFFSET_LOWER
;
1668 priv
->nCur40MhzPrimeSC
= HAL_PRIME_CHNL_OFFSET_DONT_CARE
;
1670 rtl8192_SetBWModeWorkItem(dev
);
1674 void InitialGain819xUsb(struct net_device
*dev
, u8 Operation
)
1676 struct r8192_priv
*priv
= ieee80211_priv(dev
);
1678 priv
->InitialGainOperateType
= Operation
;
1681 queue_delayed_work(priv
->priv_wq
, &priv
->initialgain_operate_wq
, 0);
1684 void InitialGainOperateWorkItemCallBack(struct work_struct
*work
)
1686 struct delayed_work
*dwork
= container_of(work
, struct delayed_work
,
1688 struct r8192_priv
*priv
= container_of(dwork
, struct r8192_priv
,
1689 initialgain_operate_wq
);
1690 struct net_device
*dev
= priv
->ieee80211
->dev
;
1691 #define SCAN_RX_INITIAL_GAIN 0x17
1692 #define POWER_DETECTION_TH 0x08
1697 Operation
= priv
->InitialGainOperateType
;
1699 switch (Operation
) {
1701 RT_TRACE(COMP_SCAN
, "IG_Backup, backup the initial gain.\n");
1702 initial_gain
= SCAN_RX_INITIAL_GAIN
;
1703 bitmask
= bMaskByte0
;
1704 if (dm_digtable
.dig_algorithm
== DIG_ALGO_BY_FALSE_ALARM
)
1706 rtl8192_setBBreg(dev
, UFWP
, bMaskByte1
, 0x8);
1707 priv
->initgain_backup
.xaagccore1
=
1708 (u8
)rtl8192_QueryBBReg(dev
, rOFDM0_XAAGCCore1
, bitmask
);
1709 priv
->initgain_backup
.xbagccore1
=
1710 (u8
)rtl8192_QueryBBReg(dev
, rOFDM0_XBAGCCore1
, bitmask
);
1711 priv
->initgain_backup
.xcagccore1
=
1712 (u8
)rtl8192_QueryBBReg(dev
, rOFDM0_XCAGCCore1
, bitmask
);
1713 priv
->initgain_backup
.xdagccore1
=
1714 (u8
)rtl8192_QueryBBReg(dev
, rOFDM0_XDAGCCore1
, bitmask
);
1715 bitmask
= bMaskByte2
;
1716 priv
->initgain_backup
.cca
=
1717 (u8
)rtl8192_QueryBBReg(dev
, rCCK0_CCA
, bitmask
);
1719 RT_TRACE(COMP_SCAN
, "Scan InitialGainBackup 0xc50 is %x\n",
1720 priv
->initgain_backup
.xaagccore1
);
1721 RT_TRACE(COMP_SCAN
, "Scan InitialGainBackup 0xc58 is %x\n",
1722 priv
->initgain_backup
.xbagccore1
);
1723 RT_TRACE(COMP_SCAN
, "Scan InitialGainBackup 0xc60 is %x\n",
1724 priv
->initgain_backup
.xcagccore1
);
1725 RT_TRACE(COMP_SCAN
, "Scan InitialGainBackup 0xc68 is %x\n",
1726 priv
->initgain_backup
.xdagccore1
);
1727 RT_TRACE(COMP_SCAN
, "Scan InitialGainBackup 0xa0a is %x\n",
1728 priv
->initgain_backup
.cca
);
1730 RT_TRACE(COMP_SCAN
, "Write scan initial gain = 0x%x\n",
1732 write_nic_byte(dev
, rOFDM0_XAAGCCore1
, initial_gain
);
1733 write_nic_byte(dev
, rOFDM0_XBAGCCore1
, initial_gain
);
1734 write_nic_byte(dev
, rOFDM0_XCAGCCore1
, initial_gain
);
1735 write_nic_byte(dev
, rOFDM0_XDAGCCore1
, initial_gain
);
1736 RT_TRACE(COMP_SCAN
, "Write scan 0xa0a = 0x%x\n",
1737 POWER_DETECTION_TH
);
1738 write_nic_byte(dev
, 0xa0a, POWER_DETECTION_TH
);
1741 RT_TRACE(COMP_SCAN
, "IG_Restore, restore the initial gain.\n");
1742 bitmask
= 0x7f; /* Bit0 ~ Bit6 */
1743 if (dm_digtable
.dig_algorithm
== DIG_ALGO_BY_FALSE_ALARM
)
1745 rtl8192_setBBreg(dev
, UFWP
, bMaskByte1
, 0x8);
1747 rtl8192_setBBreg(dev
, rOFDM0_XAAGCCore1
, bitmask
,
1748 (u32
)priv
->initgain_backup
.xaagccore1
);
1749 rtl8192_setBBreg(dev
, rOFDM0_XBAGCCore1
, bitmask
,
1750 (u32
)priv
->initgain_backup
.xbagccore1
);
1751 rtl8192_setBBreg(dev
, rOFDM0_XCAGCCore1
, bitmask
,
1752 (u32
)priv
->initgain_backup
.xcagccore1
);
1753 rtl8192_setBBreg(dev
, rOFDM0_XDAGCCore1
, bitmask
,
1754 (u32
)priv
->initgain_backup
.xdagccore1
);
1755 bitmask
= bMaskByte2
;
1756 rtl8192_setBBreg(dev
, rCCK0_CCA
, bitmask
,
1757 (u32
)priv
->initgain_backup
.cca
);
1759 RT_TRACE(COMP_SCAN
, "Scan BBInitialGainRestore 0xc50 is %x\n",
1760 priv
->initgain_backup
.xaagccore1
);
1761 RT_TRACE(COMP_SCAN
, "Scan BBInitialGainRestore 0xc58 is %x\n",
1762 priv
->initgain_backup
.xbagccore1
);
1763 RT_TRACE(COMP_SCAN
, "Scan BBInitialGainRestore 0xc60 is %x\n",
1764 priv
->initgain_backup
.xcagccore1
);
1765 RT_TRACE(COMP_SCAN
, "Scan BBInitialGainRestore 0xc68 is %x\n",
1766 priv
->initgain_backup
.xdagccore1
);
1767 RT_TRACE(COMP_SCAN
, "Scan BBInitialGainRestore 0xa0a is %x\n",
1768 priv
->initgain_backup
.cca
);
1770 rtl8192_phy_setTxPower(dev
, priv
->ieee80211
->current_network
.channel
);
1772 if (dm_digtable
.dig_algorithm
== DIG_ALGO_BY_FALSE_ALARM
)
1774 rtl8192_setBBreg(dev
, UFWP
, bMaskByte1
, 0x1);
1777 RT_TRACE(COMP_SCAN
, "Unknown IG Operation.\n");