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staging: rtl8723au: Remove another pile of useless ODM variables
[deliverable/linux.git] / drivers / staging / rtl8723au / hal / odm.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 ******************************************************************************/
15
16 #include "odm_precomp.h"
17 #include "usb_ops_linux.h"
18
19 static const u16 dB_Invert_Table[8][12] = {
20 {1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 4, 4},
21 {4, 5, 6, 6, 7, 8, 9, 10, 11, 13, 14, 16},
22 {18, 20, 22, 25, 28, 32, 35, 40, 45, 50, 56, 63},
23 {71, 79, 89, 100, 112, 126, 141, 158, 178, 200, 224, 251},
24 {282, 316, 355, 398, 447, 501, 562, 631, 708, 794, 891, 1000},
25 {1122, 1259, 1413, 1585, 1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981},
26 {4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000, 11220, 12589, 14125, 15849},
27 {17783, 19953, 22387, 25119, 28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535}
28 };
29
30 static u32 EDCAParam[HT_IOT_PEER_MAX][3] = { /* UL DL */
31 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 0:unknown AP */
32 {0xa44f, 0x5ea44f, 0x5e431c}, /* 1:realtek AP */
33 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 2:unknown AP => realtek_92SE */
34 {0x5ea32b, 0x5ea42b, 0x5e4322}, /* 3:broadcom AP */
35 {0x5ea422, 0x00a44f, 0x00a44f}, /* 4:ralink AP */
36 {0x5ea322, 0x00a630, 0x00a44f}, /* 5:atheros AP */
37 {0x5e4322, 0x5e4322, 0x5e4322},/* 6:cisco AP */
38 {0x5ea44f, 0x00a44f, 0x5ea42b}, /* 8:marvell AP */
39 {0x5ea42b, 0x5ea42b, 0x5ea42b}, /* 10:unknown AP => 92U AP */
40 {0x5ea42b, 0xa630, 0x5e431c}, /* 11:airgocap AP */
41 };
42
43 /* EDCA Paramter for AP/ADSL by Mingzhi 2011-11-22 */
44
45 /* Global var */
46 u32 OFDMSwingTable23A[OFDM_TABLE_SIZE_92D] = {
47 0x7f8001fe, /* 0, +6.0dB */
48 0x788001e2, /* 1, +5.5dB */
49 0x71c001c7, /* 2, +5.0dB */
50 0x6b8001ae, /* 3, +4.5dB */
51 0x65400195, /* 4, +4.0dB */
52 0x5fc0017f, /* 5, +3.5dB */
53 0x5a400169, /* 6, +3.0dB */
54 0x55400155, /* 7, +2.5dB */
55 0x50800142, /* 8, +2.0dB */
56 0x4c000130, /* 9, +1.5dB */
57 0x47c0011f, /* 10, +1.0dB */
58 0x43c0010f, /* 11, +0.5dB */
59 0x40000100, /* 12, +0dB */
60 0x3c8000f2, /* 13, -0.5dB */
61 0x390000e4, /* 14, -1.0dB */
62 0x35c000d7, /* 15, -1.5dB */
63 0x32c000cb, /* 16, -2.0dB */
64 0x300000c0, /* 17, -2.5dB */
65 0x2d4000b5, /* 18, -3.0dB */
66 0x2ac000ab, /* 19, -3.5dB */
67 0x288000a2, /* 20, -4.0dB */
68 0x26000098, /* 21, -4.5dB */
69 0x24000090, /* 22, -5.0dB */
70 0x22000088, /* 23, -5.5dB */
71 0x20000080, /* 24, -6.0dB */
72 0x1e400079, /* 25, -6.5dB */
73 0x1c800072, /* 26, -7.0dB */
74 0x1b00006c, /* 27. -7.5dB */
75 0x19800066, /* 28, -8.0dB */
76 0x18000060, /* 29, -8.5dB */
77 0x16c0005b, /* 30, -9.0dB */
78 0x15800056, /* 31, -9.5dB */
79 0x14400051, /* 32, -10.0dB */
80 0x1300004c, /* 33, -10.5dB */
81 0x12000048, /* 34, -11.0dB */
82 0x11000044, /* 35, -11.5dB */
83 0x10000040, /* 36, -12.0dB */
84 0x0f00003c,/* 37, -12.5dB */
85 0x0e400039,/* 38, -13.0dB */
86 0x0d800036,/* 39, -13.5dB */
87 0x0cc00033,/* 40, -14.0dB */
88 0x0c000030,/* 41, -14.5dB */
89 0x0b40002d,/* 42, -15.0dB */
90 };
91
92 u8 CCKSwingTable_Ch1_Ch1323A[CCK_TABLE_SIZE][8] = {
93 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, /* 0, +0dB */
94 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, /* 1, -0.5dB */
95 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, /* 2, -1.0dB */
96 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, /* 3, -1.5dB */
97 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, /* 4, -2.0dB */
98 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, /* 5, -2.5dB */
99 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, /* 6, -3.0dB */
100 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, /* 7, -3.5dB */
101 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, /* 8, -4.0dB */
102 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, /* 9, -4.5dB */
103 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, /* 10, -5.0dB */
104 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, /* 11, -5.5dB */
105 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, /* 12, -6.0dB */
106 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, /* 13, -6.5dB */
107 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, /* 14, -7.0dB */
108 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, /* 15, -7.5dB */
109 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, /* 16, -8.0dB */
110 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, /* 17, -8.5dB */
111 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, /* 18, -9.0dB */
112 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 19, -9.5dB */
113 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, /* 20, -10.0dB */
114 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 21, -10.5dB */
115 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, /* 22, -11.0dB */
116 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, /* 23, -11.5dB */
117 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, /* 24, -12.0dB */
118 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, /* 25, -12.5dB */
119 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, /* 26, -13.0dB */
120 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 27, -13.5dB */
121 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, /* 28, -14.0dB */
122 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 29, -14.5dB */
123 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, /* 30, -15.0dB */
124 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, /* 31, -15.5dB */
125 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} /* 32, -16.0dB */
126 };
127
128 u8 CCKSwingTable_Ch1423A[CCK_TABLE_SIZE][8] = {
129 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, /* 0, +0dB */
130 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, /* 1, -0.5dB */
131 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, /* 2, -1.0dB */
132 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, /* 3, -1.5dB */
133 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, /* 4, -2.0dB */
134 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, /* 5, -2.5dB */
135 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, /* 6, -3.0dB */
136 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, /* 7, -3.5dB */
137 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, /* 8, -4.0dB */
138 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, /* 9, -4.5dB */
139 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, /* 10, -5.0dB */
140 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 11, -5.5dB */
141 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, /* 12, -6.0dB */
142 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, /* 13, -6.5dB */
143 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, /* 14, -7.0dB */
144 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 15, -7.5dB */
145 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, /* 16, -8.0dB */
146 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 17, -8.5dB */
147 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, /* 18, -9.0dB */
148 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 19, -9.5dB */
149 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, /* 20, -10.0dB */
150 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 21, -10.5dB */
151 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, /* 22, -11.0dB */
152 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 23, -11.5dB */
153 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, /* 24, -12.0dB */
154 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 25, -12.5dB */
155 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 26, -13.0dB */
156 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, /* 27, -13.5dB */
157 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 28, -14.0dB */
158 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 29, -14.5dB */
159 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 30, -15.0dB */
160 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, /* 31, -15.5dB */
161 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} /* 32, -16.0dB */
162 };
163
164 /* Local Function predefine. */
165
166 /* START------------COMMON INFO RELATED--------------- */
167 void odm_CommonInfoSelfInit23a(struct dm_odm_t *pDM_Odm);
168
169 void odm_CommonInfoSelfUpdate23a(struct dm_odm_t *pDM_Odm);
170
171 void odm_CmnInfoInit_Debug23a(struct dm_odm_t *pDM_Odm);
172
173 void odm_CmnInfoHook_Debug23a(struct dm_odm_t *pDM_Odm);
174
175 void odm_CmnInfoUpdate_Debug23a(struct dm_odm_t *pDM_Odm);
176
177 /* START---------------DIG--------------------------- */
178 void odm_FalseAlarmCounterStatistics23a(struct dm_odm_t *pDM_Odm);
179
180 void odm_DIG23aInit(struct dm_odm_t *pDM_Odm);
181
182 void odm_DIG23a(struct dm_odm_t *pDM_Odm);
183
184 void odm_CCKPacketDetectionThresh23a(struct dm_odm_t *pDM_Odm);
185 /* END---------------DIG--------------------------- */
186
187 /* START-------BB POWER SAVE----------------------- */
188 void odm23a_DynBBPSInit(struct dm_odm_t *pDM_Odm);
189
190 void odm_DynamicBBPowerSaving23a(struct dm_odm_t *pDM_Odm);
191
192 void odm_1R_CCA23a(struct dm_odm_t *pDM_Odm);
193 /* END---------BB POWER SAVE----------------------- */
194
195 void odm_RefreshRateAdaptiveMask23aMP23a(struct dm_odm_t *pDM_Odm);
196
197 void odm_RefreshRateAdaptiveMask23aCE23a(struct dm_odm_t *pDM_Odm);
198
199 void odm_RefreshRateAdaptiveMask23aAPADSL23a(struct dm_odm_t *pDM_Odm);
200
201 void odm_DynamicTxPower23aInit(struct dm_odm_t *pDM_Odm);
202
203 void odm_RSSIMonitorInit(struct dm_odm_t *pDM_Odm);
204
205 void odm_RSSIMonitorCheck23aMP(struct dm_odm_t *pDM_Odm);
206
207 void odm_RSSIMonitorCheck23aCE(struct dm_odm_t *pDM_Odm);
208 void odm_RSSIMonitorCheck23aAP(struct dm_odm_t *pDM_Odm);
209
210 void odm_RSSIMonitorCheck23a(struct dm_odm_t *pDM_Odm);
211 void odm_DynamicTxPower23a(struct dm_odm_t *pDM_Odm);
212
213 void odm_SwAntDivInit(struct dm_odm_t *pDM_Odm);
214
215 void odm_SwAntDivInit_NIC(struct dm_odm_t *pDM_Odm);
216
217 void odm_SwAntDivChkAntSwitch(struct dm_odm_t *pDM_Odm, u8 Step);
218
219 void odm_SwAntDivChkAntSwitchNIC(struct dm_odm_t *pDM_Odm,
220 u8 Step
221 );
222
223 void odm_SwAntDivChkAntSwitchCallback23a(unsigned long data);
224
225 void odm_RefreshRateAdaptiveMask23a(struct dm_odm_t *pDM_Odm);
226
227 void ODM_TXPowerTrackingCheck23a(struct dm_odm_t *pDM_Odm);
228
229 void odm_TXPowerTrackingCheckAP(struct dm_odm_t *pDM_Odm);
230
231 void odm_RateAdaptiveMaskInit23a(struct dm_odm_t *pDM_Odm);
232
233 void odm_TXPowerTrackingThermalMeterInit23a(struct dm_odm_t *pDM_Odm);
234
235 void odm_TXPowerTrackingInit23a(struct dm_odm_t *pDM_Odm);
236
237 void odm_TXPowerTrackingCheckMP(struct dm_odm_t *pDM_Odm);
238
239 void odm_TXPowerTrackingCheckCE23a(struct dm_odm_t *pDM_Odm);
240
241 static void odm_EdcaTurboCheck23a(struct dm_odm_t *pDM_Odm);
242 static void ODM_EdcaTurboInit23a(struct dm_odm_t *pDM_Odm);
243
244 #define RxDefaultAnt1 0x65a9
245 #define RxDefaultAnt2 0x569a
246
247 void odm_InitHybridAntDiv23a(struct dm_odm_t *pDM_Odm);
248
249 bool odm_StaDefAntSel(struct dm_odm_t *pDM_Odm,
250 u32 OFDM_Ant1_Cnt,
251 u32 OFDM_Ant2_Cnt,
252 u32 CCK_Ant1_Cnt,
253 u32 CCK_Ant2_Cnt,
254 u8 *pDefAnt
255 );
256
257 void odm_SetRxIdleAnt(struct dm_odm_t *pDM_Odm,
258 u8 Ant,
259 bool bDualPath
260 );
261
262 void odm_HwAntDiv23a(struct dm_odm_t *pDM_Odm);
263
264 /* 3 Export Interface */
265
266 /* 2011/09/21 MH Add to describe different team necessary resource allocate?? */
267 void ODM23a_DMInit(struct dm_odm_t *pDM_Odm)
268 {
269 /* For all IC series */
270 odm_CommonInfoSelfInit23a(pDM_Odm);
271 odm_CmnInfoInit_Debug23a(pDM_Odm);
272 odm_DIG23aInit(pDM_Odm);
273 odm_RateAdaptiveMaskInit23a(pDM_Odm);
274
275 odm23a_DynBBPSInit(pDM_Odm);
276 odm_DynamicTxPower23aInit(pDM_Odm);
277 odm_TXPowerTrackingInit23a(pDM_Odm);
278 ODM_EdcaTurboInit23a(pDM_Odm);
279 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) ||
280 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) ||
281 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV))
282 odm_InitHybridAntDiv23a(pDM_Odm);
283 else if (pDM_Odm->AntDivType == CGCS_RX_SW_ANTDIV)
284 odm_SwAntDivInit(pDM_Odm);
285 }
286
287 /* 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM. */
288 /* You can not add any dummy function here, be care, you can only use DM structure */
289 /* to perform any new ODM_DM. */
290 void ODM_DMWatchdog23a(struct dm_odm_t *pDM_Odm)
291 {
292 /* 2012.05.03 Luke: For all IC series */
293 odm_CmnInfoHook_Debug23a(pDM_Odm);
294 odm_CmnInfoUpdate_Debug23a(pDM_Odm);
295 odm_CommonInfoSelfUpdate23a(pDM_Odm);
296 odm_FalseAlarmCounterStatistics23a(pDM_Odm);
297 odm_RSSIMonitorCheck23a(pDM_Odm);
298
299 /* 8723A or 8189ES platform */
300 /* NeilChen--2012--08--24-- */
301 /* Fix Leave LPS issue */
302 if ((pDM_Odm->Adapter->pwrctrlpriv.pwr_mode != PS_MODE_ACTIVE) &&/* in LPS mode */
303 (pDM_Odm->SupportICType & ODM_RTL8723A)) {
304 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("----Step1: odm_DIG23a is in LPS mode\n"));
305 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("---Step2: 8723AS is in LPS mode\n"));
306 odm_DIG23abyRSSI_LPS(pDM_Odm);
307 } else {
308 odm_DIG23a(pDM_Odm);
309 }
310
311 odm_CCKPacketDetectionThresh23a(pDM_Odm);
312
313 if (*(pDM_Odm->pbPowerSaving))
314 return;
315
316 odm_RefreshRateAdaptiveMask23a(pDM_Odm);
317
318 odm_DynamicBBPowerSaving23a(pDM_Odm);
319 if ((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV) ||
320 (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) ||
321 (pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV))
322 odm_HwAntDiv23a(pDM_Odm);
323 else if (pDM_Odm->AntDivType == CGCS_RX_SW_ANTDIV)
324 odm_SwAntDivChkAntSwitch(pDM_Odm, SWAW_STEP_PEAK);
325
326 ODM_TXPowerTrackingCheck23a(pDM_Odm);
327 odm_EdcaTurboCheck23a(pDM_Odm);
328
329 odm_dtc(pDM_Odm);
330 }
331
332 /* */
333 /* Init /.. Fixed HW value. Only init time. */
334 /* */
335 void ODM_CmnInfoInit23a(struct dm_odm_t *pDM_Odm,
336 enum odm_cmninfo CmnInfo,
337 u32 Value
338 )
339 {
340 /* ODM_RT_TRACE(pDM_Odm,); */
341
342 /* */
343 /* This section is used for init value */
344 /* */
345 switch (CmnInfo) {
346 /* Fixed ODM value. */
347 case ODM_CMNINFO_ABILITY:
348 pDM_Odm->SupportAbility = (u32)Value;
349 break;
350 case ODM_CMNINFO_PLATFORM:
351 break;
352 case ODM_CMNINFO_INTERFACE:
353 pDM_Odm->SupportInterface = (u8)Value;
354 break;
355 case ODM_CMNINFO_MP_TEST_CHIP:
356 pDM_Odm->bIsMPChip = (u8)Value;
357 break;
358 case ODM_CMNINFO_IC_TYPE:
359 pDM_Odm->SupportICType = Value;
360 break;
361 case ODM_CMNINFO_CUT_VER:
362 pDM_Odm->CutVersion = (u8)Value;
363 break;
364 case ODM_CMNINFO_FAB_VER:
365 pDM_Odm->FabVersion = (u8)Value;
366 break;
367 case ODM_CMNINFO_RF_TYPE:
368 pDM_Odm->RFType = (u8)Value;
369 break;
370 case ODM_CMNINFO_RF_ANTENNA_TYPE:
371 pDM_Odm->AntDivType = (u8)Value;
372 break;
373 case ODM_CMNINFO_BOARD_TYPE:
374 pDM_Odm->BoardType = (u8)Value;
375 break;
376 case ODM_CMNINFO_EXT_LNA:
377 pDM_Odm->ExtLNA = (u8)Value;
378 break;
379 case ODM_CMNINFO_EXT_PA:
380 pDM_Odm->ExtPA = (u8)Value;
381 break;
382 case ODM_CMNINFO_EXT_TRSW:
383 pDM_Odm->ExtTRSW = (u8)Value;
384 break;
385 case ODM_CMNINFO_PATCH_ID:
386 pDM_Odm->PatchID = (u8)Value;
387 break;
388 case ODM_CMNINFO_BINHCT_TEST:
389 pDM_Odm->bInHctTest = (bool)Value;
390 break;
391 case ODM_CMNINFO_BWIFI_TEST:
392 pDM_Odm->bWIFITest = (bool)Value;
393 break;
394 case ODM_CMNINFO_SMART_CONCURRENT:
395 pDM_Odm->bDualMacSmartConcurrent = (bool)Value;
396 break;
397 /* To remove the compiler warning, must add an empty default statement to handle the other values. */
398 default:
399 /* do nothing */
400 break;
401 }
402
403 /* */
404 /* Tx power tracking BB swing table. */
405 /* The base index = 12. +((12-n)/2)dB 13~?? = decrease tx pwr by -((n-12)/2)dB */
406 /* */
407 pDM_Odm->BbSwingIdxOfdm = 12; /* Set defalut value as index 12. */
408 pDM_Odm->BbSwingIdxOfdmCurrent = 12;
409 pDM_Odm->BbSwingFlagOfdm = false;
410
411 }
412
413 void ODM23a_CmnInfoHook(struct dm_odm_t *pDM_Odm,
414 enum odm_cmninfo CmnInfo,
415 void *pValue
416 )
417 {
418 /* Hook call by reference pointer. */
419 switch (CmnInfo) {
420 /* Dynamic call by reference pointer. */
421 case ODM_CMNINFO_SEC_CHNL_OFFSET:
422 pDM_Odm->pSecChOffset = (u8 *)pValue;
423 break;
424 case ODM_CMNINFO_BW:
425 pDM_Odm->pBandWidth = (u8 *)pValue;
426 break;
427 case ODM_CMNINFO_CHNL:
428 pDM_Odm->pChannel = (u8 *)pValue;
429 break;
430 case ODM_CMNINFO_SCAN:
431 pDM_Odm->pbScanInProcess = (bool *)pValue;
432 break;
433 case ODM_CMNINFO_POWER_SAVING:
434 pDM_Odm->pbPowerSaving = (bool *)pValue;
435 break;
436 case ODM_CMNINFO_ONE_PATH_CCA:
437 pDM_Odm->pOnePathCCA = (u8 *)pValue;
438 break;
439 case ODM_CMNINFO_DRV_STOP:
440 pDM_Odm->pbDriverStopped = (bool *)pValue;
441 break;
442 case ODM_CMNINFO_PNP_IN:
443 pDM_Odm->pbDriverIsGoingToPnpSetPowerSleep = (bool *)pValue;
444 break;
445 case ODM_CMNINFO_INIT_ON:
446 pDM_Odm->pinit_adpt_in_progress = (bool *)pValue;
447 break;
448 case ODM_CMNINFO_ANT_TEST:
449 pDM_Odm->pAntennaTest = (u8 *)pValue;
450 break;
451 case ODM_CMNINFO_NET_CLOSED:
452 pDM_Odm->pbNet_closed = (bool *)pValue;
453 break;
454 /* To remove the compiler warning, must add an empty default statement to handle the other values. */
455 default:
456 /* do nothing */
457 break;
458 }
459 }
460
461 void ODM_CmnInfoPtrArrayHook23a(struct dm_odm_t *pDM_Odm, enum odm_cmninfo CmnInfo,
462 u16 Index, void *pValue)
463 {
464 /* Hook call by reference pointer. */
465 switch (CmnInfo) {
466 /* Dynamic call by reference pointer. */
467 case ODM_CMNINFO_STA_STATUS:
468 pDM_Odm->pODM_StaInfo[Index] = (struct sta_info *)pValue;
469 break;
470 /* To remove the compiler warning, must add an empty default statement to handle the other values. */
471 default:
472 /* do nothing */
473 break;
474 }
475 }
476
477 /* Update Band/CHannel/.. The values are dynamic but non-per-packet. */
478 void ODM_CmnInfoUpdate23a(struct dm_odm_t *pDM_Odm, u32 CmnInfo, u64 Value)
479 {
480 /* This init variable may be changed in run time. */
481 switch (CmnInfo) {
482 case ODM_CMNINFO_ABILITY:
483 pDM_Odm->SupportAbility = (u32)Value;
484 break;
485 case ODM_CMNINFO_RF_TYPE:
486 pDM_Odm->RFType = (u8)Value;
487 break;
488 case ODM_CMNINFO_WIFI_DIRECT:
489 pDM_Odm->bWIFI_Direct = (bool)Value;
490 break;
491 case ODM_CMNINFO_WIFI_DISPLAY:
492 pDM_Odm->bWIFI_Display = (bool)Value;
493 break;
494 case ODM_CMNINFO_LINK:
495 pDM_Odm->bLinked = (bool)Value;
496 break;
497 case ODM_CMNINFO_RSSI_MIN:
498 pDM_Odm->RSSI_Min = (u8)Value;
499 break;
500 case ODM_CMNINFO_DBG_COMP:
501 pDM_Odm->DebugComponents = Value;
502 break;
503 case ODM_CMNINFO_DBG_LEVEL:
504 pDM_Odm->DebugLevel = (u32)Value;
505 break;
506 case ODM_CMNINFO_RA_THRESHOLD_HIGH:
507 pDM_Odm->RateAdaptive.HighRSSIThresh = (u8)Value;
508 break;
509 case ODM_CMNINFO_RA_THRESHOLD_LOW:
510 pDM_Odm->RateAdaptive.LowRSSIThresh = (u8)Value;
511 break;
512 }
513
514 }
515
516 void odm_CommonInfoSelfInit23a(struct dm_odm_t *pDM_Odm
517 )
518 {
519 pDM_Odm->bCckHighPower = (bool) ODM_GetBBReg(pDM_Odm, 0x824, BIT(9));
520 pDM_Odm->RFPathRxEnable = (u8) ODM_GetBBReg(pDM_Odm, 0xc04, 0x0F);
521 if (pDM_Odm->SupportICType & ODM_RTL8723A)
522 pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;
523
524 ODM_InitDebugSetting23a(pDM_Odm);
525 }
526
527 void odm_CommonInfoSelfUpdate23a(struct dm_odm_t *pDM_Odm)
528 {
529 u8 EntryCnt = 0;
530 u8 i;
531 struct sta_info *pEntry;
532
533 if (*(pDM_Odm->pBandWidth) == ODM_BW40M) {
534 if (*(pDM_Odm->pSecChOffset) == 1)
535 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) - 2;
536 else if (*(pDM_Odm->pSecChOffset) == 2)
537 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) + 2;
538 } else {
539 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel);
540 }
541
542 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
543 pEntry = pDM_Odm->pODM_StaInfo[i];
544 if (pEntry)
545 EntryCnt++;
546 }
547 if (EntryCnt == 1)
548 pDM_Odm->bOneEntryOnly = true;
549 else
550 pDM_Odm->bOneEntryOnly = false;
551 }
552
553 void odm_CmnInfoInit_Debug23a(struct dm_odm_t *pDM_Odm)
554 {
555 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoInit_Debug23a ==>\n"));
556 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportAbility = 0x%x\n", pDM_Odm->SupportAbility));
557 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportInterface =%d\n", pDM_Odm->SupportInterface));
558 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportICType = 0x%x\n", pDM_Odm->SupportICType));
559 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("CutVersion =%d\n", pDM_Odm->CutVersion));
560 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("FabVersion =%d\n", pDM_Odm->FabVersion));
561 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RFType =%d\n", pDM_Odm->RFType));
562 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("BoardType =%d\n", pDM_Odm->BoardType));
563 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtLNA =%d\n", pDM_Odm->ExtLNA));
564 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtPA =%d\n", pDM_Odm->ExtPA));
565 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtTRSW =%d\n", pDM_Odm->ExtTRSW));
566 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("PatchID =%d\n", pDM_Odm->PatchID));
567 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bInHctTest =%d\n", pDM_Odm->bInHctTest));
568 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFITest =%d\n", pDM_Odm->bWIFITest));
569 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bDualMacSmartConcurrent =%d\n", pDM_Odm->bDualMacSmartConcurrent));
570
571 }
572
573 void odm_CmnInfoHook_Debug23a(struct dm_odm_t *pDM_Odm)
574 {
575 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoHook_Debug23a ==>\n"));
576 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecChOffset =%d\n", *(pDM_Odm->pSecChOffset)));
577 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBandWidth =%d\n", *(pDM_Odm->pBandWidth)));
578 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pChannel =%d\n", *(pDM_Odm->pChannel)));
579
580 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbScanInProcess =%d\n", *(pDM_Odm->pbScanInProcess)));
581 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbPowerSaving =%d\n", *(pDM_Odm->pbPowerSaving)));
582 }
583
584 void odm_CmnInfoUpdate_Debug23a(struct dm_odm_t *pDM_Odm)
585 {
586 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoUpdate_Debug23a ==>\n"));
587 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Direct =%d\n", pDM_Odm->bWIFI_Direct));
588 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Display =%d\n", pDM_Odm->bWIFI_Display));
589 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked =%d\n", pDM_Odm->bLinked));
590 ODM_RT_TRACE(pDM_Odm, ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_Min =%d\n", pDM_Odm->RSSI_Min));
591 }
592
593 void ODM_Write_DIG23a(struct dm_odm_t *pDM_Odm,
594 u8 CurrentIGI
595 )
596 {
597 struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
598
599 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_REG(IGI_A, pDM_Odm) = 0x%x, ODM_BIT(IGI, pDM_Odm) = 0x%x \n",
600 ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm)));
601
602 if (pDM_DigTable->CurIGValue != CurrentIGI) {
603 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm), CurrentIGI);
604 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("CurrentIGI(0x%02x). \n", CurrentIGI));
605 pDM_DigTable->CurIGValue = CurrentIGI;
606 }
607 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
608 ("ODM_Write_DIG23a():CurrentIGI = 0x%x \n", CurrentIGI));
609 }
610
611 /* Need LPS mode for CE platform --2012--08--24--- */
612 /* 8723AS/8189ES */
613 void odm_DIG23abyRSSI_LPS(struct dm_odm_t *pDM_Odm)
614 {
615 struct rtw_adapter *pAdapter = pDM_Odm->Adapter;
616 struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
617 u8 RSSI_Lower = DM_DIG_MIN_NIC; /* 0x1E or 0x1C */
618 u8 bFwCurrentInPSMode = false;
619 u8 CurrentIGI = pDM_Odm->RSSI_Min;
620
621 if (!(pDM_Odm->SupportICType & ODM_RTL8723A))
622 return;
623
624 CurrentIGI = CurrentIGI+RSSI_OFFSET_DIG;
625 bFwCurrentInPSMode = pAdapter->pwrctrlpriv.bFwCurrentInPSMode;
626
627 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG_LPS, ODM_DBG_LOUD, ("odm_DIG23a() ==>\n")); */
628
629 /* Using FW PS mode to make IGI */
630 if (bFwCurrentInPSMode) {
631 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("---Neil---odm_DIG23a is in LPS mode\n"));
632 /* Adjust by FA in LPS MODE */
633 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_LPS)
634 CurrentIGI = CurrentIGI+2;
635 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_LPS)
636 CurrentIGI = CurrentIGI+1;
637 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_LPS)
638 CurrentIGI = CurrentIGI-1;
639 } else {
640 CurrentIGI = RSSI_Lower;
641 }
642
643 /* Lower bound checking */
644
645 /* RSSI Lower bound check */
646 if ((pDM_Odm->RSSI_Min-10) > DM_DIG_MIN_NIC)
647 RSSI_Lower = (pDM_Odm->RSSI_Min-10);
648 else
649 RSSI_Lower = DM_DIG_MIN_NIC;
650
651 /* Upper and Lower Bound checking */
652 if (CurrentIGI > DM_DIG_MAX_NIC)
653 CurrentIGI = DM_DIG_MAX_NIC;
654 else if (CurrentIGI < RSSI_Lower)
655 CurrentIGI = RSSI_Lower;
656
657 ODM_Write_DIG23a(pDM_Odm, CurrentIGI);/* ODM_Write_DIG23a(pDM_Odm, pDM_DigTable->CurIGValue); */
658
659 }
660
661 void odm_DIG23aInit(struct dm_odm_t *pDM_Odm)
662 {
663 struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
664
665 pDM_DigTable->CurIGValue = (u8) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A, pDM_Odm), ODM_BIT(IGI, pDM_Odm));
666 pDM_DigTable->RssiLowThresh = DM_DIG_THRESH_LOW;
667 pDM_DigTable->RssiHighThresh = DM_DIG_THRESH_HIGH;
668 pDM_DigTable->FALowThresh = DM_FALSEALARM_THRESH_LOW;
669 pDM_DigTable->FAHighThresh = DM_FALSEALARM_THRESH_HIGH;
670 if (pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) {
671 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
672 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
673 } else {
674 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
675 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
676 }
677 pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT;
678 pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX;
679 pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN;
680 pDM_DigTable->PreCCK_CCAThres = 0xFF;
681 pDM_DigTable->CurCCK_CCAThres = 0x83;
682 pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC;
683 pDM_DigTable->LargeFAHit = 0;
684 pDM_DigTable->Recover_cnt = 0;
685 pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC;
686 pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC;
687 pDM_DigTable->bMediaConnect_0 = false;
688 pDM_DigTable->bMediaConnect_1 = false;
689 }
690
691 void odm_DIG23a(struct dm_odm_t *pDM_Odm)
692 {
693
694 struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
695 struct false_alarm_stats *pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
696 u8 DIG_Dynamic_MIN;
697 u8 DIG_MaxOfMin;
698 bool FirstConnect, FirstDisConnect;
699 u8 dm_dig_max, dm_dig_min;
700 u8 CurrentIGI = pDM_DigTable->CurIGValue;
701
702 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a() ==>\n"));
703 /* if (!(pDM_Odm->SupportAbility & (ODM_BB_DIG|ODM_BB_FA_CNT))) */
704 if ((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) || (!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT))) {
705 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
706 ("odm_DIG23a() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n"));
707 return;
708 }
709
710 if (*(pDM_Odm->pbScanInProcess)) {
711 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a() Return: In Scan Progress \n"));
712 return;
713 }
714
715 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
716 FirstConnect = (pDM_Odm->bLinked) && (!pDM_DigTable->bMediaConnect_0);
717 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0);
718
719 /* 1 Boundary Decision */
720 if ((pDM_Odm->SupportICType & ODM_RTL8723A) &&
721 ((pDM_Odm->BoardType == ODM_BOARD_HIGHPWR) || pDM_Odm->ExtLNA)) {
722 dm_dig_max = DM_DIG_MAX_NIC_HP;
723 dm_dig_min = DM_DIG_MIN_NIC_HP;
724 DIG_MaxOfMin = DM_DIG_MAX_AP_HP;
725 } else {
726 dm_dig_max = DM_DIG_MAX_NIC;
727 dm_dig_min = DM_DIG_MIN_NIC;
728 DIG_MaxOfMin = DM_DIG_MAX_AP;
729 }
730
731 if (pDM_Odm->bLinked) {
732 /* 2 8723A Series, offset need to be 10 */
733 if (pDM_Odm->SupportICType == ODM_RTL8723A) {
734 /* 2 Upper Bound */
735 if ((pDM_Odm->RSSI_Min + 10) > DM_DIG_MAX_NIC)
736 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
737 else if ((pDM_Odm->RSSI_Min + 10) < DM_DIG_MIN_NIC)
738 pDM_DigTable->rx_gain_range_max = DM_DIG_MIN_NIC;
739 else
740 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 10;
741
742 /* 2 If BT is Concurrent, need to set Lower Bound */
743 DIG_Dynamic_MIN = DM_DIG_MIN_NIC;
744 } else {
745 /* 2 Modify DIG upper bound */
746 if ((pDM_Odm->RSSI_Min + 20) > dm_dig_max)
747 pDM_DigTable->rx_gain_range_max = dm_dig_max;
748 else if ((pDM_Odm->RSSI_Min + 20) < dm_dig_min)
749 pDM_DigTable->rx_gain_range_max = dm_dig_min;
750 else
751 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20;
752
753 /* 2 Modify DIG lower bound */
754 if (pDM_Odm->bOneEntryOnly) {
755 if (pDM_Odm->RSSI_Min < dm_dig_min)
756 DIG_Dynamic_MIN = dm_dig_min;
757 else if (pDM_Odm->RSSI_Min > DIG_MaxOfMin)
758 DIG_Dynamic_MIN = DIG_MaxOfMin;
759 else
760 DIG_Dynamic_MIN = pDM_Odm->RSSI_Min;
761 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
762 ("odm_DIG23a() : bOneEntryOnly = true, DIG_Dynamic_MIN = 0x%x\n",
763 DIG_Dynamic_MIN));
764 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
765 ("odm_DIG23a() : pDM_Odm->RSSI_Min =%d\n",
766 pDM_Odm->RSSI_Min));
767 } else {
768 DIG_Dynamic_MIN = dm_dig_min;
769 }
770 }
771 } else {
772 pDM_DigTable->rx_gain_range_max = dm_dig_max;
773 DIG_Dynamic_MIN = dm_dig_min;
774 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a() : No Link\n"));
775 }
776
777 /* 1 Modify DIG lower bound, deal with abnormally large false alarm */
778 if (pFalseAlmCnt->Cnt_all > 10000) {
779 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
780 ("dm_DIG(): Abnornally false alarm case. \n"));
781
782 if (pDM_DigTable->LargeFAHit != 3)
783 pDM_DigTable->LargeFAHit++;
784 if (pDM_DigTable->ForbiddenIGI < CurrentIGI) {
785 pDM_DigTable->ForbiddenIGI = CurrentIGI;
786 pDM_DigTable->LargeFAHit = 1;
787 }
788
789 if (pDM_DigTable->LargeFAHit >= 3) {
790 if ((pDM_DigTable->ForbiddenIGI+1) > pDM_DigTable->rx_gain_range_max)
791 pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max;
792 else
793 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
794 pDM_DigTable->Recover_cnt = 3600; /* 3600 = 2hr */
795 }
796 } else {
797 /* Recovery mechanism for IGI lower bound */
798 if (pDM_DigTable->Recover_cnt != 0) {
799 pDM_DigTable->Recover_cnt--;
800 } else {
801 if (pDM_DigTable->LargeFAHit < 3) {
802 if ((pDM_DigTable->ForbiddenIGI - 1) < DIG_Dynamic_MIN) {
803 pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
804 pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; /* DM_DIG_MIN; */
805 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
806 ("odm_DIG23a(): Normal Case: At Lower Bound\n"));
807 } else {
808 pDM_DigTable->ForbiddenIGI--;
809 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
810 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD,
811 ("odm_DIG23a(): Normal Case: Approach Lower Bound\n"));
812 }
813 } else {
814 pDM_DigTable->LargeFAHit = 0;
815 }
816 }
817 }
818 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): pDM_DigTable->LargeFAHit =%d\n", pDM_DigTable->LargeFAHit));
819
820 /* 1 Adjust initial gain by false alarm */
821 if (pDM_Odm->bLinked) {
822 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): DIG AfterLink\n"));
823 if (FirstConnect) {
824 CurrentIGI = pDM_Odm->RSSI_Min;
825 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n"));
826 } else {
827 if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2)
828 CurrentIGI = CurrentIGI + 4;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
829 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1)
830 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
831 else if (pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0)
832 CurrentIGI = CurrentIGI - 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue-1; */
833 }
834 } else {
835 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): DIG BeforeLink\n"));
836 if (FirstDisConnect) {
837 CurrentIGI = pDM_DigTable->rx_gain_range_min;
838 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): First DisConnect \n"));
839 } else {
840 /* 2012.03.30 LukeLee: enable DIG before link but with very high thresholds */
841 if (pFalseAlmCnt->Cnt_all > 10000)
842 CurrentIGI = CurrentIGI + 2;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2; */
843 else if (pFalseAlmCnt->Cnt_all > 8000)
844 CurrentIGI = CurrentIGI + 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1; */
845 else if (pFalseAlmCnt->Cnt_all < 500)
846 CurrentIGI = CurrentIGI - 1;/* pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue-1; */
847 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): England DIG \n"));
848 }
849 }
850 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): DIG End Adjust IGI\n"));
851 /* 1 Check initial gain by upper/lower bound */
852 if (CurrentIGI > pDM_DigTable->rx_gain_range_max)
853 CurrentIGI = pDM_DigTable->rx_gain_range_max;
854 if (CurrentIGI < pDM_DigTable->rx_gain_range_min)
855 CurrentIGI = pDM_DigTable->rx_gain_range_min;
856
857 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): rx_gain_range_max = 0x%x, rx_gain_range_min = 0x%x\n",
858 pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min));
859 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): TotalFA =%d\n", pFalseAlmCnt->Cnt_all));
860 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG23a(): CurIGValue = 0x%x\n", CurrentIGI));
861
862 /* 2 High power RSSI threshold */
863
864 ODM_Write_DIG23a(pDM_Odm, CurrentIGI);/* ODM_Write_DIG23a(pDM_Odm, pDM_DigTable->CurIGValue); */
865 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
866 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
867 }
868
869 /* 3 ============================================================ */
870 /* 3 FASLE ALARM CHECK */
871 /* 3 ============================================================ */
872
873 void odm_FalseAlarmCounterStatistics23a(struct dm_odm_t *pDM_Odm)
874 {
875 u32 ret_value;
876 struct false_alarm_stats *FalseAlmCnt = &pDM_Odm->FalseAlmCnt;
877
878 if (!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))
879 return;
880
881 /* hold ofdm counter */
882 /* hold page C counter */
883 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1);
884 /* hold page D counter */
885 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 1);
886 ret_value =
887 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord);
888 FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff);
889 FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16);
890 ret_value =
891 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord);
892 FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff);
893 FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16);
894 ret_value =
895 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord);
896 FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff);
897 FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16);
898 ret_value =
899 ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord);
900 FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff);
901
902 FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail +
903 FalseAlmCnt->Cnt_Rate_Illegal +
904 FalseAlmCnt->Cnt_Crc8_fail +
905 FalseAlmCnt->Cnt_Mcs_fail +
906 FalseAlmCnt->Cnt_Fast_Fsync +
907 FalseAlmCnt->Cnt_SB_Search_fail;
908 /* hold cck counter */
909 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(12), 1);
910 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT(14), 1);
911
912 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_LSB_11N, bMaskByte0);
913 FalseAlmCnt->Cnt_Cck_fail = ret_value;
914 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_MSB_11N, bMaskByte3);
915 FalseAlmCnt->Cnt_Cck_fail += (ret_value & 0xff) << 8;
916
917 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord);
918 FalseAlmCnt->Cnt_CCK_CCA =
919 ((ret_value&0xFF)<<8) | ((ret_value&0xFF00)>>8);
920
921 FalseAlmCnt->Cnt_all = (FalseAlmCnt->Cnt_Fast_Fsync +
922 FalseAlmCnt->Cnt_SB_Search_fail +
923 FalseAlmCnt->Cnt_Parity_Fail +
924 FalseAlmCnt->Cnt_Rate_Illegal +
925 FalseAlmCnt->Cnt_Crc8_fail +
926 FalseAlmCnt->Cnt_Mcs_fail +
927 FalseAlmCnt->Cnt_Cck_fail);
928
929 FalseAlmCnt->Cnt_CCA_all =
930 FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA;
931
932 if (pDM_Odm->SupportICType >= ODM_RTL8723A) {
933 /* reset false alarm counter registers */
934 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31), 1);
935 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT(31), 0);
936 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27), 1);
937 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(27), 0);
938 /* update ofdm counter */
939 /* update page C counter */
940 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 0);
941 /* update page D counter */
942 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 0);
943
944 /* reset CCK CCA counter */
945 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
946 BIT(13) | BIT(12), 0);
947 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
948 BIT(13) | BIT(12), 2);
949 /* reset CCK FA counter */
950 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
951 BIT(15) | BIT(14), 0);
952 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N,
953 BIT(15) | BIT(14), 2);
954 }
955
956 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
957 ("Enter odm_FalseAlarmCounterStatistics23a\n"));
958 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
959 ("Cnt_Fast_Fsync =%d, Cnt_SB_Search_fail =%d\n",
960 FalseAlmCnt->Cnt_Fast_Fsync,
961 FalseAlmCnt->Cnt_SB_Search_fail));
962 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
963 ("Cnt_Parity_Fail =%d, Cnt_Rate_Illegal =%d\n",
964 FalseAlmCnt->Cnt_Parity_Fail,
965 FalseAlmCnt->Cnt_Rate_Illegal));
966 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD,
967 ("Cnt_Crc8_fail =%d, Cnt_Mcs_fail =%d\n",
968 FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail));
969
970 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail =%d\n", FalseAlmCnt->Cnt_Cck_fail));
971 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail =%d\n", FalseAlmCnt->Cnt_Ofdm_fail));
972 ODM_RT_TRACE(pDM_Odm, ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm =%d\n", FalseAlmCnt->Cnt_all));
973 }
974
975 /* 3 ============================================================ */
976 /* 3 CCK Packet Detect Threshold */
977 /* 3 ============================================================ */
978
979 void odm_CCKPacketDetectionThresh23a(struct dm_odm_t *pDM_Odm)
980 {
981 struct false_alarm_stats *FalseAlmCnt = &pDM_Odm->FalseAlmCnt;
982 u8 CurCCK_CCAThres;
983
984 if (!(pDM_Odm->SupportAbility & (ODM_BB_CCK_PD|ODM_BB_FA_CNT)))
985 return;
986
987 if (pDM_Odm->ExtLNA)
988 return;
989
990 if (pDM_Odm->bLinked) {
991 if (pDM_Odm->RSSI_Min > 25) {
992 CurCCK_CCAThres = 0xcd;
993 } else if ((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10)) {
994 CurCCK_CCAThres = 0x83;
995 } else {
996 if (FalseAlmCnt->Cnt_Cck_fail > 1000)
997 CurCCK_CCAThres = 0x83;
998 else
999 CurCCK_CCAThres = 0x40;
1000 }
1001 } else {
1002 if (FalseAlmCnt->Cnt_Cck_fail > 1000)
1003 CurCCK_CCAThres = 0x83;
1004 else
1005 CurCCK_CCAThres = 0x40;
1006 }
1007
1008 ODM_Write_CCK_CCA_Thres23a(pDM_Odm, CurCCK_CCAThres);
1009 }
1010
1011 void ODM_Write_CCK_CCA_Thres23a(struct dm_odm_t *pDM_Odm, u8 CurCCK_CCAThres)
1012 {
1013 struct dig_t *pDM_DigTable = &pDM_Odm->DM_DigTable;
1014
1015 if (pDM_DigTable->CurCCK_CCAThres != CurCCK_CCAThres)
1016 ODM_Write1Byte(pDM_Odm, ODM_REG(CCK_CCA, pDM_Odm), CurCCK_CCAThres);
1017 pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres;
1018 pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres;
1019
1020 }
1021
1022 /* 3 ============================================================ */
1023 /* 3 BB Power Save */
1024 /* 3 ============================================================ */
1025 void odm23a_DynBBPSInit(struct dm_odm_t *pDM_Odm)
1026 {
1027 struct dynamic_pwr_sav *pDM_PSTable = &pDM_Odm->DM_PSTable;
1028
1029 pDM_PSTable->PreCCAState = CCA_MAX;
1030 pDM_PSTable->CurCCAState = CCA_MAX;
1031 pDM_PSTable->PreRFState = RF_MAX;
1032 pDM_PSTable->CurRFState = RF_MAX;
1033 pDM_PSTable->Rssi_val_min = 0;
1034 pDM_PSTable->initialize = 0;
1035 }
1036
1037 void odm_DynamicBBPowerSaving23a(struct dm_odm_t *pDM_Odm)
1038 {
1039 return;
1040 }
1041
1042 void odm_1R_CCA23a(struct dm_odm_t *pDM_Odm)
1043 {
1044 struct dynamic_pwr_sav *pDM_PSTable = &pDM_Odm->DM_PSTable;
1045
1046 if (pDM_Odm->RSSI_Min != 0xFF) {
1047 if (pDM_PSTable->PreCCAState == CCA_2R) {
1048 if (pDM_Odm->RSSI_Min >= 35)
1049 pDM_PSTable->CurCCAState = CCA_1R;
1050 else
1051 pDM_PSTable->CurCCAState = CCA_2R;
1052 } else {
1053 if (pDM_Odm->RSSI_Min <= 30)
1054 pDM_PSTable->CurCCAState = CCA_2R;
1055 else
1056 pDM_PSTable->CurCCAState = CCA_1R;
1057 }
1058 } else {
1059 pDM_PSTable->CurCCAState = CCA_MAX;
1060 }
1061
1062 if (pDM_PSTable->PreCCAState != pDM_PSTable->CurCCAState) {
1063 if (pDM_PSTable->CurCCAState == CCA_1R) {
1064 if (pDM_Odm->RFType == ODM_2T2R)
1065 ODM_SetBBReg(pDM_Odm, 0xc04, bMaskByte0, 0x13);
1066 else
1067 ODM_SetBBReg(pDM_Odm, 0xc04, bMaskByte0, 0x23);
1068 } else {
1069 ODM_SetBBReg(pDM_Odm, 0xc04, bMaskByte0, 0x33);
1070 /* PHY_SetBBReg(pAdapter, 0xe70, bMaskByte3, 0x63); */
1071 }
1072 pDM_PSTable->PreCCAState = pDM_PSTable->CurCCAState;
1073 }
1074 }
1075
1076 void ODM_RF_Saving23a(struct dm_odm_t *pDM_Odm, u8 bForceInNormal)
1077 {
1078 struct dynamic_pwr_sav *pDM_PSTable = &pDM_Odm->DM_PSTable;
1079 u8 Rssi_Up_bound = 30 ;
1080 u8 Rssi_Low_bound = 25;
1081 if (pDM_Odm->PatchID == 40) { /* RT_CID_819x_FUNAI_TV */
1082 Rssi_Up_bound = 50 ;
1083 Rssi_Low_bound = 45;
1084 }
1085 if (pDM_PSTable->initialize == 0) {
1086
1087 pDM_PSTable->Reg874 = (ODM_GetBBReg(pDM_Odm, 0x874, bMaskDWord)&0x1CC000)>>14;
1088 pDM_PSTable->RegC70 =
1089 (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord) & BIT(3)) >>3;
1090 pDM_PSTable->Reg85C = (ODM_GetBBReg(pDM_Odm, 0x85c, bMaskDWord)&0xFF000000)>>24;
1091 pDM_PSTable->RegA74 = (ODM_GetBBReg(pDM_Odm, 0xa74, bMaskDWord)&0xF000)>>12;
1092 /* Reg818 = PHY_QueryBBReg(pAdapter, 0x818, bMaskDWord); */
1093 pDM_PSTable->initialize = 1;
1094 }
1095
1096 if (!bForceInNormal) {
1097 if (pDM_Odm->RSSI_Min != 0xFF) {
1098 if (pDM_PSTable->PreRFState == RF_Normal) {
1099 if (pDM_Odm->RSSI_Min >= Rssi_Up_bound)
1100 pDM_PSTable->CurRFState = RF_Save;
1101 else
1102 pDM_PSTable->CurRFState = RF_Normal;
1103 } else {
1104 if (pDM_Odm->RSSI_Min <= Rssi_Low_bound)
1105 pDM_PSTable->CurRFState = RF_Normal;
1106 else
1107 pDM_PSTable->CurRFState = RF_Save;
1108 }
1109 } else {
1110 pDM_PSTable->CurRFState = RF_MAX;
1111 }
1112 } else {
1113 pDM_PSTable->CurRFState = RF_Normal;
1114 }
1115
1116 if (pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) {
1117 if (pDM_PSTable->CurRFState == RF_Save) {
1118 /* <tynli_note> 8723 RSSI report will be wrong. Set 0x874[5]= 1 when enter BB power saving mode. */
1119 /* Suggested by SD3 Yu-Nan. 2011.01.20. */
1120 if (pDM_Odm->SupportICType == ODM_RTL8723A)
1121 ODM_SetBBReg(pDM_Odm, 0x874, BIT(5), 0x1); /* Reg874[5]= 1b'1 */
1122 ODM_SetBBReg(pDM_Odm, 0x874, 0x1C0000, 0x2); /* Reg874[20:18]= 3'b010 */
1123 ODM_SetBBReg(pDM_Odm, 0xc70, BIT(3), 0); /* RegC70[3]= 1'b0 */
1124 ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]= 0x63 */
1125 ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); /* Reg874[15:14]= 2'b10 */
1126 ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); /* RegA75[7:4]= 0x3 */
1127 ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x0); /* Reg818[28]= 1'b0 */
1128 ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x1); /* Reg818[28]= 1'b1 */
1129 } else {
1130 ODM_SetBBReg(pDM_Odm, 0x874, 0x1CC000, pDM_PSTable->Reg874);
1131 ODM_SetBBReg(pDM_Odm, 0xc70, BIT(3), pDM_PSTable->RegC70);
1132 ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, pDM_PSTable->Reg85C);
1133 ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, pDM_PSTable->RegA74);
1134 ODM_SetBBReg(pDM_Odm, 0x818, BIT(28), 0x0);
1135
1136 if (pDM_Odm->SupportICType == ODM_RTL8723A)
1137 ODM_SetBBReg(pDM_Odm, 0x874, BIT(5), 0x0); /* Reg874[5]= 1b'0 */
1138 }
1139 pDM_PSTable->PreRFState = pDM_PSTable->CurRFState;
1140 }
1141 }
1142
1143 /* 3 ============================================================ */
1144 /* 3 RATR MASK */
1145 /* 3 ============================================================ */
1146 /* 3 ============================================================ */
1147 /* 3 Rate Adaptive */
1148 /* 3 ============================================================ */
1149
1150 void odm_RateAdaptiveMaskInit23a(struct dm_odm_t *pDM_Odm)
1151 {
1152 struct odm_rate_adapt *pOdmRA = &pDM_Odm->RateAdaptive;
1153
1154 pOdmRA->Type = DM_Type_ByDriver;
1155 if (pOdmRA->Type == DM_Type_ByDriver)
1156 pDM_Odm->bUseRAMask = true;
1157 else
1158 pDM_Odm->bUseRAMask = false;
1159
1160 pOdmRA->RATRState = DM_RATR_STA_INIT;
1161 pOdmRA->HighRSSIThresh = 50;
1162 pOdmRA->LowRSSIThresh = 20;
1163 }
1164
1165 u32 ODM_Get_Rate_Bitmap23a(struct dm_odm_t *pDM_Odm,
1166 u32 macid,
1167 u32 ra_mask,
1168 u8 rssi_level)
1169 {
1170 struct sta_info *pEntry;
1171 u32 rate_bitmap = 0x0fffffff;
1172 u8 WirelessMode;
1173
1174 pEntry = pDM_Odm->pODM_StaInfo[macid];
1175 if (!pEntry)
1176 return ra_mask;
1177
1178 WirelessMode = pEntry->wireless_mode;
1179
1180 switch (WirelessMode) {
1181 case ODM_WM_B:
1182 if (ra_mask & 0x0000000c) /* 11M or 5.5M enable */
1183 rate_bitmap = 0x0000000d;
1184 else
1185 rate_bitmap = 0x0000000f;
1186 break;
1187 case (ODM_WM_A|ODM_WM_G):
1188 if (rssi_level == DM_RATR_STA_HIGH)
1189 rate_bitmap = 0x00000f00;
1190 else
1191 rate_bitmap = 0x00000ff0;
1192 break;
1193 case (ODM_WM_B|ODM_WM_G):
1194 if (rssi_level == DM_RATR_STA_HIGH)
1195 rate_bitmap = 0x00000f00;
1196 else if (rssi_level == DM_RATR_STA_MIDDLE)
1197 rate_bitmap = 0x00000ff0;
1198 else
1199 rate_bitmap = 0x00000ff5;
1200 break;
1201 case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G):
1202 case (ODM_WM_A|ODM_WM_B|ODM_WM_G|ODM_WM_N24G):
1203 if (pDM_Odm->RFType == ODM_1T2R || pDM_Odm->RFType == ODM_1T1R) {
1204 if (rssi_level == DM_RATR_STA_HIGH) {
1205 rate_bitmap = 0x000f0000;
1206 } else if (rssi_level == DM_RATR_STA_MIDDLE) {
1207 rate_bitmap = 0x000ff000;
1208 } else {
1209 if (*(pDM_Odm->pBandWidth) == ODM_BW40M)
1210 rate_bitmap = 0x000ff015;
1211 else
1212 rate_bitmap = 0x000ff005;
1213 }
1214 } else {
1215 if (rssi_level == DM_RATR_STA_HIGH) {
1216 rate_bitmap = 0x0f8f0000;
1217 } else if (rssi_level == DM_RATR_STA_MIDDLE) {
1218 rate_bitmap = 0x0f8ff000;
1219 } else {
1220 if (*(pDM_Odm->pBandWidth) == ODM_BW40M)
1221 rate_bitmap = 0x0f8ff015;
1222 else
1223 rate_bitmap = 0x0f8ff005;
1224 }
1225 }
1226 break;
1227 default:
1228 /* case WIRELESS_11_24N: */
1229 /* case WIRELESS_11_5N: */
1230 if (pDM_Odm->RFType == RF_1T2R)
1231 rate_bitmap = 0x000fffff;
1232 else
1233 rate_bitmap = 0x0fffffff;
1234 break;
1235 }
1236
1237 /* printk("%s ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x \n", __func__, rssi_level, WirelessMode, rate_bitmap); */
1238 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x \n", rssi_level, WirelessMode, rate_bitmap));
1239
1240 return rate_bitmap;
1241
1242 }
1243
1244 /*-----------------------------------------------------------------------------
1245 * Function: odm_RefreshRateAdaptiveMask23a()
1246 *
1247 * Overview: Update rate table mask according to rssi
1248 *
1249 * Input: NONE
1250 *
1251 * Output: NONE
1252 *
1253 * Return: NONE
1254 *
1255 * Revised History:
1256 *When Who Remark
1257 *05/27/2009 hpfan Create Version 0.
1258 *
1259 *---------------------------------------------------------------------------*/
1260 void odm_RefreshRateAdaptiveMask23a(struct dm_odm_t *pDM_Odm)
1261 {
1262 if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK))
1263 return;
1264 /* */
1265 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1266 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
1267 /* HW dynamic mechanism. */
1268 /* */
1269 odm_RefreshRateAdaptiveMask23aCE23a(pDM_Odm);
1270 }
1271
1272 void odm_RefreshRateAdaptiveMask23aMP23a(struct dm_odm_t *pDM_Odm)
1273 {
1274 }
1275
1276 void odm_RefreshRateAdaptiveMask23aCE23a(struct dm_odm_t *pDM_Odm)
1277 {
1278 u8 i;
1279 struct rtw_adapter *pAdapter = pDM_Odm->Adapter;
1280
1281 if (pAdapter->bDriverStopped) {
1282 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE,
1283 ("<---- odm_RefreshRateAdaptiveMask23a(): driver is going to unload\n"));
1284 return;
1285 }
1286
1287 if (!pDM_Odm->bUseRAMask) {
1288 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
1289 ("<---- odm_RefreshRateAdaptiveMask23a(): driver does not control rate adaptive mask\n"));
1290 return;
1291 }
1292
1293 /* printk("==> %s \n", __func__); */
1294
1295 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
1296 struct sta_info *pstat = pDM_Odm->pODM_StaInfo[i];
1297 if (pstat) {
1298 if (ODM_RAStateCheck23a(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, false, &pstat->rssi_level)) {
1299 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
1300 ("RSSI:%d, RSSI_LEVEL:%d\n",
1301 pstat->rssi_stat.UndecoratedSmoothedPWDB,
1302 pstat->rssi_level));
1303 rtw_hal_update_ra_mask23a(pstat, pstat->rssi_level);
1304 }
1305
1306 }
1307 }
1308
1309 }
1310
1311 void odm_RefreshRateAdaptiveMask23aAPADSL23a(struct dm_odm_t *pDM_Odm)
1312 {
1313 }
1314
1315 /* Return Value: bool */
1316 /* - true: RATRState is changed. */
1317 bool ODM_RAStateCheck23a(struct dm_odm_t *pDM_Odm, s32 RSSI, bool bForceUpdate,
1318 u8 *pRATRState)
1319 {
1320 struct odm_rate_adapt *pRA = &pDM_Odm->RateAdaptive;
1321 const u8 GoUpGap = 5;
1322 u8 HighRSSIThreshForRA = pRA->HighRSSIThresh;
1323 u8 LowRSSIThreshForRA = pRA->LowRSSIThresh;
1324 u8 RATRState;
1325
1326 /* Threshold Adjustment: */
1327 /* when RSSI state trends to go up one or two levels, make sure RSSI is high enough. */
1328 /* Here GoUpGap is added to solve the boundary's level alternation issue. */
1329 switch (*pRATRState) {
1330 case DM_RATR_STA_INIT:
1331 case DM_RATR_STA_HIGH:
1332 break;
1333 case DM_RATR_STA_MIDDLE:
1334 HighRSSIThreshForRA += GoUpGap;
1335 break;
1336 case DM_RATR_STA_LOW:
1337 HighRSSIThreshForRA += GoUpGap;
1338 LowRSSIThreshForRA += GoUpGap;
1339 break;
1340 default:
1341 ODM_RT_ASSERT(pDM_Odm, false, ("wrong rssi level setting %d !", *pRATRState));
1342 break;
1343 }
1344
1345 /* Decide RATRState by RSSI. */
1346 if (RSSI > HighRSSIThreshForRA)
1347 RATRState = DM_RATR_STA_HIGH;
1348 else if (RSSI > LowRSSIThreshForRA)
1349 RATRState = DM_RATR_STA_MIDDLE;
1350 else
1351 RATRState = DM_RATR_STA_LOW;
1352
1353 if (*pRATRState != RATRState || bForceUpdate) {
1354 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD,
1355 ("RSSI Level %d -> %d\n", *pRATRState, RATRState));
1356 *pRATRState = RATRState;
1357 return true;
1358 }
1359 return false;
1360 }
1361
1362 /* 3 ============================================================ */
1363 /* 3 Dynamic Tx Power */
1364 /* 3 ============================================================ */
1365
1366 void odm_DynamicTxPower23aInit(struct dm_odm_t *pDM_Odm)
1367 {
1368 struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1369 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1370 struct dm_priv *pdmpriv = &pHalData->dmpriv;
1371
1372 /*
1373 * This is never changed, so we should be able to clean up the
1374 * code checking for different values in rtl8723a_rf6052.c
1375 */
1376 pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
1377 }
1378
1379 /* 3 ============================================================ */
1380 /* 3 RSSI Monitor */
1381 /* 3 ============================================================ */
1382
1383 void odm_RSSIMonitorInit(struct dm_odm_t *pDM_Odm)
1384 {
1385 }
1386
1387 void odm_RSSIMonitorCheck23a(struct dm_odm_t *pDM_Odm)
1388 {
1389 /* For AP/ADSL use struct rtl8723a_priv * */
1390 /* For CE/NIC use struct rtw_adapter * */
1391
1392 if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR))
1393 return;
1394
1395 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1396 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
1397 /* HW dynamic mechanism. */
1398 odm_RSSIMonitorCheck23aCE(pDM_Odm);
1399 } /* odm_RSSIMonitorCheck23a */
1400
1401 void odm_RSSIMonitorCheck23aMP(struct dm_odm_t *pDM_Odm)
1402 {
1403 }
1404
1405 static void
1406 FindMinimumRSSI(
1407 struct rtw_adapter *pAdapter
1408 )
1409 {
1410 struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter);
1411 struct dm_priv *pdmpriv = &pHalData->dmpriv;
1412 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv;
1413
1414 /* 1 1.Determine the minimum RSSI */
1415
1416 if ((!pDM_Odm->bLinked) &&
1417 (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0))
1418 pdmpriv->MinUndecoratedPWDBForDM = 0;
1419 else
1420 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
1421 }
1422
1423 void odm_RSSIMonitorCheck23aCE(struct dm_odm_t *pDM_Odm)
1424 {
1425 struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1426 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1427 struct dm_priv *pdmpriv = &pHalData->dmpriv;
1428 int i;
1429 int tmpEntryMaxPWDB = 0, tmpEntryMinPWDB = 0xff;
1430 u8 sta_cnt = 0;
1431 u32 PWDB_rssi[NUM_STA] = {0};/* 0~15]:MACID, [16~31]:PWDB_rssi */
1432 struct sta_info *psta;
1433
1434 if (!pDM_Odm->bLinked)
1435 return;
1436
1437 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
1438 psta = pDM_Odm->pODM_StaInfo[i];
1439 if (psta) {
1440 if (psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB)
1441 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
1442
1443 if (psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB)
1444 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
1445
1446 if (psta->rssi_stat.UndecoratedSmoothedPWDB != (-1))
1447 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16));
1448 }
1449 }
1450
1451 for (i = 0; i < sta_cnt; i++) {
1452 if (PWDB_rssi[i] != (0)) {
1453 if (pHalData->fw_ractrl) /* Report every sta's RSSI to FW */
1454 rtl8723a_set_rssi_cmd(Adapter, (u8 *)&PWDB_rssi[i]);
1455 }
1456 }
1457
1458 if (tmpEntryMaxPWDB != 0) /* If associated entry is found */
1459 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB;
1460 else
1461 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0;
1462
1463 if (tmpEntryMinPWDB != 0xff) /* If associated entry is found */
1464 pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB;
1465 else
1466 pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0;
1467
1468 FindMinimumRSSI(Adapter);/* get pdmpriv->MinUndecoratedPWDBForDM */
1469
1470 ODM_CmnInfoUpdate23a(&pHalData->odmpriv, ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM);
1471 }
1472
1473 void odm_RSSIMonitorCheck23aAP(struct dm_odm_t *pDM_Odm)
1474 {
1475 }
1476
1477 /* endif */
1478 /* 3 ============================================================ */
1479 /* 3 Tx Power Tracking */
1480 /* 3 ============================================================ */
1481
1482 void odm_TXPowerTrackingInit23a(struct dm_odm_t *pDM_Odm)
1483 {
1484 odm_TXPowerTrackingThermalMeterInit23a(pDM_Odm);
1485 }
1486
1487 void odm_TXPowerTrackingThermalMeterInit23a(struct dm_odm_t *pDM_Odm)
1488 {
1489 struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1490 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1491 struct dm_priv *pdmpriv = &pHalData->dmpriv;
1492
1493 pdmpriv->bTXPowerTracking = true;
1494 pdmpriv->TXPowercount = 0;
1495 pdmpriv->bTXPowerTrackingInit = false;
1496 pdmpriv->TxPowerTrackControl = true;
1497 MSG_8723A("pdmpriv->TxPowerTrackControl = %d\n", pdmpriv->TxPowerTrackControl);
1498
1499 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = true;
1500 }
1501
1502 void ODM_TXPowerTrackingCheck23a(struct dm_odm_t *pDM_Odm)
1503 {
1504 /* For AP/ADSL use struct rtl8723a_priv * */
1505 /* For CE/NIC use struct rtw_adapter * */
1506
1507 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1508 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
1509 /* HW dynamic mechanism. */
1510 odm_TXPowerTrackingCheckCE23a(pDM_Odm);
1511 }
1512
1513 void odm_TXPowerTrackingCheckCE23a(struct dm_odm_t *pDM_Odm)
1514 {
1515 }
1516
1517 void odm_TXPowerTrackingCheckMP(struct dm_odm_t *pDM_Odm)
1518 {
1519 }
1520
1521 void odm_TXPowerTrackingCheckAP(struct dm_odm_t *pDM_Odm)
1522 {
1523 }
1524
1525 /* antenna mapping info */
1526 /* 1: right-side antenna */
1527 /* 2/0: left-side antenna */
1528 /* PpDM_SWAT_Table->CCK_Ant1_Cnt /OFDM_Ant1_Cnt: for right-side antenna: Ant:1 RxDefaultAnt1 */
1529 /* PpDM_SWAT_Table->CCK_Ant2_Cnt /OFDM_Ant2_Cnt: for left-side antenna: Ant:0 RxDefaultAnt2 */
1530 /* We select left antenna as default antenna in initial process, modify it as needed */
1531 /* */
1532
1533 /* 3 ============================================================ */
1534 /* 3 SW Antenna Diversity */
1535 /* 3 ============================================================ */
1536 void odm_SwAntDivInit(struct dm_odm_t *pDM_Odm)
1537 {
1538 }
1539
1540 void ODM_SwAntDivChkPerPktRssi(struct dm_odm_t *pDM_Odm, u8 StationID,
1541 struct phy_info *pPhyInfo)
1542 {
1543 }
1544
1545 void odm_SwAntDivChkAntSwitch(struct dm_odm_t *pDM_Odm, u8 Step)
1546 {
1547 }
1548
1549 void ODM_SwAntDivRestAfterLink(struct dm_odm_t *pDM_Odm)
1550 {
1551 }
1552
1553 void odm_SwAntDivChkAntSwitchCallback23a(unsigned long data)
1554 {
1555 }
1556
1557 /* 3 ============================================================ */
1558 /* 3 SW Antenna Diversity */
1559 /* 3 ============================================================ */
1560
1561 void odm_InitHybridAntDiv23a(struct dm_odm_t *pDM_Odm)
1562 {
1563 }
1564
1565 void odm_HwAntDiv23a(struct dm_odm_t *pDM_Odm)
1566 {
1567 }
1568
1569 /* EDCA Turbo */
1570 static void ODM_EdcaTurboInit23a(struct dm_odm_t *pDM_Odm)
1571 {
1572
1573 struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1574 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
1575 pDM_Odm->DM_EDCA_Table.bIsCurRDLState = false;
1576 Adapter->recvpriv.bIsAnyNonBEPkts = false;
1577
1578 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VO PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_VO_PARAM)));
1579 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial VI PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_VI_PARAM)));
1580 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BE PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_BE_PARAM)));
1581 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("Orginial BK PARAM: 0x%x\n", ODM_Read4Byte(pDM_Odm, ODM_EDCA_BK_PARAM)));
1582
1583 } /* ODM_InitEdcaTurbo */
1584
1585 static void odm_EdcaTurboCheck23a(struct dm_odm_t *pDM_Odm)
1586 {
1587 struct rtw_adapter *Adapter = pDM_Odm->Adapter;
1588 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1589 struct xmit_priv *pxmitpriv = &Adapter->xmitpriv;
1590 struct recv_priv *precvpriv = &Adapter->recvpriv;
1591 struct registry_priv *pregpriv = &Adapter->registrypriv;
1592 struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
1593 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
1594 u32 trafficIndex;
1595 u32 edca_param;
1596 u64 cur_tx_bytes = 0;
1597 u64 cur_rx_bytes = 0;
1598 u8 bbtchange = false;
1599
1600 /* For AP/ADSL use struct rtl8723a_priv * */
1601 /* For CE/NIC use struct rtw_adapter * */
1602
1603 /* 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate */
1604 /* at the same time. In the stage2/3, we need to prive universal interface and merge all */
1605 /* HW dynamic mechanism. */
1606
1607 if (!(pDM_Odm->SupportAbility & ODM_MAC_EDCA_TURBO))
1608 return;
1609
1610 if ((pregpriv->wifi_spec == 1))/* (pmlmeinfo->HT_enable == 0)) */
1611 goto dm_CheckEdcaTurbo_EXIT;
1612
1613 if (pmlmeinfo->assoc_AP_vendor >= HT_IOT_PEER_MAX)
1614 goto dm_CheckEdcaTurbo_EXIT;
1615
1616 if (rtl8723a_BT_disable_EDCA_turbo(Adapter))
1617 goto dm_CheckEdcaTurbo_EXIT;
1618
1619 /* Check if the status needs to be changed. */
1620 if ((bbtchange) || (!precvpriv->bIsAnyNonBEPkts)) {
1621 cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes;
1622 cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes;
1623
1624 /* traffic, TX or RX */
1625 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_RALINK) ||
1626 (pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_ATHEROS)) {
1627 if (cur_tx_bytes > (cur_rx_bytes << 2)) {
1628 /* Uplink TP is present. */
1629 trafficIndex = UP_LINK;
1630 } else { /* Balance TP is present. */
1631 trafficIndex = DOWN_LINK;
1632 }
1633 } else {
1634 if (cur_rx_bytes > (cur_tx_bytes << 2)) {
1635 /* Downlink TP is present. */
1636 trafficIndex = DOWN_LINK;
1637 } else { /* Balance TP is present. */
1638 trafficIndex = UP_LINK;
1639 }
1640 }
1641
1642 if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) ||
1643 (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)) {
1644 if ((pmlmeinfo->assoc_AP_vendor == HT_IOT_PEER_CISCO) &&
1645 (pmlmeext->cur_wireless_mode & WIRELESS_11_24N))
1646 edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex];
1647 else
1648 edca_param = EDCAParam[HT_IOT_PEER_UNKNOWN][trafficIndex];
1649 rtl8723au_write32(Adapter, REG_EDCA_BE_PARAM,
1650 edca_param);
1651
1652 pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex;
1653 }
1654
1655 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = true;
1656 } else {
1657 /* Turn Off EDCA turbo here. */
1658 /* Restore original EDCA according to the declaration of AP. */
1659 if (pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA) {
1660 rtl8723au_write32(Adapter, REG_EDCA_BE_PARAM,
1661 pHalData->AcParam_BE);
1662 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = false;
1663 }
1664 }
1665
1666 dm_CheckEdcaTurbo_EXIT:
1667 /* Set variables for next time. */
1668 precvpriv->bIsAnyNonBEPkts = false;
1669 pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes;
1670 precvpriv->last_rx_bytes = precvpriv->rx_bytes;
1671 }
1672
1673 u32 GetPSDData(struct dm_odm_t *pDM_Odm, unsigned int point, u8 initial_gain_psd)
1674 {
1675 u32 psd_report;
1676
1677 /* Set DCO frequency index, offset = (40MHz/SamplePts)*point */
1678 ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point);
1679
1680 /* Start PSD calculation, Reg808[22]= 0->1 */
1681 ODM_SetBBReg(pDM_Odm, 0x808, BIT(22), 1);
1682 /* Need to wait for HW PSD report */
1683 udelay(30);
1684 ODM_SetBBReg(pDM_Odm, 0x808, BIT(22), 0);
1685 /* Read PSD report, Reg8B4[15:0] */
1686 psd_report = ODM_GetBBReg(pDM_Odm, 0x8B4, bMaskDWord) & 0x0000FFFF;
1687
1688 psd_report = (u32)(ConvertTo_dB23a(psd_report))+(u32)(initial_gain_psd-0x1c);
1689
1690 return psd_report;
1691 }
1692
1693 u32
1694 ConvertTo_dB23a(
1695 u32 Value)
1696 {
1697 u8 i;
1698 u8 j;
1699 u32 dB;
1700
1701 Value = Value & 0xFFFF;
1702
1703 for (i = 0; i < 8; i++) {
1704 if (Value <= dB_Invert_Table[i][11])
1705 break;
1706 }
1707
1708 if (i >= 8)
1709 return 96; /* maximum 96 dB */
1710
1711 for (j = 0; j < 12; j++) {
1712 if (Value <= dB_Invert_Table[i][j])
1713 break;
1714 }
1715
1716 dB = i*12 + j + 1;
1717
1718 return dB;
1719 }
1720
1721 /* */
1722 /* Description: */
1723 /*Set Single/Dual Antenna default setting for products that do not do detection in advance. */
1724 /* */
1725 /* Added by Joseph, 2012.03.22 */
1726 /* */
1727 void ODM_SingleDualAntennaDefaultSetting(struct dm_odm_t *pDM_Odm)
1728 {
1729 struct sw_ant_sw *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
1730 pDM_SWAT_Table->ANTA_ON = true;
1731 pDM_SWAT_Table->ANTB_ON = true;
1732 }
1733
1734 /* 2 8723A ANT DETECT */
1735
1736 static void odm_PHY_SaveAFERegisters(
1737 struct dm_odm_t *pDM_Odm,
1738 u32 *AFEReg,
1739 u32 *AFEBackup,
1740 u32 RegisterNum
1741 )
1742 {
1743 u32 i;
1744
1745 /* RTPRINT(FINIT, INIT_IQK, ("Save ADDA parameters.\n")); */
1746 for (i = 0 ; i < RegisterNum ; i++)
1747 AFEBackup[i] = ODM_GetBBReg(pDM_Odm, AFEReg[i], bMaskDWord);
1748 }
1749
1750 static void odm_PHY_ReloadAFERegisters(struct dm_odm_t *pDM_Odm, u32 *AFEReg,
1751 u32 *AFEBackup, u32 RegiesterNum)
1752 {
1753 u32 i;
1754
1755 for (i = 0 ; i < RegiesterNum; i++)
1756 ODM_SetBBReg(pDM_Odm, AFEReg[i], bMaskDWord, AFEBackup[i]);
1757 }
1758
1759 /* 2 8723A ANT DETECT */
1760 /* Description: */
1761 /* Implement IQK single tone for RF DPK loopback and BB PSD scanning. */
1762 /* This function is cooperated with BB team Neil. */
1763 bool ODM_SingleDualAntennaDetection(struct dm_odm_t *pDM_Odm, u8 mode)
1764 {
1765 struct sw_ant_sw *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
1766 u32 CurrentChannel, RfLoopReg;
1767 u8 n;
1768 u32 Reg88c, Regc08, Reg874, Regc50;
1769 u8 initial_gain = 0x5a;
1770 u32 PSD_report_tmp;
1771 u32 AntA_report = 0x0, AntB_report = 0x0, AntO_report = 0x0;
1772 bool bResult = true;
1773 u32 AFE_Backup[16];
1774 u32 AFE_REG_8723A[16] = {
1775 rRx_Wait_CCA, rTx_CCK_RFON,
1776 rTx_CCK_BBON, rTx_OFDM_RFON,
1777 rTx_OFDM_BBON, rTx_To_Rx,
1778 rTx_To_Tx, rRx_CCK,
1779 rRx_OFDM, rRx_Wait_RIFS,
1780 rRx_TO_Rx, rStandby,
1781 rSleep, rPMPD_ANAEN,
1782 rFPGA0_XCD_SwitchControl, rBlue_Tooth};
1783
1784 if (!(pDM_Odm->SupportICType & ODM_RTL8723A))
1785 return bResult;
1786
1787 if (!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV))
1788 return bResult;
1789 /* 1 Backup Current RF/BB Settings */
1790
1791 CurrentChannel = ODM_GetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask);
1792 RfLoopReg = ODM_GetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask);
1793 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, ODM_DPDT, Antenna_A); /* change to Antenna A */
1794 /* Step 1: USE IQK to transmitter single tone */
1795
1796 udelay(10);
1797
1798 /* Store A Path Register 88c, c08, 874, c50 */
1799 Reg88c = ODM_GetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord);
1800 Regc08 = ODM_GetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord);
1801 Reg874 = ODM_GetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord);
1802 Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord);
1803
1804 /* Store AFE Registers */
1805 odm_PHY_SaveAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
1806
1807 /* Set PSD 128 pts */
1808 ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT(14) | BIT(15), 0x0);
1809
1810 /* To SET CH1 to do */
1811 ODM_SetRFReg(pDM_Odm, RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x01); /* Channel 1 */
1812
1813 /* AFE all on step */
1814 ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, 0x6FDB25A4);
1815 ODM_SetBBReg(pDM_Odm, rTx_CCK_RFON, bMaskDWord, 0x6FDB25A4);
1816 ODM_SetBBReg(pDM_Odm, rTx_CCK_BBON, bMaskDWord, 0x6FDB25A4);
1817 ODM_SetBBReg(pDM_Odm, rTx_OFDM_RFON, bMaskDWord, 0x6FDB25A4);
1818 ODM_SetBBReg(pDM_Odm, rTx_OFDM_BBON, bMaskDWord, 0x6FDB25A4);
1819 ODM_SetBBReg(pDM_Odm, rTx_To_Rx, bMaskDWord, 0x6FDB25A4);
1820 ODM_SetBBReg(pDM_Odm, rTx_To_Tx, bMaskDWord, 0x6FDB25A4);
1821 ODM_SetBBReg(pDM_Odm, rRx_CCK, bMaskDWord, 0x6FDB25A4);
1822 ODM_SetBBReg(pDM_Odm, rRx_OFDM, bMaskDWord, 0x6FDB25A4);
1823 ODM_SetBBReg(pDM_Odm, rRx_Wait_RIFS, bMaskDWord, 0x6FDB25A4);
1824 ODM_SetBBReg(pDM_Odm, rRx_TO_Rx, bMaskDWord, 0x6FDB25A4);
1825 ODM_SetBBReg(pDM_Odm, rStandby, bMaskDWord, 0x6FDB25A4);
1826 ODM_SetBBReg(pDM_Odm, rSleep, bMaskDWord, 0x6FDB25A4);
1827 ODM_SetBBReg(pDM_Odm, rPMPD_ANAEN, bMaskDWord, 0x6FDB25A4);
1828 ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_SwitchControl, bMaskDWord, 0x6FDB25A4);
1829 ODM_SetBBReg(pDM_Odm, rBlue_Tooth, bMaskDWord, 0x6FDB25A4);
1830
1831 /* 3 wire Disable */
1832 ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, 0xCCF000C0);
1833
1834 /* BB IQK Setting */
1835 ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800E4);
1836 ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22208000);
1837
1838 /* IQK setting tone@ 4.34Mhz */
1839 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008C1C);
1840 ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
1841
1842 /* Page B init */
1843 ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00080000);
1844 ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000);
1845 ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);
1846 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
1847 ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82150008);
1848 ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28150008);
1849 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0);
1850
1851 /* RF loop Setting */
1852 ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x0, 0xFFFFF, 0x50008);
1853
1854 /* IQK Single tone start */
1855 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000);
1856 ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
1857 udelay(1000);
1858 PSD_report_tmp = 0x0;
1859
1860 for (n = 0; n < 2; n++) {
1861 PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain);
1862 if (PSD_report_tmp > AntA_report)
1863 AntA_report = PSD_report_tmp;
1864 }
1865
1866 PSD_report_tmp = 0x0;
1867
1868 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B); /* change to Antenna B */
1869 udelay(10);
1870
1871 for (n = 0; n < 2; n++) {
1872 PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain);
1873 if (PSD_report_tmp > AntB_report)
1874 AntB_report = PSD_report_tmp;
1875 }
1876
1877 /* change to open case */
1878 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, 0); /* change to Ant A and B all open case */
1879 udelay(10);
1880
1881 for (n = 0; n < 2; n++) {
1882 PSD_report_tmp = GetPSDData(pDM_Odm, 14, initial_gain);
1883 if (PSD_report_tmp > AntO_report)
1884 AntO_report = PSD_report_tmp;
1885 }
1886
1887 /* Close IQK Single Tone function */
1888 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
1889 PSD_report_tmp = 0x0;
1890
1891 /* 1 Return to antanna A */
1892 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A);
1893 ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, Reg88c);
1894 ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, Regc08);
1895 ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, Reg874);
1896 ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7F, 0x40);
1897 ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord, Regc50);
1898 ODM_SetRFReg(pDM_Odm, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel);
1899 ODM_SetRFReg(pDM_Odm, RF_PATH_A, 0x00, bRFRegOffsetMask, RfLoopReg);
1900
1901 /* Reload AFE Registers */
1902 odm_PHY_ReloadAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
1903
1904 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d \n", 2416, AntA_report));
1905 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d \n", 2416, AntB_report));
1906 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_O[%d]= %d \n", 2416, AntO_report));
1907
1908 /* 2 Test Ant B based on Ant A is ON */
1909 if (mode == ANTTESTB) {
1910 if (AntA_report >= 100) {
1911 if (AntB_report > (AntA_report+1)) {
1912 pDM_SWAT_Table->ANTB_ON = false;
1913 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n"));
1914 } else {
1915 pDM_SWAT_Table->ANTB_ON = true;
1916 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Dual Antenna is A and B\n"));
1917 }
1918 } else {
1919 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
1920 pDM_SWAT_Table->ANTB_ON = false; /* Set Antenna B off as default */
1921 bResult = false;
1922 }
1923 } else if (mode == ANTTESTALL) {
1924 /* 2 Test Ant A and B based on DPDT Open */
1925 if ((AntO_report >= 100) & (AntO_report < 118)) {
1926 if (AntA_report > (AntO_report+1)) {
1927 pDM_SWAT_Table->ANTA_ON = false;
1928 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant A is OFF"));
1929 } else {
1930 pDM_SWAT_Table->ANTA_ON = true;
1931 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant A is ON"));
1932 }
1933
1934 if (AntB_report > (AntO_report+2)) {
1935 pDM_SWAT_Table->ANTB_ON = false;
1936 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant B is OFF"));
1937 } else {
1938 pDM_SWAT_Table->ANTB_ON = true;
1939 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ant B is ON"));
1940 }
1941 }
1942 } else {
1943 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
1944 pDM_SWAT_Table->ANTA_ON = true; /* Set Antenna A on as default */
1945 pDM_SWAT_Table->ANTB_ON = false; /* Set Antenna B off as default */
1946 bResult = false;
1947 }
1948 return bResult;
1949 }
1950
1951 /* Justin: According to the current RRSI to adjust Response Frame TX power, 2012/11/05 */
1952 void odm_dtc(struct dm_odm_t *pDM_Odm)
1953 {
1954 }
Linux kernel - Deliverables
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