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staging: rtl8723au: Remove RegBcnCtrlVal
[deliverable/linux.git] / drivers / staging / rtl8723au / hal / rtl8723a_hal_init.c
1 /******************************************************************************
2 *
3 * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 ******************************************************************************/
15 #define _HAL_INIT_C_
16
17 #include <linux/firmware.h>
18 #include <drv_types.h>
19 #include <rtw_efuse.h>
20
21 #include <rtl8723a_hal.h>
22 #include <usb_ops_linux.h>
23
24 static void _FWDownloadEnable(struct rtw_adapter *padapter, bool enable)
25 {
26 u8 tmp;
27
28 if (enable) {
29 /* 8051 enable */
30 tmp = rtl8723au_read8(padapter, REG_SYS_FUNC_EN + 1);
31 rtl8723au_write8(padapter, REG_SYS_FUNC_EN + 1, tmp | 0x04);
32
33 /* MCU firmware download enable. */
34 tmp = rtl8723au_read8(padapter, REG_MCUFWDL);
35 rtl8723au_write8(padapter, REG_MCUFWDL, tmp | 0x01);
36
37 /* 8051 reset */
38 tmp = rtl8723au_read8(padapter, REG_MCUFWDL + 2);
39 rtl8723au_write8(padapter, REG_MCUFWDL + 2, tmp & 0xf7);
40 } else {
41 /* MCU firmware download disable. */
42 tmp = rtl8723au_read8(padapter, REG_MCUFWDL);
43 rtl8723au_write8(padapter, REG_MCUFWDL, tmp & 0xfe);
44
45 /* Reserved for fw extension. */
46 rtl8723au_write8(padapter, REG_MCUFWDL + 1, 0x00);
47 }
48 }
49
50 static int _BlockWrite(struct rtw_adapter *padapter, void *buffer, u32 buffSize)
51 {
52 int ret;
53
54 if (buffSize > MAX_PAGE_SIZE)
55 return _FAIL;
56
57 ret = rtl8723au_writeN(padapter, FW_8723A_START_ADDRESS,
58 buffSize, buffer);
59
60 return ret;
61 }
62
63 static int
64 _PageWrite(struct rtw_adapter *padapter, u32 page, void *buffer, u32 size)
65 {
66 u8 value8;
67 u8 u8Page = (u8) (page & 0x07);
68
69 value8 = (rtl8723au_read8(padapter, REG_MCUFWDL + 2) & 0xF8) | u8Page;
70 rtl8723au_write8(padapter, REG_MCUFWDL + 2, value8);
71
72 return _BlockWrite(padapter, buffer, size);
73 }
74
75 static int _WriteFW(struct rtw_adapter *padapter, void *buffer, u32 size)
76 {
77 /* Since we need dynamic decide method of dwonload fw, so we
78 call this function to get chip version. */
79 /* We can remove _ReadChipVersion from ReadpadapterInfo8192C later. */
80 int ret = _SUCCESS;
81 u32 pageNums, remainSize;
82 u32 page, offset;
83 u8 *bufferPtr = (u8 *) buffer;
84
85 pageNums = size / MAX_PAGE_SIZE;
86 /* RT_ASSERT((pageNums <= 4),
87 ("Page numbers should not greater then 4 \n")); */
88 remainSize = size % MAX_PAGE_SIZE;
89
90 for (page = 0; page < pageNums; page++) {
91 offset = page * MAX_PAGE_SIZE;
92 ret = _PageWrite(padapter, page, bufferPtr + offset,
93 MAX_PAGE_SIZE);
94
95 if (ret == _FAIL)
96 goto exit;
97 }
98 if (remainSize) {
99 offset = pageNums * MAX_PAGE_SIZE;
100 page = pageNums;
101 ret = _PageWrite(padapter, page, bufferPtr + offset,
102 remainSize);
103
104 if (ret == _FAIL)
105 goto exit;
106 }
107 RT_TRACE(_module_hal_init_c_, _drv_info_,
108 ("_WriteFW Done- for Normal chip.\n"));
109
110 exit:
111 return ret;
112 }
113
114 static int _FWFreeToGo(struct rtw_adapter *padapter)
115 {
116 u32 counter = 0;
117 u32 value32;
118
119 /* polling CheckSum report */
120 do {
121 value32 = rtl8723au_read32(padapter, REG_MCUFWDL);
122 if (value32 & FWDL_ChkSum_rpt)
123 break;
124 } while (counter++ < POLLING_READY_TIMEOUT_COUNT);
125
126 if (counter >= POLLING_READY_TIMEOUT_COUNT) {
127 RT_TRACE(_module_hal_init_c_, _drv_err_,
128 ("%s: chksum report fail! REG_MCUFWDL:0x%08x\n",
129 __func__, value32));
130 return _FAIL;
131 }
132 RT_TRACE(_module_hal_init_c_, _drv_info_,
133 ("%s: Checksum report OK! REG_MCUFWDL:0x%08x\n", __func__,
134 value32));
135
136 value32 = rtl8723au_read32(padapter, REG_MCUFWDL);
137 value32 |= MCUFWDL_RDY;
138 value32 &= ~WINTINI_RDY;
139 rtl8723au_write32(padapter, REG_MCUFWDL, value32);
140
141 /* polling for FW ready */
142 counter = 0;
143 do {
144 value32 = rtl8723au_read32(padapter, REG_MCUFWDL);
145 if (value32 & WINTINI_RDY) {
146 RT_TRACE(_module_hal_init_c_, _drv_info_,
147 ("%s: Polling FW ready success!! "
148 "REG_MCUFWDL:0x%08x\n",
149 __func__, value32));
150 return _SUCCESS;
151 }
152 udelay(5);
153 } while (counter++ < POLLING_READY_TIMEOUT_COUNT);
154
155 RT_TRACE(_module_hal_init_c_, _drv_err_,
156 ("%s: Polling FW ready fail!! REG_MCUFWDL:0x%08x\n",
157 __func__, value32));
158 return _FAIL;
159 }
160
161 #define IS_FW_81xxC(padapter) (((GET_HAL_DATA(padapter))->FirmwareSignature & 0xFFF0) == 0x88C0)
162
163 void rtl8723a_FirmwareSelfReset(struct rtw_adapter *padapter)
164 {
165 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
166 u8 u1bTmp;
167 u8 Delay = 100;
168
169 if (!(IS_FW_81xxC(padapter) &&
170 ((pHalData->FirmwareVersion < 0x21) ||
171 (pHalData->FirmwareVersion == 0x21 &&
172 pHalData->FirmwareSubVersion < 0x01)))) {
173 /* after 88C Fw v33.1 */
174 /* 0x1cf = 0x20. Inform 8051 to reset. 2009.12.25. tynli_test */
175 rtl8723au_write8(padapter, REG_HMETFR + 3, 0x20);
176
177 u1bTmp = rtl8723au_read8(padapter, REG_SYS_FUNC_EN + 1);
178 while (u1bTmp & BIT(2)) {
179 Delay--;
180 if (Delay == 0)
181 break;
182 udelay(50);
183 u1bTmp = rtl8723au_read8(padapter, REG_SYS_FUNC_EN + 1);
184 }
185 RT_TRACE(_module_hal_init_c_, _drv_info_,
186 ("-%s: 8051 reset success (%d)\n", __func__,
187 Delay));
188
189 if ((Delay == 0)) {
190 /* force firmware reset */
191 u1bTmp = rtl8723au_read8(padapter, REG_SYS_FUNC_EN + 1);
192 rtl8723au_write8(padapter, REG_SYS_FUNC_EN + 1,
193 u1bTmp & ~BIT(2));
194 }
195 }
196 }
197
198 /* */
199 /* Description: */
200 /* Download 8192C firmware code. */
201 /* */
202 /* */
203 int rtl8723a_FirmwareDownload(struct rtw_adapter *padapter)
204 {
205 int rtStatus = _SUCCESS;
206 u8 writeFW_retry = 0;
207 unsigned long fwdl_start_time;
208 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
209 struct dvobj_priv *dvobj = adapter_to_dvobj(padapter);
210 struct device *device = dvobj_to_dev(dvobj);
211 struct rt_8723a_firmware_hdr *pFwHdr = NULL;
212 const struct firmware *fw;
213 char *fw_name;
214 u8 *firmware_buf = NULL;
215 u8 *buf;
216 int fw_size;
217 static int log_version;
218
219 RT_TRACE(_module_hal_init_c_, _drv_info_, ("+%s\n", __func__));
220
221 if (IS_8723A_A_CUT(pHalData->VersionID)) {
222 fw_name = "rtlwifi/rtl8723aufw_A.bin";
223 RT_TRACE(_module_hal_init_c_, _drv_info_,
224 ("rtl8723a_FirmwareDownload: R8723FwImageArray_UMC "
225 "for RTL8723A A CUT\n"));
226 } else if (IS_8723A_B_CUT(pHalData->VersionID)) {
227 /* WLAN Fw. */
228 if (padapter->registrypriv.wifi_spec == 1) {
229 fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
230 DBG_8723A(" Rtl8723_FwUMCBCutImageArrayWithoutBT for "
231 "RTL8723A B CUT\n");
232 } else {
233 if (rtl8723a_BT_coexist(padapter)) {
234 fw_name = "rtlwifi/rtl8723aufw_B.bin";
235 DBG_8723A(" Rtl8723_FwUMCBCutImageArrayWithBT "
236 "for RTL8723A B CUT\n");
237 } else {
238 fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
239 DBG_8723A(" Rtl8723_FwUMCBCutImageArrayWithout "
240 "BT for RTL8723A B CUT\n");
241 }
242 }
243 } else {
244 /* <Roger_TODO> We should download proper RAM Code here
245 to match the ROM code. */
246 RT_TRACE(_module_hal_init_c_, _drv_err_,
247 ("%s: unknow version!\n", __func__));
248 rtStatus = _FAIL;
249 goto Exit;
250 }
251
252 pr_info("rtl8723au: Loading firmware %s\n", fw_name);
253 if (request_firmware(&fw, fw_name, device)) {
254 pr_err("rtl8723au: request_firmware load failed\n");
255 rtStatus = _FAIL;
256 goto Exit;
257 }
258 if (!fw) {
259 pr_err("rtl8723au: Firmware %s not available\n", fw_name);
260 rtStatus = _FAIL;
261 goto Exit;
262 }
263 firmware_buf = kmemdup(fw->data, fw->size, GFP_KERNEL);
264 if (!firmware_buf) {
265 rtStatus = _FAIL;
266 goto Exit;
267 }
268 buf = firmware_buf;
269 fw_size = fw->size;
270 release_firmware(fw);
271
272 /* To Check Fw header. Added by tynli. 2009.12.04. */
273 pFwHdr = (struct rt_8723a_firmware_hdr *)firmware_buf;
274
275 pHalData->FirmwareVersion = le16_to_cpu(pFwHdr->Version);
276 pHalData->FirmwareSubVersion = pFwHdr->Subversion;
277 pHalData->FirmwareSignature = le16_to_cpu(pFwHdr->Signature);
278
279 DBG_8723A("%s: fw_ver =%d fw_subver =%d sig = 0x%x\n",
280 __func__, pHalData->FirmwareVersion,
281 pHalData->FirmwareSubVersion, pHalData->FirmwareSignature);
282
283 if (!log_version++)
284 pr_info("%sFirmware Version %d, SubVersion %d, Signature "
285 "0x%x\n", DRIVER_PREFIX, pHalData->FirmwareVersion,
286 pHalData->FirmwareSubVersion,
287 pHalData->FirmwareSignature);
288
289 if (IS_FW_HEADER_EXIST(pFwHdr)) {
290 /* Shift 32 bytes for FW header */
291 buf = buf + 32;
292 fw_size = fw_size - 32;
293 }
294
295 /* Suggested by Filen. If 8051 is running in RAM code, driver should
296 inform Fw to reset by itself, */
297 /* or it will cause download Fw fail. 2010.02.01. by tynli. */
298 if (rtl8723au_read8(padapter, REG_MCUFWDL) & RAM_DL_SEL) {
299 /* 8051 RAM code */
300 rtl8723a_FirmwareSelfReset(padapter);
301 rtl8723au_write8(padapter, REG_MCUFWDL, 0x00);
302 }
303
304 _FWDownloadEnable(padapter, true);
305 fwdl_start_time = jiffies;
306 while (1) {
307 /* reset the FWDL chksum */
308 rtl8723au_write8(padapter, REG_MCUFWDL,
309 rtl8723au_read8(padapter, REG_MCUFWDL) |
310 FWDL_ChkSum_rpt);
311
312 rtStatus = _WriteFW(padapter, buf, fw_size);
313
314 if (rtStatus == _SUCCESS ||
315 (jiffies_to_msecs(jiffies - fwdl_start_time) > 500 &&
316 writeFW_retry++ >= 3))
317 break;
318
319 DBG_8723A("%s writeFW_retry:%u, time after fwdl_start_time:"
320 "%ums\n", __func__, writeFW_retry,
321 jiffies_to_msecs(jiffies - fwdl_start_time));
322 }
323 _FWDownloadEnable(padapter, false);
324 if (_SUCCESS != rtStatus) {
325 DBG_8723A("DL Firmware failed!\n");
326 goto Exit;
327 }
328
329 rtStatus = _FWFreeToGo(padapter);
330 if (_SUCCESS != rtStatus) {
331 RT_TRACE(_module_hal_init_c_, _drv_err_,
332 ("DL Firmware failed!\n"));
333 goto Exit;
334 }
335 RT_TRACE(_module_hal_init_c_, _drv_info_,
336 ("Firmware is ready to run!\n"));
337
338 Exit:
339 kfree(firmware_buf);
340 return rtStatus;
341 }
342
343 void rtl8723a_InitializeFirmwareVars(struct rtw_adapter *padapter)
344 {
345 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
346
347 /* Init Fw LPS related. */
348 padapter->pwrctrlpriv.bFwCurrentInPSMode = false;
349
350 /* Init H2C counter. by tynli. 2009.12.09. */
351 pHalData->LastHMEBoxNum = 0;
352 }
353
354 /* */
355 /* Efuse related code */
356 /* */
357 static u8
358 hal_EfuseSwitchToBank(struct rtw_adapter *padapter, u8 bank)
359 {
360 u8 bRet = false;
361 u32 value32 = 0;
362
363 DBG_8723A("%s: Efuse switch bank to %d\n", __func__, bank);
364 value32 = rtl8723au_read32(padapter, EFUSE_TEST);
365 bRet = true;
366 switch (bank) {
367 case 0:
368 value32 = (value32 & ~EFUSE_SEL_MASK) |
369 EFUSE_SEL(EFUSE_WIFI_SEL_0);
370 break;
371 case 1:
372 value32 = (value32 & ~EFUSE_SEL_MASK) |
373 EFUSE_SEL(EFUSE_BT_SEL_0);
374 break;
375 case 2:
376 value32 = (value32 & ~EFUSE_SEL_MASK) |
377 EFUSE_SEL(EFUSE_BT_SEL_1);
378 break;
379 case 3:
380 value32 = (value32 & ~EFUSE_SEL_MASK) |
381 EFUSE_SEL(EFUSE_BT_SEL_2);
382 break;
383 default:
384 value32 = (value32 & ~EFUSE_SEL_MASK) |
385 EFUSE_SEL(EFUSE_WIFI_SEL_0);
386 bRet = false;
387 break;
388 }
389 rtl8723au_write32(padapter, EFUSE_TEST, value32);
390
391 return bRet;
392 }
393
394 static void
395 hal_ReadEFuse_WiFi(struct rtw_adapter *padapter,
396 u16 _offset, u16 _size_byte, u8 *pbuf)
397 {
398 u8 *efuseTbl = NULL;
399 u16 eFuse_Addr = 0;
400 u8 offset, wden;
401 u8 efuseHeader, efuseExtHdr, efuseData;
402 u16 i, total, used;
403 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
404
405 /* Do NOT excess total size of EFuse table.
406 Added by Roger, 2008.11.10. */
407 if ((_offset + _size_byte) > EFUSE_MAP_LEN_8723A) {
408 DBG_8723A("%s: Invalid offset(%#x) with read bytes(%#x)!!\n",
409 __func__, _offset, _size_byte);
410 return;
411 }
412
413 efuseTbl = kmalloc(EFUSE_MAP_LEN_8723A, GFP_KERNEL);
414 if (efuseTbl == NULL) {
415 DBG_8723A("%s: alloc efuseTbl fail!\n", __func__);
416 return;
417 }
418 /* 0xff will be efuse default value instead of 0x00. */
419 memset(efuseTbl, 0xFF, EFUSE_MAP_LEN_8723A);
420
421 /* switch bank back to bank 0 for later BT and wifi use. */
422 hal_EfuseSwitchToBank(padapter, 0);
423
424 while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) {
425 ReadEFuseByte23a(padapter, eFuse_Addr++, &efuseHeader);
426 if (efuseHeader == 0xFF) {
427 DBG_8723A("%s: data end at address =%#x\n", __func__,
428 eFuse_Addr);
429 break;
430 }
431
432 /* Check PG header for section num. */
433 if (EXT_HEADER(efuseHeader)) { /* extended header */
434 offset = GET_HDR_OFFSET_2_0(efuseHeader);
435
436 ReadEFuseByte23a(padapter, eFuse_Addr++, &efuseExtHdr);
437 if (ALL_WORDS_DISABLED(efuseExtHdr)) {
438 continue;
439 }
440
441 offset |= ((efuseExtHdr & 0xF0) >> 1);
442 wden = (efuseExtHdr & 0x0F);
443 } else {
444 offset = ((efuseHeader >> 4) & 0x0f);
445 wden = (efuseHeader & 0x0f);
446 }
447
448 if (offset < EFUSE_MAX_SECTION_8723A) {
449 u16 addr;
450 /* Get word enable value from PG header */
451
452 addr = offset * PGPKT_DATA_SIZE;
453 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
454 /* Check word enable condition in the section */
455 if (!(wden & (0x01 << i))) {
456 ReadEFuseByte23a(padapter, eFuse_Addr++,
457 &efuseData);
458 efuseTbl[addr] = efuseData;
459
460 ReadEFuseByte23a(padapter, eFuse_Addr++,
461 &efuseData);
462 efuseTbl[addr + 1] = efuseData;
463 }
464 addr += 2;
465 }
466 } else {
467 DBG_8723A(KERN_ERR "%s: offset(%d) is illegal!!\n",
468 __func__, offset);
469 eFuse_Addr += Efuse_CalculateWordCnts23a(wden) * 2;
470 }
471 }
472
473 /* Copy from Efuse map to output pointer memory!!! */
474 for (i = 0; i < _size_byte; i++)
475 pbuf[i] = efuseTbl[_offset + i];
476
477 /* Calculate Efuse utilization */
478 EFUSE_GetEfuseDefinition23a(padapter, EFUSE_WIFI,
479 TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total);
480 used = eFuse_Addr - 1;
481 pHalData->EfuseUsedBytes = used;
482
483 kfree(efuseTbl);
484 }
485
486 static void
487 hal_ReadEFuse_BT(struct rtw_adapter *padapter,
488 u16 _offset, u16 _size_byte, u8 *pbuf)
489 {
490 u8 *efuseTbl;
491 u8 bank;
492 u16 eFuse_Addr;
493 u8 efuseHeader, efuseExtHdr, efuseData;
494 u8 offset, wden;
495 u16 i, total, used;
496 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
497
498 /* Do NOT excess total size of EFuse table.
499 Added by Roger, 2008.11.10. */
500 if ((_offset + _size_byte) > EFUSE_BT_MAP_LEN) {
501 DBG_8723A("%s: Invalid offset(%#x) with read bytes(%#x)!!\n",
502 __func__, _offset, _size_byte);
503 return;
504 }
505
506 efuseTbl = kmalloc(EFUSE_BT_MAP_LEN, GFP_KERNEL);
507 if (efuseTbl == NULL) {
508 DBG_8723A("%s: efuseTbl malloc fail!\n", __func__);
509 return;
510 }
511 /* 0xff will be efuse default value instead of 0x00. */
512 memset(efuseTbl, 0xFF, EFUSE_BT_MAP_LEN);
513
514 EFUSE_GetEfuseDefinition23a(padapter, EFUSE_BT,
515 TYPE_AVAILABLE_EFUSE_BYTES_BANK, &total);
516
517 for (bank = 1; bank < EFUSE_MAX_BANK; bank++) {
518 if (hal_EfuseSwitchToBank(padapter, bank) == false) {
519 DBG_8723A("%s: hal_EfuseSwitchToBank Fail!!\n",
520 __func__);
521 goto exit;
522 }
523
524 eFuse_Addr = 0;
525
526 while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) {
527 ReadEFuseByte23a(padapter, eFuse_Addr++, &efuseHeader);
528 if (efuseHeader == 0xFF)
529 break;
530
531 /* Check PG header for section num. */
532 if (EXT_HEADER(efuseHeader)) { /* extended header */
533 offset = GET_HDR_OFFSET_2_0(efuseHeader);
534
535 ReadEFuseByte23a(padapter, eFuse_Addr++,
536 &efuseExtHdr);
537 if (ALL_WORDS_DISABLED(efuseExtHdr)) {
538 continue;
539 }
540
541 offset |= ((efuseExtHdr & 0xF0) >> 1);
542 wden = (efuseExtHdr & 0x0F);
543 } else {
544 offset = ((efuseHeader >> 4) & 0x0f);
545 wden = (efuseHeader & 0x0f);
546 }
547
548 if (offset < EFUSE_BT_MAX_SECTION) {
549 u16 addr;
550
551 /* Get word enable value from PG header */
552
553 addr = offset * PGPKT_DATA_SIZE;
554 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
555 /* Check word enable condition in
556 the section */
557 if (!(wden & (0x01 << i))) {
558 ReadEFuseByte23a(padapter,
559 eFuse_Addr++,
560 &efuseData);
561 efuseTbl[addr] = efuseData;
562
563 ReadEFuseByte23a(padapter,
564 eFuse_Addr++,
565 &efuseData);
566 efuseTbl[addr + 1] = efuseData;
567 }
568 addr += 2;
569 }
570 } else {
571 DBG_8723A(KERN_ERR
572 "%s: offset(%d) is illegal!!\n",
573 __func__, offset);
574 eFuse_Addr += Efuse_CalculateWordCnts23a(wden) * 2;
575 }
576 }
577
578 if ((eFuse_Addr - 1) < total) {
579 DBG_8723A("%s: bank(%d) data end at %#x\n",
580 __func__, bank, eFuse_Addr - 1);
581 break;
582 }
583 }
584
585 /* switch bank back to bank 0 for later BT and wifi use. */
586 hal_EfuseSwitchToBank(padapter, 0);
587
588 /* Copy from Efuse map to output pointer memory!!! */
589 for (i = 0; i < _size_byte; i++)
590 pbuf[i] = efuseTbl[_offset + i];
591
592 /* */
593 /* Calculate Efuse utilization. */
594 /* */
595 EFUSE_GetEfuseDefinition23a(padapter, EFUSE_BT,
596 TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total);
597 used = (EFUSE_BT_REAL_BANK_CONTENT_LEN * (bank - 1)) + eFuse_Addr - 1;
598 pHalData->BTEfuseUsedBytes = used;
599
600 exit:
601 kfree(efuseTbl);
602 }
603
604 void
605 rtl8723a_readefuse(struct rtw_adapter *padapter,
606 u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf)
607 {
608 if (efuseType == EFUSE_WIFI)
609 hal_ReadEFuse_WiFi(padapter, _offset, _size_byte, pbuf);
610 else
611 hal_ReadEFuse_BT(padapter, _offset, _size_byte, pbuf);
612 }
613
614 u16 rtl8723a_EfuseGetCurrentSize_WiFi(struct rtw_adapter *padapter)
615 {
616 u16 efuse_addr = 0;
617 u8 hoffset = 0, hworden = 0;
618 u8 efuse_data, word_cnts = 0;
619 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
620
621 efuse_addr = pHalData->EfuseUsedBytes;
622
623 DBG_8723A("%s: start_efuse_addr = 0x%X\n", __func__, efuse_addr);
624
625 /* switch bank back to bank 0 for later BT and wifi use. */
626 hal_EfuseSwitchToBank(padapter, 0);
627
628 while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
629 if (efuse_OneByteRead23a(padapter, efuse_addr, &efuse_data) ==
630 _FAIL) {
631 DBG_8723A(KERN_ERR "%s: efuse_OneByteRead23a Fail! "
632 "addr = 0x%X !!\n", __func__, efuse_addr);
633 break;
634 }
635
636 if (efuse_data == 0xFF)
637 break;
638
639 if (EXT_HEADER(efuse_data)) {
640 hoffset = GET_HDR_OFFSET_2_0(efuse_data);
641 efuse_addr++;
642 efuse_OneByteRead23a(padapter, efuse_addr, &efuse_data);
643 if (ALL_WORDS_DISABLED(efuse_data)) {
644 continue;
645 }
646
647 hoffset |= ((efuse_data & 0xF0) >> 1);
648 hworden = efuse_data & 0x0F;
649 } else {
650 hoffset = (efuse_data >> 4) & 0x0F;
651 hworden = efuse_data & 0x0F;
652 }
653
654 word_cnts = Efuse_CalculateWordCnts23a(hworden);
655 efuse_addr += (word_cnts * 2) + 1;
656 }
657
658 pHalData->EfuseUsedBytes = efuse_addr;
659
660 DBG_8723A("%s: CurrentSize =%d\n", __func__, efuse_addr);
661
662 return efuse_addr;
663 }
664
665 u16 rtl8723a_EfuseGetCurrentSize_BT(struct rtw_adapter *padapter)
666 {
667 u16 btusedbytes;
668 u16 efuse_addr;
669 u8 bank, startBank;
670 u8 hoffset = 0, hworden = 0;
671 u8 efuse_data, word_cnts = 0;
672 u16 retU2 = 0;
673 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
674
675 btusedbytes = pHalData->BTEfuseUsedBytes;
676
677 efuse_addr = (u16) ((btusedbytes % EFUSE_BT_REAL_BANK_CONTENT_LEN));
678 startBank = (u8) (1 + (btusedbytes / EFUSE_BT_REAL_BANK_CONTENT_LEN));
679
680 DBG_8723A("%s: start from bank =%d addr = 0x%X\n", __func__, startBank,
681 efuse_addr);
682
683 EFUSE_GetEfuseDefinition23a(padapter, EFUSE_BT,
684 TYPE_AVAILABLE_EFUSE_BYTES_BANK, &retU2);
685
686 for (bank = startBank; bank < EFUSE_MAX_BANK; bank++) {
687 if (hal_EfuseSwitchToBank(padapter, bank) == false) {
688 DBG_8723A(KERN_ERR "%s: switch bank(%d) Fail!!\n",
689 __func__, bank);
690 bank = EFUSE_MAX_BANK;
691 break;
692 }
693
694 /* only when bank is switched we have to reset
695 the efuse_addr. */
696 if (bank != startBank)
697 efuse_addr = 0;
698
699 while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
700 if (efuse_OneByteRead23a(padapter, efuse_addr,
701 &efuse_data) == _FAIL) {
702 DBG_8723A(KERN_ERR "%s: efuse_OneByteRead23a Fail!"
703 " addr = 0x%X !!\n",
704 __func__, efuse_addr);
705 bank = EFUSE_MAX_BANK;
706 break;
707 }
708
709 if (efuse_data == 0xFF)
710 break;
711
712 if (EXT_HEADER(efuse_data)) {
713 hoffset = GET_HDR_OFFSET_2_0(efuse_data);
714 efuse_addr++;
715 efuse_OneByteRead23a(padapter, efuse_addr,
716 &efuse_data);
717 if (ALL_WORDS_DISABLED(efuse_data)) {
718 efuse_addr++;
719 continue;
720 }
721
722 hoffset |= ((efuse_data & 0xF0) >> 1);
723 hworden = efuse_data & 0x0F;
724 } else {
725 hoffset = (efuse_data >> 4) & 0x0F;
726 hworden = efuse_data & 0x0F;
727 }
728 word_cnts = Efuse_CalculateWordCnts23a(hworden);
729 /* read next header */
730 efuse_addr += (word_cnts * 2) + 1;
731 }
732
733 /* Check if we need to check next bank efuse */
734 if (efuse_addr < retU2) {
735 break; /* don't need to check next bank. */
736 }
737 }
738
739 retU2 = ((bank - 1) * EFUSE_BT_REAL_BANK_CONTENT_LEN) + efuse_addr;
740 pHalData->BTEfuseUsedBytes = retU2;
741
742 DBG_8723A("%s: CurrentSize =%d\n", __func__, retU2);
743 return retU2;
744 }
745
746 bool
747 rtl8723a_EfusePgPacketRead(struct rtw_adapter *padapter, u8 offset, u8 *data)
748 {
749 u8 efuse_data, word_cnts = 0;
750 u16 efuse_addr = 0;
751 u8 hoffset = 0, hworden = 0;
752 u8 i;
753 u8 max_section = 0;
754 s32 ret;
755
756 if (data == NULL)
757 return false;
758
759 EFUSE_GetEfuseDefinition23a(padapter, EFUSE_WIFI, TYPE_EFUSE_MAX_SECTION,
760 &max_section);
761 if (offset > max_section) {
762 DBG_8723A("%s: Packet offset(%d) is illegal(>%d)!\n",
763 __func__, offset, max_section);
764 return false;
765 }
766
767 memset(data, 0xFF, PGPKT_DATA_SIZE);
768 ret = true;
769
770 /* */
771 /* <Roger_TODO> Efuse has been pre-programmed dummy 5Bytes at the
772 end of Efuse by CP. */
773 /* Skip dummy parts to prevent unexpected data read from Efuse. */
774 /* By pass right now. 2009.02.19. */
775 /* */
776 while (AVAILABLE_EFUSE_ADDR(efuse_addr)) {
777 if (efuse_OneByteRead23a(padapter, efuse_addr++, &efuse_data) ==
778 _FAIL) {
779 ret = false;
780 break;
781 }
782
783 if (efuse_data == 0xFF)
784 break;
785
786 if (EXT_HEADER(efuse_data)) {
787 hoffset = GET_HDR_OFFSET_2_0(efuse_data);
788 efuse_OneByteRead23a(padapter, efuse_addr++, &efuse_data);
789 if (ALL_WORDS_DISABLED(efuse_data)) {
790 DBG_8723A("%s: Error!! All words disabled!\n",
791 __func__);
792 continue;
793 }
794
795 hoffset |= ((efuse_data & 0xF0) >> 1);
796 hworden = efuse_data & 0x0F;
797 } else {
798 hoffset = (efuse_data >> 4) & 0x0F;
799 hworden = efuse_data & 0x0F;
800 }
801
802 if (hoffset == offset) {
803 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
804 /* Check word enable condition in the section */
805 if (!(hworden & (0x01 << i))) {
806 ReadEFuseByte23a(padapter, efuse_addr++,
807 &efuse_data);
808 data[i * 2] = efuse_data;
809
810 ReadEFuseByte23a(padapter, efuse_addr++,
811 &efuse_data);
812 data[(i * 2) + 1] = efuse_data;
813 }
814 }
815 } else {
816 word_cnts = Efuse_CalculateWordCnts23a(hworden);
817 efuse_addr += word_cnts * 2;
818 }
819 }
820
821 return ret;
822 }
823
824 void rtl8723a_read_chip_version(struct rtw_adapter *padapter)
825 {
826 u32 value32;
827 struct hal_version ChipVersion;
828 struct hal_data_8723a *pHalData;
829
830 pHalData = GET_HAL_DATA(padapter);
831
832 value32 = rtl8723au_read32(padapter, REG_SYS_CFG);
833 ChipVersion.ICType = CHIP_8723A;
834 ChipVersion.ChipType = ((value32 & RTL_ID) ? TEST_CHIP : NORMAL_CHIP);
835 ChipVersion.RFType = RF_TYPE_1T1R;
836 ChipVersion.VendorType =
837 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : CHIP_VENDOR_TSMC);
838 ChipVersion.CUTVersion = (value32 & CHIP_VER_RTL_MASK) >> CHIP_VER_RTL_SHIFT; /* IC version (CUT) */
839
840 /* For regulator mode. by tynli. 2011.01.14 */
841 pHalData->RegulatorMode = ((value32 & SPS_SEL) ?
842 RT_LDO_REGULATOR : RT_SWITCHING_REGULATOR);
843
844 value32 = rtl8723au_read32(padapter, REG_GPIO_OUTSTS);
845 /* ROM code version. */
846 ChipVersion.ROMVer = ((value32 & RF_RL_ID) >> 20);
847
848 /* For multi-function consideration. Added by Roger, 2010.10.06. */
849 pHalData->MultiFunc = RT_MULTI_FUNC_NONE;
850 value32 = rtl8723au_read32(padapter, REG_MULTI_FUNC_CTRL);
851 pHalData->MultiFunc |=
852 ((value32 & WL_FUNC_EN) ? RT_MULTI_FUNC_WIFI : 0);
853 pHalData->MultiFunc |= ((value32 & BT_FUNC_EN) ? RT_MULTI_FUNC_BT : 0);
854 pHalData->MultiFunc |=
855 ((value32 & GPS_FUNC_EN) ? RT_MULTI_FUNC_GPS : 0);
856 pHalData->PolarityCtl =
857 ((value32 & WL_HWPDN_SL) ? RT_POLARITY_HIGH_ACT :
858 RT_POLARITY_LOW_ACT);
859 dump_chip_info23a(ChipVersion);
860 pHalData->VersionID = ChipVersion;
861
862 if (IS_1T2R(ChipVersion))
863 pHalData->rf_type = RF_1T2R;
864 else if (IS_2T2R(ChipVersion))
865 pHalData->rf_type = RF_2T2R;
866 else
867 pHalData->rf_type = RF_1T1R;
868
869 MSG_8723A("RF_Type is %x!!\n", pHalData->rf_type);
870 }
871
872 /* */
873 /* */
874 /* 20100209 Joseph: */
875 /* This function is used only for 92C to set REG_BCN_CTRL(0x550) register. */
876 /* We just reserve the value of the register in variable
877 pHalData->RegBcnCtrlVal and then operate */
878 /* the value of the register via atomic operation. */
879 /* This prevents from race condition when setting this register. */
880 /* The value of pHalData->RegBcnCtrlVal is initialized in
881 HwConfigureRTL8192CE() function. */
882 /* */
883 void SetBcnCtrlReg23a(struct rtw_adapter *padapter, u8 SetBits, u8 ClearBits)
884 {
885 u8 val8;
886
887 val8 = rtl8723au_read8(padapter, REG_BCN_CTRL);
888 val8 |= SetBits;
889 val8 &= ~ClearBits;
890
891 rtl8723au_write8(padapter, REG_BCN_CTRL, val8);
892 }
893
894 void rtl8723a_InitBeaconParameters(struct rtw_adapter *padapter)
895 {
896 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
897
898 rtl8723au_write16(padapter, REG_BCN_CTRL, 0x1010);
899
900 /* TODO: Remove these magic number */
901 rtl8723au_write16(padapter, REG_TBTT_PROHIBIT, 0x6404); /* ms */
902 /* Firmware will control REG_DRVERLYINT when power saving is enable, */
903 /* so don't set this register on STA mode. */
904 if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == false)
905 rtl8723au_write8(padapter, REG_DRVERLYINT,
906 DRIVER_EARLY_INT_TIME);
907 /* 2ms */
908 rtl8723au_write8(padapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
909
910 /* Suggested by designer timchen. Change beacon AIFS to the
911 largest number beacause test chip does not contension before
912 sending beacon. by tynli. 2009.11.03 */
913 rtl8723au_write16(padapter, REG_BCNTCFG, 0x660F);
914 }
915
916 static void ResumeTxBeacon(struct rtw_adapter *padapter)
917 {
918 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
919
920 /* 2010.03.01. Marked by tynli. No need to call workitem beacause
921 we record the value */
922 /* which should be read from register to a global variable. */
923
924 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+ResumeTxBeacon\n"));
925
926 pHalData->RegFwHwTxQCtrl |= BIT(6);
927 rtl8723au_write8(padapter, REG_FWHW_TXQ_CTRL + 2,
928 pHalData->RegFwHwTxQCtrl);
929 rtl8723au_write8(padapter, REG_TBTT_PROHIBIT + 1, 0xff);
930 pHalData->RegReg542 |= BIT(0);
931 rtl8723au_write8(padapter, REG_TBTT_PROHIBIT + 2, pHalData->RegReg542);
932 }
933
934 static void StopTxBeacon(struct rtw_adapter *padapter)
935 {
936 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
937
938 /* 2010.03.01. Marked by tynli. No need to call workitem beacause
939 we record the value */
940 /* which should be read from register to a global variable. */
941
942 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+StopTxBeacon\n"));
943
944 pHalData->RegFwHwTxQCtrl &= ~BIT(6);
945 rtl8723au_write8(padapter, REG_FWHW_TXQ_CTRL + 2,
946 pHalData->RegFwHwTxQCtrl);
947 rtl8723au_write8(padapter, REG_TBTT_PROHIBIT + 1, 0x64);
948 pHalData->RegReg542 &= ~BIT(0);
949 rtl8723au_write8(padapter, REG_TBTT_PROHIBIT + 2, pHalData->RegReg542);
950 }
951
952 static void _BeaconFunctionEnable(struct rtw_adapter *padapter, u8 Enable,
953 u8 Linked)
954 {
955 SetBcnCtrlReg23a(padapter, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB,
956 0);
957 rtl8723au_write8(padapter, REG_RD_CTRL + 1, 0x6F);
958 }
959
960 void rtl8723a_SetBeaconRelatedRegisters(struct rtw_adapter *padapter)
961 {
962 u32 value32;
963 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
964 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
965
966 /* reset TSF, enable update TSF, correcting TSF On Beacon */
967
968 /* REG_BCN_INTERVAL */
969 /* REG_BCNDMATIM */
970 /* REG_ATIMWND */
971 /* REG_TBTT_PROHIBIT */
972 /* REG_DRVERLYINT */
973 /* REG_BCN_MAX_ERR */
974 /* REG_BCNTCFG (0x510) */
975 /* REG_DUAL_TSF_RST */
976 /* REG_BCN_CTRL (0x550) */
977
978 /* */
979 /* ATIM window */
980 /* */
981 rtl8723au_write16(padapter, REG_ATIMWND, 2);
982
983 /* */
984 /* Beacon interval (in unit of TU). */
985 /* */
986 rtl8723au_write16(padapter, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval);
987
988 rtl8723a_InitBeaconParameters(padapter);
989
990 rtl8723au_write8(padapter, REG_SLOT, 0x09);
991
992 /* */
993 /* Reset TSF Timer to zero, added by Roger. 2008.06.24 */
994 /* */
995 value32 = rtl8723au_read32(padapter, REG_TCR);
996 value32 &= ~TSFRST;
997 rtl8723au_write32(padapter, REG_TCR, value32);
998
999 value32 |= TSFRST;
1000 rtl8723au_write32(padapter, REG_TCR, value32);
1001
1002 /* NOTE: Fix test chip's bug (about contention windows's randomness) */
1003 if (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE |
1004 WIFI_ADHOC_MASTER_STATE | WIFI_AP_STATE) == true) {
1005 rtl8723au_write8(padapter, REG_RXTSF_OFFSET_CCK, 0x50);
1006 rtl8723au_write8(padapter, REG_RXTSF_OFFSET_OFDM, 0x50);
1007 }
1008
1009 _BeaconFunctionEnable(padapter, true, true);
1010
1011 ResumeTxBeacon(padapter);
1012 SetBcnCtrlReg23a(padapter, DIS_BCNQ_SUB, 0);
1013 }
1014
1015 void rtl8723a_SetHalODMVar(struct rtw_adapter *Adapter,
1016 enum hal_odm_variable eVariable,
1017 void *pValue1, bool bSet)
1018 {
1019 struct hal_data_8723a *pHalData = GET_HAL_DATA(Adapter);
1020 struct dm_odm_t *podmpriv = &pHalData->odmpriv;
1021 switch (eVariable) {
1022 case HAL_ODM_STA_INFO:
1023 {
1024 struct sta_info *psta = (struct sta_info *)pValue1;
1025
1026 if (bSet) {
1027 DBG_8723A("Set STA_(%d) info\n", psta->mac_id);
1028 ODM_CmnInfoPtrArrayHook23a(podmpriv,
1029 ODM_CMNINFO_STA_STATUS,
1030 psta->mac_id, psta);
1031 } else {
1032 DBG_8723A("Clean STA_(%d) info\n", psta->mac_id);
1033 ODM_CmnInfoPtrArrayHook23a(podmpriv,
1034 ODM_CMNINFO_STA_STATUS,
1035 psta->mac_id, NULL);
1036 }
1037 }
1038 break;
1039 case HAL_ODM_P2P_STATE:
1040 ODM_CmnInfoUpdate23a(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet);
1041 break;
1042 case HAL_ODM_WIFI_DISPLAY_STATE:
1043 ODM_CmnInfoUpdate23a(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet);
1044 break;
1045 default:
1046 break;
1047 }
1048 }
1049
1050 void rtl8723a_notch_filter(struct rtw_adapter *adapter, bool enable)
1051 {
1052 if (enable) {
1053 DBG_8723A("Enable notch filter\n");
1054 rtl8723au_write8(adapter, rOFDM0_RxDSP + 1,
1055 rtl8723au_read8(adapter, rOFDM0_RxDSP + 1) |
1056 BIT(1));
1057 } else {
1058 DBG_8723A("Disable notch filter\n");
1059 rtl8723au_write8(adapter, rOFDM0_RxDSP + 1,
1060 rtl8723au_read8(adapter, rOFDM0_RxDSP + 1) &
1061 ~BIT(1));
1062 }
1063 }
1064
1065 bool c2h_id_filter_ccx_8723a(u8 id)
1066 {
1067 bool ret = false;
1068 if (id == C2H_CCX_TX_RPT)
1069 ret = true;
1070
1071 return ret;
1072 }
1073
1074 int c2h_handler_8723a(struct rtw_adapter *padapter, struct c2h_evt_hdr *c2h_evt)
1075 {
1076 int ret = _SUCCESS;
1077 u8 i = 0;
1078
1079 if (c2h_evt == NULL) {
1080 DBG_8723A("%s c2h_evt is NULL\n", __func__);
1081 ret = _FAIL;
1082 goto exit;
1083 }
1084
1085 switch (c2h_evt->id) {
1086 case C2H_DBG:
1087 RT_TRACE(_module_hal_init_c_, _drv_info_,
1088 ("C2HCommandHandler: %s\n", c2h_evt->payload));
1089 break;
1090
1091 case C2H_CCX_TX_RPT:
1092 handle_txrpt_ccx_8723a(padapter, c2h_evt->payload);
1093 break;
1094 case C2H_EXT_RA_RPT:
1095 break;
1096 case C2H_HW_INFO_EXCH:
1097 RT_TRACE(_module_hal_init_c_, _drv_info_,
1098 ("[BT], C2H_HW_INFO_EXCH\n"));
1099 for (i = 0; i < c2h_evt->plen; i++) {
1100 RT_TRACE(_module_hal_init_c_, _drv_info_,
1101 ("[BT], tmpBuf[%d]= 0x%x\n", i,
1102 c2h_evt->payload[i]));
1103 }
1104 break;
1105
1106 case C2H_C2H_H2C_TEST:
1107 RT_TRACE(_module_hal_init_c_, _drv_info_,
1108 ("[BT], C2H_H2C_TEST\n"));
1109 RT_TRACE(_module_hal_init_c_, _drv_info_,
1110 ("[BT], tmpBuf[0]/[1]/[2]/[3]/[4]= 0x%x/ 0x%x/ "
1111 "0x%x/ 0x%x/ 0x%x\n", c2h_evt->payload[0],
1112 c2h_evt->payload[1], c2h_evt->payload[2],
1113 c2h_evt->payload[3], c2h_evt->payload[4]));
1114 break;
1115
1116 case C2H_BT_INFO:
1117 DBG_8723A("%s , Got C2H_BT_INFO \n", __func__);
1118 rtl8723a_fw_c2h_BT_info(padapter,
1119 c2h_evt->payload, c2h_evt->plen);
1120 break;
1121
1122 default:
1123 ret = _FAIL;
1124 break;
1125 }
1126
1127 exit:
1128 return ret;
1129 }
1130
1131 void rtl8723a_InitAntenna_Selection(struct rtw_adapter *padapter)
1132 {
1133 u8 val;
1134
1135 val = rtl8723au_read8(padapter, REG_LEDCFG2);
1136 /* Let 8051 take control antenna settting */
1137 val |= BIT(7); /* DPDT_SEL_EN, 0x4C[23] */
1138 rtl8723au_write8(padapter, REG_LEDCFG2, val);
1139 }
1140
1141 void rtl8723a_CheckAntenna_Selection(struct rtw_adapter *padapter)
1142 {
1143 u8 val;
1144
1145 val = rtl8723au_read8(padapter, REG_LEDCFG2);
1146 /* Let 8051 take control antenna settting */
1147 if (!(val & BIT(7))) {
1148 val |= BIT(7); /* DPDT_SEL_EN, 0x4C[23] */
1149 rtl8723au_write8(padapter, REG_LEDCFG2, val);
1150 }
1151 }
1152
1153 void rtl8723a_DeinitAntenna_Selection(struct rtw_adapter *padapter)
1154 {
1155 u8 val;
1156
1157 val = rtl8723au_read8(padapter, REG_LEDCFG2);
1158 /* Let 8051 take control antenna settting */
1159 val &= ~BIT(7); /* DPDT_SEL_EN, clear 0x4C[23] */
1160 rtl8723au_write8(padapter, REG_LEDCFG2, val);
1161 }
1162
1163 void rtl8723a_init_default_value(struct rtw_adapter *padapter)
1164 {
1165 struct hal_data_8723a *pHalData;
1166 struct dm_priv *pdmpriv;
1167 u8 i;
1168
1169 pHalData = GET_HAL_DATA(padapter);
1170 pdmpriv = &pHalData->dmpriv;
1171
1172 /* init default value */
1173 pHalData->fw_ractrl = false;
1174 pHalData->bIQKInitialized = false;
1175 if (!padapter->pwrctrlpriv.bkeepfwalive)
1176 pHalData->LastHMEBoxNum = 0;
1177
1178 pHalData->bIQKInitialized = false;
1179
1180 /* init dm default value */
1181 pdmpriv->TM_Trigger = 0; /* for IQK */
1182 /* pdmpriv->binitialized = false; */
1183 /* pdmpriv->prv_traffic_idx = 3; */
1184 /* pdmpriv->initialize = 0; */
1185
1186 pdmpriv->ThermalValue_HP_index = 0;
1187 for (i = 0; i < HP_THERMAL_NUM; i++)
1188 pdmpriv->ThermalValue_HP[i] = 0;
1189
1190 /* init Efuse variables */
1191 pHalData->EfuseUsedBytes = 0;
1192 pHalData->BTEfuseUsedBytes = 0;
1193 }
1194
1195 u8 GetEEPROMSize8723A(struct rtw_adapter *padapter)
1196 {
1197 u8 size = 0;
1198 u32 cr;
1199
1200 cr = rtl8723au_read16(padapter, REG_9346CR);
1201 /* 6: EEPROM used is 93C46, 4: boot from E-Fuse. */
1202 size = (cr & BOOT_FROM_EEPROM) ? 6 : 4;
1203
1204 MSG_8723A("EEPROM type is %s\n", size == 4 ? "E-FUSE" : "93C46");
1205
1206 return size;
1207 }
1208
1209 /* */
1210 /* */
1211 /* LLT R/W/Init function */
1212 /* */
1213 /* */
1214 static int _LLTWrite(struct rtw_adapter *padapter, u32 address, u32 data)
1215 {
1216 int status = _SUCCESS;
1217 s32 count = 0;
1218 u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
1219 _LLT_OP(_LLT_WRITE_ACCESS);
1220 u16 LLTReg = REG_LLT_INIT;
1221
1222 rtl8723au_write32(padapter, LLTReg, value);
1223
1224 /* polling */
1225 do {
1226 value = rtl8723au_read32(padapter, LLTReg);
1227 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)) {
1228 break;
1229 }
1230
1231 if (count > POLLING_LLT_THRESHOLD) {
1232 RT_TRACE(_module_hal_init_c_, _drv_err_,
1233 ("Failed to polling write LLT done at "
1234 "address %d!\n", address));
1235 status = _FAIL;
1236 break;
1237 }
1238 } while (count++);
1239
1240 return status;
1241 }
1242
1243 int InitLLTTable23a(struct rtw_adapter *padapter, u32 boundary)
1244 {
1245 int status = _SUCCESS;
1246 u32 i;
1247 u32 txpktbuf_bndy = boundary;
1248 u32 Last_Entry_Of_TxPktBuf = LAST_ENTRY_OF_TX_PKT_BUFFER;
1249
1250 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
1251 status = _LLTWrite(padapter, i, i + 1);
1252 if (status != _SUCCESS) {
1253 return status;
1254 }
1255 }
1256
1257 /* end of list */
1258 status = _LLTWrite(padapter, (txpktbuf_bndy - 1), 0xFF);
1259 if (status != _SUCCESS) {
1260 return status;
1261 }
1262
1263 /* Make the other pages as ring buffer */
1264 /* This ring buffer is used as beacon buffer if we config this
1265 MAC as two MAC transfer. */
1266 /* Otherwise used as local loopback buffer. */
1267 for (i = txpktbuf_bndy; i < Last_Entry_Of_TxPktBuf; i++) {
1268 status = _LLTWrite(padapter, i, (i + 1));
1269 if (_SUCCESS != status) {
1270 return status;
1271 }
1272 }
1273
1274 /* Let last entry point to the start entry of ring buffer */
1275 status = _LLTWrite(padapter, Last_Entry_Of_TxPktBuf, txpktbuf_bndy);
1276 if (status != _SUCCESS) {
1277 return status;
1278 }
1279
1280 return status;
1281 }
1282
1283 static void _DisableGPIO(struct rtw_adapter *padapter)
1284 {
1285 /***************************************
1286 j. GPIO_PIN_CTRL 0x44[31:0]= 0x000
1287 k.Value = GPIO_PIN_CTRL[7:0]
1288 l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write external PIN level
1289 m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
1290 n. LEDCFG 0x4C[15:0] = 0x8080
1291 ***************************************/
1292 u32 value32;
1293 u32 u4bTmp;
1294
1295 /* 1. Disable GPIO[7:0] */
1296 rtl8723au_write16(padapter, REG_GPIO_PIN_CTRL + 2, 0x0000);
1297 value32 = rtl8723au_read32(padapter, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
1298 u4bTmp = value32 & 0x000000FF;
1299 value32 |= ((u4bTmp << 8) | 0x00FF0000);
1300 rtl8723au_write32(padapter, REG_GPIO_PIN_CTRL, value32);
1301
1302 /* */
1303 /* <Roger_Notes> For RTL8723u multi-function configuration which
1304 was autoload from Efuse offset 0x0a and 0x0b, */
1305 /* WLAN HW GPIO[9], GPS HW GPIO[10] and BT HW GPIO[11]. */
1306 /* Added by Roger, 2010.10.07. */
1307 /* */
1308 /* 2. Disable GPIO[8] and GPIO[12] */
1309
1310 /* Configure all pins as input mode. */
1311 rtl8723au_write16(padapter, REG_GPIO_IO_SEL_2, 0x0000);
1312 value32 = rtl8723au_read32(padapter, REG_GPIO_PIN_CTRL_2) & 0xFFFF001F;
1313 u4bTmp = value32 & 0x0000001F;
1314 /* Set pin 8, 10, 11 and pin 12 to output mode. */
1315 value32 |= ((u4bTmp << 8) | 0x001D0000);
1316 rtl8723au_write32(padapter, REG_GPIO_PIN_CTRL_2, value32);
1317
1318 /* 3. Disable LED0 & 1 */
1319 rtl8723au_write16(padapter, REG_LEDCFG0, 0x8080);
1320 } /* end of _DisableGPIO() */
1321
1322 static void _DisableRFAFEAndResetBB8192C(struct rtw_adapter *padapter)
1323 {
1324 /**************************************
1325 a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue
1326 b. RF path 0 offset 0x00 = 0x00 disable RF
1327 c. APSD_CTRL 0x600[7:0] = 0x40
1328 d. SYS_FUNC_EN 0x02[7:0] = 0x16 reset BB state machine
1329 e. SYS_FUNC_EN 0x02[7:0] = 0x14 reset BB state machine
1330 ***************************************/
1331 u8 eRFPath = 0, value8 = 0;
1332
1333 rtl8723au_write8(padapter, REG_TXPAUSE, 0xFF);
1334
1335 PHY_SetRFReg(padapter, (enum RF_RADIO_PATH) eRFPath, 0x0, bMaskByte0, 0x0);
1336
1337 value8 |= APSDOFF;
1338 rtl8723au_write8(padapter, REG_APSD_CTRL, value8); /* 0x40 */
1339
1340 /* Set BB reset at first */
1341 value8 = 0;
1342 value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
1343 rtl8723au_write8(padapter, REG_SYS_FUNC_EN, value8); /* 0x16 */
1344
1345 /* Set global reset. */
1346 value8 &= ~FEN_BB_GLB_RSTn;
1347 rtl8723au_write8(padapter, REG_SYS_FUNC_EN, value8); /* 0x14 */
1348
1349 /* 2010/08/12 MH We need to set BB/GLBAL reset to save power
1350 for SS mode. */
1351
1352 /* RT_TRACE(COMP_INIT, DBG_LOUD, ("======> RF off and reset BB.\n")); */
1353 }
1354
1355 static void _DisableRFAFEAndResetBB(struct rtw_adapter *padapter)
1356 {
1357 _DisableRFAFEAndResetBB8192C(padapter);
1358 }
1359
1360 static void _ResetDigitalProcedure1_92C(struct rtw_adapter *padapter,
1361 bool bWithoutHWSM)
1362 {
1363 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
1364
1365 if (IS_FW_81xxC(padapter) && (pHalData->FirmwareVersion <= 0x20)) {
1366 /*****************************
1367 f. MCUFWDL 0x80[7:0]= 0 reset MCU ready status
1368 g. SYS_FUNC_EN 0x02[10]= 0 reset MCU register, (8051 reset)
1369 h. SYS_FUNC_EN 0x02[15-12]= 5 reset MAC register, DCORE
1370 i. SYS_FUNC_EN 0x02[10]= 1 enable MCU register,
1371 (8051 enable)
1372 ******************************/
1373 u16 valu16 = 0;
1374 rtl8723au_write8(padapter, REG_MCUFWDL, 0);
1375
1376 valu16 = rtl8723au_read16(padapter, REG_SYS_FUNC_EN);
1377 /* reset MCU , 8051 */
1378 rtl8723au_write16(padapter, REG_SYS_FUNC_EN,
1379 valu16 & (~FEN_CPUEN));
1380
1381 valu16 = rtl8723au_read16(padapter, REG_SYS_FUNC_EN) & 0x0FFF;
1382 /* reset MAC */
1383 rtl8723au_write16(padapter, REG_SYS_FUNC_EN,
1384 valu16 | (FEN_HWPDN | FEN_ELDR));
1385
1386 valu16 = rtl8723au_read16(padapter, REG_SYS_FUNC_EN);
1387 /* enable MCU , 8051 */
1388 rtl8723au_write16(padapter, REG_SYS_FUNC_EN,
1389 valu16 | FEN_CPUEN);
1390 } else {
1391 u8 retry_cnts = 0;
1392
1393 /* 2010/08/12 MH For USB SS, we can not stop 8051 when we
1394 are trying to enter IPS/HW&SW radio off. For
1395 S3/S4/S5/Disable, we can stop 8051 because */
1396 /* we will init FW when power on again. */
1397 /* If we want to SS mode, we can not reset 8051. */
1398 if (rtl8723au_read8(padapter, REG_MCUFWDL) & BIT(1)) {
1399 /* IF fw in RAM code, do reset */
1400 if (padapter->bFWReady) {
1401 /* 2010/08/25 MH Accordign to RD alfred's
1402 suggestion, we need to disable other */
1403 /* HRCV INT to influence 8051 reset. */
1404 rtl8723au_write8(padapter, REG_FWIMR, 0x20);
1405 /* 2011/02/15 MH According to Alex's
1406 suggestion, close mask to prevent
1407 incorrect FW write operation. */
1408 rtl8723au_write8(padapter, REG_FTIMR, 0x00);
1409 rtl8723au_write8(padapter, REG_FSIMR, 0x00);
1410
1411 /* 8051 reset by self */
1412 rtl8723au_write8(padapter, REG_HMETFR + 3,
1413 0x20);
1414
1415 while ((retry_cnts++ < 100) &&
1416 (FEN_CPUEN &
1417 rtl8723au_read16(padapter,
1418 REG_SYS_FUNC_EN))) {
1419 udelay(50); /* us */
1420 }
1421
1422 if (retry_cnts >= 100) {
1423 /* Reset MAC and Enable 8051 */
1424 rtl8723au_write8(padapter,
1425 REG_SYS_FUNC_EN + 1,
1426 0x50);
1427 mdelay(10);
1428 }
1429 }
1430 }
1431 /* Reset MAC and Enable 8051 */
1432 rtl8723au_write8(padapter, REG_SYS_FUNC_EN + 1, 0x54);
1433 rtl8723au_write8(padapter, REG_MCUFWDL, 0);
1434 }
1435
1436 if (bWithoutHWSM) {
1437 /*****************************
1438 Without HW auto state machine
1439 g. SYS_CLKR 0x08[15:0] = 0x30A3 disable MAC clock
1440 h. AFE_PLL_CTRL 0x28[7:0] = 0x80 disable AFE PLL
1441 i. AFE_XTAL_CTRL 0x24[15:0] = 0x880F gated AFE DIG_CLOCK
1442 j. SYS_ISO_CTRL 0x00[7:0] = 0xF9 isolated digital to PON
1443 ******************************/
1444 /* modify to 0x70A3 by Scott. */
1445 rtl8723au_write16(padapter, REG_SYS_CLKR, 0x70A3);
1446 rtl8723au_write8(padapter, REG_AFE_PLL_CTRL, 0x80);
1447 rtl8723au_write16(padapter, REG_AFE_XTAL_CTRL, 0x880F);
1448 rtl8723au_write8(padapter, REG_SYS_ISO_CTRL, 0xF9);
1449 } else {
1450 /* Disable all RF/BB power */
1451 rtl8723au_write8(padapter, REG_RF_CTRL, 0x00);
1452 }
1453 }
1454
1455 static void _ResetDigitalProcedure1(struct rtw_adapter *padapter,
1456 bool bWithoutHWSM)
1457 {
1458 _ResetDigitalProcedure1_92C(padapter, bWithoutHWSM);
1459 }
1460
1461 static void _ResetDigitalProcedure2(struct rtw_adapter *padapter)
1462 {
1463 /*****************************
1464 k. SYS_FUNC_EN 0x03[7:0] = 0x44 disable ELDR runction
1465 l. SYS_CLKR 0x08[15:0] = 0x3083 disable ELDR clock
1466 m. SYS_ISO_CTRL 0x01[7:0] = 0x83 isolated ELDR to PON
1467 ******************************/
1468 /* modify to 0x70a3 by Scott. */
1469 rtl8723au_write16(padapter, REG_SYS_CLKR, 0x70a3);
1470 /* modify to 0x82 by Scott. */
1471 rtl8723au_write8(padapter, REG_SYS_ISO_CTRL + 1, 0x82);
1472 }
1473
1474 static void _DisableAnalog(struct rtw_adapter *padapter, bool bWithoutHWSM)
1475 {
1476 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
1477 u16 value16 = 0;
1478 u8 value8 = 0;
1479
1480 if (bWithoutHWSM) {
1481 /*****************************
1482 n. LDOA15_CTRL 0x20[7:0] = 0x04 disable A15 power
1483 o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power
1484 r. When driver call disable, the ASIC will turn off remaining
1485 clock automatically
1486 ******************************/
1487
1488 rtl8723au_write8(padapter, REG_LDOA15_CTRL, 0x04);
1489 /* rtl8723au_write8(padapter, REG_LDOV12D_CTRL, 0x54); */
1490
1491 value8 = rtl8723au_read8(padapter, REG_LDOV12D_CTRL);
1492 value8 &= (~LDV12_EN);
1493 rtl8723au_write8(padapter, REG_LDOV12D_CTRL, value8);
1494 /* RT_TRACE(COMP_INIT, DBG_LOUD,
1495 (" REG_LDOV12D_CTRL Reg0x21:0x%02x.\n", value8)); */
1496 }
1497
1498 /*****************************
1499 h. SPS0_CTRL 0x11[7:0] = 0x23 enter PFM mode
1500 i. APS_FSMCO 0x04[15:0] = 0x4802 set USB suspend
1501 ******************************/
1502 value8 = 0x23;
1503 if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID))
1504 value8 |= BIT(3);
1505
1506 rtl8723au_write8(padapter, REG_SPS0_CTRL, value8);
1507
1508 if (bWithoutHWSM) {
1509 /* value16 |= (APDM_HOST | FSM_HSUS |/PFM_ALDN); */
1510 /* 2010/08/31 According to Filen description, we need to
1511 use HW to shut down 8051 automatically. */
1512 /* Becasue suspend operatione need the asistance of 8051
1513 to wait for 3ms. */
1514 value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
1515 } else {
1516 value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
1517 }
1518
1519 rtl8723au_write16(padapter, REG_APS_FSMCO, value16); /* 0x4802 */
1520
1521 rtl8723au_write8(padapter, REG_RSV_CTRL, 0x0e);
1522 }
1523
1524 /* HW Auto state machine */
1525 int CardDisableHWSM(struct rtw_adapter *padapter, u8 resetMCU)
1526 {
1527 int rtStatus = _SUCCESS;
1528
1529 if (padapter->bSurpriseRemoved) {
1530 return rtStatus;
1531 }
1532 /* RF Off Sequence ==== */
1533 _DisableRFAFEAndResetBB(padapter);
1534
1535 /* ==== Reset digital sequence ====== */
1536 _ResetDigitalProcedure1(padapter, false);
1537
1538 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1539 _DisableGPIO(padapter);
1540
1541 /* ==== Disable analog sequence === */
1542 _DisableAnalog(padapter, false);
1543
1544 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1545 ("======> Card disable finished.\n"));
1546
1547 return rtStatus;
1548 }
1549
1550 /* without HW Auto state machine */
1551 int CardDisableWithoutHWSM(struct rtw_adapter *padapter)
1552 {
1553 int rtStatus = _SUCCESS;
1554
1555 /* RT_TRACE(COMP_INIT, DBG_LOUD,
1556 ("======> Card Disable Without HWSM .\n")); */
1557 if (padapter->bSurpriseRemoved) {
1558 return rtStatus;
1559 }
1560
1561 /* RF Off Sequence ==== */
1562 _DisableRFAFEAndResetBB(padapter);
1563
1564 /* ==== Reset digital sequence ====== */
1565 _ResetDigitalProcedure1(padapter, true);
1566
1567 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1568 _DisableGPIO(padapter);
1569
1570 /* ==== Reset digital sequence ====== */
1571 _ResetDigitalProcedure2(padapter);
1572
1573 /* ==== Disable analog sequence === */
1574 _DisableAnalog(padapter, true);
1575
1576 /* RT_TRACE(COMP_INIT, DBG_LOUD,
1577 ("<====== Card Disable Without HWSM .\n")); */
1578 return rtStatus;
1579 }
1580
1581 void Hal_InitPGData(struct rtw_adapter *padapter, u8 *PROMContent)
1582 {
1583 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1584
1585 if (false == pEEPROM->bautoload_fail_flag) { /* autoload OK. */
1586 if (!pEEPROM->EepromOrEfuse) {
1587 /* Read EFUSE real map to shadow. */
1588 EFUSE_ShadowMapUpdate23a(padapter, EFUSE_WIFI);
1589 memcpy((void *)PROMContent,
1590 (void *)pEEPROM->efuse_eeprom_data,
1591 HWSET_MAX_SIZE);
1592 }
1593 } else { /* autoload fail */
1594 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_,
1595 ("AutoLoad Fail reported from CR9346!!\n"));
1596 /* pHalData->AutoloadFailFlag = true; */
1597 /* update to default value 0xFF */
1598 if (false == pEEPROM->EepromOrEfuse)
1599 EFUSE_ShadowMapUpdate23a(padapter, EFUSE_WIFI);
1600 memcpy((void *)PROMContent, (void *)pEEPROM->efuse_eeprom_data,
1601 HWSET_MAX_SIZE);
1602 }
1603 }
1604
1605 void Hal_EfuseParseIDCode(struct rtw_adapter *padapter, u8 *hwinfo)
1606 {
1607 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1608 /* struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter); */
1609 u16 EEPROMId;
1610
1611 /* Checl 0x8129 again for making sure autoload status!! */
1612 EEPROMId = le16_to_cpu(*((u16 *) hwinfo));
1613 if (EEPROMId != RTL_EEPROM_ID) {
1614 DBG_8723A("EEPROM ID(%#x) is invalid!!\n", EEPROMId);
1615 pEEPROM->bautoload_fail_flag = true;
1616 } else {
1617 pEEPROM->bautoload_fail_flag = false;
1618 }
1619
1620 RT_TRACE(_module_hal_init_c_, _drv_info_,
1621 ("EEPROM ID = 0x%04x\n", EEPROMId));
1622 }
1623
1624 static void Hal_EEValueCheck(u8 EEType, void *pInValue, void *pOutValue)
1625 {
1626 switch (EEType) {
1627 case EETYPE_TX_PWR:
1628 {
1629 u8 *pIn, *pOut;
1630 pIn = (u8 *) pInValue;
1631 pOut = (u8 *) pOutValue;
1632 if (*pIn <= 63)
1633 *pOut = *pIn;
1634 else {
1635 RT_TRACE(_module_hci_hal_init_c_, _drv_err_,
1636 ("EETYPE_TX_PWR, value =%d is invalid, set "
1637 "to default = 0x%x\n",
1638 *pIn, EEPROM_Default_TxPowerLevel));
1639 *pOut = EEPROM_Default_TxPowerLevel;
1640 }
1641 }
1642 break;
1643 default:
1644 break;
1645 }
1646 }
1647
1648 static void
1649 Hal_ReadPowerValueFromPROM_8723A(struct txpowerinfo *pwrInfo,
1650 u8 *PROMContent, bool AutoLoadFail)
1651 {
1652 u32 rfPath, eeAddr, group, rfPathMax = 1;
1653
1654 memset(pwrInfo, 0, sizeof(*pwrInfo));
1655
1656 if (AutoLoadFail) {
1657 for (group = 0; group < MAX_CHNL_GROUP; group++) {
1658 for (rfPath = 0; rfPath < rfPathMax; rfPath++) {
1659 pwrInfo->CCKIndex[rfPath][group] =
1660 EEPROM_Default_TxPowerLevel;
1661 pwrInfo->HT40_1SIndex[rfPath][group] =
1662 EEPROM_Default_TxPowerLevel;
1663 pwrInfo->HT40_2SIndexDiff[rfPath][group] =
1664 EEPROM_Default_HT40_2SDiff;
1665 pwrInfo->HT20IndexDiff[rfPath][group] =
1666 EEPROM_Default_HT20_Diff;
1667 pwrInfo->OFDMIndexDiff[rfPath][group] =
1668 EEPROM_Default_LegacyHTTxPowerDiff;
1669 pwrInfo->HT40MaxOffset[rfPath][group] =
1670 EEPROM_Default_HT40_PwrMaxOffset;
1671 pwrInfo->HT20MaxOffset[rfPath][group] =
1672 EEPROM_Default_HT20_PwrMaxOffset;
1673 }
1674 }
1675 pwrInfo->TSSI_A[0] = EEPROM_Default_TSSI;
1676 return;
1677 }
1678
1679 for (rfPath = 0; rfPath < rfPathMax; rfPath++) {
1680 for (group = 0; group < MAX_CHNL_GROUP; group++) {
1681 eeAddr =
1682 EEPROM_CCK_TX_PWR_INX_8723A + (rfPath * 3) + group;
1683 /* pwrInfo->CCKIndex[rfPath][group] =
1684 PROMContent[eeAddr]; */
1685 Hal_EEValueCheck(EETYPE_TX_PWR, &PROMContent[eeAddr],
1686 &pwrInfo->CCKIndex[rfPath][group]);
1687 eeAddr = EEPROM_HT40_1S_TX_PWR_INX_8723A +
1688 (rfPath * 3) + group;
1689 /* pwrInfo->HT40_1SIndex[rfPath][group] =
1690 PROMContent[eeAddr]; */
1691 Hal_EEValueCheck(EETYPE_TX_PWR, &PROMContent[eeAddr],
1692 &pwrInfo->HT40_1SIndex[rfPath][group]);
1693 }
1694 }
1695
1696 for (group = 0; group < MAX_CHNL_GROUP; group++) {
1697 for (rfPath = 0; rfPath < rfPathMax; rfPath++) {
1698 pwrInfo->HT40_2SIndexDiff[rfPath][group] = 0;
1699 pwrInfo->HT20IndexDiff[rfPath][group] =
1700 (PROMContent
1701 [EEPROM_HT20_TX_PWR_INX_DIFF_8723A +
1702 group] >> (rfPath * 4)) & 0xF;
1703 /* 4bit sign number to 8 bit sign number */
1704 if (pwrInfo->HT20IndexDiff[rfPath][group] & BIT(3))
1705 pwrInfo->HT20IndexDiff[rfPath][group] |= 0xF0;
1706
1707 pwrInfo->OFDMIndexDiff[rfPath][group] =
1708 (PROMContent[EEPROM_OFDM_TX_PWR_INX_DIFF_8723A +
1709 group] >> (rfPath * 4)) & 0xF;
1710
1711 pwrInfo->HT40MaxOffset[rfPath][group] =
1712 (PROMContent[EEPROM_HT40_MAX_PWR_OFFSET_8723A +
1713 group] >> (rfPath * 4)) & 0xF;
1714
1715 pwrInfo->HT20MaxOffset[rfPath][group] =
1716 (PROMContent[EEPROM_HT20_MAX_PWR_OFFSET_8723A +
1717 group] >> (rfPath * 4)) & 0xF;
1718 }
1719 }
1720
1721 pwrInfo->TSSI_A[0] = PROMContent[EEPROM_TSSI_A_8723A];
1722 }
1723
1724 static u8 Hal_GetChnlGroup(u8 chnl)
1725 {
1726 u8 group = 0;
1727
1728 if (chnl < 3) /* Cjanel 1-3 */
1729 group = 0;
1730 else if (chnl < 9) /* Channel 4-9 */
1731 group = 1;
1732 else /* Channel 10-14 */
1733 group = 2;
1734
1735 return group;
1736 }
1737
1738 void
1739 Hal_EfuseParsetxpowerinfo_8723A(struct rtw_adapter *padapter,
1740 u8 *PROMContent, bool AutoLoadFail)
1741 {
1742 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
1743 struct txpowerinfo pwrInfo;
1744 u8 rfPath, ch, group, rfPathMax = 1;
1745 u8 pwr, diff;
1746
1747 Hal_ReadPowerValueFromPROM_8723A(&pwrInfo, PROMContent, AutoLoadFail);
1748 for (rfPath = 0; rfPath < rfPathMax; rfPath++) {
1749 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
1750 group = Hal_GetChnlGroup(ch);
1751
1752 pHalData->TxPwrLevelCck[rfPath][ch] =
1753 pwrInfo.CCKIndex[rfPath][group];
1754 pHalData->TxPwrLevelHT40_1S[rfPath][ch] =
1755 pwrInfo.HT40_1SIndex[rfPath][group];
1756
1757 pHalData->TxPwrHt20Diff[rfPath][ch] =
1758 pwrInfo.HT20IndexDiff[rfPath][group];
1759 pHalData->TxPwrLegacyHtDiff[rfPath][ch] =
1760 pwrInfo.OFDMIndexDiff[rfPath][group];
1761 pHalData->PwrGroupHT20[rfPath][ch] =
1762 pwrInfo.HT20MaxOffset[rfPath][group];
1763 pHalData->PwrGroupHT40[rfPath][ch] =
1764 pwrInfo.HT40MaxOffset[rfPath][group];
1765
1766 pwr = pwrInfo.HT40_1SIndex[rfPath][group];
1767 diff = pwrInfo.HT40_2SIndexDiff[rfPath][group];
1768
1769 pHalData->TxPwrLevelHT40_2S[rfPath][ch] =
1770 (pwr > diff) ? (pwr - diff) : 0;
1771 }
1772 }
1773 for (rfPath = 0; rfPath < RF_PATH_MAX; rfPath++) {
1774 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
1775 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1776 ("RF(%u)-Ch(%u) [CCK / HT40_1S / HT40_2S] = "
1777 "[0x%x / 0x%x / 0x%x]\n",
1778 rfPath, ch,
1779 pHalData->TxPwrLevelCck[rfPath][ch],
1780 pHalData->TxPwrLevelHT40_1S[rfPath][ch],
1781 pHalData->TxPwrLevelHT40_2S[rfPath][ch]));
1782
1783 }
1784 }
1785 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
1786 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1787 ("RF-A Ht20 to HT40 Diff[%u] = 0x%x(%d)\n", ch,
1788 pHalData->TxPwrHt20Diff[RF_PATH_A][ch],
1789 pHalData->TxPwrHt20Diff[RF_PATH_A][ch]));
1790 }
1791 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++)
1792 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1793 ("RF-A Legacy to Ht40 Diff[%u] = 0x%x\n", ch,
1794 pHalData->TxPwrLegacyHtDiff[RF_PATH_A][ch]));
1795 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
1796 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1797 ("RF-B Ht20 to HT40 Diff[%u] = 0x%x(%d)\n", ch,
1798 pHalData->TxPwrHt20Diff[RF_PATH_B][ch],
1799 pHalData->TxPwrHt20Diff[RF_PATH_B][ch]));
1800 }
1801 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++)
1802 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1803 ("RF-B Legacy to HT40 Diff[%u] = 0x%x\n", ch,
1804 pHalData->TxPwrLegacyHtDiff[RF_PATH_B][ch]));
1805 if (!AutoLoadFail) {
1806 struct registry_priv *registry_par = &padapter->registrypriv;
1807 if (registry_par->regulatory_tid == 0xff) {
1808 if (PROMContent[RF_OPTION1_8723A] == 0xff)
1809 pHalData->EEPROMRegulatory = 0;
1810 else
1811 pHalData->EEPROMRegulatory =
1812 PROMContent[RF_OPTION1_8723A] & 0x7;
1813 } else {
1814 pHalData->EEPROMRegulatory =
1815 registry_par->regulatory_tid;
1816 }
1817 } else {
1818 pHalData->EEPROMRegulatory = 0;
1819 }
1820 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1821 ("EEPROMRegulatory = 0x%x\n", pHalData->EEPROMRegulatory));
1822
1823 if (!AutoLoadFail)
1824 pHalData->bTXPowerDataReadFromEEPORM = true;
1825 }
1826
1827 void
1828 Hal_EfuseParseBTCoexistInfo_8723A(struct rtw_adapter *padapter,
1829 u8 *hwinfo, bool AutoLoadFail)
1830 {
1831 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
1832 u8 tempval;
1833 u32 tmpu4;
1834
1835 if (!AutoLoadFail) {
1836 tmpu4 = rtl8723au_read32(padapter, REG_MULTI_FUNC_CTRL);
1837 if (tmpu4 & BT_FUNC_EN)
1838 pHalData->EEPROMBluetoothCoexist = 1;
1839 else
1840 pHalData->EEPROMBluetoothCoexist = 0;
1841 pHalData->EEPROMBluetoothType = BT_RTL8723A;
1842
1843 /* The following need to be checked with newer version of */
1844 /* eeprom spec */
1845 tempval = hwinfo[RF_OPTION4_8723A];
1846 pHalData->EEPROMBluetoothAntNum = (tempval & 0x1);
1847 pHalData->EEPROMBluetoothAntIsolation = ((tempval & 0x10) >> 4);
1848 pHalData->EEPROMBluetoothRadioShared = ((tempval & 0x20) >> 5);
1849 } else {
1850 pHalData->EEPROMBluetoothCoexist = 0;
1851 pHalData->EEPROMBluetoothType = BT_RTL8723A;
1852 pHalData->EEPROMBluetoothAntNum = Ant_x2;
1853 pHalData->EEPROMBluetoothAntIsolation = 0;
1854 pHalData->EEPROMBluetoothRadioShared = BT_Radio_Shared;
1855 }
1856
1857 rtl8723a_BT_init_hal_vars(padapter);
1858 }
1859
1860 void
1861 Hal_EfuseParseEEPROMVer(struct rtw_adapter *padapter,
1862 u8 *hwinfo, bool AutoLoadFail)
1863 {
1864 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
1865
1866 if (!AutoLoadFail)
1867 pHalData->EEPROMVersion = hwinfo[EEPROM_VERSION_8723A];
1868 else
1869 pHalData->EEPROMVersion = 1;
1870 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1871 ("Hal_EfuseParseEEPROMVer(), EEVer = %d\n",
1872 pHalData->EEPROMVersion));
1873 }
1874
1875 void
1876 rtl8723a_EfuseParseChnlPlan(struct rtw_adapter *padapter,
1877 u8 *hwinfo, bool AutoLoadFail)
1878 {
1879 padapter->mlmepriv.ChannelPlan =
1880 hal_com_get_channel_plan23a(padapter, hwinfo ?
1881 hwinfo[EEPROM_ChannelPlan_8723A]:0xFF,
1882 padapter->registrypriv.channel_plan,
1883 RT_CHANNEL_DOMAIN_WORLD_WIDE_13,
1884 AutoLoadFail);
1885
1886 DBG_8723A("mlmepriv.ChannelPlan = 0x%02x\n",
1887 padapter->mlmepriv.ChannelPlan);
1888 }
1889
1890 void
1891 Hal_EfuseParseCustomerID(struct rtw_adapter *padapter,
1892 u8 *hwinfo, bool AutoLoadFail)
1893 {
1894 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
1895
1896 if (!AutoLoadFail) {
1897 pHalData->EEPROMCustomerID = hwinfo[EEPROM_CustomID_8723A];
1898 pHalData->EEPROMSubCustomerID =
1899 hwinfo[EEPROM_SubCustomID_8723A];
1900 } else {
1901 pHalData->EEPROMCustomerID = 0;
1902 pHalData->EEPROMSubCustomerID = 0;
1903 }
1904 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1905 ("EEPROM Customer ID: 0x%2x\n", pHalData->EEPROMCustomerID));
1906 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1907 ("EEPROM SubCustomer ID: 0x%02x\n",
1908 pHalData->EEPROMSubCustomerID));
1909 }
1910
1911 void
1912 Hal_EfuseParseAntennaDiversity(struct rtw_adapter *padapter,
1913 u8 *hwinfo, bool AutoLoadFail)
1914 {
1915 }
1916
1917 void
1918 Hal_EfuseParseRateIndicationOption(struct rtw_adapter *padapter,
1919 u8 *hwinfo, bool AutoLoadFail)
1920 {
1921 }
1922
1923 void
1924 Hal_EfuseParseXtal_8723A(struct rtw_adapter *pAdapter,
1925 u8 *hwinfo, u8 AutoLoadFail)
1926 {
1927 struct hal_data_8723a *pHalData = GET_HAL_DATA(pAdapter);
1928
1929 if (!AutoLoadFail) {
1930 pHalData->CrystalCap = hwinfo[EEPROM_XTAL_K_8723A];
1931 if (pHalData->CrystalCap == 0xFF)
1932 pHalData->CrystalCap = EEPROM_Default_CrystalCap_8723A;
1933 } else {
1934 pHalData->CrystalCap = EEPROM_Default_CrystalCap_8723A;
1935 }
1936 RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1937 ("%s: CrystalCap = 0x%2x\n", __func__,
1938 pHalData->CrystalCap));
1939 }
1940
1941 void
1942 Hal_EfuseParseThermalMeter_8723A(struct rtw_adapter *padapter,
1943 u8 *PROMContent, bool AutoloadFail)
1944 {
1945 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
1946
1947 /* */
1948 /* ThermalMeter from EEPROM */
1949 /* */
1950 if (AutoloadFail == false)
1951 pHalData->EEPROMThermalMeter =
1952 PROMContent[EEPROM_THERMAL_METER_8723A];
1953 else
1954 pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
1955
1956 if ((pHalData->EEPROMThermalMeter == 0xff) || (AutoloadFail == true)) {
1957 pHalData->bAPKThermalMeterIgnore = true;
1958 pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter;
1959 }
1960
1961 DBG_8723A("%s: ThermalMeter = 0x%x\n", __func__,
1962 pHalData->EEPROMThermalMeter);
1963 }
1964
1965 void Hal_InitChannelPlan23a(struct rtw_adapter *padapter)
1966 {
1967 }
1968
1969 static void rtl8723a_cal_txdesc_chksum(struct tx_desc *ptxdesc)
1970 {
1971 u16 *usPtr = (u16 *) ptxdesc;
1972 u32 count = 16; /* (32 bytes / 2 bytes per XOR) => 16 times */
1973 u32 index;
1974 u16 checksum = 0;
1975
1976 /* Clear first */
1977 ptxdesc->txdw7 &= cpu_to_le32(0xffff0000);
1978
1979 for (index = 0; index < count; index++) {
1980 checksum ^= le16_to_cpu(*(usPtr + index));
1981 }
1982
1983 ptxdesc->txdw7 |= cpu_to_le32(checksum & 0x0000ffff);
1984 }
1985
1986 static void fill_txdesc_sectype(struct pkt_attrib *pattrib,
1987 struct txdesc_8723a *ptxdesc)
1988 {
1989 if ((pattrib->encrypt > 0) && !pattrib->bswenc) {
1990 switch (pattrib->encrypt) {
1991 /* SEC_TYPE */
1992 case WLAN_CIPHER_SUITE_WEP40:
1993 case WLAN_CIPHER_SUITE_WEP104:
1994 case WLAN_CIPHER_SUITE_TKIP:
1995 ptxdesc->sectype = 1;
1996 break;
1997
1998 case WLAN_CIPHER_SUITE_CCMP:
1999 ptxdesc->sectype = 3;
2000 break;
2001
2002 case 0:
2003 default:
2004 break;
2005 }
2006 }
2007 }
2008
2009 static void fill_txdesc_vcs(struct pkt_attrib *pattrib,
2010 struct txdesc_8723a *ptxdesc)
2011 {
2012 /* DBG_8723A("cvs_mode =%d\n", pattrib->vcs_mode); */
2013
2014 switch (pattrib->vcs_mode) {
2015 case RTS_CTS:
2016 ptxdesc->rtsen = 1;
2017 break;
2018
2019 case CTS_TO_SELF:
2020 ptxdesc->cts2self = 1;
2021 break;
2022
2023 case NONE_VCS:
2024 default:
2025 break;
2026 }
2027
2028 if (pattrib->vcs_mode) {
2029 ptxdesc->hw_rts_en = 1; /* ENABLE HW RTS */
2030
2031 /* Set RTS BW */
2032 if (pattrib->ht_en) {
2033 if (pattrib->bwmode & HT_CHANNEL_WIDTH_40)
2034 ptxdesc->rts_bw = 1;
2035
2036 switch (pattrib->ch_offset) {
2037 case HAL_PRIME_CHNL_OFFSET_DONT_CARE:
2038 ptxdesc->rts_sc = 0;
2039 break;
2040
2041 case HAL_PRIME_CHNL_OFFSET_LOWER:
2042 ptxdesc->rts_sc = 1;
2043 break;
2044
2045 case HAL_PRIME_CHNL_OFFSET_UPPER:
2046 ptxdesc->rts_sc = 2;
2047 break;
2048
2049 default:
2050 ptxdesc->rts_sc = 3; /* Duplicate */
2051 break;
2052 }
2053 }
2054 }
2055 }
2056
2057 static void fill_txdesc_phy(struct pkt_attrib *pattrib,
2058 struct txdesc_8723a *ptxdesc)
2059 {
2060 if (pattrib->ht_en) {
2061 if (pattrib->bwmode & HT_CHANNEL_WIDTH_40)
2062 ptxdesc->data_bw = 1;
2063
2064 switch (pattrib->ch_offset) {
2065 case HAL_PRIME_CHNL_OFFSET_DONT_CARE:
2066 ptxdesc->data_sc = 0;
2067 break;
2068
2069 case HAL_PRIME_CHNL_OFFSET_LOWER:
2070 ptxdesc->data_sc = 1;
2071 break;
2072
2073 case HAL_PRIME_CHNL_OFFSET_UPPER:
2074 ptxdesc->data_sc = 2;
2075 break;
2076
2077 default:
2078 ptxdesc->data_sc = 3; /* Duplicate */
2079 break;
2080 }
2081 }
2082 }
2083
2084 static void rtl8723a_fill_default_txdesc(struct xmit_frame *pxmitframe,
2085 u8 *pbuf)
2086 {
2087 struct rtw_adapter *padapter;
2088 struct hal_data_8723a *pHalData;
2089 struct dm_priv *pdmpriv;
2090 struct mlme_ext_priv *pmlmeext;
2091 struct mlme_ext_info *pmlmeinfo;
2092 struct pkt_attrib *pattrib;
2093 struct txdesc_8723a *ptxdesc;
2094 s32 bmcst;
2095
2096 padapter = pxmitframe->padapter;
2097 pHalData = GET_HAL_DATA(padapter);
2098 pdmpriv = &pHalData->dmpriv;
2099 pmlmeext = &padapter->mlmeextpriv;
2100 pmlmeinfo = &pmlmeext->mlmext_info;
2101
2102 pattrib = &pxmitframe->attrib;
2103 bmcst = is_multicast_ether_addr(pattrib->ra);
2104
2105 ptxdesc = (struct txdesc_8723a *)pbuf;
2106
2107 if (pxmitframe->frame_tag == DATA_FRAMETAG) {
2108 ptxdesc->macid = pattrib->mac_id; /* CAM_ID(MAC_ID) */
2109
2110 if (pattrib->ampdu_en == true)
2111 ptxdesc->agg_en = 1; /* AGG EN */
2112 else
2113 ptxdesc->bk = 1; /* AGG BK */
2114
2115 ptxdesc->qsel = pattrib->qsel;
2116 ptxdesc->rate_id = pattrib->raid;
2117
2118 fill_txdesc_sectype(pattrib, ptxdesc);
2119
2120 ptxdesc->seq = pattrib->seqnum;
2121
2122 if ((pattrib->ether_type != 0x888e) &&
2123 (pattrib->ether_type != 0x0806) &&
2124 (pattrib->dhcp_pkt != 1)) {
2125 /* Non EAP & ARP & DHCP type data packet */
2126
2127 fill_txdesc_vcs(pattrib, ptxdesc);
2128 fill_txdesc_phy(pattrib, ptxdesc);
2129
2130 ptxdesc->rtsrate = 8; /* RTS Rate = 24M */
2131 ptxdesc->data_ratefb_lmt = 0x1F;
2132 ptxdesc->rts_ratefb_lmt = 0xF;
2133
2134 /* use REG_INIDATA_RATE_SEL value */
2135 ptxdesc->datarate =
2136 pdmpriv->INIDATA_RATE[pattrib->mac_id];
2137
2138 } else {
2139 /* EAP data packet and ARP packet. */
2140 /* Use the 1M data rate to send the EAP/ARP packet. */
2141 /* This will maybe make the handshake smooth. */
2142
2143 ptxdesc->bk = 1; /* AGG BK */
2144 ptxdesc->userate = 1; /* driver uses rate */
2145 if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT)
2146 ptxdesc->data_short = 1;
2147 ptxdesc->datarate = MRateToHwRate23a(pmlmeext->tx_rate);
2148 }
2149 } else if (pxmitframe->frame_tag == MGNT_FRAMETAG) {
2150 /* RT_TRACE(_module_hal_xmit_c_, _drv_notice_,
2151 ("%s: MGNT_FRAMETAG\n", __func__)); */
2152
2153 ptxdesc->macid = pattrib->mac_id; /* CAM_ID(MAC_ID) */
2154 ptxdesc->qsel = pattrib->qsel;
2155 ptxdesc->rate_id = pattrib->raid; /* Rate ID */
2156 ptxdesc->seq = pattrib->seqnum;
2157 ptxdesc->userate = 1; /* driver uses rate, 1M */
2158 ptxdesc->rty_lmt_en = 1; /* retry limit enable */
2159 ptxdesc->data_rt_lmt = 6; /* retry limit = 6 */
2160
2161 /* CCX-TXRPT ack for xmit mgmt frames. */
2162 if (pxmitframe->ack_report)
2163 ptxdesc->ccx = 1;
2164
2165 ptxdesc->datarate = MRateToHwRate23a(pmlmeext->tx_rate);
2166 } else if (pxmitframe->frame_tag == TXAGG_FRAMETAG) {
2167 RT_TRACE(_module_hal_xmit_c_, _drv_warning_,
2168 ("%s: TXAGG_FRAMETAG\n", __func__));
2169 } else {
2170 RT_TRACE(_module_hal_xmit_c_, _drv_warning_,
2171 ("%s: frame_tag = 0x%x\n", __func__,
2172 pxmitframe->frame_tag));
2173
2174 ptxdesc->macid = 4; /* CAM_ID(MAC_ID) */
2175 ptxdesc->rate_id = 6; /* Rate ID */
2176 ptxdesc->seq = pattrib->seqnum;
2177 ptxdesc->userate = 1; /* driver uses rate */
2178 ptxdesc->datarate = MRateToHwRate23a(pmlmeext->tx_rate);
2179 }
2180
2181 ptxdesc->pktlen = pattrib->last_txcmdsz;
2182 ptxdesc->offset = TXDESC_SIZE + OFFSET_SZ;
2183 if (bmcst)
2184 ptxdesc->bmc = 1;
2185 ptxdesc->ls = 1;
2186 ptxdesc->fs = 1;
2187 ptxdesc->own = 1;
2188
2189 /* 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS. */
2190 /* (1) The sequence number of each non-Qos frame / broadcast /
2191 * multicast / mgnt frame should be controled by Hw because Fw
2192 * will also send null data which we cannot control when Fw LPS enable.
2193 * --> default enable non-Qos data sequense number.
2194 2010.06.23. by tynli. */
2195 /* (2) Enable HW SEQ control for beacon packet,
2196 * because we use Hw beacon. */
2197 /* (3) Use HW Qos SEQ to control the seq num of Ext port
2198 * non-Qos packets. */
2199 /* 2010.06.23. Added by tynli. */
2200 if (!pattrib->qos_en) {
2201 /* Hw set sequence number */
2202 ptxdesc->hwseq_en = 1; /* HWSEQ_EN */
2203 ptxdesc->hwseq_sel = 0; /* HWSEQ_SEL */
2204 }
2205 }
2206
2207 /*
2208 * Description:
2209 *
2210 * Parameters:
2211 * pxmitframe xmitframe
2212 * pbuf where to fill tx desc
2213 */
2214 void rtl8723a_update_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf)
2215 {
2216 struct tx_desc *pdesc;
2217
2218 pdesc = (struct tx_desc *)pbuf;
2219 memset(pdesc, 0, sizeof(struct tx_desc));
2220
2221 rtl8723a_fill_default_txdesc(pxmitframe, pbuf);
2222
2223 pdesc->txdw0 = cpu_to_le32(pdesc->txdw0);
2224 pdesc->txdw1 = cpu_to_le32(pdesc->txdw1);
2225 pdesc->txdw2 = cpu_to_le32(pdesc->txdw2);
2226 pdesc->txdw3 = cpu_to_le32(pdesc->txdw3);
2227 pdesc->txdw4 = cpu_to_le32(pdesc->txdw4);
2228 pdesc->txdw5 = cpu_to_le32(pdesc->txdw5);
2229 pdesc->txdw6 = cpu_to_le32(pdesc->txdw6);
2230 pdesc->txdw7 = cpu_to_le32(pdesc->txdw7);
2231 rtl8723a_cal_txdesc_chksum(pdesc);
2232 }
2233
2234 /*
2235 * Description: In normal chip, we should send some packet to Hw which
2236 * will be used by Fw in FW LPS mode. The function is to fill the Tx
2237 * descriptor of this packets, then
2238 */
2239 /* Fw can tell Hw to send these packet derectly. */
2240 /* Added by tynli. 2009.10.15. */
2241 /* */
2242 void rtl8723a_fill_fake_txdesc(struct rtw_adapter *padapter, u8 *pDesc,
2243 u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull)
2244 {
2245 struct tx_desc *ptxdesc;
2246
2247 /* Clear all status */
2248 ptxdesc = (struct tx_desc *)pDesc;
2249 memset(pDesc, 0, TXDESC_SIZE);
2250
2251 /* offset 0 */
2252 /* own, bFirstSeg, bLastSeg; */
2253 ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
2254
2255 /* 32 bytes for TX Desc */
2256 ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) <<
2257 OFFSET_SHT) & 0x00ff0000);
2258
2259 /* Buffer size + command header */
2260 ptxdesc->txdw0 |= cpu_to_le32(BufferLen & 0x0000ffff);
2261
2262 /* offset 4 */
2263 /* Fixed queue of Mgnt queue */
2264 ptxdesc->txdw1 |= cpu_to_le32((QSLT_MGNT << QSEL_SHT) & 0x00001f00);
2265
2266 /* Set NAVUSEHDR to prevent Ps-poll AId filed to be changed
2267 to error vlaue by Hw. */
2268 if (IsPsPoll) {
2269 ptxdesc->txdw1 |= cpu_to_le32(NAVUSEHDR);
2270 } else {
2271 /* Hw set sequence number */
2272 ptxdesc->txdw4 |= cpu_to_le32(BIT(7));
2273 /* set bit3 to 1. Suugested by TimChen. 2009.12.29. */
2274 ptxdesc->txdw3 |= cpu_to_le32((8 << 28));
2275 }
2276
2277 if (true == IsBTQosNull) {
2278 ptxdesc->txdw2 |= cpu_to_le32(BIT(23)); /* BT NULL */
2279 }
2280
2281 /* offset 16 */
2282 ptxdesc->txdw4 |= cpu_to_le32(BIT(8)); /* driver uses rate */
2283
2284 /* USB interface drop packet if the checksum of descriptor isn't
2285 correct. */
2286 /* Using this checksum can let hardware recovery from packet bulk
2287 out error (e.g. Cancel URC, Bulk out error.). */
2288 rtl8723a_cal_txdesc_chksum(ptxdesc);
2289 }
2290
2291 void hw_var_set_opmode(struct rtw_adapter *padapter, u8 mode)
2292 {
2293 u8 val8;
2294
2295 if (mode == MSR_INFRA || mode == MSR_NOLINK) {
2296 StopTxBeacon(padapter);
2297
2298 /* disable atim wnd */
2299 val8 = DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_ATIM;
2300 SetBcnCtrlReg23a(padapter, val8, ~val8);
2301 } else if (mode == MSR_ADHOC) {
2302 ResumeTxBeacon(padapter);
2303
2304 val8 = DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB;
2305 SetBcnCtrlReg23a(padapter, val8, ~val8);
2306 } else if (mode == MSR_AP) {
2307 /* add NULL Data and BT NULL Data Packets to FW RSVD Page */
2308 rtl8723a_set_BTCoex_AP_mode_FwRsvdPkt_cmd(padapter);
2309
2310 ResumeTxBeacon(padapter);
2311
2312 val8 = DIS_TSF_UDT | DIS_BCNQ_SUB;
2313 SetBcnCtrlReg23a(padapter, val8, ~val8);
2314
2315 /* Set RCR */
2316 /* rtl8723au_write32(padapter, REG_RCR, 0x70002a8e);
2317 CBSSID_DATA must set to 0 */
2318 /* CBSSID_DATA must set to 0 */
2319 rtl8723au_write32(padapter, REG_RCR, 0x7000228e);
2320 /* enable to rx data frame */
2321 rtl8723au_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
2322 /* enable to rx ps-poll */
2323 rtl8723au_write16(padapter, REG_RXFLTMAP1, 0x0400);
2324
2325 /* Beacon Control related register for first time */
2326 /* 2ms */
2327 rtl8723au_write8(padapter, REG_BCNDMATIM, 0x02);
2328 /* 5ms */
2329 rtl8723au_write8(padapter, REG_DRVERLYINT, 0x05);
2330 /* 10ms for port0 */
2331 rtl8723au_write8(padapter, REG_ATIMWND, 0x0a);
2332 rtl8723au_write16(padapter, REG_BCNTCFG, 0x00);
2333 rtl8723au_write16(padapter, REG_TBTT_PROHIBIT, 0xff04);
2334 /* +32767 (~32ms) */
2335 rtl8723au_write16(padapter, REG_TSFTR_SYN_OFFSET, 0x7fff);
2336
2337 /* reset TSF */
2338 rtl8723au_write8(padapter, REG_DUAL_TSF_RST, BIT(0));
2339
2340 /* enable BCN Function */
2341 /* don't enable update TSF (due to TSF update when
2342 beacon/probe rsp are received) */
2343 val8 = DIS_TSF_UDT | EN_BCN_FUNCTION |
2344 EN_TXBCN_RPT | DIS_BCNQ_SUB;
2345 SetBcnCtrlReg23a(padapter, val8, ~val8);
2346 }
2347
2348 val8 = rtl8723au_read8(padapter, MSR);
2349 val8 = (val8 & 0xC) | mode;
2350 rtl8723au_write8(padapter, MSR, val8);
2351 }
2352
2353 void hw_var_set_macaddr(struct rtw_adapter *padapter, u8 *val)
2354 {
2355 u8 idx = 0;
2356 u32 reg_macid;
2357
2358 reg_macid = REG_MACID;
2359
2360 for (idx = 0; idx < 6; idx++)
2361 rtl8723au_write8(padapter, (reg_macid + idx), val[idx]);
2362 }
2363
2364 void hw_var_set_bssid(struct rtw_adapter *padapter, u8 *val)
2365 {
2366 u8 idx = 0;
2367 u32 reg_bssid;
2368
2369 reg_bssid = REG_BSSID;
2370
2371 for (idx = 0; idx < 6; idx++)
2372 rtl8723au_write8(padapter, (reg_bssid + idx), val[idx]);
2373 }
2374
2375 void hw_var_set_correct_tsf(struct rtw_adapter *padapter)
2376 {
2377 u64 tsf;
2378 u32 reg_tsftr;
2379 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
2380 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
2381
2382 /* tsf = pmlmeext->TSFValue - ((u32)pmlmeext->TSFValue %
2383 (pmlmeinfo->bcn_interval*1024)) - 1024; us */
2384 tsf = pmlmeext->TSFValue -
2385 do_div(pmlmeext->TSFValue,
2386 (pmlmeinfo->bcn_interval * 1024)) - 1024; /* us */
2387
2388 if (((pmlmeinfo->state & 0x03) == MSR_ADHOC) ||
2389 ((pmlmeinfo->state & 0x03) == MSR_AP)) {
2390 /* pHalData->RegTxPause |= STOP_BCNQ;BIT(6) */
2391 /* rtl8723au_write8(padapter, REG_TXPAUSE,
2392 (rtl8723au_read8(Adapter, REG_TXPAUSE)|BIT(6))); */
2393 StopTxBeacon(padapter);
2394 }
2395
2396 reg_tsftr = REG_TSFTR;
2397
2398 /* disable related TSF function */
2399 SetBcnCtrlReg23a(padapter, 0, EN_BCN_FUNCTION);
2400
2401 rtl8723au_write32(padapter, reg_tsftr, tsf);
2402 rtl8723au_write32(padapter, reg_tsftr + 4, tsf >> 32);
2403
2404 /* enable related TSF function */
2405 SetBcnCtrlReg23a(padapter, EN_BCN_FUNCTION, 0);
2406
2407 if (((pmlmeinfo->state & 0x03) == MSR_ADHOC) ||
2408 ((pmlmeinfo->state & 0x03) == MSR_AP))
2409 ResumeTxBeacon(padapter);
2410 }
2411
2412 void hw_var_set_mlme_disconnect(struct rtw_adapter *padapter)
2413 {
2414 /* reject all data frames */
2415 rtl8723au_write16(padapter, REG_RXFLTMAP2, 0);
2416
2417 /* reset TSF */
2418 rtl8723au_write8(padapter, REG_DUAL_TSF_RST, BIT(0));
2419
2420 /* disable update TSF */
2421 SetBcnCtrlReg23a(padapter, DIS_TSF_UDT, 0);
2422 }
2423
2424 void hw_var_set_mlme_join(struct rtw_adapter *padapter, u8 type)
2425 {
2426 u8 RetryLimit = 0x30;
2427
2428 struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter);
2429 struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
2430
2431 if (type == 0) { /* prepare to join */
2432 u32 v32;
2433
2434 /* enable to rx data frame.Accept all data frame */
2435 /* rtl8723au_write32(padapter, REG_RCR,
2436 rtl8723au_read32(padapter, REG_RCR)|RCR_ADF); */
2437 rtl8723au_write16(padapter, REG_RXFLTMAP2, 0xFFFF);
2438
2439 v32 = rtl8723au_read32(padapter, REG_RCR);
2440 v32 |= RCR_CBSSID_DATA | RCR_CBSSID_BCN;
2441 rtl8723au_write32(padapter, REG_RCR, v32);
2442
2443 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == true)
2444 RetryLimit =
2445 (pHalData->CustomerID == RT_CID_CCX) ? 7 : 48;
2446 else /* Ad-hoc Mode */
2447 RetryLimit = 0x7;
2448 } else if (type == 1) { /* joinbss_event callback when join res < 0 */
2449 /* config RCR to receive different BSSID & not to
2450 receive data frame during linking */
2451 rtl8723au_write16(padapter, REG_RXFLTMAP2, 0);
2452 } else if (type == 2) { /* sta add event callback */
2453 /* enable update TSF */
2454 SetBcnCtrlReg23a(padapter, 0, DIS_TSF_UDT);
2455
2456 if (check_fwstate(pmlmepriv,
2457 WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) {
2458 /* fixed beacon issue for 8191su........... */
2459 rtl8723au_write8(padapter, 0x542, 0x02);
2460 RetryLimit = 0x7;
2461 }
2462 }
2463
2464 rtl8723au_write16(padapter, REG_RL,
2465 RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit <<
2466 RETRY_LIMIT_LONG_SHIFT);
2467
2468 switch (type) {
2469 case 0:
2470 /* prepare to join */
2471 rtl8723a_BT_wifiassociate_notify(padapter, true);
2472 break;
2473 case 1:
2474 /* joinbss_event callback when join res < 0 */
2475 rtl8723a_BT_wifiassociate_notify(padapter, false);
2476 break;
2477 case 2:
2478 /* sta add event callback */
2479 /* BT_WifiMediaStatusNotify(padapter, RT_MEDIA_CONNECT); */
2480 break;
2481 }
2482 }
Linux kernel - Deliverables
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