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staging: add rts_pstor for Realtek PCIE cardreader
[deliverable/linux.git] / drivers / staging / rts_pstor / xd.c
1 /* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * wwang (wei_wang@realsil.com.cn)
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
21 */
22
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
26
27 #include "rtsx.h"
28 #include "rtsx_transport.h"
29 #include "rtsx_scsi.h"
30 #include "rtsx_card.h"
31 #include "xd.h"
32
33 static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no);
34 static int xd_init_page(struct rtsx_chip *chip, u32 phy_blk, u16 logoff, u8 start_page, u8 end_page);
35
36 static inline void xd_set_err_code(struct rtsx_chip *chip, u8 err_code)
37 {
38 struct xd_info *xd_card = &(chip->xd_card);
39
40 xd_card->err_code = err_code;
41 }
42
43 static inline int xd_check_err_code(struct rtsx_chip *chip, u8 err_code)
44 {
45 struct xd_info *xd_card = &(chip->xd_card);
46
47 return (xd_card->err_code == err_code);
48 }
49
50 static int xd_set_init_para(struct rtsx_chip *chip)
51 {
52 struct xd_info *xd_card = &(chip->xd_card);
53 int retval;
54
55 if (chip->asic_code) {
56 xd_card->xd_clock = 47;
57 } else {
58 xd_card->xd_clock = CLK_50;
59 }
60
61 retval = switch_clock(chip, xd_card->xd_clock);
62 if (retval != STATUS_SUCCESS) {
63 TRACE_RET(chip, STATUS_FAIL);
64 }
65
66 return STATUS_SUCCESS;
67 }
68
69 static int xd_switch_clock(struct rtsx_chip *chip)
70 {
71 struct xd_info *xd_card = &(chip->xd_card);
72 int retval;
73
74 retval = select_card(chip, XD_CARD);
75 if (retval != STATUS_SUCCESS) {
76 TRACE_RET(chip, STATUS_FAIL);
77 }
78
79 retval = switch_clock(chip, xd_card->xd_clock);
80 if (retval != STATUS_SUCCESS) {
81 TRACE_RET(chip, STATUS_FAIL);
82 }
83
84 return STATUS_SUCCESS;
85 }
86
87 static int xd_read_id(struct rtsx_chip *chip, u8 id_cmd, u8 *id_buf, u8 buf_len)
88 {
89 int retval, i;
90 u8 *ptr;
91
92 rtsx_init_cmd(chip);
93
94 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, id_cmd);
95 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_READ_ID);
96 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
97
98 for (i = 0; i < 4; i++) {
99 rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_ADDRESS1 + i), 0, 0);
100 }
101
102 retval = rtsx_send_cmd(chip, XD_CARD, 20);
103 if (retval < 0) {
104 TRACE_RET(chip, STATUS_FAIL);
105 }
106
107 ptr = rtsx_get_cmd_data(chip) + 1;
108 if (id_buf && buf_len) {
109 if (buf_len > 4)
110 buf_len = 4;
111 memcpy(id_buf, ptr, buf_len);
112 }
113
114 return STATUS_SUCCESS;
115 }
116
117 static void xd_assign_phy_addr(struct rtsx_chip *chip, u32 addr, u8 mode)
118 {
119 struct xd_info *xd_card = &(chip->xd_card);
120
121 switch (mode) {
122 case XD_RW_ADDR:
123 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, 0);
124 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF, (u8)addr);
125 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2, 0xFF, (u8)(addr >> 8));
126 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS3, 0xFF, (u8)(addr >> 16));
127 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF,
128 xd_card->addr_cycle | XD_CALC_ECC | XD_BA_NO_TRANSFORM);
129 break;
130
131 case XD_ERASE_ADDR:
132 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, (u8)addr);
133 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF, (u8)(addr >> 8));
134 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2, 0xFF, (u8)(addr >> 16));
135 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF,
136 (xd_card->addr_cycle - 1) | XD_CALC_ECC | XD_BA_NO_TRANSFORM);
137 break;
138
139 default:
140 break;
141 }
142 }
143
144 static int xd_read_redundant(struct rtsx_chip *chip, u32 page_addr, u8 *buf, int buf_len)
145 {
146 int retval, i;
147
148 rtsx_init_cmd(chip);
149
150 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
151
152 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_READ_REDUNDANT);
153 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
154
155 for (i = 0; i < 6; i++) {
156 rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_PAGE_STATUS + i), 0, 0);
157 }
158 for (i = 0; i < 4; i++) {
159 rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_RESERVED0 + i), 0, 0);
160 }
161 rtsx_add_cmd(chip, READ_REG_CMD, XD_PARITY, 0, 0);
162
163 retval = rtsx_send_cmd(chip, XD_CARD, 500);
164 if (retval < 0) {
165 TRACE_RET(chip, STATUS_FAIL);
166 }
167
168 if (buf && buf_len) {
169 u8 *ptr = rtsx_get_cmd_data(chip) + 1;
170
171 if (buf_len > 11)
172 buf_len = 11;
173 memcpy(buf, ptr, buf_len);
174 }
175
176 return STATUS_SUCCESS;
177 }
178
179 static int xd_read_data_from_ppb(struct rtsx_chip *chip, int offset, u8 *buf, int buf_len)
180 {
181 int retval, i;
182
183 if (!buf || (buf_len < 0)) {
184 TRACE_RET(chip, STATUS_FAIL);
185 }
186
187 rtsx_init_cmd(chip);
188
189 for (i = 0; i < buf_len; i++) {
190 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + offset + i, 0, 0);
191 }
192
193 retval = rtsx_send_cmd(chip, 0, 250);
194 if (retval < 0) {
195 rtsx_clear_xd_error(chip);
196 TRACE_RET(chip, STATUS_FAIL);
197 }
198
199 memcpy(buf, rtsx_get_cmd_data(chip), buf_len);
200
201 return STATUS_SUCCESS;
202 }
203
204 static int xd_read_cis(struct rtsx_chip *chip, u32 page_addr, u8 *buf, int buf_len)
205 {
206 int retval;
207 u8 reg;
208
209 if (!buf || (buf_len < 10)) {
210 TRACE_RET(chip, STATUS_FAIL);
211 }
212
213 rtsx_init_cmd(chip);
214
215 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
216
217 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
218 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
219 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS);
220
221 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_READ_PAGES);
222 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
223
224 retval = rtsx_send_cmd(chip, XD_CARD, 250);
225 if (retval == -ETIMEDOUT) {
226 rtsx_clear_xd_error(chip);
227 TRACE_RET(chip, STATUS_FAIL);
228 }
229
230 RTSX_READ_REG(chip, XD_PAGE_STATUS, &reg);
231 if (reg != XD_GPG) {
232 rtsx_clear_xd_error(chip);
233 TRACE_RET(chip, STATUS_FAIL);
234 }
235
236 RTSX_READ_REG(chip, XD_CTL, &reg);
237 if (!(reg & XD_ECC1_ERROR) || !(reg & XD_ECC1_UNCORRECTABLE)) {
238 retval = xd_read_data_from_ppb(chip, 0, buf, buf_len);
239 if (retval != STATUS_SUCCESS) {
240 TRACE_RET(chip, STATUS_FAIL);
241 }
242 if (reg & XD_ECC1_ERROR) {
243 u8 ecc_bit, ecc_byte;
244
245 RTSX_READ_REG(chip, XD_ECC_BIT1, &ecc_bit);
246 RTSX_READ_REG(chip, XD_ECC_BYTE1, &ecc_byte);
247
248 RTSX_DEBUGP("ECC_BIT1 = 0x%x, ECC_BYTE1 = 0x%x\n", ecc_bit, ecc_byte);
249 if (ecc_byte < buf_len) {
250 RTSX_DEBUGP("Before correct: 0x%x\n", buf[ecc_byte]);
251 buf[ecc_byte] ^= (1 << ecc_bit);
252 RTSX_DEBUGP("After correct: 0x%x\n", buf[ecc_byte]);
253 }
254 }
255 } else if (!(reg & XD_ECC2_ERROR) || !(reg & XD_ECC2_UNCORRECTABLE)) {
256 rtsx_clear_xd_error(chip);
257
258 retval = xd_read_data_from_ppb(chip, 256, buf, buf_len);
259 if (retval != STATUS_SUCCESS) {
260 TRACE_RET(chip, STATUS_FAIL);
261 }
262 if (reg & XD_ECC2_ERROR) {
263 u8 ecc_bit, ecc_byte;
264
265 RTSX_READ_REG(chip, XD_ECC_BIT2, &ecc_bit);
266 RTSX_READ_REG(chip, XD_ECC_BYTE2, &ecc_byte);
267
268 RTSX_DEBUGP("ECC_BIT2 = 0x%x, ECC_BYTE2 = 0x%x\n", ecc_bit, ecc_byte);
269 if (ecc_byte < buf_len) {
270 RTSX_DEBUGP("Before correct: 0x%x\n", buf[ecc_byte]);
271 buf[ecc_byte] ^= (1 << ecc_bit);
272 RTSX_DEBUGP("After correct: 0x%x\n", buf[ecc_byte]);
273 }
274 }
275 } else {
276 rtsx_clear_xd_error(chip);
277 TRACE_RET(chip, STATUS_FAIL);
278 }
279
280 return STATUS_SUCCESS;
281 }
282
283 static void xd_fill_pull_ctl_disable(struct rtsx_chip *chip)
284 {
285 if (CHECK_PID(chip, 0x5209)) {
286 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
287 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
288 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0xD5);
289 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
290 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
291 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x15);
292 } else if (CHECK_PID(chip, 0x5208)) {
293 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
294 XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD);
295 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
296 XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD);
297 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
298 XD_WP_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
299 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
300 XD_RDY_PD | XD_WE_PD | XD_RE_PD | XD_ALE_PD);
301 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
302 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
303 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, MS_D5_PD | MS_D4_PD);
304 } else if (CHECK_PID(chip, 0x5288)) {
305 if (CHECK_BARO_PKG(chip, QFN)) {
306 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
307 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
308 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x4B);
309 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x69);
310 }
311 }
312 }
313
314 static void xd_fill_pull_ctl_stage1_barossa(struct rtsx_chip *chip)
315 {
316 if (CHECK_BARO_PKG(chip, QFN)) {
317 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
318 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
319 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x4B);
320 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
321 }
322 }
323
324 static void xd_fill_pull_ctl_enable(struct rtsx_chip *chip)
325 {
326 if (CHECK_PID(chip, 0x5209)) {
327 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0xAA);
328 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
329 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0xD5);
330 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
331 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
332 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x15);
333 } else if (CHECK_PID(chip, 0x5208)) {
334 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
335 XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD);
336 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
337 XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD);
338 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
339 XD_WP_PD | XD_CE_PU | XD_CLE_PD | XD_CD_PU);
340 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
341 XD_RDY_PU | XD_WE_PU | XD_RE_PU | XD_ALE_PD);
342 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
343 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
344 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, MS_D5_PD | MS_D4_PD);
345 } else if (CHECK_PID(chip, 0x5288)) {
346 if (CHECK_BARO_PKG(chip, QFN)) {
347 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
348 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
349 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x53);
350 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0xA9);
351 }
352 }
353 }
354
355 static int xd_pull_ctl_disable(struct rtsx_chip *chip)
356 {
357 if (CHECK_PID(chip, 0x5209)) {
358 RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55);
359 RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55);
360 RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0xD5);
361 RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, 0x55);
362 RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF, 0x55);
363 RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF, 0x15);
364 } else if (CHECK_PID(chip, 0x5208)) {
365 RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF,
366 XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD);
367 RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF,
368 XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD);
369 RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF,
370 XD_WP_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
371 RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF,
372 XD_RDY_PD | XD_WE_PD | XD_RE_PD | XD_ALE_PD);
373 RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF,
374 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
375 RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF, MS_D5_PD | MS_D4_PD);
376 } else if (CHECK_PID(chip, 0x5288)) {
377 if (CHECK_BARO_PKG(chip, QFN)) {
378 RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55);
379 RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55);
380 RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0x4B);
381 RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, 0x69);
382 }
383 }
384
385 return STATUS_SUCCESS;
386 }
387
388 static void xd_clear_dma_buffer(struct rtsx_chip *chip)
389 {
390 if (CHECK_PID(chip, 0x5209)) {
391 int retval;
392 u8 *buf;
393
394 RTSX_DEBUGP("xD ECC error, dummy write!\n");
395
396 buf = (u8 *)rtsx_alloc_dma_buf(chip, 512, GFP_KERNEL);
397 if (!buf) {
398 return;
399 }
400
401 rtsx_init_cmd(chip);
402
403 trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512);
404
405 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL);
406 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, SD_CLK_EN);
407 if (chip->asic_code) {
408 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0xAA);
409 } else {
410 rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL,
411 FPGA_SD_PULL_CTL_BIT, 0);
412 }
413
414 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, 0x00);
415 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, 0x02);
416 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1);
417 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0);
418 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_CFG1, 0x03, SD_BUS_WIDTH_4);
419
420 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
421
422 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_TRANSFER, 0xFF,
423 SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
424 rtsx_add_cmd(chip, CHECK_REG_CMD, SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END);
425
426 rtsx_send_cmd_no_wait(chip);
427
428 retval = rtsx_transfer_data(chip, SD_CARD, buf, 512, 0, DMA_TO_DEVICE, 100);
429 if (retval < 0) {
430 u8 val;
431
432 rtsx_read_register(chip, SD_STAT1, &val);
433 RTSX_DEBUGP("SD_STAT1: 0x%x\n", val);
434
435 rtsx_read_register(chip, SD_STAT2, &val);
436 RTSX_DEBUGP("SD_STAT2: 0x%x\n", val);
437
438 rtsx_read_register(chip, SD_BUS_STAT, &val);
439 RTSX_DEBUGP("SD_BUS_STAT: 0x%x\n", val);
440
441 rtsx_write_register(chip, CARD_STOP, SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
442 }
443
444 rtsx_free_dma_buf(chip, buf);
445
446 if (chip->asic_code) {
447 rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF, 0x55);
448 } else {
449 rtsx_write_register(chip, FPGA_PULL_CTL,
450 FPGA_SD_PULL_CTL_BIT, FPGA_SD_PULL_CTL_BIT);
451 }
452 rtsx_write_register(chip, CARD_SELECT, 0x07, XD_MOD_SEL);
453 rtsx_write_register(chip, CARD_CLK_EN, SD_CLK_EN, 0);
454 }
455 }
456
457 static int reset_xd(struct rtsx_chip *chip)
458 {
459 struct xd_info *xd_card = &(chip->xd_card);
460 int retval, i, j;
461 u8 *ptr, id_buf[4], redunt[11];
462
463 retval = select_card(chip, XD_CARD);
464 if (retval != STATUS_SUCCESS) {
465 TRACE_RET(chip, STATUS_FAIL);
466 }
467
468 rtsx_init_cmd(chip);
469
470 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, 0xFF, XD_PGSTS_NOT_FF);
471 if (chip->asic_code) {
472 if (!CHECK_PID(chip, 0x5288)) {
473 xd_fill_pull_ctl_disable(chip);
474 } else {
475 xd_fill_pull_ctl_stage1_barossa(chip);
476 }
477 } else {
478 rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
479 (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN3) | 0x20);
480 }
481
482 if (!chip->ft2_fast_mode) {
483 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_INIT, XD_NO_AUTO_PWR_OFF, 0);
484 }
485
486 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, 0);
487
488 retval = rtsx_send_cmd(chip, XD_CARD, 100);
489 if (retval < 0) {
490 TRACE_RET(chip, STATUS_FAIL);
491 }
492
493 if (!chip->ft2_fast_mode) {
494 retval = card_power_off(chip, XD_CARD);
495 if (retval != STATUS_SUCCESS) {
496 TRACE_RET(chip, STATUS_FAIL);
497 }
498
499 wait_timeout(250);
500
501 if (CHECK_PID(chip, 0x5209)) {
502 RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0xAA);
503 }
504
505 rtsx_init_cmd(chip);
506
507 if (chip->asic_code) {
508 xd_fill_pull_ctl_enable(chip);
509 } else {
510 rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
511 (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN2) | 0x20);
512 }
513
514 retval = rtsx_send_cmd(chip, XD_CARD, 100);
515 if (retval < 0) {
516 TRACE_RET(chip, STATUS_FAIL);
517 }
518
519 retval = card_power_on(chip, XD_CARD);
520 if (retval != STATUS_SUCCESS) {
521 TRACE_RET(chip, STATUS_FAIL);
522 }
523
524 #ifdef SUPPORT_OCP
525 wait_timeout(50);
526 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
527 RTSX_DEBUGP("Over current, OCPSTAT is 0x%x\n", chip->ocp_stat);
528 TRACE_RET(chip, STATUS_FAIL);
529 }
530 #endif
531 }
532
533 rtsx_init_cmd(chip);
534
535 if (chip->ft2_fast_mode) {
536 if (chip->asic_code) {
537 xd_fill_pull_ctl_enable(chip);
538 } else {
539 rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
540 (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN2) | 0x20);
541 }
542 }
543
544 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, XD_OUTPUT_EN);
545 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CTL, XD_CE_DISEN, XD_CE_DISEN);
546
547 retval = rtsx_send_cmd(chip, XD_CARD, 100);
548 if (retval < 0) {
549 TRACE_RET(chip, STATUS_FAIL);
550 }
551
552 if (!chip->ft2_fast_mode) {
553 wait_timeout(200);
554 }
555
556 retval = xd_set_init_para(chip);
557 if (retval != STATUS_SUCCESS) {
558 TRACE_RET(chip, STATUS_FAIL);
559 }
560
561 /* Read ID to check if the timing setting is right */
562 for (i = 0; i < 4; i++) {
563 rtsx_init_cmd(chip);
564
565 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DTCTL, 0xFF,
566 XD_TIME_SETUP_STEP * 3 + XD_TIME_RW_STEP * (2 + i) + XD_TIME_RWN_STEP * i);
567 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CATCTL, 0xFF,
568 XD_TIME_SETUP_STEP * 3 + XD_TIME_RW_STEP * (4 + i) + XD_TIME_RWN_STEP * (3 + i));
569
570 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_RESET);
571 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
572
573 rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
574 rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0);
575
576 retval = rtsx_send_cmd(chip, XD_CARD, 100);
577 if (retval < 0) {
578 TRACE_RET(chip, STATUS_FAIL);
579 }
580
581 ptr = rtsx_get_cmd_data(chip) + 1;
582
583 RTSX_DEBUGP("XD_DAT: 0x%x, XD_CTL: 0x%x\n", ptr[0], ptr[1]);
584
585 if (((ptr[0] & READY_FLAG) != READY_STATE) || !(ptr[1] & XD_RDY)) {
586 continue;
587 }
588
589 retval = xd_read_id(chip, READ_ID, id_buf, 4);
590 if (retval != STATUS_SUCCESS) {
591 TRACE_RET(chip, STATUS_FAIL);
592 }
593
594 RTSX_DEBUGP("READ_ID: 0x%x 0x%x 0x%x 0x%x\n",
595 id_buf[0], id_buf[1], id_buf[2], id_buf[3]);
596
597 xd_card->device_code = id_buf[1];
598
599 /* Check if the xD card is supported */
600 switch (xd_card->device_code) {
601 case XD_4M_X8_512_1:
602 case XD_4M_X8_512_2:
603 xd_card->block_shift = 4;
604 xd_card->page_off = 0x0F;
605 xd_card->addr_cycle = 3;
606 xd_card->zone_cnt = 1;
607 xd_card->capacity = 8000;
608 XD_SET_4MB(xd_card);
609 break;
610 case XD_8M_X8_512:
611 xd_card->block_shift = 4;
612 xd_card->page_off = 0x0F;
613 xd_card->addr_cycle = 3;
614 xd_card->zone_cnt = 1;
615 xd_card->capacity = 16000;
616 break;
617 case XD_16M_X8_512:
618 XD_PAGE_512(xd_card);
619 xd_card->addr_cycle = 3;
620 xd_card->zone_cnt = 1;
621 xd_card->capacity = 32000;
622 break;
623 case XD_32M_X8_512:
624 XD_PAGE_512(xd_card);
625 xd_card->addr_cycle = 3;
626 xd_card->zone_cnt = 2;
627 xd_card->capacity = 64000;
628 break;
629 case XD_64M_X8_512:
630 XD_PAGE_512(xd_card);
631 xd_card->addr_cycle = 4;
632 xd_card->zone_cnt = 4;
633 xd_card->capacity = 128000;
634 break;
635 case XD_128M_X8_512:
636 XD_PAGE_512(xd_card);
637 xd_card->addr_cycle = 4;
638 xd_card->zone_cnt = 8;
639 xd_card->capacity = 256000;
640 break;
641 case XD_256M_X8_512:
642 XD_PAGE_512(xd_card);
643 xd_card->addr_cycle = 4;
644 xd_card->zone_cnt = 16;
645 xd_card->capacity = 512000;
646 break;
647 case XD_512M_X8:
648 XD_PAGE_512(xd_card);
649 xd_card->addr_cycle = 4;
650 xd_card->zone_cnt = 32;
651 xd_card->capacity = 1024000;
652 break;
653 case xD_1G_X8_512:
654 XD_PAGE_512(xd_card);
655 xd_card->addr_cycle = 4;
656 xd_card->zone_cnt = 64;
657 xd_card->capacity = 2048000;
658 break;
659 case xD_2G_X8_512:
660 XD_PAGE_512(xd_card);
661 xd_card->addr_cycle = 4;
662 xd_card->zone_cnt = 128;
663 xd_card->capacity = 4096000;
664 break;
665 default:
666 continue;
667 }
668
669 /* Confirm timing setting */
670 for (j = 0; j < 10; j++) {
671 retval = xd_read_id(chip, READ_ID, id_buf, 4);
672 if (retval != STATUS_SUCCESS) {
673 TRACE_RET(chip, STATUS_FAIL);
674 }
675
676 if (id_buf[1] != xd_card->device_code)
677 break;
678 }
679
680 if (j == 10)
681 break;
682 }
683
684 if (i == 4) {
685 xd_card->block_shift = 0;
686 xd_card->page_off = 0;
687 xd_card->addr_cycle = 0;
688 xd_card->capacity = 0;
689
690 TRACE_RET(chip, STATUS_FAIL);
691 }
692
693 retval = xd_read_id(chip, READ_xD_ID, id_buf, 4);
694 if (retval != STATUS_SUCCESS) {
695 TRACE_RET(chip, STATUS_FAIL);
696 }
697 RTSX_DEBUGP("READ_xD_ID: 0x%x 0x%x 0x%x 0x%x\n",
698 id_buf[0], id_buf[1], id_buf[2], id_buf[3]);
699 if (id_buf[2] != XD_ID_CODE) {
700 TRACE_RET(chip, STATUS_FAIL);
701 }
702
703 /* Search CIS block */
704 for (i = 0; i < 24; i++) {
705 u32 page_addr;
706
707 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
708 TRACE_RET(chip, STATUS_FAIL);
709 }
710
711 page_addr = (u32)i << xd_card->block_shift;
712
713 for (j = 0; j < 3; j++) {
714 retval = xd_read_redundant(chip, page_addr, redunt, 11);
715 if (retval == STATUS_SUCCESS) {
716 break;
717 }
718 }
719 if (j == 3) {
720 continue;
721 }
722
723 if (redunt[BLOCK_STATUS] != XD_GBLK)
724 continue;
725
726 j = 0;
727 if (redunt[PAGE_STATUS] != XD_GPG) {
728 for (j = 1; j <= 8; j++) {
729 retval = xd_read_redundant(chip, page_addr + j, redunt, 11);
730 if (retval == STATUS_SUCCESS) {
731 if (redunt[PAGE_STATUS] == XD_GPG) {
732 break;
733 }
734 }
735 }
736
737 if (j == 9)
738 break;
739 }
740
741 /* Check CIS data */
742 if ((redunt[BLOCK_STATUS] == XD_GBLK) && (redunt[PARITY] & XD_BA1_ALL0)) {
743 u8 buf[10];
744
745 page_addr += j;
746
747 retval = xd_read_cis(chip, page_addr, buf, 10);
748 if (retval != STATUS_SUCCESS) {
749 TRACE_RET(chip, STATUS_FAIL);
750 }
751
752 if ((buf[0] == 0x01) && (buf[1] == 0x03) && (buf[2] == 0xD9)
753 && (buf[3] == 0x01) && (buf[4] == 0xFF)
754 && (buf[5] == 0x18) && (buf[6] == 0x02)
755 && (buf[7] == 0xDF) && (buf[8] == 0x01)
756 && (buf[9] == 0x20)) {
757 xd_card->cis_block = (u16)i;
758 }
759 }
760
761 break;
762 }
763
764 RTSX_DEBUGP("CIS block: 0x%x\n", xd_card->cis_block);
765 if (xd_card->cis_block == 0xFFFF) {
766 TRACE_RET(chip, STATUS_FAIL);
767 }
768
769 chip->capacity[chip->card2lun[XD_CARD]] = xd_card->capacity;
770
771 return STATUS_SUCCESS;
772 }
773
774 static int xd_check_data_blank(u8 *redunt)
775 {
776 int i;
777
778 for (i = 0; i < 6; i++) {
779 if (redunt[PAGE_STATUS + i] != 0xFF)
780 return 0;
781 }
782
783 if ((redunt[PARITY] & (XD_ECC1_ALL1 | XD_ECC2_ALL1)) != (XD_ECC1_ALL1 | XD_ECC2_ALL1)) {
784 return 0;
785 }
786
787 for (i = 0; i < 4; i++) {
788 if (redunt[RESERVED0 + i] != 0xFF)
789 return 0;
790 }
791
792 return 1;
793 }
794
795 static u16 xd_load_log_block_addr(u8 *redunt)
796 {
797 u16 addr = 0xFFFF;
798
799 if (redunt[PARITY] & XD_BA1_BA2_EQL) {
800 addr = ((u16)redunt[BLOCK_ADDR1_H] << 8) | redunt[BLOCK_ADDR1_L];
801 } else if (redunt[PARITY] & XD_BA1_VALID) {
802 addr = ((u16)redunt[BLOCK_ADDR1_H] << 8) | redunt[BLOCK_ADDR1_L];
803 } else if (redunt[PARITY] & XD_BA2_VALID) {
804 addr = ((u16)redunt[BLOCK_ADDR2_H] << 8) | redunt[BLOCK_ADDR2_L];
805 }
806
807 return addr;
808 }
809
810 static int xd_init_l2p_tbl(struct rtsx_chip *chip)
811 {
812 struct xd_info *xd_card = &(chip->xd_card);
813 int size, i;
814
815 RTSX_DEBUGP("xd_init_l2p_tbl: zone_cnt = %d\n", xd_card->zone_cnt);
816
817 if (xd_card->zone_cnt < 1) {
818 TRACE_RET(chip, STATUS_FAIL);
819 }
820
821 size = xd_card->zone_cnt * sizeof(struct zone_entry);
822 RTSX_DEBUGP("Buffer size for l2p table is %d\n", size);
823
824 xd_card->zone = (struct zone_entry *)vmalloc(size);
825 if (!xd_card->zone) {
826 TRACE_RET(chip, STATUS_ERROR);
827 }
828
829 for (i = 0; i < xd_card->zone_cnt; i++) {
830 xd_card->zone[i].build_flag = 0;
831 xd_card->zone[i].l2p_table = NULL;
832 xd_card->zone[i].free_table = NULL;
833 xd_card->zone[i].get_index = 0;
834 xd_card->zone[i].set_index = 0;
835 xd_card->zone[i].unused_blk_cnt = 0;
836 }
837
838 return STATUS_SUCCESS;
839 }
840
841 static inline void free_zone(struct zone_entry *zone)
842 {
843 RTSX_DEBUGP("free_zone\n");
844
845 if (!zone)
846 return;
847
848 zone->build_flag = 0;
849 zone->set_index = 0;
850 zone->get_index = 0;
851 zone->unused_blk_cnt = 0;
852 if (zone->l2p_table) {
853 vfree(zone->l2p_table);
854 zone->l2p_table = NULL;
855 }
856 if (zone->free_table) {
857 vfree(zone->free_table);
858 zone->free_table = NULL;
859 }
860 }
861
862 static void xd_set_unused_block(struct rtsx_chip *chip, u32 phy_blk)
863 {
864 struct xd_info *xd_card = &(chip->xd_card);
865 struct zone_entry *zone;
866 int zone_no;
867
868 zone_no = (int)phy_blk >> 10;
869 if (zone_no >= xd_card->zone_cnt) {
870 RTSX_DEBUGP("Set unused block to invalid zone (zone_no = %d, zone_cnt = %d)\n",
871 zone_no, xd_card->zone_cnt);
872 return;
873 }
874 zone = &(xd_card->zone[zone_no]);
875
876 if (zone->free_table == NULL) {
877 if (xd_build_l2p_tbl(chip, zone_no) != STATUS_SUCCESS) {
878 return;
879 }
880 }
881
882 if ((zone->set_index >= XD_FREE_TABLE_CNT)
883 || (zone->set_index < 0)) {
884 free_zone(zone);
885 RTSX_DEBUGP("Set unused block fail, invalid set_index\n");
886 return;
887 }
888
889 RTSX_DEBUGP("Set unused block to index %d\n", zone->set_index);
890
891 zone->free_table[zone->set_index++] = (u16) (phy_blk & 0x3ff);
892 if (zone->set_index >= XD_FREE_TABLE_CNT) {
893 zone->set_index = 0;
894 }
895 zone->unused_blk_cnt++;
896 }
897
898 static u32 xd_get_unused_block(struct rtsx_chip *chip, int zone_no)
899 {
900 struct xd_info *xd_card = &(chip->xd_card);
901 struct zone_entry *zone;
902 u32 phy_blk;
903
904 if (zone_no >= xd_card->zone_cnt) {
905 RTSX_DEBUGP("Get unused block from invalid zone (zone_no = %d, zone_cnt = %d)\n",
906 zone_no, xd_card->zone_cnt);
907 return BLK_NOT_FOUND;
908 }
909 zone = &(xd_card->zone[zone_no]);
910
911 if ((zone->unused_blk_cnt == 0) || (zone->set_index == zone->get_index)) {
912 free_zone(zone);
913 RTSX_DEBUGP("Get unused block fail, no unused block available\n");
914 return BLK_NOT_FOUND;
915 }
916 if ((zone->get_index >= XD_FREE_TABLE_CNT) || (zone->get_index < 0)) {
917 free_zone(zone);
918 RTSX_DEBUGP("Get unused block fail, invalid get_index\n");
919 return BLK_NOT_FOUND;
920 }
921
922 RTSX_DEBUGP("Get unused block from index %d\n", zone->get_index);
923
924 phy_blk = zone->free_table[zone->get_index];
925 zone->free_table[zone->get_index++] = 0xFFFF;
926 if (zone->get_index >= XD_FREE_TABLE_CNT) {
927 zone->get_index = 0;
928 }
929 zone->unused_blk_cnt--;
930
931 phy_blk += ((u32)(zone_no) << 10);
932 return phy_blk;
933 }
934
935 static void xd_set_l2p_tbl(struct rtsx_chip *chip, int zone_no, u16 log_off, u16 phy_off)
936 {
937 struct xd_info *xd_card = &(chip->xd_card);
938 struct zone_entry *zone;
939
940 zone = &(xd_card->zone[zone_no]);
941 zone->l2p_table[log_off] = phy_off;
942 }
943
944 static u32 xd_get_l2p_tbl(struct rtsx_chip *chip, int zone_no, u16 log_off)
945 {
946 struct xd_info *xd_card = &(chip->xd_card);
947 struct zone_entry *zone;
948 int retval;
949
950 zone = &(xd_card->zone[zone_no]);
951 if (zone->l2p_table[log_off] == 0xFFFF) {
952 u32 phy_blk = 0;
953 int i;
954
955 #ifdef XD_DELAY_WRITE
956 retval = xd_delay_write(chip);
957 if (retval != STATUS_SUCCESS) {
958 RTSX_DEBUGP("In xd_get_l2p_tbl, delay write fail!\n");
959 return BLK_NOT_FOUND;
960 }
961 #endif
962
963 if (zone->unused_blk_cnt <= 0) {
964 RTSX_DEBUGP("No unused block!\n");
965 return BLK_NOT_FOUND;
966 }
967
968 for (i = 0; i < zone->unused_blk_cnt; i++) {
969 phy_blk = xd_get_unused_block(chip, zone_no);
970 if (phy_blk == BLK_NOT_FOUND) {
971 RTSX_DEBUGP("No unused block available!\n");
972 return BLK_NOT_FOUND;
973 }
974
975 retval = xd_init_page(chip, phy_blk, log_off, 0, xd_card->page_off + 1);
976 if (retval == STATUS_SUCCESS)
977 break;
978 }
979 if (i >= zone->unused_blk_cnt) {
980 RTSX_DEBUGP("No good unused block available!\n");
981 return BLK_NOT_FOUND;
982 }
983
984 xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(phy_blk & 0x3FF));
985 return phy_blk;
986 }
987
988 return (u32)zone->l2p_table[log_off] + ((u32)(zone_no) << 10);
989 }
990
991 int reset_xd_card(struct rtsx_chip *chip)
992 {
993 struct xd_info *xd_card = &(chip->xd_card);
994 int retval;
995
996 memset(xd_card, 0, sizeof(struct xd_info));
997
998 xd_card->block_shift = 0;
999 xd_card->page_off = 0;
1000 xd_card->addr_cycle = 0;
1001 xd_card->capacity = 0;
1002 xd_card->zone_cnt = 0;
1003 xd_card->cis_block = 0xFFFF;
1004 xd_card->delay_write.delay_write_flag = 0;
1005
1006 retval = enable_card_clock(chip, XD_CARD);
1007 if (retval != STATUS_SUCCESS) {
1008 TRACE_RET(chip, STATUS_FAIL);
1009 }
1010
1011 retval = reset_xd(chip);
1012 if (retval != STATUS_SUCCESS) {
1013 TRACE_RET(chip, STATUS_FAIL);
1014 }
1015
1016 retval = xd_init_l2p_tbl(chip);
1017 if (retval != STATUS_SUCCESS) {
1018 TRACE_RET(chip, STATUS_FAIL);
1019 }
1020
1021 return STATUS_SUCCESS;
1022 }
1023
1024 static int xd_mark_bad_block(struct rtsx_chip *chip, u32 phy_blk)
1025 {
1026 struct xd_info *xd_card = &(chip->xd_card);
1027 int retval;
1028 u32 page_addr;
1029 u8 reg = 0;
1030
1031 RTSX_DEBUGP("mark block 0x%x as bad block\n", phy_blk);
1032
1033 if (phy_blk == BLK_NOT_FOUND) {
1034 TRACE_RET(chip, STATUS_FAIL);
1035 }
1036
1037 rtsx_init_cmd(chip);
1038
1039 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG);
1040 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_LATER_BBLK);
1041 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF, 0xFF);
1042 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, 0xFF);
1043 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_H, 0xFF, 0xFF);
1044 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_L, 0xFF, 0xFF);
1045 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED0, 0xFF, 0xFF);
1046 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED1, 0xFF, 0xFF);
1047 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED2, 0xFF, 0xFF);
1048 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED3, 0xFF, 0xFF);
1049
1050 page_addr = phy_blk << xd_card->block_shift;
1051
1052 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1053
1054 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, xd_card->page_off + 1);
1055
1056 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_WRITE_REDUNDANT);
1057 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
1058
1059 retval = rtsx_send_cmd(chip, XD_CARD, 500);
1060 if (retval < 0) {
1061 rtsx_clear_xd_error(chip);
1062 rtsx_read_register(chip, XD_DAT, &reg);
1063 if (reg & PROGRAM_ERROR) {
1064 xd_set_err_code(chip, XD_PRG_ERROR);
1065 } else {
1066 xd_set_err_code(chip, XD_TO_ERROR);
1067 }
1068 TRACE_RET(chip, STATUS_FAIL);
1069 }
1070
1071 return STATUS_SUCCESS;
1072 }
1073
1074 static int xd_init_page(struct rtsx_chip *chip, u32 phy_blk, u16 logoff, u8 start_page, u8 end_page)
1075 {
1076 struct xd_info *xd_card = &(chip->xd_card);
1077 int retval;
1078 u32 page_addr;
1079 u8 reg = 0;
1080
1081 RTSX_DEBUGP("Init block 0x%x\n", phy_blk);
1082
1083 if (start_page > end_page) {
1084 TRACE_RET(chip, STATUS_FAIL);
1085 }
1086 if (phy_blk == BLK_NOT_FOUND) {
1087 TRACE_RET(chip, STATUS_FAIL);
1088 }
1089
1090 rtsx_init_cmd(chip);
1091
1092 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, 0xFF);
1093 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, 0xFF);
1094 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF, (u8)(logoff >> 8));
1095 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, (u8)logoff);
1096
1097 page_addr = (phy_blk << xd_card->block_shift) + start_page;
1098
1099 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1100
1101 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_BA_TRANSFORM, XD_BA_TRANSFORM);
1102
1103 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, (end_page - start_page));
1104
1105 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_WRITE_REDUNDANT);
1106 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
1107
1108 retval = rtsx_send_cmd(chip, XD_CARD, 500);
1109 if (retval < 0) {
1110 rtsx_clear_xd_error(chip);
1111 rtsx_read_register(chip, XD_DAT, &reg);
1112 if (reg & PROGRAM_ERROR) {
1113 xd_mark_bad_block(chip, phy_blk);
1114 xd_set_err_code(chip, XD_PRG_ERROR);
1115 } else {
1116 xd_set_err_code(chip, XD_TO_ERROR);
1117 }
1118 TRACE_RET(chip, STATUS_FAIL);
1119 }
1120
1121 return STATUS_SUCCESS;
1122 }
1123
1124 static int xd_copy_page(struct rtsx_chip *chip, u32 old_blk, u32 new_blk, u8 start_page, u8 end_page)
1125 {
1126 struct xd_info *xd_card = &(chip->xd_card);
1127 u32 old_page, new_page;
1128 u8 i, reg = 0;
1129 int retval;
1130
1131 RTSX_DEBUGP("Copy page from block 0x%x to block 0x%x\n", old_blk, new_blk);
1132
1133 if (start_page > end_page) {
1134 TRACE_RET(chip, STATUS_FAIL);
1135 }
1136
1137 if ((old_blk == BLK_NOT_FOUND) || (new_blk == BLK_NOT_FOUND)) {
1138 TRACE_RET(chip, STATUS_FAIL);
1139 }
1140
1141 old_page = (old_blk << xd_card->block_shift) + start_page;
1142 new_page = (new_blk << xd_card->block_shift) + start_page;
1143
1144 XD_CLR_BAD_NEWBLK(xd_card);
1145
1146 RTSX_WRITE_REG(chip, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
1147
1148 for (i = start_page; i < end_page; i++) {
1149 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1150 rtsx_clear_xd_error(chip);
1151 xd_set_err_code(chip, XD_NO_CARD);
1152 TRACE_RET(chip, STATUS_FAIL);
1153 }
1154
1155 rtsx_init_cmd(chip);
1156
1157 xd_assign_phy_addr(chip, old_page, XD_RW_ADDR);
1158
1159 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
1160 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS, 0);
1161 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_READ_PAGES);
1162 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
1163
1164 retval = rtsx_send_cmd(chip, XD_CARD, 500);
1165 if (retval < 0) {
1166 rtsx_clear_xd_error(chip);
1167 reg = 0;
1168 rtsx_read_register(chip, XD_CTL, &reg);
1169 if (reg & (XD_ECC1_ERROR | XD_ECC2_ERROR)) {
1170 wait_timeout(100);
1171
1172 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1173 xd_set_err_code(chip, XD_NO_CARD);
1174 TRACE_RET(chip, STATUS_FAIL);
1175 }
1176
1177 if (((reg & (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) ==
1178 (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE))
1179 || ((reg & (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE)) ==
1180 (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))) {
1181 rtsx_write_register(chip, XD_PAGE_STATUS, 0xFF, XD_BPG);
1182 rtsx_write_register(chip, XD_BLOCK_STATUS, 0xFF, XD_GBLK);
1183 XD_SET_BAD_OLDBLK(xd_card);
1184 RTSX_DEBUGP("old block 0x%x ecc error\n", old_blk);
1185 }
1186 } else {
1187 xd_set_err_code(chip, XD_TO_ERROR);
1188 TRACE_RET(chip, STATUS_FAIL);
1189 }
1190 }
1191
1192 if (XD_CHK_BAD_OLDBLK(xd_card)) {
1193 rtsx_clear_xd_error(chip);
1194 }
1195
1196 rtsx_init_cmd(chip);
1197
1198 xd_assign_phy_addr(chip, new_page, XD_RW_ADDR);
1199 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
1200 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1201 XD_TRANSFER_START | XD_WRITE_PAGES);
1202 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
1203
1204 retval = rtsx_send_cmd(chip, XD_CARD, 300);
1205 if (retval < 0) {
1206 rtsx_clear_xd_error(chip);
1207 reg = 0;
1208 rtsx_read_register(chip, XD_DAT, &reg);
1209 if (reg & PROGRAM_ERROR) {
1210 xd_mark_bad_block(chip, new_blk);
1211 xd_set_err_code(chip, XD_PRG_ERROR);
1212 XD_SET_BAD_NEWBLK(xd_card);
1213 } else {
1214 xd_set_err_code(chip, XD_TO_ERROR);
1215 }
1216 TRACE_RET(chip, STATUS_FAIL);
1217 }
1218
1219 old_page++;
1220 new_page++;
1221 }
1222
1223 return STATUS_SUCCESS;
1224 }
1225
1226 static int xd_reset_cmd(struct rtsx_chip *chip)
1227 {
1228 int retval;
1229 u8 *ptr;
1230
1231 rtsx_init_cmd(chip);
1232
1233 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_RESET);
1234 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
1235 rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
1236 rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0);
1237
1238 retval = rtsx_send_cmd(chip, XD_CARD, 100);
1239 if (retval < 0) {
1240 TRACE_RET(chip, STATUS_FAIL);
1241 }
1242
1243 ptr = rtsx_get_cmd_data(chip) + 1;
1244 if (((ptr[0] & READY_FLAG) == READY_STATE) && (ptr[1] & XD_RDY)) {
1245 return STATUS_SUCCESS;
1246 }
1247
1248 TRACE_RET(chip, STATUS_FAIL);
1249 }
1250
1251 static int xd_erase_block(struct rtsx_chip *chip, u32 phy_blk)
1252 {
1253 struct xd_info *xd_card = &(chip->xd_card);
1254 u32 page_addr;
1255 u8 reg = 0, *ptr;
1256 int i, retval;
1257
1258 if (phy_blk == BLK_NOT_FOUND) {
1259 TRACE_RET(chip, STATUS_FAIL);
1260 }
1261
1262 page_addr = phy_blk << xd_card->block_shift;
1263
1264 for (i = 0; i < 3; i++) {
1265 rtsx_init_cmd(chip);
1266
1267 xd_assign_phy_addr(chip, page_addr, XD_ERASE_ADDR);
1268
1269 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_ERASE);
1270 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
1271 rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
1272
1273 retval = rtsx_send_cmd(chip, XD_CARD, 250);
1274 if (retval < 0) {
1275 rtsx_clear_xd_error(chip);
1276 rtsx_read_register(chip, XD_DAT, &reg);
1277 if (reg & PROGRAM_ERROR) {
1278 xd_mark_bad_block(chip, phy_blk);
1279 xd_set_err_code(chip, XD_PRG_ERROR);
1280 TRACE_RET(chip, STATUS_FAIL);
1281 } else {
1282 xd_set_err_code(chip, XD_ERASE_FAIL);
1283 }
1284 retval = xd_reset_cmd(chip);
1285 if (retval != STATUS_SUCCESS) {
1286 TRACE_RET(chip, STATUS_FAIL);
1287 }
1288 continue;
1289 }
1290
1291 ptr = rtsx_get_cmd_data(chip) + 1;
1292 if (*ptr & PROGRAM_ERROR) {
1293 xd_mark_bad_block(chip, phy_blk);
1294 xd_set_err_code(chip, XD_PRG_ERROR);
1295 TRACE_RET(chip, STATUS_FAIL);
1296 }
1297
1298 return STATUS_SUCCESS;
1299 }
1300
1301 xd_mark_bad_block(chip, phy_blk);
1302 xd_set_err_code(chip, XD_ERASE_FAIL);
1303 TRACE_RET(chip, STATUS_FAIL);
1304 }
1305
1306
1307 static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no)
1308 {
1309 struct xd_info *xd_card = &(chip->xd_card);
1310 struct zone_entry *zone;
1311 int retval;
1312 u32 start, end, i;
1313 u16 max_logoff, cur_fst_page_logoff, cur_lst_page_logoff, ent_lst_page_logoff;
1314 u8 redunt[11];
1315
1316 RTSX_DEBUGP("xd_build_l2p_tbl: %d\n", zone_no);
1317
1318 if (xd_card->zone == NULL) {
1319 retval = xd_init_l2p_tbl(chip);
1320 if (retval != STATUS_SUCCESS) {
1321 return retval;
1322 }
1323 }
1324
1325 if (xd_card->zone[zone_no].build_flag) {
1326 RTSX_DEBUGP("l2p table of zone %d has been built\n", zone_no);
1327 return STATUS_SUCCESS;
1328 }
1329
1330 zone = &(xd_card->zone[zone_no]);
1331
1332 if (zone->l2p_table == NULL) {
1333 zone->l2p_table = (u16 *)vmalloc(2000);
1334 if (zone->l2p_table == NULL) {
1335 TRACE_GOTO(chip, Build_Fail);
1336 }
1337 }
1338 memset((u8 *)(zone->l2p_table), 0xff, 2000);
1339
1340 if (zone->free_table == NULL) {
1341 zone->free_table = (u16 *)vmalloc(XD_FREE_TABLE_CNT * 2);
1342 if (zone->free_table == NULL) {
1343 TRACE_GOTO(chip, Build_Fail);
1344 }
1345 }
1346 memset((u8 *)(zone->free_table), 0xff, XD_FREE_TABLE_CNT * 2);
1347
1348 if (zone_no == 0) {
1349 if (xd_card->cis_block == 0xFFFF) {
1350 start = 0;
1351 } else {
1352 start = xd_card->cis_block + 1;
1353 }
1354 if (XD_CHK_4MB(xd_card)) {
1355 end = 0x200;
1356 max_logoff = 499;
1357 } else {
1358 end = 0x400;
1359 max_logoff = 999;
1360 }
1361 } else {
1362 start = (u32)(zone_no) << 10;
1363 end = (u32)(zone_no + 1) << 10;
1364 max_logoff = 999;
1365 }
1366
1367 RTSX_DEBUGP("start block 0x%x, end block 0x%x\n", start, end);
1368
1369 zone->set_index = zone->get_index = 0;
1370 zone->unused_blk_cnt = 0;
1371
1372 for (i = start; i < end; i++) {
1373 u32 page_addr = i << xd_card->block_shift;
1374 u32 phy_block;
1375
1376 retval = xd_read_redundant(chip, page_addr, redunt, 11);
1377 if (retval != STATUS_SUCCESS) {
1378 continue;
1379 }
1380
1381 if (redunt[BLOCK_STATUS] != 0xFF) {
1382 RTSX_DEBUGP("bad block\n");
1383 continue;
1384 }
1385
1386 if (xd_check_data_blank(redunt)) {
1387 RTSX_DEBUGP("blank block\n");
1388 xd_set_unused_block(chip, i);
1389 continue;
1390 }
1391
1392 cur_fst_page_logoff = xd_load_log_block_addr(redunt);
1393 if ((cur_fst_page_logoff == 0xFFFF) || (cur_fst_page_logoff > max_logoff)) {
1394 retval = xd_erase_block(chip, i);
1395 if (retval == STATUS_SUCCESS) {
1396 xd_set_unused_block(chip, i);
1397 }
1398 continue;
1399 }
1400
1401 if ((zone_no == 0) && (cur_fst_page_logoff == 0) && (redunt[PAGE_STATUS] != XD_GPG)) {
1402 XD_SET_MBR_FAIL(xd_card);
1403 }
1404
1405 if (zone->l2p_table[cur_fst_page_logoff] == 0xFFFF) {
1406 zone->l2p_table[cur_fst_page_logoff] = (u16)(i & 0x3FF);
1407 continue;
1408 }
1409
1410 phy_block = zone->l2p_table[cur_fst_page_logoff] + ((u32)((zone_no) << 10));
1411
1412 page_addr = ((i + 1) << xd_card->block_shift) - 1;
1413
1414 retval = xd_read_redundant(chip, page_addr, redunt, 11);
1415 if (retval != STATUS_SUCCESS) {
1416 continue;
1417 }
1418
1419 cur_lst_page_logoff = xd_load_log_block_addr(redunt);
1420 if (cur_lst_page_logoff == cur_fst_page_logoff) {
1421 int m;
1422
1423 page_addr = ((phy_block + 1) << xd_card->block_shift) - 1;
1424
1425 for (m = 0; m < 3; m++) {
1426 retval = xd_read_redundant(chip, page_addr, redunt, 11);
1427 if (retval == STATUS_SUCCESS)
1428 break;
1429 }
1430
1431 if (m == 3) {
1432 zone->l2p_table[cur_fst_page_logoff] = (u16)(i & 0x3FF);
1433 retval = xd_erase_block(chip, phy_block);
1434 if (retval == STATUS_SUCCESS) {
1435 xd_set_unused_block(chip, phy_block);
1436 }
1437 continue;
1438 }
1439
1440 ent_lst_page_logoff = xd_load_log_block_addr(redunt);
1441 if (ent_lst_page_logoff != cur_fst_page_logoff) {
1442 zone->l2p_table[cur_fst_page_logoff] = (u16)(i & 0x3FF);
1443 retval = xd_erase_block(chip, phy_block);
1444 if (retval == STATUS_SUCCESS) {
1445 xd_set_unused_block(chip, phy_block);
1446 }
1447 continue;
1448 } else {
1449 retval = xd_erase_block(chip, i);
1450 if (retval == STATUS_SUCCESS) {
1451 xd_set_unused_block(chip, i);
1452 }
1453 }
1454 } else {
1455 retval = xd_erase_block(chip, i);
1456 if (retval == STATUS_SUCCESS) {
1457 xd_set_unused_block(chip, i);
1458 }
1459 }
1460 }
1461
1462 if (XD_CHK_4MB(xd_card)) {
1463 end = 500;
1464 } else {
1465 end = 1000;
1466 }
1467
1468 i = 0;
1469 for (start = 0; start < end; start++) {
1470 if (zone->l2p_table[start] == 0xFFFF) {
1471 i++;
1472 }
1473 }
1474
1475 RTSX_DEBUGP("Block count %d, invalid L2P entry %d\n", end, i);
1476 RTSX_DEBUGP("Total unused block: %d\n", zone->unused_blk_cnt);
1477
1478 if ((zone->unused_blk_cnt - i) < 1) {
1479 chip->card_wp |= XD_CARD;
1480 }
1481
1482 zone->build_flag = 1;
1483
1484 return STATUS_SUCCESS;
1485
1486 Build_Fail:
1487 if (zone->l2p_table) {
1488 vfree(zone->l2p_table);
1489 zone->l2p_table = NULL;
1490 }
1491 if (zone->free_table) {
1492 vfree(zone->free_table);
1493 zone->free_table = NULL;
1494 }
1495
1496 return STATUS_FAIL;
1497 }
1498
1499 static int xd_send_cmd(struct rtsx_chip *chip, u8 cmd)
1500 {
1501 int retval;
1502
1503 rtsx_init_cmd(chip);
1504
1505 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, cmd);
1506 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_SET_CMD);
1507 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
1508
1509 retval = rtsx_send_cmd(chip, XD_CARD, 200);
1510 if (retval < 0) {
1511 TRACE_RET(chip, STATUS_FAIL);
1512 }
1513
1514 return STATUS_SUCCESS;
1515 }
1516
1517 static int xd_read_multiple_pages(struct rtsx_chip *chip, u32 phy_blk, u32 log_blk,
1518 u8 start_page, u8 end_page, u8 *buf, unsigned int *index, unsigned int *offset)
1519 {
1520 struct xd_info *xd_card = &(chip->xd_card);
1521 u32 page_addr, new_blk;
1522 u16 log_off;
1523 u8 reg_val, page_cnt;
1524 int zone_no, retval, i;
1525
1526 if (start_page > end_page) {
1527 TRACE_RET(chip, STATUS_FAIL);
1528 }
1529
1530 page_cnt = end_page - start_page;
1531 zone_no = (int)(log_blk / 1000);
1532 log_off = (u16)(log_blk % 1000);
1533
1534 if ((phy_blk & 0x3FF) == 0x3FF) {
1535 for (i = 0; i < 256; i++) {
1536 page_addr = ((u32)i) << xd_card->block_shift;
1537
1538 retval = xd_read_redundant(chip, page_addr, NULL, 0);
1539 if (retval == STATUS_SUCCESS)
1540 break;
1541
1542 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1543 xd_set_err_code(chip, XD_NO_CARD);
1544 TRACE_RET(chip, STATUS_FAIL);
1545 }
1546 }
1547 }
1548
1549 page_addr = (phy_blk << xd_card->block_shift) + start_page;
1550
1551 rtsx_init_cmd(chip);
1552
1553 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1554 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_PPB_TO_SIE, XD_PPB_TO_SIE);
1555 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
1556 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt);
1557 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
1558 XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS);
1559
1560 trans_dma_enable(chip->srb->sc_data_direction, chip, page_cnt * 512, DMA_512);
1561
1562 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_READ_PAGES);
1563 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1564 XD_TRANSFER_END | XD_PPB_EMPTY, XD_TRANSFER_END | XD_PPB_EMPTY);
1565
1566 rtsx_send_cmd_no_wait(chip);
1567
1568 retval = rtsx_transfer_data_partial(chip, XD_CARD, buf, page_cnt * 512, scsi_sg_count(chip->srb),
1569 index, offset, DMA_FROM_DEVICE, chip->xd_timeout);
1570 if (retval < 0) {
1571 rtsx_clear_xd_error(chip);
1572 xd_clear_dma_buffer(chip);
1573
1574 if (retval == -ETIMEDOUT) {
1575 xd_set_err_code(chip, XD_TO_ERROR);
1576 TRACE_RET(chip, STATUS_FAIL);
1577 } else {
1578 TRACE_GOTO(chip, Fail);
1579 }
1580 }
1581
1582 return STATUS_SUCCESS;
1583
1584 Fail:
1585 RTSX_READ_REG(chip, XD_PAGE_STATUS, &reg_val);
1586
1587 if (reg_val != XD_GPG) {
1588 xd_set_err_code(chip, XD_PRG_ERROR);
1589 }
1590
1591 RTSX_READ_REG(chip, XD_CTL, &reg_val);
1592
1593 if (((reg_val & (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE))
1594 == (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE))
1595 || ((reg_val & (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))
1596 == (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))) {
1597 wait_timeout(100);
1598
1599 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1600 xd_set_err_code(chip, XD_NO_CARD);
1601 TRACE_RET(chip, STATUS_FAIL);
1602 }
1603
1604 xd_set_err_code(chip, XD_ECC_ERROR);
1605
1606 new_blk = xd_get_unused_block(chip, zone_no);
1607 if (new_blk == NO_NEW_BLK) {
1608 XD_CLR_BAD_OLDBLK(xd_card);
1609 TRACE_RET(chip, STATUS_FAIL);
1610 }
1611
1612 retval = xd_copy_page(chip, phy_blk, new_blk, 0, xd_card->page_off + 1);
1613 if (retval != STATUS_SUCCESS) {
1614 if (!XD_CHK_BAD_NEWBLK(xd_card)) {
1615 retval = xd_erase_block(chip, new_blk);
1616 if (retval == STATUS_SUCCESS) {
1617 xd_set_unused_block(chip, new_blk);
1618 }
1619 } else {
1620 XD_CLR_BAD_NEWBLK(xd_card);
1621 }
1622 XD_CLR_BAD_OLDBLK(xd_card);
1623 TRACE_RET(chip, STATUS_FAIL);
1624 }
1625 xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF));
1626 xd_erase_block(chip, phy_blk);
1627 xd_mark_bad_block(chip, phy_blk);
1628 XD_CLR_BAD_OLDBLK(xd_card);
1629 }
1630
1631 TRACE_RET(chip, STATUS_FAIL);
1632 }
1633
1634 static int xd_finish_write(struct rtsx_chip *chip,
1635 u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off)
1636 {
1637 struct xd_info *xd_card = &(chip->xd_card);
1638 int retval, zone_no;
1639 u16 log_off;
1640
1641 RTSX_DEBUGP("xd_finish_write, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x\n",
1642 old_blk, new_blk, log_blk);
1643
1644 if (page_off > xd_card->page_off) {
1645 TRACE_RET(chip, STATUS_FAIL);
1646 }
1647
1648 zone_no = (int)(log_blk / 1000);
1649 log_off = (u16)(log_blk % 1000);
1650
1651 if (old_blk == BLK_NOT_FOUND) {
1652 retval = xd_init_page(chip, new_blk, log_off,
1653 page_off, xd_card->page_off + 1);
1654 if (retval != STATUS_SUCCESS) {
1655 retval = xd_erase_block(chip, new_blk);
1656 if (retval == STATUS_SUCCESS) {
1657 xd_set_unused_block(chip, new_blk);
1658 }
1659 TRACE_RET(chip, STATUS_FAIL);
1660 }
1661 } else {
1662 retval = xd_copy_page(chip, old_blk, new_blk,
1663 page_off, xd_card->page_off + 1);
1664 if (retval != STATUS_SUCCESS) {
1665 if (!XD_CHK_BAD_NEWBLK(xd_card)) {
1666 retval = xd_erase_block(chip, new_blk);
1667 if (retval == STATUS_SUCCESS) {
1668 xd_set_unused_block(chip, new_blk);
1669 }
1670 }
1671 XD_CLR_BAD_NEWBLK(xd_card);
1672 TRACE_RET(chip, STATUS_FAIL);
1673 }
1674
1675 retval = xd_erase_block(chip, old_blk);
1676 if (retval == STATUS_SUCCESS) {
1677 if (XD_CHK_BAD_OLDBLK(xd_card)) {
1678 xd_mark_bad_block(chip, old_blk);
1679 XD_CLR_BAD_OLDBLK(xd_card);
1680 } else {
1681 xd_set_unused_block(chip, old_blk);
1682 }
1683 } else {
1684 xd_set_err_code(chip, XD_NO_ERROR);
1685 XD_CLR_BAD_OLDBLK(xd_card);
1686 }
1687 }
1688
1689 xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF));
1690
1691 return STATUS_SUCCESS;
1692 }
1693
1694 static int xd_prepare_write(struct rtsx_chip *chip,
1695 u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off)
1696 {
1697 int retval;
1698
1699 RTSX_DEBUGP("%s, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x, page_off = %d\n",
1700 __func__, old_blk, new_blk, log_blk, (int)page_off);
1701
1702 if (page_off) {
1703 retval = xd_copy_page(chip, old_blk, new_blk, 0, page_off);
1704 if (retval != STATUS_SUCCESS) {
1705 TRACE_RET(chip, STATUS_FAIL);
1706 }
1707 }
1708
1709 return STATUS_SUCCESS;
1710 }
1711
1712
1713 static int xd_write_multiple_pages(struct rtsx_chip *chip, u32 old_blk, u32 new_blk, u32 log_blk,
1714 u8 start_page, u8 end_page, u8 *buf, unsigned int *index, unsigned int *offset)
1715 {
1716 struct xd_info *xd_card = &(chip->xd_card);
1717 u32 page_addr;
1718 int zone_no, retval;
1719 u16 log_off;
1720 u8 page_cnt, reg_val;
1721
1722 RTSX_DEBUGP("%s, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x\n",
1723 __func__, old_blk, new_blk, log_blk);
1724
1725 if (start_page > end_page) {
1726 TRACE_RET(chip, STATUS_FAIL);
1727 }
1728
1729 page_cnt = end_page - start_page;
1730 zone_no = (int)(log_blk / 1000);
1731 log_off = (u16)(log_blk % 1000);
1732
1733 page_addr = (new_blk << xd_card->block_shift) + start_page;
1734
1735 retval = xd_send_cmd(chip, READ1_1);
1736 if (retval != STATUS_SUCCESS) {
1737 TRACE_RET(chip, STATUS_FAIL);
1738 }
1739
1740 rtsx_init_cmd(chip);
1741
1742 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF, (u8)(log_off >> 8));
1743 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, (u8)log_off);
1744 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_GBLK);
1745 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG);
1746
1747 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1748
1749 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_BA_TRANSFORM, XD_BA_TRANSFORM);
1750 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt);
1751 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
1752
1753 trans_dma_enable(chip->srb->sc_data_direction, chip, page_cnt * 512, DMA_512);
1754
1755 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, XD_TRANSFER_START | XD_WRITE_PAGES);
1756 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, XD_TRANSFER_END);
1757
1758 rtsx_send_cmd_no_wait(chip);
1759
1760 retval = rtsx_transfer_data_partial(chip, XD_CARD, buf, page_cnt * 512, scsi_sg_count(chip->srb),
1761 index, offset, DMA_TO_DEVICE, chip->xd_timeout);
1762 if (retval < 0) {
1763 rtsx_clear_xd_error(chip);
1764
1765 if (retval == -ETIMEDOUT) {
1766 xd_set_err_code(chip, XD_TO_ERROR);
1767 TRACE_RET(chip, STATUS_FAIL);
1768 } else {
1769 TRACE_GOTO(chip, Fail);
1770 }
1771 }
1772
1773 if (end_page == (xd_card->page_off + 1)) {
1774 xd_card->delay_write.delay_write_flag = 0;
1775
1776 if (old_blk != BLK_NOT_FOUND) {
1777 retval = xd_erase_block(chip, old_blk);
1778 if (retval == STATUS_SUCCESS) {
1779 if (XD_CHK_BAD_OLDBLK(xd_card)) {
1780 xd_mark_bad_block(chip, old_blk);
1781 XD_CLR_BAD_OLDBLK(xd_card);
1782 } else {
1783 xd_set_unused_block(chip, old_blk);
1784 }
1785 } else {
1786 xd_set_err_code(chip, XD_NO_ERROR);
1787 XD_CLR_BAD_OLDBLK(xd_card);
1788 }
1789 }
1790 xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF));
1791 }
1792
1793 return STATUS_SUCCESS;
1794
1795 Fail:
1796 RTSX_READ_REG(chip, XD_DAT, &reg_val);
1797 if (reg_val & PROGRAM_ERROR) {
1798 xd_set_err_code(chip, XD_PRG_ERROR);
1799 xd_mark_bad_block(chip, new_blk);
1800 }
1801
1802 TRACE_RET(chip, STATUS_FAIL);
1803 }
1804
1805 #ifdef XD_DELAY_WRITE
1806 int xd_delay_write(struct rtsx_chip *chip)
1807 {
1808 struct xd_info *xd_card = &(chip->xd_card);
1809 struct xd_delay_write_tag *delay_write = &(xd_card->delay_write);
1810 int retval;
1811
1812 if (delay_write->delay_write_flag) {
1813 RTSX_DEBUGP("xd_delay_write\n");
1814 retval = xd_switch_clock(chip);
1815 if (retval != STATUS_SUCCESS) {
1816 TRACE_RET(chip, STATUS_FAIL);
1817 }
1818
1819 delay_write->delay_write_flag = 0;
1820 retval = xd_finish_write(chip,
1821 delay_write->old_phyblock, delay_write->new_phyblock,
1822 delay_write->logblock, delay_write->pageoff);
1823 if (retval != STATUS_SUCCESS) {
1824 TRACE_RET(chip, STATUS_FAIL);
1825 }
1826 }
1827
1828 return STATUS_SUCCESS;
1829 }
1830 #endif
1831
1832 int xd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 start_sector, u16 sector_cnt)
1833 {
1834 struct xd_info *xd_card = &(chip->xd_card);
1835 unsigned int lun = SCSI_LUN(srb);
1836 #ifdef XD_DELAY_WRITE
1837 struct xd_delay_write_tag *delay_write = &(xd_card->delay_write);
1838 #endif
1839 int retval, zone_no;
1840 unsigned int index = 0, offset = 0;
1841 u32 log_blk, old_blk = 0, new_blk = 0;
1842 u16 log_off, total_sec_cnt = sector_cnt;
1843 u8 start_page, end_page = 0, page_cnt;
1844 u8 *ptr;
1845
1846 xd_set_err_code(chip, XD_NO_ERROR);
1847
1848 xd_card->cleanup_counter = 0;
1849
1850 RTSX_DEBUGP("xd_rw: scsi_sg_count = %d\n", scsi_sg_count(srb));
1851
1852 ptr = (u8 *)scsi_sglist(srb);
1853
1854 retval = xd_switch_clock(chip);
1855 if (retval != STATUS_SUCCESS) {
1856 TRACE_RET(chip, STATUS_FAIL);
1857 }
1858
1859 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1860 chip->card_fail |= XD_CARD;
1861 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1862 TRACE_RET(chip, STATUS_FAIL);
1863 }
1864
1865 log_blk = start_sector >> xd_card->block_shift;
1866 start_page = (u8)start_sector & xd_card->page_off;
1867 zone_no = (int)(log_blk / 1000);
1868 log_off = (u16)(log_blk % 1000);
1869
1870 if (xd_card->zone[zone_no].build_flag == 0) {
1871 retval = xd_build_l2p_tbl(chip, zone_no);
1872 if (retval != STATUS_SUCCESS) {
1873 chip->card_fail |= XD_CARD;
1874 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1875 TRACE_RET(chip, STATUS_FAIL);
1876 }
1877 }
1878
1879 if (srb->sc_data_direction == DMA_TO_DEVICE) {
1880 #ifdef XD_DELAY_WRITE
1881 if (delay_write->delay_write_flag &&
1882 (delay_write->logblock == log_blk) &&
1883 (start_page > delay_write->pageoff)) {
1884 delay_write->delay_write_flag = 0;
1885 if (delay_write->old_phyblock != BLK_NOT_FOUND) {
1886 retval = xd_copy_page(chip,
1887 delay_write->old_phyblock,
1888 delay_write->new_phyblock,
1889 delay_write->pageoff, start_page);
1890 if (retval != STATUS_SUCCESS) {
1891 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
1892 TRACE_RET(chip, STATUS_FAIL);
1893 }
1894 }
1895 old_blk = delay_write->old_phyblock;
1896 new_blk = delay_write->new_phyblock;
1897 } else if (delay_write->delay_write_flag &&
1898 (delay_write->logblock == log_blk) &&
1899 (start_page == delay_write->pageoff)) {
1900 delay_write->delay_write_flag = 0;
1901 old_blk = delay_write->old_phyblock;
1902 new_blk = delay_write->new_phyblock;
1903 } else {
1904 retval = xd_delay_write(chip);
1905 if (retval != STATUS_SUCCESS) {
1906 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
1907 TRACE_RET(chip, STATUS_FAIL);
1908 }
1909 #endif
1910 old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
1911 new_blk = xd_get_unused_block(chip, zone_no);
1912 if ((old_blk == BLK_NOT_FOUND) || (new_blk == BLK_NOT_FOUND)) {
1913 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
1914 TRACE_RET(chip, STATUS_FAIL);
1915 }
1916
1917 retval = xd_prepare_write(chip, old_blk, new_blk, log_blk, start_page);
1918 if (retval != STATUS_SUCCESS) {
1919 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1920 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1921 TRACE_RET(chip, STATUS_FAIL);
1922 }
1923 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
1924 TRACE_RET(chip, STATUS_FAIL);
1925 }
1926 #ifdef XD_DELAY_WRITE
1927 }
1928 #endif
1929 } else {
1930 #ifdef XD_DELAY_WRITE
1931 retval = xd_delay_write(chip);
1932 if (retval != STATUS_SUCCESS) {
1933 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1934 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1935 TRACE_RET(chip, STATUS_FAIL);
1936 }
1937 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
1938 TRACE_RET(chip, STATUS_FAIL);
1939 }
1940 #endif
1941
1942 old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
1943 if (old_blk == BLK_NOT_FOUND) {
1944 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
1945 TRACE_RET(chip, STATUS_FAIL);
1946 }
1947 }
1948
1949 RTSX_DEBUGP("old_blk = 0x%x\n", old_blk);
1950
1951 while (total_sec_cnt) {
1952 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1953 chip->card_fail |= XD_CARD;
1954 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1955 TRACE_RET(chip, STATUS_FAIL);
1956 }
1957
1958 if ((start_page + total_sec_cnt) > (xd_card->page_off + 1)) {
1959 end_page = xd_card->page_off + 1;
1960 } else {
1961 end_page = start_page + (u8)total_sec_cnt;
1962 }
1963 page_cnt = end_page - start_page;
1964 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
1965 retval = xd_read_multiple_pages(chip, old_blk, log_blk,
1966 start_page, end_page, ptr, &index, &offset);
1967 if (retval != STATUS_SUCCESS) {
1968 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
1969 TRACE_RET(chip, STATUS_FAIL);
1970 }
1971 } else {
1972 retval = xd_write_multiple_pages(chip, old_blk, new_blk, log_blk,
1973 start_page, end_page, ptr, &index, &offset);
1974 if (retval != STATUS_SUCCESS) {
1975 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
1976 TRACE_RET(chip, STATUS_FAIL);
1977 }
1978 }
1979
1980 total_sec_cnt -= page_cnt;
1981 if (scsi_sg_count(srb) == 0)
1982 ptr += page_cnt * 512;
1983
1984 if (total_sec_cnt == 0)
1985 break;
1986
1987 log_blk++;
1988 zone_no = (int)(log_blk / 1000);
1989 log_off = (u16)(log_blk % 1000);
1990
1991 if (xd_card->zone[zone_no].build_flag == 0) {
1992 retval = xd_build_l2p_tbl(chip, zone_no);
1993 if (retval != STATUS_SUCCESS) {
1994 chip->card_fail |= XD_CARD;
1995 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1996 TRACE_RET(chip, STATUS_FAIL);
1997 }
1998 }
1999
2000 old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
2001 if (old_blk == BLK_NOT_FOUND) {
2002 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2003 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
2004 } else {
2005 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
2006 }
2007 TRACE_RET(chip, STATUS_FAIL);
2008 }
2009
2010 if (srb->sc_data_direction == DMA_TO_DEVICE) {
2011 new_blk = xd_get_unused_block(chip, zone_no);
2012 if (new_blk == BLK_NOT_FOUND) {
2013 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
2014 TRACE_RET(chip, STATUS_FAIL);
2015 }
2016 }
2017
2018 start_page = 0;
2019 }
2020
2021 if ((srb->sc_data_direction == DMA_TO_DEVICE) &&
2022 (end_page != (xd_card->page_off + 1))) {
2023 #ifdef XD_DELAY_WRITE
2024 delay_write->delay_write_flag = 1;
2025 delay_write->old_phyblock = old_blk;
2026 delay_write->new_phyblock = new_blk;
2027 delay_write->logblock = log_blk;
2028 delay_write->pageoff = end_page;
2029 #else
2030 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
2031 chip->card_fail |= XD_CARD;
2032 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
2033 TRACE_RET(chip, STATUS_FAIL);
2034 }
2035
2036 retval = xd_finish_write(chip, old_blk, new_blk, log_blk, end_page);
2037 if (retval != STATUS_SUCCESS) {
2038 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
2039 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
2040 TRACE_RET(chip, STATUS_FAIL);
2041 }
2042 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
2043 TRACE_RET(chip, STATUS_FAIL);
2044 }
2045 #endif
2046 }
2047
2048 scsi_set_resid(srb, 0);
2049
2050 return STATUS_SUCCESS;
2051 }
2052
2053 void xd_free_l2p_tbl(struct rtsx_chip *chip)
2054 {
2055 struct xd_info *xd_card = &(chip->xd_card);
2056 int i = 0;
2057
2058 if (xd_card->zone != NULL) {
2059 for (i = 0; i < xd_card->zone_cnt; i++) {
2060 if (xd_card->zone[i].l2p_table != NULL) {
2061 vfree(xd_card->zone[i].l2p_table);
2062 xd_card->zone[i].l2p_table = NULL;
2063 }
2064 if (xd_card->zone[i].free_table != NULL) {
2065 vfree(xd_card->zone[i].free_table);
2066 xd_card->zone[i].free_table = NULL;
2067 }
2068 }
2069 vfree(xd_card->zone);
2070 xd_card->zone = NULL;
2071 }
2072 }
2073
2074 void xd_cleanup_work(struct rtsx_chip *chip)
2075 {
2076 #ifdef XD_DELAY_WRITE
2077 struct xd_info *xd_card = &(chip->xd_card);
2078
2079 if (xd_card->delay_write.delay_write_flag) {
2080 RTSX_DEBUGP("xD: delay write\n");
2081 xd_delay_write(chip);
2082 xd_card->cleanup_counter = 0;
2083 }
2084 #endif
2085 }
2086
2087 int xd_power_off_card3v3(struct rtsx_chip *chip)
2088 {
2089 int retval;
2090
2091 retval = disable_card_clock(chip, XD_CARD);
2092 if (retval != STATUS_SUCCESS) {
2093 TRACE_RET(chip, STATUS_FAIL);
2094 }
2095
2096 RTSX_WRITE_REG(chip, CARD_OE, XD_OUTPUT_EN, 0);
2097
2098 if (!chip->ft2_fast_mode) {
2099 retval = card_power_off(chip, XD_CARD);
2100 if (retval != STATUS_SUCCESS) {
2101 TRACE_RET(chip, STATUS_FAIL);
2102 }
2103
2104 wait_timeout(50);
2105 }
2106
2107 if (chip->asic_code) {
2108 retval = xd_pull_ctl_disable(chip);
2109 if (retval != STATUS_SUCCESS) {
2110 TRACE_RET(chip, STATUS_FAIL);
2111 }
2112 } else {
2113 RTSX_WRITE_REG(chip, FPGA_PULL_CTL, 0xFF, 0xDF);
2114 }
2115
2116 return STATUS_SUCCESS;
2117 }
2118
2119 int release_xd_card(struct rtsx_chip *chip)
2120 {
2121 struct xd_info *xd_card = &(chip->xd_card);
2122 int retval;
2123
2124 RTSX_DEBUGP("release_xd_card\n");
2125
2126 chip->card_ready &= ~XD_CARD;
2127 chip->card_fail &= ~XD_CARD;
2128 chip->card_wp &= ~XD_CARD;
2129
2130 xd_card->delay_write.delay_write_flag = 0;
2131
2132 xd_free_l2p_tbl(chip);
2133
2134 retval = xd_power_off_card3v3(chip);
2135 if (retval != STATUS_SUCCESS) {
2136 TRACE_RET(chip, STATUS_FAIL);
2137 }
2138
2139 return STATUS_SUCCESS;
2140 }
Linux kernel - Deliverables
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