drivers/staging/sb105x/sb_pci_mp.h

   1 #include <linux/errno.h>
   2 #include <linux/signal.h>
   3 #include <linux/tty.h>
   4 #include <linux/tty_flip.h>
   5 #include <linux/serial.h>
   6 #include <linux/serial_reg.h>
   7 #include <linux/ioport.h>
   8 #include <linux/mm.h>
   9 #include <linux/sched.h>
  10
  11 #include <linux/kernel.h>
  12 #include <linux/slab.h>
  13 #include <linux/wait.h>
  14 #include <linux/tty_driver.h>
  15 #include <linux/pci.h>
  16 #include <linux/circ_buf.h>
  17
  18 #include <asm/uaccess.h>
  19 #include <asm/io.h>
  20 #include <asm/irq.h>
  21 #include <asm/serial.h>
  22 #include <linux/interrupt.h>
  23
  24
  25 #include <linux/parport.h>
  26 #include <linux/ctype.h>
  27 #include <linux/poll.h>
  28
  29
  30 #define MP_TERMIOS  ktermios
  31
  32 #include "sb_mp_register.h"
  33 #include "sb_ser_core.h"
  34
  35 #define DRIVER_VERSION  "1.1"
  36 #define DRIVER_DATE     "2012/01/05"
  37 #define DRIVER_AUTHOR  "SYSTEMBASE<tech@sysbas.com>"
  38 #define DRIVER_DESC  "SystemBase PCI/PCIe Multiport Core"
  39
  40 #define SB_TTY_MP_MAJOR                 54
  41 #define PCI_VENDOR_ID_MULTIPORT         0x14A1
  42
  43 #define PCI_DEVICE_ID_MP1               0x4d01
  44 #define PCI_DEVICE_ID_MP2               0x4d02
  45 #define PCI_DEVICE_ID_MP4               0x4d04
  46 #define PCI_DEVICE_ID_MP4A              0x4d54
  47 #define PCI_DEVICE_ID_MP6               0x4d06
  48 #define PCI_DEVICE_ID_MP6A              0x4d56
  49 #define PCI_DEVICE_ID_MP8               0x4d08
  50 #define PCI_DEVICE_ID_MP32              0x4d32
  51 /* Parallel port */
  52 #define PCI_DEVICE_ID_MP1P              0x4301
  53 #define PCI_DEVICE_ID_MP2S1P            0x4303
  54
  55 #define PCIE_DEVICE_ID_MP1              0x4501
  56 #define PCIE_DEVICE_ID_MP2              0x4502
  57 #define PCIE_DEVICE_ID_MP4              0x4504
  58 #define PCIE_DEVICE_ID_MP8              0x4508
  59 #define PCIE_DEVICE_ID_MP32             0x4532
  60
  61 #define PCIE_DEVICE_ID_MP1E             0x4e01
  62 #define PCIE_DEVICE_ID_MP2E             0x4e02
  63 #define PCIE_DEVICE_ID_MP2B             0x4b02
  64 #define PCIE_DEVICE_ID_MP4B             0x4b04
  65 #define PCIE_DEVICE_ID_MP8B             0x4b08
  66
  67 #define PCI_DEVICE_ID_GT_MP4            0x0004
  68 #define PCI_DEVICE_ID_GT_MP4A           0x0054
  69 #define PCI_DEVICE_ID_GT_MP6            0x0006
  70 #define PCI_DEVICE_ID_GT_MP6A           0x0056
  71 #define PCI_DEVICE_ID_GT_MP8            0x0008
  72 #define PCI_DEVICE_ID_GT_MP32           0x0032
  73
  74 #define PCIE_DEVICE_ID_GT_MP1           0x1501
  75 #define PCIE_DEVICE_ID_GT_MP2           0x1502
  76 #define PCIE_DEVICE_ID_GT_MP4           0x1504
  77 #define PCIE_DEVICE_ID_GT_MP8           0x1508
  78 #define PCIE_DEVICE_ID_GT_MP32          0x1532
  79
  80 #define PCI_DEVICE_ID_MP4M              0x4604  //modem
  81
  82 #define MAX_MP_DEV  8
  83 #define BD_MAX_PORT 32  /* Max serial port in one board */
  84 #define MAX_MP_PORT 256 /* Max serial port in one PC */
  85
  86 #define PORT_16C105XA   3
  87 #define PORT_16C105X    2
  88 #define PORT_16C55X             1
  89
  90 #define ENABLE          1
  91 #define DISABLE         0
  92
  93 /* ioctls */
  94 #define TIOCGNUMOFPORT          0x545F
  95 #define TIOCSMULTIECHO          0x5440
  96 #define TIOCSPTPNOECHO          0x5441
  97
  98 #define TIOCGOPTIONREG          0x5461
  99 #define TIOCGDISABLEIRQ         0x5462
 100 #define TIOCGENABLEIRQ          0x5463
 101 #define TIOCGSOFTRESET          0x5464
 102 #define TIOCGSOFTRESETR         0x5465
 103 #define TIOCGREGINFO            0x5466
 104 #define TIOCGGETLSR             0x5467
 105 #define TIOCGGETDEVID           0x5468
 106 #define TIOCGGETBDNO            0x5469
 107 #define TIOCGGETINTERFACE       0x546A
 108 #define TIOCGGETREV             0x546B
 109 #define TIOCGGETNRPORTS         0x546C
 110 #define TIOCGGETPORTTYPE        0x546D
 111 #define GETDEEPFIFO             0x54AA
 112 #define SETDEEPFIFO             0x54AB
 113 #define SETFCR                  0x54BA
 114 #define SETTTR                  0x54B1
 115 #define SETRTR                  0x54B2
 116 #define GETTTR                  0x54B3
 117 #define GETRTR                  0x54B4
 118
 119 /* multi-drop mode related ioctl commands */
 120 #define TIOCSMULTIDROP          0x5470
 121 #define TIOCSMDADDR             0x5471
 122 #define TIOCGMDADDR             0x5472
 123 #define TIOCSENDADDR            0x5473
 124
 125
 126 /* serial interface */
 127 #define RS232           1
 128 #define RS422PTP        2
 129 #define RS422MD         3
 130 #define RS485NE         4
 131 #define RS485ECHO       5
 132
 133 #define serial_inp(up, offset)      serial_in(up, offset)
 134 #define serial_outp(up, offset, value)  serial_out(up, offset, value)
 135
 136 #define PASS_LIMIT  256
 137 #define is_real_interrupt(irq)  ((irq) != 0)
 138
 139 #define PROBE_ANY   (~0)
 140
 141 static DEFINE_MUTEX(mp_mutex);
 142 #define MP_MUTEX_LOCK(x) mutex_lock(&(x))
 143 #define MP_MUTEX_UNLOCK(x) mutex_unlock(&(x))
 144 #define MP_STATE_LOCK(x) mutex_lock(&((x)->mutex))
 145 #define MP_STATE_UNLOCK(x) mutex_unlock(&((x)->mutex))
 146
 147
 148 #define UART_LSR_SPECIAL    0x1E
 149
 150 #define HIGH_BITS_OFFSET        ((sizeof(long)-sizeof(int))*8)
 151 #define uart_users(state)       ((state)->count + ((state)->info ? (state)->info->blocked_open : 0))
 152
 153
 154 //#define MP_DEBUG 1
 155 #undef MP_DEBUG
 156
 157 #ifdef MP_DEBUG
 158 #define DPRINTK(x...)   printk(x)
 159 #else
 160 #define DPRINTK(x...)   do { } while (0)
 161 #endif
 162
 163 #ifdef MP_DEBUG
 164 #define DEBUG_AUTOCONF(fmt...)  printk(fmt)
 165 #else
 166 #define DEBUG_AUTOCONF(fmt...)  do { } while (0)
 167 #endif
 168
 169 #ifdef MP_DEBUG
 170 #define DEBUG_INTR(fmt...)  printk(fmt)
 171 #else
 172 #define DEBUG_INTR(fmt...)  do { } while (0)
 173 #endif
 174
 175 #if defined(__i386__) && defined(CONFIG_M486)
 176 #define SERIAL_INLINE
 177 #endif
 178 #ifdef SERIAL_INLINE
 179 #define _INLINE_ inline
 180 #else
 181 #define _INLINE_
 182 #endif
 183
 184 #define TYPE_POLL       1
 185 #define TYPE_INTERRUPT  2
 186
 187
 188 struct mp_device_t {
 189         unsigned short  device_id;
 190         unsigned char   revision;
 191         char            *name;
 192         unsigned long   uart_access_addr;
 193         unsigned long   option_reg_addr;
 194         unsigned long   reserved_addr[4];
 195         int             irq;
 196         int             nr_ports;
 197         int             poll_type;
 198 };
 199
 200 typedef struct mppcibrd {
 201         char            *name;
 202         unsigned short  vendor_id;
 203         unsigned short  device_id;
 204 } mppcibrd_t;
 205
 206 static mppcibrd_t mp_pciboards[] = {
 207
 208         { "Multi-1 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP1} ,
 209         { "Multi-2 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP2} ,
 210         { "Multi-4 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP4} ,
 211         { "Multi-4 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP4A} ,
 212         { "Multi-6 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP6} ,
 213         { "Multi-6 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP6A} ,
 214         { "Multi-8 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP8} ,
 215         { "Multi-32 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP32} ,
 216
 217         { "Multi-1P PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP1P} ,
 218         { "Multi-2S1P PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP2S1P} ,
 219
 220         { "Multi-4(GT) PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_GT_MP4} ,
 221         { "Multi-4(GT) PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_GT_MP4A} ,
 222         { "Multi-6(GT) PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_GT_MP6} ,
 223         { "Multi-6(GT) PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_GT_MP6A} ,
 224         { "Multi-8(GT) PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_GT_MP8} ,
 225         { "Multi-32(GT) PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_GT_MP32} ,
 226
 227         { "Multi-1 PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP1} ,
 228         { "Multi-2 PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP2} ,
 229         { "Multi-4 PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP4} ,
 230         { "Multi-8 PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP8} ,
 231         { "Multi-32 PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP32} ,
 232
 233         { "Multi-1 PCIe E", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP1E} ,
 234         { "Multi-2 PCIe E", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP2E} ,
 235         { "Multi-2 PCIe B", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP2B} ,
 236         { "Multi-4 PCIe B", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP4B} ,
 237         { "Multi-8 PCIe B", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP8B} ,
 238
 239         { "Multi-1(GT) PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_GT_MP1} ,
 240         { "Multi-2(GT) PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_GT_MP2} ,
 241         { "Multi-4(GT) PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_GT_MP4} ,
 242         { "Multi-8(GT) PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_GT_MP8} ,
 243         { "Multi-32(GT) PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_GT_MP32} ,
 244
 245         { "Multi-4M PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP4M} ,
 246 };
 247
 248 struct mp_port {
 249         struct sb_uart_port port;
 250
 251         struct timer_list   timer;      /* "no irq" timer */
 252         struct list_head    list;       /* ports on this IRQ */
 253         unsigned int        capabilities;   /* port capabilities */
 254         unsigned short      rev;
 255         unsigned char       acr;
 256         unsigned char       ier;
 257         unsigned char       lcr;
 258         unsigned char       mcr;
 259         unsigned char       mcr_mask;   /* mask of user bits */
 260         unsigned char       mcr_force;  /* mask of forced bits */
 261         unsigned char       lsr_break_flag;
 262
 263         void            (*pm)(struct sb_uart_port *port,
 264                         unsigned int state, unsigned int old);
 265         struct mp_device_t *device;
 266         unsigned long   interface_config_addr;
 267         unsigned long   option_base_addr;
 268         unsigned char   interface;
 269         unsigned char   poll_type;
 270 };
 271
 272 struct irq_info {
 273         spinlock_t      lock;
 274         struct list_head    *head;
 275 };
 276
 277 struct sb105x_uart_config {
 278         char    *name;
 279         int     dfl_xmit_fifo_size;
 280         int     flags;
 281 };
 282
 283 static const struct sb105x_uart_config uart_config[] = {
 284         { "unknown",    1,  0 },
 285         { "16550A", 16, UART_CLEAR_FIFO | UART_USE_FIFO },
 286         { "SB16C1050",    128,    UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
 287         { "SB16C1050A",    128,    UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
 288 };
 289
 290
 291