1 /**************************************************************************
3 * Copyright (C) 2000-2008 Alacritech, Inc. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above
12 * copyright notice, this list of conditions and the following
13 * disclaimer in the documentation and/or other materials provided
14 * with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
17 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
24 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
26 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * The views and conclusions contained in the software and documentation
30 * are those of the authors and should not be interpreted as representing
31 * official policies, either expressed or implied, of Alacritech, Inc.
33 * Parts developed by LinSysSoft Sahara team
35 **************************************************************************/
40 * The SXG driver for Alacritech's 10Gbe products.
42 * NOTE: This is the standard, non-accelerated version of Alacritech's
46 #include <linux/kernel.h>
47 #include <linux/string.h>
48 #include <linux/errno.h>
49 #include <linux/module.h>
50 #include <linux/moduleparam.h>
51 #include <linux/firmware.h>
52 #include <linux/ioport.h>
53 #include <linux/slab.h>
54 #include <linux/interrupt.h>
55 #include <linux/timer.h>
56 #include <linux/pci.h>
57 #include <linux/spinlock.h>
58 #include <linux/init.h>
59 #include <linux/netdevice.h>
60 #include <linux/etherdevice.h>
61 #include <linux/ethtool.h>
62 #include <linux/skbuff.h>
63 #include <linux/delay.h>
64 #include <linux/types.h>
65 #include <linux/dma-mapping.h>
66 #include <linux/mii.h>
69 #include <linux/tcp.h>
70 #include <linux/ipv6.h>
72 #define SLIC_GET_STATS_ENABLED 0
73 #define LINUX_FREES_ADAPTER_RESOURCES 1
74 #define SXG_OFFLOAD_IP_CHECKSUM 0
75 #define SXG_POWER_MANAGEMENT_ENABLED 0
78 #define SXG_UCODE_DEBUG 0
86 #include "sxgphycode-1.2.h"
88 static int sxg_allocate_buffer_memory(struct adapter_t
*adapter
, u32 Size
,
89 enum sxg_buffer_type BufferType
);
90 static int sxg_allocate_rcvblock_complete(struct adapter_t
*adapter
,
92 dma_addr_t PhysicalAddress
,
94 static void sxg_allocate_sgl_buffer_complete(struct adapter_t
*adapter
,
95 struct sxg_scatter_gather
*SxgSgl
,
96 dma_addr_t PhysicalAddress
,
99 static void sxg_mcast_init_crc32(void);
100 static int sxg_entry_open(struct net_device
*dev
);
101 static int sxg_second_open(struct net_device
* dev
);
102 static int sxg_entry_halt(struct net_device
*dev
);
103 static int sxg_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
);
104 static int sxg_send_packets(struct sk_buff
*skb
, struct net_device
*dev
);
105 static int sxg_transmit_packet(struct adapter_t
*adapter
, struct sk_buff
*skb
);
106 static int sxg_dumb_sgl(struct sxg_x64_sgl
*pSgl
,
107 struct sxg_scatter_gather
*SxgSgl
);
109 static void sxg_handle_interrupt(struct adapter_t
*adapter
, int *work_done
,
111 static void sxg_interrupt(struct adapter_t
*adapter
);
112 static int sxg_poll(struct napi_struct
*napi
, int budget
);
113 static int sxg_process_isr(struct adapter_t
*adapter
, u32 MessageId
);
114 static u32
sxg_process_event_queue(struct adapter_t
*adapter
, u32 RssId
,
115 int *sxg_napi_continue
, int *work_done
, int budget
);
116 static void sxg_complete_slow_send(struct adapter_t
*adapter
);
117 static struct sk_buff
*sxg_slow_receive(struct adapter_t
*adapter
,
118 struct sxg_event
*Event
);
119 static void sxg_process_rcv_error(struct adapter_t
*adapter
, u32 ErrorStatus
);
120 static bool sxg_mac_filter(struct adapter_t
*adapter
,
121 struct ether_header
*EtherHdr
, ushort length
);
122 static struct net_device_stats
*sxg_get_stats(struct net_device
* dev
);
123 void sxg_free_resources(struct adapter_t
*adapter
);
124 void sxg_free_rcvblocks(struct adapter_t
*adapter
);
125 void sxg_free_sgl_buffers(struct adapter_t
*adapter
);
126 void sxg_unmap_resources(struct adapter_t
*adapter
);
127 void sxg_free_mcast_addrs(struct adapter_t
*adapter
);
128 void sxg_collect_statistics(struct adapter_t
*adapter
);
129 static int sxg_register_interrupt(struct adapter_t
*adapter
);
130 static void sxg_remove_isr(struct adapter_t
*adapter
);
131 static irqreturn_t
sxg_isr(int irq
, void *dev_id
);
133 static void sxg_watchdog(unsigned long data
);
134 static void sxg_update_link_status (struct work_struct
*work
);
139 static int sxg_mac_set_address(struct net_device
*dev
, void *ptr
);
141 static void sxg_mcast_set_list(struct net_device
*dev
);
143 static int sxg_adapter_set_hwaddr(struct adapter_t
*adapter
);
145 static int sxg_initialize_adapter(struct adapter_t
*adapter
);
146 static void sxg_stock_rcv_buffers(struct adapter_t
*adapter
);
147 static void sxg_complete_descriptor_blocks(struct adapter_t
*adapter
,
148 unsigned char Index
);
149 int sxg_change_mtu (struct net_device
*netdev
, int new_mtu
);
150 static int sxg_initialize_link(struct adapter_t
*adapter
);
151 static int sxg_phy_init(struct adapter_t
*adapter
);
152 static void sxg_link_event(struct adapter_t
*adapter
);
153 static enum SXG_LINK_STATE
sxg_get_link_state(struct adapter_t
*adapter
);
154 static void sxg_link_state(struct adapter_t
*adapter
,
155 enum SXG_LINK_STATE LinkState
);
156 static int sxg_write_mdio_reg(struct adapter_t
*adapter
,
157 u32 DevAddr
, u32 RegAddr
, u32 Value
);
158 static int sxg_read_mdio_reg(struct adapter_t
*adapter
,
159 u32 DevAddr
, u32 RegAddr
, u32
*pValue
);
160 static void sxg_set_mcast_addr(struct adapter_t
*adapter
);
162 static unsigned int sxg_first_init
= 1;
163 static char *sxg_banner
=
164 "Alacritech SLIC Technology(tm) Server and Storage \
165 10Gbe Accelerator (Non-Accelerated)\n";
167 static int sxg_debug
= 1;
168 static int debug
= -1;
169 static struct net_device
*head_netdevice
= NULL
;
171 static struct sxgbase_driver sxg_global
= {
174 static int intagg_delay
= 100;
175 static u32 dynamic_intagg
= 0;
177 char sxg_driver_name
[] = "sxg_nic";
178 #define DRV_AUTHOR "Alacritech, Inc. Engineering"
179 #define DRV_DESCRIPTION \
180 "Alacritech SLIC Techonology(tm) Non-Accelerated 10Gbe Driver"
181 #define DRV_COPYRIGHT \
182 "Copyright 2000-2008 Alacritech, Inc. All rights reserved."
184 MODULE_AUTHOR(DRV_AUTHOR
);
185 MODULE_DESCRIPTION(DRV_DESCRIPTION
);
186 MODULE_LICENSE("GPL");
188 module_param(dynamic_intagg
, int, 0);
189 MODULE_PARM_DESC(dynamic_intagg
, "Dynamic Interrupt Aggregation Setting");
190 module_param(intagg_delay
, int, 0);
191 MODULE_PARM_DESC(intagg_delay
, "uSec Interrupt Aggregation Delay");
193 static struct pci_device_id sxg_pci_tbl
[] __devinitdata
= {
194 {PCI_DEVICE(SXG_VENDOR_ID
, SXG_DEVICE_ID
)},
198 MODULE_DEVICE_TABLE(pci
, sxg_pci_tbl
);
200 static inline void sxg_reg32_write(void __iomem
*reg
, u32 value
, bool flush
)
207 static inline void sxg_reg64_write(struct adapter_t
*adapter
, void __iomem
*reg
,
210 u32 value_high
= (u32
) (value
>> 32);
211 u32 value_low
= (u32
) (value
& 0x00000000FFFFFFFF);
214 spin_lock_irqsave(&adapter
->Bit64RegLock
, flags
);
215 writel(value_high
, (void __iomem
*)(&adapter
->UcodeRegs
[cpu
].Upper
));
216 writel(value_low
, reg
);
217 spin_unlock_irqrestore(&adapter
->Bit64RegLock
, flags
);
220 static void sxg_init_driver(void)
222 if (sxg_first_init
) {
223 DBG_ERROR("sxg: %s sxg_first_init set jiffies[%lx]\n",
226 spin_lock_init(&sxg_global
.driver_lock
);
230 static void sxg_dbg_macaddrs(struct adapter_t
*adapter
)
232 DBG_ERROR(" (%s) curr %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n",
233 adapter
->netdev
->name
, adapter
->currmacaddr
[0],
234 adapter
->currmacaddr
[1], adapter
->currmacaddr
[2],
235 adapter
->currmacaddr
[3], adapter
->currmacaddr
[4],
236 adapter
->currmacaddr
[5]);
237 DBG_ERROR(" (%s) mac %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n",
238 adapter
->netdev
->name
, adapter
->macaddr
[0],
239 adapter
->macaddr
[1], adapter
->macaddr
[2],
240 adapter
->macaddr
[3], adapter
->macaddr
[4],
241 adapter
->macaddr
[5]);
246 static struct sxg_driver SxgDriver
;
249 static struct sxg_trace_buffer LSxgTraceBuffer
;
251 static struct sxg_trace_buffer
*SxgTraceBuffer
= NULL
;
256 int sxg_register_intr(struct adapter_t
*adapter
);
257 int sxg_enable_msi_x(struct adapter_t
*adapter
);
258 int sxg_add_msi_isr(struct adapter_t
*adapter
);
259 void sxg_remove_msix_isr(struct adapter_t
*adapter
);
260 int sxg_set_interrupt_capability(struct adapter_t
*adapter
);
262 int sxg_set_interrupt_capability(struct adapter_t
*adapter
)
266 ret
= sxg_enable_msi_x(adapter
);
267 if (ret
!= STATUS_SUCCESS
) {
268 adapter
->msi_enabled
= FALSE
;
269 DBG_ERROR("sxg_set_interrupt_capability MSI-X Disable\n");
271 adapter
->msi_enabled
= TRUE
;
272 DBG_ERROR("sxg_set_interrupt_capability MSI-X Enable\n");
277 int sxg_register_intr(struct adapter_t
*adapter
)
281 if (adapter
->msi_enabled
) {
282 ret
= sxg_add_msi_isr(adapter
);
285 DBG_ERROR("MSI-X Enable Failed. Using Pin INT\n");
286 ret
= sxg_register_interrupt(adapter
);
287 if (ret
!= STATUS_SUCCESS
) {
288 DBG_ERROR("sxg_register_interrupt Failed\n");
294 int sxg_enable_msi_x(struct adapter_t
*adapter
)
298 adapter
->nr_msix_entries
= 1;
299 adapter
->msi_entries
= kmalloc(adapter
->nr_msix_entries
*
300 sizeof(struct msix_entry
),GFP_KERNEL
);
301 if (!adapter
->msi_entries
) {
302 DBG_ERROR("%s:MSI Entries memory allocation Failed\n",__func__
);
305 memset(adapter
->msi_entries
, 0, adapter
->nr_msix_entries
*
306 sizeof(struct msix_entry
));
308 ret
= pci_enable_msix(adapter
->pcidev
, adapter
->msi_entries
,
309 adapter
->nr_msix_entries
);
311 DBG_ERROR("Enabling MSI-X with %d vectors failed\n",
312 adapter
->nr_msix_entries
);
313 /*Should try with less vector returned.*/
314 kfree(adapter
->msi_entries
);
315 return STATUS_FAILURE
; /*MSI-X Enable failed.*/
317 return (STATUS_SUCCESS
);
320 int sxg_add_msi_isr(struct adapter_t
*adapter
)
324 if (!adapter
->intrregistered
) {
325 for (i
=0; i
<adapter
->nr_msix_entries
; i
++) {
326 ret
= request_irq (adapter
->msi_entries
[i
].vector
,
329 adapter
->netdev
->name
,
332 DBG_ERROR("sxg: MSI-X request_irq (%s) "
333 "FAILED [%x]\n", adapter
->netdev
->name
,
339 adapter
->msi_enabled
= TRUE
;
340 adapter
->intrregistered
= 1;
341 adapter
->IntRegistered
= TRUE
;
342 return (STATUS_SUCCESS
);
345 void sxg_remove_msix_isr(struct adapter_t
*adapter
)
348 struct net_device
*netdev
= adapter
->netdev
;
350 for(i
=0; i
< adapter
->nr_msix_entries
;i
++)
352 vector
= adapter
->msi_entries
[i
].vector
;
353 DBG_ERROR("%s : Freeing IRQ vector#%d\n",__FUNCTION__
,vector
);
354 free_irq(vector
,netdev
);
359 static void sxg_remove_isr(struct adapter_t
*adapter
)
361 struct net_device
*netdev
= adapter
->netdev
;
362 if (adapter
->msi_enabled
)
363 sxg_remove_msix_isr(adapter
);
365 free_irq(adapter
->netdev
->irq
, netdev
);
368 void sxg_reset_interrupt_capability(struct adapter_t
*adapter
)
370 if (adapter
->msi_enabled
) {
371 pci_disable_msix(adapter
->pcidev
);
372 kfree(adapter
->msi_entries
);
373 adapter
->msi_entries
= NULL
;
379 * sxg_download_microcode
381 * Download Microcode to Sahara adapter using the Linux
382 * Firmware module to get the ucode.sys file.
385 * adapter - A pointer to our adapter structure
386 * UcodeSel - microcode file selection
391 static bool sxg_download_microcode(struct adapter_t
*adapter
,
392 enum SXG_UCODE_SEL UcodeSel
)
394 const struct firmware
*fw
;
395 const char *file
= "";
396 struct sxg_hw_regs
*HwRegs
= adapter
->HwRegs
;
402 u32 BaseAddress
, AddressOffset
, Address
;
407 u32 num_sections
= 0;
409 u32 sectionStart
[16];
411 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "DnldUcod",
415 * This routine is only implemented to download the microcode
416 * for the Revision B Sahara chip. Rev A and Diagnostic
417 * microcode is not supported at this time. If Rev A or
418 * diagnostic ucode is required, this routine will obviously
419 * need to change. Also, eventually need to add support for
420 * Rev B checked version of ucode. That's easy enough once
421 * the free version of Rev B works.
423 ASSERT(UcodeSel
== SXG_UCODE_SYSTEM
);
424 ASSERT(adapter
->asictype
== SAHARA_REV_B
);
426 file
= "sxg/saharadbgdownloadB.sys";
428 file
= "sxg/saharadownloadB.sys";
430 ret
= request_firmware(&fw
, file
, &adapter
->pcidev
->dev
);
432 DBG_ERROR("%s SXG_NIC: Failed to load firmware %s\n", __func__
,file
);
437 * The microcode .sys file contains starts with a 4 byte word containing
438 * the number of sections. That is followed by "num_sections" 4 byte
439 * words containing each "section" size. That is followed num_sections
440 * 4 byte words containing each section "start" address.
442 * Following the above header, the .sys file contains num_sections,
443 * where each section size is specified, newline delineatetd 12 byte
444 * microcode instructions.
446 num_sections
= *(u32
*)(fw
->data
+ index
);
448 ASSERT(num_sections
<= 3);
449 for (i
= 0; i
< num_sections
; i
++) {
450 sectionSize
[i
] = *(u32
*)(fw
->data
+ index
);
453 for (i
= 0; i
< num_sections
; i
++) {
454 sectionStart
[i
] = *(u32
*)(fw
->data
+ index
);
458 /* First, reset the card */
459 WRITE_REG(HwRegs
->Reset
, 0xDEAD, FLUSH
);
461 HwRegs
= adapter
->HwRegs
;
464 * Download each section of the microcode as specified in
465 * sectionSize[index] to sectionStart[index] address. As
466 * described above, the .sys file contains 12 byte word
467 * microcode instructions. The *download.sys file is generated
468 * using the objtosys.exe utility that was built for Sahara
471 /* See usage of this below when we read back for parity */
473 instruction
= *(u32
*)(fw
->data
+ index
);
476 for (Section
= 0; Section
< num_sections
; Section
++) {
477 BaseAddress
= sectionStart
[Section
];
478 /* Size in instructions */
479 ThisSectionSize
= sectionSize
[Section
] / 12;
480 for (AddressOffset
= 0; AddressOffset
< ThisSectionSize
;
482 u32 first_instr
= 0; /* See comment below */
484 Address
= BaseAddress
+ AddressOffset
;
485 ASSERT((Address
& ~MICROCODE_ADDRESS_MASK
) == 0);
486 /* Write instruction bits 31 - 0 (low) */
487 first_instr
= instruction
;
488 WRITE_REG(HwRegs
->UcodeDataLow
, instruction
, FLUSH
);
489 instruction
= *(u32
*)(fw
->data
+ index
);
490 index
+= 4; /* Advance to the "next" instruction */
492 /* Write instruction bits 63-32 (middle) */
493 WRITE_REG(HwRegs
->UcodeDataMiddle
, instruction
, FLUSH
);
494 instruction
= *(u32
*)(fw
->data
+ index
);
495 index
+= 4; /* Advance to the "next" instruction */
497 /* Write instruction bits 95-64 (high) */
498 WRITE_REG(HwRegs
->UcodeDataHigh
, instruction
, FLUSH
);
499 instruction
= *(u32
*)(fw
->data
+ index
);
500 index
+= 4; /* Advance to the "next" instruction */
502 /* Write instruction address with the WRITE bit set */
503 WRITE_REG(HwRegs
->UcodeAddr
,
504 (Address
| MICROCODE_ADDRESS_WRITE
), FLUSH
);
506 * Sahara bug in the ucode download logic - the write to DataLow
507 * for the next instruction could get corrupted. To avoid this,
508 * write to DataLow again for this instruction (which may get
509 * corrupted, but it doesn't matter), then increment the address
510 * and write the data for the next instruction to DataLow. That
511 * write should succeed.
513 WRITE_REG(HwRegs
->UcodeDataLow
, first_instr
, FLUSH
);
517 * Now repeat the entire operation reading the instruction back and
518 * checking for parity errors
522 for (Section
= 0; Section
< num_sections
; Section
++) {
523 BaseAddress
= sectionStart
[Section
];
524 /* Size in instructions */
525 ThisSectionSize
= sectionSize
[Section
] / 12;
526 for (AddressOffset
= 0; AddressOffset
< ThisSectionSize
;
528 Address
= BaseAddress
+ AddressOffset
;
529 /* Write the address with the READ bit set */
530 WRITE_REG(HwRegs
->UcodeAddr
,
531 (Address
| MICROCODE_ADDRESS_READ
), FLUSH
);
532 /* Read it back and check parity bit. */
533 READ_REG(HwRegs
->UcodeAddr
, ValueRead
);
534 if (ValueRead
& MICROCODE_ADDRESS_PARITY
) {
535 DBG_ERROR("sxg: %s PARITY ERROR\n",
538 return FALSE
; /* Parity error */
540 ASSERT((ValueRead
& MICROCODE_ADDRESS_MASK
) == Address
);
541 /* Read the instruction back and compare */
542 /* First instruction */
543 instruction
= *(u32
*)(fw
->data
+ index
);
545 READ_REG(HwRegs
->UcodeDataLow
, ValueRead
);
546 if (ValueRead
!= instruction
) {
547 DBG_ERROR("sxg: %s MISCOMPARE LOW\n",
549 return FALSE
; /* Miscompare */
551 instruction
= *(u32
*)(fw
->data
+ index
);
553 READ_REG(HwRegs
->UcodeDataMiddle
, ValueRead
);
554 if (ValueRead
!= instruction
) {
555 DBG_ERROR("sxg: %s MISCOMPARE MIDDLE\n",
557 return FALSE
; /* Miscompare */
559 instruction
= *(u32
*)(fw
->data
+ index
);
561 READ_REG(HwRegs
->UcodeDataHigh
, ValueRead
);
562 if (ValueRead
!= instruction
) {
563 DBG_ERROR("sxg: %s MISCOMPARE HIGH\n",
565 return FALSE
; /* Miscompare */
570 /* download finished */
571 release_firmware(fw
);
572 /* Everything OK, Go. */
573 WRITE_REG(HwRegs
->UcodeAddr
, MICROCODE_ADDRESS_GO
, FLUSH
);
576 * Poll the CardUp register to wait for microcode to initialize
577 * Give up after 10,000 attemps (500ms).
579 for (i
= 0; i
< 10000; i
++) {
581 READ_REG(adapter
->UcodeRegs
[0].CardUp
, ValueRead
);
582 if (ValueRead
== 0xCAFE) {
587 DBG_ERROR("sxg: %s TIMEOUT bringing up card - verify MICROCODE\n", __func__
);
589 return FALSE
; /* Timeout */
592 * Now write the LoadSync register. This is used to
593 * synchronize with the card so it can scribble on the memory
594 * that contained 0xCAFE from the "CardUp" step above
596 if (UcodeSel
== SXG_UCODE_SYSTEM
) {
597 WRITE_REG(adapter
->UcodeRegs
[0].LoadSync
, 0, FLUSH
);
600 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "XDnldUcd",
606 * sxg_allocate_resources - Allocate memory and locks
609 * adapter - A pointer to our adapter structure
613 static int sxg_allocate_resources(struct adapter_t
*adapter
)
615 int status
= STATUS_SUCCESS
;
616 u32 RssIds
, IsrCount
;
617 /* struct sxg_xmt_ring *XmtRing; */
618 /* struct sxg_rcv_ring *RcvRing; */
620 DBG_ERROR("%s ENTER\n", __func__
);
622 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "AllocRes",
625 /* Windows tells us how many CPUs it plans to use for */
627 RssIds
= SXG_RSS_CPU_COUNT(adapter
);
628 IsrCount
= adapter
->msi_enabled
? RssIds
: 1;
630 DBG_ERROR("%s Setup the spinlocks\n", __func__
);
632 /* Allocate spinlocks and initialize listheads first. */
633 spin_lock_init(&adapter
->RcvQLock
);
634 spin_lock_init(&adapter
->SglQLock
);
635 spin_lock_init(&adapter
->XmtZeroLock
);
636 spin_lock_init(&adapter
->Bit64RegLock
);
637 spin_lock_init(&adapter
->AdapterLock
);
638 atomic_set(&adapter
->pending_allocations
, 0);
640 DBG_ERROR("%s Setup the lists\n", __func__
);
642 InitializeListHead(&adapter
->FreeRcvBuffers
);
643 InitializeListHead(&adapter
->FreeRcvBlocks
);
644 InitializeListHead(&adapter
->AllRcvBlocks
);
645 InitializeListHead(&adapter
->FreeSglBuffers
);
646 InitializeListHead(&adapter
->AllSglBuffers
);
649 * Mark these basic allocations done. This flags essentially
650 * tells the SxgFreeResources routine that it can grab spinlocks
651 * and reference listheads.
653 adapter
->BasicAllocations
= TRUE
;
655 * Main allocation loop. Start with the maximum supported by
656 * the microcode and back off if memory allocation
657 * fails. If we hit a minimum, fail.
661 DBG_ERROR("%s Allocate XmtRings size[%x]\n", __func__
,
662 (unsigned int)(sizeof(struct sxg_xmt_ring
) * 1));
665 * Start with big items first - receive and transmit rings.
666 * At the moment I'm going to keep the ring size fixed and
667 * adjust the TCBs if we fail. Later we might
668 * consider reducing the ring size as well..
670 adapter
->XmtRings
= pci_alloc_consistent(adapter
->pcidev
,
671 sizeof(struct sxg_xmt_ring
) *
673 &adapter
->PXmtRings
);
674 DBG_ERROR("%s XmtRings[%p]\n", __func__
, adapter
->XmtRings
);
676 if (!adapter
->XmtRings
) {
677 goto per_tcb_allocation_failed
;
679 memset(adapter
->XmtRings
, 0, sizeof(struct sxg_xmt_ring
) * 1);
681 DBG_ERROR("%s Allocate RcvRings size[%x]\n", __func__
,
682 (unsigned int)(sizeof(struct sxg_rcv_ring
) * 1));
684 pci_alloc_consistent(adapter
->pcidev
,
685 sizeof(struct sxg_rcv_ring
) * 1,
686 &adapter
->PRcvRings
);
687 DBG_ERROR("%s RcvRings[%p]\n", __func__
, adapter
->RcvRings
);
688 if (!adapter
->RcvRings
) {
689 goto per_tcb_allocation_failed
;
691 memset(adapter
->RcvRings
, 0, sizeof(struct sxg_rcv_ring
) * 1);
692 adapter
->ucode_stats
= kzalloc(sizeof(struct sxg_ucode_stats
), GFP_ATOMIC
);
693 adapter
->pucode_stats
= pci_map_single(adapter
->pcidev
,
694 adapter
->ucode_stats
,
695 sizeof(struct sxg_ucode_stats
),
697 // memset(adapter->ucode_stats, 0, sizeof(struct sxg_ucode_stats));
700 per_tcb_allocation_failed
:
701 /* an allocation failed. Free any successful allocations. */
702 if (adapter
->XmtRings
) {
703 pci_free_consistent(adapter
->pcidev
,
704 sizeof(struct sxg_xmt_ring
) * 1,
707 adapter
->XmtRings
= NULL
;
709 if (adapter
->RcvRings
) {
710 pci_free_consistent(adapter
->pcidev
,
711 sizeof(struct sxg_rcv_ring
) * 1,
714 adapter
->RcvRings
= NULL
;
716 /* Loop around and try again.... */
717 if (adapter
->ucode_stats
) {
718 pci_unmap_single(adapter
->pcidev
,
719 sizeof(struct sxg_ucode_stats
),
720 adapter
->pucode_stats
, PCI_DMA_FROMDEVICE
);
721 adapter
->ucode_stats
= NULL
;
726 DBG_ERROR("%s Initialize RCV ZERO and XMT ZERO rings\n", __func__
);
727 /* Initialize rcv zero and xmt zero rings */
728 SXG_INITIALIZE_RING(adapter
->RcvRingZeroInfo
, SXG_RCV_RING_SIZE
);
729 SXG_INITIALIZE_RING(adapter
->XmtRingZeroInfo
, SXG_XMT_RING_SIZE
);
731 /* Sanity check receive data structure format */
732 /* ASSERT((adapter->ReceiveBufferSize == SXG_RCV_DATA_BUFFER_SIZE) ||
733 (adapter->ReceiveBufferSize == SXG_RCV_JUMBO_BUFFER_SIZE)); */
734 ASSERT(sizeof(struct sxg_rcv_descriptor_block
) ==
735 SXG_RCV_DESCRIPTOR_BLOCK_SIZE
);
737 DBG_ERROR("%s Allocate EventRings size[%x]\n", __func__
,
738 (unsigned int)(sizeof(struct sxg_event_ring
) * RssIds
));
740 /* Allocate event queues. */
741 adapter
->EventRings
= pci_alloc_consistent(adapter
->pcidev
,
742 sizeof(struct sxg_event_ring
) *
744 &adapter
->PEventRings
);
746 if (!adapter
->EventRings
) {
747 /* Caller will call SxgFreeAdapter to clean up above
749 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "XAResF8",
750 adapter
, SXG_MAX_ENTRIES
, 0, 0);
751 status
= STATUS_RESOURCES
;
752 goto per_tcb_allocation_failed
;
754 memset(adapter
->EventRings
, 0, sizeof(struct sxg_event_ring
) * RssIds
);
756 DBG_ERROR("%s Allocate ISR size[%x]\n", __func__
, IsrCount
);
758 adapter
->Isr
= pci_alloc_consistent(adapter
->pcidev
,
759 IsrCount
, &adapter
->PIsr
);
761 /* Caller will call SxgFreeAdapter to clean up above
763 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "XAResF9",
764 adapter
, SXG_MAX_ENTRIES
, 0, 0);
765 status
= STATUS_RESOURCES
;
766 goto per_tcb_allocation_failed
;
768 memset(adapter
->Isr
, 0, sizeof(u32
) * IsrCount
);
770 DBG_ERROR("%s Allocate shared XMT ring zero index location size[%x]\n",
771 __func__
, (unsigned int)sizeof(u32
));
773 /* Allocate shared XMT ring zero index location */
774 adapter
->XmtRingZeroIndex
= pci_alloc_consistent(adapter
->pcidev
,
778 if (!adapter
->XmtRingZeroIndex
) {
779 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "XAResF10",
780 adapter
, SXG_MAX_ENTRIES
, 0, 0);
781 status
= STATUS_RESOURCES
;
782 goto per_tcb_allocation_failed
;
784 memset(adapter
->XmtRingZeroIndex
, 0, sizeof(u32
));
786 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "XAlcResS",
787 adapter
, SXG_MAX_ENTRIES
, 0, 0);
795 * Set up PCI Configuration space
798 * pcidev - A pointer to our adapter structure
800 static void sxg_config_pci(struct pci_dev
*pcidev
)
805 pci_read_config_word(pcidev
, PCI_COMMAND
, &pci_command
);
806 DBG_ERROR("sxg: %s PCI command[%4.4x]\n", __func__
, pci_command
);
807 /* Set the command register */
808 new_command
= pci_command
| (
809 /* Memory Space Enable */
811 /* Bus master enable */
813 /* Memory write and invalidate */
814 PCI_COMMAND_INVALIDATE
|
815 /* Parity error response */
819 /* Fast back-to-back */
820 PCI_COMMAND_FAST_BACK
);
821 if (pci_command
!= new_command
) {
822 DBG_ERROR("%s -- Updating PCI COMMAND register %4.4x->%4.4x.\n",
823 __func__
, pci_command
, new_command
);
824 pci_write_config_word(pcidev
, PCI_COMMAND
, new_command
);
830 * @adapter : Pointer to the adapter structure for the card
831 * This function will read the configuration data from EEPROM/FLASH
833 static inline int sxg_read_config(struct adapter_t
*adapter
)
835 /* struct sxg_config data; */
836 struct sxg_config
*config
;
837 struct sw_cfg_data
*data
;
839 unsigned long status
;
841 config
= pci_alloc_consistent(adapter
->pcidev
,
842 sizeof(struct sxg_config
), &p_addr
);
846 * We cant get even this much memory. Raise a hell
849 printk(KERN_ERR
"%s : Could not allocate memory for reading \
850 EEPROM\n", __FUNCTION__
);
854 data
= &config
->SwCfg
;
856 /* Initialize (reflective memory) status register */
857 WRITE_REG(adapter
->UcodeRegs
[0].ConfigStat
, SXG_CFG_TIMEOUT
, TRUE
);
859 /* Send request to fetch configuration data */
860 WRITE_REG64(adapter
, adapter
->UcodeRegs
[0].Config
, p_addr
, 0);
861 for(i
=0; i
<1000; i
++) {
862 READ_REG(adapter
->UcodeRegs
[0].ConfigStat
, status
);
863 if (status
!= SXG_CFG_TIMEOUT
)
865 mdelay(1); /* Do we really need this */
869 /* Config read from EEPROM succeeded */
870 case SXG_CFG_LOAD_EEPROM
:
871 /* Config read from Flash succeeded */
872 case SXG_CFG_LOAD_FLASH
:
874 * Copy the MAC address to adapter structure
875 * TODO: We are not doing the remaining part : FRU, etc
877 memcpy(adapter
->macaddr
, data
->MacAddr
[0].MacAddr
,
878 sizeof(struct sxg_config_mac
));
880 case SXG_CFG_TIMEOUT
:
881 case SXG_CFG_LOAD_INVALID
:
882 case SXG_CFG_LOAD_ERROR
:
883 default: /* Fix default handler later */
884 printk(KERN_WARNING
"%s : We could not read the config \
885 word. Status = %ld\n", __FUNCTION__
, status
);
888 pci_free_consistent(adapter
->pcidev
, sizeof(struct sw_cfg_data
), data
,
890 if (adapter
->netdev
) {
891 memcpy(adapter
->netdev
->dev_addr
, adapter
->currmacaddr
, 6);
892 memcpy(adapter
->netdev
->perm_addr
, adapter
->currmacaddr
, 6);
894 sxg_dbg_macaddrs(adapter
);
899 static const struct net_device_ops sxg_netdev_ops
= {
900 .ndo_open
= sxg_entry_open
,
901 .ndo_stop
= sxg_entry_halt
,
902 .ndo_start_xmit
= sxg_send_packets
,
903 .ndo_do_ioctl
= sxg_ioctl
,
904 .ndo_change_mtu
= sxg_change_mtu
,
905 .ndo_get_stats
= sxg_get_stats
,
906 .ndo_set_multicast_list
= sxg_mcast_set_list
,
907 .ndo_validate_addr
= eth_validate_addr
,
909 .ndo_set_mac_address
= sxg_mac_set_address
,
911 .ndo_set_mac_address
= eth_mac_addr
,
915 static int sxg_entry_probe(struct pci_dev
*pcidev
,
916 const struct pci_device_id
*pci_tbl_entry
)
918 static int did_version
= 0;
920 struct net_device
*netdev
;
921 struct adapter_t
*adapter
;
922 void __iomem
*memmapped_ioaddr
;
924 ulong mmio_start
= 0;
926 unsigned char revision_id
;
928 DBG_ERROR("sxg: %s 2.6 VERSION ENTER jiffies[%lx] cpu %d\n",
929 __func__
, jiffies
, smp_processor_id());
931 /* Initialize trace buffer */
933 SxgTraceBuffer
= &LSxgTraceBuffer
;
934 SXG_TRACE_INIT(SxgTraceBuffer
, TRACE_NOISY
);
937 sxg_global
.dynamic_intagg
= dynamic_intagg
;
939 err
= pci_enable_device(pcidev
);
941 DBG_ERROR("Call pci_enable_device(%p) status[%x]\n", pcidev
, err
);
946 if (sxg_debug
> 0 && did_version
++ == 0) {
947 printk(KERN_INFO
"%s\n", sxg_banner
);
948 printk(KERN_INFO
"%s\n", SXG_DRV_VERSION
);
951 pci_read_config_byte(pcidev
, PCI_REVISION_ID
, &revision_id
);
953 if (!(err
= pci_set_dma_mask(pcidev
, DMA_BIT_MASK(64)))) {
954 DBG_ERROR("pci_set_dma_mask(DMA_BIT_MASK(64)) successful\n");
956 if ((err
= pci_set_dma_mask(pcidev
, DMA_BIT_MASK(32)))) {
958 ("No usable DMA configuration, aborting err[%x]\n",
962 DBG_ERROR("pci_set_dma_mask(DMA_BIT_MASK(32)) successful\n");
965 DBG_ERROR("Call pci_request_regions\n");
967 err
= pci_request_regions(pcidev
, sxg_driver_name
);
969 DBG_ERROR("pci_request_regions FAILED err[%x]\n", err
);
973 DBG_ERROR("call pci_set_master\n");
974 pci_set_master(pcidev
);
976 DBG_ERROR("call alloc_etherdev\n");
977 netdev
= alloc_etherdev(sizeof(struct adapter_t
));
980 goto err_out_exit_sxg_probe
;
982 DBG_ERROR("alloc_etherdev for slic netdev[%p]\n", netdev
);
984 SET_NETDEV_DEV(netdev
, &pcidev
->dev
);
986 pci_set_drvdata(pcidev
, netdev
);
987 adapter
= netdev_priv(netdev
);
988 if (revision_id
== 1) {
989 adapter
->asictype
= SAHARA_REV_A
;
990 } else if (revision_id
== 2) {
991 adapter
->asictype
= SAHARA_REV_B
;
994 DBG_ERROR("%s Unexpected revision ID %x\n", __FUNCTION__
, revision_id
);
995 goto err_out_exit_sxg_probe
;
997 adapter
->netdev
= netdev
;
998 adapter
->pcidev
= pcidev
;
1000 mmio_start
= pci_resource_start(pcidev
, 0);
1001 mmio_len
= pci_resource_len(pcidev
, 0);
1003 DBG_ERROR("sxg: call ioremap(mmio_start[%lx], mmio_len[%lx])\n",
1004 mmio_start
, mmio_len
);
1006 memmapped_ioaddr
= ioremap(mmio_start
, mmio_len
);
1007 DBG_ERROR("sxg: %s MEMMAPPED_IOADDR [%p]\n", __func__
,
1009 if (!memmapped_ioaddr
) {
1010 DBG_ERROR("%s cannot remap MMIO region %lx @ %lx\n",
1011 __func__
, mmio_len
, mmio_start
);
1012 goto err_out_free_mmio_region_0
;
1015 DBG_ERROR("sxg: %s found Alacritech SXG PCI, MMIO at %p, start[%lx] \
1016 len[%lx], IRQ %d.\n", __func__
, memmapped_ioaddr
, mmio_start
,
1017 mmio_len
, pcidev
->irq
);
1019 adapter
->HwRegs
= (void *)memmapped_ioaddr
;
1020 adapter
->base_addr
= memmapped_ioaddr
;
1022 mmio_start
= pci_resource_start(pcidev
, 2);
1023 mmio_len
= pci_resource_len(pcidev
, 2);
1025 DBG_ERROR("sxg: call ioremap(mmio_start[%lx], mmio_len[%lx])\n",
1026 mmio_start
, mmio_len
);
1028 memmapped_ioaddr
= ioremap(mmio_start
, mmio_len
);
1029 DBG_ERROR("sxg: %s MEMMAPPED_IOADDR [%p]\n", __func__
,
1031 if (!memmapped_ioaddr
) {
1032 DBG_ERROR("%s cannot remap MMIO region %lx @ %lx\n",
1033 __func__
, mmio_len
, mmio_start
);
1034 goto err_out_free_mmio_region_2
;
1037 DBG_ERROR("sxg: %s found Alacritech SXG PCI, MMIO at %p, "
1038 "start[%lx] len[%lx], IRQ %d.\n", __func__
,
1039 memmapped_ioaddr
, mmio_start
, mmio_len
, pcidev
->irq
);
1041 adapter
->UcodeRegs
= (void *)memmapped_ioaddr
;
1043 adapter
->State
= SXG_STATE_INITIALIZING
;
1045 * Maintain a list of all adapters anchored by
1046 * the global SxgDriver structure.
1048 adapter
->Next
= SxgDriver
.Adapters
;
1049 SxgDriver
.Adapters
= adapter
;
1050 adapter
->AdapterID
= ++SxgDriver
.AdapterID
;
1052 /* Initialize CRC table used to determine multicast hash */
1053 sxg_mcast_init_crc32();
1055 adapter
->JumboEnabled
= FALSE
;
1056 adapter
->RssEnabled
= FALSE
;
1057 if (adapter
->JumboEnabled
) {
1058 adapter
->FrameSize
= JUMBOMAXFRAME
;
1059 adapter
->ReceiveBufferSize
= SXG_RCV_JUMBO_BUFFER_SIZE
;
1061 adapter
->FrameSize
= ETHERMAXFRAME
;
1062 adapter
->ReceiveBufferSize
= SXG_RCV_DATA_BUFFER_SIZE
;
1066 * status = SXG_READ_EEPROM(adapter);
1068 * goto sxg_init_bad;
1072 DBG_ERROR("sxg: %s ENTER sxg_config_pci\n", __func__
);
1073 sxg_config_pci(pcidev
);
1074 DBG_ERROR("sxg: %s EXIT sxg_config_pci\n", __func__
);
1076 DBG_ERROR("sxg: %s ENTER sxg_init_driver\n", __func__
);
1078 DBG_ERROR("sxg: %s EXIT sxg_init_driver\n", __func__
);
1080 adapter
->vendid
= pci_tbl_entry
->vendor
;
1081 adapter
->devid
= pci_tbl_entry
->device
;
1082 adapter
->subsysid
= pci_tbl_entry
->subdevice
;
1083 adapter
->slotnumber
= ((pcidev
->devfn
>> 3) & 0x1F);
1084 adapter
->functionnumber
= (pcidev
->devfn
& 0x7);
1085 adapter
->memorylength
= pci_resource_len(pcidev
, 0);
1086 adapter
->irq
= pcidev
->irq
;
1087 adapter
->next_netdevice
= head_netdevice
;
1088 head_netdevice
= netdev
;
1089 adapter
->port
= 0; /*adapter->functionnumber; */
1091 /* Allocate memory and other resources */
1092 DBG_ERROR("sxg: %s ENTER sxg_allocate_resources\n", __func__
);
1093 status
= sxg_allocate_resources(adapter
);
1094 DBG_ERROR("sxg: %s EXIT sxg_allocate_resources status %x\n",
1096 if (status
!= STATUS_SUCCESS
) {
1100 DBG_ERROR("sxg: %s ENTER sxg_download_microcode\n", __func__
);
1101 if (sxg_download_microcode(adapter
, SXG_UCODE_SYSTEM
)) {
1102 DBG_ERROR("sxg: %s ENTER sxg_adapter_set_hwaddr\n",
1104 sxg_read_config(adapter
);
1105 status
= sxg_adapter_set_hwaddr(adapter
);
1107 adapter
->state
= ADAPT_FAIL
;
1108 adapter
->linkstate
= LINK_DOWN
;
1109 DBG_ERROR("sxg_download_microcode FAILED status[%x]\n", status
);
1112 netdev
->base_addr
= (unsigned long)adapter
->base_addr
;
1113 netdev
->irq
= adapter
->irq
;
1114 netdev
->netdev_ops
= &sxg_netdev_ops
;
1115 SET_ETHTOOL_OPS(netdev
, &sxg_nic_ethtool_ops
);
1116 netdev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
;
1117 err
= sxg_set_interrupt_capability(adapter
);
1118 if (err
!= STATUS_SUCCESS
)
1119 DBG_ERROR("Cannot enable MSI-X capability\n");
1121 strcpy(netdev
->name
, "eth%d");
1122 /* strcpy(netdev->name, pci_name(pcidev)); */
1123 if ((err
= register_netdev(netdev
))) {
1124 DBG_ERROR("Cannot register net device, aborting. %s\n",
1129 netif_napi_add(netdev
, &adapter
->napi
,
1130 sxg_poll
, SXG_NETDEV_WEIGHT
);
1131 netdev
->watchdog_timeo
= 2 * HZ
;
1132 init_timer(&adapter
->watchdog_timer
);
1133 adapter
->watchdog_timer
.function
= &sxg_watchdog
;
1134 adapter
->watchdog_timer
.data
= (unsigned long) adapter
;
1135 INIT_WORK(&adapter
->update_link_status
, sxg_update_link_status
);
1138 ("sxg: %s addr 0x%lx, irq %d, MAC addr \
1139 %02X:%02X:%02X:%02X:%02X:%02X\n",
1140 netdev
->name
, netdev
->base_addr
, pcidev
->irq
, netdev
->dev_addr
[0],
1141 netdev
->dev_addr
[1], netdev
->dev_addr
[2], netdev
->dev_addr
[3],
1142 netdev
->dev_addr
[4], netdev
->dev_addr
[5]);
1145 ASSERT(status
== FALSE
);
1146 /* sxg_free_adapter(adapter); */
1148 DBG_ERROR("sxg: %s EXIT status[%x] jiffies[%lx] cpu %d\n", __func__
,
1149 status
, jiffies
, smp_processor_id());
1153 sxg_free_resources(adapter
);
1155 err_out_free_mmio_region_2
:
1157 mmio_start
= pci_resource_start(pcidev
, 2);
1158 mmio_len
= pci_resource_len(pcidev
, 2);
1159 release_mem_region(mmio_start
, mmio_len
);
1161 err_out_free_mmio_region_0
:
1163 mmio_start
= pci_resource_start(pcidev
, 0);
1164 mmio_len
= pci_resource_len(pcidev
, 0);
1166 release_mem_region(mmio_start
, mmio_len
);
1168 err_out_exit_sxg_probe
:
1170 DBG_ERROR("%s EXIT jiffies[%lx] cpu %d\n", __func__
, jiffies
,
1171 smp_processor_id());
1173 pci_disable_device(pcidev
);
1174 DBG_ERROR("sxg: %s deallocate device\n", __FUNCTION__
);
1176 printk("Exit %s, Sxg driver loading failed..\n", __FUNCTION__
);
1182 * LINE BASE Interrupt routines..
1184 * sxg_disable_interrupt
1186 * DisableInterrupt Handler
1190 * adapter: Our adapter structure
1195 static void sxg_disable_interrupt(struct adapter_t
*adapter
)
1197 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "DisIntr",
1198 adapter
, adapter
->InterruptsEnabled
, 0, 0);
1199 /* For now, RSS is disabled with line based interrupts */
1200 ASSERT(adapter
->RssEnabled
== FALSE
);
1201 /* Turn off interrupts by writing to the icr register. */
1202 WRITE_REG(adapter
->UcodeRegs
[0].Icr
, SXG_ICR(0, SXG_ICR_DISABLE
), TRUE
);
1204 adapter
->InterruptsEnabled
= 0;
1206 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "XDisIntr",
1207 adapter
, adapter
->InterruptsEnabled
, 0, 0);
1211 * sxg_enable_interrupt
1213 * EnableInterrupt Handler
1217 * adapter: Our adapter structure
1222 static void sxg_enable_interrupt(struct adapter_t
*adapter
)
1224 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "EnIntr",
1225 adapter
, adapter
->InterruptsEnabled
, 0, 0);
1226 /* For now, RSS is disabled with line based interrupts */
1227 ASSERT(adapter
->RssEnabled
== FALSE
);
1228 /* Turn on interrupts by writing to the icr register. */
1229 WRITE_REG(adapter
->UcodeRegs
[0].Icr
, SXG_ICR(0, SXG_ICR_ENABLE
), TRUE
);
1231 adapter
->InterruptsEnabled
= 1;
1233 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "XEnIntr",
1238 * sxg_isr - Process an line-based interrupt
1241 * Context - Our adapter structure
1242 * QueueDefault - Output parameter to queue to default CPU
1243 * TargetCpus - Output bitmap to schedule DPC's
1245 * Return Value: TRUE if our interrupt
1247 static irqreturn_t
sxg_isr(int irq
, void *dev_id
)
1249 struct net_device
*dev
= (struct net_device
*) dev_id
;
1250 struct adapter_t
*adapter
= (struct adapter_t
*) netdev_priv(dev
);
1252 if(adapter
->state
!= ADAPT_UP
)
1254 adapter
->Stats
.NumInts
++;
1255 if (adapter
->Isr
[0] == 0) {
1257 * The SLIC driver used to experience a number of spurious
1258 * interrupts due to the delay associated with the masking of
1259 * the interrupt (we'd bounce back in here). If we see that
1260 * again with Sahara,add a READ_REG of the Icr register after
1261 * the WRITE_REG below.
1263 adapter
->Stats
.FalseInts
++;
1267 * Move the Isr contents and clear the value in
1268 * shared memory, and mask interrupts
1270 /* ASSERT(adapter->IsrDpcsPending == 0); */
1271 #if XXXTODO /* RSS Stuff */
1273 * If RSS is enabled and the ISR specifies SXG_ISR_EVENT, then
1274 * schedule DPC's based on event queues.
1276 if (adapter
->RssEnabled
&& (adapter
->IsrCopy
[0] & SXG_ISR_EVENT
)) {
1278 i
< adapter
->RssSystemInfo
->ProcessorInfo
.RssCpuCount
;
1280 struct sxg_event_ring
*EventRing
=
1281 &adapter
->EventRings
[i
];
1282 struct sxg_event
*Event
=
1283 &EventRing
->Ring
[adapter
->NextEvent
[i
]];
1285 adapter
->RssSystemInfo
->RssIdToCpu
[i
];
1286 if (Event
->Status
& EVENT_STATUS_VALID
) {
1287 adapter
->IsrDpcsPending
++;
1288 CpuMask
|= (1 << Cpu
);
1293 * Now, either schedule the CPUs specified by the CpuMask,
1297 *QueueDefault
= FALSE
;
1299 adapter
->IsrDpcsPending
= 1;
1300 *QueueDefault
= TRUE
;
1302 *TargetCpus
= CpuMask
;
1304 sxg_interrupt(adapter
);
1309 static void sxg_interrupt(struct adapter_t
*adapter
)
1311 WRITE_REG(adapter
->UcodeRegs
[0].Icr
, SXG_ICR(0, SXG_ICR_MASK
), TRUE
);
1313 if (napi_schedule_prep(&adapter
->napi
)) {
1314 __napi_schedule(&adapter
->napi
);
1318 static void sxg_handle_interrupt(struct adapter_t
*adapter
, int *work_done
,
1321 /* unsigned char RssId = 0; */
1323 int sxg_napi_continue
= 1;
1324 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "HndlIntr",
1325 adapter
, adapter
->IsrCopy
[0], 0, 0);
1326 /* For now, RSS is disabled with line based interrupts */
1327 ASSERT(adapter
->RssEnabled
== FALSE
);
1329 adapter
->IsrCopy
[0] = adapter
->Isr
[0];
1330 adapter
->Isr
[0] = 0;
1332 /* Always process the event queue. */
1333 while (sxg_napi_continue
)
1335 sxg_process_event_queue(adapter
,
1336 (adapter
->RssEnabled
? /*RssId */ 0 : 0),
1337 &sxg_napi_continue
, work_done
, budget
);
1340 #if XXXTODO /* RSS stuff */
1341 if (--adapter
->IsrDpcsPending
) {
1343 ASSERT(adapter
->RssEnabled
);
1344 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "DPCsPend",
1349 /* Last (or only) DPC processes the ISR and clears the interrupt. */
1350 NewIsr
= sxg_process_isr(adapter
, 0);
1351 /* Reenable interrupts */
1352 adapter
->IsrCopy
[0] = 0;
1353 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "ClearIsr",
1354 adapter
, NewIsr
, 0, 0);
1356 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "XHndlInt",
1359 static int sxg_poll(struct napi_struct
*napi
, int budget
)
1361 struct adapter_t
*adapter
= container_of(napi
, struct adapter_t
, napi
);
1364 sxg_handle_interrupt(adapter
, &work_done
, budget
);
1366 if (work_done
< budget
) {
1367 napi_complete(napi
);
1368 WRITE_REG(adapter
->UcodeRegs
[0].Isr
, 0, TRUE
);
1374 * sxg_process_isr - Process an interrupt. Called from the line-based and
1375 * message based interrupt DPC routines
1378 * adapter - Our adapter structure
1379 * Queue - The ISR that needs processing
1384 static int sxg_process_isr(struct adapter_t
*adapter
, u32 MessageId
)
1386 u32 Isr
= adapter
->IsrCopy
[MessageId
];
1389 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "ProcIsr",
1390 adapter
, Isr
, 0, 0);
1393 if (Isr
& SXG_ISR_ERR
) {
1394 if (Isr
& SXG_ISR_PDQF
) {
1395 adapter
->Stats
.PdqFull
++;
1396 DBG_ERROR("%s: SXG_ISR_ERR PDQF!!\n", __func__
);
1398 /* No host buffer */
1399 if (Isr
& SXG_ISR_RMISS
) {
1401 * There is a bunch of code in the SLIC driver which
1402 * attempts to process more receive events per DPC
1403 * if we start to fall behind. We'll probablyd
1404 * need to do something similar here, but hold
1405 * off for now. I don't want to make the code more
1406 * complicated than strictly needed.
1408 adapter
->stats
.rx_missed_errors
++;
1409 if (adapter
->stats
.rx_missed_errors
< 5) {
1410 DBG_ERROR("%s: SXG_ISR_ERR RMISS!!\n",
1415 if (Isr
& SXG_ISR_DEAD
) {
1417 * Set aside the crash info and set the adapter state
1420 adapter
->CrashCpu
= (unsigned char)
1421 ((Isr
& SXG_ISR_CPU
) >> SXG_ISR_CPU_SHIFT
);
1422 adapter
->CrashLocation
= (ushort
) (Isr
& SXG_ISR_CRASH
);
1423 adapter
->Dead
= TRUE
;
1424 DBG_ERROR("%s: ISR_DEAD %x, CPU: %d\n", __func__
,
1425 adapter
->CrashLocation
, adapter
->CrashCpu
);
1427 /* Event ring full */
1428 if (Isr
& SXG_ISR_ERFULL
) {
1430 * Same issue as RMISS, really. This means the
1431 * host is falling behind the card. Need to increase
1432 * event ring size, process more events per interrupt,
1433 * and/or reduce/remove interrupt aggregation.
1435 adapter
->Stats
.EventRingFull
++;
1436 DBG_ERROR("%s: SXG_ISR_ERR EVENT RING FULL!!\n",
1439 /* Transmit drop - no DRAM buffers or XMT error */
1440 if (Isr
& SXG_ISR_XDROP
) {
1441 DBG_ERROR("%s: SXG_ISR_ERR XDROP!!\n", __func__
);
1444 /* Slowpath send completions */
1445 if (Isr
& SXG_ISR_SPSEND
) {
1446 sxg_complete_slow_send(adapter
);
1449 if (Isr
& SXG_ISR_UPC
) {
1450 /* Maybe change when debug is added.. */
1451 // ASSERT(adapter->DumpCmdRunning);
1452 adapter
->DumpCmdRunning
= FALSE
;
1455 if (Isr
& SXG_ISR_LINK
) {
1456 if (adapter
->state
!= ADAPT_DOWN
) {
1457 adapter
->link_status_changed
= 1;
1458 schedule_work(&adapter
->update_link_status
);
1461 /* Debug - breakpoint hit */
1462 if (Isr
& SXG_ISR_BREAK
) {
1464 * At the moment AGDB isn't written to support interactive
1465 * debug sessions. When it is, this interrupt will be used to
1466 * signal AGDB that it has hit a breakpoint. For now, ASSERT.
1470 /* Heartbeat response */
1471 if (Isr
& SXG_ISR_PING
) {
1472 adapter
->PingOutstanding
= FALSE
;
1474 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "XProcIsr",
1475 adapter
, Isr
, NewIsr
, 0);
1481 * sxg_rcv_checksum - Set the checksum for received packet
1484 * @adapter - Adapter structure on which packet is received
1485 * @skb - Packet which is receieved
1486 * @Event - Event read from hardware
1489 void sxg_rcv_checksum(struct adapter_t
*adapter
, struct sk_buff
*skb
,
1490 struct sxg_event
*Event
)
1492 skb
->ip_summed
= CHECKSUM_NONE
;
1493 if (likely(adapter
->flags
& SXG_RCV_IP_CSUM_ENABLED
)) {
1494 if (likely(adapter
->flags
& SXG_RCV_TCP_CSUM_ENABLED
)
1495 && (Event
->Status
& EVENT_STATUS_TCPIP
)) {
1496 if(!(Event
->Status
& EVENT_STATUS_TCPBAD
))
1497 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1498 if(!(Event
->Status
& EVENT_STATUS_IPBAD
))
1499 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1500 } else if(Event
->Status
& EVENT_STATUS_IPONLY
) {
1501 if(!(Event
->Status
& EVENT_STATUS_IPBAD
))
1502 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1508 * sxg_process_event_queue - Process our event queue
1511 * - adapter - Adapter structure
1512 * - RssId - The event queue requiring processing
1517 static u32
sxg_process_event_queue(struct adapter_t
*adapter
, u32 RssId
,
1518 int *sxg_napi_continue
, int *work_done
, int budget
)
1520 struct sxg_event_ring
*EventRing
= &adapter
->EventRings
[RssId
];
1521 struct sxg_event
*Event
= &EventRing
->Ring
[adapter
->NextEvent
[RssId
]];
1522 u32 EventsProcessed
= 0, Batches
= 0;
1523 struct sk_buff
*skb
;
1524 #ifdef LINUX_HANDLES_RCV_INDICATION_LISTS
1525 struct sk_buff
*prev_skb
= NULL
;
1526 struct sk_buff
*IndicationList
[SXG_RCV_ARRAYSIZE
];
1528 struct sxg_rcv_data_buffer_hdr
*RcvDataBufferHdr
;
1530 u32 ReturnStatus
= 0;
1531 int sxg_rcv_data_buffers
= SXG_RCV_DATA_BUFFERS
;
1533 ASSERT((adapter
->State
== SXG_STATE_RUNNING
) ||
1534 (adapter
->State
== SXG_STATE_PAUSING
) ||
1535 (adapter
->State
== SXG_STATE_PAUSED
) ||
1536 (adapter
->State
== SXG_STATE_HALTING
));
1538 * We may still have unprocessed events on the queue if
1539 * the card crashed. Don't process them.
1541 if (adapter
->Dead
) {
1545 * In theory there should only be a single processor that
1546 * accesses this queue, and only at interrupt-DPC time. So/
1547 * we shouldn't need a lock for any of this.
1549 while (Event
->Status
& EVENT_STATUS_VALID
) {
1550 (*sxg_napi_continue
) = 1;
1551 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "Event",
1552 Event
, Event
->Code
, Event
->Status
,
1553 adapter
->NextEvent
);
1554 switch (Event
->Code
) {
1555 case EVENT_CODE_BUFFERS
:
1556 /* struct sxg_ring_info Head & Tail == unsigned char */
1557 ASSERT(!(Event
->CommandIndex
& 0xFF00));
1558 sxg_complete_descriptor_blocks(adapter
,
1559 Event
->CommandIndex
);
1561 case EVENT_CODE_SLOWRCV
:
1563 --adapter
->RcvBuffersOnCard
;
1564 if ((skb
= sxg_slow_receive(adapter
, Event
))) {
1566 #ifdef LINUX_HANDLES_RCV_INDICATION_LISTS
1567 /* Add it to our indication list */
1568 SXG_ADD_RCV_PACKET(adapter
, skb
, prev_skb
,
1569 IndicationList
, num_skbs
);
1571 * Linux, we just pass up each skb to the
1572 * protocol above at this point, there is no
1573 * capability of an indication list.
1576 /* CHECK skb_pull(skb, INIC_RCVBUF_HEADSIZE); */
1577 /* (rcvbuf->length & IRHDDR_FLEN_MSK); */
1578 rx_bytes
= Event
->Length
;
1579 adapter
->stats
.rx_packets
++;
1580 adapter
->stats
.rx_bytes
+= rx_bytes
;
1581 sxg_rcv_checksum(adapter
, skb
, Event
);
1582 skb
->dev
= adapter
->netdev
;
1583 netif_receive_skb(skb
);
1588 DBG_ERROR("%s: ERROR Invalid EventCode %d\n",
1589 __func__
, Event
->Code
);
1593 * See if we need to restock card receive buffers.
1594 * There are two things to note here:
1595 * First - This test is not SMP safe. The
1596 * adapter->BuffersOnCard field is protected via atomic
1597 * interlocked calls, but we do not protect it with respect
1598 * to these tests. The only way to do that is with a lock,
1599 * and I don't want to grab a lock every time we adjust the
1600 * BuffersOnCard count. Instead, we allow the buffer
1601 * replenishment to be off once in a while. The worst that
1602 * can happen is the card is given on more-or-less descriptor
1603 * block than the arbitrary value we've chosen. No big deal
1604 * In short DO NOT ADD A LOCK HERE, OR WHERE RcvBuffersOnCard
1606 * Second - We expect this test to rarely
1607 * evaluate to true. We attempt to refill descriptor blocks
1608 * as they are returned to us (sxg_complete_descriptor_blocks)
1609 * so The only time this should evaluate to true is when
1610 * sxg_complete_descriptor_blocks failed to allocate
1613 if (adapter
->JumboEnabled
)
1614 sxg_rcv_data_buffers
= SXG_JUMBO_RCV_DATA_BUFFERS
;
1616 if (adapter
->RcvBuffersOnCard
< sxg_rcv_data_buffers
) {
1617 sxg_stock_rcv_buffers(adapter
);
1620 * It's more efficient to just set this to zero.
1621 * But clearing the top bit saves potential debug info...
1623 Event
->Status
&= ~EVENT_STATUS_VALID
;
1624 /* Advance to the next event */
1625 SXG_ADVANCE_INDEX(adapter
->NextEvent
[RssId
], EVENT_RING_SIZE
);
1626 Event
= &EventRing
->Ring
[adapter
->NextEvent
[RssId
]];
1628 if (EventsProcessed
== EVENT_RING_BATCH
) {
1629 /* Release a batch of events back to the card */
1630 WRITE_REG(adapter
->UcodeRegs
[RssId
].EventRelease
,
1631 EVENT_RING_BATCH
, FALSE
);
1632 EventsProcessed
= 0;
1634 * If we've processed our batch limit, break out of the
1635 * loop and return SXG_ISR_EVENT to arrange for us to
1638 if (Batches
++ == EVENT_BATCH_LIMIT
) {
1639 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
,
1640 TRACE_NOISY
, "EvtLimit", Batches
,
1641 adapter
->NextEvent
, 0, 0);
1642 ReturnStatus
= SXG_ISR_EVENT
;
1646 if (*work_done
>= budget
) {
1647 WRITE_REG(adapter
->UcodeRegs
[RssId
].EventRelease
,
1648 EventsProcessed
, FALSE
);
1649 EventsProcessed
= 0;
1650 (*sxg_napi_continue
) = 0;
1654 if (!(Event
->Status
& EVENT_STATUS_VALID
))
1655 (*sxg_napi_continue
) = 0;
1657 #ifdef LINUX_HANDLES_RCV_INDICATION_LISTS
1658 /* Indicate any received dumb-nic frames */
1659 SXG_INDICATE_PACKETS(adapter
, IndicationList
, num_skbs
);
1661 /* Release events back to the card. */
1662 if (EventsProcessed
) {
1663 WRITE_REG(adapter
->UcodeRegs
[RssId
].EventRelease
,
1664 EventsProcessed
, FALSE
);
1666 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "XPrcEvnt",
1667 Batches
, EventsProcessed
, adapter
->NextEvent
, num_skbs
);
1669 return (ReturnStatus
);
1673 * sxg_complete_slow_send - Complete slowpath or dumb-nic sends
1676 * adapter - A pointer to our adapter structure
1680 static void sxg_complete_slow_send(struct adapter_t
*adapter
)
1682 struct sxg_xmt_ring
*XmtRing
= &adapter
->XmtRings
[0];
1683 struct sxg_ring_info
*XmtRingInfo
= &adapter
->XmtRingZeroInfo
;
1685 struct sxg_cmd
*XmtCmd
;
1686 unsigned long flags
= 0;
1687 unsigned long sgl_flags
= 0;
1688 unsigned int processed_count
= 0;
1691 * NOTE - This lock is dropped and regrabbed in this loop.
1692 * This means two different processors can both be running/
1693 * through this loop. Be *very* careful.
1695 spin_lock_irqsave(&adapter
->XmtZeroLock
, flags
);
1697 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "CmpSnds",
1698 adapter
, XmtRingInfo
->Head
, XmtRingInfo
->Tail
, 0);
1700 while ((XmtRingInfo
->Tail
!= *adapter
->XmtRingZeroIndex
)
1701 && processed_count
++ < SXG_COMPLETE_SLOW_SEND_LIMIT
) {
1703 * Locate the current Cmd (ring descriptor entry), and
1704 * associated SGL, and advance the tail
1706 SXG_RETURN_CMD(XmtRing
, XmtRingInfo
, XmtCmd
, ContextType
);
1707 ASSERT(ContextType
);
1708 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "CmpSnd",
1709 XmtRingInfo
->Head
, XmtRingInfo
->Tail
, XmtCmd
, 0);
1710 /* Clear the SGL field. */
1713 switch (*ContextType
) {
1716 struct sk_buff
*skb
;
1717 struct sxg_scatter_gather
*SxgSgl
=
1718 (struct sxg_scatter_gather
*)ContextType
;
1719 dma64_addr_t FirstSgeAddress
;
1722 /* Dumb-nic send. Command context is the dumb-nic SGL */
1723 skb
= (struct sk_buff
*)ContextType
;
1724 skb
= SxgSgl
->DumbPacket
;
1725 FirstSgeAddress
= XmtCmd
->Buffer
.FirstSgeAddress
;
1726 FirstSgeLength
= XmtCmd
->Buffer
.FirstSgeLength
;
1727 /* Complete the send */
1728 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
,
1729 TRACE_IMPORTANT
, "DmSndCmp", skb
, 0,
1731 ASSERT(adapter
->Stats
.XmtQLen
);
1733 * Now drop the lock and complete the send
1734 * back to Microsoft. We need to drop the lock
1735 * because Microsoft can come back with a
1736 * chimney send, which results in a double trip
1739 spin_unlock_irqrestore(
1740 &adapter
->XmtZeroLock
, flags
);
1742 SxgSgl
->DumbPacket
= NULL
;
1743 SXG_COMPLETE_DUMB_SEND(adapter
, skb
,
1746 SXG_FREE_SGL_BUFFER(adapter
, SxgSgl
, NULL
);
1747 /* and reacquire.. */
1748 spin_lock_irqsave(&adapter
->XmtZeroLock
, flags
);
1755 spin_unlock_irqrestore(&adapter
->XmtZeroLock
, flags
);
1756 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "CmpSnd",
1757 adapter
, XmtRingInfo
->Head
, XmtRingInfo
->Tail
, 0);
1764 * adapter - A pointer to our adapter structure
1765 * Event - Receive event
1769 static struct sk_buff
*sxg_slow_receive(struct adapter_t
*adapter
,
1770 struct sxg_event
*Event
)
1772 u32 BufferSize
= adapter
->ReceiveBufferSize
;
1773 struct sxg_rcv_data_buffer_hdr
*RcvDataBufferHdr
;
1774 struct sk_buff
*Packet
;
1775 static int read_counter
= 0;
1777 RcvDataBufferHdr
= (struct sxg_rcv_data_buffer_hdr
*) Event
->HostHandle
;
1778 if(read_counter
++ & 0x100)
1780 sxg_collect_statistics(adapter
);
1783 ASSERT(RcvDataBufferHdr
);
1784 ASSERT(RcvDataBufferHdr
->State
== SXG_BUFFER_ONCARD
);
1785 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_IMPORTANT
, "SlowRcv", Event
,
1786 RcvDataBufferHdr
, RcvDataBufferHdr
->State
,
1787 /*RcvDataBufferHdr->VirtualAddress*/ 0);
1788 /* Drop rcv frames in non-running state */
1789 switch (adapter
->State
) {
1790 case SXG_STATE_RUNNING
:
1792 case SXG_STATE_PAUSING
:
1793 case SXG_STATE_PAUSED
:
1794 case SXG_STATE_HALTING
:
1802 * memcpy(SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr),
1803 * RcvDataBufferHdr->VirtualAddress, Event->Length);
1806 /* Change buffer state to UPSTREAM */
1807 RcvDataBufferHdr
->State
= SXG_BUFFER_UPSTREAM
;
1808 if (Event
->Status
& EVENT_STATUS_RCVERR
) {
1809 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "RcvError",
1810 Event
, Event
->Status
, Event
->HostHandle
, 0);
1811 sxg_process_rcv_error(adapter
, *(u32
*)
1812 SXG_RECEIVE_DATA_LOCATION
1813 (RcvDataBufferHdr
));
1816 #if XXXTODO /* VLAN stuff */
1817 /* If there's a VLAN tag, extract it and validate it */
1818 if (((struct ether_header
*)
1819 (SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr
)))->EtherType
1820 == ETHERTYPE_VLAN
) {
1821 if (SxgExtractVlanHeader(adapter
, RcvDataBufferHdr
, Event
) !=
1823 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
,
1825 SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr
),
1831 /* Dumb-nic frame. See if it passes our mac filter and update stats */
1833 if (!sxg_mac_filter(adapter
,
1834 (struct ether_header
*)(SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr
)),
1836 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "RcvFiltr",
1837 Event
, SXG_RECEIVE_DATA_LOCATION(RcvDataBufferHdr
),
1842 Packet
= RcvDataBufferHdr
->SxgDumbRcvPacket
;
1843 SXG_ADJUST_RCV_PACKET(Packet
, RcvDataBufferHdr
, Event
);
1844 Packet
->protocol
= eth_type_trans(Packet
, adapter
->netdev
);
1846 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_IMPORTANT
, "DumbRcv",
1847 RcvDataBufferHdr
, Packet
, Event
->Length
, 0);
1848 /* Lastly adjust the receive packet length. */
1849 RcvDataBufferHdr
->SxgDumbRcvPacket
= NULL
;
1850 RcvDataBufferHdr
->PhysicalAddress
= (dma_addr_t
)NULL
;
1851 SXG_ALLOCATE_RCV_PACKET(adapter
, RcvDataBufferHdr
, BufferSize
);
1852 if (RcvDataBufferHdr
->skb
)
1854 spin_lock(&adapter
->RcvQLock
);
1855 SXG_FREE_RCV_DATA_BUFFER(adapter
, RcvDataBufferHdr
);
1856 // adapter->RcvBuffersOnCard ++;
1857 spin_unlock(&adapter
->RcvQLock
);
1862 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "DropRcv",
1863 RcvDataBufferHdr
, Event
->Length
, 0, 0);
1864 adapter
->stats
.rx_dropped
++;
1865 // adapter->Stats.RcvDiscards++;
1866 spin_lock(&adapter
->RcvQLock
);
1867 SXG_FREE_RCV_DATA_BUFFER(adapter
, RcvDataBufferHdr
);
1868 spin_unlock(&adapter
->RcvQLock
);
1873 * sxg_process_rcv_error - process receive error and update
1877 * adapter - Adapter structure
1878 * ErrorStatus - 4-byte receive error status
1880 * Return Value : None
1882 static void sxg_process_rcv_error(struct adapter_t
*adapter
, u32 ErrorStatus
)
1886 adapter
->stats
.rx_errors
++;
1888 if (ErrorStatus
& SXG_RCV_STATUS_TRANSPORT_ERROR
) {
1889 Error
= ErrorStatus
& SXG_RCV_STATUS_TRANSPORT_MASK
;
1891 case SXG_RCV_STATUS_TRANSPORT_CSUM
:
1892 adapter
->Stats
.TransportCsum
++;
1894 case SXG_RCV_STATUS_TRANSPORT_UFLOW
:
1895 adapter
->Stats
.TransportUflow
++;
1897 case SXG_RCV_STATUS_TRANSPORT_HDRLEN
:
1898 adapter
->Stats
.TransportHdrLen
++;
1902 if (ErrorStatus
& SXG_RCV_STATUS_NETWORK_ERROR
) {
1903 Error
= ErrorStatus
& SXG_RCV_STATUS_NETWORK_MASK
;
1905 case SXG_RCV_STATUS_NETWORK_CSUM
:
1906 adapter
->Stats
.NetworkCsum
++;
1908 case SXG_RCV_STATUS_NETWORK_UFLOW
:
1909 adapter
->Stats
.NetworkUflow
++;
1911 case SXG_RCV_STATUS_NETWORK_HDRLEN
:
1912 adapter
->Stats
.NetworkHdrLen
++;
1916 if (ErrorStatus
& SXG_RCV_STATUS_PARITY
) {
1917 adapter
->Stats
.Parity
++;
1919 if (ErrorStatus
& SXG_RCV_STATUS_LINK_ERROR
) {
1920 Error
= ErrorStatus
& SXG_RCV_STATUS_LINK_MASK
;
1922 case SXG_RCV_STATUS_LINK_PARITY
:
1923 adapter
->Stats
.LinkParity
++;
1925 case SXG_RCV_STATUS_LINK_EARLY
:
1926 adapter
->Stats
.LinkEarly
++;
1928 case SXG_RCV_STATUS_LINK_BUFOFLOW
:
1929 adapter
->Stats
.LinkBufOflow
++;
1931 case SXG_RCV_STATUS_LINK_CODE
:
1932 adapter
->Stats
.LinkCode
++;
1934 case SXG_RCV_STATUS_LINK_DRIBBLE
:
1935 adapter
->Stats
.LinkDribble
++;
1937 case SXG_RCV_STATUS_LINK_CRC
:
1938 adapter
->Stats
.LinkCrc
++;
1940 case SXG_RCV_STATUS_LINK_OFLOW
:
1941 adapter
->Stats
.LinkOflow
++;
1943 case SXG_RCV_STATUS_LINK_UFLOW
:
1944 adapter
->Stats
.LinkUflow
++;
1954 * adapter - Adapter structure
1955 * pether - Ethernet header
1956 * length - Frame length
1958 * Return Value : TRUE if the frame is to be allowed
1960 static bool sxg_mac_filter(struct adapter_t
*adapter
,
1961 struct ether_header
*EtherHdr
, ushort length
)
1964 struct net_device
*dev
= adapter
->netdev
;
1966 if (SXG_MULTICAST_PACKET(EtherHdr
)) {
1967 if (SXG_BROADCAST_PACKET(EtherHdr
)) {
1969 if (adapter
->MacFilter
& MAC_BCAST
) {
1970 adapter
->Stats
.DumbRcvBcastPkts
++;
1971 adapter
->Stats
.DumbRcvBcastBytes
+= length
;
1976 if (adapter
->MacFilter
& MAC_ALLMCAST
) {
1977 adapter
->Stats
.DumbRcvMcastPkts
++;
1978 adapter
->Stats
.DumbRcvMcastBytes
+= length
;
1981 if (adapter
->MacFilter
& MAC_MCAST
) {
1982 struct dev_mc_list
*mclist
= dev
->mc_list
;
1984 ETHER_EQ_ADDR(mclist
->da_addr
,
1985 EtherHdr
->ether_dhost
,
1991 DumbRcvMcastBytes
+= length
;
1994 mclist
= mclist
->next
;
1998 } else if (adapter
->MacFilter
& MAC_DIRECTED
) {
2000 * Not broadcast or multicast. Must be directed at us or
2001 * the card is in promiscuous mode. Either way, consider it
2002 * ours if MAC_DIRECTED is set
2004 adapter
->Stats
.DumbRcvUcastPkts
++;
2005 adapter
->Stats
.DumbRcvUcastBytes
+= length
;
2008 if (adapter
->MacFilter
& MAC_PROMISC
) {
2009 /* Whatever it is, keep it. */
2015 static int sxg_register_interrupt(struct adapter_t
*adapter
)
2017 if (!adapter
->intrregistered
) {
2021 ("sxg: %s AllocAdaptRsrcs adapter[%p] dev->irq[%x] %x\n",
2022 __func__
, adapter
, adapter
->netdev
->irq
, NR_IRQS
);
2024 spin_unlock_irqrestore(&sxg_global
.driver_lock
,
2027 retval
= request_irq(adapter
->netdev
->irq
,
2030 adapter
->netdev
->name
, adapter
->netdev
);
2032 spin_lock_irqsave(&sxg_global
.driver_lock
, sxg_global
.flags
);
2035 DBG_ERROR("sxg: request_irq (%s) FAILED [%x]\n",
2036 adapter
->netdev
->name
, retval
);
2039 adapter
->intrregistered
= 1;
2040 adapter
->IntRegistered
= TRUE
;
2041 /* Disable RSS with line-based interrupts */
2042 adapter
->RssEnabled
= FALSE
;
2043 DBG_ERROR("sxg: %s AllocAdaptRsrcs adapter[%p] dev->irq[%x]\n",
2044 __func__
, adapter
, adapter
->netdev
->irq
);
2046 return (STATUS_SUCCESS
);
2049 static void sxg_deregister_interrupt(struct adapter_t
*adapter
)
2051 DBG_ERROR("sxg: %s ENTER adapter[%p]\n", __func__
, adapter
);
2053 slic_init_cleanup(adapter
);
2055 memset(&adapter
->stats
, 0, sizeof(struct net_device_stats
));
2056 adapter
->error_interrupts
= 0;
2057 adapter
->rcv_interrupts
= 0;
2058 adapter
->xmit_interrupts
= 0;
2059 adapter
->linkevent_interrupts
= 0;
2060 adapter
->upr_interrupts
= 0;
2061 adapter
->num_isrs
= 0;
2062 adapter
->xmit_completes
= 0;
2063 adapter
->rcv_broadcasts
= 0;
2064 adapter
->rcv_multicasts
= 0;
2065 adapter
->rcv_unicasts
= 0;
2066 DBG_ERROR("sxg: %s EXIT\n", __func__
);
2072 * Perform initialization of our slic interface.
2075 static int sxg_if_init(struct adapter_t
*adapter
)
2077 struct net_device
*dev
= adapter
->netdev
;
2080 DBG_ERROR("sxg: %s (%s) ENTER states[%d:%d] flags[%x]\n",
2081 __func__
, adapter
->netdev
->name
,
2083 adapter
->linkstate
, dev
->flags
);
2085 /* adapter should be down at this point */
2086 if (adapter
->state
!= ADAPT_DOWN
) {
2087 DBG_ERROR("sxg_if_init adapter->state != ADAPT_DOWN\n");
2090 ASSERT(adapter
->linkstate
== LINK_DOWN
);
2092 adapter
->devflags_prev
= dev
->flags
;
2093 adapter
->MacFilter
= MAC_DIRECTED
;
2095 DBG_ERROR("sxg: %s (%s) Set MAC options: ", __func__
,
2096 adapter
->netdev
->name
);
2097 if (dev
->flags
& IFF_BROADCAST
) {
2098 adapter
->MacFilter
|= MAC_BCAST
;
2099 DBG_ERROR("BCAST ");
2101 if (dev
->flags
& IFF_PROMISC
) {
2102 adapter
->MacFilter
|= MAC_PROMISC
;
2103 DBG_ERROR("PROMISC ");
2105 if (dev
->flags
& IFF_ALLMULTI
) {
2106 adapter
->MacFilter
|= MAC_ALLMCAST
;
2107 DBG_ERROR("ALL_MCAST ");
2109 if (dev
->flags
& IFF_MULTICAST
) {
2110 adapter
->MacFilter
|= MAC_MCAST
;
2111 DBG_ERROR("MCAST ");
2115 status
= sxg_register_intr(adapter
);
2116 if (status
!= STATUS_SUCCESS
) {
2117 DBG_ERROR("sxg_if_init: sxg_register_intr FAILED %x\n",
2119 sxg_deregister_interrupt(adapter
);
2123 adapter
->state
= ADAPT_UP
;
2125 /* clear any pending events, then enable interrupts */
2126 DBG_ERROR("sxg: %s ENABLE interrupts(slic)\n", __func__
);
2128 return (STATUS_SUCCESS
);
2131 void sxg_set_interrupt_aggregation(struct adapter_t
*adapter
)
2134 * Top bit disables aggregation on xmt (SXG_AGG_XMT_DISABLE).
2135 * Make sure Max is less than 0x8000.
2137 adapter
->max_aggregation
= SXG_MAX_AGG_DEFAULT
;
2138 adapter
->min_aggregation
= SXG_MIN_AGG_DEFAULT
;
2139 WRITE_REG(adapter
->UcodeRegs
[0].Aggregation
,
2140 ((adapter
->max_aggregation
<< SXG_MAX_AGG_SHIFT
) |
2141 adapter
->min_aggregation
),
2145 static int sxg_entry_open(struct net_device
*dev
)
2147 struct adapter_t
*adapter
= (struct adapter_t
*) netdev_priv(dev
);
2150 int sxg_initial_rcv_data_buffers
= SXG_INITIAL_RCV_DATA_BUFFERS
;
2153 if (adapter
->JumboEnabled
== TRUE
) {
2154 sxg_initial_rcv_data_buffers
=
2155 SXG_INITIAL_JUMBO_RCV_DATA_BUFFERS
;
2156 SXG_INITIALIZE_RING(adapter
->RcvRingZeroInfo
,
2157 SXG_JUMBO_RCV_RING_SIZE
);
2161 * Allocate receive data buffers. We allocate a block of buffers and
2162 * a corresponding descriptor block at once. See sxghw.h:SXG_RCV_BLOCK
2165 for (i
= 0; i
< sxg_initial_rcv_data_buffers
;
2166 i
+= SXG_RCV_DESCRIPTORS_PER_BLOCK
)
2168 status
= sxg_allocate_buffer_memory(adapter
,
2169 SXG_RCV_BLOCK_SIZE(SXG_RCV_DATA_HDR_SIZE
),
2170 SXG_BUFFER_TYPE_RCV
);
2171 if (status
!= STATUS_SUCCESS
)
2175 * NBL resource allocation can fail in the 'AllocateComplete' routine,
2176 * which doesn't return status. Make sure we got the number of buffers
2180 if (adapter
->FreeRcvBufferCount
< sxg_initial_rcv_data_buffers
) {
2181 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "XAResF6",
2182 adapter
, adapter
->FreeRcvBufferCount
, SXG_MAX_ENTRIES
,
2184 return (STATUS_RESOURCES
);
2187 * The microcode expects it to be downloaded on every open.
2189 DBG_ERROR("sxg: %s ENTER sxg_download_microcode\n", __FUNCTION__
);
2190 if (sxg_download_microcode(adapter
, SXG_UCODE_SYSTEM
)) {
2191 DBG_ERROR("sxg: %s ENTER sxg_adapter_set_hwaddr\n",
2193 sxg_read_config(adapter
);
2195 adapter
->state
= ADAPT_FAIL
;
2196 adapter
->linkstate
= LINK_DOWN
;
2197 DBG_ERROR("sxg_download_microcode FAILED status[%x]\n",
2203 sxg_second_open(adapter
->netdev
);
2205 return STATUS_SUCCESS
;
2211 DBG_ERROR("sxg: %s adapter->activated[%d]\n", __func__
,
2212 adapter
->activated
);
2214 ("sxg: %s (%s): [jiffies[%lx] cpu %d] dev[%p] adapt[%p] port[%d]\n",
2215 __func__
, adapter
->netdev
->name
, jiffies
, smp_processor_id(),
2216 adapter
->netdev
, adapter
, adapter
->port
);
2218 netif_stop_queue(adapter
->netdev
);
2220 spin_lock_irqsave(&sxg_global
.driver_lock
, sxg_global
.flags
);
2221 if (!adapter
->activated
) {
2222 sxg_global
.num_sxg_ports_active
++;
2223 adapter
->activated
= 1;
2225 /* Initialize the adapter */
2226 DBG_ERROR("sxg: %s ENTER sxg_initialize_adapter\n", __func__
);
2227 status
= sxg_initialize_adapter(adapter
);
2228 DBG_ERROR("sxg: %s EXIT sxg_initialize_adapter status[%x]\n",
2231 if (status
== STATUS_SUCCESS
) {
2232 DBG_ERROR("sxg: %s ENTER sxg_if_init\n", __func__
);
2233 status
= sxg_if_init(adapter
);
2234 DBG_ERROR("sxg: %s EXIT sxg_if_init status[%x]\n", __func__
,
2238 if (status
!= STATUS_SUCCESS
) {
2239 if (adapter
->activated
) {
2240 sxg_global
.num_sxg_ports_active
--;
2241 adapter
->activated
= 0;
2243 spin_unlock_irqrestore(&sxg_global
.driver_lock
,
2247 DBG_ERROR("sxg: %s ENABLE ALL INTERRUPTS\n", __func__
);
2248 sxg_set_interrupt_aggregation(adapter
);
2249 napi_enable(&adapter
->napi
);
2251 /* Enable interrupts */
2252 SXG_ENABLE_ALL_INTERRUPTS(adapter
);
2254 DBG_ERROR("sxg: %s EXIT\n", __func__
);
2256 spin_unlock_irqrestore(&sxg_global
.driver_lock
, sxg_global
.flags
);
2257 mod_timer(&adapter
->watchdog_timer
, jiffies
);
2259 return STATUS_SUCCESS
;
2262 int sxg_second_open(struct net_device
* dev
)
2264 struct adapter_t
*adapter
= (struct adapter_t
*) netdev_priv(dev
);
2267 spin_lock_irqsave(&sxg_global
.driver_lock
, sxg_global
.flags
);
2268 netif_start_queue(adapter
->netdev
);
2269 adapter
->state
= ADAPT_UP
;
2270 adapter
->linkstate
= LINK_UP
;
2272 status
= sxg_initialize_adapter(adapter
);
2273 sxg_set_interrupt_aggregation(adapter
);
2274 napi_enable(&adapter
->napi
);
2275 /* Re-enable interrupts */
2276 SXG_ENABLE_ALL_INTERRUPTS(adapter
);
2278 sxg_register_intr(adapter
);
2279 spin_unlock_irqrestore(&sxg_global
.driver_lock
, sxg_global
.flags
);
2280 mod_timer(&adapter
->watchdog_timer
, jiffies
);
2281 return (STATUS_SUCCESS
);
2285 static void __devexit
sxg_entry_remove(struct pci_dev
*pcidev
)
2290 struct net_device
*dev
= pci_get_drvdata(pcidev
);
2291 struct adapter_t
*adapter
= (struct adapter_t
*) netdev_priv(dev
);
2293 flush_scheduled_work();
2295 /* Deallocate Resources */
2296 unregister_netdev(dev
);
2297 sxg_reset_interrupt_capability(adapter
);
2298 sxg_free_resources(adapter
);
2302 mmio_start
= pci_resource_start(pcidev
, 0);
2303 mmio_len
= pci_resource_len(pcidev
, 0);
2305 DBG_ERROR("sxg: %s rel_region(0) start[%x] len[%x]\n", __FUNCTION__
,
2306 mmio_start
, mmio_len
);
2307 release_mem_region(mmio_start
, mmio_len
);
2309 mmio_start
= pci_resource_start(pcidev
, 2);
2310 mmio_len
= pci_resource_len(pcidev
, 2);
2312 DBG_ERROR("sxg: %s rel_region(2) start[%x] len[%x]\n", __FUNCTION__
,
2313 mmio_start
, mmio_len
);
2314 release_mem_region(mmio_start
, mmio_len
);
2316 pci_disable_device(pcidev
);
2318 DBG_ERROR("sxg: %s deallocate device\n", __func__
);
2320 DBG_ERROR("sxg: %s EXIT\n", __func__
);
2323 static int sxg_entry_halt(struct net_device
*dev
)
2325 struct adapter_t
*adapter
= (struct adapter_t
*) netdev_priv(dev
);
2326 struct sxg_hw_regs
*HwRegs
= adapter
->HwRegs
;
2328 u32 RssIds
, IsrCount
;
2329 unsigned long flags
;
2331 RssIds
= SXG_RSS_CPU_COUNT(adapter
);
2332 IsrCount
= adapter
->msi_enabled
? RssIds
: 1;
2333 /* Disable interrupts */
2334 spin_lock_irqsave(&sxg_global
.driver_lock
, sxg_global
.flags
);
2335 SXG_DISABLE_ALL_INTERRUPTS(adapter
);
2336 adapter
->state
= ADAPT_DOWN
;
2337 adapter
->linkstate
= LINK_DOWN
;
2339 spin_unlock_irqrestore(&sxg_global
.driver_lock
, sxg_global
.flags
);
2340 sxg_deregister_interrupt(adapter
);
2341 WRITE_REG(HwRegs
->Reset
, 0xDEAD, FLUSH
);
2344 del_timer_sync(&adapter
->watchdog_timer
);
2345 netif_stop_queue(dev
);
2346 netif_carrier_off(dev
);
2348 napi_disable(&adapter
->napi
);
2350 WRITE_REG(adapter
->UcodeRegs
[0].RcvCmd
, 0, true);
2351 adapter
->devflags_prev
= 0;
2352 DBG_ERROR("sxg: %s (%s) set adapter[%p] state to ADAPT_DOWN(%d)\n",
2353 __func__
, dev
->name
, adapter
, adapter
->state
);
2355 spin_lock(&adapter
->RcvQLock
);
2356 /* Free all the blocks and the buffers, moved from remove() routine */
2357 if (!(IsListEmpty(&adapter
->AllRcvBlocks
))) {
2358 sxg_free_rcvblocks(adapter
);
2362 InitializeListHead(&adapter
->FreeRcvBuffers
);
2363 InitializeListHead(&adapter
->FreeRcvBlocks
);
2364 InitializeListHead(&adapter
->AllRcvBlocks
);
2365 InitializeListHead(&adapter
->FreeSglBuffers
);
2366 InitializeListHead(&adapter
->AllSglBuffers
);
2368 adapter
->FreeRcvBufferCount
= 0;
2369 adapter
->FreeRcvBlockCount
= 0;
2370 adapter
->AllRcvBlockCount
= 0;
2371 adapter
->RcvBuffersOnCard
= 0;
2372 adapter
->PendingRcvCount
= 0;
2374 memset(adapter
->RcvRings
, 0, sizeof(struct sxg_rcv_ring
) * 1);
2375 memset(adapter
->EventRings
, 0, sizeof(struct sxg_event_ring
) * RssIds
);
2376 memset(adapter
->Isr
, 0, sizeof(u32
) * IsrCount
);
2377 for (i
= 0; i
< SXG_MAX_RING_SIZE
; i
++)
2378 adapter
->RcvRingZeroInfo
.Context
[i
] = NULL
;
2379 SXG_INITIALIZE_RING(adapter
->RcvRingZeroInfo
, SXG_RCV_RING_SIZE
);
2380 SXG_INITIALIZE_RING(adapter
->XmtRingZeroInfo
, SXG_XMT_RING_SIZE
);
2382 spin_unlock(&adapter
->RcvQLock
);
2384 spin_lock_irqsave(&adapter
->XmtZeroLock
, flags
);
2385 adapter
->AllSglBufferCount
= 0;
2386 adapter
->FreeSglBufferCount
= 0;
2387 adapter
->PendingXmtCount
= 0;
2388 memset(adapter
->XmtRings
, 0, sizeof(struct sxg_xmt_ring
) * 1);
2389 memset(adapter
->XmtRingZeroIndex
, 0, sizeof(u32
));
2390 spin_unlock_irqrestore(&adapter
->XmtZeroLock
, flags
);
2392 for (i
= 0; i
< SXG_MAX_RSS
; i
++) {
2393 adapter
->NextEvent
[i
] = 0;
2395 atomic_set(&adapter
->pending_allocations
, 0);
2396 adapter
->intrregistered
= 0;
2397 sxg_remove_isr(adapter
);
2398 DBG_ERROR("sxg: %s (%s) EXIT\n", __FUNCTION__
, dev
->name
);
2399 return (STATUS_SUCCESS
);
2402 static int sxg_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
2405 /* DBG_ERROR("sxg: %s cmd[%x] rq[%p] dev[%p]\n", __func__, cmd, rq, dev);*/
2407 case SIOCSLICSETINTAGG
:
2409 /* struct adapter_t *adapter = (struct adapter_t *)
2415 if (copy_from_user(data
, rq
->ifr_data
, 28)) {
2416 DBG_ERROR("copy_from_user FAILED getting \
2422 "%s: set interrupt aggregation to %d\n",
2428 /* DBG_ERROR("sxg: %s UNSUPPORTED[%x]\n", __func__, cmd); */
2434 #define NORMAL_ETHFRAME 0
2437 * sxg_send_packets - Send a skb packet
2440 * skb - The packet to send
2441 * dev - Our linux net device that refs our adapter
2444 * 0 regardless of outcome XXXTODO refer to e1000 driver
2446 static int sxg_send_packets(struct sk_buff
*skb
, struct net_device
*dev
)
2448 struct adapter_t
*adapter
= (struct adapter_t
*) netdev_priv(dev
);
2449 u32 status
= STATUS_SUCCESS
;
2452 * DBG_ERROR("sxg: %s ENTER sxg_send_packets skb[%p]\n", __FUNCTION__,
2456 /* Check the adapter state */
2457 switch (adapter
->State
) {
2458 case SXG_STATE_INITIALIZING
:
2459 case SXG_STATE_HALTED
:
2460 case SXG_STATE_SHUTDOWN
:
2461 ASSERT(0); /* unexpected */
2463 case SXG_STATE_RESETTING
:
2464 case SXG_STATE_SLEEP
:
2465 case SXG_STATE_BOOTDIAG
:
2466 case SXG_STATE_DIAG
:
2467 case SXG_STATE_HALTING
:
2468 status
= STATUS_FAILURE
;
2470 case SXG_STATE_RUNNING
:
2471 if (adapter
->LinkState
!= SXG_LINK_UP
) {
2472 status
= STATUS_FAILURE
;
2477 status
= STATUS_FAILURE
;
2479 if (status
!= STATUS_SUCCESS
) {
2483 status
= sxg_transmit_packet(adapter
, skb
);
2484 if (status
== STATUS_SUCCESS
) {
2489 /* reject & complete all the packets if they cant be sent */
2490 if (status
!= STATUS_SUCCESS
) {
2492 /* sxg_send_packets_fail(adapter, skb, status); */
2494 SXG_DROP_DUMB_SEND(adapter
, skb
);
2495 adapter
->stats
.tx_dropped
++;
2496 return NETDEV_TX_BUSY
;
2499 DBG_ERROR("sxg: %s EXIT sxg_send_packets status[%x]\n", __func__
,
2503 return NETDEV_TX_OK
;
2507 * sxg_transmit_packet
2509 * This function transmits a single packet.
2512 * adapter - Pointer to our adapter structure
2513 * skb - The packet to be sent
2515 * Return - STATUS of send
2517 static int sxg_transmit_packet(struct adapter_t
*adapter
, struct sk_buff
*skb
)
2519 struct sxg_x64_sgl
*pSgl
;
2520 struct sxg_scatter_gather
*SxgSgl
;
2521 unsigned long sgl_flags
;
2522 /* void *SglBuffer; */
2523 /* u32 SglBufferLength; */
2526 * The vast majority of work is done in the shared
2527 * sxg_dumb_sgl routine.
2529 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "DumbSend",
2530 adapter
, skb
, 0, 0);
2532 /* Allocate a SGL buffer */
2533 SXG_GET_SGL_BUFFER(adapter
, SxgSgl
, 0);
2535 adapter
->Stats
.NoSglBuf
++;
2536 adapter
->stats
.tx_errors
++;
2537 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "SndPktF1",
2538 adapter
, skb
, 0, 0);
2539 return (STATUS_RESOURCES
);
2541 ASSERT(SxgSgl
->adapter
== adapter
);
2542 /*SglBuffer = SXG_SGL_BUFFER(SxgSgl);
2543 SglBufferLength = SXG_SGL_BUF_SIZE; */
2544 SxgSgl
->VlanTag
.VlanTci
= 0;
2545 SxgSgl
->VlanTag
.VlanTpid
= 0;
2546 SxgSgl
->Type
= SXG_SGL_DUMB
;
2547 SxgSgl
->DumbPacket
= skb
;
2550 /* Call the common sxg_dumb_sgl routine to complete the send. */
2551 return (sxg_dumb_sgl(pSgl
, SxgSgl
));
2559 * SxgSgl - struct sxg_scatter_gather
2562 * Status of send operation.
2564 static int sxg_dumb_sgl(struct sxg_x64_sgl
*pSgl
,
2565 struct sxg_scatter_gather
*SxgSgl
)
2567 struct adapter_t
*adapter
= SxgSgl
->adapter
;
2568 struct sk_buff
*skb
= SxgSgl
->DumbPacket
;
2569 /* For now, all dumb-nic sends go on RSS queue zero */
2570 struct sxg_xmt_ring
*XmtRing
= &adapter
->XmtRings
[0];
2571 struct sxg_ring_info
*XmtRingInfo
= &adapter
->XmtRingZeroInfo
;
2572 struct sxg_cmd
*XmtCmd
= NULL
;
2573 /* u32 Index = 0; */
2574 u32 DataLength
= skb
->len
;
2575 /* unsigned int BufLen; */
2576 /* u32 SglOffset; */
2578 unsigned long flags
;
2579 unsigned long queue_id
=0;
2581 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "DumbSgl",
2582 pSgl
, SxgSgl
, 0, 0);
2584 /* Set aside a pointer to the sgl */
2585 SxgSgl
->pSgl
= pSgl
;
2587 /* Sanity check that our SGL format is as we expect. */
2588 ASSERT(sizeof(struct sxg_x64_sge
) == sizeof(struct sxg_x64_sge
));
2589 /* Shouldn't be a vlan tag on this frame */
2590 ASSERT(SxgSgl
->VlanTag
.VlanTci
== 0);
2591 ASSERT(SxgSgl
->VlanTag
.VlanTpid
== 0);
2594 * From here below we work with the SGL placed in our
2598 SxgSgl
->Sgl
.NumberOfElements
= 1;
2600 * Set ucode Queue ID based on bottom bits of destination TCP port.
2601 * This Queue ID splits slowpath/dumb-nic packet processing across
2602 * multiple threads on the card to improve performance. It is split
2603 * using the TCP port to avoid out-of-order packets that can result
2604 * from multithreaded processing. We use the destination port because
2605 * we expect to be run on a server, so in nearly all cases the local
2606 * port is likely to be constant (well-known server port) and the
2607 * remote port is likely to be random. The exception to this is iSCSI,
2608 * in which case we use the sport instead. Note
2609 * that original attempt at XOR'ing source and dest port resulted in
2610 * poor balance on NTTTCP/iometer applications since they tend to
2611 * line up (even-even, odd-odd..).
2614 if (skb
->protocol
== htons(ETH_P_IP
)) {
2618 if ((ip
->protocol
== IPPROTO_TCP
)&&(DataLength
>= sizeof(
2620 queue_id
= ((ntohs(tcp_hdr(skb
)->dest
) == ISCSI_PORT
) ?
2621 (ntohs (tcp_hdr(skb
)->source
) &
2622 SXG_LARGE_SEND_QUEUE_MASK
):
2623 (ntohs(tcp_hdr(skb
)->dest
) &
2624 SXG_LARGE_SEND_QUEUE_MASK
));
2626 } else if (skb
->protocol
== htons(ETH_P_IPV6
)) {
2627 if ((ipv6_hdr(skb
)->nexthdr
== IPPROTO_TCP
) && (DataLength
>=
2628 sizeof(struct tcphdr
)) ) {
2629 queue_id
= ((ntohs(tcp_hdr(skb
)->dest
) == ISCSI_PORT
) ?
2630 (ntohs (tcp_hdr(skb
)->source
) &
2631 SXG_LARGE_SEND_QUEUE_MASK
):
2632 (ntohs(tcp_hdr(skb
)->dest
) &
2633 SXG_LARGE_SEND_QUEUE_MASK
));
2637 /* Grab the spinlock and acquire a command */
2638 spin_lock_irqsave(&adapter
->XmtZeroLock
, flags
);
2639 SXG_GET_CMD(XmtRing
, XmtRingInfo
, XmtCmd
, SxgSgl
);
2640 if (XmtCmd
== NULL
) {
2642 * Call sxg_complete_slow_send to see if we can
2643 * free up any XmtRingZero entries and then try again
2646 spin_unlock_irqrestore(&adapter
->XmtZeroLock
, flags
);
2647 sxg_complete_slow_send(adapter
);
2648 spin_lock_irqsave(&adapter
->XmtZeroLock
, flags
);
2649 SXG_GET_CMD(XmtRing
, XmtRingInfo
, XmtCmd
, SxgSgl
);
2650 if (XmtCmd
== NULL
) {
2651 adapter
->Stats
.XmtZeroFull
++;
2655 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "DumbCmd",
2656 XmtCmd
, XmtRingInfo
->Head
, XmtRingInfo
->Tail
, 0);
2658 adapter
->stats
.tx_packets
++;
2659 adapter
->stats
.tx_bytes
+= DataLength
;
2660 #if XXXTODO /* Stats stuff */
2661 if (SXG_MULTICAST_PACKET(EtherHdr
)) {
2662 if (SXG_BROADCAST_PACKET(EtherHdr
)) {
2663 adapter
->Stats
.DumbXmtBcastPkts
++;
2664 adapter
->Stats
.DumbXmtBcastBytes
+= DataLength
;
2666 adapter
->Stats
.DumbXmtMcastPkts
++;
2667 adapter
->Stats
.DumbXmtMcastBytes
+= DataLength
;
2670 adapter
->Stats
.DumbXmtUcastPkts
++;
2671 adapter
->Stats
.DumbXmtUcastBytes
+= DataLength
;
2675 * Fill in the command
2676 * Copy out the first SGE to the command and adjust for offset
2678 phys_addr
= pci_map_single(adapter
->pcidev
, skb
->data
, skb
->len
,
2682 * SAHARA SGL WORKAROUND
2683 * See if the SGL straddles a 64k boundary. If so, skip to
2684 * the start of the next 64k boundary and continue
2687 if ((adapter
->asictype
== SAHARA_REV_A
) &&
2688 (SXG_INVALID_SGL(phys_addr
,skb
->data_len
)))
2690 spin_unlock_irqrestore(&adapter
->XmtZeroLock
, flags
);
2691 /* Silently drop this packet */
2692 printk(KERN_EMERG
"Dropped a packet for 64k boundary problem\n");
2693 return STATUS_SUCCESS
;
2695 memset(XmtCmd
, '\0', sizeof(*XmtCmd
));
2696 XmtCmd
->Buffer
.FirstSgeAddress
= phys_addr
;
2697 XmtCmd
->Buffer
.FirstSgeLength
= DataLength
;
2698 XmtCmd
->Buffer
.SgeOffset
= 0;
2699 XmtCmd
->Buffer
.TotalLength
= DataLength
;
2700 XmtCmd
->SgEntries
= 1;
2703 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
2705 * We need to set the Checkum in IP header to 0. This is
2706 * required by hardware.
2708 ip_hdr(skb
)->check
= 0x0;
2709 XmtCmd
->CsumFlags
.Flags
|= SXG_SLOWCMD_CSUM_IP
;
2710 XmtCmd
->CsumFlags
.Flags
|= SXG_SLOWCMD_CSUM_TCP
;
2711 /* Dont know if length will require a change in case of VLAN */
2712 XmtCmd
->CsumFlags
.MacLen
= ETH_HLEN
;
2713 XmtCmd
->CsumFlags
.IpHl
= skb_network_header_len(skb
) >>
2714 SXG_NW_HDR_LEN_SHIFT
;
2717 * Advance transmit cmd descripter by 1.
2718 * NOTE - See comments in SxgTcpOutput where we write
2719 * to the XmtCmd register regarding CPU ID values and/or
2720 * multiple commands.
2721 * Top 16 bits specify queue_id. See comments about queue_id above
2723 /* Four queues at the moment */
2724 ASSERT((queue_id
& ~SXG_LARGE_SEND_QUEUE_MASK
) == 0);
2725 WRITE_REG(adapter
->UcodeRegs
[0].XmtCmd
, ((queue_id
<< 16) | 1), TRUE
);
2726 adapter
->Stats
.XmtQLen
++; /* Stats within lock */
2727 spin_unlock_irqrestore(&adapter
->XmtZeroLock
, flags
);
2728 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "XDumSgl2",
2729 XmtCmd
, pSgl
, SxgSgl
, 0);
2730 return STATUS_SUCCESS
;
2734 * NOTE - Only jump to this label AFTER grabbing the
2735 * XmtZeroLock, and DO NOT DROP IT between the
2736 * command allocation and the following abort.
2739 SXG_ABORT_CMD(XmtRingInfo
);
2741 spin_unlock_irqrestore(&adapter
->XmtZeroLock
, flags
);
2745 * Jump to this label if failure occurs before the
2746 * XmtZeroLock is grabbed
2748 adapter
->stats
.tx_errors
++;
2749 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_IMPORTANT
, "DumSGFal",
2750 pSgl
, SxgSgl
, XmtRingInfo
->Head
, XmtRingInfo
->Tail
);
2751 /* SxgSgl->DumbPacket is the skb */
2752 // SXG_COMPLETE_DUMB_SEND(adapter, SxgSgl->DumbPacket);
2754 return STATUS_FAILURE
;
2758 * Link management functions
2760 * sxg_initialize_link - Initialize the link stuff
2763 * adapter - A pointer to our adapter structure
2768 static int sxg_initialize_link(struct adapter_t
*adapter
)
2770 struct sxg_hw_regs
*HwRegs
= adapter
->HwRegs
;
2777 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "InitLink",
2780 /* Reset PHY and XGXS module */
2781 WRITE_REG(HwRegs
->LinkStatus
, LS_SERDES_POWER_DOWN
, TRUE
);
2783 /* Reset transmit configuration register */
2784 WRITE_REG(HwRegs
->XmtConfig
, XMT_CONFIG_RESET
, TRUE
);
2786 /* Reset receive configuration register */
2787 WRITE_REG(HwRegs
->RcvConfig
, RCV_CONFIG_RESET
, TRUE
);
2789 /* Reset all MAC modules */
2790 WRITE_REG(HwRegs
->MacConfig0
, AXGMAC_CFG0_SUB_RESET
, TRUE
);
2794 * XXXTODO - This assumes the MAC address (0a:0b:0c:0d:0e:0f)
2795 * is stored with the first nibble (0a) in the byte 0
2796 * of the Mac address. Possibly reverse?
2798 Value
= *(u32
*) adapter
->macaddr
;
2799 WRITE_REG(HwRegs
->LinkAddress0Low
, Value
, TRUE
);
2800 /* also write the MAC address to the MAC. Endian is reversed. */
2801 WRITE_REG(HwRegs
->MacAddressLow
, ntohl(Value
), TRUE
);
2802 Value
= (*(u16
*) & adapter
->macaddr
[4] & 0x0000FFFF);
2803 WRITE_REG(HwRegs
->LinkAddress0High
, Value
| LINK_ADDRESS_ENABLE
, TRUE
);
2804 /* endian swap for the MAC (put high bytes in bits [31:16], swapped) */
2805 Value
= ntohl(Value
);
2806 WRITE_REG(HwRegs
->MacAddressHigh
, Value
, TRUE
);
2807 /* Link address 1 */
2808 WRITE_REG(HwRegs
->LinkAddress1Low
, 0, TRUE
);
2809 WRITE_REG(HwRegs
->LinkAddress1High
, 0, TRUE
);
2810 /* Link address 2 */
2811 WRITE_REG(HwRegs
->LinkAddress2Low
, 0, TRUE
);
2812 WRITE_REG(HwRegs
->LinkAddress2High
, 0, TRUE
);
2813 /* Link address 3 */
2814 WRITE_REG(HwRegs
->LinkAddress3Low
, 0, TRUE
);
2815 WRITE_REG(HwRegs
->LinkAddress3High
, 0, TRUE
);
2817 /* Enable MAC modules */
2818 WRITE_REG(HwRegs
->MacConfig0
, 0, TRUE
);
2821 AxgMacReg1
= ( /* Enable XMT */
2822 AXGMAC_CFG1_XMT_EN
|
2823 /* Enable receive */
2824 AXGMAC_CFG1_RCV_EN
|
2825 /* short frame detection */
2826 AXGMAC_CFG1_SHORT_ASSERT
|
2827 /* Verify frame length */
2828 AXGMAC_CFG1_CHECK_LEN
|
2830 AXGMAC_CFG1_GEN_FCS
|
2831 /* Pad frames to 64 bytes */
2832 AXGMAC_CFG1_PAD_64
);
2834 if (adapter
->XmtFcEnabled
) {
2835 AxgMacReg1
|= AXGMAC_CFG1_XMT_PAUSE
; /* Allow sending of pause */
2837 if (adapter
->RcvFcEnabled
) {
2838 AxgMacReg1
|= AXGMAC_CFG1_RCV_PAUSE
; /* Enable detection of pause */
2841 WRITE_REG(HwRegs
->MacConfig1
, AxgMacReg1
, TRUE
);
2843 /* Set AXGMAC max frame length if jumbo. Not needed for standard MTU */
2844 if (adapter
->JumboEnabled
) {
2845 WRITE_REG(HwRegs
->MacMaxFrameLen
, AXGMAC_MAXFRAME_JUMBO
, TRUE
);
2848 * AMIIM Configuration Register -
2849 * The value placed in the AXGMAC_AMIIM_CFG_HALF_CLOCK portion
2850 * (bottom bits) of this register is used to determine the MDC frequency
2851 * as specified in the A-XGMAC Design Document. This value must not be
2852 * zero. The following value (62 or 0x3E) is based on our MAC transmit
2853 * clock frequency (MTCLK) of 312.5 MHz. Given a maximum MDIO clock
2854 * frequency of 2.5 MHz (see the PHY spec), we get:
2855 * 312.5/(2*(X+1)) < 2.5 ==> X = 62.
2856 * This value happens to be the default value for this register, so we
2857 * really don't have to do this.
2859 if (adapter
->asictype
== SAHARA_REV_B
) {
2860 WRITE_REG(HwRegs
->MacAmiimConfig
, 0x0000001F, TRUE
);
2862 WRITE_REG(HwRegs
->MacAmiimConfig
, 0x0000003E, TRUE
);
2865 /* Power up and enable PHY and XAUI/XGXS/Serdes logic */
2866 WRITE_REG(HwRegs
->LinkStatus
,
2873 DBG_ERROR("After Power Up and enable PHY in sxg_initialize_link\n");
2876 * Per information given by Aeluros, wait 100 ms after removing reset.
2877 * It's not enough to wait for the self-clearing reset bit in reg 0 to
2882 /* Verify the PHY has come up by checking that the Reset bit has
2885 status
= sxg_read_mdio_reg(adapter
,
2886 MIIM_DEV_PHY_PMA
, /* PHY PMA/PMD module */
2887 PHY_PMA_CONTROL1
, /* PMA/PMD control register */
2889 DBG_ERROR("After sxg_read_mdio_reg Value[%x] fail=%x\n", Value
,
2890 (Value
& PMA_CONTROL1_RESET
));
2891 if (status
!= STATUS_SUCCESS
)
2892 return (STATUS_FAILURE
);
2893 if (Value
& PMA_CONTROL1_RESET
) /* reset complete if bit is 0 */
2894 return (STATUS_FAILURE
);
2896 /* The SERDES should be initialized by now - confirm */
2897 READ_REG(HwRegs
->LinkStatus
, Value
);
2898 if (Value
& LS_SERDES_DOWN
) /* verify SERDES is initialized */
2899 return (STATUS_FAILURE
);
2901 /* The XAUI link should also be up - confirm */
2902 if (!(Value
& LS_XAUI_LINK_UP
)) /* verify XAUI link is up */
2903 return (STATUS_FAILURE
);
2905 /* Initialize the PHY */
2906 status
= sxg_phy_init(adapter
);
2907 if (status
!= STATUS_SUCCESS
)
2908 return (STATUS_FAILURE
);
2910 /* Enable the Link Alarm */
2912 /* MIIM_DEV_PHY_PMA - PHY PMA/PMD module
2913 * LASI_CONTROL - LASI control register
2914 * LASI_CTL_LS_ALARM_ENABLE - enable link alarm bit
2916 status
= sxg_write_mdio_reg(adapter
, MIIM_DEV_PHY_PMA
,
2918 LASI_CTL_LS_ALARM_ENABLE
);
2919 if (status
!= STATUS_SUCCESS
)
2920 return (STATUS_FAILURE
);
2922 /* XXXTODO - temporary - verify bit is set */
2924 /* MIIM_DEV_PHY_PMA - PHY PMA/PMD module
2925 * LASI_CONTROL - LASI control register
2927 status
= sxg_read_mdio_reg(adapter
, MIIM_DEV_PHY_PMA
,
2931 if (status
!= STATUS_SUCCESS
)
2932 return (STATUS_FAILURE
);
2933 if (!(Value
& LASI_CTL_LS_ALARM_ENABLE
)) {
2934 DBG_ERROR("Error! LASI Control Alarm Enable bit not set!\n");
2936 /* Enable receive */
2937 MaxFrame
= adapter
->JumboEnabled
? JUMBOMAXFRAME
: ETHERMAXFRAME
;
2938 ConfigData
= (RCV_CONFIG_ENABLE
|
2939 RCV_CONFIG_ENPARSE
|
2941 RCV_CONFIG_RCVPAUSE
|
2944 RCV_CONFIG_HASH_16
|
2945 RCV_CONFIG_SOCKET
| RCV_CONFIG_BUFSIZE(MaxFrame
));
2947 if (adapter
->asictype
== SAHARA_REV_B
) {
2948 ConfigData
|= (RCV_CONFIG_HIPRICTL
|
2949 RCV_CONFIG_NEWSTATUSFMT
);
2951 WRITE_REG(HwRegs
->RcvConfig
, ConfigData
, TRUE
);
2953 WRITE_REG(HwRegs
->XmtConfig
, XMT_CONFIG_ENABLE
, TRUE
);
2955 /* Mark the link as down. We'll get a link event when it comes up. */
2956 sxg_link_state(adapter
, SXG_LINK_DOWN
);
2958 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "XInitLnk",
2960 return (STATUS_SUCCESS
);
2964 * sxg_phy_init - Initialize the PHY
2967 * adapter - A pointer to our adapter structure
2972 static int sxg_phy_init(struct adapter_t
*adapter
)
2975 struct phy_ucode
*p
;
2978 DBG_ERROR("ENTER %s\n", __func__
);
2980 /* MIIM_DEV_PHY_PMA - PHY PMA/PMD module
2981 * 0xC205 - PHY ID register (?)
2982 * &Value - XXXTODO - add def
2984 status
= sxg_read_mdio_reg(adapter
, MIIM_DEV_PHY_PMA
,
2987 if (status
!= STATUS_SUCCESS
)
2988 return (STATUS_FAILURE
);
2990 if (Value
== 0x0012) {
2991 /* 0x0012 == AEL2005C PHY(?) - XXXTODO - add def */
2992 DBG_ERROR("AEL2005C PHY detected. Downloading PHY \
2995 /* Initialize AEL2005C PHY and download PHY microcode */
2996 for (p
= PhyUcode
; p
->Addr
!= 0xFFFF; p
++) {
2998 /* if address == 0, data == sleep time in ms */
3001 /* write the given data to the specified address */
3002 status
= sxg_write_mdio_reg(adapter
,
3008 if (status
!= STATUS_SUCCESS
)
3009 return (STATUS_FAILURE
);
3013 DBG_ERROR("EXIT %s\n", __func__
);
3015 return (STATUS_SUCCESS
);
3019 * sxg_link_event - Process a link event notification from the card
3022 * adapter - A pointer to our adapter structure
3027 static void sxg_link_event(struct adapter_t
*adapter
)
3029 struct sxg_hw_regs
*HwRegs
= adapter
->HwRegs
;
3030 struct net_device
*netdev
= adapter
->netdev
;
3031 enum SXG_LINK_STATE LinkState
;
3035 if (adapter
->state
== ADAPT_DOWN
)
3037 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "LinkEvnt",
3039 DBG_ERROR("ENTER %s\n", __func__
);
3041 /* Check the Link Status register. We should have a Link Alarm. */
3042 READ_REG(HwRegs
->LinkStatus
, Value
);
3043 if (Value
& LS_LINK_ALARM
) {
3045 * We got a Link Status alarm. First, pause to let the
3046 * link state settle (it can bounce a number of times)
3050 /* Now clear the alarm by reading the LASI status register. */
3051 /* MIIM_DEV_PHY_PMA - PHY PMA/PMD module */
3052 status
= sxg_read_mdio_reg(adapter
, MIIM_DEV_PHY_PMA
,
3053 /* LASI status register */
3056 if (status
!= STATUS_SUCCESS
) {
3057 DBG_ERROR("Error reading LASI Status MDIO register!\n");
3058 sxg_link_state(adapter
, SXG_LINK_DOWN
);
3062 * We used to assert that the LASI_LS_ALARM bit was set, as
3063 * it should be. But there appears to be cases during
3064 * initialization (when the PHY is reset and re-initialized)
3065 * when we get a link alarm, but the status bit is 0 when we
3066 * read it. Rather than trying to assure this never happens
3067 * (and nver being certain), just ignore it.
3069 * ASSERT(Value & LASI_STATUS_LS_ALARM);
3072 /* Now get and set the link state */
3073 LinkState
= sxg_get_link_state(adapter
);
3074 sxg_link_state(adapter
, LinkState
);
3075 DBG_ERROR("SXG: Link Alarm occurred. Link is %s\n",
3076 ((LinkState
== SXG_LINK_UP
) ? "UP" : "DOWN"));
3077 if (LinkState
== SXG_LINK_UP
) {
3078 netif_carrier_on(netdev
);
3079 netif_tx_start_all_queues(netdev
);
3081 netif_tx_stop_all_queues(netdev
);
3082 netif_carrier_off(netdev
);
3086 * XXXTODO - Assuming Link Attention is only being generated
3087 * for the Link Alarm pin (and not for a XAUI Link Status change)
3088 * , then it's impossible to get here. Yet we've gotten here
3089 * twice (under extreme conditions - bouncing the link up and
3090 * down many times a second). Needs further investigation.
3092 DBG_ERROR("SXG: sxg_link_event: Can't get here!\n");
3093 DBG_ERROR("SXG: Link Status == 0x%08X.\n", Value
);
3096 DBG_ERROR("EXIT %s\n", __func__
);
3101 * sxg_get_link_state - Determine if the link is up or down
3104 * adapter - A pointer to our adapter structure
3109 static enum SXG_LINK_STATE
sxg_get_link_state(struct adapter_t
*adapter
)
3114 DBG_ERROR("ENTER %s\n", __func__
);
3116 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "GetLink",
3120 * Per the Xenpak spec (and the IEEE 10Gb spec?), the link is up if
3121 * the following 3 bits (from 3 different MDIO registers) are all true.
3124 /* MIIM_DEV_PHY_PMA - PHY PMA/PMD module */
3125 status
= sxg_read_mdio_reg(adapter
, MIIM_DEV_PHY_PMA
,
3126 /* PMA/PMD Receive Signal Detect register */
3129 if (status
!= STATUS_SUCCESS
)
3132 /* If PMA/PMD receive signal detect is 0, then the link is down */
3133 if (!(Value
& PMA_RCV_DETECT
))
3134 return (SXG_LINK_DOWN
);
3136 /* MIIM_DEV_PHY_PCS - PHY PCS module */
3137 status
= sxg_read_mdio_reg(adapter
, MIIM_DEV_PHY_PCS
,
3138 /* PCS 10GBASE-R Status 1 register */
3139 PHY_PCS_10G_STATUS1
,
3141 if (status
!= STATUS_SUCCESS
)
3144 /* If PCS is not locked to receive blocks, then the link is down */
3145 if (!(Value
& PCS_10B_BLOCK_LOCK
))
3146 return (SXG_LINK_DOWN
);
3148 status
= sxg_read_mdio_reg(adapter
, MIIM_DEV_PHY_XS
,/* PHY XS module */
3149 /* XS Lane Status register */
3152 if (status
!= STATUS_SUCCESS
)
3155 /* If XS transmit lanes are not aligned, then the link is down */
3156 if (!(Value
& XS_LANE_ALIGN
))
3157 return (SXG_LINK_DOWN
);
3159 /* All 3 bits are true, so the link is up */
3160 DBG_ERROR("EXIT %s\n", __func__
);
3162 return (SXG_LINK_UP
);
3165 /* An error occurred reading an MDIO register. This shouldn't happen. */
3166 DBG_ERROR("Error reading an MDIO register!\n");
3168 return (SXG_LINK_DOWN
);
3171 static void sxg_indicate_link_state(struct adapter_t
*adapter
,
3172 enum SXG_LINK_STATE LinkState
)
3174 if (adapter
->LinkState
== SXG_LINK_UP
) {
3175 DBG_ERROR("%s: LINK now UP, call netif_start_queue\n",
3177 netif_start_queue(adapter
->netdev
);
3179 DBG_ERROR("%s: LINK now DOWN, call netif_stop_queue\n",
3181 netif_stop_queue(adapter
->netdev
);
3186 * sxg_change_mtu - Change the Maximum Transfer Unit
3187 * * @returns 0 on success, negative on failure
3189 int sxg_change_mtu (struct net_device
*netdev
, int new_mtu
)
3191 struct adapter_t
*adapter
= (struct adapter_t
*) netdev_priv(netdev
);
3193 if (!((new_mtu
== SXG_DEFAULT_MTU
) || (new_mtu
== SXG_JUMBO_MTU
)))
3196 if(new_mtu
== netdev
->mtu
)
3199 netdev
->mtu
= new_mtu
;
3201 if (new_mtu
== SXG_JUMBO_MTU
) {
3202 adapter
->JumboEnabled
= TRUE
;
3203 adapter
->FrameSize
= JUMBOMAXFRAME
;
3204 adapter
->ReceiveBufferSize
= SXG_RCV_JUMBO_BUFFER_SIZE
;
3206 adapter
->JumboEnabled
= FALSE
;
3207 adapter
->FrameSize
= ETHERMAXFRAME
;
3208 adapter
->ReceiveBufferSize
= SXG_RCV_DATA_BUFFER_SIZE
;
3211 sxg_entry_halt(netdev
);
3212 sxg_entry_open(netdev
);
3217 * sxg_link_state - Set the link state and if necessary, indicate.
3218 * This routine the central point of processing for all link state changes.
3219 * Nothing else in the driver should alter the link state or perform
3220 * link state indications
3223 * adapter - A pointer to our adapter structure
3224 * LinkState - The link state
3229 static void sxg_link_state(struct adapter_t
*adapter
,
3230 enum SXG_LINK_STATE LinkState
)
3232 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_IMPORTANT
, "LnkINDCT",
3233 adapter
, LinkState
, adapter
->LinkState
, adapter
->State
);
3235 DBG_ERROR("ENTER %s\n", __func__
);
3238 * Hold the adapter lock during this routine. Maybe move
3239 * the lock to the caller.
3241 /* IMP TODO : Check if we can survive without taking this lock */
3242 // spin_lock(&adapter->AdapterLock);
3243 if (LinkState
== adapter
->LinkState
) {
3244 /* Nothing changed.. */
3245 // spin_unlock(&adapter->AdapterLock);
3246 DBG_ERROR("EXIT #0 %s. Link status = %d\n",
3247 __func__
, LinkState
);
3250 /* Save the adapter state */
3251 adapter
->LinkState
= LinkState
;
3253 /* Drop the lock and indicate link state */
3254 // spin_unlock(&adapter->AdapterLock);
3255 DBG_ERROR("EXIT #1 %s\n", __func__
);
3257 sxg_indicate_link_state(adapter
, LinkState
);
3261 * sxg_write_mdio_reg - Write to a register on the MDIO bus
3264 * adapter - A pointer to our adapter structure
3265 * DevAddr - MDIO device number being addressed
3266 * RegAddr - register address for the specified MDIO device
3267 * Value - value to write to the MDIO register
3272 static int sxg_write_mdio_reg(struct adapter_t
*adapter
,
3273 u32 DevAddr
, u32 RegAddr
, u32 Value
)
3275 struct sxg_hw_regs
*HwRegs
= adapter
->HwRegs
;
3276 /* Address operation (written to MIIM field reg) */
3278 /* Write operation (written to MIIM field reg) */
3280 u32 Cmd
;/* Command (written to MIIM command reg) */
3284 /* DBG_ERROR("ENTER %s\n", __func__); */
3286 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "WrtMDIO",
3289 /* Ensure values don't exceed field width */
3290 DevAddr
&= 0x001F; /* 5-bit field */
3291 RegAddr
&= 0xFFFF; /* 16-bit field */
3292 Value
&= 0xFFFF; /* 16-bit field */
3294 /* Set MIIM field register bits for an MIIM address operation */
3295 AddrOp
= (MIIM_PORT_NUM
<< AXGMAC_AMIIM_FIELD_PORT_SHIFT
) |
3296 (DevAddr
<< AXGMAC_AMIIM_FIELD_DEV_SHIFT
) |
3297 (MIIM_TA_10GB
<< AXGMAC_AMIIM_FIELD_TA_SHIFT
) |
3298 (MIIM_OP_ADDR
<< AXGMAC_AMIIM_FIELD_OP_SHIFT
) | RegAddr
;
3300 /* Set MIIM field register bits for an MIIM write operation */
3301 WriteOp
= (MIIM_PORT_NUM
<< AXGMAC_AMIIM_FIELD_PORT_SHIFT
) |
3302 (DevAddr
<< AXGMAC_AMIIM_FIELD_DEV_SHIFT
) |
3303 (MIIM_TA_10GB
<< AXGMAC_AMIIM_FIELD_TA_SHIFT
) |
3304 (MIIM_OP_WRITE
<< AXGMAC_AMIIM_FIELD_OP_SHIFT
) | Value
;
3306 /* Set MIIM command register bits to execute an MIIM command */
3307 Cmd
= AXGMAC_AMIIM_CMD_START
| AXGMAC_AMIIM_CMD_10G_OPERATION
;
3309 /* Reset the command register command bit (in case it's not 0) */
3310 WRITE_REG(HwRegs
->MacAmiimCmd
, 0, TRUE
);
3312 /* MIIM write to set the address of the specified MDIO register */
3313 WRITE_REG(HwRegs
->MacAmiimField
, AddrOp
, TRUE
);
3315 /* Write to MIIM Command Register to execute to address operation */
3316 WRITE_REG(HwRegs
->MacAmiimCmd
, Cmd
, TRUE
);
3318 /* Poll AMIIM Indicator register to wait for completion */
3319 Timeout
= SXG_LINK_TIMEOUT
;
3321 udelay(100); /* Timeout in 100us units */
3322 READ_REG(HwRegs
->MacAmiimIndicator
, ValueRead
);
3323 if (--Timeout
== 0) {
3324 return (STATUS_FAILURE
);
3326 } while (ValueRead
& AXGMAC_AMIIM_INDC_BUSY
);
3328 /* Reset the command register command bit */
3329 WRITE_REG(HwRegs
->MacAmiimCmd
, 0, TRUE
);
3331 /* MIIM write to set up an MDIO write operation */
3332 WRITE_REG(HwRegs
->MacAmiimField
, WriteOp
, TRUE
);
3334 /* Write to MIIM Command Register to execute the write operation */
3335 WRITE_REG(HwRegs
->MacAmiimCmd
, Cmd
, TRUE
);
3337 /* Poll AMIIM Indicator register to wait for completion */
3338 Timeout
= SXG_LINK_TIMEOUT
;
3340 udelay(100); /* Timeout in 100us units */
3341 READ_REG(HwRegs
->MacAmiimIndicator
, ValueRead
);
3342 if (--Timeout
== 0) {
3343 return (STATUS_FAILURE
);
3345 } while (ValueRead
& AXGMAC_AMIIM_INDC_BUSY
);
3347 /* DBG_ERROR("EXIT %s\n", __func__); */
3349 return (STATUS_SUCCESS
);
3353 * sxg_read_mdio_reg - Read a register on the MDIO bus
3356 * adapter - A pointer to our adapter structure
3357 * DevAddr - MDIO device number being addressed
3358 * RegAddr - register address for the specified MDIO device
3359 * pValue - pointer to where to put data read from the MDIO register
3364 static int sxg_read_mdio_reg(struct adapter_t
*adapter
,
3365 u32 DevAddr
, u32 RegAddr
, u32
*pValue
)
3367 struct sxg_hw_regs
*HwRegs
= adapter
->HwRegs
;
3368 u32 AddrOp
; /* Address operation (written to MIIM field reg) */
3369 u32 ReadOp
; /* Read operation (written to MIIM field reg) */
3370 u32 Cmd
; /* Command (written to MIIM command reg) */
3374 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "WrtMDIO",
3376 DBG_ERROR("ENTER %s\n", __FUNCTION__
);
3378 /* Ensure values don't exceed field width */
3379 DevAddr
&= 0x001F; /* 5-bit field */
3380 RegAddr
&= 0xFFFF; /* 16-bit field */
3382 /* Set MIIM field register bits for an MIIM address operation */
3383 AddrOp
= (MIIM_PORT_NUM
<< AXGMAC_AMIIM_FIELD_PORT_SHIFT
) |
3384 (DevAddr
<< AXGMAC_AMIIM_FIELD_DEV_SHIFT
) |
3385 (MIIM_TA_10GB
<< AXGMAC_AMIIM_FIELD_TA_SHIFT
) |
3386 (MIIM_OP_ADDR
<< AXGMAC_AMIIM_FIELD_OP_SHIFT
) | RegAddr
;
3388 /* Set MIIM field register bits for an MIIM read operation */
3389 ReadOp
= (MIIM_PORT_NUM
<< AXGMAC_AMIIM_FIELD_PORT_SHIFT
) |
3390 (DevAddr
<< AXGMAC_AMIIM_FIELD_DEV_SHIFT
) |
3391 (MIIM_TA_10GB
<< AXGMAC_AMIIM_FIELD_TA_SHIFT
) |
3392 (MIIM_OP_READ
<< AXGMAC_AMIIM_FIELD_OP_SHIFT
);
3394 /* Set MIIM command register bits to execute an MIIM command */
3395 Cmd
= AXGMAC_AMIIM_CMD_START
| AXGMAC_AMIIM_CMD_10G_OPERATION
;
3397 /* Reset the command register command bit (in case it's not 0) */
3398 WRITE_REG(HwRegs
->MacAmiimCmd
, 0, TRUE
);
3400 /* MIIM write to set the address of the specified MDIO register */
3401 WRITE_REG(HwRegs
->MacAmiimField
, AddrOp
, TRUE
);
3403 /* Write to MIIM Command Register to execute to address operation */
3404 WRITE_REG(HwRegs
->MacAmiimCmd
, Cmd
, TRUE
);
3406 /* Poll AMIIM Indicator register to wait for completion */
3407 Timeout
= SXG_LINK_TIMEOUT
;
3409 udelay(100); /* Timeout in 100us units */
3410 READ_REG(HwRegs
->MacAmiimIndicator
, ValueRead
);
3411 if (--Timeout
== 0) {
3412 DBG_ERROR("EXIT %s with STATUS_FAILURE 1\n", __FUNCTION__
);
3414 return (STATUS_FAILURE
);
3416 } while (ValueRead
& AXGMAC_AMIIM_INDC_BUSY
);
3418 /* Reset the command register command bit */
3419 WRITE_REG(HwRegs
->MacAmiimCmd
, 0, TRUE
);
3421 /* MIIM write to set up an MDIO register read operation */
3422 WRITE_REG(HwRegs
->MacAmiimField
, ReadOp
, TRUE
);
3424 /* Write to MIIM Command Register to execute the read operation */
3425 WRITE_REG(HwRegs
->MacAmiimCmd
, Cmd
, TRUE
);
3427 /* Poll AMIIM Indicator register to wait for completion */
3428 Timeout
= SXG_LINK_TIMEOUT
;
3430 udelay(100); /* Timeout in 100us units */
3431 READ_REG(HwRegs
->MacAmiimIndicator
, ValueRead
);
3432 if (--Timeout
== 0) {
3433 DBG_ERROR("EXIT %s with STATUS_FAILURE 2\n", __FUNCTION__
);
3435 return (STATUS_FAILURE
);
3437 } while (ValueRead
& AXGMAC_AMIIM_INDC_BUSY
);
3439 /* Read the MDIO register data back from the field register */
3440 READ_REG(HwRegs
->MacAmiimField
, *pValue
);
3441 *pValue
&= 0xFFFF; /* data is in the lower 16 bits */
3443 DBG_ERROR("EXIT %s\n", __FUNCTION__
);
3445 return (STATUS_SUCCESS
);
3449 * Functions to obtain the CRC corresponding to the destination mac address.
3450 * This is a standard ethernet CRC in that it is a 32-bit, reflected CRC using
3452 * x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5
3453 * + x^4 + x^2 + x^1.
3455 * After the CRC for the 6 bytes is generated (but before the value is
3456 * complemented), we must then transpose the value and return bits 30-23.
3458 static u32 sxg_crc_table
[256];/* Table of CRC's for all possible byte values */
3459 static u32 sxg_crc_init
; /* Is table initialized */
3461 /* Contruct the CRC32 table */
3462 static void sxg_mcast_init_crc32(void)
3464 u32 c
; /* CRC shit reg */
3465 u32 e
= 0; /* Poly X-or pattern */
3466 int i
; /* counter */
3467 int k
; /* byte being shifted into crc */
3469 static int p
[] = { 0, 1, 2, 4, 5, 7, 8, 10, 11, 12, 16, 22, 23, 26 };
3471 for (i
= 0; i
< sizeof(p
) / sizeof(int); i
++) {
3472 e
|= 1L << (31 - p
[i
]);
3475 for (i
= 1; i
< 256; i
++) {
3477 for (k
= 8; k
; k
--) {
3478 c
= c
& 1 ? (c
>> 1) ^ e
: c
>> 1;
3480 sxg_crc_table
[i
] = c
;
3485 * Return the MAC hast as described above.
3487 static unsigned char sxg_mcast_get_mac_hash(char *macaddr
)
3492 unsigned char machash
= 0;
3494 if (!sxg_crc_init
) {
3495 sxg_mcast_init_crc32();
3499 crc
= 0xFFFFFFFF; /* Preload shift register, per crc-32 spec */
3500 for (i
= 0, p
= macaddr
; i
< 6; ++p
, ++i
) {
3501 crc
= (crc
>> 8) ^ sxg_crc_table
[(crc
^ *p
) & 0xFF];
3504 /* Return bits 1-8, transposed */
3505 for (i
= 1; i
< 9; i
++) {
3506 machash
|= (((crc
>> i
) & 1) << (8 - i
));
3512 static void sxg_mcast_set_mask(struct adapter_t
*adapter
)
3514 struct sxg_ucode_regs
*sxg_regs
= adapter
->UcodeRegs
;
3516 DBG_ERROR("%s ENTER (%s) MacFilter[%x] mask[%llx]\n", __FUNCTION__
,
3517 adapter
->netdev
->name
, (unsigned int)adapter
->MacFilter
,
3518 adapter
->MulticastMask
);
3520 if (adapter
->MacFilter
& (MAC_ALLMCAST
| MAC_PROMISC
)) {
3522 * Turn on all multicast addresses. We have to do this for
3523 * promiscuous mode as well as ALLMCAST mode. It saves the
3524 * Microcode from having keep state about the MAC configuration
3526 /* DBG_ERROR("sxg: %s MacFilter = MAC_ALLMCAST | MAC_PROMISC\n \
3527 * SLUT MODE!!!\n",__func__);
3529 WRITE_REG(sxg_regs
->McastLow
, 0xFFFFFFFF, FLUSH
);
3530 WRITE_REG(sxg_regs
->McastHigh
, 0xFFFFFFFF, FLUSH
);
3531 /* DBG_ERROR("%s (%s) WRITE to slic_regs slic_mcastlow&high \
3532 * 0xFFFFFFFF\n",__func__, adapter->netdev->name);
3537 * Commit our multicast mast to the SLIC by writing to the
3538 * multicast address mask registers
3540 DBG_ERROR("%s (%s) WRITE mcastlow[%lx] mcasthigh[%lx]\n",
3541 __func__
, adapter
->netdev
->name
,
3542 ((ulong
) (adapter
->MulticastMask
& 0xFFFFFFFF)),
3544 ((adapter
->MulticastMask
>> 32) & 0xFFFFFFFF)));
3546 WRITE_REG(sxg_regs
->McastLow
,
3547 (u32
) (adapter
->MulticastMask
& 0xFFFFFFFF), FLUSH
);
3548 WRITE_REG(sxg_regs
->McastHigh
,
3550 MulticastMask
>> 32) & 0xFFFFFFFF), FLUSH
);
3554 static void sxg_mcast_set_bit(struct adapter_t
*adapter
, char *address
)
3556 unsigned char crcpoly
;
3558 /* Get the CRC polynomial for the mac address */
3559 crcpoly
= sxg_mcast_get_mac_hash(address
);
3562 * We only have space on the SLIC for 64 entries. Lop
3563 * off the top two bits. (2^6 = 64)
3567 /* OR in the new bit into our 64 bit mask. */
3568 adapter
->MulticastMask
|= (u64
) 1 << crcpoly
;
3572 * Function takes MAC addresses from dev_mc_list and generates the Mask
3575 static void sxg_set_mcast_addr(struct adapter_t
*adapter
)
3577 struct dev_mc_list
*mclist
;
3578 struct net_device
*dev
= adapter
->netdev
;
3581 if (adapter
->MacFilter
& (MAC_ALLMCAST
| MAC_MCAST
)) {
3582 for (i
= 0, mclist
= dev
->mc_list
; i
< dev
->mc_count
;
3583 i
++, mclist
= mclist
->next
) {
3584 sxg_mcast_set_bit(adapter
,mclist
->da_addr
);
3587 sxg_mcast_set_mask(adapter
);
3590 static void sxg_mcast_set_list(struct net_device
*dev
)
3592 struct adapter_t
*adapter
= (struct adapter_t
*) netdev_priv(dev
);
3595 if (dev
->flags
& IFF_PROMISC
)
3596 adapter
->MacFilter
|= MAC_PROMISC
;
3597 if (dev
->flags
& IFF_MULTICAST
)
3598 adapter
->MacFilter
|= MAC_MCAST
;
3599 if (dev
->flags
& IFF_ALLMULTI
)
3600 adapter
->MacFilter
|= MAC_ALLMCAST
;
3602 //XXX handle other flags as well
3603 sxg_set_mcast_addr(adapter
);
3606 void sxg_free_sgl_buffers(struct adapter_t
*adapter
)
3608 struct list_entry
*ple
;
3609 struct sxg_scatter_gather
*Sgl
;
3611 while(!(IsListEmpty(&adapter
->AllSglBuffers
))) {
3612 ple
= RemoveHeadList(&adapter
->AllSglBuffers
);
3613 Sgl
= container_of(ple
, struct sxg_scatter_gather
, AllList
);
3615 adapter
->AllSglBufferCount
--;
3619 void sxg_free_rcvblocks(struct adapter_t
*adapter
)
3622 void *temp_RcvBlock
;
3623 struct list_entry
*ple
;
3624 struct sxg_rcv_block_hdr
*RcvBlockHdr
;
3625 struct sxg_rcv_data_buffer_hdr
*RcvDataBufferHdr
;
3626 ASSERT((adapter
->state
== SXG_STATE_INITIALIZING
) ||
3627 (adapter
->state
== SXG_STATE_HALTING
));
3628 while(!(IsListEmpty(&adapter
->AllRcvBlocks
))) {
3630 ple
= RemoveHeadList(&adapter
->AllRcvBlocks
);
3631 RcvBlockHdr
= container_of(ple
, struct sxg_rcv_block_hdr
, AllList
);
3633 if(RcvBlockHdr
->VirtualAddress
) {
3634 temp_RcvBlock
= RcvBlockHdr
->VirtualAddress
;
3636 for(i
=0; i
< SXG_RCV_DESCRIPTORS_PER_BLOCK
;
3637 i
++, temp_RcvBlock
+= SXG_RCV_DATA_HDR_SIZE
) {
3639 (struct sxg_rcv_data_buffer_hdr
*)temp_RcvBlock
;
3640 SXG_FREE_RCV_PACKET(RcvDataBufferHdr
);
3644 pci_free_consistent(adapter
->pcidev
,
3645 SXG_RCV_BLOCK_SIZE(SXG_RCV_DATA_HDR_SIZE
),
3646 RcvBlockHdr
->VirtualAddress
,
3647 RcvBlockHdr
->PhysicalAddress
);
3648 adapter
->AllRcvBlockCount
--;
3650 ASSERT(adapter
->AllRcvBlockCount
== 0);
3651 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "XFrRBlk",
3654 void sxg_free_mcast_addrs(struct adapter_t
*adapter
)
3656 struct sxg_multicast_address
*address
;
3657 while(adapter
->MulticastAddrs
) {
3658 address
= adapter
->MulticastAddrs
;
3659 adapter
->MulticastAddrs
= address
->Next
;
3663 adapter
->MulticastMask
= 0;
3666 void sxg_unmap_resources(struct adapter_t
*adapter
)
3668 if(adapter
->HwRegs
) {
3669 iounmap((void *)adapter
->HwRegs
);
3671 if(adapter
->UcodeRegs
) {
3672 iounmap((void *)adapter
->UcodeRegs
);
3675 ASSERT(adapter
->AllRcvBlockCount
== 0);
3676 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "XFrRBlk",
3683 * sxg_free_resources - Free everything allocated in SxgAllocateResources
3686 * adapter - A pointer to our adapter structure
3691 void sxg_free_resources(struct adapter_t
*adapter
)
3693 u32 RssIds
, IsrCount
;
3694 RssIds
= SXG_RSS_CPU_COUNT(adapter
);
3695 IsrCount
= adapter
->msi_enabled
? RssIds
: 1;
3697 if (adapter
->BasicAllocations
== FALSE
) {
3699 * No allocations have been made, including spinlocks,
3700 * or listhead initializations. Return.
3705 if (!(IsListEmpty(&adapter
->AllRcvBlocks
))) {
3706 sxg_free_rcvblocks(adapter
);
3708 if (!(IsListEmpty(&adapter
->AllSglBuffers
))) {
3709 sxg_free_sgl_buffers(adapter
);
3712 if (adapter
->XmtRingZeroIndex
) {
3713 pci_free_consistent(adapter
->pcidev
,
3715 adapter
->XmtRingZeroIndex
,
3716 adapter
->PXmtRingZeroIndex
);
3719 pci_free_consistent(adapter
->pcidev
,
3720 sizeof(u32
) * IsrCount
,
3721 adapter
->Isr
, adapter
->PIsr
);
3724 if (adapter
->EventRings
) {
3725 pci_free_consistent(adapter
->pcidev
,
3726 sizeof(struct sxg_event_ring
) * RssIds
,
3727 adapter
->EventRings
, adapter
->PEventRings
);
3729 if (adapter
->RcvRings
) {
3730 pci_free_consistent(adapter
->pcidev
,
3731 sizeof(struct sxg_rcv_ring
) * 1,
3733 adapter
->PRcvRings
);
3734 adapter
->RcvRings
= NULL
;
3737 if(adapter
->XmtRings
) {
3738 pci_free_consistent(adapter
->pcidev
,
3739 sizeof(struct sxg_xmt_ring
) * 1,
3741 adapter
->PXmtRings
);
3742 adapter
->XmtRings
= NULL
;
3745 if (adapter
->ucode_stats
) {
3746 pci_unmap_single(adapter
->pcidev
,
3747 sizeof(struct sxg_ucode_stats
),
3748 adapter
->pucode_stats
, PCI_DMA_FROMDEVICE
);
3749 adapter
->ucode_stats
= NULL
;
3753 /* Unmap register spaces */
3754 sxg_unmap_resources(adapter
);
3756 sxg_free_mcast_addrs(adapter
);
3758 adapter
->BasicAllocations
= FALSE
;
3763 * sxg_allocate_complete -
3765 * This routine is called when a memory allocation has completed.
3768 * struct adapter_t * - Our adapter structure
3769 * VirtualAddress - Memory virtual address
3770 * PhysicalAddress - Memory physical address
3771 * Length - Length of memory allocated (or 0)
3772 * Context - The type of buffer allocated
3777 static int sxg_allocate_complete(struct adapter_t
*adapter
,
3778 void *VirtualAddress
,
3779 dma_addr_t PhysicalAddress
,
3780 u32 Length
, enum sxg_buffer_type Context
)
3783 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "AllocCmp",
3784 adapter
, VirtualAddress
, Length
, Context
);
3785 ASSERT(atomic_read(&adapter
->pending_allocations
));
3786 atomic_dec(&adapter
->pending_allocations
);
3790 case SXG_BUFFER_TYPE_RCV
:
3791 status
= sxg_allocate_rcvblock_complete(adapter
,
3793 PhysicalAddress
, Length
);
3795 case SXG_BUFFER_TYPE_SGL
:
3796 sxg_allocate_sgl_buffer_complete(adapter
, (struct sxg_scatter_gather
*)
3798 PhysicalAddress
, Length
);
3801 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "XAlocCmp",
3802 adapter
, VirtualAddress
, Length
, Context
);
3808 * sxg_allocate_buffer_memory - Shared memory allocation routine used for
3809 * synchronous and asynchronous buffer allocations
3812 * adapter - A pointer to our adapter structure
3813 * Size - block size to allocate
3814 * BufferType - Type of buffer to allocate
3819 static int sxg_allocate_buffer_memory(struct adapter_t
*adapter
,
3820 u32 Size
, enum sxg_buffer_type BufferType
)
3826 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "AllocMem",
3827 adapter
, Size
, BufferType
, 0);
3829 * Grab the adapter lock and check the state. If we're in anything other
3830 * than INITIALIZING or RUNNING state, fail. This is to prevent
3831 * allocations in an improper driver state
3834 atomic_inc(&adapter
->pending_allocations
);
3836 if(BufferType
!= SXG_BUFFER_TYPE_SGL
)
3837 Buffer
= pci_alloc_consistent(adapter
->pcidev
, Size
, &pBuffer
);
3839 Buffer
= kzalloc(Size
, GFP_ATOMIC
);
3840 pBuffer
= (dma_addr_t
)NULL
;
3842 if (Buffer
== NULL
) {
3844 * Decrement the AllocationsPending count while holding
3845 * the lock. Pause processing relies on this
3847 atomic_dec(&adapter
->pending_allocations
);
3848 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "AlcMemF1",
3849 adapter
, Size
, BufferType
, 0);
3850 return (STATUS_RESOURCES
);
3852 status
= sxg_allocate_complete(adapter
, Buffer
, pBuffer
, Size
, BufferType
);
3854 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "XAlocMem",
3855 adapter
, Size
, BufferType
, status
);
3860 * sxg_allocate_rcvblock_complete - Complete a receive descriptor
3864 * adapter - A pointer to our adapter structure
3865 * RcvBlock - receive block virtual address
3866 * PhysicalAddress - Physical address
3867 * Length - Memory length
3871 static int sxg_allocate_rcvblock_complete(struct adapter_t
*adapter
,
3873 dma_addr_t PhysicalAddress
,
3877 u32 BufferSize
= adapter
->ReceiveBufferSize
;
3879 void *temp_RcvBlock
;
3880 struct sxg_rcv_block_hdr
*RcvBlockHdr
;
3881 struct sxg_rcv_data_buffer_hdr
*RcvDataBufferHdr
;
3882 struct sxg_rcv_descriptor_block
*RcvDescriptorBlock
;
3883 struct sxg_rcv_descriptor_block_hdr
*RcvDescriptorBlockHdr
;
3885 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "AlRcvBlk",
3886 adapter
, RcvBlock
, Length
, 0);
3887 if (RcvBlock
== NULL
) {
3890 memset(RcvBlock
, 0, Length
);
3891 ASSERT((BufferSize
== SXG_RCV_DATA_BUFFER_SIZE
) ||
3892 (BufferSize
== SXG_RCV_JUMBO_BUFFER_SIZE
));
3893 ASSERT(Length
== SXG_RCV_BLOCK_SIZE(SXG_RCV_DATA_HDR_SIZE
));
3895 * First, initialize the contained pool of receive data buffers.
3896 * This initialization requires NBL/NB/MDL allocations, if any of them
3897 * fail, free the block and return without queueing the shared memory
3899 //RcvDataBuffer = RcvBlock;
3900 temp_RcvBlock
= RcvBlock
;
3901 for (i
= 0; i
< SXG_RCV_DESCRIPTORS_PER_BLOCK
;
3902 i
++, temp_RcvBlock
+= SXG_RCV_DATA_HDR_SIZE
) {
3903 RcvDataBufferHdr
= (struct sxg_rcv_data_buffer_hdr
*)
3905 /* For FREE macro assertion */
3906 RcvDataBufferHdr
->State
= SXG_BUFFER_UPSTREAM
;
3907 SXG_ALLOCATE_RCV_PACKET(adapter
, RcvDataBufferHdr
, BufferSize
);
3908 if (RcvDataBufferHdr
->SxgDumbRcvPacket
== NULL
)
3914 * Place this entire block of memory on the AllRcvBlocks queue so it
3918 RcvBlockHdr
= (struct sxg_rcv_block_hdr
*) ((unsigned char *)RcvBlock
+
3919 SXG_RCV_BLOCK_HDR_OFFSET(SXG_RCV_DATA_HDR_SIZE
));
3920 RcvBlockHdr
->VirtualAddress
= RcvBlock
;
3921 RcvBlockHdr
->PhysicalAddress
= PhysicalAddress
;
3922 spin_lock(&adapter
->RcvQLock
);
3923 adapter
->AllRcvBlockCount
++;
3924 InsertTailList(&adapter
->AllRcvBlocks
, &RcvBlockHdr
->AllList
);
3925 spin_unlock(&adapter
->RcvQLock
);
3927 /* Now free the contained receive data buffers that we
3928 * initialized above */
3929 temp_RcvBlock
= RcvBlock
;
3930 for (i
= 0, Paddr
= PhysicalAddress
;
3931 i
< SXG_RCV_DESCRIPTORS_PER_BLOCK
;
3932 i
++, Paddr
+= SXG_RCV_DATA_HDR_SIZE
,
3933 temp_RcvBlock
+= SXG_RCV_DATA_HDR_SIZE
) {
3935 (struct sxg_rcv_data_buffer_hdr
*)temp_RcvBlock
;
3936 spin_lock(&adapter
->RcvQLock
);
3937 SXG_FREE_RCV_DATA_BUFFER(adapter
, RcvDataBufferHdr
);
3938 spin_unlock(&adapter
->RcvQLock
);
3941 /* Locate the descriptor block and put it on a separate free queue */
3942 RcvDescriptorBlock
=
3943 (struct sxg_rcv_descriptor_block
*) ((unsigned char *)RcvBlock
+
3944 SXG_RCV_DESCRIPTOR_BLOCK_OFFSET
3945 (SXG_RCV_DATA_HDR_SIZE
));
3946 RcvDescriptorBlockHdr
=
3947 (struct sxg_rcv_descriptor_block_hdr
*) ((unsigned char *)RcvBlock
+
3948 SXG_RCV_DESCRIPTOR_BLOCK_HDR_OFFSET
3949 (SXG_RCV_DATA_HDR_SIZE
));
3950 RcvDescriptorBlockHdr
->VirtualAddress
= RcvDescriptorBlock
;
3951 RcvDescriptorBlockHdr
->PhysicalAddress
= Paddr
;
3952 spin_lock(&adapter
->RcvQLock
);
3953 SXG_FREE_RCV_DESCRIPTOR_BLOCK(adapter
, RcvDescriptorBlockHdr
);
3954 spin_unlock(&adapter
->RcvQLock
);
3955 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "XAlRBlk",
3956 adapter
, RcvBlock
, Length
, 0);
3957 return STATUS_SUCCESS
;
3959 /* Free any allocated resources */
3961 temp_RcvBlock
= RcvBlock
;
3962 for (i
= 0; i
< SXG_RCV_DESCRIPTORS_PER_BLOCK
;
3963 i
++, temp_RcvBlock
+= SXG_RCV_DATA_HDR_SIZE
) {
3965 (struct sxg_rcv_data_buffer_hdr
*)temp_RcvBlock
;
3966 SXG_FREE_RCV_PACKET(RcvDataBufferHdr
);
3968 pci_free_consistent(adapter
->pcidev
,
3969 Length
, RcvBlock
, PhysicalAddress
);
3971 DBG_ERROR("%s: OUT OF RESOURCES\n", __func__
);
3972 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_IMPORTANT
, "RcvAFail",
3973 adapter
, adapter
->FreeRcvBufferCount
,
3974 adapter
->FreeRcvBlockCount
, adapter
->AllRcvBlockCount
);
3975 adapter
->Stats
.NoMem
++;
3976 /* As allocation failed, free all previously allocated blocks..*/
3977 //sxg_free_rcvblocks(adapter);
3979 return STATUS_RESOURCES
;
3983 * sxg_allocate_sgl_buffer_complete - Complete a SGL buffer allocation
3986 * adapter - A pointer to our adapter structure
3987 * SxgSgl - struct sxg_scatter_gather buffer
3988 * PhysicalAddress - Physical address
3989 * Length - Memory length
3993 static void sxg_allocate_sgl_buffer_complete(struct adapter_t
*adapter
,
3994 struct sxg_scatter_gather
*SxgSgl
,
3995 dma_addr_t PhysicalAddress
,
3998 unsigned long sgl_flags
;
3999 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "AlSglCmp",
4000 adapter
, SxgSgl
, Length
, 0);
4001 spin_lock_irqsave(&adapter
->SglQLock
, sgl_flags
);
4002 adapter
->AllSglBufferCount
++;
4003 /* PhysicalAddress; */
4004 SxgSgl
->PhysicalAddress
= PhysicalAddress
;
4005 /* Initialize backpointer once */
4006 SxgSgl
->adapter
= adapter
;
4007 InsertTailList(&adapter
->AllSglBuffers
, &SxgSgl
->AllList
);
4008 spin_unlock_irqrestore(&adapter
->SglQLock
, sgl_flags
);
4009 SxgSgl
->State
= SXG_BUFFER_BUSY
;
4010 SXG_FREE_SGL_BUFFER(adapter
, SxgSgl
, NULL
);
4011 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "XAlSgl",
4012 adapter
, SxgSgl
, Length
, 0);
4016 static int sxg_adapter_set_hwaddr(struct adapter_t
*adapter
)
4019 * DBG_ERROR ("%s ENTER card->config_set[%x] port[%d] physport[%d] \
4020 * funct#[%d]\n", __func__, card->config_set,
4021 * adapter->port, adapter->physport, adapter->functionnumber);
4023 * sxg_dbg_macaddrs(adapter);
4025 /* DBG_ERROR ("%s AFTER copying from config.macinfo into currmacaddr\n",
4029 /* sxg_dbg_macaddrs(adapter); */
4031 struct net_device
* dev
= adapter
->netdev
;
4034 printk("sxg: Dev is Null\n");
4037 DBG_ERROR("%s ENTER (%s)\n", __FUNCTION__
, adapter
->netdev
->name
);
4039 if (netif_running(dev
)) {
4046 if (!(adapter
->currmacaddr
[0] ||
4047 adapter
->currmacaddr
[1] ||
4048 adapter
->currmacaddr
[2] ||
4049 adapter
->currmacaddr
[3] ||
4050 adapter
->currmacaddr
[4] || adapter
->currmacaddr
[5])) {
4051 memcpy(adapter
->currmacaddr
, adapter
->macaddr
, 6);
4053 if (adapter
->netdev
) {
4054 memcpy(adapter
->netdev
->dev_addr
, adapter
->currmacaddr
, 6);
4055 memcpy(adapter
->netdev
->perm_addr
, adapter
->currmacaddr
, 6);
4057 /* DBG_ERROR ("%s EXIT port %d\n", __func__, adapter->port); */
4058 sxg_dbg_macaddrs(adapter
);
4064 static int sxg_mac_set_address(struct net_device
*dev
, void *ptr
)
4066 struct adapter_t
*adapter
= (struct adapter_t
*) netdev_priv(dev
);
4067 struct sockaddr
*addr
= ptr
;
4069 DBG_ERROR("%s ENTER (%s)\n", __func__
, adapter
->netdev
->name
);
4071 if (netif_running(dev
)) {
4077 DBG_ERROR("sxg: %s (%s) curr %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n",
4078 __func__
, adapter
->netdev
->name
, adapter
->currmacaddr
[0],
4079 adapter
->currmacaddr
[1], adapter
->currmacaddr
[2],
4080 adapter
->currmacaddr
[3], adapter
->currmacaddr
[4],
4081 adapter
->currmacaddr
[5]);
4082 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
4083 memcpy(adapter
->currmacaddr
, addr
->sa_data
, dev
->addr_len
);
4084 DBG_ERROR("sxg: %s (%s) new %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n",
4085 __func__
, adapter
->netdev
->name
, adapter
->currmacaddr
[0],
4086 adapter
->currmacaddr
[1], adapter
->currmacaddr
[2],
4087 adapter
->currmacaddr
[3], adapter
->currmacaddr
[4],
4088 adapter
->currmacaddr
[5]);
4090 sxg_config_set(adapter
, TRUE
);
4096 * SXG DRIVER FUNCTIONS (below)
4098 * sxg_initialize_adapter - Initialize adapter
4101 * adapter - A pointer to our adapter structure
4105 static int sxg_initialize_adapter(struct adapter_t
*adapter
)
4107 u32 RssIds
, IsrCount
;
4110 int sxg_rcv_ring_size
= SXG_RCV_RING_SIZE
;
4112 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "InitAdpt",
4115 RssIds
= 1; /* XXXTODO SXG_RSS_CPU_COUNT(adapter); */
4116 IsrCount
= adapter
->msi_enabled
? RssIds
: 1;
4119 * Sanity check SXG_UCODE_REGS structure definition to
4120 * make sure the length is correct
4122 ASSERT(sizeof(struct sxg_ucode_regs
) == SXG_REGISTER_SIZE_PER_CPU
);
4124 /* Disable interrupts */
4125 SXG_DISABLE_ALL_INTERRUPTS(adapter
);
4128 ASSERT((adapter
->FrameSize
== ETHERMAXFRAME
) ||
4129 (adapter
->FrameSize
== JUMBOMAXFRAME
));
4130 WRITE_REG(adapter
->UcodeRegs
[0].LinkMtu
, adapter
->FrameSize
, TRUE
);
4132 /* Set event ring base address and size */
4133 WRITE_REG64(adapter
,
4134 adapter
->UcodeRegs
[0].EventBase
, adapter
->PEventRings
, 0);
4135 WRITE_REG(adapter
->UcodeRegs
[0].EventSize
, EVENT_RING_SIZE
, TRUE
);
4137 /* Per-ISR initialization */
4138 for (i
= 0; i
< IsrCount
; i
++) {
4140 /* Set interrupt status pointer */
4141 Addr
= adapter
->PIsr
+ (i
* sizeof(u32
));
4142 WRITE_REG64(adapter
, adapter
->UcodeRegs
[i
].Isp
, Addr
, i
);
4145 /* XMT ring zero index */
4146 WRITE_REG64(adapter
,
4147 adapter
->UcodeRegs
[0].SPSendIndex
,
4148 adapter
->PXmtRingZeroIndex
, 0);
4150 /* Per-RSS initialization */
4151 for (i
= 0; i
< RssIds
; i
++) {
4152 /* Release all event ring entries to the Microcode */
4153 WRITE_REG(adapter
->UcodeRegs
[i
].EventRelease
, EVENT_RING_SIZE
,
4157 /* Transmit ring base and size */
4158 WRITE_REG64(adapter
,
4159 adapter
->UcodeRegs
[0].XmtBase
, adapter
->PXmtRings
, 0);
4160 WRITE_REG(adapter
->UcodeRegs
[0].XmtSize
, SXG_XMT_RING_SIZE
, TRUE
);
4162 /* Receive ring base and size */
4163 WRITE_REG64(adapter
,
4164 adapter
->UcodeRegs
[0].RcvBase
, adapter
->PRcvRings
, 0);
4165 if (adapter
->JumboEnabled
== TRUE
)
4166 sxg_rcv_ring_size
= SXG_JUMBO_RCV_RING_SIZE
;
4167 WRITE_REG(adapter
->UcodeRegs
[0].RcvSize
, sxg_rcv_ring_size
, TRUE
);
4169 /* Populate the card with receive buffers */
4170 sxg_stock_rcv_buffers(adapter
);
4173 * Initialize checksum offload capabilities. At the moment we always
4174 * enable IP and TCP receive checksums on the card. Depending on the
4175 * checksum configuration specified by the user, we can choose to
4176 * report or ignore the checksum information provided by the card.
4178 WRITE_REG(adapter
->UcodeRegs
[0].ReceiveChecksum
,
4179 SXG_RCV_TCP_CSUM_ENABLED
| SXG_RCV_IP_CSUM_ENABLED
, TRUE
);
4181 adapter
->flags
|= (SXG_RCV_TCP_CSUM_ENABLED
| SXG_RCV_IP_CSUM_ENABLED
);
4183 /* Initialize the MAC, XAUI */
4184 DBG_ERROR("sxg: %s ENTER sxg_initialize_link\n", __func__
);
4185 status
= sxg_initialize_link(adapter
);
4186 DBG_ERROR("sxg: %s EXIT sxg_initialize_link status[%x]\n", __func__
,
4188 if (status
!= STATUS_SUCCESS
) {
4192 * Initialize Dead to FALSE.
4193 * SlicCheckForHang or SlicDumpThread will take it from here.
4195 adapter
->Dead
= FALSE
;
4196 adapter
->PingOutstanding
= FALSE
;
4197 adapter
->XmtFcEnabled
= TRUE
;
4198 adapter
->RcvFcEnabled
= TRUE
;
4200 adapter
->State
= SXG_STATE_RUNNING
;
4202 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "XInit",
4204 return (STATUS_SUCCESS
);
4208 * sxg_fill_descriptor_block - Populate a descriptor block and give it to
4209 * the card. The caller should hold the RcvQLock
4212 * adapter - A pointer to our adapter structure
4213 * RcvDescriptorBlockHdr - Descriptor block to fill
4218 static int sxg_fill_descriptor_block(struct adapter_t
*adapter
,
4219 struct sxg_rcv_descriptor_block_hdr
*RcvDescriptorBlockHdr
)
4222 struct sxg_ring_info
*RcvRingInfo
= &adapter
->RcvRingZeroInfo
;
4223 struct sxg_rcv_data_buffer_hdr
*RcvDataBufferHdr
;
4224 struct sxg_rcv_descriptor_block
*RcvDescriptorBlock
;
4225 struct sxg_cmd
*RingDescriptorCmd
;
4226 struct sxg_rcv_ring
*RingZero
= &adapter
->RcvRings
[0];
4228 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "FilBlk",
4229 adapter
, adapter
->RcvBuffersOnCard
,
4230 adapter
->FreeRcvBufferCount
, adapter
->AllRcvBlockCount
);
4232 ASSERT(RcvDescriptorBlockHdr
);
4235 * If we don't have the resources to fill the descriptor block,
4238 if ((adapter
->FreeRcvBufferCount
< SXG_RCV_DESCRIPTORS_PER_BLOCK
) ||
4239 SXG_RING_FULL(RcvRingInfo
)) {
4240 adapter
->Stats
.NoMem
++;
4241 return (STATUS_FAILURE
);
4243 /* Get a ring descriptor command */
4244 SXG_GET_CMD(RingZero
,
4245 RcvRingInfo
, RingDescriptorCmd
, RcvDescriptorBlockHdr
);
4246 ASSERT(RingDescriptorCmd
);
4247 RcvDescriptorBlockHdr
->State
= SXG_BUFFER_ONCARD
;
4248 RcvDescriptorBlock
= (struct sxg_rcv_descriptor_block
*)
4249 RcvDescriptorBlockHdr
->VirtualAddress
;
4251 /* Fill in the descriptor block */
4252 for (i
= 0; i
< SXG_RCV_DESCRIPTORS_PER_BLOCK
; i
++) {
4253 SXG_GET_RCV_DATA_BUFFER(adapter
, RcvDataBufferHdr
);
4254 ASSERT(RcvDataBufferHdr
);
4255 // ASSERT(RcvDataBufferHdr->SxgDumbRcvPacket);
4256 if (!RcvDataBufferHdr
->SxgDumbRcvPacket
) {
4257 SXG_ALLOCATE_RCV_PACKET(adapter
, RcvDataBufferHdr
,
4258 adapter
->ReceiveBufferSize
);
4259 if(RcvDataBufferHdr
->skb
)
4260 RcvDataBufferHdr
->SxgDumbRcvPacket
=
4261 RcvDataBufferHdr
->skb
;
4265 SXG_REINIATIALIZE_PACKET(RcvDataBufferHdr
->SxgDumbRcvPacket
);
4266 RcvDataBufferHdr
->State
= SXG_BUFFER_ONCARD
;
4267 RcvDescriptorBlock
->Descriptors
[i
].VirtualAddress
=
4268 (void *)RcvDataBufferHdr
;
4270 RcvDescriptorBlock
->Descriptors
[i
].PhysicalAddress
=
4271 RcvDataBufferHdr
->PhysicalAddress
;
4273 /* Add the descriptor block to receive descriptor ring 0 */
4274 RingDescriptorCmd
->Sgl
= RcvDescriptorBlockHdr
->PhysicalAddress
;
4277 * RcvBuffersOnCard is not protected via the receive lock (see
4278 * sxg_process_event_queue) We don't want to grap a lock every time a
4279 * buffer is returned to us, so we use atomic interlocked functions
4282 adapter
->RcvBuffersOnCard
+= SXG_RCV_DESCRIPTORS_PER_BLOCK
;
4284 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "DscBlk",
4285 RcvDescriptorBlockHdr
,
4286 RingDescriptorCmd
, RcvRingInfo
->Head
, RcvRingInfo
->Tail
);
4288 WRITE_REG(adapter
->UcodeRegs
[0].RcvCmd
, 1, true);
4289 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "XFilBlk",
4290 adapter
, adapter
->RcvBuffersOnCard
,
4291 adapter
->FreeRcvBufferCount
, adapter
->AllRcvBlockCount
);
4292 return (STATUS_SUCCESS
);
4294 for (; i
>= 0 ; i
--) {
4295 if (RcvDescriptorBlock
->Descriptors
[i
].VirtualAddress
) {
4296 RcvDataBufferHdr
= (struct sxg_rcv_data_buffer_hdr
*)
4297 RcvDescriptorBlock
->Descriptors
[i
].
4299 RcvDescriptorBlock
->Descriptors
[i
].PhysicalAddress
=
4301 RcvDescriptorBlock
->Descriptors
[i
].VirtualAddress
=NULL
;
4303 SXG_FREE_RCV_DATA_BUFFER(adapter
, RcvDataBufferHdr
);
4305 RcvDescriptorBlockHdr
->State
= SXG_BUFFER_FREE
;
4306 SXG_RETURN_CMD(RingZero
, RcvRingInfo
, RingDescriptorCmd
,
4307 RcvDescriptorBlockHdr
);
4313 * sxg_stock_rcv_buffers - Stock the card with receive buffers
4316 * adapter - A pointer to our adapter structure
4321 static void sxg_stock_rcv_buffers(struct adapter_t
*adapter
)
4323 struct sxg_rcv_descriptor_block_hdr
*RcvDescriptorBlockHdr
;
4324 int sxg_rcv_data_buffers
= SXG_RCV_DATA_BUFFERS
;
4325 int sxg_min_rcv_data_buffers
= SXG_MIN_RCV_DATA_BUFFERS
;
4327 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "StockBuf",
4328 adapter
, adapter
->RcvBuffersOnCard
,
4329 adapter
->FreeRcvBufferCount
, adapter
->AllRcvBlockCount
);
4331 * First, see if we've got less than our minimum threshold of
4332 * receive buffers, there isn't an allocation in progress, and
4333 * we haven't exceeded our maximum.. get another block of buffers
4334 * None of this needs to be SMP safe. It's round numbers.
4336 if (adapter
->JumboEnabled
== TRUE
)
4337 sxg_min_rcv_data_buffers
= SXG_MIN_JUMBO_RCV_DATA_BUFFERS
;
4338 if ((adapter
->FreeRcvBufferCount
< sxg_min_rcv_data_buffers
) &&
4339 (adapter
->AllRcvBlockCount
< SXG_MAX_RCV_BLOCKS
) &&
4340 (atomic_read(&adapter
->pending_allocations
) == 0)) {
4341 sxg_allocate_buffer_memory(adapter
,
4343 (SXG_RCV_DATA_HDR_SIZE
),
4344 SXG_BUFFER_TYPE_RCV
);
4346 /* Now grab the RcvQLock lock and proceed */
4347 spin_lock(&adapter
->RcvQLock
);
4348 if (adapter
->JumboEnabled
)
4349 sxg_rcv_data_buffers
= SXG_JUMBO_RCV_DATA_BUFFERS
;
4350 while (adapter
->RcvBuffersOnCard
< sxg_rcv_data_buffers
) {
4351 struct list_entry
*_ple
;
4353 /* Get a descriptor block */
4354 RcvDescriptorBlockHdr
= NULL
;
4355 if (adapter
->FreeRcvBlockCount
) {
4356 _ple
= RemoveHeadList(&adapter
->FreeRcvBlocks
);
4357 RcvDescriptorBlockHdr
=
4358 container_of(_ple
, struct sxg_rcv_descriptor_block_hdr
,
4360 adapter
->FreeRcvBlockCount
--;
4361 RcvDescriptorBlockHdr
->State
= SXG_BUFFER_BUSY
;
4364 if (RcvDescriptorBlockHdr
== NULL
) {
4366 adapter
->Stats
.NoMem
++;
4369 /* Fill in the descriptor block and give it to the card */
4370 if (sxg_fill_descriptor_block(adapter
, RcvDescriptorBlockHdr
) ==
4372 /* Free the descriptor block */
4373 SXG_FREE_RCV_DESCRIPTOR_BLOCK(adapter
,
4374 RcvDescriptorBlockHdr
);
4378 spin_unlock(&adapter
->RcvQLock
);
4379 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "XFilBlks",
4380 adapter
, adapter
->RcvBuffersOnCard
,
4381 adapter
->FreeRcvBufferCount
, adapter
->AllRcvBlockCount
);
4385 * sxg_complete_descriptor_blocks - Return descriptor blocks that have been
4386 * completed by the microcode
4389 * adapter - A pointer to our adapter structure
4390 * Index - Where the microcode is up to
4395 static void sxg_complete_descriptor_blocks(struct adapter_t
*adapter
,
4396 unsigned char Index
)
4398 struct sxg_rcv_ring
*RingZero
= &adapter
->RcvRings
[0];
4399 struct sxg_ring_info
*RcvRingInfo
= &adapter
->RcvRingZeroInfo
;
4400 struct sxg_rcv_descriptor_block_hdr
*RcvDescriptorBlockHdr
;
4401 struct sxg_cmd
*RingDescriptorCmd
;
4403 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "CmpRBlks",
4404 adapter
, Index
, RcvRingInfo
->Head
, RcvRingInfo
->Tail
);
4406 /* Now grab the RcvQLock lock and proceed */
4407 spin_lock(&adapter
->RcvQLock
);
4408 ASSERT(Index
!= RcvRingInfo
->Tail
);
4409 while (sxg_ring_get_forward_diff(RcvRingInfo
, Index
,
4410 RcvRingInfo
->Tail
) > 3) {
4412 * Locate the current Cmd (ring descriptor entry), and
4413 * associated receive descriptor block, and advance
4416 SXG_RETURN_CMD(RingZero
,
4418 RingDescriptorCmd
, RcvDescriptorBlockHdr
);
4419 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "CmpRBlk",
4420 RcvRingInfo
->Head
, RcvRingInfo
->Tail
,
4421 RingDescriptorCmd
, RcvDescriptorBlockHdr
);
4423 /* Clear the SGL field */
4424 RingDescriptorCmd
->Sgl
= 0;
4426 * Attempt to refill it and hand it right back to the
4427 * card. If we fail to refill it, free the descriptor block
4428 * header. The card will be restocked later via the
4429 * RcvBuffersOnCard test
4431 if (sxg_fill_descriptor_block(adapter
,
4432 RcvDescriptorBlockHdr
) == STATUS_FAILURE
)
4433 SXG_FREE_RCV_DESCRIPTOR_BLOCK(adapter
,
4434 RcvDescriptorBlockHdr
);
4436 spin_unlock(&adapter
->RcvQLock
);
4437 SXG_TRACE(TRACE_SXG
, SxgTraceBuffer
, TRACE_NOISY
, "XCRBlks",
4438 adapter
, Index
, RcvRingInfo
->Head
, RcvRingInfo
->Tail
);
4442 * Read the statistics which the card has been maintaining.
4444 void sxg_collect_statistics(struct adapter_t
*adapter
)
4446 if(adapter
->ucode_stats
)
4447 WRITE_REG64(adapter
, adapter
->UcodeRegs
[0].GetUcodeStats
,
4448 adapter
->pucode_stats
, 0);
4449 adapter
->stats
.rx_fifo_errors
= adapter
->ucode_stats
->ERDrops
;
4450 adapter
->stats
.rx_over_errors
= adapter
->ucode_stats
->NBDrops
;
4451 adapter
->stats
.tx_fifo_errors
= adapter
->ucode_stats
->XDrops
;
4454 static struct net_device_stats
*sxg_get_stats(struct net_device
* dev
)
4456 struct adapter_t
*adapter
= netdev_priv(dev
);
4458 sxg_collect_statistics(adapter
);
4459 return (&adapter
->stats
);
4462 static void sxg_watchdog(unsigned long data
)
4464 struct adapter_t
*adapter
= (struct adapter_t
*) data
;
4466 if (adapter
->state
!= ADAPT_DOWN
) {
4467 sxg_link_event(adapter
);
4468 /* Reset the timer */
4469 mod_timer(&adapter
->watchdog_timer
, round_jiffies(jiffies
+ 2 * HZ
));
4473 static void sxg_update_link_status (struct work_struct
*work
)
4475 struct adapter_t
*adapter
= (struct adapter_t
*)container_of
4476 (work
, struct adapter_t
, update_link_status
);
4477 if (likely(adapter
->link_status_changed
)) {
4478 sxg_link_event(adapter
);
4479 adapter
->link_status_changed
= 0;
4483 static struct pci_driver sxg_driver
= {
4484 .name
= sxg_driver_name
,
4485 .id_table
= sxg_pci_tbl
,
4486 .probe
= sxg_entry_probe
,
4487 .remove
= sxg_entry_remove
,
4488 #if SXG_POWER_MANAGEMENT_ENABLED
4489 .suspend
= sxgpm_suspend
,
4490 .resume
= sxgpm_resume
,
4492 /* .shutdown = slic_shutdown, MOOK_INVESTIGATE */
4495 static int __init
sxg_module_init(void)
4502 return pci_register_driver(&sxg_driver
);
4505 static void __exit
sxg_module_cleanup(void)
4507 pci_unregister_driver(&sxg_driver
);
4510 module_init(sxg_module_init
);
4511 module_exit(sxg_module_cleanup
);