drivers/staging/vt6655/mac.c

   1 /*
   2  * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  *
  20  * File: mac.c
  21  *
  22  * Purpose:  MAC routines
  23  *
  24  * Author: Tevin Chen
  25  *
  26  * Date: May 21, 1996
  27  *
  28  * Functions:
  29  *      MACbIsRegBitsOn - Test if All test Bits On
  30  *      MACbIsRegBitsOff - Test if All test Bits Off
  31  *      MACbIsIntDisable - Test if MAC interrupt disable
  32  *      MACvSetShortRetryLimit - Set 802.11 Short Retry limit
  33  *      MACvSetLongRetryLimit - Set 802.11 Long Retry limit
  34  *      MACvSetLoopbackMode - Set MAC Loopback Mode
  35  *      MACvSaveContext - Save Context of MAC Registers
  36  *      MACvRestoreContext - Restore Context of MAC Registers
  37  *      MACbSoftwareReset - Software Reset MAC
  38  *      MACbSafeRxOff - Turn Off MAC Rx
  39  *      MACbSafeTxOff - Turn Off MAC Tx
  40  *      MACbSafeStop - Stop MAC function
  41  *      MACbShutdown - Shut down MAC
  42  *      MACvInitialize - Initialize MAC
  43  *      MACvSetCurrRxDescAddr - Set Rx Descriptors Address
  44  *      MACvSetCurrTx0DescAddr - Set Tx0 Descriptors Address
  45  *      MACvSetCurrTx1DescAddr - Set Tx1 Descriptors Address
  46  *      MACvTimer0MicroSDelay - Micro Second Delay Loop by MAC
  47  *
  48  * Revision History:
  49  *      08-22-2003 Kyle Hsu     :  Porting MAC functions from sim53
  50  *      09-03-2003 Bryan YC Fan :  Add MACvClearBusSusInd()& MACvEnableBusSusEn()
  51  *      09-18-2003 Jerry Chen   :  Add MACvSetKeyEntry & MACvDisableKeyEntry
  52  *
  53  */
  54
  55 #include "tmacro.h"
  56 #include "mac.h"
  57
  58 /*
  59  * Description:
  60  *      Test if all test bits on
  61  *
  62  * Parameters:
  63  *  In:
  64  *      io_base    - Base Address for MAC
  65  *      byRegOfs    - Offset of MAC Register
  66  *      byTestBits  - Test bits
  67  *  Out:
  68  *      none
  69  *
  70  * Return Value: true if all test bits On; otherwise false
  71  *
  72  */
  73 bool MACbIsRegBitsOn(struct vnt_private *priv, unsigned char byRegOfs,
  74                      unsigned char byTestBits)
  75 {
  76         void __iomem *io_base = priv->PortOffset;
  77
  78         return (ioread8(io_base + byRegOfs) & byTestBits) == byTestBits;
  79 }
  80
  81 /*
  82  * Description:
  83  *      Test if all test bits off
  84  *
  85  * Parameters:
  86  *  In:
  87  *      io_base    - Base Address for MAC
  88  *      byRegOfs    - Offset of MAC Register
  89  *      byTestBits  - Test bits
  90  *  Out:
  91  *      none
  92  *
  93  * Return Value: true if all test bits Off; otherwise false
  94  *
  95  */
  96 bool MACbIsRegBitsOff(struct vnt_private *priv, unsigned char byRegOfs,
  97                       unsigned char byTestBits)
  98 {
  99         void __iomem *io_base = priv->PortOffset;
 100
 101         return !(ioread8(io_base + byRegOfs) & byTestBits);
 102 }
 103
 104 /*
 105  * Description:
 106  *      Test if MAC interrupt disable
 107  *
 108  * Parameters:
 109  *  In:
 110  *      io_base    - Base Address for MAC
 111  *  Out:
 112  *      none
 113  *
 114  * Return Value: true if interrupt is disable; otherwise false
 115  *
 116  */
 117 bool MACbIsIntDisable(struct vnt_private *priv)
 118 {
 119         void __iomem *io_base = priv->PortOffset;
 120
 121         if (ioread32(io_base + MAC_REG_IMR))
 122                 return false;
 123
 124         return true;
 125 }
 126
 127 /*
 128  * Description:
 129  *      Set 802.11 Short Retry Limit
 130  *
 131  * Parameters:
 132  *  In:
 133  *      io_base    - Base Address for MAC
 134  *      byRetryLimit- Retry Limit
 135  *  Out:
 136  *      none
 137  *
 138  * Return Value: none
 139  *
 140  */
 141 void MACvSetShortRetryLimit(struct vnt_private *priv, unsigned char byRetryLimit)
 142 {
 143         void __iomem *io_base = priv->PortOffset;
 144         /* set SRT */
 145         iowrite8(byRetryLimit, io_base + MAC_REG_SRT);
 146 }
 147
 148
 149 /*
 150  * Description:
 151  *      Set 802.11 Long Retry Limit
 152  *
 153  * Parameters:
 154  *  In:
 155  *      io_base    - Base Address for MAC
 156  *      byRetryLimit- Retry Limit
 157  *  Out:
 158  *      none
 159  *
 160  * Return Value: none
 161  *
 162  */
 163 void MACvSetLongRetryLimit(struct vnt_private *priv, unsigned char byRetryLimit)
 164 {
 165         void __iomem *io_base = priv->PortOffset;
 166         /* set LRT */
 167         iowrite8(byRetryLimit, io_base + MAC_REG_LRT);
 168 }
 169
 170 /*
 171  * Description:
 172  *      Set MAC Loopback mode
 173  *
 174  * Parameters:
 175  *  In:
 176  *      io_base        - Base Address for MAC
 177  *      byLoopbackMode  - Loopback Mode
 178  *  Out:
 179  *      none
 180  *
 181  * Return Value: none
 182  *
 183  */
 184 void MACvSetLoopbackMode(struct vnt_private *priv, unsigned char byLoopbackMode)
 185 {
 186         void __iomem *io_base = priv->PortOffset;
 187
 188         byLoopbackMode <<= 6;
 189         /* set TCR */
 190         iowrite8((ioread8(io_base + MAC_REG_TEST) & 0x3f) | byLoopbackMode,
 191                  io_base + MAC_REG_TEST);
 192 }
 193
 194 /*
 195  * Description:
 196  *      Save MAC registers to context buffer
 197  *
 198  * Parameters:
 199  *  In:
 200  *      io_base    - Base Address for MAC
 201  *  Out:
 202  *      cxt_buf   - Context buffer
 203  *
 204  * Return Value: none
 205  *
 206  */
 207 void MACvSaveContext(struct vnt_private *priv, unsigned char *cxt_buf)
 208 {
 209         void __iomem *io_base = priv->PortOffset;
 210
 211         /* read page0 register */
 212         memcpy_fromio(cxt_buf, io_base, MAC_MAX_CONTEXT_SIZE_PAGE0);
 213
 214         MACvSelectPage1(io_base);
 215
 216         /* read page1 register */
 217         memcpy_fromio(cxt_buf + MAC_MAX_CONTEXT_SIZE_PAGE0, io_base,
 218                       MAC_MAX_CONTEXT_SIZE_PAGE1);
 219
 220         MACvSelectPage0(io_base);
 221 }
 222
 223 /*
 224  * Description:
 225  *      Restore MAC registers from context buffer
 226  *
 227  * Parameters:
 228  *  In:
 229  *      io_base    - Base Address for MAC
 230  *      cxt_buf   - Context buffer
 231  *  Out:
 232  *      none
 233  *
 234  * Return Value: none
 235  *
 236  */
 237 void MACvRestoreContext(struct vnt_private *priv, unsigned char *cxt_buf)
 238 {
 239         void __iomem *io_base = priv->PortOffset;
 240
 241         MACvSelectPage1(io_base);
 242         /* restore page1 */
 243         memcpy_toio(io_base, cxt_buf + MAC_MAX_CONTEXT_SIZE_PAGE0,
 244                     MAC_MAX_CONTEXT_SIZE_PAGE1);
 245
 246         MACvSelectPage0(io_base);
 247
 248         /* restore RCR,TCR,IMR... */
 249         memcpy_toio(io_base + MAC_REG_RCR, cxt_buf + MAC_REG_RCR,
 250                     MAC_REG_ISR - MAC_REG_RCR);
 251
 252         /* restore MAC Config. */
 253         memcpy_toio(io_base + MAC_REG_LRT, cxt_buf + MAC_REG_LRT,
 254                     MAC_REG_PAGE1SEL - MAC_REG_LRT);
 255
 256         iowrite8(*(cxt_buf + MAC_REG_CFG), io_base + MAC_REG_CFG);
 257
 258         /* restore PS Config. */
 259         memcpy_toio(io_base + MAC_REG_PSCFG, cxt_buf + MAC_REG_PSCFG,
 260                     MAC_REG_BBREGCTL - MAC_REG_PSCFG);
 261
 262         /* restore CURR_RX_DESC_ADDR, CURR_TX_DESC_ADDR */
 263         iowrite32(*(u32 *)(cxt_buf + MAC_REG_TXDMAPTR0),
 264                   io_base + MAC_REG_TXDMAPTR0);
 265         iowrite32(*(u32 *)(cxt_buf + MAC_REG_AC0DMAPTR),
 266                   io_base + MAC_REG_AC0DMAPTR);
 267         iowrite32(*(u32 *)(cxt_buf + MAC_REG_BCNDMAPTR),
 268                   io_base + MAC_REG_BCNDMAPTR);
 269         iowrite32(*(u32 *)(cxt_buf + MAC_REG_RXDMAPTR0),
 270                   io_base + MAC_REG_RXDMAPTR0);
 271         iowrite32(*(u32 *)(cxt_buf + MAC_REG_RXDMAPTR1),
 272                   io_base + MAC_REG_RXDMAPTR1);
 273 }
 274
 275 /*
 276  * Description:
 277  *      Software Reset MAC
 278  *
 279  * Parameters:
 280  *  In:
 281  *      io_base    - Base Address for MAC
 282  *  Out:
 283  *      none
 284  *
 285  * Return Value: true if Reset Success; otherwise false
 286  *
 287  */
 288 bool MACbSoftwareReset(struct vnt_private *priv)
 289 {
 290         void __iomem *io_base = priv->PortOffset;
 291         unsigned short ww;
 292
 293         /* turn on HOSTCR_SOFTRST, just write 0x01 to reset */
 294         iowrite8(0x01, io_base + MAC_REG_HOSTCR);
 295
 296         for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
 297                 if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_SOFTRST))
 298                         break;
 299         }
 300         if (ww == W_MAX_TIMEOUT)
 301                 return false;
 302         return true;
 303 }
 304
 305 /*
 306  * Description:
 307  *      save some important register's value, then do reset, then restore register's value
 308  *
 309  * Parameters:
 310  *  In:
 311  *      io_base    - Base Address for MAC
 312  *  Out:
 313  *      none
 314  *
 315  * Return Value: true if success; otherwise false
 316  *
 317  */
 318 bool MACbSafeSoftwareReset(struct vnt_private *priv)
 319 {
 320         unsigned char abyTmpRegData[MAC_MAX_CONTEXT_SIZE_PAGE0+MAC_MAX_CONTEXT_SIZE_PAGE1];
 321         bool bRetVal;
 322
 323         /* PATCH....
 324          * save some important register's value, then do
 325          * reset, then restore register's value
 326          */
 327         /* save MAC context */
 328         MACvSaveContext(priv, abyTmpRegData);
 329         /* do reset */
 330         bRetVal = MACbSoftwareReset(priv);
 331         /* restore MAC context, except CR0 */
 332         MACvRestoreContext(priv, abyTmpRegData);
 333
 334         return bRetVal;
 335 }
 336
 337 /*
 338  * Description:
 339  *      Turn Off MAC Rx
 340  *
 341  * Parameters:
 342  *  In:
 343  *      io_base    - Base Address for MAC
 344  *  Out:
 345  *      none
 346  *
 347  * Return Value: true if success; otherwise false
 348  *
 349  */
 350 bool MACbSafeRxOff(struct vnt_private *priv)
 351 {
 352         void __iomem *io_base = priv->PortOffset;
 353         unsigned short ww;
 354
 355         /* turn off wow temp for turn off Rx safely */
 356
 357         /* Clear RX DMA0,1 */
 358         iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL0);
 359         iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL1);
 360         for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
 361                 if (!(ioread32(io_base + MAC_REG_RXDMACTL0) & DMACTL_RUN))
 362                         break;
 363         }
 364         if (ww == W_MAX_TIMEOUT) {
 365                 pr_debug(" DBG_PORT80(0x10)\n");
 366                 return false;
 367         }
 368         for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
 369                 if (!(ioread32(io_base + MAC_REG_RXDMACTL1) & DMACTL_RUN))
 370                         break;
 371         }
 372         if (ww == W_MAX_TIMEOUT) {
 373                 pr_debug(" DBG_PORT80(0x11)\n");
 374                 return false;
 375         }
 376
 377         /* try to safe shutdown RX */
 378         MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_RXON);
 379         /* W_MAX_TIMEOUT is the timeout period */
 380         for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
 381                 if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_RXONST))
 382                         break;
 383         }
 384         if (ww == W_MAX_TIMEOUT) {
 385                 pr_debug(" DBG_PORT80(0x12)\n");
 386                 return false;
 387         }
 388         return true;
 389 }
 390
 391 /*
 392  * Description:
 393  *      Turn Off MAC Tx
 394  *
 395  * Parameters:
 396  *  In:
 397  *      io_base    - Base Address for MAC
 398  *  Out:
 399  *      none
 400  *
 401  * Return Value: true if success; otherwise false
 402  *
 403  */
 404 bool MACbSafeTxOff(struct vnt_private *priv)
 405 {
 406         void __iomem *io_base = priv->PortOffset;
 407         unsigned short ww;
 408
 409         /* Clear TX DMA */
 410         /* Tx0 */
 411         iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_TXDMACTL0);
 412         /* AC0 */
 413         iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_AC0DMACTL);
 414
 415         for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
 416                 if (!(ioread32(io_base + MAC_REG_TXDMACTL0) & DMACTL_RUN))
 417                         break;
 418         }
 419         if (ww == W_MAX_TIMEOUT) {
 420                 pr_debug(" DBG_PORT80(0x20)\n");
 421                 return false;
 422         }
 423         for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
 424                 if (!(ioread32(io_base + MAC_REG_AC0DMACTL) & DMACTL_RUN))
 425                         break;
 426         }
 427         if (ww == W_MAX_TIMEOUT) {
 428                 pr_debug(" DBG_PORT80(0x21)\n");
 429                 return false;
 430         }
 431
 432         /* try to safe shutdown TX */
 433         MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_TXON);
 434
 435         /* W_MAX_TIMEOUT is the timeout period */
 436         for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
 437                 if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_TXONST))
 438                         break;
 439         }
 440         if (ww == W_MAX_TIMEOUT) {
 441                 pr_debug(" DBG_PORT80(0x24)\n");
 442                 return false;
 443         }
 444         return true;
 445 }
 446
 447 /*
 448  * Description:
 449  *      Stop MAC function
 450  *
 451  * Parameters:
 452  *  In:
 453  *      io_base    - Base Address for MAC
 454  *  Out:
 455  *      none
 456  *
 457  * Return Value: true if success; otherwise false
 458  *
 459  */
 460 bool MACbSafeStop(struct vnt_private *priv)
 461 {
 462         void __iomem *io_base = priv->PortOffset;
 463
 464         MACvRegBitsOff(io_base, MAC_REG_TCR, TCR_AUTOBCNTX);
 465
 466         if (!MACbSafeRxOff(priv)) {
 467                 pr_debug(" MACbSafeRxOff == false)\n");
 468                 MACbSafeSoftwareReset(priv);
 469                 return false;
 470         }
 471         if (!MACbSafeTxOff(priv)) {
 472                 pr_debug(" MACbSafeTxOff == false)\n");
 473                 MACbSafeSoftwareReset(priv);
 474                 return false;
 475         }
 476
 477         MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_MACEN);
 478
 479         return true;
 480 }
 481
 482 /*
 483  * Description:
 484  *      Shut Down MAC
 485  *
 486  * Parameters:
 487  *  In:
 488  *      io_base    - Base Address for MAC
 489  *  Out:
 490  *      none
 491  *
 492  * Return Value: true if success; otherwise false
 493  *
 494  */
 495 bool MACbShutdown(struct vnt_private *priv)
 496 {
 497         void __iomem *io_base = priv->PortOffset;
 498         /* disable MAC IMR */
 499         MACvIntDisable(io_base);
 500         MACvSetLoopbackMode(priv, MAC_LB_INTERNAL);
 501         /* stop the adapter */
 502         if (!MACbSafeStop(priv)) {
 503                 MACvSetLoopbackMode(priv, MAC_LB_NONE);
 504                 return false;
 505         }
 506         MACvSetLoopbackMode(priv, MAC_LB_NONE);
 507         return true;
 508 }
 509
 510 /*
 511  * Description:
 512  *      Initialize MAC
 513  *
 514  * Parameters:
 515  *  In:
 516  *      io_base    - Base Address for MAC
 517  *  Out:
 518  *      none
 519  *
 520  * Return Value: none
 521  *
 522  */
 523 void MACvInitialize(struct vnt_private *priv)
 524 {
 525         void __iomem *io_base = priv->PortOffset;
 526         /* clear sticky bits */
 527         MACvClearStckDS(io_base);
 528         /* disable force PME-enable */
 529         iowrite8(PME_OVR, io_base + MAC_REG_PMC1);
 530         /* only 3253 A */
 531
 532         /* do reset */
 533         MACbSoftwareReset(priv);
 534
 535         /* reset TSF counter */
 536         iowrite8(TFTCTL_TSFCNTRST, io_base + MAC_REG_TFTCTL);
 537         /* enable TSF counter */
 538         iowrite8(TFTCTL_TSFCNTREN, io_base + MAC_REG_TFTCTL);
 539 }
 540
 541 /*
 542  * Description:
 543  *      Set the chip with current rx descriptor address
 544  *
 545  * Parameters:
 546  *  In:
 547  *      io_base        - Base Address for MAC
 548  *      curr_desc_addr  - Descriptor Address
 549  *  Out:
 550  *      none
 551  *
 552  * Return Value: none
 553  *
 554  */
 555 void MACvSetCurrRx0DescAddr(struct vnt_private *priv, u32 curr_desc_addr)
 556 {
 557         void __iomem *io_base = priv->PortOffset;
 558         unsigned short ww;
 559         unsigned char org_dma_ctl;
 560
 561         org_dma_ctl = ioread8(io_base + MAC_REG_RXDMACTL0);
 562         if (org_dma_ctl & DMACTL_RUN)
 563                 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL0 + 2);
 564
 565         for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
 566                 if (!(ioread8(io_base + MAC_REG_RXDMACTL0) & DMACTL_RUN))
 567                         break;
 568         }
 569
 570         iowrite32(curr_desc_addr, io_base + MAC_REG_RXDMAPTR0);
 571         if (org_dma_ctl & DMACTL_RUN)
 572                 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL0);
 573 }
 574
 575 /*
 576  * Description:
 577  *      Set the chip with current rx descriptor address
 578  *
 579  * Parameters:
 580  *  In:
 581  *      io_base        - Base Address for MAC
 582  *      curr_desc_addr  - Descriptor Address
 583  *  Out:
 584  *      none
 585  *
 586  * Return Value: none
 587  *
 588  */
 589 void MACvSetCurrRx1DescAddr(struct vnt_private *priv, u32 curr_desc_addr)
 590 {
 591         void __iomem *io_base = priv->PortOffset;
 592         unsigned short ww;
 593         unsigned char org_dma_ctl;
 594
 595         org_dma_ctl = ioread8(io_base + MAC_REG_RXDMACTL1);
 596         if (org_dma_ctl & DMACTL_RUN)
 597                 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL1 + 2);
 598
 599         for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
 600                 if (!(ioread8(io_base + MAC_REG_RXDMACTL1) & DMACTL_RUN))
 601                         break;
 602         }
 603
 604         iowrite32(curr_desc_addr, io_base + MAC_REG_RXDMAPTR1);
 605         if (org_dma_ctl & DMACTL_RUN)
 606                 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL1);
 607
 608 }
 609
 610 /*
 611  * Description:
 612  *      Set the chip with current tx0 descriptor address
 613  *
 614  * Parameters:
 615  *  In:
 616  *      io_base        - Base Address for MAC
 617  *      curr_desc_addr  - Descriptor Address
 618  *  Out:
 619  *      none
 620  *
 621  * Return Value: none
 622  *
 623  */
 624 void MACvSetCurrTx0DescAddrEx(struct vnt_private *priv,
 625                               u32 curr_desc_addr)
 626 {
 627         void __iomem *io_base = priv->PortOffset;
 628         unsigned short ww;
 629         unsigned char org_dma_ctl;
 630
 631         org_dma_ctl = ioread8(io_base + MAC_REG_TXDMACTL0);
 632         if (org_dma_ctl & DMACTL_RUN)
 633                 iowrite8(DMACTL_RUN, io_base + MAC_REG_TXDMACTL0 + 2);
 634
 635         for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
 636                 if (!(ioread8(io_base + MAC_REG_TXDMACTL0) & DMACTL_RUN))
 637                         break;
 638         }
 639
 640         iowrite32(curr_desc_addr, io_base + MAC_REG_TXDMAPTR0);
 641         if (org_dma_ctl & DMACTL_RUN)
 642                 iowrite8(DMACTL_RUN, io_base + MAC_REG_TXDMACTL0);
 643 }
 644
 645 /*
 646  * Description:
 647  *      Set the chip with current AC0 descriptor address
 648  *
 649  * Parameters:
 650  *  In:
 651  *      io_base        - Base Address for MAC
 652  *      curr_desc_addr  - Descriptor Address
 653  *  Out:
 654  *      none
 655  *
 656  * Return Value: none
 657  *
 658  */
 659 /* TxDMA1 = AC0DMA */
 660 void MACvSetCurrAC0DescAddrEx(struct vnt_private *priv,
 661                               u32 curr_desc_addr)
 662 {
 663         void __iomem *io_base = priv->PortOffset;
 664         unsigned short ww;
 665         unsigned char org_dma_ctl;
 666
 667         org_dma_ctl = ioread8(io_base + MAC_REG_AC0DMACTL);
 668         if (org_dma_ctl & DMACTL_RUN)
 669                 iowrite8(DMACTL_RUN, io_base + MAC_REG_AC0DMACTL + 2);
 670
 671         for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
 672                 if (!(ioread8(io_base + MAC_REG_AC0DMACTL) & DMACTL_RUN))
 673                         break;
 674         }
 675         if (ww == W_MAX_TIMEOUT)
 676                 pr_debug(" DBG_PORT80(0x26)\n");
 677         iowrite32(curr_desc_addr, io_base + MAC_REG_AC0DMAPTR);
 678         if (org_dma_ctl & DMACTL_RUN)
 679                 iowrite8(DMACTL_RUN, io_base + MAC_REG_AC0DMACTL);
 680 }
 681
 682 void MACvSetCurrTXDescAddr(int iTxType, struct vnt_private *priv,
 683                            u32 curr_desc_addr)
 684 {
 685         if (iTxType == TYPE_AC0DMA)
 686                 MACvSetCurrAC0DescAddrEx(priv, curr_desc_addr);
 687         else if (iTxType == TYPE_TXDMA0)
 688                 MACvSetCurrTx0DescAddrEx(priv, curr_desc_addr);
 689 }
 690
 691 /*
 692  * Description:
 693  *      Micro Second Delay via MAC
 694  *
 695  * Parameters:
 696  *  In:
 697  *      io_base    - Base Address for MAC
 698  *      uDelay      - Delay time (timer resolution is 4 us)
 699  *  Out:
 700  *      none
 701  *
 702  * Return Value: none
 703  *
 704  */
 705 void MACvTimer0MicroSDelay(struct vnt_private *priv, unsigned int uDelay)
 706 {
 707         void __iomem *io_base = priv->PortOffset;
 708         unsigned char byValue;
 709         unsigned int uu, ii;
 710
 711         iowrite8(0, io_base + MAC_REG_TMCTL0);
 712         iowrite32(uDelay, io_base + MAC_REG_TMDATA0);
 713         iowrite8((TMCTL_TMD | TMCTL_TE), io_base + MAC_REG_TMCTL0);
 714         for (ii = 0; ii < 66; ii++) {  /* assume max PCI clock is 66Mhz */
 715                 for (uu = 0; uu < uDelay; uu++) {
 716                         byValue = ioread8(io_base + MAC_REG_TMCTL0);
 717                         if ((byValue == 0) ||
 718                             (byValue & TMCTL_TSUSP)) {
 719                                 iowrite8(0, io_base + MAC_REG_TMCTL0);
 720                                 return;
 721                         }
 722                 }
 723         }
 724         iowrite8(0, io_base + MAC_REG_TMCTL0);
 725 }
 726
 727 /*
 728  * Description:
 729  *      Micro Second One shot timer via MAC
 730  *
 731  * Parameters:
 732  *  In:
 733  *      io_base    - Base Address for MAC
 734  *      uDelay      - Delay time
 735  *  Out:
 736  *      none
 737  *
 738  * Return Value: none
 739  *
 740  */
 741 void MACvOneShotTimer1MicroSec(struct vnt_private *priv, unsigned int uDelayTime)
 742 {
 743         void __iomem *io_base = priv->PortOffset;
 744
 745         iowrite8(0, io_base + MAC_REG_TMCTL1);
 746         iowrite32(uDelayTime, io_base + MAC_REG_TMDATA1);
 747         iowrite8((TMCTL_TMD | TMCTL_TE), io_base + MAC_REG_TMCTL1);
 748 }
 749
 750 void MACvSetMISCFifo(struct vnt_private *priv, unsigned short wOffset,
 751                      u32 dwData)
 752 {
 753         void __iomem *io_base = priv->PortOffset;
 754
 755         if (wOffset > 273)
 756                 return;
 757         iowrite16(wOffset, io_base + MAC_REG_MISCFFNDEX);
 758         iowrite32(dwData, io_base + MAC_REG_MISCFFDATA);
 759         iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
 760 }
 761
 762 bool MACbPSWakeup(struct vnt_private *priv)
 763 {
 764         void __iomem *io_base = priv->PortOffset;
 765         unsigned int ww;
 766         /* Read PSCTL */
 767         if (MACbIsRegBitsOff(priv, MAC_REG_PSCTL, PSCTL_PS))
 768                 return true;
 769
 770         /* Disable PS */
 771         MACvRegBitsOff(io_base, MAC_REG_PSCTL, PSCTL_PSEN);
 772
 773         /* Check if SyncFlushOK */
 774         for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
 775                 if (ioread8(io_base + MAC_REG_PSCTL) & PSCTL_WAKEDONE)
 776                         break;
 777         }
 778         if (ww == W_MAX_TIMEOUT) {
 779                 pr_debug(" DBG_PORT80(0x33)\n");
 780                 return false;
 781         }
 782         return true;
 783 }
 784
 785 /*
 786  * Description:
 787  *      Set the Key by MISCFIFO
 788  *
 789  * Parameters:
 790  *  In:
 791  *      io_base        - Base Address for MAC
 792  *
 793  *  Out:
 794  *      none
 795  *
 796  * Return Value: none
 797  *
 798  */
 799
 800 void MACvSetKeyEntry(struct vnt_private *priv, unsigned short wKeyCtl,
 801                      unsigned int uEntryIdx, unsigned int uKeyIdx,
 802                      unsigned char *pbyAddr, u32 *pdwKey,
 803                      unsigned char byLocalID)
 804 {
 805         void __iomem *io_base = priv->PortOffset;
 806         unsigned short wOffset;
 807         u32 dwData;
 808         int     ii;
 809
 810         if (byLocalID <= 1)
 811                 return;
 812
 813         pr_debug("MACvSetKeyEntry\n");
 814         wOffset = MISCFIFO_KEYETRY0;
 815         wOffset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE);
 816
 817         dwData = 0;
 818         dwData |= wKeyCtl;
 819         dwData <<= 16;
 820         dwData |= MAKEWORD(*(pbyAddr+4), *(pbyAddr+5));
 821         pr_debug("1. wOffset: %d, Data: %X, KeyCtl:%X\n",
 822                  wOffset, dwData, wKeyCtl);
 823
 824         iowrite16(wOffset, io_base + MAC_REG_MISCFFNDEX);
 825         iowrite32(dwData, io_base + MAC_REG_MISCFFDATA);
 826         iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
 827         wOffset++;
 828
 829         dwData = 0;
 830         dwData |= *(pbyAddr+3);
 831         dwData <<= 8;
 832         dwData |= *(pbyAddr+2);
 833         dwData <<= 8;
 834         dwData |= *(pbyAddr+1);
 835         dwData <<= 8;
 836         dwData |= *(pbyAddr+0);
 837         pr_debug("2. wOffset: %d, Data: %X\n", wOffset, dwData);
 838
 839         iowrite16(wOffset, io_base + MAC_REG_MISCFFNDEX);
 840         iowrite32(dwData, io_base + MAC_REG_MISCFFDATA);
 841         iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
 842         wOffset++;
 843
 844         wOffset += (uKeyIdx * 4);
 845         for (ii = 0; ii < 4; ii++) {
 846                 /* always push 128 bits */
 847                 pr_debug("3.(%d) wOffset: %d, Data: %X\n",
 848                          ii, wOffset+ii, *pdwKey);
 849                 iowrite16(wOffset + ii, io_base + MAC_REG_MISCFFNDEX);
 850                 iowrite32(*pdwKey++, io_base + MAC_REG_MISCFFDATA);
 851                 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
 852         }
 853 }
 854
 855 /*
 856  * Description:
 857  *      Disable the Key Entry by MISCFIFO
 858  *
 859  * Parameters:
 860  *  In:
 861  *      io_base        - Base Address for MAC
 862  *
 863  *  Out:
 864  *      none
 865  *
 866  * Return Value: none
 867  *
 868  */
 869 void MACvDisableKeyEntry(struct vnt_private *priv, unsigned int uEntryIdx)
 870 {
 871         void __iomem *io_base = priv->PortOffset;
 872         unsigned short wOffset;
 873
 874         wOffset = MISCFIFO_KEYETRY0;
 875         wOffset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE);
 876
 877         iowrite16(wOffset, io_base + MAC_REG_MISCFFNDEX);
 878         iowrite32(0, io_base + MAC_REG_MISCFFDATA);
 879         iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
 880 }