4 #include "wilc_oswrapper.h"
7 #define ISWILC1000(id) (((id & 0xfffff000) == 0x100000) ? 1 : 0)
10 /********************************************
12 * Mac eth header length
14 ********************************************/
15 #define DRIVER_HANDLER_SIZE 4
16 #define MAX_MAC_HDR_LEN 26 /* QOS_MAC_HDR_LEN */
17 #define SUB_MSDU_HEADER_LENGTH 14
18 #define SNAP_HDR_LEN 8
19 #define ETHERNET_HDR_LEN 14
20 #define WORD_ALIGNMENT_PAD 0
22 #define ETH_ETHERNET_HDR_OFFSET (MAX_MAC_HDR_LEN + SUB_MSDU_HEADER_LENGTH + \
23 SNAP_HDR_LEN - ETHERNET_HDR_LEN + WORD_ALIGNMENT_PAD)
25 /*Bug3959: transmitting mgmt frames received from host*/
26 #define HOST_HDR_OFFSET 4
27 #define ETHERNET_HDR_LEN 14
29 #define IP_HDR_OFFSET ETHERNET_HDR_LEN
30 #define UDP_HDR_OFFSET (IP_HDR_LEN + IP_HDR_OFFSET)
32 #define UDP_DATA_OFFSET (UDP_HDR_OFFSET + UDP_HDR_LEN)
33 #define ETH_CONFIG_PKT_HDR_LEN UDP_DATA_OFFSET
35 #define ETH_CONFIG_PKT_HDR_OFFSET (ETH_ETHERNET_HDR_OFFSET + \
36 ETH_CONFIG_PKT_HDR_LEN)
38 #define PROBE_REQ 0x40
39 #ifdef WILC_FULLY_HOSTING_AP
40 #define FH_TX_HOST_HDR_OFFSET 24
43 /********************************************
47 ********************************************/
49 #define BYTE_SWAP(val) ((((val) & 0x000000FF) << 24) + \
50 (((val) & 0x0000FF00) << 8) + \
51 (((val) & 0x00FF0000) >> 8) + \
52 (((val) & 0xFF000000) >> 24))
54 /********************************************
58 ********************************************/
59 #define WILC_PERIPH_REG_BASE 0x1000
61 #define WILC_CHANGING_VIR_IF (0x108c)
62 #define WILC_CHIPID (WILC_PERIPH_REG_BASE)
63 #define WILC_GLB_RESET_0 (WILC_PERIPH_REG_BASE + 0x400)
64 #define WILC_PIN_MUX_0 (WILC_PERIPH_REG_BASE + 0x408)
65 #define WILC_HOST_TX_CTRL (WILC_PERIPH_REG_BASE + 0x6c)
66 #define WILC_HOST_RX_CTRL_0 (WILC_PERIPH_REG_BASE + 0x70)
67 #define WILC_HOST_RX_CTRL_1 (WILC_PERIPH_REG_BASE + 0x74)
68 #define WILC_HOST_VMM_CTL (WILC_PERIPH_REG_BASE + 0x78)
69 #define WILC_HOST_RX_CTRL (WILC_PERIPH_REG_BASE + 0x80)
70 #define WILC_HOST_RX_EXTRA_SIZE (WILC_PERIPH_REG_BASE + 0x84)
71 #define WILC_HOST_TX_CTRL_1 (WILC_PERIPH_REG_BASE + 0x88)
72 #define WILC_MISC (WILC_PERIPH_REG_BASE + 0x428)
73 #define WILC_INTR_REG_BASE (WILC_PERIPH_REG_BASE + 0xa00)
74 #define WILC_INTR_ENABLE (WILC_INTR_REG_BASE)
75 #define WILC_INTR2_ENABLE (WILC_INTR_REG_BASE + 4)
77 #define WILC_INTR_POLARITY (WILC_INTR_REG_BASE + 0x10)
78 #define WILC_INTR_TYPE (WILC_INTR_REG_BASE + 0x20)
79 #define WILC_INTR_CLEAR (WILC_INTR_REG_BASE + 0x30)
80 #define WILC_INTR_STATUS (WILC_INTR_REG_BASE + 0x40)
82 #define WILC_VMM_TBL_SIZE 64
83 #define WILC_VMM_TX_TBL_BASE (0x150400)
84 #define WILC_VMM_RX_TBL_BASE (0x150500)
86 #define WILC_VMM_BASE 0x150000
87 #define WILC_VMM_CORE_CTL (WILC_VMM_BASE)
88 #define WILC_VMM_TBL_CTL (WILC_VMM_BASE + 0x4)
89 #define WILC_VMM_TBL_ENTRY (WILC_VMM_BASE + 0x8)
90 #define WILC_VMM_TBL0_SIZE (WILC_VMM_BASE + 0xc)
91 #define WILC_VMM_TO_HOST_SIZE (WILC_VMM_BASE + 0x10)
92 #define WILC_VMM_CORE_CFG (WILC_VMM_BASE + 0x14)
93 #define WILC_VMM_TBL_ACTIVE (WILC_VMM_BASE + 040)
94 #define WILC_VMM_TBL_STATUS (WILC_VMM_BASE + 0x44)
96 #define WILC_SPI_REG_BASE 0xe800
97 #define WILC_SPI_CTL (WILC_SPI_REG_BASE)
98 #define WILC_SPI_MASTER_DMA_ADDR (WILC_SPI_REG_BASE + 0x4)
99 #define WILC_SPI_MASTER_DMA_COUNT (WILC_SPI_REG_BASE + 0x8)
100 #define WILC_SPI_SLAVE_DMA_ADDR (WILC_SPI_REG_BASE + 0xc)
101 #define WILC_SPI_SLAVE_DMA_COUNT (WILC_SPI_REG_BASE + 0x10)
102 #define WILC_SPI_TX_MODE (WILC_SPI_REG_BASE + 0x20)
103 #define WILC_SPI_PROTOCOL_CONFIG (WILC_SPI_REG_BASE + 0x24)
104 #define WILC_SPI_INTR_CTL (WILC_SPI_REG_BASE + 0x2c)
106 #define WILC_SPI_PROTOCOL_OFFSET (WILC_SPI_PROTOCOL_CONFIG - WILC_SPI_REG_BASE)
108 #define WILC_AHB_DATA_MEM_BASE 0x30000
109 #define WILC_AHB_SHARE_MEM_BASE 0xd0000
111 #define WILC_VMM_TBL_RX_SHADOW_BASE WILC_AHB_SHARE_MEM_BASE /* Bug 4477 fix */
112 #define WILC_VMM_TBL_RX_SHADOW_SIZE (256) /* Bug 4477 fix */
114 #define WILC_GP_REG_0 0x149c
115 #define WILC_GP_REG_1 0x14a0
117 #define rHAVE_SDIO_IRQ_GPIO_BIT (0)
118 #define rHAVE_USE_PMU_BIT (1)
119 #define rHAVE_SLEEP_CLK_SRC_RTC_BIT (2)
120 #define rHAVE_SLEEP_CLK_SRC_XO_BIT (3)
121 #define rHAVE_EXT_PA_INV_TX_RX_BIT (4)
122 #define rHAVE_LEGACY_RF_SETTINGS_BIT (5)
123 #define rHAVE_XTAL_24_BIT (6)
124 #define rHAVE_DISABLE_WILC_UART_BIT (7)
127 #define WILC_HAVE_SDIO_IRQ_GPIO (1 << rHAVE_SDIO_IRQ_GPIO_BIT)
128 #define WILC_HAVE_USE_PMU (1 << rHAVE_USE_PMU_BIT)
129 #define WILC_HAVE_SLEEP_CLK_SRC_RTC (1 << rHAVE_SLEEP_CLK_SRC_RTC_BIT)
130 #define WILC_HAVE_SLEEP_CLK_SRC_XO (1 << rHAVE_SLEEP_CLK_SRC_XO_BIT)
131 #define WILC_HAVE_EXT_PA_INV_TX_RX (1 << rHAVE_EXT_PA_INV_TX_RX_BIT)
132 #define WILC_HAVE_LEGACY_RF_SETTINGS (1 << rHAVE_LEGACY_RF_SETTINGS_BIT)
133 #define WILC_HAVE_XTAL_24 (1 << rHAVE_XTAL_24_BIT)
134 #define WILC_HAVE_DISABLE_WILC_UART (1 << rHAVE_DISABLE_WILC_UART_BIT)
137 /********************************************
141 ********************************************/
142 #define WILC_CFG_PKT 1
143 #define WILC_NET_PKT 0
144 /*Bug3959: transmitting mgmt frames received from host*/
145 #ifdef WILC_AP_EXTERNAL_MLME
146 #define WILC_MGMT_PKT 2
148 #ifdef WILC_FULLY_HOSTING_AP
149 #define WILC_FH_DATA_PKT 4
152 #endif /*WILC_AP_EXTERNAL_MLME*/
153 #define WILC_CFG_SET 1
154 #define WILC_CFG_QUERY 0
156 #define WILC_CFG_RSP 1
157 #define WILC_CFG_RSP_STATUS 2
158 #define WILC_CFG_RSP_SCAN 3
161 #define WILC_PLL_TO 4
163 #define WILC_PLL_TO 2
167 #define ABORT_INT (1 << 31)
169 /*******************************************/
170 /* E0 and later Interrupt flags. */
171 /*******************************************/
172 /*******************************************/
173 /* E0 and later Interrupt flags. */
174 /* IRQ Status word */
175 /* 15:0 = DMA count in words. */
182 /*******************************************/
183 #define IRG_FLAGS_OFFSET 16
184 #define IRQ_DMA_WD_CNT_MASK ((1ul << IRG_FLAGS_OFFSET) - 1)
185 #define INT_0 (1 << (IRG_FLAGS_OFFSET))
186 #define INT_1 (1 << (IRG_FLAGS_OFFSET + 1))
187 #define INT_2 (1 << (IRG_FLAGS_OFFSET + 2))
188 #define INT_3 (1 << (IRG_FLAGS_OFFSET + 3))
189 #define INT_4 (1 << (IRG_FLAGS_OFFSET + 4))
190 #define INT_5 (1 << (IRG_FLAGS_OFFSET + 5))
191 #define MAX_NUM_INT (6)
193 /*******************************************/
194 /* E0 and later Interrupt flags. */
202 /* 6: Select VMM table 1 */
203 /* 7: Select VMM table 2 */
205 /*******************************************/
206 #define CLR_INT0 (1 << 0)
207 #define CLR_INT1 (1 << 1)
208 #define CLR_INT2 (1 << 2)
209 #define CLR_INT3 (1 << 3)
210 #define CLR_INT4 (1 << 4)
211 #define CLR_INT5 (1 << 5)
212 #define SEL_VMM_TBL0 (1 << 6)
213 #define SEL_VMM_TBL1 (1 << 7)
214 #define EN_VMM (1 << 8)
216 #define DATA_INT_EXT INT_0
217 #define PLL_INT_EXT INT_1
218 #define SLEEP_INT_EXT INT_2
219 #define ALL_INT_EXT (DATA_INT_EXT | PLL_INT_EXT | SLEEP_INT_EXT)
220 #define NUM_INT_EXT (3)
222 #define DATA_INT_CLR CLR_INT0
223 #define PLL_INT_CLR CLR_INT1
224 #define SLEEP_INT_CLR CLR_INT2
226 #define ENABLE_RX_VMM (SEL_VMM_TBL1 | EN_VMM)
227 #define ENABLE_TX_VMM (SEL_VMM_TBL0 | EN_VMM)
230 /*time for expiring the semaphores of cfg packets*/
231 #define CFG_PKTS_TIMEOUT 2000
232 /********************************************
236 ********************************************/
237 typedef void (*wilc_debug_func
)(uint32_t, char *, ...);
239 /********************************************
241 * Tx/Rx Queue Structure
243 ********************************************/
246 struct txq_entry_t
*next
;
247 struct txq_entry_t
*prev
;
249 int tcp_PendingAck_index
;
254 void (*tx_complete_func
)(void *, int);
258 struct rxq_entry_t
*next
;
263 /********************************************
267 ********************************************/
270 int (*hif_init
)(wilc_wlan_inp_t
*, wilc_debug_func
);
271 int (*hif_deinit
)(void *);
272 int (*hif_read_reg
)(uint32_t, uint32_t *);
273 int (*hif_write_reg
)(uint32_t, uint32_t);
274 int (*hif_block_rx
)(uint32_t, uint8_t *, uint32_t);
275 int (*hif_block_tx
)(uint32_t, uint8_t *, uint32_t);
276 int (*hif_sync
)(void);
277 int (*hif_clear_int
)(void);
278 int (*hif_read_int
)(uint32_t *);
279 int (*hif_clear_int_ext
)(uint32_t);
280 int (*hif_read_size
)(uint32_t *);
281 int (*hif_block_tx_ext
)(uint32_t, uint8_t *, uint32_t);
282 int (*hif_block_rx_ext
)(uint32_t, uint8_t *, uint32_t);
283 int (*hif_sync_ext
)(int);
284 void (*hif_set_max_bus_speed
)(void);
285 void (*hif_set_default_bus_speed
)(void);
288 /********************************************
290 * Configuration Structure
292 ********************************************/
294 #define MAX_CFG_FRAME_SIZE 1468
297 uint8_t ether_header
[14];
298 uint8_t ip_header
[20];
299 uint8_t udp_header
[8];
300 uint8_t wid_header
[8];
301 uint8_t frame
[MAX_CFG_FRAME_SIZE
];
305 int (*wlan_tx
)(uint8_t *, uint32_t, wilc_tx_complete_func_t
);
306 } wilc_wlan_cfg_func_t
;
314 int (*cfg_wid_set
)(uint8_t *, uint32_t, uint16_t, uint8_t *, int);
315 int (*cfg_wid_get
)(uint8_t *, uint32_t, uint16_t);
316 int (*cfg_wid_get_val
)(uint16_t, uint8_t *, uint32_t);
317 int (*rx_indicate
)(uint8_t *, int, wilc_cfg_rsp_t
*);
318 int (*cfg_init
)(wilc_debug_func
);