drivers/staging/wilc1000/wilc_wlan.h

   1 #ifndef WILC_WLAN_H
   2 #define WILC_WLAN_H
   3
   4 #include "wilc_oswrapper.h"
   5
   6
   7 #define ISWILC1000(id)   (((id & 0xfffff000) == 0x100000) ? 1 : 0)
   8
   9
  10 /********************************************
  11  *
  12  *      Mac eth header length
  13  *
  14  ********************************************/
  15 #define DRIVER_HANDLER_SIZE 4
  16 #define MAX_MAC_HDR_LEN         26 /* QOS_MAC_HDR_LEN */
  17 #define SUB_MSDU_HEADER_LENGTH  14
  18 #define SNAP_HDR_LEN            8
  19 #define ETHERNET_HDR_LEN          14
  20 #define WORD_ALIGNMENT_PAD        0
  21
  22 #define ETH_ETHERNET_HDR_OFFSET   (MAX_MAC_HDR_LEN + SUB_MSDU_HEADER_LENGTH + \
  23                                    SNAP_HDR_LEN - ETHERNET_HDR_LEN + WORD_ALIGNMENT_PAD)
  24
  25 /*Bug3959: transmitting mgmt frames received from host*/
  26 #define HOST_HDR_OFFSET         4
  27 #define ETHERNET_HDR_LEN          14
  28 #define IP_HDR_LEN                20
  29 #define IP_HDR_OFFSET             ETHERNET_HDR_LEN
  30 #define UDP_HDR_OFFSET            (IP_HDR_LEN + IP_HDR_OFFSET)
  31 #define UDP_HDR_LEN               8
  32 #define UDP_DATA_OFFSET           (UDP_HDR_OFFSET + UDP_HDR_LEN)
  33 #define ETH_CONFIG_PKT_HDR_LEN    UDP_DATA_OFFSET
  34
  35 #define ETH_CONFIG_PKT_HDR_OFFSET (ETH_ETHERNET_HDR_OFFSET + \
  36                                    ETH_CONFIG_PKT_HDR_LEN)
  37 #define   ACTION         0xD0
  38 #define   PROBE_REQ   0x40
  39
  40 /********************************************
  41  *
  42  *      Endian Conversion
  43  *
  44  ********************************************/
  45
  46 #define BYTE_SWAP(val) ((((val) & 0x000000FF) << 24) + \
  47                         (((val) & 0x0000FF00) << 8)  + \
  48                         (((val) & 0x00FF0000) >> 8)   + \
  49                         (((val) & 0xFF000000) >> 24))
  50
  51 /********************************************
  52  *
  53  *      Register Defines
  54  *
  55  ********************************************/
  56 #define WILC_PERIPH_REG_BASE 0x1000
  57 /*BugID_5137*/
  58 #define WILC_CHANGING_VIR_IF                     (0x108c)
  59 #define WILC_CHIPID     (WILC_PERIPH_REG_BASE)
  60 #define WILC_GLB_RESET_0 (WILC_PERIPH_REG_BASE + 0x400)
  61 #define WILC_PIN_MUX_0 (WILC_PERIPH_REG_BASE + 0x408)
  62 #define WILC_HOST_TX_CTRL (WILC_PERIPH_REG_BASE + 0x6c)
  63 #define WILC_HOST_RX_CTRL_0 (WILC_PERIPH_REG_BASE + 0x70)
  64 #define WILC_HOST_RX_CTRL_1 (WILC_PERIPH_REG_BASE + 0x74)
  65 #define WILC_HOST_VMM_CTL       (WILC_PERIPH_REG_BASE + 0x78)
  66 #define WILC_HOST_RX_CTRL       (WILC_PERIPH_REG_BASE + 0x80)
  67 #define WILC_HOST_RX_EXTRA_SIZE (WILC_PERIPH_REG_BASE + 0x84)
  68 #define WILC_HOST_TX_CTRL_1     (WILC_PERIPH_REG_BASE + 0x88)
  69 #define WILC_MISC       (WILC_PERIPH_REG_BASE + 0x428)
  70 #define WILC_INTR_REG_BASE (WILC_PERIPH_REG_BASE + 0xa00)
  71 #define WILC_INTR_ENABLE (WILC_INTR_REG_BASE)
  72 #define WILC_INTR2_ENABLE (WILC_INTR_REG_BASE + 4)
  73
  74 #define WILC_INTR_POLARITY (WILC_INTR_REG_BASE + 0x10)
  75 #define WILC_INTR_TYPE (WILC_INTR_REG_BASE + 0x20)
  76 #define WILC_INTR_CLEAR (WILC_INTR_REG_BASE + 0x30)
  77 #define WILC_INTR_STATUS (WILC_INTR_REG_BASE + 0x40)
  78
  79 #define WILC_VMM_TBL_SIZE 64
  80 #define WILC_VMM_TX_TBL_BASE (0x150400)
  81 #define WILC_VMM_RX_TBL_BASE (0x150500)
  82
  83 #define WILC_VMM_BASE 0x150000
  84 #define WILC_VMM_CORE_CTL (WILC_VMM_BASE)
  85 #define WILC_VMM_TBL_CTL (WILC_VMM_BASE + 0x4)
  86 #define WILC_VMM_TBL_ENTRY (WILC_VMM_BASE + 0x8)
  87 #define WILC_VMM_TBL0_SIZE (WILC_VMM_BASE + 0xc)
  88 #define WILC_VMM_TO_HOST_SIZE (WILC_VMM_BASE + 0x10)
  89 #define WILC_VMM_CORE_CFG (WILC_VMM_BASE + 0x14)
  90 #define WILC_VMM_TBL_ACTIVE (WILC_VMM_BASE + 040)
  91 #define WILC_VMM_TBL_STATUS (WILC_VMM_BASE + 0x44)
  92
  93 #define WILC_SPI_REG_BASE 0xe800
  94 #define WILC_SPI_CTL (WILC_SPI_REG_BASE)
  95 #define WILC_SPI_MASTER_DMA_ADDR (WILC_SPI_REG_BASE + 0x4)
  96 #define WILC_SPI_MASTER_DMA_COUNT (WILC_SPI_REG_BASE + 0x8)
  97 #define WILC_SPI_SLAVE_DMA_ADDR (WILC_SPI_REG_BASE + 0xc)
  98 #define WILC_SPI_SLAVE_DMA_COUNT (WILC_SPI_REG_BASE + 0x10)
  99 #define WILC_SPI_TX_MODE (WILC_SPI_REG_BASE + 0x20)
 100 #define WILC_SPI_PROTOCOL_CONFIG (WILC_SPI_REG_BASE + 0x24)
 101 #define WILC_SPI_INTR_CTL (WILC_SPI_REG_BASE + 0x2c)
 102
 103 #define WILC_SPI_PROTOCOL_OFFSET (WILC_SPI_PROTOCOL_CONFIG - WILC_SPI_REG_BASE)
 104
 105 #define WILC_AHB_DATA_MEM_BASE 0x30000
 106 #define WILC_AHB_SHARE_MEM_BASE 0xd0000
 107
 108 #define WILC_VMM_TBL_RX_SHADOW_BASE WILC_AHB_SHARE_MEM_BASE /* Bug 4477 fix */
 109 #define WILC_VMM_TBL_RX_SHADOW_SIZE (256) /* Bug 4477 fix */
 110
 111 #define WILC_GP_REG_0   0x149c
 112 #define WILC_GP_REG_1   0x14a0
 113
 114 #define rHAVE_SDIO_IRQ_GPIO_BIT      (0)
 115 #define rHAVE_USE_PMU_BIT            (1)
 116 #define rHAVE_SLEEP_CLK_SRC_RTC_BIT  (2)
 117 #define rHAVE_SLEEP_CLK_SRC_XO_BIT   (3)
 118 #define rHAVE_EXT_PA_INV_TX_RX_BIT   (4)
 119 #define rHAVE_LEGACY_RF_SETTINGS_BIT (5)
 120 #define rHAVE_XTAL_24_BIT            (6)
 121 #define rHAVE_DISABLE_WILC_UART_BIT   (7)
 122
 123
 124 #define WILC_HAVE_SDIO_IRQ_GPIO       (1 << rHAVE_SDIO_IRQ_GPIO_BIT)
 125 #define WILC_HAVE_USE_PMU             (1 << rHAVE_USE_PMU_BIT)
 126 #define WILC_HAVE_SLEEP_CLK_SRC_RTC   (1 << rHAVE_SLEEP_CLK_SRC_RTC_BIT)
 127 #define WILC_HAVE_SLEEP_CLK_SRC_XO    (1 << rHAVE_SLEEP_CLK_SRC_XO_BIT)
 128 #define WILC_HAVE_EXT_PA_INV_TX_RX    (1 << rHAVE_EXT_PA_INV_TX_RX_BIT)
 129 #define WILC_HAVE_LEGACY_RF_SETTINGS  (1 << rHAVE_LEGACY_RF_SETTINGS_BIT)
 130 #define WILC_HAVE_XTAL_24             (1 << rHAVE_XTAL_24_BIT)
 131 #define WILC_HAVE_DISABLE_WILC_UART    (1 << rHAVE_DISABLE_WILC_UART_BIT)
 132
 133
 134 /********************************************
 135  *
 136  *      Wlan Defines
 137  *
 138  ********************************************/
 139 #define WILC_CFG_PKT    1
 140 #define WILC_NET_PKT 0
 141 /*Bug3959: transmitting mgmt frames received from host*/
 142 #define WILC_MGMT_PKT 2
 143
 144 #define WILC_CFG_SET 1
 145 #define WILC_CFG_QUERY 0
 146
 147 #define WILC_CFG_RSP    1
 148 #define WILC_CFG_RSP_STATUS 2
 149 #define WILC_CFG_RSP_SCAN 3
 150
 151 #ifdef WILC_SDIO
 152 #define WILC_PLL_TO     4
 153 #else
 154 #define WILC_PLL_TO     2
 155 #endif
 156
 157
 158 #define ABORT_INT   (1 << 31)
 159
 160 /*******************************************/
 161 /*        E0 and later Interrupt flags.    */
 162 /*******************************************/
 163 /*******************************************/
 164 /*        E0 and later Interrupt flags.    */
 165 /*           IRQ Status word               */
 166 /* 15:0 = DMA count in words.              */
 167 /* 16: INT0 flag                           */
 168 /* 17: INT1 flag                           */
 169 /* 18: INT2 flag                           */
 170 /* 19: INT3 flag                           */
 171 /* 20: INT4 flag                           */
 172 /* 21: INT5 flag                           */
 173 /*******************************************/
 174 #define                 IRG_FLAGS_OFFSET 16
 175 #define IRQ_DMA_WD_CNT_MASK ((1ul << IRG_FLAGS_OFFSET) - 1)
 176 #define INT_0           (1 << (IRG_FLAGS_OFFSET))
 177 #define INT_1           (1 << (IRG_FLAGS_OFFSET + 1))
 178 #define INT_2           (1 << (IRG_FLAGS_OFFSET + 2))
 179 #define INT_3           (1 << (IRG_FLAGS_OFFSET + 3))
 180 #define INT_4           (1 << (IRG_FLAGS_OFFSET + 4))
 181 #define INT_5           (1 << (IRG_FLAGS_OFFSET + 5))
 182 #define MAX_NUM_INT     (6)
 183
 184 /*******************************************/
 185 /*        E0 and later Interrupt flags.    */
 186 /*           IRQ Clear word                */
 187 /* 0: Clear INT0                           */
 188 /* 1: Clear INT1                           */
 189 /* 2: Clear INT2                           */
 190 /* 3: Clear INT3                           */
 191 /* 4: Clear INT4                           */
 192 /* 5: Clear INT5                           */
 193 /* 6: Select VMM table 1                   */
 194 /* 7: Select VMM table 2                   */
 195 /* 8: Enable VMM                           */
 196 /*******************************************/
 197 #define CLR_INT0             (1 << 0)
 198 #define CLR_INT1             (1 << 1)
 199 #define CLR_INT2             (1 << 2)
 200 #define CLR_INT3             (1 << 3)
 201 #define CLR_INT4             (1 << 4)
 202 #define CLR_INT5             (1 << 5)
 203 #define SEL_VMM_TBL0         (1 << 6)
 204 #define SEL_VMM_TBL1         (1 << 7)
 205 #define EN_VMM               (1 << 8)
 206
 207 #define DATA_INT_EXT    INT_0
 208 #define PLL_INT_EXT         INT_1
 209 #define SLEEP_INT_EXT   INT_2
 210 #define ALL_INT_EXT     (DATA_INT_EXT | PLL_INT_EXT | SLEEP_INT_EXT)
 211 #define NUM_INT_EXT     (3)
 212
 213 #define DATA_INT_CLR    CLR_INT0
 214 #define PLL_INT_CLR         CLR_INT1
 215 #define SLEEP_INT_CLR   CLR_INT2
 216
 217 #define ENABLE_RX_VMM   (SEL_VMM_TBL1 | EN_VMM)
 218 #define ENABLE_TX_VMM   (SEL_VMM_TBL0 | EN_VMM)
 219
 220
 221 /*time for expiring the semaphores of cfg packets*/
 222 #define CFG_PKTS_TIMEOUT        2000
 223 /********************************************
 224  *
 225  *      Debug Type
 226  *
 227  ********************************************/
 228 typedef void (*wilc_debug_func)(u32, char *, ...);
 229
 230 /********************************************
 231  *
 232  *      Tx/Rx Queue Structure
 233  *
 234  ********************************************/
 235
 236 struct txq_entry_t {
 237         struct txq_entry_t *next;
 238         struct txq_entry_t *prev;
 239         int type;
 240         int tcp_PendingAck_index;
 241         u8 *buffer;
 242         int buffer_size;
 243         void *priv;
 244         int status;
 245         void (*tx_complete_func)(void *, int);
 246 };
 247
 248 struct rxq_entry_t {
 249         struct rxq_entry_t *next;
 250         u8 *buffer;
 251         int buffer_size;
 252 };
 253
 254 /********************************************
 255  *
 256  *      Host IF Structure
 257  *
 258  ********************************************/
 259
 260 typedef struct {
 261         int (*hif_init)(wilc_wlan_inp_t *, wilc_debug_func);
 262         int (*hif_deinit)(void *);
 263         int (*hif_read_reg)(u32, u32 *);
 264         int (*hif_write_reg)(u32, u32);
 265         int (*hif_block_rx)(u32, u8 *, u32);
 266         int (*hif_block_tx)(u32, u8 *, u32);
 267         int (*hif_sync)(void);
 268         int (*hif_clear_int)(void);
 269         int (*hif_read_int)(u32 *);
 270         int (*hif_clear_int_ext)(u32);
 271         int (*hif_read_size)(u32 *);
 272         int (*hif_block_tx_ext)(u32, u8 *, u32);
 273         int (*hif_block_rx_ext)(u32, u8 *, u32);
 274         int (*hif_sync_ext)(int);
 275         void (*hif_set_max_bus_speed)(void);
 276         void (*hif_set_default_bus_speed)(void);
 277 } wilc_hif_func_t;
 278
 279 /********************************************
 280  *
 281  *      Configuration Structure
 282  *
 283  ********************************************/
 284
 285 #define MAX_CFG_FRAME_SIZE 1468
 286
 287 typedef struct {
 288         u8 ether_header[14];
 289         u8 ip_header[20];
 290         u8 udp_header[8];
 291         u8 wid_header[8];
 292         u8 frame[MAX_CFG_FRAME_SIZE];
 293 } wilc_cfg_frame_t;
 294
 295 typedef struct {
 296         int (*wlan_tx)(u8 *, u32, wilc_tx_complete_func_t);
 297 } wilc_wlan_cfg_func_t;
 298
 299 typedef struct {
 300         int type;
 301         u32 seq_no;
 302 } wilc_cfg_rsp_t;
 303
 304 typedef struct {
 305         int (*cfg_wid_set)(u8 *, u32, u16, u8 *, int);
 306         int (*cfg_wid_get)(u8 *, u32, u16);
 307         int (*cfg_wid_get_val)(u16, u8 *, u32);
 308         int (*rx_indicate)(u8 *, int, wilc_cfg_rsp_t *);
 309         int (*cfg_init)(wilc_debug_func);
 310 } wilc_cfg_func_t;
 311
 312 #endif