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Linux 3.9-rc5
[deliverable/linux.git] / drivers / staging / xgifb / vb_init.c
1 #include <linux/delay.h>
2 #include <linux/vmalloc.h>
3
4 #include "XGIfb.h"
5 #include "vb_def.h"
6 #include "vb_util.h"
7 #include "vb_setmode.h"
8 #include "vb_init.h"
9 static const unsigned short XGINew_DDRDRAM_TYPE340[4][2] = {
10 { 16, 0x45},
11 { 8, 0x35},
12 { 4, 0x31},
13 { 2, 0x21} };
14
15 static const unsigned short XGINew_DDRDRAM_TYPE20[12][2] = {
16 { 128, 0x5D},
17 { 64, 0x59},
18 { 64, 0x4D},
19 { 32, 0x55},
20 { 32, 0x49},
21 { 32, 0x3D},
22 { 16, 0x51},
23 { 16, 0x45},
24 { 16, 0x39},
25 { 8, 0x41},
26 { 8, 0x35},
27 { 4, 0x31} };
28
29 #define XGIFB_ROM_SIZE 65536
30
31 static unsigned char
32 XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
33 struct vb_device_info *pVBInfo)
34 {
35 unsigned char data, temp;
36
37 if (HwDeviceExtension->jChipType < XG20) {
38 data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
39 if (data == 0)
40 data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
41 0x02) >> 1;
42 return data;
43 } else if (HwDeviceExtension->jChipType == XG27) {
44 temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
45 /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
46 if (((temp & 0x88) == 0x80) || ((temp & 0x88) == 0x08))
47 data = 0; /* DDR */
48 else
49 data = 1; /* DDRII */
50 return data;
51 } else if (HwDeviceExtension->jChipType == XG21) {
52 /* Independent GPIO control */
53 xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02);
54 udelay(800);
55 xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
56 /* GPIOF 0:DVI 1:DVO */
57 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
58 /* HOTPLUG_SUPPORT */
59 /* for current XG20 & XG21, GPIOH is floating, driver will
60 * fix DDR temporarily */
61 if (temp & 0x01) /* DVI read GPIOH */
62 data = 1; /* DDRII */
63 else
64 data = 0; /* DDR */
65 /* ~HOTPLUG_SUPPORT */
66 xgifb_reg_or(pVBInfo->P3d4, 0xB4, 0x02);
67 return data;
68 } else {
69 data = xgifb_reg_get(pVBInfo->P3d4, 0x97) & 0x01;
70
71 if (data == 1)
72 data++;
73
74 return data;
75 }
76 }
77
78 static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
79 struct vb_device_info *pVBInfo)
80 {
81 xgifb_reg_set(P3c4, 0x18, 0x01);
82 xgifb_reg_set(P3c4, 0x19, 0x20);
83 xgifb_reg_set(P3c4, 0x16, 0x00);
84 xgifb_reg_set(P3c4, 0x16, 0x80);
85
86 mdelay(3);
87 xgifb_reg_set(P3c4, 0x18, 0x00);
88 xgifb_reg_set(P3c4, 0x19, 0x20);
89 xgifb_reg_set(P3c4, 0x16, 0x00);
90 xgifb_reg_set(P3c4, 0x16, 0x80);
91
92 udelay(60);
93 xgifb_reg_set(P3c4,
94 0x18,
95 pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
96 xgifb_reg_set(P3c4, 0x19, 0x01);
97 xgifb_reg_set(P3c4, 0x16, 0x03);
98 xgifb_reg_set(P3c4, 0x16, 0x83);
99 mdelay(1);
100 xgifb_reg_set(P3c4, 0x1B, 0x03);
101 udelay(500);
102 xgifb_reg_set(P3c4,
103 0x18,
104 pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
105 xgifb_reg_set(P3c4, 0x19, 0x00);
106 xgifb_reg_set(P3c4, 0x16, 0x03);
107 xgifb_reg_set(P3c4, 0x16, 0x83);
108 xgifb_reg_set(P3c4, 0x1B, 0x00);
109 }
110
111 static void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension,
112 struct vb_device_info *pVBInfo)
113 {
114
115 xgifb_reg_set(pVBInfo->P3c4,
116 0x28,
117 pVBInfo->MCLKData[pVBInfo->ram_type].SR28);
118 xgifb_reg_set(pVBInfo->P3c4,
119 0x29,
120 pVBInfo->MCLKData[pVBInfo->ram_type].SR29);
121 xgifb_reg_set(pVBInfo->P3c4,
122 0x2A,
123 pVBInfo->MCLKData[pVBInfo->ram_type].SR2A);
124
125 xgifb_reg_set(pVBInfo->P3c4,
126 0x2E,
127 XGI340_ECLKData[pVBInfo->ram_type].SR2E);
128 xgifb_reg_set(pVBInfo->P3c4,
129 0x2F,
130 XGI340_ECLKData[pVBInfo->ram_type].SR2F);
131 xgifb_reg_set(pVBInfo->P3c4,
132 0x30,
133 XGI340_ECLKData[pVBInfo->ram_type].SR30);
134 }
135
136 static void XGINew_DDRII_Bootup_XG27(
137 struct xgi_hw_device_info *HwDeviceExtension,
138 unsigned long P3c4, struct vb_device_info *pVBInfo)
139 {
140 unsigned long P3d4 = P3c4 + 0x10;
141 pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
142 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
143
144 /* Set Double Frequency */
145 xgifb_reg_set(P3d4, 0x97, pVBInfo->XGINew_CR97); /* CR97 */
146
147 udelay(200);
148
149 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
150 xgifb_reg_set(P3c4, 0x19, 0x80); /* Set SR19 */
151 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
152 udelay(15);
153 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
154 udelay(15);
155
156 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
157 xgifb_reg_set(P3c4, 0x19, 0xC0); /* Set SR19 */
158 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
159 udelay(15);
160 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
161 udelay(15);
162
163 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
164 xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
165 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
166 udelay(30);
167 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
168 udelay(15);
169
170 xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
171 xgifb_reg_set(P3c4, 0x19, 0x0A); /* Set SR19 */
172 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
173 udelay(30);
174 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
175 xgifb_reg_set(P3c4, 0x16, 0x80); /* Set SR16 */
176
177 xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B */
178 udelay(60);
179 xgifb_reg_set(P3c4, 0x1B, 0x00); /* Set SR1B */
180
181 xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
182 xgifb_reg_set(P3c4, 0x19, 0x08); /* Set SR19 */
183 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
184
185 udelay(30);
186 xgifb_reg_set(P3c4, 0x16, 0x83); /* Set SR16 */
187 udelay(15);
188
189 xgifb_reg_set(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
190 xgifb_reg_set(P3c4, 0x19, 0x46); /* Set SR19 */
191 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
192 udelay(30);
193 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
194 udelay(15);
195
196 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
197 xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
198 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
199 udelay(30);
200 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
201 udelay(15);
202
203 /* Set SR1B refresh control 000:close; 010:open */
204 xgifb_reg_set(P3c4, 0x1B, 0x04);
205 udelay(200);
206
207 }
208
209 static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
210 unsigned long P3c4, struct vb_device_info *pVBInfo)
211 {
212 unsigned long P3d4 = P3c4 + 0x10;
213
214 pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
215 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
216
217 xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
218
219 udelay(200);
220 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS2 */
221 xgifb_reg_set(P3c4, 0x19, 0x80);
222 xgifb_reg_set(P3c4, 0x16, 0x05);
223 xgifb_reg_set(P3c4, 0x16, 0x85);
224
225 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS3 */
226 xgifb_reg_set(P3c4, 0x19, 0xC0);
227 xgifb_reg_set(P3c4, 0x16, 0x05);
228 xgifb_reg_set(P3c4, 0x16, 0x85);
229
230 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS1 */
231 xgifb_reg_set(P3c4, 0x19, 0x40);
232 xgifb_reg_set(P3c4, 0x16, 0x05);
233 xgifb_reg_set(P3c4, 0x16, 0x85);
234
235 xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
236 xgifb_reg_set(P3c4, 0x19, 0x02);
237 xgifb_reg_set(P3c4, 0x16, 0x05);
238 xgifb_reg_set(P3c4, 0x16, 0x85);
239
240 udelay(15);
241 xgifb_reg_set(P3c4, 0x1B, 0x04); /* SR1B */
242 udelay(30);
243 xgifb_reg_set(P3c4, 0x1B, 0x00); /* SR1B */
244 udelay(100);
245
246 xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
247 xgifb_reg_set(P3c4, 0x19, 0x00);
248 xgifb_reg_set(P3c4, 0x16, 0x05);
249 xgifb_reg_set(P3c4, 0x16, 0x85);
250
251 udelay(200);
252 }
253
254 static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
255 struct vb_device_info *pVBInfo)
256 {
257 xgifb_reg_set(P3c4, 0x18, 0x01);
258 xgifb_reg_set(P3c4, 0x19, 0x40);
259 xgifb_reg_set(P3c4, 0x16, 0x00);
260 xgifb_reg_set(P3c4, 0x16, 0x80);
261 udelay(60);
262
263 xgifb_reg_set(P3c4, 0x18, 0x00);
264 xgifb_reg_set(P3c4, 0x19, 0x40);
265 xgifb_reg_set(P3c4, 0x16, 0x00);
266 xgifb_reg_set(P3c4, 0x16, 0x80);
267 udelay(60);
268 xgifb_reg_set(P3c4,
269 0x18,
270 pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
271 xgifb_reg_set(P3c4, 0x19, 0x01);
272 xgifb_reg_set(P3c4, 0x16, 0x03);
273 xgifb_reg_set(P3c4, 0x16, 0x83);
274 mdelay(1);
275 xgifb_reg_set(P3c4, 0x1B, 0x03);
276 udelay(500);
277 xgifb_reg_set(P3c4,
278 0x18,
279 pVBInfo->SR15[2][pVBInfo->ram_type]); /* SR18 */
280 xgifb_reg_set(P3c4, 0x19, 0x00);
281 xgifb_reg_set(P3c4, 0x16, 0x03);
282 xgifb_reg_set(P3c4, 0x16, 0x83);
283 xgifb_reg_set(P3c4, 0x1B, 0x00);
284 }
285
286 static void XGINew_DDR1x_DefaultRegister(
287 struct xgi_hw_device_info *HwDeviceExtension,
288 unsigned long Port, struct vb_device_info *pVBInfo)
289 {
290 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
291
292 if (HwDeviceExtension->jChipType >= XG20) {
293 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
294 xgifb_reg_set(P3d4,
295 0x82,
296 pVBInfo->CR40[11][pVBInfo->ram_type]); /* CR82 */
297 xgifb_reg_set(P3d4,
298 0x85,
299 pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
300 xgifb_reg_set(P3d4,
301 0x86,
302 pVBInfo->CR40[13][pVBInfo->ram_type]); /* CR86 */
303
304 xgifb_reg_set(P3d4, 0x98, 0x01);
305 xgifb_reg_set(P3d4, 0x9A, 0x02);
306
307 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
308 } else {
309 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
310
311 switch (HwDeviceExtension->jChipType) {
312 case XG42:
313 /* CR82 */
314 xgifb_reg_set(P3d4,
315 0x82,
316 pVBInfo->CR40[11][pVBInfo->ram_type]);
317 /* CR85 */
318 xgifb_reg_set(P3d4,
319 0x85,
320 pVBInfo->CR40[12][pVBInfo->ram_type]);
321 /* CR86 */
322 xgifb_reg_set(P3d4,
323 0x86,
324 pVBInfo->CR40[13][pVBInfo->ram_type]);
325 break;
326 default:
327 xgifb_reg_set(P3d4, 0x82, 0x88);
328 xgifb_reg_set(P3d4, 0x86, 0x00);
329 /* Insert read command for delay */
330 xgifb_reg_get(P3d4, 0x86);
331 xgifb_reg_set(P3d4, 0x86, 0x88);
332 xgifb_reg_get(P3d4, 0x86);
333 xgifb_reg_set(P3d4,
334 0x86,
335 pVBInfo->CR40[13][pVBInfo->ram_type]);
336 xgifb_reg_set(P3d4, 0x82, 0x77);
337 xgifb_reg_set(P3d4, 0x85, 0x00);
338
339 /* Insert read command for delay */
340 xgifb_reg_get(P3d4, 0x85);
341 xgifb_reg_set(P3d4, 0x85, 0x88);
342
343 /* Insert read command for delay */
344 xgifb_reg_get(P3d4, 0x85);
345 /* CR85 */
346 xgifb_reg_set(P3d4,
347 0x85,
348 pVBInfo->CR40[12][pVBInfo->ram_type]);
349 /* CR82 */
350 xgifb_reg_set(P3d4,
351 0x82,
352 pVBInfo->CR40[11][pVBInfo->ram_type]);
353 break;
354 }
355
356 xgifb_reg_set(P3d4, 0x97, 0x00);
357 xgifb_reg_set(P3d4, 0x98, 0x01);
358 xgifb_reg_set(P3d4, 0x9A, 0x02);
359 XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
360 }
361 }
362
363 static void XGINew_DDR2_DefaultRegister(
364 struct xgi_hw_device_info *HwDeviceExtension,
365 unsigned long Port, struct vb_device_info *pVBInfo)
366 {
367 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
368
369 /* keep following setting sequence, each setting in
370 * the same reg insert idle */
371 xgifb_reg_set(P3d4, 0x82, 0x77);
372 xgifb_reg_set(P3d4, 0x86, 0x00);
373 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
374 xgifb_reg_set(P3d4, 0x86, 0x88);
375 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
376 /* CR86 */
377 xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][pVBInfo->ram_type]);
378 xgifb_reg_set(P3d4, 0x82, 0x77);
379 xgifb_reg_set(P3d4, 0x85, 0x00);
380 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
381 xgifb_reg_set(P3d4, 0x85, 0x88);
382 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
383 xgifb_reg_set(P3d4,
384 0x85,
385 pVBInfo->CR40[12][pVBInfo->ram_type]); /* CR85 */
386 if (HwDeviceExtension->jChipType == XG27)
387 /* CR82 */
388 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][pVBInfo->ram_type]);
389 else
390 xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
391
392 xgifb_reg_set(P3d4, 0x98, 0x01);
393 xgifb_reg_set(P3d4, 0x9A, 0x02);
394 if (HwDeviceExtension->jChipType == XG27)
395 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
396 else
397 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
398 }
399
400 static void XGI_SetDRAM_Helper(unsigned long P3d4, u8 seed, u8 temp2, u8 reg,
401 u8 shift_factor, u8 mask1, u8 mask2)
402 {
403 u8 j;
404 for (j = 0; j < 4; j++) {
405 temp2 |= (((seed >> (2 * j)) & 0x03) << shift_factor);
406 xgifb_reg_set(P3d4, reg, temp2);
407 xgifb_reg_get(P3d4, reg);
408 temp2 &= mask1;
409 temp2 += mask2;
410 }
411 }
412
413 static void XGINew_SetDRAMDefaultRegister340(
414 struct xgi_hw_device_info *HwDeviceExtension,
415 unsigned long Port, struct vb_device_info *pVBInfo)
416 {
417 unsigned char temp, temp1, temp2, temp3, j, k;
418
419 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
420
421 xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][pVBInfo->ram_type]);
422 xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][pVBInfo->ram_type]);
423 xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][pVBInfo->ram_type]);
424 xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][pVBInfo->ram_type]);
425
426 /* CR6B DQS fine tune delay */
427 temp = 0xaa;
428 XGI_SetDRAM_Helper(P3d4, temp, 0, 0x6B, 2, 0xF0, 0x10);
429
430 /* CR6E DQM fine tune delay */
431 XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6E, 2, 0xF0, 0x10);
432
433 temp3 = 0;
434 for (k = 0; k < 4; k++) {
435 /* CR6E_D[1:0] select channel */
436 xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3);
437 XGI_SetDRAM_Helper(P3d4, 0, 0, 0x6F, 0, 0xF8, 0x08);
438 temp3 += 0x01;
439 }
440
441 xgifb_reg_set(P3d4,
442 0x80,
443 pVBInfo->CR40[9][pVBInfo->ram_type]); /* CR80 */
444 xgifb_reg_set(P3d4,
445 0x81,
446 pVBInfo->CR40[10][pVBInfo->ram_type]); /* CR81 */
447
448 temp2 = 0x80;
449 /* CR89 terminator type select */
450 XGI_SetDRAM_Helper(P3d4, 0, temp2, 0x89, 0, 0xF0, 0x10);
451
452 temp = 0;
453 temp1 = temp & 0x03;
454 temp2 |= temp1;
455 xgifb_reg_set(P3d4, 0x89, temp2);
456
457 temp = pVBInfo->CR40[3][pVBInfo->ram_type];
458 temp1 = temp & 0x0F;
459 temp2 = (temp >> 4) & 0x07;
460 temp3 = temp & 0x80;
461 xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */
462 xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */
463 xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */
464 xgifb_reg_set(P3d4,
465 0x41,
466 pVBInfo->CR40[0][pVBInfo->ram_type]); /* CR41 */
467
468 if (HwDeviceExtension->jChipType == XG27)
469 xgifb_reg_set(P3d4, 0x8F, XG27_CR8F); /* CR8F */
470
471 for (j = 0; j <= 6; j++) /* CR90 - CR96 */
472 xgifb_reg_set(P3d4, (0x90 + j),
473 pVBInfo->CR40[14 + j][pVBInfo->ram_type]);
474
475 for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */
476 xgifb_reg_set(P3d4, (0xC3 + j),
477 pVBInfo->CR40[21 + j][pVBInfo->ram_type]);
478
479 for (j = 0; j < 2; j++) /* CR8A - CR8B */
480 xgifb_reg_set(P3d4, (0x8A + j),
481 pVBInfo->CR40[1 + j][pVBInfo->ram_type]);
482
483 if (HwDeviceExtension->jChipType == XG42)
484 xgifb_reg_set(P3d4, 0x8C, 0x87);
485
486 xgifb_reg_set(P3d4,
487 0x59,
488 pVBInfo->CR40[4][pVBInfo->ram_type]); /* CR59 */
489
490 xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */
491 xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */
492 xgifb_reg_set(P3d4, 0xCF, XG40_CRCF); /* CRCF */
493 if (pVBInfo->ram_type) {
494 xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */
495 if (HwDeviceExtension->jChipType == XG27)
496 xgifb_reg_set(P3c4, 0x17, 0x02); /* SR17 DDRII */
497
498 } else {
499 xgifb_reg_set(P3c4, 0x17, 0x00); /* SR17 DDR */
500 }
501 xgifb_reg_set(P3c4, 0x1A, 0x87); /* SR1A */
502
503 temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
504 if (temp == 0) {
505 XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
506 } else {
507 xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
508 XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
509 }
510 xgifb_reg_set(P3c4,
511 0x1B,
512 pVBInfo->SR15[3][pVBInfo->ram_type]); /* SR1B */
513 }
514
515
516 static unsigned short XGINew_SetDRAMSize20Reg(
517 unsigned short dram_size,
518 struct vb_device_info *pVBInfo)
519 {
520 unsigned short data = 0, memsize = 0;
521 int RankSize;
522 unsigned char ChannelNo;
523
524 RankSize = dram_size * pVBInfo->ram_bus / 8;
525 data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
526 data &= 0x80;
527
528 if (data == 0x80)
529 RankSize *= 2;
530
531 data = 0;
532
533 if (pVBInfo->ram_channel == 3)
534 ChannelNo = 4;
535 else
536 ChannelNo = pVBInfo->ram_channel;
537
538 if (ChannelNo * RankSize <= 256) {
539 while ((RankSize >>= 1) > 0)
540 data += 0x10;
541
542 memsize = data >> 4;
543
544 /* Fix DRAM Sizing Error */
545 xgifb_reg_set(pVBInfo->P3c4,
546 0x14,
547 (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
548 (data & 0xF0));
549 udelay(15);
550 }
551 return memsize;
552 }
553
554 static int XGINew_ReadWriteRest(unsigned short StopAddr,
555 unsigned short StartAddr, struct vb_device_info *pVBInfo)
556 {
557 int i;
558 unsigned long Position = 0;
559 void __iomem *fbaddr = pVBInfo->FBAddr;
560
561 writel(Position, fbaddr + Position);
562
563 for (i = StartAddr; i <= StopAddr; i++) {
564 Position = 1 << i;
565 writel(Position, fbaddr + Position);
566 }
567
568 udelay(500); /* Fix #1759 Memory Size error in Multi-Adapter. */
569
570 Position = 0;
571
572 if (readl(fbaddr + Position) != Position)
573 return 0;
574
575 for (i = StartAddr; i <= StopAddr; i++) {
576 Position = 1 << i;
577 if (readl(fbaddr + Position) != Position)
578 return 0;
579 }
580 return 1;
581 }
582
583 static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
584 {
585 unsigned char data;
586
587 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
588
589 if ((data & 0x10) == 0) {
590 data = xgifb_reg_get(pVBInfo->P3c4, 0x39);
591 data = (data & 0x02) >> 1;
592 return data;
593 } else {
594 return data & 0x01;
595 }
596 }
597
598 static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
599 struct vb_device_info *pVBInfo)
600 {
601 unsigned char data;
602
603 switch (HwDeviceExtension->jChipType) {
604 case XG20:
605 case XG21:
606 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
607 data = data & 0x01;
608 pVBInfo->ram_channel = 1; /* XG20 "JUST" one channel */
609
610 if (data == 0) { /* Single_32_16 */
611
612 if ((HwDeviceExtension->ulVideoMemorySize - 1)
613 > 0x1000000) {
614
615 pVBInfo->ram_bus = 32; /* 32 bits */
616 /* 22bit + 2 rank + 32bit */
617 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
618 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
619 udelay(15);
620
621 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
622 return;
623
624 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
625 0x800000) {
626 /* 22bit + 1 rank + 32bit */
627 xgifb_reg_set(pVBInfo->P3c4,
628 0x13,
629 0x31);
630 xgifb_reg_set(pVBInfo->P3c4,
631 0x14,
632 0x42);
633 udelay(15);
634
635 if (XGINew_ReadWriteRest(23,
636 23,
637 pVBInfo) == 1)
638 return;
639 }
640 }
641
642 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
643 0x800000) {
644 pVBInfo->ram_bus = 16; /* 16 bits */
645 /* 22bit + 2 rank + 16bit */
646 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
647 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
648 udelay(15);
649
650 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
651 return;
652 else
653 xgifb_reg_set(pVBInfo->P3c4,
654 0x13,
655 0x31);
656 udelay(15);
657 }
658
659 } else { /* Dual_16_8 */
660 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
661 0x800000) {
662 pVBInfo->ram_bus = 16; /* 16 bits */
663 /* (0x31:12x8x2) 22bit + 2 rank */
664 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
665 /* 0x41:16Mx16 bit*/
666 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
667 udelay(15);
668
669 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
670 return;
671
672 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
673 0x400000) {
674 /* (0x31:12x8x2) 22bit + 1 rank */
675 xgifb_reg_set(pVBInfo->P3c4,
676 0x13,
677 0x31);
678 /* 0x31:8Mx16 bit*/
679 xgifb_reg_set(pVBInfo->P3c4,
680 0x14,
681 0x31);
682 udelay(15);
683
684 if (XGINew_ReadWriteRest(22,
685 22,
686 pVBInfo) == 1)
687 return;
688 }
689 }
690
691 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
692 0x400000) {
693 pVBInfo->ram_bus = 8; /* 8 bits */
694 /* (0x31:12x8x2) 22bit + 2 rank */
695 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
696 /* 0x30:8Mx8 bit*/
697 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
698 udelay(15);
699
700 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
701 return;
702 else /* (0x31:12x8x2) 22bit + 1 rank */
703 xgifb_reg_set(pVBInfo->P3c4,
704 0x13,
705 0x31);
706 udelay(15);
707 }
708 }
709 break;
710
711 case XG27:
712 pVBInfo->ram_bus = 16; /* 16 bits */
713 pVBInfo->ram_channel = 1; /* Single channel */
714 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/
715 break;
716 case XG42:
717 /*
718 XG42 SR14 D[3] Reserve
719 D[2] = 1, Dual Channel
720 = 0, Single Channel
721
722 It's Different from Other XG40 Series.
723 */
724 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
725 pVBInfo->ram_bus = 32; /* 32 bits */
726 pVBInfo->ram_channel = 2; /* 2 Channel */
727 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
728 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44);
729
730 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
731 return;
732
733 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
734 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x34);
735 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
736 return;
737
738 pVBInfo->ram_channel = 1; /* Single Channel */
739 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
740 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40);
741
742 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
743 return;
744 else {
745 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
746 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
747 }
748 } else { /* DDR */
749 pVBInfo->ram_bus = 64; /* 64 bits */
750 pVBInfo->ram_channel = 1; /* 1 channels */
751 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
752 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
753
754 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
755 return;
756 else {
757 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
758 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
759 }
760 }
761
762 break;
763
764 default: /* XG40 */
765
766 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
767 pVBInfo->ram_bus = 32; /* 32 bits */
768 pVBInfo->ram_channel = 3;
769 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
770 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
771
772 if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
773 return;
774
775 pVBInfo->ram_channel = 2; /* 2 channels */
776 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
777
778 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
779 return;
780
781 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
782 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
783
784 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
785 pVBInfo->ram_channel = 3; /* 4 channels */
786 } else {
787 pVBInfo->ram_channel = 2; /* 2 channels */
788 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
789 }
790 } else { /* DDR */
791 pVBInfo->ram_bus = 64; /* 64 bits */
792 pVBInfo->ram_channel = 2; /* 2 channels */
793 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
794 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
795
796 if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1) {
797 return;
798 } else {
799 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
800 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
801 }
802 }
803 break;
804 }
805 }
806
807 static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
808 struct vb_device_info *pVBInfo)
809 {
810 u8 i, size;
811 unsigned short memsize, start_addr;
812 const unsigned short (*dram_table)[2];
813
814 xgifb_reg_set(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
815 xgifb_reg_set(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
816 XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
817
818 if (HwDeviceExtension->jChipType >= XG20) {
819 dram_table = XGINew_DDRDRAM_TYPE20;
820 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE20);
821 start_addr = 5;
822 } else {
823 dram_table = XGINew_DDRDRAM_TYPE340;
824 size = ARRAY_SIZE(XGINew_DDRDRAM_TYPE340);
825 start_addr = 9;
826 }
827
828 for (i = 0; i < size; i++) {
829 /* SetDRAMSizingType */
830 xgifb_reg_and_or(pVBInfo->P3c4, 0x13, 0x80, dram_table[i][1]);
831 udelay(15); /* should delay 50 ns */
832
833 memsize = XGINew_SetDRAMSize20Reg(dram_table[i][0], pVBInfo);
834
835 if (memsize == 0)
836 continue;
837
838 memsize += (pVBInfo->ram_channel - 2) + 20;
839 if ((HwDeviceExtension->ulVideoMemorySize - 1) <
840 (unsigned long) (1 << memsize))
841 continue;
842
843 if (XGINew_ReadWriteRest(memsize, start_addr, pVBInfo) == 1)
844 return 1;
845 }
846 return 0;
847 }
848
849 static void XGINew_SetDRAMSize_340(struct xgifb_video_info *xgifb_info,
850 struct xgi_hw_device_info *HwDeviceExtension,
851 struct vb_device_info *pVBInfo)
852 {
853 unsigned short data;
854
855 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
856
857 XGISetModeNew(xgifb_info, HwDeviceExtension, 0x2e);
858
859 data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
860 /* disable read cache */
861 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF));
862 XGI_DisplayOff(xgifb_info, HwDeviceExtension, pVBInfo);
863
864 XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
865 data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
866 /* enable read cache */
867 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20));
868 }
869
870 static u8 *xgifb_copy_rom(struct pci_dev *dev, size_t *rom_size)
871 {
872 void __iomem *rom_address;
873 u8 *rom_copy;
874
875 rom_address = pci_map_rom(dev, rom_size);
876 if (rom_address == NULL)
877 return NULL;
878
879 rom_copy = vzalloc(XGIFB_ROM_SIZE);
880 if (rom_copy == NULL)
881 goto done;
882
883 *rom_size = min_t(size_t, *rom_size, XGIFB_ROM_SIZE);
884 memcpy_fromio(rom_copy, rom_address, *rom_size);
885
886 done:
887 pci_unmap_rom(dev, rom_address);
888 return rom_copy;
889 }
890
891 static void xgifb_read_vbios(struct pci_dev *pdev,
892 struct vb_device_info *pVBInfo)
893 {
894 struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
895 u8 *vbios;
896 unsigned long i;
897 unsigned char j;
898 struct XGI21_LVDSCapStruct *lvds;
899 size_t vbios_size;
900 int entry;
901
902 if (xgifb_info->chip != XG21)
903 return;
904 pVBInfo->IF_DEF_LVDS = 0;
905 vbios = xgifb_copy_rom(pdev, &vbios_size);
906 if (vbios == NULL) {
907 dev_err(&pdev->dev, "Video BIOS not available\n");
908 return;
909 }
910 if (vbios_size <= 0x65)
911 goto error;
912 /*
913 * The user can ignore the LVDS bit in the BIOS and force the display
914 * type.
915 */
916 if (!(vbios[0x65] & 0x1) &&
917 (!xgifb_info->display2_force ||
918 xgifb_info->display2 != XGIFB_DISP_LCD)) {
919 vfree(vbios);
920 return;
921 }
922 if (vbios_size <= 0x317)
923 goto error;
924 i = vbios[0x316] | (vbios[0x317] << 8);
925 if (vbios_size <= i - 1)
926 goto error;
927 j = vbios[i - 1];
928 if (j == 0)
929 goto error;
930 if (j == 0xff)
931 j = 1;
932 /*
933 * Read the LVDS table index scratch register set by the BIOS.
934 */
935 entry = xgifb_reg_get(xgifb_info->dev_info.P3d4, 0x36);
936 if (entry >= j)
937 entry = 0;
938 i += entry * 25;
939 lvds = &xgifb_info->lvds_data;
940 if (vbios_size <= i + 24)
941 goto error;
942 lvds->LVDS_Capability = vbios[i] | (vbios[i + 1] << 8);
943 lvds->LVDSHT = vbios[i + 2] | (vbios[i + 3] << 8);
944 lvds->LVDSVT = vbios[i + 4] | (vbios[i + 5] << 8);
945 lvds->LVDSHDE = vbios[i + 6] | (vbios[i + 7] << 8);
946 lvds->LVDSVDE = vbios[i + 8] | (vbios[i + 9] << 8);
947 lvds->LVDSHFP = vbios[i + 10] | (vbios[i + 11] << 8);
948 lvds->LVDSVFP = vbios[i + 12] | (vbios[i + 13] << 8);
949 lvds->LVDSHSYNC = vbios[i + 14] | (vbios[i + 15] << 8);
950 lvds->LVDSVSYNC = vbios[i + 16] | (vbios[i + 17] << 8);
951 lvds->VCLKData1 = vbios[i + 18];
952 lvds->VCLKData2 = vbios[i + 19];
953 lvds->PSC_S1 = vbios[i + 20];
954 lvds->PSC_S2 = vbios[i + 21];
955 lvds->PSC_S3 = vbios[i + 22];
956 lvds->PSC_S4 = vbios[i + 23];
957 lvds->PSC_S5 = vbios[i + 24];
958 vfree(vbios);
959 pVBInfo->IF_DEF_LVDS = 1;
960 return;
961 error:
962 dev_err(&pdev->dev, "Video BIOS corrupted\n");
963 vfree(vbios);
964 }
965
966 static void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension,
967 struct vb_device_info *pVBInfo)
968 {
969 unsigned short tempbx = 0, temp, tempcx, CR3CData;
970
971 temp = xgifb_reg_get(pVBInfo->P3d4, 0x32);
972
973 if (temp & Monitor1Sense)
974 tempbx |= ActiveCRT1;
975 if (temp & LCDSense)
976 tempbx |= ActiveLCD;
977 if (temp & Monitor2Sense)
978 tempbx |= ActiveCRT2;
979 if (temp & TVSense) {
980 tempbx |= ActiveTV;
981 if (temp & AVIDEOSense)
982 tempbx |= (ActiveAVideo << 8);
983 if (temp & SVIDEOSense)
984 tempbx |= (ActiveSVideo << 8);
985 if (temp & SCARTSense)
986 tempbx |= (ActiveSCART << 8);
987 if (temp & HiTVSense)
988 tempbx |= (ActiveHiTV << 8);
989 if (temp & YPbPrSense)
990 tempbx |= (ActiveYPbPr << 8);
991 }
992
993 tempcx = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
994 tempcx |= (xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8);
995
996 if (tempbx & tempcx) {
997 CR3CData = xgifb_reg_get(pVBInfo->P3d4, 0x3c);
998 if (!(CR3CData & DisplayDeviceFromCMOS))
999 tempcx = 0x1FF0;
1000 } else {
1001 tempcx = 0x1FF0;
1002 }
1003
1004 tempbx &= tempcx;
1005 xgifb_reg_set(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
1006 xgifb_reg_set(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
1007 }
1008
1009 static void XGINew_SetModeScratch(struct xgi_hw_device_info *HwDeviceExtension,
1010 struct vb_device_info *pVBInfo)
1011 {
1012 unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
1013
1014 temp = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
1015 temp |= xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8;
1016 temp |= (xgifb_reg_get(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
1017
1018 if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
1019 if (temp & ActiveCRT2)
1020 tempcl = SetCRT2ToRAMDAC;
1021 }
1022
1023 if (temp & ActiveLCD) {
1024 tempcl |= SetCRT2ToLCD;
1025 if (temp & DriverMode) {
1026 if (temp & ActiveTV) {
1027 tempch = SetToLCDA | EnableDualEdge;
1028 temp ^= SetCRT2ToLCD;
1029
1030 if ((temp >> 8) & ActiveAVideo)
1031 tempcl |= SetCRT2ToAVIDEO;
1032 if ((temp >> 8) & ActiveSVideo)
1033 tempcl |= SetCRT2ToSVIDEO;
1034 if ((temp >> 8) & ActiveSCART)
1035 tempcl |= SetCRT2ToSCART;
1036
1037 if (pVBInfo->IF_DEF_HiVision == 1) {
1038 if ((temp >> 8) & ActiveHiTV)
1039 tempcl |= SetCRT2ToHiVision;
1040 }
1041
1042 if (pVBInfo->IF_DEF_YPbPr == 1) {
1043 if ((temp >> 8) & ActiveYPbPr)
1044 tempch |= SetYPbPr;
1045 }
1046 }
1047 }
1048 } else {
1049 if ((temp >> 8) & ActiveAVideo)
1050 tempcl |= SetCRT2ToAVIDEO;
1051 if ((temp >> 8) & ActiveSVideo)
1052 tempcl |= SetCRT2ToSVIDEO;
1053 if ((temp >> 8) & ActiveSCART)
1054 tempcl |= SetCRT2ToSCART;
1055
1056 if (pVBInfo->IF_DEF_HiVision == 1) {
1057 if ((temp >> 8) & ActiveHiTV)
1058 tempcl |= SetCRT2ToHiVision;
1059 }
1060
1061 if (pVBInfo->IF_DEF_YPbPr == 1) {
1062 if ((temp >> 8) & ActiveYPbPr)
1063 tempch |= SetYPbPr;
1064 }
1065 }
1066
1067 tempcl |= SetSimuScanMode;
1068 if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) || (temp & ActiveTV)
1069 || (temp & ActiveCRT2)))
1070 tempcl ^= (SetSimuScanMode | SwitchCRT2);
1071 if ((temp & ActiveLCD) && (temp & ActiveTV))
1072 tempcl ^= (SetSimuScanMode | SwitchCRT2);
1073 xgifb_reg_set(pVBInfo->P3d4, 0x30, tempcl);
1074
1075 CR31Data = xgifb_reg_get(pVBInfo->P3d4, 0x31);
1076 CR31Data &= ~(SetNotSimuMode >> 8);
1077 if (!(temp & ActiveCRT1))
1078 CR31Data |= (SetNotSimuMode >> 8);
1079 CR31Data &= ~(DisableCRT2Display >> 8);
1080 if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
1081 CR31Data |= (DisableCRT2Display >> 8);
1082 xgifb_reg_set(pVBInfo->P3d4, 0x31, CR31Data);
1083
1084 CR38Data = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1085 CR38Data &= ~SetYPbPr;
1086 CR38Data |= tempch;
1087 xgifb_reg_set(pVBInfo->P3d4, 0x38, CR38Data);
1088
1089 }
1090
1091 static unsigned short XGINew_SenseLCD(struct xgi_hw_device_info
1092 *HwDeviceExtension,
1093 struct vb_device_info *pVBInfo)
1094 {
1095 unsigned short temp;
1096
1097 /* add lcd sense */
1098 if (HwDeviceExtension->ulCRT2LCDType == LCD_UNKNOWN) {
1099 return 0;
1100 } else {
1101 temp = (unsigned short) HwDeviceExtension->ulCRT2LCDType;
1102 switch (HwDeviceExtension->ulCRT2LCDType) {
1103 case LCD_INVALID:
1104 case LCD_800x600:
1105 case LCD_1024x768:
1106 case LCD_1280x1024:
1107 break;
1108
1109 case LCD_640x480:
1110 case LCD_1024x600:
1111 case LCD_1152x864:
1112 case LCD_1280x960:
1113 case LCD_1152x768:
1114 temp = 0;
1115 break;
1116
1117 case LCD_1400x1050:
1118 case LCD_1280x768:
1119 case LCD_1600x1200:
1120 break;
1121
1122 case LCD_1920x1440:
1123 case LCD_2048x1536:
1124 temp = 0;
1125 break;
1126
1127 default:
1128 break;
1129 }
1130 xgifb_reg_and_or(pVBInfo->P3d4, 0x36, 0xF0, temp);
1131 return 1;
1132 }
1133 }
1134
1135 static void XGINew_GetXG21Sense(struct xgi_hw_device_info *HwDeviceExtension,
1136 struct vb_device_info *pVBInfo)
1137 {
1138 unsigned char Temp;
1139
1140 if (pVBInfo->IF_DEF_LVDS) { /* For XG21 LVDS */
1141 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1142 /* LVDS on chip */
1143 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1144 } else {
1145 /* Enable GPIOA/B read */
1146 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1147 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0;
1148 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
1149 XGINew_SenseLCD(HwDeviceExtension, pVBInfo);
1150 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1151 /* Enable read GPIOF */
1152 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20);
1153 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04;
1154 if (!Temp)
1155 xgifb_reg_and_or(pVBInfo->P3d4,
1156 0x38,
1157 ~0xE0,
1158 0x80); /* TMDS on chip */
1159 else
1160 xgifb_reg_and_or(pVBInfo->P3d4,
1161 0x38,
1162 ~0xE0,
1163 0xA0); /* Only DVO on chip */
1164 /* Disable read GPIOF */
1165 xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20);
1166 }
1167 }
1168 }
1169
1170 static void XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension,
1171 struct vb_device_info *pVBInfo)
1172 {
1173 unsigned char Temp, bCR4A;
1174
1175 pVBInfo->IF_DEF_LVDS = 0;
1176 bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1177 /* Enable GPIOA/B/C read */
1178 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07);
1179 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07;
1180 xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A);
1181
1182 if (Temp <= 0x02) {
1183 /* LVDS setting */
1184 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1185 xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21);
1186 } else {
1187 /* TMDS/DVO setting */
1188 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0);
1189 }
1190 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1191
1192 }
1193
1194 static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1195 {
1196 unsigned char CR38, CR4A, temp;
1197
1198 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1199 /* enable GPIOE read */
1200 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10);
1201 CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1202 temp = 0;
1203 if ((CR38 & 0xE0) > 0x80) {
1204 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1205 temp &= 0x08;
1206 temp >>= 3;
1207 }
1208
1209 xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1210
1211 return temp;
1212 }
1213
1214 static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1215 {
1216 unsigned char CR4A, temp;
1217
1218 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1219 /* enable GPIOA/B/C read */
1220 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1221 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1222 if (temp <= 2)
1223 temp &= 0x03;
1224 else
1225 temp = ((temp & 0x04) >> 1) | ((~temp) & 0x01);
1226
1227 xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1228
1229 return temp;
1230 }
1231
1232 unsigned char XGIInitNew(struct pci_dev *pdev)
1233 {
1234 struct xgifb_video_info *xgifb_info = pci_get_drvdata(pdev);
1235 struct xgi_hw_device_info *HwDeviceExtension = &xgifb_info->hw_info;
1236 struct vb_device_info VBINF;
1237 struct vb_device_info *pVBInfo = &VBINF;
1238 unsigned char i, temp = 0, temp1;
1239
1240 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1241
1242 if (pVBInfo->FBAddr == NULL) {
1243 dev_dbg(&pdev->dev, "pVBInfo->FBAddr == 0\n");
1244 return 0;
1245 }
1246
1247 XGIRegInit(pVBInfo, xgifb_info->vga_base);
1248
1249 outb(0x67, pVBInfo->P3c2);
1250
1251 if (HwDeviceExtension->jChipType < XG20)
1252 /* Run XGI_GetVBType before InitTo330Pointer */
1253 XGI_GetVBType(pVBInfo);
1254
1255 InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1256
1257 xgifb_read_vbios(pdev, pVBInfo);
1258
1259 /* Openkey */
1260 xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86);
1261
1262 /* GetXG21Sense (GPIO) */
1263 if (HwDeviceExtension->jChipType == XG21)
1264 XGINew_GetXG21Sense(HwDeviceExtension, pVBInfo);
1265
1266 if (HwDeviceExtension->jChipType == XG27)
1267 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo);
1268
1269 /* Reset Extended register */
1270
1271 for (i = 0x06; i < 0x20; i++)
1272 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1273
1274 for (i = 0x21; i <= 0x27; i++)
1275 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1276
1277 for (i = 0x31; i <= 0x3B; i++)
1278 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1279
1280 /* Auto over driver for XG42 */
1281 if (HwDeviceExtension->jChipType == XG42)
1282 xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0);
1283
1284 for (i = 0x79; i <= 0x7C; i++)
1285 xgifb_reg_set(pVBInfo->P3d4, i, 0);
1286
1287 if (HwDeviceExtension->jChipType >= XG20)
1288 xgifb_reg_set(pVBInfo->P3d4, 0x97, pVBInfo->XGINew_CR97);
1289
1290 /* SetDefExt1Regs begin */
1291 xgifb_reg_set(pVBInfo->P3c4, 0x07, XGI330_SR07);
1292 if (HwDeviceExtension->jChipType == XG27) {
1293 xgifb_reg_set(pVBInfo->P3c4, 0x40, XG27_SR40);
1294 xgifb_reg_set(pVBInfo->P3c4, 0x41, XG27_SR41);
1295 }
1296 xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
1297 xgifb_reg_set(pVBInfo->P3c4, 0x1F, XGI330_SR1F);
1298 /* Frame buffer can read/write SR20 */
1299 xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0);
1300 /* H/W request for slow corner chip */
1301 xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70);
1302 if (HwDeviceExtension->jChipType == XG27)
1303 xgifb_reg_set(pVBInfo->P3c4, 0x36, XG27_SR36);
1304
1305 if (HwDeviceExtension->jChipType < XG20) {
1306 u32 Temp;
1307
1308 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1309 for (i = 0x47; i <= 0x4C; i++)
1310 xgifb_reg_set(pVBInfo->P3d4,
1311 i,
1312 XGI340_AGPReg[i - 0x47]);
1313
1314 for (i = 0x70; i <= 0x71; i++)
1315 xgifb_reg_set(pVBInfo->P3d4,
1316 i,
1317 XGI340_AGPReg[6 + i - 0x70]);
1318
1319 for (i = 0x74; i <= 0x77; i++)
1320 xgifb_reg_set(pVBInfo->P3d4,
1321 i,
1322 XGI340_AGPReg[8 + i - 0x74]);
1323
1324 pci_read_config_dword(pdev, 0x50, &Temp);
1325 Temp >>= 20;
1326 Temp &= 0xF;
1327
1328 if (Temp == 1)
1329 xgifb_reg_set(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
1330 } /* != XG20 */
1331
1332 /* Set PCI */
1333 xgifb_reg_set(pVBInfo->P3c4, 0x23, XGI330_SR23);
1334 xgifb_reg_set(pVBInfo->P3c4, 0x24, XGI330_SR24);
1335 xgifb_reg_set(pVBInfo->P3c4, 0x25, 0);
1336
1337 if (HwDeviceExtension->jChipType < XG20) {
1338 /* Set VB */
1339 XGI_UnLockCRT2(HwDeviceExtension, pVBInfo);
1340 /* disable VideoCapture */
1341 xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00);
1342 xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00);
1343 /* chk if BCLK>=100MHz */
1344 temp1 = xgifb_reg_get(pVBInfo->P3d4, 0x7B);
1345 temp = (unsigned char) ((temp1 >> 4) & 0x0F);
1346
1347 xgifb_reg_set(pVBInfo->Part1Port,
1348 0x02, XGI330_CRT2Data_1_2);
1349
1350 xgifb_reg_set(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
1351 } /* != XG20 */
1352
1353 xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F);
1354
1355 if ((HwDeviceExtension->jChipType == XG42) &&
1356 XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) {
1357 /* Not DDR */
1358 xgifb_reg_set(pVBInfo->P3c4,
1359 0x31,
1360 (XGI330_SR31 & 0x3F) | 0x40);
1361 xgifb_reg_set(pVBInfo->P3c4,
1362 0x32,
1363 (XGI330_SR32 & 0xFC) | 0x01);
1364 } else {
1365 xgifb_reg_set(pVBInfo->P3c4, 0x31, XGI330_SR31);
1366 xgifb_reg_set(pVBInfo->P3c4, 0x32, XGI330_SR32);
1367 }
1368 xgifb_reg_set(pVBInfo->P3c4, 0x33, XGI330_SR33);
1369
1370 if (HwDeviceExtension->jChipType < XG20) {
1371 if (XGI_BridgeIsOn(pVBInfo) == 1) {
1372 if (pVBInfo->IF_DEF_LVDS == 0) {
1373 xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
1374 xgifb_reg_set(pVBInfo->Part4Port,
1375 0x0D, XGI330_CRT2Data_4_D);
1376 xgifb_reg_set(pVBInfo->Part4Port,
1377 0x0E, XGI330_CRT2Data_4_E);
1378 xgifb_reg_set(pVBInfo->Part4Port,
1379 0x10, XGI330_CRT2Data_4_10);
1380 xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
1381 }
1382
1383 XGI_LockCRT2(HwDeviceExtension, pVBInfo);
1384 }
1385 } /* != XG20 */
1386
1387 XGI_SenseCRT1(pVBInfo);
1388
1389 if (HwDeviceExtension->jChipType == XG21) {
1390
1391 xgifb_reg_and_or(pVBInfo->P3d4,
1392 0x32,
1393 ~Monitor1Sense,
1394 Monitor1Sense); /* Z9 default has CRT */
1395 temp = GetXG21FPBits(pVBInfo);
1396 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp);
1397
1398 }
1399 if (HwDeviceExtension->jChipType == XG27) {
1400 xgifb_reg_and_or(pVBInfo->P3d4,
1401 0x32,
1402 ~Monitor1Sense,
1403 Monitor1Sense); /* Z9 default has CRT */
1404 temp = GetXG27FPBits(pVBInfo);
1405 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp);
1406 }
1407
1408 pVBInfo->ram_type = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
1409
1410 XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,
1411 pVBInfo->P3d4,
1412 pVBInfo);
1413
1414 XGINew_SetDRAMSize_340(xgifb_info, HwDeviceExtension, pVBInfo);
1415
1416 xgifb_reg_set(pVBInfo->P3c4, 0x22, 0xfa);
1417 xgifb_reg_set(pVBInfo->P3c4, 0x21, 0xa3);
1418
1419 XGINew_ChkSenseStatus(HwDeviceExtension, pVBInfo);
1420 XGINew_SetModeScratch(HwDeviceExtension, pVBInfo);
1421
1422 xgifb_reg_set(pVBInfo->P3d4, 0x8c, 0x87);
1423
1424 return 1;
1425 } /* end of init */
Linux kernel - Deliverables
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