2 * exynos_tmu_data.c - Samsung EXYNOS tmu data file
4 * Copyright (C) 2013 Samsung Electronics
5 * Amit Daniel Kachhap <amit.daniel@samsung.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include "exynos_thermal_common.h"
24 #include "exynos_tmu.h"
25 #include "exynos_tmu_data.h"
27 #if defined(CONFIG_CPU_EXYNOS4210)
28 static const struct exynos_tmu_registers exynos4210_tmu_registers
= {
29 .triminfo_data
= EXYNOS_TMU_REG_TRIMINFO
,
30 .triminfo_25_shift
= EXYNOS_TRIMINFO_25_SHIFT
,
31 .triminfo_85_shift
= EXYNOS_TRIMINFO_85_SHIFT
,
32 .tmu_ctrl
= EXYNOS_TMU_REG_CONTROL
,
33 .buf_vref_sel_shift
= EXYNOS_TMU_REF_VOLTAGE_SHIFT
,
34 .buf_vref_sel_mask
= EXYNOS_TMU_REF_VOLTAGE_MASK
,
35 .buf_slope_sel_shift
= EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT
,
36 .buf_slope_sel_mask
= EXYNOS_TMU_BUF_SLOPE_SEL_MASK
,
37 .core_en_shift
= EXYNOS_TMU_CORE_EN_SHIFT
,
38 .tmu_status
= EXYNOS_TMU_REG_STATUS
,
39 .tmu_cur_temp
= EXYNOS_TMU_REG_CURRENT_TEMP
,
40 .threshold_temp
= EXYNOS4210_TMU_REG_THRESHOLD_TEMP
,
41 .threshold_th0
= EXYNOS4210_TMU_REG_TRIG_LEVEL0
,
42 .tmu_inten
= EXYNOS_TMU_REG_INTEN
,
43 .inten_rise_mask
= EXYNOS4210_TMU_TRIG_LEVEL_MASK
,
44 .inten_rise0_shift
= EXYNOS_TMU_INTEN_RISE0_SHIFT
,
45 .inten_rise1_shift
= EXYNOS_TMU_INTEN_RISE1_SHIFT
,
46 .inten_rise2_shift
= EXYNOS_TMU_INTEN_RISE2_SHIFT
,
47 .inten_rise3_shift
= EXYNOS_TMU_INTEN_RISE3_SHIFT
,
48 .tmu_intstat
= EXYNOS_TMU_REG_INTSTAT
,
49 .tmu_intclear
= EXYNOS_TMU_REG_INTCLEAR
,
52 struct exynos_tmu_init_data
const exynos4210_default_tmu_data
= {
56 .trigger_levels
[0] = 5,
57 .trigger_levels
[1] = 20,
58 .trigger_levels
[2] = 30,
59 .trigger_enable
[0] = true,
60 .trigger_enable
[1] = true,
61 .trigger_enable
[2] = true,
62 .trigger_enable
[3] = false,
63 .trigger_type
[0] = THROTTLE_ACTIVE
,
64 .trigger_type
[1] = THROTTLE_ACTIVE
,
65 .trigger_type
[2] = SW_TRIP
,
66 .max_trigger_level
= 4,
68 .reference_voltage
= 7,
69 .cal_type
= TYPE_ONE_POINT_TRIMMING
,
70 .min_efuse_value
= 40,
71 .max_efuse_value
= 100,
72 .first_point_trim
= 25,
73 .second_point_trim
= 85,
74 .default_temp_offset
= 50,
76 .freq_clip_max
= 800 * 1000,
80 .freq_clip_max
= 200 * 1000,
84 .type
= SOC_ARCH_EXYNOS4210
,
85 .registers
= &exynos4210_tmu_registers
,
92 #if defined(CONFIG_SOC_EXYNOS5250) || defined(CONFIG_SOC_EXYNOS4412)
93 static const struct exynos_tmu_registers exynos5250_tmu_registers
= {
94 .triminfo_data
= EXYNOS_TMU_REG_TRIMINFO
,
95 .triminfo_25_shift
= EXYNOS_TRIMINFO_25_SHIFT
,
96 .triminfo_85_shift
= EXYNOS_TRIMINFO_85_SHIFT
,
97 .triminfo_ctrl
= EXYNOS_TMU_TRIMINFO_CON
,
98 .triminfo_reload_shift
= EXYNOS_TRIMINFO_RELOAD_SHIFT
,
99 .tmu_ctrl
= EXYNOS_TMU_REG_CONTROL
,
100 .buf_vref_sel_shift
= EXYNOS_TMU_REF_VOLTAGE_SHIFT
,
101 .buf_vref_sel_mask
= EXYNOS_TMU_REF_VOLTAGE_MASK
,
102 .therm_trip_mode_shift
= EXYNOS_TMU_TRIP_MODE_SHIFT
,
103 .therm_trip_mode_mask
= EXYNOS_TMU_TRIP_MODE_MASK
,
104 .therm_trip_en_shift
= EXYNOS_TMU_THERM_TRIP_EN_SHIFT
,
105 .buf_slope_sel_shift
= EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT
,
106 .buf_slope_sel_mask
= EXYNOS_TMU_BUF_SLOPE_SEL_MASK
,
107 .core_en_shift
= EXYNOS_TMU_CORE_EN_SHIFT
,
108 .tmu_status
= EXYNOS_TMU_REG_STATUS
,
109 .tmu_cur_temp
= EXYNOS_TMU_REG_CURRENT_TEMP
,
110 .threshold_th0
= EXYNOS_THD_TEMP_RISE
,
111 .threshold_th1
= EXYNOS_THD_TEMP_FALL
,
112 .tmu_inten
= EXYNOS_TMU_REG_INTEN
,
113 .inten_rise_mask
= EXYNOS_TMU_RISE_INT_MASK
,
114 .inten_rise_shift
= EXYNOS_TMU_RISE_INT_SHIFT
,
115 .inten_fall_mask
= EXYNOS_TMU_FALL_INT_MASK
,
116 .inten_fall_shift
= EXYNOS_TMU_FALL_INT_SHIFT
,
117 .inten_rise0_shift
= EXYNOS_TMU_INTEN_RISE0_SHIFT
,
118 .inten_rise1_shift
= EXYNOS_TMU_INTEN_RISE1_SHIFT
,
119 .inten_rise2_shift
= EXYNOS_TMU_INTEN_RISE2_SHIFT
,
120 .inten_rise3_shift
= EXYNOS_TMU_INTEN_RISE3_SHIFT
,
121 .inten_fall0_shift
= EXYNOS_TMU_INTEN_FALL0_SHIFT
,
122 .tmu_intstat
= EXYNOS_TMU_REG_INTSTAT
,
123 .tmu_intclear
= EXYNOS_TMU_REG_INTCLEAR
,
124 .emul_con
= EXYNOS_EMUL_CON
,
125 .emul_temp_shift
= EXYNOS_EMUL_DATA_SHIFT
,
126 .emul_time_shift
= EXYNOS_EMUL_TIME_SHIFT
,
127 .emul_time_mask
= EXYNOS_EMUL_TIME_MASK
,
130 #define EXYNOS5250_TMU_DATA \
131 .threshold_falling = 10, \
132 .trigger_levels[0] = 85, \
133 .trigger_levels[1] = 103, \
134 .trigger_levels[2] = 110, \
135 .trigger_levels[3] = 120, \
136 .trigger_enable[0] = true, \
137 .trigger_enable[1] = true, \
138 .trigger_enable[2] = true, \
139 .trigger_enable[3] = false, \
140 .trigger_type[0] = THROTTLE_ACTIVE, \
141 .trigger_type[1] = THROTTLE_ACTIVE, \
142 .trigger_type[2] = SW_TRIP, \
143 .trigger_type[3] = HW_TRIP, \
144 .max_trigger_level = 4, \
146 .reference_voltage = 16, \
147 .noise_cancel_mode = 4, \
148 .cal_type = TYPE_ONE_POINT_TRIMMING, \
150 .min_efuse_value = 40, \
151 .max_efuse_value = 100, \
152 .first_point_trim = 25, \
153 .second_point_trim = 85, \
154 .default_temp_offset = 50, \
156 .freq_clip_max = 800 * 1000, \
160 .freq_clip_max = 200 * 1000, \
163 .freq_tab_count = 2, \
164 .type = SOC_ARCH_EXYNOS, \
165 .registers = &exynos5250_tmu_registers,
167 struct exynos_tmu_init_data
const exynos5250_default_tmu_data
= {
169 { EXYNOS5250_TMU_DATA
},