drivers/thermal/ti-soc-thermal/dra752-thermal-data.c

   1 /*
   2  * DRA752 thermal data.
   3  *
   4  * Copyright (C) 2013 Texas Instruments Inc.
   5  * Contact:
   6  *      Eduardo Valentin <eduardo.valentin@ti.com>
   7  *      Tero Kristo <t-kristo@ti.com>
   8  *
   9  * This file is partially autogenerated.
  10  *
  11  * This software is licensed under the terms of the GNU General Public
  12  * License version 2, as published by the Free Software Foundation, and
  13  * may be copied, distributed, and modified under those terms.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18  * GNU General Public License for more details.
  19  *
  20  */
  21
  22 #include "ti-thermal.h"
  23 #include "ti-bandgap.h"
  24 #include "dra752-bandgap.h"
  25
  26 /*
  27  * DRA752 has five instances of thermal sensor: MPU, GPU, CORE,
  28  * IVA and DSPEVE need to describe the individual registers and
  29  * bit fields.
  30  */
  31
  32 /*
  33  * DRA752 CORE thermal sensor register offsets and bit-fields
  34  */
  35 static struct temp_sensor_registers
  36 dra752_core_temp_sensor_registers = {
  37         .temp_sensor_ctrl = DRA752_TEMP_SENSOR_CORE_OFFSET,
  38         .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
  39         .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
  40         .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
  41         .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
  42         .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK,
  43         .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK,
  44         .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
  45         .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK,
  46         .mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_CORE_MASK,
  47         .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_CORE_MASK,
  48         .bgap_threshold = DRA752_BANDGAP_THRESHOLD_CORE_OFFSET,
  49         .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
  50         .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
  51         .tshut_threshold = DRA752_BANDGAP_TSHUT_CORE_OFFSET,
  52         .tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
  53         .tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
  54         .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
  55         .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
  56         .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK,
  57         .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK,
  58         .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_CORE_OFFSET,
  59         .ctrl_dtemp_0 = DRA752_DTEMP_CORE_0_OFFSET,
  60         .ctrl_dtemp_1 = DRA752_DTEMP_CORE_1_OFFSET,
  61         .ctrl_dtemp_2 = DRA752_DTEMP_CORE_2_OFFSET,
  62         .ctrl_dtemp_3 = DRA752_DTEMP_CORE_3_OFFSET,
  63         .ctrl_dtemp_4 = DRA752_DTEMP_CORE_4_OFFSET,
  64         .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET,
  65 };
  66
  67 /*
  68  * DRA752 IVA thermal sensor register offsets and bit-fields
  69  */
  70 static struct temp_sensor_registers
  71 dra752_iva_temp_sensor_registers = {
  72         .temp_sensor_ctrl = DRA752_TEMP_SENSOR_IVA_OFFSET,
  73         .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
  74         .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
  75         .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
  76         .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET,
  77         .mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK,
  78         .mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK,
  79         .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
  80         .mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK,
  81         .mask_clear_mask = DRA752_BANDGAP_CTRL_2_CLEAR_IVA_MASK,
  82         .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_IVA_MASK,
  83         .bgap_threshold = DRA752_BANDGAP_THRESHOLD_IVA_OFFSET,
  84         .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
  85         .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
  86         .tshut_threshold = DRA752_BANDGAP_TSHUT_IVA_OFFSET,
  87         .tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
  88         .tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
  89         .bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,
  90         .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
  91         .status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK,
  92         .status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK,
  93         .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_IVA_OFFSET,
  94         .ctrl_dtemp_0 = DRA752_DTEMP_IVA_0_OFFSET,
  95         .ctrl_dtemp_1 = DRA752_DTEMP_IVA_1_OFFSET,
  96         .ctrl_dtemp_2 = DRA752_DTEMP_IVA_2_OFFSET,
  97         .ctrl_dtemp_3 = DRA752_DTEMP_IVA_3_OFFSET,
  98         .ctrl_dtemp_4 = DRA752_DTEMP_IVA_4_OFFSET,
  99         .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET,
 100 };
 101
 102 /*
 103  * DRA752 MPU thermal sensor register offsets and bit-fields
 104  */
 105 static struct temp_sensor_registers
 106 dra752_mpu_temp_sensor_registers = {
 107         .temp_sensor_ctrl = DRA752_TEMP_SENSOR_MPU_OFFSET,
 108         .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
 109         .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
 110         .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
 111         .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
 112         .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK,
 113         .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK,
 114         .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
 115         .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK,
 116         .mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_MPU_MASK,
 117         .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_MPU_MASK,
 118         .bgap_threshold = DRA752_BANDGAP_THRESHOLD_MPU_OFFSET,
 119         .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
 120         .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
 121         .tshut_threshold = DRA752_BANDGAP_TSHUT_MPU_OFFSET,
 122         .tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
 123         .tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
 124         .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
 125         .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
 126         .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK,
 127         .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK,
 128         .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_MPU_OFFSET,
 129         .ctrl_dtemp_0 = DRA752_DTEMP_MPU_0_OFFSET,
 130         .ctrl_dtemp_1 = DRA752_DTEMP_MPU_1_OFFSET,
 131         .ctrl_dtemp_2 = DRA752_DTEMP_MPU_2_OFFSET,
 132         .ctrl_dtemp_3 = DRA752_DTEMP_MPU_3_OFFSET,
 133         .ctrl_dtemp_4 = DRA752_DTEMP_MPU_4_OFFSET,
 134         .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET,
 135 };
 136
 137 /*
 138  * DRA752 DSPEVE thermal sensor register offsets and bit-fields
 139  */
 140 static struct temp_sensor_registers
 141 dra752_dspeve_temp_sensor_registers = {
 142         .temp_sensor_ctrl = DRA752_TEMP_SENSOR_DSPEVE_OFFSET,
 143         .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
 144         .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
 145         .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
 146         .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_2_OFFSET,
 147         .mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK,
 148         .mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK,
 149         .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
 150         .mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK,
 151         .mask_clear_mask = DRA752_BANDGAP_CTRL_2_CLEAR_DSPEVE_MASK,
 152         .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_DSPEVE_MASK,
 153         .bgap_threshold = DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET,
 154         .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
 155         .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
 156         .tshut_threshold = DRA752_BANDGAP_TSHUT_DSPEVE_OFFSET,
 157         .tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
 158         .tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
 159         .bgap_status = DRA752_BANDGAP_STATUS_2_OFFSET,
 160         .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
 161         .status_hot_mask = DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK,
 162         .status_cold_mask = DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK,
 163         .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_DSPEVE_OFFSET,
 164         .ctrl_dtemp_0 = DRA752_DTEMP_DSPEVE_0_OFFSET,
 165         .ctrl_dtemp_1 = DRA752_DTEMP_DSPEVE_1_OFFSET,
 166         .ctrl_dtemp_2 = DRA752_DTEMP_DSPEVE_2_OFFSET,
 167         .ctrl_dtemp_3 = DRA752_DTEMP_DSPEVE_3_OFFSET,
 168         .ctrl_dtemp_4 = DRA752_DTEMP_DSPEVE_4_OFFSET,
 169         .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET,
 170 };
 171
 172 /*
 173  * DRA752 GPU thermal sensor register offsets and bit-fields
 174  */
 175 static struct temp_sensor_registers
 176 dra752_gpu_temp_sensor_registers = {
 177         .temp_sensor_ctrl = DRA752_TEMP_SENSOR_GPU_OFFSET,
 178         .bgap_tempsoff_mask = DRA752_TEMP_SENSOR_TMPSOFF_MASK,
 179         .bgap_eocz_mask = DRA752_TEMP_SENSOR_EOCZ_MASK,
 180         .bgap_dtemp_mask = DRA752_TEMP_SENSOR_DTEMP_MASK,
 181         .bgap_mask_ctrl = DRA752_BANDGAP_CTRL_1_OFFSET,
 182         .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK,
 183         .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK,
 184         .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK,
 185         .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK,
 186         .mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_GPU_MASK,
 187         .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_GPU_MASK,
 188         .bgap_threshold = DRA752_BANDGAP_THRESHOLD_GPU_OFFSET,
 189         .threshold_thot_mask = DRA752_BANDGAP_THRESHOLD_HOT_MASK,
 190         .threshold_tcold_mask = DRA752_BANDGAP_THRESHOLD_COLD_MASK,
 191         .tshut_threshold = DRA752_BANDGAP_TSHUT_GPU_OFFSET,
 192         .tshut_hot_mask = DRA752_TSHUT_THRESHOLD_HOT_MASK,
 193         .tshut_cold_mask = DRA752_TSHUT_THRESHOLD_COLD_MASK,
 194         .bgap_status = DRA752_BANDGAP_STATUS_1_OFFSET,
 195         .status_bgap_alert_mask = DRA752_BANDGAP_STATUS_1_ALERT_MASK,
 196         .status_hot_mask = DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK,
 197         .status_cold_mask = DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK,
 198         .bgap_cumul_dtemp = DRA752_BANDGAP_CUMUL_DTEMP_GPU_OFFSET,
 199         .ctrl_dtemp_0 = DRA752_DTEMP_GPU_0_OFFSET,
 200         .ctrl_dtemp_1 = DRA752_DTEMP_GPU_1_OFFSET,
 201         .ctrl_dtemp_2 = DRA752_DTEMP_GPU_2_OFFSET,
 202         .ctrl_dtemp_3 = DRA752_DTEMP_GPU_3_OFFSET,
 203         .ctrl_dtemp_4 = DRA752_DTEMP_GPU_4_OFFSET,
 204         .bgap_efuse = DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET,
 205 };
 206
 207 /* Thresholds and limits for DRA752 MPU temperature sensor */
 208 static struct temp_sensor_data dra752_mpu_temp_sensor_data = {
 209         .tshut_hot = DRA752_MPU_TSHUT_HOT,
 210         .tshut_cold = DRA752_MPU_TSHUT_COLD,
 211         .t_hot = DRA752_MPU_T_HOT,
 212         .t_cold = DRA752_MPU_T_COLD,
 213         .min_freq = DRA752_MPU_MIN_FREQ,
 214         .max_freq = DRA752_MPU_MAX_FREQ,
 215         .max_temp = DRA752_MPU_MAX_TEMP,
 216         .min_temp = DRA752_MPU_MIN_TEMP,
 217         .hyst_val = DRA752_MPU_HYST_VAL,
 218         .update_int1 = 1000,
 219         .update_int2 = 2000,
 220 };
 221
 222 /* Thresholds and limits for DRA752 GPU temperature sensor */
 223 static struct temp_sensor_data dra752_gpu_temp_sensor_data = {
 224         .tshut_hot = DRA752_GPU_TSHUT_HOT,
 225         .tshut_cold = DRA752_GPU_TSHUT_COLD,
 226         .t_hot = DRA752_GPU_T_HOT,
 227         .t_cold = DRA752_GPU_T_COLD,
 228         .min_freq = DRA752_GPU_MIN_FREQ,
 229         .max_freq = DRA752_GPU_MAX_FREQ,
 230         .max_temp = DRA752_GPU_MAX_TEMP,
 231         .min_temp = DRA752_GPU_MIN_TEMP,
 232         .hyst_val = DRA752_GPU_HYST_VAL,
 233         .update_int1 = 1000,
 234         .update_int2 = 2000,
 235 };
 236
 237 /* Thresholds and limits for DRA752 CORE temperature sensor */
 238 static struct temp_sensor_data dra752_core_temp_sensor_data = {
 239         .tshut_hot = DRA752_CORE_TSHUT_HOT,
 240         .tshut_cold = DRA752_CORE_TSHUT_COLD,
 241         .t_hot = DRA752_CORE_T_HOT,
 242         .t_cold = DRA752_CORE_T_COLD,
 243         .min_freq = DRA752_CORE_MIN_FREQ,
 244         .max_freq = DRA752_CORE_MAX_FREQ,
 245         .max_temp = DRA752_CORE_MAX_TEMP,
 246         .min_temp = DRA752_CORE_MIN_TEMP,
 247         .hyst_val = DRA752_CORE_HYST_VAL,
 248         .update_int1 = 1000,
 249         .update_int2 = 2000,
 250 };
 251
 252 /* Thresholds and limits for DRA752 DSPEVE temperature sensor */
 253 static struct temp_sensor_data dra752_dspeve_temp_sensor_data = {
 254         .tshut_hot = DRA752_DSPEVE_TSHUT_HOT,
 255         .tshut_cold = DRA752_DSPEVE_TSHUT_COLD,
 256         .t_hot = DRA752_DSPEVE_T_HOT,
 257         .t_cold = DRA752_DSPEVE_T_COLD,
 258         .min_freq = DRA752_DSPEVE_MIN_FREQ,
 259         .max_freq = DRA752_DSPEVE_MAX_FREQ,
 260         .max_temp = DRA752_DSPEVE_MAX_TEMP,
 261         .min_temp = DRA752_DSPEVE_MIN_TEMP,
 262         .hyst_val = DRA752_DSPEVE_HYST_VAL,
 263         .update_int1 = 1000,
 264         .update_int2 = 2000,
 265 };
 266
 267 /* Thresholds and limits for DRA752 IVA temperature sensor */
 268 static struct temp_sensor_data dra752_iva_temp_sensor_data = {
 269         .tshut_hot = DRA752_IVA_TSHUT_HOT,
 270         .tshut_cold = DRA752_IVA_TSHUT_COLD,
 271         .t_hot = DRA752_IVA_T_HOT,
 272         .t_cold = DRA752_IVA_T_COLD,
 273         .min_freq = DRA752_IVA_MIN_FREQ,
 274         .max_freq = DRA752_IVA_MAX_FREQ,
 275         .max_temp = DRA752_IVA_MAX_TEMP,
 276         .min_temp = DRA752_IVA_MIN_TEMP,
 277         .hyst_val = DRA752_IVA_HYST_VAL,
 278         .update_int1 = 1000,
 279         .update_int2 = 2000,
 280 };
 281
 282 /*
 283  * DRA752 : Temperature values in milli degree celsius
 284  * ADC code values from 540 to 945
 285  */
 286 static
 287 int dra752_adc_to_temp[DRA752_ADC_END_VALUE - DRA752_ADC_START_VALUE + 1] = {
 288         /* Index 540 - 549 */
 289         -40000, -40000, -40000, -40000, -39800, -39400, -39000, -38600, -38200,
 290         -37800,
 291         /* Index 550 - 559 */
 292         -37400, -37000, -36600, -36200, -35800, -35300, -34700, -34200, -33800,
 293         -33400,
 294         /* Index 560 - 569 */
 295         -33000, -32600, -32200, -31800, -31400, -31000, -30600, -30200, -29800,
 296         -29400,
 297         /* Index 570 - 579 */
 298         -29000, -28600, -28200, -27700, -27100, -26600, -26200, -25800, -25400,
 299         -25000,
 300         /* Index 580 - 589 */
 301         -24600, -24200, -23800, -23400, -23000, -22600, -22200, -21800, -21400,
 302         -21000,
 303         /* Index 590 - 599 */
 304         -20500, -19900, -19400, -19000, -18600, -18200, -17800, -17400, -17000,
 305         -16600,
 306         /* Index 600 - 609 */
 307         -16200, -15800, -15400, -15000, -14600, -14200, -13800, -13400, -13000,
 308         -12500,
 309         /* Index 610 - 619 */
 310         -11900, -11400, -11000, -10600, -10200, -9800, -9400, -9000, -8600,
 311         -8200,
 312         /* Index 620 - 629 */
 313         -7800, -7400, -7000, -6600, -6200, -5800, -5400, -5000, -4500,
 314         -3900,
 315         /* Index 630 - 639 */
 316         -3400, -3000, -2600, -2200, -1800, -1400, -1000, -600, -200,
 317         200,
 318         /* Index 640 - 649 */
 319         600, 1000, 1400, 1800, 2200, 2600, 3000, 3400, 3900,
 320         4500,
 321         /* Index 650 - 659 */
 322         5000, 5400, 5800, 6200, 6600, 7000, 7400, 7800, 8200,
 323         8600,
 324         /* Index 660 - 669 */
 325         9000, 9400, 9800, 10200, 10600, 11000, 11400, 11800, 12200,
 326         12700,
 327         /* Index 670 - 679 */
 328         13300, 13800, 14200, 14600, 15000, 15400, 15800, 16200, 16600,
 329         17000,
 330         /* Index 680 - 689 */
 331         17400, 17800, 18200, 18600, 19000, 19400, 19800, 20200, 20600,
 332         21000,
 333         /* Index 690 - 699 */
 334         21400, 21900, 22500, 23000, 23400, 23800, 24200, 24600, 25000,
 335         25400,
 336         /* Index 700 - 709 */
 337         25800, 26200, 26600, 27000, 27400, 27800, 28200, 28600, 29000,
 338         29400,
 339         /* Index 710 - 719 */
 340         29800, 30200, 30600, 31000, 31400, 31900, 32500, 33000, 33400,
 341         33800,
 342         /* Index 720 - 729 */
 343         34200, 34600, 35000, 35400, 35800, 36200, 36600, 37000, 37400,
 344         37800,
 345         /* Index 730 - 739 */
 346         38200, 38600, 39000, 39400, 39800, 40200, 40600, 41000, 41400,
 347         41800,
 348         /* Index 740 - 749 */
 349         42200, 42600, 43100, 43700, 44200, 44600, 45000, 45400, 45800,
 350         46200,
 351         /* Index 750 - 759 */
 352         46600, 47000, 47400, 47800, 48200, 48600, 49000, 49400, 49800,
 353         50200,
 354         /* Index 760 - 769 */
 355         50600, 51000, 51400, 51800, 52200, 52600, 53000, 53400, 53800,
 356         54200,
 357         /* Index 770 - 779 */
 358         54600, 55000, 55400, 55900, 56500, 57000, 57400, 57800, 58200,
 359         58600,
 360         /* Index 780 - 789 */
 361         59000, 59400, 59800, 60200, 60600, 61000, 61400, 61800, 62200,
 362         62600,
 363         /* Index 790 - 799 */
 364         63000, 63400, 63800, 64200, 64600, 65000, 65400, 65800, 66200,
 365         66600,
 366         /* Index 800 - 809 */
 367         67000, 67400, 67800, 68200, 68600, 69000, 69400, 69800, 70200,
 368         70600,
 369         /* Index 810 - 819 */
 370         71000, 71500, 72100, 72600, 73000, 73400, 73800, 74200, 74600,
 371         75000,
 372         /* Index 820 - 829 */
 373         75400, 75800, 76200, 76600, 77000, 77400, 77800, 78200, 78600,
 374         79000,
 375         /* Index 830 - 839 */
 376         79400, 79800, 80200, 80600, 81000, 81400, 81800, 82200, 82600,
 377         83000,
 378         /* Index 840 - 849 */
 379         83400, 83800, 84200, 84600, 85000, 85400, 85800, 86200, 86600,
 380         87000,
 381         /* Index 850 - 859 */
 382         87400, 87800, 88200, 88600, 89000, 89400, 89800, 90200, 90600,
 383         91000,
 384         /* Index 860 - 869 */
 385         91400, 91800, 92200, 92600, 93000, 93400, 93800, 94200, 94600,
 386         95000,
 387         /* Index 870 - 879 */
 388         95400, 95800, 96200, 96600, 97000, 97500, 98100, 98600, 99000,
 389         99400,
 390         /* Index 880 - 889 */
 391         99800, 100200, 100600, 101000, 101400, 101800, 102200, 102600, 103000,
 392         103400,
 393         /* Index 890 - 899 */
 394         103800, 104200, 104600, 105000, 105400, 105800, 106200, 106600, 107000,
 395         107400,
 396         /* Index 900 - 909 */
 397         107800, 108200, 108600, 109000, 109400, 109800, 110200, 110600, 111000,
 398         111400,
 399         /* Index 910 - 919 */
 400         111800, 112200, 112600, 113000, 113400, 113800, 114200, 114600, 115000,
 401         115400,
 402         /* Index 920 - 929 */
 403         115800, 116200, 116600, 117000, 117400, 117800, 118200, 118600, 119000,
 404         119400,
 405         /* Index 930 - 939 */
 406         119800, 120200, 120600, 121000, 121400, 121800, 122200, 122600, 123000,
 407         123400,
 408         /* Index 940 - 945 */
 409         123800, 124200, 124600, 124900, 125000, 125000,
 410 };
 411
 412 /* DRA752 data */
 413 const struct ti_bandgap_data dra752_data = {
 414         .features = TI_BANDGAP_FEATURE_TSHUT_CONFIG |
 415                         TI_BANDGAP_FEATURE_FREEZE_BIT |
 416                         TI_BANDGAP_FEATURE_TALERT |
 417                         TI_BANDGAP_FEATURE_COUNTER_DELAY |
 418                         TI_BANDGAP_FEATURE_HISTORY_BUFFER,
 419         .fclock_name = "l3instr_ts_gclk_div",
 420         .div_ck_name = "l3instr_ts_gclk_div",
 421         .conv_table = dra752_adc_to_temp,
 422         .adc_start_val = DRA752_ADC_START_VALUE,
 423         .adc_end_val = DRA752_ADC_END_VALUE,
 424         .expose_sensor = ti_thermal_expose_sensor,
 425         .remove_sensor = ti_thermal_remove_sensor,
 426         .sensors = {
 427                 {
 428                 .registers = &dra752_mpu_temp_sensor_registers,
 429                 .ts_data = &dra752_mpu_temp_sensor_data,
 430                 .domain = "cpu",
 431                 .register_cooling = ti_thermal_register_cpu_cooling,
 432                 .unregister_cooling = ti_thermal_unregister_cpu_cooling,
 433                 .slope = DRA752_GRADIENT_SLOPE,
 434                 .constant = DRA752_GRADIENT_CONST,
 435                 .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
 436                 .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
 437                 },
 438                 {
 439                 .registers = &dra752_gpu_temp_sensor_registers,
 440                 .ts_data = &dra752_gpu_temp_sensor_data,
 441                 .domain = "gpu",
 442                 .slope = DRA752_GRADIENT_SLOPE,
 443                 .constant = DRA752_GRADIENT_CONST,
 444                 .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
 445                 .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
 446                 },
 447                 {
 448                 .registers = &dra752_core_temp_sensor_registers,
 449                 .ts_data = &dra752_core_temp_sensor_data,
 450                 .domain = "core",
 451                 .slope = DRA752_GRADIENT_SLOPE,
 452                 .constant = DRA752_GRADIENT_CONST,
 453                 .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
 454                 .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
 455                 },
 456                 {
 457                 .registers = &dra752_dspeve_temp_sensor_registers,
 458                 .ts_data = &dra752_dspeve_temp_sensor_data,
 459                 .domain = "dspeve",
 460                 .slope = DRA752_GRADIENT_SLOPE,
 461                 .constant = DRA752_GRADIENT_CONST,
 462                 .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
 463                 .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
 464                 },
 465                 {
 466                 .registers = &dra752_iva_temp_sensor_registers,
 467                 .ts_data = &dra752_iva_temp_sensor_data,
 468                 .domain = "iva",
 469                 .slope = DRA752_GRADIENT_SLOPE,
 470                 .constant = DRA752_GRADIENT_CONST,
 471                 .slope_pcb = DRA752_GRADIENT_SLOPE_W_PCB,
 472                 .constant_pcb = DRA752_GRADIENT_CONST_W_PCB,
 473                 },
 474         },
 475         .sensor_count = 5,
 476 };