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tty: Remove ASYNC_CLOSING checks in open()/hangup() methods
[deliverable/linux.git] / drivers / tty / rocket.c
1 /*
2 * RocketPort device driver for Linux
3 *
4 * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
5 *
6 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23 /*
24 * Kernel Synchronization:
25 *
26 * This driver has 2 kernel control paths - exception handlers (calls into the driver
27 * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
28 * are not used.
29 *
30 * Critical data:
31 * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
32 * serial port state information and the xmit_buf circular buffer. Protected by
33 * a per port spinlock.
34 * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
35 * is data to be transmitted. Protected by atomic bit operations.
36 * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
37 *
38 * rp_write() and rp_write_char() functions use a per port semaphore to protect against
39 * simultaneous access to the same port by more than one process.
40 */
41
42 /****** Defines ******/
43 #define ROCKET_PARANOIA_CHECK
44 #define ROCKET_DISABLE_SIMUSAGE
45
46 #undef ROCKET_SOFT_FLOW
47 #undef ROCKET_DEBUG_OPEN
48 #undef ROCKET_DEBUG_INTR
49 #undef ROCKET_DEBUG_WRITE
50 #undef ROCKET_DEBUG_FLOW
51 #undef ROCKET_DEBUG_THROTTLE
52 #undef ROCKET_DEBUG_WAIT_UNTIL_SENT
53 #undef ROCKET_DEBUG_RECEIVE
54 #undef ROCKET_DEBUG_HANGUP
55 #undef REV_PCI_ORDER
56 #undef ROCKET_DEBUG_IO
57
58 #define POLL_PERIOD (HZ/100) /* Polling period .01 seconds (10ms) */
59
60 /****** Kernel includes ******/
61
62 #include <linux/module.h>
63 #include <linux/errno.h>
64 #include <linux/major.h>
65 #include <linux/kernel.h>
66 #include <linux/signal.h>
67 #include <linux/slab.h>
68 #include <linux/mm.h>
69 #include <linux/sched.h>
70 #include <linux/timer.h>
71 #include <linux/interrupt.h>
72 #include <linux/tty.h>
73 #include <linux/tty_driver.h>
74 #include <linux/tty_flip.h>
75 #include <linux/serial.h>
76 #include <linux/string.h>
77 #include <linux/fcntl.h>
78 #include <linux/ptrace.h>
79 #include <linux/mutex.h>
80 #include <linux/ioport.h>
81 #include <linux/delay.h>
82 #include <linux/completion.h>
83 #include <linux/wait.h>
84 #include <linux/pci.h>
85 #include <linux/uaccess.h>
86 #include <linux/atomic.h>
87 #include <asm/unaligned.h>
88 #include <linux/bitops.h>
89 #include <linux/spinlock.h>
90 #include <linux/init.h>
91
92 /****** RocketPort includes ******/
93
94 #include "rocket_int.h"
95 #include "rocket.h"
96
97 #define ROCKET_VERSION "2.09"
98 #define ROCKET_DATE "12-June-2003"
99
100 /****** RocketPort Local Variables ******/
101
102 static void rp_do_poll(unsigned long dummy);
103
104 static struct tty_driver *rocket_driver;
105
106 static struct rocket_version driver_version = {
107 ROCKET_VERSION, ROCKET_DATE
108 };
109
110 static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
111 static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
112 /* eg. Bit 0 indicates port 0 has xmit data, ... */
113 static atomic_t rp_num_ports_open; /* Number of serial ports open */
114 static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
115
116 static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
117 static unsigned long board2;
118 static unsigned long board3;
119 static unsigned long board4;
120 static unsigned long controller;
121 static bool support_low_speed;
122 static unsigned long modem1;
123 static unsigned long modem2;
124 static unsigned long modem3;
125 static unsigned long modem4;
126 static unsigned long pc104_1[8];
127 static unsigned long pc104_2[8];
128 static unsigned long pc104_3[8];
129 static unsigned long pc104_4[8];
130 static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
131
132 static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
133 static unsigned long rcktpt_io_addr[NUM_BOARDS];
134 static int rcktpt_type[NUM_BOARDS];
135 static int is_PCI[NUM_BOARDS];
136 static rocketModel_t rocketModel[NUM_BOARDS];
137 static int max_board;
138 static const struct tty_port_operations rocket_port_ops;
139
140 /*
141 * The following arrays define the interrupt bits corresponding to each AIOP.
142 * These bits are different between the ISA and regular PCI boards and the
143 * Universal PCI boards.
144 */
145
146 static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
147 AIOP_INTR_BIT_0,
148 AIOP_INTR_BIT_1,
149 AIOP_INTR_BIT_2,
150 AIOP_INTR_BIT_3
151 };
152
153 #ifdef CONFIG_PCI
154 static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
155 UPCI_AIOP_INTR_BIT_0,
156 UPCI_AIOP_INTR_BIT_1,
157 UPCI_AIOP_INTR_BIT_2,
158 UPCI_AIOP_INTR_BIT_3
159 };
160 #endif
161
162 static Byte_t RData[RDATASIZE] = {
163 0x00, 0x09, 0xf6, 0x82,
164 0x02, 0x09, 0x86, 0xfb,
165 0x04, 0x09, 0x00, 0x0a,
166 0x06, 0x09, 0x01, 0x0a,
167 0x08, 0x09, 0x8a, 0x13,
168 0x0a, 0x09, 0xc5, 0x11,
169 0x0c, 0x09, 0x86, 0x85,
170 0x0e, 0x09, 0x20, 0x0a,
171 0x10, 0x09, 0x21, 0x0a,
172 0x12, 0x09, 0x41, 0xff,
173 0x14, 0x09, 0x82, 0x00,
174 0x16, 0x09, 0x82, 0x7b,
175 0x18, 0x09, 0x8a, 0x7d,
176 0x1a, 0x09, 0x88, 0x81,
177 0x1c, 0x09, 0x86, 0x7a,
178 0x1e, 0x09, 0x84, 0x81,
179 0x20, 0x09, 0x82, 0x7c,
180 0x22, 0x09, 0x0a, 0x0a
181 };
182
183 static Byte_t RRegData[RREGDATASIZE] = {
184 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
185 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
186 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
187 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
188 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
189 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
190 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
191 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
192 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
193 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
194 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
195 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
196 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
197 };
198
199 static CONTROLLER_T sController[CTL_SIZE] = {
200 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
201 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
202 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
203 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
204 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
205 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
206 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
207 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
208 };
209
210 static Byte_t sBitMapClrTbl[8] = {
211 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
212 };
213
214 static Byte_t sBitMapSetTbl[8] = {
215 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
216 };
217
218 static int sClockPrescale = 0x14;
219
220 /*
221 * Line number is the ttySIx number (x), the Minor number. We
222 * assign them sequentially, starting at zero. The following
223 * array keeps track of the line number assigned to a given board/aiop/channel.
224 */
225 static unsigned char lineNumbers[MAX_RP_PORTS];
226 static unsigned long nextLineNumber;
227
228 /***** RocketPort Static Prototypes *********/
229 static int __init init_ISA(int i);
230 static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
231 static void rp_flush_buffer(struct tty_struct *tty);
232 static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
233 static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
234 static void rp_start(struct tty_struct *tty);
235 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
236 int ChanNum);
237 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
238 static void sFlushRxFIFO(CHANNEL_T * ChP);
239 static void sFlushTxFIFO(CHANNEL_T * ChP);
240 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
241 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
242 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
243 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
244 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
245 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
246 ByteIO_t * AiopIOList, int AiopIOListSize,
247 int IRQNum, Byte_t Frequency, int PeriodicOnly);
248 static int sReadAiopID(ByteIO_t io);
249 static int sReadAiopNumChan(WordIO_t io);
250
251 MODULE_AUTHOR("Theodore Ts'o");
252 MODULE_DESCRIPTION("Comtrol RocketPort driver");
253 module_param(board1, ulong, 0);
254 MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
255 module_param(board2, ulong, 0);
256 MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
257 module_param(board3, ulong, 0);
258 MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
259 module_param(board4, ulong, 0);
260 MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
261 module_param(controller, ulong, 0);
262 MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
263 module_param(support_low_speed, bool, 0);
264 MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
265 module_param(modem1, ulong, 0);
266 MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
267 module_param(modem2, ulong, 0);
268 MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
269 module_param(modem3, ulong, 0);
270 MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
271 module_param(modem4, ulong, 0);
272 MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
273 module_param_array(pc104_1, ulong, NULL, 0);
274 MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
275 module_param_array(pc104_2, ulong, NULL, 0);
276 MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
277 module_param_array(pc104_3, ulong, NULL, 0);
278 MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
279 module_param_array(pc104_4, ulong, NULL, 0);
280 MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
281
282 static int rp_init(void);
283 static void rp_cleanup_module(void);
284
285 module_init(rp_init);
286 module_exit(rp_cleanup_module);
287
288
289 MODULE_LICENSE("Dual BSD/GPL");
290
291 /*************************************************************************/
292 /* Module code starts here */
293
294 static inline int rocket_paranoia_check(struct r_port *info,
295 const char *routine)
296 {
297 #ifdef ROCKET_PARANOIA_CHECK
298 if (!info)
299 return 1;
300 if (info->magic != RPORT_MAGIC) {
301 printk(KERN_WARNING "Warning: bad magic number for rocketport "
302 "struct in %s\n", routine);
303 return 1;
304 }
305 #endif
306 return 0;
307 }
308
309
310 /* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
311 * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
312 * tty layer.
313 */
314 static void rp_do_receive(struct r_port *info, CHANNEL_t *cp,
315 unsigned int ChanStatus)
316 {
317 unsigned int CharNStat;
318 int ToRecv, wRecv, space;
319 unsigned char *cbuf;
320
321 ToRecv = sGetRxCnt(cp);
322 #ifdef ROCKET_DEBUG_INTR
323 printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
324 #endif
325 if (ToRecv == 0)
326 return;
327
328 /*
329 * if status indicates there are errored characters in the
330 * FIFO, then enter status mode (a word in FIFO holds
331 * character and status).
332 */
333 if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
334 if (!(ChanStatus & STATMODE)) {
335 #ifdef ROCKET_DEBUG_RECEIVE
336 printk(KERN_INFO "Entering STATMODE...\n");
337 #endif
338 ChanStatus |= STATMODE;
339 sEnRxStatusMode(cp);
340 }
341 }
342
343 /*
344 * if we previously entered status mode, then read down the
345 * FIFO one word at a time, pulling apart the character and
346 * the status. Update error counters depending on status
347 */
348 if (ChanStatus & STATMODE) {
349 #ifdef ROCKET_DEBUG_RECEIVE
350 printk(KERN_INFO "Ignore %x, read %x...\n",
351 info->ignore_status_mask, info->read_status_mask);
352 #endif
353 while (ToRecv) {
354 char flag;
355
356 CharNStat = sInW(sGetTxRxDataIO(cp));
357 #ifdef ROCKET_DEBUG_RECEIVE
358 printk(KERN_INFO "%x...\n", CharNStat);
359 #endif
360 if (CharNStat & STMBREAKH)
361 CharNStat &= ~(STMFRAMEH | STMPARITYH);
362 if (CharNStat & info->ignore_status_mask) {
363 ToRecv--;
364 continue;
365 }
366 CharNStat &= info->read_status_mask;
367 if (CharNStat & STMBREAKH)
368 flag = TTY_BREAK;
369 else if (CharNStat & STMPARITYH)
370 flag = TTY_PARITY;
371 else if (CharNStat & STMFRAMEH)
372 flag = TTY_FRAME;
373 else if (CharNStat & STMRCVROVRH)
374 flag = TTY_OVERRUN;
375 else
376 flag = TTY_NORMAL;
377 tty_insert_flip_char(&info->port, CharNStat & 0xff,
378 flag);
379 ToRecv--;
380 }
381
382 /*
383 * after we've emptied the FIFO in status mode, turn
384 * status mode back off
385 */
386 if (sGetRxCnt(cp) == 0) {
387 #ifdef ROCKET_DEBUG_RECEIVE
388 printk(KERN_INFO "Status mode off.\n");
389 #endif
390 sDisRxStatusMode(cp);
391 }
392 } else {
393 /*
394 * we aren't in status mode, so read down the FIFO two
395 * characters at time by doing repeated word IO
396 * transfer.
397 */
398 space = tty_prepare_flip_string(&info->port, &cbuf, ToRecv);
399 if (space < ToRecv) {
400 #ifdef ROCKET_DEBUG_RECEIVE
401 printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
402 #endif
403 if (space <= 0)
404 return;
405 ToRecv = space;
406 }
407 wRecv = ToRecv >> 1;
408 if (wRecv)
409 sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
410 if (ToRecv & 1)
411 cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
412 }
413 /* Push the data up to the tty layer */
414 tty_flip_buffer_push(&info->port);
415 }
416
417 /*
418 * Serial port transmit data function. Called from the timer polling loop as a
419 * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
420 * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
421 * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
422 */
423 static void rp_do_transmit(struct r_port *info)
424 {
425 int c;
426 CHANNEL_t *cp = &info->channel;
427 struct tty_struct *tty;
428 unsigned long flags;
429
430 #ifdef ROCKET_DEBUG_INTR
431 printk(KERN_DEBUG "%s\n", __func__);
432 #endif
433 if (!info)
434 return;
435 tty = tty_port_tty_get(&info->port);
436
437 if (tty == NULL) {
438 printk(KERN_WARNING "rp: WARNING %s called with tty==NULL\n", __func__);
439 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
440 return;
441 }
442
443 spin_lock_irqsave(&info->slock, flags);
444 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
445
446 /* Loop sending data to FIFO until done or FIFO full */
447 while (1) {
448 if (tty->stopped)
449 break;
450 c = min(info->xmit_fifo_room, info->xmit_cnt);
451 c = min(c, XMIT_BUF_SIZE - info->xmit_tail);
452 if (c <= 0 || info->xmit_fifo_room <= 0)
453 break;
454 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
455 if (c & 1)
456 sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
457 info->xmit_tail += c;
458 info->xmit_tail &= XMIT_BUF_SIZE - 1;
459 info->xmit_cnt -= c;
460 info->xmit_fifo_room -= c;
461 #ifdef ROCKET_DEBUG_INTR
462 printk(KERN_INFO "tx %d chars...\n", c);
463 #endif
464 }
465
466 if (info->xmit_cnt == 0)
467 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
468
469 if (info->xmit_cnt < WAKEUP_CHARS) {
470 tty_wakeup(tty);
471 #ifdef ROCKETPORT_HAVE_POLL_WAIT
472 wake_up_interruptible(&tty->poll_wait);
473 #endif
474 }
475
476 spin_unlock_irqrestore(&info->slock, flags);
477 tty_kref_put(tty);
478
479 #ifdef ROCKET_DEBUG_INTR
480 printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
481 info->xmit_tail, info->xmit_fifo_room);
482 #endif
483 }
484
485 /*
486 * Called when a serial port signals it has read data in it's RX FIFO.
487 * It checks what interrupts are pending and services them, including
488 * receiving serial data.
489 */
490 static void rp_handle_port(struct r_port *info)
491 {
492 CHANNEL_t *cp;
493 unsigned int IntMask, ChanStatus;
494
495 if (!info)
496 return;
497
498 if ((info->port.flags & ASYNC_INITIALIZED) == 0) {
499 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
500 "info->flags & NOT_INIT\n");
501 return;
502 }
503
504 cp = &info->channel;
505
506 IntMask = sGetChanIntID(cp) & info->intmask;
507 #ifdef ROCKET_DEBUG_INTR
508 printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
509 #endif
510 ChanStatus = sGetChanStatus(cp);
511 if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
512 rp_do_receive(info, cp, ChanStatus);
513 }
514 if (IntMask & DELTA_CD) { /* CD change */
515 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
516 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
517 (ChanStatus & CD_ACT) ? "on" : "off");
518 #endif
519 if (!(ChanStatus & CD_ACT) && info->cd_status) {
520 #ifdef ROCKET_DEBUG_HANGUP
521 printk(KERN_INFO "CD drop, calling hangup.\n");
522 #endif
523 tty_port_tty_hangup(&info->port, false);
524 }
525 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
526 wake_up_interruptible(&info->port.open_wait);
527 }
528 #ifdef ROCKET_DEBUG_INTR
529 if (IntMask & DELTA_CTS) { /* CTS change */
530 printk(KERN_INFO "CTS change...\n");
531 }
532 if (IntMask & DELTA_DSR) { /* DSR change */
533 printk(KERN_INFO "DSR change...\n");
534 }
535 #endif
536 }
537
538 /*
539 * The top level polling routine. Repeats every 1/100 HZ (10ms).
540 */
541 static void rp_do_poll(unsigned long dummy)
542 {
543 CONTROLLER_t *ctlp;
544 int ctrl, aiop, ch, line;
545 unsigned int xmitmask, i;
546 unsigned int CtlMask;
547 unsigned char AiopMask;
548 Word_t bit;
549
550 /* Walk through all the boards (ctrl's) */
551 for (ctrl = 0; ctrl < max_board; ctrl++) {
552 if (rcktpt_io_addr[ctrl] <= 0)
553 continue;
554
555 /* Get a ptr to the board's control struct */
556 ctlp = sCtlNumToCtlPtr(ctrl);
557
558 /* Get the interrupt status from the board */
559 #ifdef CONFIG_PCI
560 if (ctlp->BusType == isPCI)
561 CtlMask = sPCIGetControllerIntStatus(ctlp);
562 else
563 #endif
564 CtlMask = sGetControllerIntStatus(ctlp);
565
566 /* Check if any AIOP read bits are set */
567 for (aiop = 0; CtlMask; aiop++) {
568 bit = ctlp->AiopIntrBits[aiop];
569 if (CtlMask & bit) {
570 CtlMask &= ~bit;
571 AiopMask = sGetAiopIntStatus(ctlp, aiop);
572
573 /* Check if any port read bits are set */
574 for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
575 if (AiopMask & 1) {
576
577 /* Get the line number (/dev/ttyRx number). */
578 /* Read the data from the port. */
579 line = GetLineNumber(ctrl, aiop, ch);
580 rp_handle_port(rp_table[line]);
581 }
582 }
583 }
584 }
585
586 xmitmask = xmit_flags[ctrl];
587
588 /*
589 * xmit_flags contains bit-significant flags, indicating there is data
590 * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
591 * 1, ... (32 total possible). The variable i has the aiop and ch
592 * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
593 */
594 if (xmitmask) {
595 for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
596 if (xmitmask & (1 << i)) {
597 aiop = (i & 0x18) >> 3;
598 ch = i & 0x07;
599 line = GetLineNumber(ctrl, aiop, ch);
600 rp_do_transmit(rp_table[line]);
601 }
602 }
603 }
604 }
605
606 /*
607 * Reset the timer so we get called at the next clock tick (10ms).
608 */
609 if (atomic_read(&rp_num_ports_open))
610 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
611 }
612
613 /*
614 * Initializes the r_port structure for a port, as well as enabling the port on
615 * the board.
616 * Inputs: board, aiop, chan numbers
617 */
618 static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
619 {
620 unsigned rocketMode;
621 struct r_port *info;
622 int line;
623 CONTROLLER_T *ctlp;
624
625 /* Get the next available line number */
626 line = SetLineNumber(board, aiop, chan);
627
628 ctlp = sCtlNumToCtlPtr(board);
629
630 /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
631 info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
632 if (!info) {
633 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
634 line);
635 return;
636 }
637
638 info->magic = RPORT_MAGIC;
639 info->line = line;
640 info->ctlp = ctlp;
641 info->board = board;
642 info->aiop = aiop;
643 info->chan = chan;
644 tty_port_init(&info->port);
645 info->port.ops = &rocket_port_ops;
646 init_completion(&info->close_wait);
647 info->flags &= ~ROCKET_MODE_MASK;
648 switch (pc104[board][line]) {
649 case 422:
650 info->flags |= ROCKET_MODE_RS422;
651 break;
652 case 485:
653 info->flags |= ROCKET_MODE_RS485;
654 break;
655 case 232:
656 default:
657 info->flags |= ROCKET_MODE_RS232;
658 break;
659 }
660
661 info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
662 if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
663 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
664 board, aiop, chan);
665 tty_port_destroy(&info->port);
666 kfree(info);
667 return;
668 }
669
670 rocketMode = info->flags & ROCKET_MODE_MASK;
671
672 if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
673 sEnRTSToggle(&info->channel);
674 else
675 sDisRTSToggle(&info->channel);
676
677 if (ctlp->boardType == ROCKET_TYPE_PC104) {
678 switch (rocketMode) {
679 case ROCKET_MODE_RS485:
680 sSetInterfaceMode(&info->channel, InterfaceModeRS485);
681 break;
682 case ROCKET_MODE_RS422:
683 sSetInterfaceMode(&info->channel, InterfaceModeRS422);
684 break;
685 case ROCKET_MODE_RS232:
686 default:
687 if (info->flags & ROCKET_RTS_TOGGLE)
688 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
689 else
690 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
691 break;
692 }
693 }
694 spin_lock_init(&info->slock);
695 mutex_init(&info->write_mtx);
696 rp_table[line] = info;
697 tty_port_register_device(&info->port, rocket_driver, line,
698 pci_dev ? &pci_dev->dev : NULL);
699 }
700
701 /*
702 * Configures a rocketport port according to its termio settings. Called from
703 * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
704 */
705 static void configure_r_port(struct tty_struct *tty, struct r_port *info,
706 struct ktermios *old_termios)
707 {
708 unsigned cflag;
709 unsigned long flags;
710 unsigned rocketMode;
711 int bits, baud, divisor;
712 CHANNEL_t *cp;
713 struct ktermios *t = &tty->termios;
714
715 cp = &info->channel;
716 cflag = t->c_cflag;
717
718 /* Byte size and parity */
719 if ((cflag & CSIZE) == CS8) {
720 sSetData8(cp);
721 bits = 10;
722 } else {
723 sSetData7(cp);
724 bits = 9;
725 }
726 if (cflag & CSTOPB) {
727 sSetStop2(cp);
728 bits++;
729 } else {
730 sSetStop1(cp);
731 }
732
733 if (cflag & PARENB) {
734 sEnParity(cp);
735 bits++;
736 if (cflag & PARODD) {
737 sSetOddParity(cp);
738 } else {
739 sSetEvenParity(cp);
740 }
741 } else {
742 sDisParity(cp);
743 }
744
745 /* baud rate */
746 baud = tty_get_baud_rate(tty);
747 if (!baud)
748 baud = 9600;
749 divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
750 if ((divisor >= 8192 || divisor < 0) && old_termios) {
751 baud = tty_termios_baud_rate(old_termios);
752 if (!baud)
753 baud = 9600;
754 divisor = (rp_baud_base[info->board] / baud) - 1;
755 }
756 if (divisor >= 8192 || divisor < 0) {
757 baud = 9600;
758 divisor = (rp_baud_base[info->board] / baud) - 1;
759 }
760 info->cps = baud / bits;
761 sSetBaud(cp, divisor);
762
763 /* FIXME: Should really back compute a baud rate from the divisor */
764 tty_encode_baud_rate(tty, baud, baud);
765
766 if (cflag & CRTSCTS) {
767 info->intmask |= DELTA_CTS;
768 sEnCTSFlowCtl(cp);
769 } else {
770 info->intmask &= ~DELTA_CTS;
771 sDisCTSFlowCtl(cp);
772 }
773 if (cflag & CLOCAL) {
774 info->intmask &= ~DELTA_CD;
775 } else {
776 spin_lock_irqsave(&info->slock, flags);
777 if (sGetChanStatus(cp) & CD_ACT)
778 info->cd_status = 1;
779 else
780 info->cd_status = 0;
781 info->intmask |= DELTA_CD;
782 spin_unlock_irqrestore(&info->slock, flags);
783 }
784
785 /*
786 * Handle software flow control in the board
787 */
788 #ifdef ROCKET_SOFT_FLOW
789 if (I_IXON(tty)) {
790 sEnTxSoftFlowCtl(cp);
791 if (I_IXANY(tty)) {
792 sEnIXANY(cp);
793 } else {
794 sDisIXANY(cp);
795 }
796 sSetTxXONChar(cp, START_CHAR(tty));
797 sSetTxXOFFChar(cp, STOP_CHAR(tty));
798 } else {
799 sDisTxSoftFlowCtl(cp);
800 sDisIXANY(cp);
801 sClrTxXOFF(cp);
802 }
803 #endif
804
805 /*
806 * Set up ignore/read mask words
807 */
808 info->read_status_mask = STMRCVROVRH | 0xFF;
809 if (I_INPCK(tty))
810 info->read_status_mask |= STMFRAMEH | STMPARITYH;
811 if (I_BRKINT(tty) || I_PARMRK(tty))
812 info->read_status_mask |= STMBREAKH;
813
814 /*
815 * Characters to ignore
816 */
817 info->ignore_status_mask = 0;
818 if (I_IGNPAR(tty))
819 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
820 if (I_IGNBRK(tty)) {
821 info->ignore_status_mask |= STMBREAKH;
822 /*
823 * If we're ignoring parity and break indicators,
824 * ignore overruns too. (For real raw support).
825 */
826 if (I_IGNPAR(tty))
827 info->ignore_status_mask |= STMRCVROVRH;
828 }
829
830 rocketMode = info->flags & ROCKET_MODE_MASK;
831
832 if ((info->flags & ROCKET_RTS_TOGGLE)
833 || (rocketMode == ROCKET_MODE_RS485))
834 sEnRTSToggle(cp);
835 else
836 sDisRTSToggle(cp);
837
838 sSetRTS(&info->channel);
839
840 if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
841 switch (rocketMode) {
842 case ROCKET_MODE_RS485:
843 sSetInterfaceMode(cp, InterfaceModeRS485);
844 break;
845 case ROCKET_MODE_RS422:
846 sSetInterfaceMode(cp, InterfaceModeRS422);
847 break;
848 case ROCKET_MODE_RS232:
849 default:
850 if (info->flags & ROCKET_RTS_TOGGLE)
851 sSetInterfaceMode(cp, InterfaceModeRS232T);
852 else
853 sSetInterfaceMode(cp, InterfaceModeRS232);
854 break;
855 }
856 }
857 }
858
859 static int carrier_raised(struct tty_port *port)
860 {
861 struct r_port *info = container_of(port, struct r_port, port);
862 return (sGetChanStatusLo(&info->channel) & CD_ACT) ? 1 : 0;
863 }
864
865 static void dtr_rts(struct tty_port *port, int on)
866 {
867 struct r_port *info = container_of(port, struct r_port, port);
868 if (on) {
869 sSetDTR(&info->channel);
870 sSetRTS(&info->channel);
871 } else {
872 sClrDTR(&info->channel);
873 sClrRTS(&info->channel);
874 }
875 }
876
877 /*
878 * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
879 * port's r_port struct. Initializes the port hardware.
880 */
881 static int rp_open(struct tty_struct *tty, struct file *filp)
882 {
883 struct r_port *info;
884 struct tty_port *port;
885 int retval;
886 CHANNEL_t *cp;
887 unsigned long page;
888
889 info = rp_table[tty->index];
890 if (info == NULL)
891 return -ENXIO;
892 port = &info->port;
893
894 page = __get_free_page(GFP_KERNEL);
895 if (!page)
896 return -ENOMEM;
897
898 /*
899 * We must not sleep from here until the port is marked fully in use.
900 */
901 if (info->xmit_buf)
902 free_page(page);
903 else
904 info->xmit_buf = (unsigned char *) page;
905
906 tty->driver_data = info;
907 tty_port_tty_set(port, tty);
908
909 if (port->count++ == 0) {
910 atomic_inc(&rp_num_ports_open);
911
912 #ifdef ROCKET_DEBUG_OPEN
913 printk(KERN_INFO "rocket mod++ = %d...\n",
914 atomic_read(&rp_num_ports_open));
915 #endif
916 }
917 #ifdef ROCKET_DEBUG_OPEN
918 printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->port.count);
919 #endif
920
921 /*
922 * Info->count is now 1; so it's safe to sleep now.
923 */
924 if (!test_bit(ASYNCB_INITIALIZED, &port->flags)) {
925 cp = &info->channel;
926 sSetRxTrigger(cp, TRIG_1);
927 if (sGetChanStatus(cp) & CD_ACT)
928 info->cd_status = 1;
929 else
930 info->cd_status = 0;
931 sDisRxStatusMode(cp);
932 sFlushRxFIFO(cp);
933 sFlushTxFIFO(cp);
934
935 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
936 sSetRxTrigger(cp, TRIG_1);
937
938 sGetChanStatus(cp);
939 sDisRxStatusMode(cp);
940 sClrTxXOFF(cp);
941
942 sDisCTSFlowCtl(cp);
943 sDisTxSoftFlowCtl(cp);
944
945 sEnRxFIFO(cp);
946 sEnTransmit(cp);
947
948 set_bit(ASYNCB_INITIALIZED, &info->port.flags);
949
950 /*
951 * Set up the tty->alt_speed kludge
952 */
953 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
954 tty->alt_speed = 57600;
955 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
956 tty->alt_speed = 115200;
957 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
958 tty->alt_speed = 230400;
959 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
960 tty->alt_speed = 460800;
961
962 configure_r_port(tty, info, NULL);
963 if (tty->termios.c_cflag & CBAUD) {
964 sSetDTR(cp);
965 sSetRTS(cp);
966 }
967 }
968 /* Starts (or resets) the maint polling loop */
969 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
970
971 retval = tty_port_block_til_ready(port, tty, filp);
972 if (retval) {
973 #ifdef ROCKET_DEBUG_OPEN
974 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
975 #endif
976 return retval;
977 }
978 return 0;
979 }
980
981 /*
982 * Exception handler that closes a serial port. info->port.count is considered critical.
983 */
984 static void rp_close(struct tty_struct *tty, struct file *filp)
985 {
986 struct r_port *info = tty->driver_data;
987 struct tty_port *port = &info->port;
988 int timeout;
989 CHANNEL_t *cp;
990
991 if (rocket_paranoia_check(info, "rp_close"))
992 return;
993
994 #ifdef ROCKET_DEBUG_OPEN
995 printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->port.count);
996 #endif
997
998 if (tty_port_close_start(port, tty, filp) == 0)
999 return;
1000
1001 mutex_lock(&port->mutex);
1002 cp = &info->channel;
1003 /*
1004 * Before we drop DTR, make sure the UART transmitter
1005 * has completely drained; this is especially
1006 * important if there is a transmit FIFO!
1007 */
1008 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1009 if (timeout == 0)
1010 timeout = 1;
1011 rp_wait_until_sent(tty, timeout);
1012 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1013
1014 sDisTransmit(cp);
1015 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1016 sDisCTSFlowCtl(cp);
1017 sDisTxSoftFlowCtl(cp);
1018 sClrTxXOFF(cp);
1019 sFlushRxFIFO(cp);
1020 sFlushTxFIFO(cp);
1021 sClrRTS(cp);
1022 if (C_HUPCL(tty))
1023 sClrDTR(cp);
1024
1025 rp_flush_buffer(tty);
1026
1027 tty_ldisc_flush(tty);
1028
1029 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1030
1031 /* We can't yet use tty_port_close_end as the buffer handling in this
1032 driver is a bit different to the usual */
1033
1034 if (port->blocked_open) {
1035 if (port->close_delay) {
1036 msleep_interruptible(jiffies_to_msecs(port->close_delay));
1037 }
1038 wake_up_interruptible(&port->open_wait);
1039 } else {
1040 if (info->xmit_buf) {
1041 free_page((unsigned long) info->xmit_buf);
1042 info->xmit_buf = NULL;
1043 }
1044 }
1045 spin_lock_irq(&port->lock);
1046 info->port.flags &= ~(ASYNC_INITIALIZED | ASYNC_CLOSING | ASYNC_NORMAL_ACTIVE);
1047 tty->closing = 0;
1048 spin_unlock_irq(&port->lock);
1049 mutex_unlock(&port->mutex);
1050 tty_port_tty_set(port, NULL);
1051
1052 wake_up_interruptible(&port->close_wait);
1053 complete_all(&info->close_wait);
1054 atomic_dec(&rp_num_ports_open);
1055
1056 #ifdef ROCKET_DEBUG_OPEN
1057 printk(KERN_INFO "rocket mod-- = %d...\n",
1058 atomic_read(&rp_num_ports_open));
1059 printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1060 #endif
1061
1062 }
1063
1064 static void rp_set_termios(struct tty_struct *tty,
1065 struct ktermios *old_termios)
1066 {
1067 struct r_port *info = tty->driver_data;
1068 CHANNEL_t *cp;
1069 unsigned cflag;
1070
1071 if (rocket_paranoia_check(info, "rp_set_termios"))
1072 return;
1073
1074 cflag = tty->termios.c_cflag;
1075
1076 /*
1077 * This driver doesn't support CS5 or CS6
1078 */
1079 if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1080 tty->termios.c_cflag =
1081 ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
1082 /* Or CMSPAR */
1083 tty->termios.c_cflag &= ~CMSPAR;
1084
1085 configure_r_port(tty, info, old_termios);
1086
1087 cp = &info->channel;
1088
1089 /* Handle transition to B0 status */
1090 if ((old_termios->c_cflag & CBAUD) && !(tty->termios.c_cflag & CBAUD)) {
1091 sClrDTR(cp);
1092 sClrRTS(cp);
1093 }
1094
1095 /* Handle transition away from B0 status */
1096 if (!(old_termios->c_cflag & CBAUD) && (tty->termios.c_cflag & CBAUD)) {
1097 sSetRTS(cp);
1098 sSetDTR(cp);
1099 }
1100
1101 if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios.c_cflag & CRTSCTS))
1102 rp_start(tty);
1103 }
1104
1105 static int rp_break(struct tty_struct *tty, int break_state)
1106 {
1107 struct r_port *info = tty->driver_data;
1108 unsigned long flags;
1109
1110 if (rocket_paranoia_check(info, "rp_break"))
1111 return -EINVAL;
1112
1113 spin_lock_irqsave(&info->slock, flags);
1114 if (break_state == -1)
1115 sSendBreak(&info->channel);
1116 else
1117 sClrBreak(&info->channel);
1118 spin_unlock_irqrestore(&info->slock, flags);
1119 return 0;
1120 }
1121
1122 /*
1123 * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1124 * the UPCI boards was added, it was decided to make this a function because
1125 * the macro was getting too complicated. All cases except the first one
1126 * (UPCIRingInd) are taken directly from the original macro.
1127 */
1128 static int sGetChanRI(CHANNEL_T * ChP)
1129 {
1130 CONTROLLER_t *CtlP = ChP->CtlP;
1131 int ChanNum = ChP->ChanNum;
1132 int RingInd = 0;
1133
1134 if (CtlP->UPCIRingInd)
1135 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1136 else if (CtlP->AltChanRingIndicator)
1137 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1138 else if (CtlP->boardType == ROCKET_TYPE_PC104)
1139 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1140
1141 return RingInd;
1142 }
1143
1144 /********************************************************************************************/
1145 /* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
1146
1147 /*
1148 * Returns the state of the serial modem control lines. These next 2 functions
1149 * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1150 */
1151 static int rp_tiocmget(struct tty_struct *tty)
1152 {
1153 struct r_port *info = tty->driver_data;
1154 unsigned int control, result, ChanStatus;
1155
1156 ChanStatus = sGetChanStatusLo(&info->channel);
1157 control = info->channel.TxControl[3];
1158 result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1159 ((control & SET_DTR) ? TIOCM_DTR : 0) |
1160 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1161 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1162 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1163 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1164
1165 return result;
1166 }
1167
1168 /*
1169 * Sets the modem control lines
1170 */
1171 static int rp_tiocmset(struct tty_struct *tty,
1172 unsigned int set, unsigned int clear)
1173 {
1174 struct r_port *info = tty->driver_data;
1175
1176 if (set & TIOCM_RTS)
1177 info->channel.TxControl[3] |= SET_RTS;
1178 if (set & TIOCM_DTR)
1179 info->channel.TxControl[3] |= SET_DTR;
1180 if (clear & TIOCM_RTS)
1181 info->channel.TxControl[3] &= ~SET_RTS;
1182 if (clear & TIOCM_DTR)
1183 info->channel.TxControl[3] &= ~SET_DTR;
1184
1185 out32(info->channel.IndexAddr, info->channel.TxControl);
1186 return 0;
1187 }
1188
1189 static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1190 {
1191 struct rocket_config tmp;
1192
1193 if (!retinfo)
1194 return -EFAULT;
1195 memset(&tmp, 0, sizeof (tmp));
1196 mutex_lock(&info->port.mutex);
1197 tmp.line = info->line;
1198 tmp.flags = info->flags;
1199 tmp.close_delay = info->port.close_delay;
1200 tmp.closing_wait = info->port.closing_wait;
1201 tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1202 mutex_unlock(&info->port.mutex);
1203
1204 if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1205 return -EFAULT;
1206 return 0;
1207 }
1208
1209 static int set_config(struct tty_struct *tty, struct r_port *info,
1210 struct rocket_config __user *new_info)
1211 {
1212 struct rocket_config new_serial;
1213
1214 if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1215 return -EFAULT;
1216
1217 mutex_lock(&info->port.mutex);
1218 if (!capable(CAP_SYS_ADMIN))
1219 {
1220 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK)) {
1221 mutex_unlock(&info->port.mutex);
1222 return -EPERM;
1223 }
1224 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1225 configure_r_port(tty, info, NULL);
1226 mutex_unlock(&info->port.mutex);
1227 return 0;
1228 }
1229
1230 info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1231 info->port.close_delay = new_serial.close_delay;
1232 info->port.closing_wait = new_serial.closing_wait;
1233
1234 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1235 tty->alt_speed = 57600;
1236 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1237 tty->alt_speed = 115200;
1238 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1239 tty->alt_speed = 230400;
1240 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1241 tty->alt_speed = 460800;
1242 mutex_unlock(&info->port.mutex);
1243
1244 configure_r_port(tty, info, NULL);
1245 return 0;
1246 }
1247
1248 /*
1249 * This function fills in a rocket_ports struct with information
1250 * about what boards/ports are in the system. This info is passed
1251 * to user space. See setrocket.c where the info is used to create
1252 * the /dev/ttyRx ports.
1253 */
1254 static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1255 {
1256 struct rocket_ports tmp;
1257 int board;
1258
1259 if (!retports)
1260 return -EFAULT;
1261 memset(&tmp, 0, sizeof (tmp));
1262 tmp.tty_major = rocket_driver->major;
1263
1264 for (board = 0; board < 4; board++) {
1265 tmp.rocketModel[board].model = rocketModel[board].model;
1266 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1267 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1268 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1269 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1270 }
1271 if (copy_to_user(retports, &tmp, sizeof (*retports)))
1272 return -EFAULT;
1273 return 0;
1274 }
1275
1276 static int reset_rm2(struct r_port *info, void __user *arg)
1277 {
1278 int reset;
1279
1280 if (!capable(CAP_SYS_ADMIN))
1281 return -EPERM;
1282
1283 if (copy_from_user(&reset, arg, sizeof (int)))
1284 return -EFAULT;
1285 if (reset)
1286 reset = 1;
1287
1288 if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1289 rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1290 return -EINVAL;
1291
1292 if (info->ctlp->BusType == isISA)
1293 sModemReset(info->ctlp, info->chan, reset);
1294 else
1295 sPCIModemReset(info->ctlp, info->chan, reset);
1296
1297 return 0;
1298 }
1299
1300 static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1301 {
1302 if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1303 return -EFAULT;
1304 return 0;
1305 }
1306
1307 /* IOCTL call handler into the driver */
1308 static int rp_ioctl(struct tty_struct *tty,
1309 unsigned int cmd, unsigned long arg)
1310 {
1311 struct r_port *info = tty->driver_data;
1312 void __user *argp = (void __user *)arg;
1313 int ret = 0;
1314
1315 if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1316 return -ENXIO;
1317
1318 switch (cmd) {
1319 case RCKP_GET_STRUCT:
1320 if (copy_to_user(argp, info, sizeof (struct r_port)))
1321 ret = -EFAULT;
1322 break;
1323 case RCKP_GET_CONFIG:
1324 ret = get_config(info, argp);
1325 break;
1326 case RCKP_SET_CONFIG:
1327 ret = set_config(tty, info, argp);
1328 break;
1329 case RCKP_GET_PORTS:
1330 ret = get_ports(info, argp);
1331 break;
1332 case RCKP_RESET_RM2:
1333 ret = reset_rm2(info, argp);
1334 break;
1335 case RCKP_GET_VERSION:
1336 ret = get_version(info, argp);
1337 break;
1338 default:
1339 ret = -ENOIOCTLCMD;
1340 }
1341 return ret;
1342 }
1343
1344 static void rp_send_xchar(struct tty_struct *tty, char ch)
1345 {
1346 struct r_port *info = tty->driver_data;
1347 CHANNEL_t *cp;
1348
1349 if (rocket_paranoia_check(info, "rp_send_xchar"))
1350 return;
1351
1352 cp = &info->channel;
1353 if (sGetTxCnt(cp))
1354 sWriteTxPrioByte(cp, ch);
1355 else
1356 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1357 }
1358
1359 static void rp_throttle(struct tty_struct *tty)
1360 {
1361 struct r_port *info = tty->driver_data;
1362
1363 #ifdef ROCKET_DEBUG_THROTTLE
1364 printk(KERN_INFO "throttle %s: %d....\n", tty->name,
1365 tty->ldisc.chars_in_buffer(tty));
1366 #endif
1367
1368 if (rocket_paranoia_check(info, "rp_throttle"))
1369 return;
1370
1371 if (I_IXOFF(tty))
1372 rp_send_xchar(tty, STOP_CHAR(tty));
1373
1374 sClrRTS(&info->channel);
1375 }
1376
1377 static void rp_unthrottle(struct tty_struct *tty)
1378 {
1379 struct r_port *info = tty->driver_data;
1380 #ifdef ROCKET_DEBUG_THROTTLE
1381 printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
1382 tty->ldisc.chars_in_buffer(tty));
1383 #endif
1384
1385 if (rocket_paranoia_check(info, "rp_unthrottle"))
1386 return;
1387
1388 if (I_IXOFF(tty))
1389 rp_send_xchar(tty, START_CHAR(tty));
1390
1391 sSetRTS(&info->channel);
1392 }
1393
1394 /*
1395 * ------------------------------------------------------------
1396 * rp_stop() and rp_start()
1397 *
1398 * This routines are called before setting or resetting tty->stopped.
1399 * They enable or disable transmitter interrupts, as necessary.
1400 * ------------------------------------------------------------
1401 */
1402 static void rp_stop(struct tty_struct *tty)
1403 {
1404 struct r_port *info = tty->driver_data;
1405
1406 #ifdef ROCKET_DEBUG_FLOW
1407 printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1408 info->xmit_cnt, info->xmit_fifo_room);
1409 #endif
1410
1411 if (rocket_paranoia_check(info, "rp_stop"))
1412 return;
1413
1414 if (sGetTxCnt(&info->channel))
1415 sDisTransmit(&info->channel);
1416 }
1417
1418 static void rp_start(struct tty_struct *tty)
1419 {
1420 struct r_port *info = tty->driver_data;
1421
1422 #ifdef ROCKET_DEBUG_FLOW
1423 printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1424 info->xmit_cnt, info->xmit_fifo_room);
1425 #endif
1426
1427 if (rocket_paranoia_check(info, "rp_stop"))
1428 return;
1429
1430 sEnTransmit(&info->channel);
1431 set_bit((info->aiop * 8) + info->chan,
1432 (void *) &xmit_flags[info->board]);
1433 }
1434
1435 /*
1436 * rp_wait_until_sent() --- wait until the transmitter is empty
1437 */
1438 static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1439 {
1440 struct r_port *info = tty->driver_data;
1441 CHANNEL_t *cp;
1442 unsigned long orig_jiffies;
1443 int check_time, exit_time;
1444 int txcnt;
1445
1446 if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1447 return;
1448
1449 cp = &info->channel;
1450
1451 orig_jiffies = jiffies;
1452 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1453 printk(KERN_INFO "In %s(%d) (jiff=%lu)...\n", __func__, timeout,
1454 jiffies);
1455 printk(KERN_INFO "cps=%d...\n", info->cps);
1456 #endif
1457 while (1) {
1458 txcnt = sGetTxCnt(cp);
1459 if (!txcnt) {
1460 if (sGetChanStatusLo(cp) & TXSHRMT)
1461 break;
1462 check_time = (HZ / info->cps) / 5;
1463 } else {
1464 check_time = HZ * txcnt / info->cps;
1465 }
1466 if (timeout) {
1467 exit_time = orig_jiffies + timeout - jiffies;
1468 if (exit_time <= 0)
1469 break;
1470 if (exit_time < check_time)
1471 check_time = exit_time;
1472 }
1473 if (check_time == 0)
1474 check_time = 1;
1475 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1476 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1477 jiffies, check_time);
1478 #endif
1479 msleep_interruptible(jiffies_to_msecs(check_time));
1480 if (signal_pending(current))
1481 break;
1482 }
1483 __set_current_state(TASK_RUNNING);
1484 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1485 printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1486 #endif
1487 }
1488
1489 /*
1490 * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1491 */
1492 static void rp_hangup(struct tty_struct *tty)
1493 {
1494 CHANNEL_t *cp;
1495 struct r_port *info = tty->driver_data;
1496 unsigned long flags;
1497
1498 if (rocket_paranoia_check(info, "rp_hangup"))
1499 return;
1500
1501 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
1502 printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1503 #endif
1504 rp_flush_buffer(tty);
1505 spin_lock_irqsave(&info->port.lock, flags);
1506 if (info->port.count)
1507 atomic_dec(&rp_num_ports_open);
1508 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1509 spin_unlock_irqrestore(&info->port.lock, flags);
1510
1511 tty_port_hangup(&info->port);
1512
1513 cp = &info->channel;
1514 sDisRxFIFO(cp);
1515 sDisTransmit(cp);
1516 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1517 sDisCTSFlowCtl(cp);
1518 sDisTxSoftFlowCtl(cp);
1519 sClrTxXOFF(cp);
1520 clear_bit(ASYNCB_INITIALIZED, &info->port.flags);
1521
1522 wake_up_interruptible(&info->port.open_wait);
1523 }
1524
1525 /*
1526 * Exception handler - write char routine. The RocketPort driver uses a
1527 * double-buffering strategy, with the twist that if the in-memory CPU
1528 * buffer is empty, and there's space in the transmit FIFO, the
1529 * writing routines will write directly to transmit FIFO.
1530 * Write buffer and counters protected by spinlocks
1531 */
1532 static int rp_put_char(struct tty_struct *tty, unsigned char ch)
1533 {
1534 struct r_port *info = tty->driver_data;
1535 CHANNEL_t *cp;
1536 unsigned long flags;
1537
1538 if (rocket_paranoia_check(info, "rp_put_char"))
1539 return 0;
1540
1541 /*
1542 * Grab the port write mutex, locking out other processes that try to
1543 * write to this port
1544 */
1545 mutex_lock(&info->write_mtx);
1546
1547 #ifdef ROCKET_DEBUG_WRITE
1548 printk(KERN_INFO "rp_put_char %c...\n", ch);
1549 #endif
1550
1551 spin_lock_irqsave(&info->slock, flags);
1552 cp = &info->channel;
1553
1554 if (!tty->stopped && info->xmit_fifo_room == 0)
1555 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1556
1557 if (tty->stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1558 info->xmit_buf[info->xmit_head++] = ch;
1559 info->xmit_head &= XMIT_BUF_SIZE - 1;
1560 info->xmit_cnt++;
1561 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1562 } else {
1563 sOutB(sGetTxRxDataIO(cp), ch);
1564 info->xmit_fifo_room--;
1565 }
1566 spin_unlock_irqrestore(&info->slock, flags);
1567 mutex_unlock(&info->write_mtx);
1568 return 1;
1569 }
1570
1571 /*
1572 * Exception handler - write routine, called when user app writes to the device.
1573 * A per port write mutex is used to protect from another process writing to
1574 * this port at the same time. This other process could be running on the other CPU
1575 * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1576 * Spinlocks protect the info xmit members.
1577 */
1578 static int rp_write(struct tty_struct *tty,
1579 const unsigned char *buf, int count)
1580 {
1581 struct r_port *info = tty->driver_data;
1582 CHANNEL_t *cp;
1583 const unsigned char *b;
1584 int c, retval = 0;
1585 unsigned long flags;
1586
1587 if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1588 return 0;
1589
1590 if (mutex_lock_interruptible(&info->write_mtx))
1591 return -ERESTARTSYS;
1592
1593 #ifdef ROCKET_DEBUG_WRITE
1594 printk(KERN_INFO "rp_write %d chars...\n", count);
1595 #endif
1596 cp = &info->channel;
1597
1598 if (!tty->stopped && info->xmit_fifo_room < count)
1599 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1600
1601 /*
1602 * If the write queue for the port is empty, and there is FIFO space, stuff bytes
1603 * into FIFO. Use the write queue for temp storage.
1604 */
1605 if (!tty->stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1606 c = min(count, info->xmit_fifo_room);
1607 b = buf;
1608
1609 /* Push data into FIFO, 2 bytes at a time */
1610 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1611
1612 /* If there is a byte remaining, write it */
1613 if (c & 1)
1614 sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1615
1616 retval += c;
1617 buf += c;
1618 count -= c;
1619
1620 spin_lock_irqsave(&info->slock, flags);
1621 info->xmit_fifo_room -= c;
1622 spin_unlock_irqrestore(&info->slock, flags);
1623 }
1624
1625 /* If count is zero, we wrote it all and are done */
1626 if (!count)
1627 goto end;
1628
1629 /* Write remaining data into the port's xmit_buf */
1630 while (1) {
1631 /* Hung up ? */
1632 if (!test_bit(ASYNCB_NORMAL_ACTIVE, &info->port.flags))
1633 goto end;
1634 c = min(count, XMIT_BUF_SIZE - info->xmit_cnt - 1);
1635 c = min(c, XMIT_BUF_SIZE - info->xmit_head);
1636 if (c <= 0)
1637 break;
1638
1639 b = buf;
1640 memcpy(info->xmit_buf + info->xmit_head, b, c);
1641
1642 spin_lock_irqsave(&info->slock, flags);
1643 info->xmit_head =
1644 (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1645 info->xmit_cnt += c;
1646 spin_unlock_irqrestore(&info->slock, flags);
1647
1648 buf += c;
1649 count -= c;
1650 retval += c;
1651 }
1652
1653 if ((retval > 0) && !tty->stopped)
1654 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1655
1656 end:
1657 if (info->xmit_cnt < WAKEUP_CHARS) {
1658 tty_wakeup(tty);
1659 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1660 wake_up_interruptible(&tty->poll_wait);
1661 #endif
1662 }
1663 mutex_unlock(&info->write_mtx);
1664 return retval;
1665 }
1666
1667 /*
1668 * Return the number of characters that can be sent. We estimate
1669 * only using the in-memory transmit buffer only, and ignore the
1670 * potential space in the transmit FIFO.
1671 */
1672 static int rp_write_room(struct tty_struct *tty)
1673 {
1674 struct r_port *info = tty->driver_data;
1675 int ret;
1676
1677 if (rocket_paranoia_check(info, "rp_write_room"))
1678 return 0;
1679
1680 ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1681 if (ret < 0)
1682 ret = 0;
1683 #ifdef ROCKET_DEBUG_WRITE
1684 printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1685 #endif
1686 return ret;
1687 }
1688
1689 /*
1690 * Return the number of characters in the buffer. Again, this only
1691 * counts those characters in the in-memory transmit buffer.
1692 */
1693 static int rp_chars_in_buffer(struct tty_struct *tty)
1694 {
1695 struct r_port *info = tty->driver_data;
1696
1697 if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1698 return 0;
1699
1700 #ifdef ROCKET_DEBUG_WRITE
1701 printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1702 #endif
1703 return info->xmit_cnt;
1704 }
1705
1706 /*
1707 * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1708 * r_port struct for the port. Note that spinlock are used to protect info members,
1709 * do not call this function if the spinlock is already held.
1710 */
1711 static void rp_flush_buffer(struct tty_struct *tty)
1712 {
1713 struct r_port *info = tty->driver_data;
1714 CHANNEL_t *cp;
1715 unsigned long flags;
1716
1717 if (rocket_paranoia_check(info, "rp_flush_buffer"))
1718 return;
1719
1720 spin_lock_irqsave(&info->slock, flags);
1721 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1722 spin_unlock_irqrestore(&info->slock, flags);
1723
1724 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1725 wake_up_interruptible(&tty->poll_wait);
1726 #endif
1727 tty_wakeup(tty);
1728
1729 cp = &info->channel;
1730 sFlushTxFIFO(cp);
1731 }
1732
1733 #ifdef CONFIG_PCI
1734
1735 static const struct pci_device_id rocket_pci_ids[] = {
1736 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4QUAD) },
1737 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8OCTA) },
1738 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8OCTA) },
1739 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8INTF) },
1740 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8INTF) },
1741 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8J) },
1742 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4J) },
1743 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8SNI) },
1744 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16SNI) },
1745 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16INTF) },
1746 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP16INTF) },
1747 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_CRP16INTF) },
1748 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP32INTF) },
1749 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP32INTF) },
1750 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP4) },
1751 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP8) },
1752 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_232) },
1753 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_422) },
1754 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP6M) },
1755 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4M) },
1756 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_8PORT) },
1757 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_4PORT) },
1758 { }
1759 };
1760 MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1761
1762 /* Resets the speaker controller on RocketModem II and III devices */
1763 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
1764 {
1765 ByteIO_t addr;
1766
1767 /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
1768 if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
1769 addr = CtlP->AiopIO[0] + 0x4F;
1770 sOutB(addr, 0);
1771 }
1772
1773 /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
1774 if ((model == MODEL_UPCI_RM3_8PORT)
1775 || (model == MODEL_UPCI_RM3_4PORT)) {
1776 addr = CtlP->AiopIO[0] + 0x88;
1777 sOutB(addr, 0);
1778 }
1779 }
1780
1781 /***************************************************************************
1782 Function: sPCIInitController
1783 Purpose: Initialization of controller global registers and controller
1784 structure.
1785 Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
1786 IRQNum,Frequency,PeriodicOnly)
1787 CONTROLLER_T *CtlP; Ptr to controller structure
1788 int CtlNum; Controller number
1789 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
1790 This list must be in the order the AIOPs will be found on the
1791 controller. Once an AIOP in the list is not found, it is
1792 assumed that there are no more AIOPs on the controller.
1793 int AiopIOListSize; Number of addresses in AiopIOList
1794 int IRQNum; Interrupt Request number. Can be any of the following:
1795 0: Disable global interrupts
1796 3: IRQ 3
1797 4: IRQ 4
1798 5: IRQ 5
1799 9: IRQ 9
1800 10: IRQ 10
1801 11: IRQ 11
1802 12: IRQ 12
1803 15: IRQ 15
1804 Byte_t Frequency: A flag identifying the frequency
1805 of the periodic interrupt, can be any one of the following:
1806 FREQ_DIS - periodic interrupt disabled
1807 FREQ_137HZ - 137 Hertz
1808 FREQ_69HZ - 69 Hertz
1809 FREQ_34HZ - 34 Hertz
1810 FREQ_17HZ - 17 Hertz
1811 FREQ_9HZ - 9 Hertz
1812 FREQ_4HZ - 4 Hertz
1813 If IRQNum is set to 0 the Frequency parameter is
1814 overidden, it is forced to a value of FREQ_DIS.
1815 int PeriodicOnly: 1 if all interrupts except the periodic
1816 interrupt are to be blocked.
1817 0 is both the periodic interrupt and
1818 other channel interrupts are allowed.
1819 If IRQNum is set to 0 the PeriodicOnly parameter is
1820 overidden, it is forced to a value of 0.
1821 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
1822 initialization failed.
1823
1824 Comments:
1825 If periodic interrupts are to be disabled but AIOP interrupts
1826 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
1827
1828 If interrupts are to be completely disabled set IRQNum to 0.
1829
1830 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
1831 invalid combination.
1832
1833 This function performs initialization of global interrupt modes,
1834 but it does not actually enable global interrupts. To enable
1835 and disable global interrupts use functions sEnGlobalInt() and
1836 sDisGlobalInt(). Enabling of global interrupts is normally not
1837 done until all other initializations are complete.
1838
1839 Even if interrupts are globally enabled, they must also be
1840 individually enabled for each channel that is to generate
1841 interrupts.
1842
1843 Warnings: No range checking on any of the parameters is done.
1844
1845 No context switches are allowed while executing this function.
1846
1847 After this function all AIOPs on the controller are disabled,
1848 they can be enabled with sEnAiop().
1849 */
1850 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
1851 ByteIO_t * AiopIOList, int AiopIOListSize,
1852 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
1853 int PeriodicOnly, int altChanRingIndicator,
1854 int UPCIRingInd)
1855 {
1856 int i;
1857 ByteIO_t io;
1858
1859 CtlP->AltChanRingIndicator = altChanRingIndicator;
1860 CtlP->UPCIRingInd = UPCIRingInd;
1861 CtlP->CtlNum = CtlNum;
1862 CtlP->CtlID = CTLID_0001; /* controller release 1 */
1863 CtlP->BusType = isPCI; /* controller release 1 */
1864
1865 if (ConfigIO) {
1866 CtlP->isUPCI = 1;
1867 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
1868 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
1869 CtlP->AiopIntrBits = upci_aiop_intr_bits;
1870 } else {
1871 CtlP->isUPCI = 0;
1872 CtlP->PCIIO =
1873 (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
1874 CtlP->AiopIntrBits = aiop_intr_bits;
1875 }
1876
1877 sPCIControllerEOI(CtlP); /* clear EOI if warm init */
1878 /* Init AIOPs */
1879 CtlP->NumAiop = 0;
1880 for (i = 0; i < AiopIOListSize; i++) {
1881 io = AiopIOList[i];
1882 CtlP->AiopIO[i] = (WordIO_t) io;
1883 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
1884
1885 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
1886 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
1887 break; /* done looking for AIOPs */
1888
1889 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
1890 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
1891 sOutB(io + _INDX_DATA, sClockPrescale);
1892 CtlP->NumAiop++; /* bump count of AIOPs */
1893 }
1894
1895 if (CtlP->NumAiop == 0)
1896 return (-1);
1897 else
1898 return (CtlP->NumAiop);
1899 }
1900
1901 /*
1902 * Called when a PCI card is found. Retrieves and stores model information,
1903 * init's aiopic and serial port hardware.
1904 * Inputs: i is the board number (0-n)
1905 */
1906 static __init int register_PCI(int i, struct pci_dev *dev)
1907 {
1908 int num_aiops, aiop, max_num_aiops, num_chan, chan;
1909 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1910 CONTROLLER_t *ctlp;
1911
1912 int fast_clock = 0;
1913 int altChanRingIndicator = 0;
1914 int ports_per_aiop = 8;
1915 WordIO_t ConfigIO = 0;
1916 ByteIO_t UPCIRingInd = 0;
1917
1918 if (!dev || !pci_match_id(rocket_pci_ids, dev) ||
1919 pci_enable_device(dev))
1920 return 0;
1921
1922 rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1923
1924 rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1925 rocketModel[i].loadrm2 = 0;
1926 rocketModel[i].startingPortNumber = nextLineNumber;
1927
1928 /* Depending on the model, set up some config variables */
1929 switch (dev->device) {
1930 case PCI_DEVICE_ID_RP4QUAD:
1931 max_num_aiops = 1;
1932 ports_per_aiop = 4;
1933 rocketModel[i].model = MODEL_RP4QUAD;
1934 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1935 rocketModel[i].numPorts = 4;
1936 break;
1937 case PCI_DEVICE_ID_RP8OCTA:
1938 max_num_aiops = 1;
1939 rocketModel[i].model = MODEL_RP8OCTA;
1940 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1941 rocketModel[i].numPorts = 8;
1942 break;
1943 case PCI_DEVICE_ID_URP8OCTA:
1944 max_num_aiops = 1;
1945 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1946 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1947 rocketModel[i].numPorts = 8;
1948 break;
1949 case PCI_DEVICE_ID_RP8INTF:
1950 max_num_aiops = 1;
1951 rocketModel[i].model = MODEL_RP8INTF;
1952 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1953 rocketModel[i].numPorts = 8;
1954 break;
1955 case PCI_DEVICE_ID_URP8INTF:
1956 max_num_aiops = 1;
1957 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1958 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1959 rocketModel[i].numPorts = 8;
1960 break;
1961 case PCI_DEVICE_ID_RP8J:
1962 max_num_aiops = 1;
1963 rocketModel[i].model = MODEL_RP8J;
1964 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1965 rocketModel[i].numPorts = 8;
1966 break;
1967 case PCI_DEVICE_ID_RP4J:
1968 max_num_aiops = 1;
1969 ports_per_aiop = 4;
1970 rocketModel[i].model = MODEL_RP4J;
1971 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1972 rocketModel[i].numPorts = 4;
1973 break;
1974 case PCI_DEVICE_ID_RP8SNI:
1975 max_num_aiops = 1;
1976 rocketModel[i].model = MODEL_RP8SNI;
1977 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1978 rocketModel[i].numPorts = 8;
1979 break;
1980 case PCI_DEVICE_ID_RP16SNI:
1981 max_num_aiops = 2;
1982 rocketModel[i].model = MODEL_RP16SNI;
1983 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1984 rocketModel[i].numPorts = 16;
1985 break;
1986 case PCI_DEVICE_ID_RP16INTF:
1987 max_num_aiops = 2;
1988 rocketModel[i].model = MODEL_RP16INTF;
1989 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1990 rocketModel[i].numPorts = 16;
1991 break;
1992 case PCI_DEVICE_ID_URP16INTF:
1993 max_num_aiops = 2;
1994 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1995 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1996 rocketModel[i].numPorts = 16;
1997 break;
1998 case PCI_DEVICE_ID_CRP16INTF:
1999 max_num_aiops = 2;
2000 rocketModel[i].model = MODEL_CPCI_RP16INTF;
2001 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
2002 rocketModel[i].numPorts = 16;
2003 break;
2004 case PCI_DEVICE_ID_RP32INTF:
2005 max_num_aiops = 4;
2006 rocketModel[i].model = MODEL_RP32INTF;
2007 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
2008 rocketModel[i].numPorts = 32;
2009 break;
2010 case PCI_DEVICE_ID_URP32INTF:
2011 max_num_aiops = 4;
2012 rocketModel[i].model = MODEL_UPCI_RP32INTF;
2013 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
2014 rocketModel[i].numPorts = 32;
2015 break;
2016 case PCI_DEVICE_ID_RPP4:
2017 max_num_aiops = 1;
2018 ports_per_aiop = 4;
2019 altChanRingIndicator++;
2020 fast_clock++;
2021 rocketModel[i].model = MODEL_RPP4;
2022 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
2023 rocketModel[i].numPorts = 4;
2024 break;
2025 case PCI_DEVICE_ID_RPP8:
2026 max_num_aiops = 2;
2027 ports_per_aiop = 4;
2028 altChanRingIndicator++;
2029 fast_clock++;
2030 rocketModel[i].model = MODEL_RPP8;
2031 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
2032 rocketModel[i].numPorts = 8;
2033 break;
2034 case PCI_DEVICE_ID_RP2_232:
2035 max_num_aiops = 1;
2036 ports_per_aiop = 2;
2037 altChanRingIndicator++;
2038 fast_clock++;
2039 rocketModel[i].model = MODEL_RP2_232;
2040 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
2041 rocketModel[i].numPorts = 2;
2042 break;
2043 case PCI_DEVICE_ID_RP2_422:
2044 max_num_aiops = 1;
2045 ports_per_aiop = 2;
2046 altChanRingIndicator++;
2047 fast_clock++;
2048 rocketModel[i].model = MODEL_RP2_422;
2049 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
2050 rocketModel[i].numPorts = 2;
2051 break;
2052 case PCI_DEVICE_ID_RP6M:
2053
2054 max_num_aiops = 1;
2055 ports_per_aiop = 6;
2056
2057 /* If revision is 1, the rocketmodem flash must be loaded.
2058 * If it is 2 it is a "socketed" version. */
2059 if (dev->revision == 1) {
2060 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2061 rocketModel[i].loadrm2 = 1;
2062 } else {
2063 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2064 }
2065
2066 rocketModel[i].model = MODEL_RP6M;
2067 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
2068 rocketModel[i].numPorts = 6;
2069 break;
2070 case PCI_DEVICE_ID_RP4M:
2071 max_num_aiops = 1;
2072 ports_per_aiop = 4;
2073 if (dev->revision == 1) {
2074 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2075 rocketModel[i].loadrm2 = 1;
2076 } else {
2077 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2078 }
2079
2080 rocketModel[i].model = MODEL_RP4M;
2081 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
2082 rocketModel[i].numPorts = 4;
2083 break;
2084 default:
2085 max_num_aiops = 0;
2086 break;
2087 }
2088
2089 /*
2090 * Check for UPCI boards.
2091 */
2092
2093 switch (dev->device) {
2094 case PCI_DEVICE_ID_URP32INTF:
2095 case PCI_DEVICE_ID_URP8INTF:
2096 case PCI_DEVICE_ID_URP16INTF:
2097 case PCI_DEVICE_ID_CRP16INTF:
2098 case PCI_DEVICE_ID_URP8OCTA:
2099 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2100 ConfigIO = pci_resource_start(dev, 1);
2101 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
2102 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2103
2104 /*
2105 * Check for octa or quad cable.
2106 */
2107 if (!
2108 (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2109 PCI_GPIO_CTRL_8PORT)) {
2110 ports_per_aiop = 4;
2111 rocketModel[i].numPorts = 4;
2112 }
2113 }
2114 break;
2115 case PCI_DEVICE_ID_UPCI_RM3_8PORT:
2116 max_num_aiops = 1;
2117 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2118 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2119 rocketModel[i].numPorts = 8;
2120 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2121 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2122 ConfigIO = pci_resource_start(dev, 1);
2123 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2124 break;
2125 case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2126 max_num_aiops = 1;
2127 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2128 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2129 rocketModel[i].numPorts = 4;
2130 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2131 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2132 ConfigIO = pci_resource_start(dev, 1);
2133 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2134 break;
2135 default:
2136 break;
2137 }
2138
2139 if (fast_clock) {
2140 sClockPrescale = 0x12; /* mod 2 (divide by 3) */
2141 rp_baud_base[i] = 921600;
2142 } else {
2143 /*
2144 * If support_low_speed is set, use the slow clock
2145 * prescale, which supports 50 bps
2146 */
2147 if (support_low_speed) {
2148 /* mod 9 (divide by 10) prescale */
2149 sClockPrescale = 0x19;
2150 rp_baud_base[i] = 230400;
2151 } else {
2152 /* mod 4 (divide by 5) prescale */
2153 sClockPrescale = 0x14;
2154 rp_baud_base[i] = 460800;
2155 }
2156 }
2157
2158 for (aiop = 0; aiop < max_num_aiops; aiop++)
2159 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2160 ctlp = sCtlNumToCtlPtr(i);
2161 num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2162 for (aiop = 0; aiop < max_num_aiops; aiop++)
2163 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2164
2165 dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2166 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2167 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2168 rocketModel[i].startingPortNumber,
2169 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
2170
2171 if (num_aiops <= 0) {
2172 rcktpt_io_addr[i] = 0;
2173 return (0);
2174 }
2175 is_PCI[i] = 1;
2176
2177 /* Reset the AIOPIC, init the serial ports */
2178 for (aiop = 0; aiop < num_aiops; aiop++) {
2179 sResetAiopByNum(ctlp, aiop);
2180 num_chan = ports_per_aiop;
2181 for (chan = 0; chan < num_chan; chan++)
2182 init_r_port(i, aiop, chan, dev);
2183 }
2184
2185 /* Rocket modems must be reset */
2186 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2187 (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2188 (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2189 num_chan = ports_per_aiop;
2190 for (chan = 0; chan < num_chan; chan++)
2191 sPCIModemReset(ctlp, chan, 1);
2192 msleep(500);
2193 for (chan = 0; chan < num_chan; chan++)
2194 sPCIModemReset(ctlp, chan, 0);
2195 msleep(500);
2196 rmSpeakerReset(ctlp, rocketModel[i].model);
2197 }
2198 return (1);
2199 }
2200
2201 /*
2202 * Probes for PCI cards, inits them if found
2203 * Input: board_found = number of ISA boards already found, or the
2204 * starting board number
2205 * Returns: Number of PCI boards found
2206 */
2207 static int __init init_PCI(int boards_found)
2208 {
2209 struct pci_dev *dev = NULL;
2210 int count = 0;
2211
2212 /* Work through the PCI device list, pulling out ours */
2213 while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
2214 if (register_PCI(count + boards_found, dev))
2215 count++;
2216 }
2217 return (count);
2218 }
2219
2220 #endif /* CONFIG_PCI */
2221
2222 /*
2223 * Probes for ISA cards
2224 * Input: i = the board number to look for
2225 * Returns: 1 if board found, 0 else
2226 */
2227 static int __init init_ISA(int i)
2228 {
2229 int num_aiops, num_chan = 0, total_num_chan = 0;
2230 int aiop, chan;
2231 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2232 CONTROLLER_t *ctlp;
2233 char *type_string;
2234
2235 /* If io_addr is zero, no board configured */
2236 if (rcktpt_io_addr[i] == 0)
2237 return (0);
2238
2239 /* Reserve the IO region */
2240 if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
2241 printk(KERN_ERR "Unable to reserve IO region for configured "
2242 "ISA RocketPort at address 0x%lx, board not "
2243 "installed...\n", rcktpt_io_addr[i]);
2244 rcktpt_io_addr[i] = 0;
2245 return (0);
2246 }
2247
2248 ctlp = sCtlNumToCtlPtr(i);
2249
2250 ctlp->boardType = rcktpt_type[i];
2251
2252 switch (rcktpt_type[i]) {
2253 case ROCKET_TYPE_PC104:
2254 type_string = "(PC104)";
2255 break;
2256 case ROCKET_TYPE_MODEM:
2257 type_string = "(RocketModem)";
2258 break;
2259 case ROCKET_TYPE_MODEMII:
2260 type_string = "(RocketModem II)";
2261 break;
2262 default:
2263 type_string = "";
2264 break;
2265 }
2266
2267 /*
2268 * If support_low_speed is set, use the slow clock prescale,
2269 * which supports 50 bps
2270 */
2271 if (support_low_speed) {
2272 sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
2273 rp_baud_base[i] = 230400;
2274 } else {
2275 sClockPrescale = 0x14; /* mod 4 (divide by 5) prescale */
2276 rp_baud_base[i] = 460800;
2277 }
2278
2279 for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2280 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2281
2282 num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2283
2284 if (ctlp->boardType == ROCKET_TYPE_PC104) {
2285 sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
2286 sEnAiop(ctlp, 3); /* CSels used for other stuff */
2287 }
2288
2289 /* If something went wrong initing the AIOP's release the ISA IO memory */
2290 if (num_aiops <= 0) {
2291 release_region(rcktpt_io_addr[i], 64);
2292 rcktpt_io_addr[i] = 0;
2293 return (0);
2294 }
2295
2296 rocketModel[i].startingPortNumber = nextLineNumber;
2297
2298 for (aiop = 0; aiop < num_aiops; aiop++) {
2299 sResetAiopByNum(ctlp, aiop);
2300 sEnAiop(ctlp, aiop);
2301 num_chan = sGetAiopNumChan(ctlp, aiop);
2302 total_num_chan += num_chan;
2303 for (chan = 0; chan < num_chan; chan++)
2304 init_r_port(i, aiop, chan, NULL);
2305 }
2306 is_PCI[i] = 0;
2307 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2308 num_chan = sGetAiopNumChan(ctlp, 0);
2309 total_num_chan = num_chan;
2310 for (chan = 0; chan < num_chan; chan++)
2311 sModemReset(ctlp, chan, 1);
2312 msleep(500);
2313 for (chan = 0; chan < num_chan; chan++)
2314 sModemReset(ctlp, chan, 0);
2315 msleep(500);
2316 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2317 } else {
2318 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2319 }
2320 rocketModel[i].numPorts = total_num_chan;
2321 rocketModel[i].model = MODEL_ISA;
2322
2323 printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2324 i, rcktpt_io_addr[i], num_aiops, type_string);
2325
2326 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2327 rocketModel[i].modelString,
2328 rocketModel[i].startingPortNumber,
2329 rocketModel[i].startingPortNumber +
2330 rocketModel[i].numPorts - 1);
2331
2332 return (1);
2333 }
2334
2335 static const struct tty_operations rocket_ops = {
2336 .open = rp_open,
2337 .close = rp_close,
2338 .write = rp_write,
2339 .put_char = rp_put_char,
2340 .write_room = rp_write_room,
2341 .chars_in_buffer = rp_chars_in_buffer,
2342 .flush_buffer = rp_flush_buffer,
2343 .ioctl = rp_ioctl,
2344 .throttle = rp_throttle,
2345 .unthrottle = rp_unthrottle,
2346 .set_termios = rp_set_termios,
2347 .stop = rp_stop,
2348 .start = rp_start,
2349 .hangup = rp_hangup,
2350 .break_ctl = rp_break,
2351 .send_xchar = rp_send_xchar,
2352 .wait_until_sent = rp_wait_until_sent,
2353 .tiocmget = rp_tiocmget,
2354 .tiocmset = rp_tiocmset,
2355 };
2356
2357 static const struct tty_port_operations rocket_port_ops = {
2358 .carrier_raised = carrier_raised,
2359 .dtr_rts = dtr_rts,
2360 };
2361
2362 /*
2363 * The module "startup" routine; it's run when the module is loaded.
2364 */
2365 static int __init rp_init(void)
2366 {
2367 int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
2368
2369 printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2370 ROCKET_VERSION, ROCKET_DATE);
2371
2372 rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2373 if (!rocket_driver)
2374 goto err;
2375
2376 /*
2377 * If board 1 is non-zero, there is at least one ISA configured. If controller is
2378 * zero, use the default controller IO address of board1 + 0x40.
2379 */
2380 if (board1) {
2381 if (controller == 0)
2382 controller = board1 + 0x40;
2383 } else {
2384 controller = 0; /* Used as a flag, meaning no ISA boards */
2385 }
2386
2387 /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2388 if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
2389 printk(KERN_ERR "Unable to reserve IO region for first "
2390 "configured ISA RocketPort controller 0x%lx. "
2391 "Driver exiting\n", controller);
2392 ret = -EBUSY;
2393 goto err_tty;
2394 }
2395
2396 /* Store ISA variable retrieved from command line or .conf file. */
2397 rcktpt_io_addr[0] = board1;
2398 rcktpt_io_addr[1] = board2;
2399 rcktpt_io_addr[2] = board3;
2400 rcktpt_io_addr[3] = board4;
2401
2402 rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2403 rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2404 rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2405 rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2406 rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2407 rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2408 rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2409 rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2410
2411 /*
2412 * Set up the tty driver structure and then register this
2413 * driver with the tty layer.
2414 */
2415
2416 rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
2417 rocket_driver->name = "ttyR";
2418 rocket_driver->driver_name = "Comtrol RocketPort";
2419 rocket_driver->major = TTY_ROCKET_MAJOR;
2420 rocket_driver->minor_start = 0;
2421 rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2422 rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2423 rocket_driver->init_termios = tty_std_termios;
2424 rocket_driver->init_termios.c_cflag =
2425 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2426 rocket_driver->init_termios.c_ispeed = 9600;
2427 rocket_driver->init_termios.c_ospeed = 9600;
2428 #ifdef ROCKET_SOFT_FLOW
2429 rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
2430 #endif
2431 tty_set_operations(rocket_driver, &rocket_ops);
2432
2433 ret = tty_register_driver(rocket_driver);
2434 if (ret < 0) {
2435 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
2436 goto err_controller;
2437 }
2438
2439 #ifdef ROCKET_DEBUG_OPEN
2440 printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2441 #endif
2442
2443 /*
2444 * OK, let's probe each of the controllers looking for boards. Any boards found
2445 * will be initialized here.
2446 */
2447 isa_boards_found = 0;
2448 pci_boards_found = 0;
2449
2450 for (i = 0; i < NUM_BOARDS; i++) {
2451 if (init_ISA(i))
2452 isa_boards_found++;
2453 }
2454
2455 #ifdef CONFIG_PCI
2456 if (isa_boards_found < NUM_BOARDS)
2457 pci_boards_found = init_PCI(isa_boards_found);
2458 #endif
2459
2460 max_board = pci_boards_found + isa_boards_found;
2461
2462 if (max_board == 0) {
2463 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2464 ret = -ENXIO;
2465 goto err_ttyu;
2466 }
2467
2468 return 0;
2469 err_ttyu:
2470 tty_unregister_driver(rocket_driver);
2471 err_controller:
2472 if (controller)
2473 release_region(controller, 4);
2474 err_tty:
2475 put_tty_driver(rocket_driver);
2476 err:
2477 return ret;
2478 }
2479
2480
2481 static void rp_cleanup_module(void)
2482 {
2483 int retval;
2484 int i;
2485
2486 del_timer_sync(&rocket_timer);
2487
2488 retval = tty_unregister_driver(rocket_driver);
2489 if (retval)
2490 printk(KERN_ERR "Error %d while trying to unregister "
2491 "rocketport driver\n", -retval);
2492
2493 for (i = 0; i < MAX_RP_PORTS; i++)
2494 if (rp_table[i]) {
2495 tty_unregister_device(rocket_driver, i);
2496 tty_port_destroy(&rp_table[i]->port);
2497 kfree(rp_table[i]);
2498 }
2499
2500 put_tty_driver(rocket_driver);
2501
2502 for (i = 0; i < NUM_BOARDS; i++) {
2503 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2504 continue;
2505 release_region(rcktpt_io_addr[i], 64);
2506 }
2507 if (controller)
2508 release_region(controller, 4);
2509 }
2510
2511 /***************************************************************************
2512 Function: sInitController
2513 Purpose: Initialization of controller global registers and controller
2514 structure.
2515 Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2516 IRQNum,Frequency,PeriodicOnly)
2517 CONTROLLER_T *CtlP; Ptr to controller structure
2518 int CtlNum; Controller number
2519 ByteIO_t MudbacIO; Mudbac base I/O address.
2520 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2521 This list must be in the order the AIOPs will be found on the
2522 controller. Once an AIOP in the list is not found, it is
2523 assumed that there are no more AIOPs on the controller.
2524 int AiopIOListSize; Number of addresses in AiopIOList
2525 int IRQNum; Interrupt Request number. Can be any of the following:
2526 0: Disable global interrupts
2527 3: IRQ 3
2528 4: IRQ 4
2529 5: IRQ 5
2530 9: IRQ 9
2531 10: IRQ 10
2532 11: IRQ 11
2533 12: IRQ 12
2534 15: IRQ 15
2535 Byte_t Frequency: A flag identifying the frequency
2536 of the periodic interrupt, can be any one of the following:
2537 FREQ_DIS - periodic interrupt disabled
2538 FREQ_137HZ - 137 Hertz
2539 FREQ_69HZ - 69 Hertz
2540 FREQ_34HZ - 34 Hertz
2541 FREQ_17HZ - 17 Hertz
2542 FREQ_9HZ - 9 Hertz
2543 FREQ_4HZ - 4 Hertz
2544 If IRQNum is set to 0 the Frequency parameter is
2545 overidden, it is forced to a value of FREQ_DIS.
2546 int PeriodicOnly: 1 if all interrupts except the periodic
2547 interrupt are to be blocked.
2548 0 is both the periodic interrupt and
2549 other channel interrupts are allowed.
2550 If IRQNum is set to 0 the PeriodicOnly parameter is
2551 overidden, it is forced to a value of 0.
2552 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2553 initialization failed.
2554
2555 Comments:
2556 If periodic interrupts are to be disabled but AIOP interrupts
2557 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2558
2559 If interrupts are to be completely disabled set IRQNum to 0.
2560
2561 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2562 invalid combination.
2563
2564 This function performs initialization of global interrupt modes,
2565 but it does not actually enable global interrupts. To enable
2566 and disable global interrupts use functions sEnGlobalInt() and
2567 sDisGlobalInt(). Enabling of global interrupts is normally not
2568 done until all other initializations are complete.
2569
2570 Even if interrupts are globally enabled, they must also be
2571 individually enabled for each channel that is to generate
2572 interrupts.
2573
2574 Warnings: No range checking on any of the parameters is done.
2575
2576 No context switches are allowed while executing this function.
2577
2578 After this function all AIOPs on the controller are disabled,
2579 they can be enabled with sEnAiop().
2580 */
2581 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2582 ByteIO_t * AiopIOList, int AiopIOListSize,
2583 int IRQNum, Byte_t Frequency, int PeriodicOnly)
2584 {
2585 int i;
2586 ByteIO_t io;
2587 int done;
2588
2589 CtlP->AiopIntrBits = aiop_intr_bits;
2590 CtlP->AltChanRingIndicator = 0;
2591 CtlP->CtlNum = CtlNum;
2592 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2593 CtlP->BusType = isISA;
2594 CtlP->MBaseIO = MudbacIO;
2595 CtlP->MReg1IO = MudbacIO + 1;
2596 CtlP->MReg2IO = MudbacIO + 2;
2597 CtlP->MReg3IO = MudbacIO + 3;
2598 #if 1
2599 CtlP->MReg2 = 0; /* interrupt disable */
2600 CtlP->MReg3 = 0; /* no periodic interrupts */
2601 #else
2602 if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
2603 CtlP->MReg2 = 0; /* interrupt disable */
2604 CtlP->MReg3 = 0; /* no periodic interrupts */
2605 } else {
2606 CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
2607 CtlP->MReg3 = Frequency; /* set frequency */
2608 if (PeriodicOnly) { /* periodic interrupt only */
2609 CtlP->MReg3 |= PERIODIC_ONLY;
2610 }
2611 }
2612 #endif
2613 sOutB(CtlP->MReg2IO, CtlP->MReg2);
2614 sOutB(CtlP->MReg3IO, CtlP->MReg3);
2615 sControllerEOI(CtlP); /* clear EOI if warm init */
2616 /* Init AIOPs */
2617 CtlP->NumAiop = 0;
2618 for (i = done = 0; i < AiopIOListSize; i++) {
2619 io = AiopIOList[i];
2620 CtlP->AiopIO[i] = (WordIO_t) io;
2621 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2622 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2623 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2624 if (done)
2625 continue;
2626 sEnAiop(CtlP, i); /* enable the AIOP */
2627 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2628 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2629 done = 1; /* done looking for AIOPs */
2630 else {
2631 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2632 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2633 sOutB(io + _INDX_DATA, sClockPrescale);
2634 CtlP->NumAiop++; /* bump count of AIOPs */
2635 }
2636 sDisAiop(CtlP, i); /* disable AIOP */
2637 }
2638
2639 if (CtlP->NumAiop == 0)
2640 return (-1);
2641 else
2642 return (CtlP->NumAiop);
2643 }
2644
2645 /***************************************************************************
2646 Function: sReadAiopID
2647 Purpose: Read the AIOP idenfication number directly from an AIOP.
2648 Call: sReadAiopID(io)
2649 ByteIO_t io: AIOP base I/O address
2650 Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2651 is replace by an identifying number.
2652 Flag AIOPID_NULL if no valid AIOP is found
2653 Warnings: No context switches are allowed while executing this function.
2654
2655 */
2656 static int sReadAiopID(ByteIO_t io)
2657 {
2658 Byte_t AiopID; /* ID byte from AIOP */
2659
2660 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
2661 sOutB(io + _CMD_REG, 0x0);
2662 AiopID = sInW(io + _CHN_STAT0) & 0x07;
2663 if (AiopID == 0x06)
2664 return (1);
2665 else /* AIOP does not exist */
2666 return (-1);
2667 }
2668
2669 /***************************************************************************
2670 Function: sReadAiopNumChan
2671 Purpose: Read the number of channels available in an AIOP directly from
2672 an AIOP.
2673 Call: sReadAiopNumChan(io)
2674 WordIO_t io: AIOP base I/O address
2675 Return: int: The number of channels available
2676 Comments: The number of channels is determined by write/reads from identical
2677 offsets within the SRAM address spaces for channels 0 and 4.
2678 If the channel 4 space is mirrored to channel 0 it is a 4 channel
2679 AIOP, otherwise it is an 8 channel.
2680 Warnings: No context switches are allowed while executing this function.
2681 */
2682 static int sReadAiopNumChan(WordIO_t io)
2683 {
2684 Word_t x;
2685 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2686
2687 /* write to chan 0 SRAM */
2688 out32((DWordIO_t) io + _INDX_ADDR, R);
2689 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2690 x = sInW(io + _INDX_DATA);
2691 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2692 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2693 return (8);
2694 else
2695 return (4);
2696 }
2697
2698 /***************************************************************************
2699 Function: sInitChan
2700 Purpose: Initialization of a channel and channel structure
2701 Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2702 CONTROLLER_T *CtlP; Ptr to controller structure
2703 CHANNEL_T *ChP; Ptr to channel structure
2704 int AiopNum; AIOP number within controller
2705 int ChanNum; Channel number within AIOP
2706 Return: int: 1 if initialization succeeded, 0 if it fails because channel
2707 number exceeds number of channels available in AIOP.
2708 Comments: This function must be called before a channel can be used.
2709 Warnings: No range checking on any of the parameters is done.
2710
2711 No context switches are allowed while executing this function.
2712 */
2713 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2714 int ChanNum)
2715 {
2716 int i;
2717 WordIO_t AiopIO;
2718 WordIO_t ChIOOff;
2719 Byte_t *ChR;
2720 Word_t ChOff;
2721 static Byte_t R[4];
2722 int brd9600;
2723
2724 if (ChanNum >= CtlP->AiopNumChan[AiopNum])
2725 return 0; /* exceeds num chans in AIOP */
2726
2727 /* Channel, AIOP, and controller identifiers */
2728 ChP->CtlP = CtlP;
2729 ChP->ChanID = CtlP->AiopID[AiopNum];
2730 ChP->AiopNum = AiopNum;
2731 ChP->ChanNum = ChanNum;
2732
2733 /* Global direct addresses */
2734 AiopIO = CtlP->AiopIO[AiopNum];
2735 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2736 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2737 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2738 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2739 ChP->IndexData = AiopIO + _INDX_DATA;
2740
2741 /* Channel direct addresses */
2742 ChIOOff = AiopIO + ChP->ChanNum * 2;
2743 ChP->TxRxData = ChIOOff + _TD0;
2744 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2745 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2746 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2747
2748 /* Initialize the channel from the RData array */
2749 for (i = 0; i < RDATASIZE; i += 4) {
2750 R[0] = RData[i];
2751 R[1] = RData[i + 1] + 0x10 * ChanNum;
2752 R[2] = RData[i + 2];
2753 R[3] = RData[i + 3];
2754 out32(ChP->IndexAddr, R);
2755 }
2756
2757 ChR = ChP->R;
2758 for (i = 0; i < RREGDATASIZE; i += 4) {
2759 ChR[i] = RRegData[i];
2760 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2761 ChR[i + 2] = RRegData[i + 2];
2762 ChR[i + 3] = RRegData[i + 3];
2763 }
2764
2765 /* Indexed registers */
2766 ChOff = (Word_t) ChanNum *0x1000;
2767
2768 if (sClockPrescale == 0x14)
2769 brd9600 = 47;
2770 else
2771 brd9600 = 23;
2772
2773 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2774 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2775 ChP->BaudDiv[2] = (Byte_t) brd9600;
2776 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2777 out32(ChP->IndexAddr, ChP->BaudDiv);
2778
2779 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2780 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2781 ChP->TxControl[2] = 0;
2782 ChP->TxControl[3] = 0;
2783 out32(ChP->IndexAddr, ChP->TxControl);
2784
2785 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2786 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2787 ChP->RxControl[2] = 0;
2788 ChP->RxControl[3] = 0;
2789 out32(ChP->IndexAddr, ChP->RxControl);
2790
2791 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2792 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2793 ChP->TxEnables[2] = 0;
2794 ChP->TxEnables[3] = 0;
2795 out32(ChP->IndexAddr, ChP->TxEnables);
2796
2797 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2798 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2799 ChP->TxCompare[2] = 0;
2800 ChP->TxCompare[3] = 0;
2801 out32(ChP->IndexAddr, ChP->TxCompare);
2802
2803 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2804 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2805 ChP->TxReplace1[2] = 0;
2806 ChP->TxReplace1[3] = 0;
2807 out32(ChP->IndexAddr, ChP->TxReplace1);
2808
2809 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2810 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2811 ChP->TxReplace2[2] = 0;
2812 ChP->TxReplace2[3] = 0;
2813 out32(ChP->IndexAddr, ChP->TxReplace2);
2814
2815 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2816 ChP->TxFIFO = ChOff + _TX_FIFO;
2817
2818 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2819 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2820 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2821 sOutW(ChP->IndexData, 0);
2822 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2823 ChP->RxFIFO = ChOff + _RX_FIFO;
2824
2825 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
2826 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
2827 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2828 sOutW(ChP->IndexData, 0);
2829 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2830 sOutW(ChP->IndexData, 0);
2831 ChP->TxPrioCnt = ChOff + _TXP_CNT;
2832 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2833 sOutB(ChP->IndexData, 0);
2834 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2835 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2836 sOutB(ChP->IndexData, 0);
2837 ChP->TxPrioBuf = ChOff + _TXP_BUF;
2838 sEnRxProcessor(ChP); /* start the Rx processor */
2839
2840 return 1;
2841 }
2842
2843 /***************************************************************************
2844 Function: sStopRxProcessor
2845 Purpose: Stop the receive processor from processing a channel.
2846 Call: sStopRxProcessor(ChP)
2847 CHANNEL_T *ChP; Ptr to channel structure
2848
2849 Comments: The receive processor can be started again with sStartRxProcessor().
2850 This function causes the receive processor to skip over the
2851 stopped channel. It does not stop it from processing other channels.
2852
2853 Warnings: No context switches are allowed while executing this function.
2854
2855 Do not leave the receive processor stopped for more than one
2856 character time.
2857
2858 After calling this function a delay of 4 uS is required to ensure
2859 that the receive processor is no longer processing this channel.
2860 */
2861 static void sStopRxProcessor(CHANNEL_T * ChP)
2862 {
2863 Byte_t R[4];
2864
2865 R[0] = ChP->R[0];
2866 R[1] = ChP->R[1];
2867 R[2] = 0x0a;
2868 R[3] = ChP->R[3];
2869 out32(ChP->IndexAddr, R);
2870 }
2871
2872 /***************************************************************************
2873 Function: sFlushRxFIFO
2874 Purpose: Flush the Rx FIFO
2875 Call: sFlushRxFIFO(ChP)
2876 CHANNEL_T *ChP; Ptr to channel structure
2877 Return: void
2878 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2879 while it is being flushed the receive processor is stopped
2880 and the transmitter is disabled. After these operations a
2881 4 uS delay is done before clearing the pointers to allow
2882 the receive processor to stop. These items are handled inside
2883 this function.
2884 Warnings: No context switches are allowed while executing this function.
2885 */
2886 static void sFlushRxFIFO(CHANNEL_T * ChP)
2887 {
2888 int i;
2889 Byte_t Ch; /* channel number within AIOP */
2890 int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
2891
2892 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
2893 return; /* don't need to flush */
2894
2895 RxFIFOEnabled = 0;
2896 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
2897 RxFIFOEnabled = 1;
2898 sDisRxFIFO(ChP); /* disable it */
2899 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
2900 sInB(ChP->IntChan); /* depends on bus i/o timing */
2901 }
2902 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
2903 Ch = (Byte_t) sGetChanNum(ChP);
2904 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
2905 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
2906 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2907 sOutW(ChP->IndexData, 0);
2908 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2909 sOutW(ChP->IndexData, 0);
2910 if (RxFIFOEnabled)
2911 sEnRxFIFO(ChP); /* enable Rx FIFO */
2912 }
2913
2914 /***************************************************************************
2915 Function: sFlushTxFIFO
2916 Purpose: Flush the Tx FIFO
2917 Call: sFlushTxFIFO(ChP)
2918 CHANNEL_T *ChP; Ptr to channel structure
2919 Return: void
2920 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2921 while it is being flushed the receive processor is stopped
2922 and the transmitter is disabled. After these operations a
2923 4 uS delay is done before clearing the pointers to allow
2924 the receive processor to stop. These items are handled inside
2925 this function.
2926 Warnings: No context switches are allowed while executing this function.
2927 */
2928 static void sFlushTxFIFO(CHANNEL_T * ChP)
2929 {
2930 int i;
2931 Byte_t Ch; /* channel number within AIOP */
2932 int TxEnabled; /* 1 if transmitter enabled */
2933
2934 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
2935 return; /* don't need to flush */
2936
2937 TxEnabled = 0;
2938 if (ChP->TxControl[3] & TX_ENABLE) {
2939 TxEnabled = 1;
2940 sDisTransmit(ChP); /* disable transmitter */
2941 }
2942 sStopRxProcessor(ChP); /* stop Rx processor */
2943 for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
2944 sInB(ChP->IntChan); /* depends on bus i/o timing */
2945 Ch = (Byte_t) sGetChanNum(ChP);
2946 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
2947 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
2948 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2949 sOutW(ChP->IndexData, 0);
2950 if (TxEnabled)
2951 sEnTransmit(ChP); /* enable transmitter */
2952 sStartRxProcessor(ChP); /* restart Rx processor */
2953 }
2954
2955 /***************************************************************************
2956 Function: sWriteTxPrioByte
2957 Purpose: Write a byte of priority transmit data to a channel
2958 Call: sWriteTxPrioByte(ChP,Data)
2959 CHANNEL_T *ChP; Ptr to channel structure
2960 Byte_t Data; The transmit data byte
2961
2962 Return: int: 1 if the bytes is successfully written, otherwise 0.
2963
2964 Comments: The priority byte is transmitted before any data in the Tx FIFO.
2965
2966 Warnings: No context switches are allowed while executing this function.
2967 */
2968 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
2969 {
2970 Byte_t DWBuf[4]; /* buffer for double word writes */
2971 Word_t *WordPtr; /* must be far because Win SS != DS */
2972 register DWordIO_t IndexAddr;
2973
2974 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
2975 IndexAddr = ChP->IndexAddr;
2976 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
2977 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
2978 return (0); /* nothing sent */
2979
2980 WordPtr = (Word_t *) (&DWBuf[0]);
2981 *WordPtr = ChP->TxPrioBuf; /* data byte address */
2982
2983 DWBuf[2] = Data; /* data byte value */
2984 out32(IndexAddr, DWBuf); /* write it out */
2985
2986 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
2987
2988 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
2989 DWBuf[3] = 0; /* priority buffer pointer */
2990 out32(IndexAddr, DWBuf); /* write it out */
2991 } else { /* write it to Tx FIFO */
2992
2993 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
2994 }
2995 return (1); /* 1 byte sent */
2996 }
2997
2998 /***************************************************************************
2999 Function: sEnInterrupts
3000 Purpose: Enable one or more interrupts for a channel
3001 Call: sEnInterrupts(ChP,Flags)
3002 CHANNEL_T *ChP; Ptr to channel structure
3003 Word_t Flags: Interrupt enable flags, can be any combination
3004 of the following flags:
3005 TXINT_EN: Interrupt on Tx FIFO empty
3006 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3007 sSetRxTrigger())
3008 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3009 MCINT_EN: Interrupt on modem input change
3010 CHANINT_EN: Allow channel interrupt signal to the AIOP's
3011 Interrupt Channel Register.
3012 Return: void
3013 Comments: If an interrupt enable flag is set in Flags, that interrupt will be
3014 enabled. If an interrupt enable flag is not set in Flags, that
3015 interrupt will not be changed. Interrupts can be disabled with
3016 function sDisInterrupts().
3017
3018 This function sets the appropriate bit for the channel in the AIOP's
3019 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
3020 this channel's bit to be set in the AIOP's Interrupt Channel Register.
3021
3022 Interrupts must also be globally enabled before channel interrupts
3023 will be passed on to the host. This is done with function
3024 sEnGlobalInt().
3025
3026 In some cases it may be desirable to disable interrupts globally but
3027 enable channel interrupts. This would allow the global interrupt
3028 status register to be used to determine which AIOPs need service.
3029 */
3030 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3031 {
3032 Byte_t Mask; /* Interrupt Mask Register */
3033
3034 ChP->RxControl[2] |=
3035 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3036
3037 out32(ChP->IndexAddr, ChP->RxControl);
3038
3039 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3040
3041 out32(ChP->IndexAddr, ChP->TxControl);
3042
3043 if (Flags & CHANINT_EN) {
3044 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3045 sOutB(ChP->IntMask, Mask);
3046 }
3047 }
3048
3049 /***************************************************************************
3050 Function: sDisInterrupts
3051 Purpose: Disable one or more interrupts for a channel
3052 Call: sDisInterrupts(ChP,Flags)
3053 CHANNEL_T *ChP; Ptr to channel structure
3054 Word_t Flags: Interrupt flags, can be any combination
3055 of the following flags:
3056 TXINT_EN: Interrupt on Tx FIFO empty
3057 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3058 sSetRxTrigger())
3059 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3060 MCINT_EN: Interrupt on modem input change
3061 CHANINT_EN: Disable channel interrupt signal to the
3062 AIOP's Interrupt Channel Register.
3063 Return: void
3064 Comments: If an interrupt flag is set in Flags, that interrupt will be
3065 disabled. If an interrupt flag is not set in Flags, that
3066 interrupt will not be changed. Interrupts can be enabled with
3067 function sEnInterrupts().
3068
3069 This function clears the appropriate bit for the channel in the AIOP's
3070 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
3071 this channel's bit from being set in the AIOP's Interrupt Channel
3072 Register.
3073 */
3074 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3075 {
3076 Byte_t Mask; /* Interrupt Mask Register */
3077
3078 ChP->RxControl[2] &=
3079 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3080 out32(ChP->IndexAddr, ChP->RxControl);
3081 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3082 out32(ChP->IndexAddr, ChP->TxControl);
3083
3084 if (Flags & CHANINT_EN) {
3085 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3086 sOutB(ChP->IntMask, Mask);
3087 }
3088 }
3089
3090 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3091 {
3092 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3093 }
3094
3095 /*
3096 * Not an official SSCI function, but how to reset RocketModems.
3097 * ISA bus version
3098 */
3099 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
3100 {
3101 ByteIO_t addr;
3102 Byte_t val;
3103
3104 addr = CtlP->AiopIO[0] + 0x400;
3105 val = sInB(CtlP->MReg3IO);
3106 /* if AIOP[1] is not enabled, enable it */
3107 if ((val & 2) == 0) {
3108 val = sInB(CtlP->MReg2IO);
3109 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3110 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3111 }
3112
3113 sEnAiop(CtlP, 1);
3114 if (!on)
3115 addr += 8;
3116 sOutB(addr + chan, 0); /* apply or remove reset */
3117 sDisAiop(CtlP, 1);
3118 }
3119
3120 /*
3121 * Not an official SSCI function, but how to reset RocketModems.
3122 * PCI bus version
3123 */
3124 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
3125 {
3126 ByteIO_t addr;
3127
3128 addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
3129 if (!on)
3130 addr += 8;
3131 sOutB(addr + chan, 0); /* apply or remove reset */
3132 }
3133
3134 /* Returns the line number given the controller (board), aiop and channel number */
3135 static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3136 {
3137 return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3138 }
3139
3140 /*
3141 * Stores the line number associated with a given controller (board), aiop
3142 * and channel number.
3143 * Returns: The line number assigned
3144 */
3145 static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3146 {
3147 lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3148 return (nextLineNumber - 1);
3149 }
Linux kernel - Deliverables
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