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tty: remove use of __devexit
[deliverable/linux.git] / drivers / tty / serial / 8250 / 8250.c
1 /*
2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * A note about mapbase / membase
14 *
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
17 */
18
19 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20 #define SUPPORT_SYSRQ
21 #endif
22
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/delay.h>
30 #include <linux/platform_device.h>
31 #include <linux/tty.h>
32 #include <linux/ratelimit.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial_reg.h>
35 #include <linux/serial_core.h>
36 #include <linux/serial.h>
37 #include <linux/serial_8250.h>
38 #include <linux/nmi.h>
39 #include <linux/mutex.h>
40 #include <linux/slab.h>
41 #ifdef CONFIG_SPARC
42 #include <linux/sunserialcore.h>
43 #endif
44
45 #include <asm/io.h>
46 #include <asm/irq.h>
47
48 #include "8250.h"
49
50 /*
51 * Configuration:
52 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
53 * is unsafe when used on edge-triggered interrupts.
54 */
55 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
56
57 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
58
59 static struct uart_driver serial8250_reg;
60
61 static int serial_index(struct uart_port *port)
62 {
63 return (serial8250_reg.minor - 64) + port->line;
64 }
65
66 static unsigned int skip_txen_test; /* force skip of txen test at init time */
67
68 /*
69 * Debugging.
70 */
71 #if 0
72 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
73 #else
74 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
75 #endif
76
77 #if 0
78 #define DEBUG_INTR(fmt...) printk(fmt)
79 #else
80 #define DEBUG_INTR(fmt...) do { } while (0)
81 #endif
82
83 #define PASS_LIMIT 512
84
85 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
86
87
88 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
89 #define CONFIG_SERIAL_DETECT_IRQ 1
90 #endif
91 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
92 #define CONFIG_SERIAL_MANY_PORTS 1
93 #endif
94
95 /*
96 * HUB6 is always on. This will be removed once the header
97 * files have been cleaned.
98 */
99 #define CONFIG_HUB6 1
100
101 #include <asm/serial.h>
102 /*
103 * SERIAL_PORT_DFNS tells us about built-in ports that have no
104 * standard enumeration mechanism. Platforms that can find all
105 * serial ports via mechanisms like ACPI or PCI need not supply it.
106 */
107 #ifndef SERIAL_PORT_DFNS
108 #define SERIAL_PORT_DFNS
109 #endif
110
111 static const struct old_serial_port old_serial_port[] = {
112 SERIAL_PORT_DFNS /* defined in asm/serial.h */
113 };
114
115 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
116
117 #ifdef CONFIG_SERIAL_8250_RSA
118
119 #define PORT_RSA_MAX 4
120 static unsigned long probe_rsa[PORT_RSA_MAX];
121 static unsigned int probe_rsa_count;
122 #endif /* CONFIG_SERIAL_8250_RSA */
123
124 struct irq_info {
125 struct hlist_node node;
126 int irq;
127 spinlock_t lock; /* Protects list not the hash */
128 struct list_head *head;
129 };
130
131 #define NR_IRQ_HASH 32 /* Can be adjusted later */
132 static struct hlist_head irq_lists[NR_IRQ_HASH];
133 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
134
135 /*
136 * Here we define the default xmit fifo size used for each type of UART.
137 */
138 static const struct serial8250_config uart_config[] = {
139 [PORT_UNKNOWN] = {
140 .name = "unknown",
141 .fifo_size = 1,
142 .tx_loadsz = 1,
143 },
144 [PORT_8250] = {
145 .name = "8250",
146 .fifo_size = 1,
147 .tx_loadsz = 1,
148 },
149 [PORT_16450] = {
150 .name = "16450",
151 .fifo_size = 1,
152 .tx_loadsz = 1,
153 },
154 [PORT_16550] = {
155 .name = "16550",
156 .fifo_size = 1,
157 .tx_loadsz = 1,
158 },
159 [PORT_16550A] = {
160 .name = "16550A",
161 .fifo_size = 16,
162 .tx_loadsz = 16,
163 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
164 .flags = UART_CAP_FIFO,
165 },
166 [PORT_CIRRUS] = {
167 .name = "Cirrus",
168 .fifo_size = 1,
169 .tx_loadsz = 1,
170 },
171 [PORT_16650] = {
172 .name = "ST16650",
173 .fifo_size = 1,
174 .tx_loadsz = 1,
175 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
176 },
177 [PORT_16650V2] = {
178 .name = "ST16650V2",
179 .fifo_size = 32,
180 .tx_loadsz = 16,
181 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
182 UART_FCR_T_TRIG_00,
183 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
184 },
185 [PORT_16750] = {
186 .name = "TI16750",
187 .fifo_size = 64,
188 .tx_loadsz = 64,
189 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
190 UART_FCR7_64BYTE,
191 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
192 },
193 [PORT_STARTECH] = {
194 .name = "Startech",
195 .fifo_size = 1,
196 .tx_loadsz = 1,
197 },
198 [PORT_16C950] = {
199 .name = "16C950/954",
200 .fifo_size = 128,
201 .tx_loadsz = 128,
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
203 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
204 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
205 },
206 [PORT_16654] = {
207 .name = "ST16654",
208 .fifo_size = 64,
209 .tx_loadsz = 32,
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
211 UART_FCR_T_TRIG_10,
212 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
213 },
214 [PORT_16850] = {
215 .name = "XR16850",
216 .fifo_size = 128,
217 .tx_loadsz = 128,
218 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
219 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
220 },
221 [PORT_RSA] = {
222 .name = "RSA",
223 .fifo_size = 2048,
224 .tx_loadsz = 2048,
225 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
226 .flags = UART_CAP_FIFO,
227 },
228 [PORT_NS16550A] = {
229 .name = "NS16550A",
230 .fifo_size = 16,
231 .tx_loadsz = 16,
232 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
233 .flags = UART_CAP_FIFO | UART_NATSEMI,
234 },
235 [PORT_XSCALE] = {
236 .name = "XScale",
237 .fifo_size = 32,
238 .tx_loadsz = 32,
239 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
240 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
241 },
242 [PORT_RM9000] = {
243 .name = "RM9000",
244 .fifo_size = 16,
245 .tx_loadsz = 16,
246 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
247 .flags = UART_CAP_FIFO,
248 },
249 [PORT_OCTEON] = {
250 .name = "OCTEON",
251 .fifo_size = 64,
252 .tx_loadsz = 64,
253 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
254 .flags = UART_CAP_FIFO,
255 },
256 [PORT_AR7] = {
257 .name = "AR7",
258 .fifo_size = 16,
259 .tx_loadsz = 16,
260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
261 .flags = UART_CAP_FIFO | UART_CAP_AFE,
262 },
263 [PORT_U6_16550A] = {
264 .name = "U6_16550A",
265 .fifo_size = 64,
266 .tx_loadsz = 64,
267 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
268 .flags = UART_CAP_FIFO | UART_CAP_AFE,
269 },
270 [PORT_TEGRA] = {
271 .name = "Tegra",
272 .fifo_size = 32,
273 .tx_loadsz = 8,
274 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
275 UART_FCR_T_TRIG_01,
276 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
277 },
278 [PORT_XR17D15X] = {
279 .name = "XR17D15X",
280 .fifo_size = 64,
281 .tx_loadsz = 64,
282 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
283 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
284 },
285 [PORT_LPC3220] = {
286 .name = "LPC3220",
287 .fifo_size = 64,
288 .tx_loadsz = 32,
289 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
290 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
291 .flags = UART_CAP_FIFO,
292 },
293 [PORT_8250_CIR] = {
294 .name = "CIR port"
295 }
296 };
297
298 /* Uart divisor latch read */
299 static int default_serial_dl_read(struct uart_8250_port *up)
300 {
301 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
302 }
303
304 /* Uart divisor latch write */
305 static void default_serial_dl_write(struct uart_8250_port *up, int value)
306 {
307 serial_out(up, UART_DLL, value & 0xff);
308 serial_out(up, UART_DLM, value >> 8 & 0xff);
309 }
310
311 #ifdef CONFIG_MIPS_ALCHEMY
312
313 /* Au1x00 UART hardware has a weird register layout */
314 static const u8 au_io_in_map[] = {
315 [UART_RX] = 0,
316 [UART_IER] = 2,
317 [UART_IIR] = 3,
318 [UART_LCR] = 5,
319 [UART_MCR] = 6,
320 [UART_LSR] = 7,
321 [UART_MSR] = 8,
322 };
323
324 static const u8 au_io_out_map[] = {
325 [UART_TX] = 1,
326 [UART_IER] = 2,
327 [UART_FCR] = 4,
328 [UART_LCR] = 5,
329 [UART_MCR] = 6,
330 };
331
332 static unsigned int au_serial_in(struct uart_port *p, int offset)
333 {
334 offset = au_io_in_map[offset] << p->regshift;
335 return __raw_readl(p->membase + offset);
336 }
337
338 static void au_serial_out(struct uart_port *p, int offset, int value)
339 {
340 offset = au_io_out_map[offset] << p->regshift;
341 __raw_writel(value, p->membase + offset);
342 }
343
344 /* Au1x00 haven't got a standard divisor latch */
345 static int au_serial_dl_read(struct uart_8250_port *up)
346 {
347 return __raw_readl(up->port.membase + 0x28);
348 }
349
350 static void au_serial_dl_write(struct uart_8250_port *up, int value)
351 {
352 __raw_writel(value, up->port.membase + 0x28);
353 }
354
355 #endif
356
357 #ifdef CONFIG_SERIAL_8250_RM9K
358
359 static const u8
360 regmap_in[8] = {
361 [UART_RX] = 0x00,
362 [UART_IER] = 0x0c,
363 [UART_IIR] = 0x14,
364 [UART_LCR] = 0x1c,
365 [UART_MCR] = 0x20,
366 [UART_LSR] = 0x24,
367 [UART_MSR] = 0x28,
368 [UART_SCR] = 0x2c
369 },
370 regmap_out[8] = {
371 [UART_TX] = 0x04,
372 [UART_IER] = 0x0c,
373 [UART_FCR] = 0x18,
374 [UART_LCR] = 0x1c,
375 [UART_MCR] = 0x20,
376 [UART_LSR] = 0x24,
377 [UART_MSR] = 0x28,
378 [UART_SCR] = 0x2c
379 };
380
381 static unsigned int rm9k_serial_in(struct uart_port *p, int offset)
382 {
383 offset = regmap_in[offset] << p->regshift;
384 return readl(p->membase + offset);
385 }
386
387 static void rm9k_serial_out(struct uart_port *p, int offset, int value)
388 {
389 offset = regmap_out[offset] << p->regshift;
390 writel(value, p->membase + offset);
391 }
392
393 static int rm9k_serial_dl_read(struct uart_8250_port *up)
394 {
395 return ((__raw_readl(up->port.membase + 0x10) << 8) |
396 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff;
397 }
398
399 static void rm9k_serial_dl_write(struct uart_8250_port *up, int value)
400 {
401 __raw_writel(value, up->port.membase + 0x08);
402 __raw_writel(value >> 8, up->port.membase + 0x10);
403 }
404
405 #endif
406
407 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
408 {
409 offset = offset << p->regshift;
410 outb(p->hub6 - 1 + offset, p->iobase);
411 return inb(p->iobase + 1);
412 }
413
414 static void hub6_serial_out(struct uart_port *p, int offset, int value)
415 {
416 offset = offset << p->regshift;
417 outb(p->hub6 - 1 + offset, p->iobase);
418 outb(value, p->iobase + 1);
419 }
420
421 static unsigned int mem_serial_in(struct uart_port *p, int offset)
422 {
423 offset = offset << p->regshift;
424 return readb(p->membase + offset);
425 }
426
427 static void mem_serial_out(struct uart_port *p, int offset, int value)
428 {
429 offset = offset << p->regshift;
430 writeb(value, p->membase + offset);
431 }
432
433 static void mem32_serial_out(struct uart_port *p, int offset, int value)
434 {
435 offset = offset << p->regshift;
436 writel(value, p->membase + offset);
437 }
438
439 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
440 {
441 offset = offset << p->regshift;
442 return readl(p->membase + offset);
443 }
444
445 static unsigned int io_serial_in(struct uart_port *p, int offset)
446 {
447 offset = offset << p->regshift;
448 return inb(p->iobase + offset);
449 }
450
451 static void io_serial_out(struct uart_port *p, int offset, int value)
452 {
453 offset = offset << p->regshift;
454 outb(value, p->iobase + offset);
455 }
456
457 static int serial8250_default_handle_irq(struct uart_port *port);
458
459 static void set_io_from_upio(struct uart_port *p)
460 {
461 struct uart_8250_port *up =
462 container_of(p, struct uart_8250_port, port);
463
464 up->dl_read = default_serial_dl_read;
465 up->dl_write = default_serial_dl_write;
466
467 switch (p->iotype) {
468 case UPIO_HUB6:
469 p->serial_in = hub6_serial_in;
470 p->serial_out = hub6_serial_out;
471 break;
472
473 case UPIO_MEM:
474 p->serial_in = mem_serial_in;
475 p->serial_out = mem_serial_out;
476 break;
477
478 case UPIO_MEM32:
479 p->serial_in = mem32_serial_in;
480 p->serial_out = mem32_serial_out;
481 break;
482
483 #ifdef CONFIG_SERIAL_8250_RM9K
484 case UPIO_RM9000:
485 p->serial_in = rm9k_serial_in;
486 p->serial_out = rm9k_serial_out;
487 up->dl_read = rm9k_serial_dl_read;
488 up->dl_write = rm9k_serial_dl_write;
489 break;
490 #endif
491
492 #ifdef CONFIG_MIPS_ALCHEMY
493 case UPIO_AU:
494 p->serial_in = au_serial_in;
495 p->serial_out = au_serial_out;
496 up->dl_read = au_serial_dl_read;
497 up->dl_write = au_serial_dl_write;
498 break;
499 #endif
500
501 default:
502 p->serial_in = io_serial_in;
503 p->serial_out = io_serial_out;
504 break;
505 }
506 /* Remember loaded iotype */
507 up->cur_iotype = p->iotype;
508 p->handle_irq = serial8250_default_handle_irq;
509 }
510
511 static void
512 serial_port_out_sync(struct uart_port *p, int offset, int value)
513 {
514 switch (p->iotype) {
515 case UPIO_MEM:
516 case UPIO_MEM32:
517 case UPIO_AU:
518 p->serial_out(p, offset, value);
519 p->serial_in(p, UART_LCR); /* safe, no side-effects */
520 break;
521 default:
522 p->serial_out(p, offset, value);
523 }
524 }
525
526 /*
527 * For the 16C950
528 */
529 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
530 {
531 serial_out(up, UART_SCR, offset);
532 serial_out(up, UART_ICR, value);
533 }
534
535 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
536 {
537 unsigned int value;
538
539 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
540 serial_out(up, UART_SCR, offset);
541 value = serial_in(up, UART_ICR);
542 serial_icr_write(up, UART_ACR, up->acr);
543
544 return value;
545 }
546
547 /*
548 * FIFO support.
549 */
550 static void serial8250_clear_fifos(struct uart_8250_port *p)
551 {
552 if (p->capabilities & UART_CAP_FIFO) {
553 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
554 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
555 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
556 serial_out(p, UART_FCR, 0);
557 }
558 }
559
560 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
561 {
562 unsigned char fcr;
563
564 serial8250_clear_fifos(p);
565 fcr = uart_config[p->port.type].fcr;
566 serial_out(p, UART_FCR, fcr);
567 }
568 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
569
570 /*
571 * IER sleep support. UARTs which have EFRs need the "extended
572 * capability" bit enabled. Note that on XR16C850s, we need to
573 * reset LCR to write to IER.
574 */
575 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
576 {
577 if (p->capabilities & UART_CAP_SLEEP) {
578 if (p->capabilities & UART_CAP_EFR) {
579 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
580 serial_out(p, UART_EFR, UART_EFR_ECB);
581 serial_out(p, UART_LCR, 0);
582 }
583 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
584 if (p->capabilities & UART_CAP_EFR) {
585 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
586 serial_out(p, UART_EFR, 0);
587 serial_out(p, UART_LCR, 0);
588 }
589 }
590 }
591
592 #ifdef CONFIG_SERIAL_8250_RSA
593 /*
594 * Attempts to turn on the RSA FIFO. Returns zero on failure.
595 * We set the port uart clock rate if we succeed.
596 */
597 static int __enable_rsa(struct uart_8250_port *up)
598 {
599 unsigned char mode;
600 int result;
601
602 mode = serial_in(up, UART_RSA_MSR);
603 result = mode & UART_RSA_MSR_FIFO;
604
605 if (!result) {
606 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
607 mode = serial_in(up, UART_RSA_MSR);
608 result = mode & UART_RSA_MSR_FIFO;
609 }
610
611 if (result)
612 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
613
614 return result;
615 }
616
617 static void enable_rsa(struct uart_8250_port *up)
618 {
619 if (up->port.type == PORT_RSA) {
620 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
621 spin_lock_irq(&up->port.lock);
622 __enable_rsa(up);
623 spin_unlock_irq(&up->port.lock);
624 }
625 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
626 serial_out(up, UART_RSA_FRR, 0);
627 }
628 }
629
630 /*
631 * Attempts to turn off the RSA FIFO. Returns zero on failure.
632 * It is unknown why interrupts were disabled in here. However,
633 * the caller is expected to preserve this behaviour by grabbing
634 * the spinlock before calling this function.
635 */
636 static void disable_rsa(struct uart_8250_port *up)
637 {
638 unsigned char mode;
639 int result;
640
641 if (up->port.type == PORT_RSA &&
642 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
643 spin_lock_irq(&up->port.lock);
644
645 mode = serial_in(up, UART_RSA_MSR);
646 result = !(mode & UART_RSA_MSR_FIFO);
647
648 if (!result) {
649 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
650 mode = serial_in(up, UART_RSA_MSR);
651 result = !(mode & UART_RSA_MSR_FIFO);
652 }
653
654 if (result)
655 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
656 spin_unlock_irq(&up->port.lock);
657 }
658 }
659 #endif /* CONFIG_SERIAL_8250_RSA */
660
661 /*
662 * This is a quickie test to see how big the FIFO is.
663 * It doesn't work at all the time, more's the pity.
664 */
665 static int size_fifo(struct uart_8250_port *up)
666 {
667 unsigned char old_fcr, old_mcr, old_lcr;
668 unsigned short old_dl;
669 int count;
670
671 old_lcr = serial_in(up, UART_LCR);
672 serial_out(up, UART_LCR, 0);
673 old_fcr = serial_in(up, UART_FCR);
674 old_mcr = serial_in(up, UART_MCR);
675 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
676 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
677 serial_out(up, UART_MCR, UART_MCR_LOOP);
678 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
679 old_dl = serial_dl_read(up);
680 serial_dl_write(up, 0x0001);
681 serial_out(up, UART_LCR, 0x03);
682 for (count = 0; count < 256; count++)
683 serial_out(up, UART_TX, count);
684 mdelay(20);/* FIXME - schedule_timeout */
685 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
686 (count < 256); count++)
687 serial_in(up, UART_RX);
688 serial_out(up, UART_FCR, old_fcr);
689 serial_out(up, UART_MCR, old_mcr);
690 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
691 serial_dl_write(up, old_dl);
692 serial_out(up, UART_LCR, old_lcr);
693
694 return count;
695 }
696
697 /*
698 * Read UART ID using the divisor method - set DLL and DLM to zero
699 * and the revision will be in DLL and device type in DLM. We
700 * preserve the device state across this.
701 */
702 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
703 {
704 unsigned char old_dll, old_dlm, old_lcr;
705 unsigned int id;
706
707 old_lcr = serial_in(p, UART_LCR);
708 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
709
710 old_dll = serial_in(p, UART_DLL);
711 old_dlm = serial_in(p, UART_DLM);
712
713 serial_out(p, UART_DLL, 0);
714 serial_out(p, UART_DLM, 0);
715
716 id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8;
717
718 serial_out(p, UART_DLL, old_dll);
719 serial_out(p, UART_DLM, old_dlm);
720 serial_out(p, UART_LCR, old_lcr);
721
722 return id;
723 }
724
725 /*
726 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
727 * When this function is called we know it is at least a StarTech
728 * 16650 V2, but it might be one of several StarTech UARTs, or one of
729 * its clones. (We treat the broken original StarTech 16650 V1 as a
730 * 16550, and why not? Startech doesn't seem to even acknowledge its
731 * existence.)
732 *
733 * What evil have men's minds wrought...
734 */
735 static void autoconfig_has_efr(struct uart_8250_port *up)
736 {
737 unsigned int id1, id2, id3, rev;
738
739 /*
740 * Everything with an EFR has SLEEP
741 */
742 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
743
744 /*
745 * First we check to see if it's an Oxford Semiconductor UART.
746 *
747 * If we have to do this here because some non-National
748 * Semiconductor clone chips lock up if you try writing to the
749 * LSR register (which serial_icr_read does)
750 */
751
752 /*
753 * Check for Oxford Semiconductor 16C950.
754 *
755 * EFR [4] must be set else this test fails.
756 *
757 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
758 * claims that it's needed for 952 dual UART's (which are not
759 * recommended for new designs).
760 */
761 up->acr = 0;
762 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
763 serial_out(up, UART_EFR, UART_EFR_ECB);
764 serial_out(up, UART_LCR, 0x00);
765 id1 = serial_icr_read(up, UART_ID1);
766 id2 = serial_icr_read(up, UART_ID2);
767 id3 = serial_icr_read(up, UART_ID3);
768 rev = serial_icr_read(up, UART_REV);
769
770 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
771
772 if (id1 == 0x16 && id2 == 0xC9 &&
773 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
774 up->port.type = PORT_16C950;
775
776 /*
777 * Enable work around for the Oxford Semiconductor 952 rev B
778 * chip which causes it to seriously miscalculate baud rates
779 * when DLL is 0.
780 */
781 if (id3 == 0x52 && rev == 0x01)
782 up->bugs |= UART_BUG_QUOT;
783 return;
784 }
785
786 /*
787 * We check for a XR16C850 by setting DLL and DLM to 0, and then
788 * reading back DLL and DLM. The chip type depends on the DLM
789 * value read back:
790 * 0x10 - XR16C850 and the DLL contains the chip revision.
791 * 0x12 - XR16C2850.
792 * 0x14 - XR16C854.
793 */
794 id1 = autoconfig_read_divisor_id(up);
795 DEBUG_AUTOCONF("850id=%04x ", id1);
796
797 id2 = id1 >> 8;
798 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
799 up->port.type = PORT_16850;
800 return;
801 }
802
803 /*
804 * It wasn't an XR16C850.
805 *
806 * We distinguish between the '654 and the '650 by counting
807 * how many bytes are in the FIFO. I'm using this for now,
808 * since that's the technique that was sent to me in the
809 * serial driver update, but I'm not convinced this works.
810 * I've had problems doing this in the past. -TYT
811 */
812 if (size_fifo(up) == 64)
813 up->port.type = PORT_16654;
814 else
815 up->port.type = PORT_16650V2;
816 }
817
818 /*
819 * We detected a chip without a FIFO. Only two fall into
820 * this category - the original 8250 and the 16450. The
821 * 16450 has a scratch register (accessible with LCR=0)
822 */
823 static void autoconfig_8250(struct uart_8250_port *up)
824 {
825 unsigned char scratch, status1, status2;
826
827 up->port.type = PORT_8250;
828
829 scratch = serial_in(up, UART_SCR);
830 serial_out(up, UART_SCR, 0xa5);
831 status1 = serial_in(up, UART_SCR);
832 serial_out(up, UART_SCR, 0x5a);
833 status2 = serial_in(up, UART_SCR);
834 serial_out(up, UART_SCR, scratch);
835
836 if (status1 == 0xa5 && status2 == 0x5a)
837 up->port.type = PORT_16450;
838 }
839
840 static int broken_efr(struct uart_8250_port *up)
841 {
842 /*
843 * Exar ST16C2550 "A2" devices incorrectly detect as
844 * having an EFR, and report an ID of 0x0201. See
845 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
846 */
847 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
848 return 1;
849
850 return 0;
851 }
852
853 static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
854 {
855 unsigned char status;
856
857 status = serial_in(up, 0x04); /* EXCR2 */
858 #define PRESL(x) ((x) & 0x30)
859 if (PRESL(status) == 0x10) {
860 /* already in high speed mode */
861 return 0;
862 } else {
863 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
864 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
865 serial_out(up, 0x04, status);
866 }
867 return 1;
868 }
869
870 /*
871 * We know that the chip has FIFOs. Does it have an EFR? The
872 * EFR is located in the same register position as the IIR and
873 * we know the top two bits of the IIR are currently set. The
874 * EFR should contain zero. Try to read the EFR.
875 */
876 static void autoconfig_16550a(struct uart_8250_port *up)
877 {
878 unsigned char status1, status2;
879 unsigned int iersave;
880
881 up->port.type = PORT_16550A;
882 up->capabilities |= UART_CAP_FIFO;
883
884 /*
885 * Check for presence of the EFR when DLAB is set.
886 * Only ST16C650V1 UARTs pass this test.
887 */
888 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
889 if (serial_in(up, UART_EFR) == 0) {
890 serial_out(up, UART_EFR, 0xA8);
891 if (serial_in(up, UART_EFR) != 0) {
892 DEBUG_AUTOCONF("EFRv1 ");
893 up->port.type = PORT_16650;
894 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
895 } else {
896 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
897 }
898 serial_out(up, UART_EFR, 0);
899 return;
900 }
901
902 /*
903 * Maybe it requires 0xbf to be written to the LCR.
904 * (other ST16C650V2 UARTs, TI16C752A, etc)
905 */
906 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
907 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
908 DEBUG_AUTOCONF("EFRv2 ");
909 autoconfig_has_efr(up);
910 return;
911 }
912
913 /*
914 * Check for a National Semiconductor SuperIO chip.
915 * Attempt to switch to bank 2, read the value of the LOOP bit
916 * from EXCR1. Switch back to bank 0, change it in MCR. Then
917 * switch back to bank 2, read it from EXCR1 again and check
918 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
919 */
920 serial_out(up, UART_LCR, 0);
921 status1 = serial_in(up, UART_MCR);
922 serial_out(up, UART_LCR, 0xE0);
923 status2 = serial_in(up, 0x02); /* EXCR1 */
924
925 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
926 serial_out(up, UART_LCR, 0);
927 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
928 serial_out(up, UART_LCR, 0xE0);
929 status2 = serial_in(up, 0x02); /* EXCR1 */
930 serial_out(up, UART_LCR, 0);
931 serial_out(up, UART_MCR, status1);
932
933 if ((status2 ^ status1) & UART_MCR_LOOP) {
934 unsigned short quot;
935
936 serial_out(up, UART_LCR, 0xE0);
937
938 quot = serial_dl_read(up);
939 quot <<= 3;
940
941 if (ns16550a_goto_highspeed(up))
942 serial_dl_write(up, quot);
943
944 serial_out(up, UART_LCR, 0);
945
946 up->port.uartclk = 921600*16;
947 up->port.type = PORT_NS16550A;
948 up->capabilities |= UART_NATSEMI;
949 return;
950 }
951 }
952
953 /*
954 * No EFR. Try to detect a TI16750, which only sets bit 5 of
955 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
956 * Try setting it with and without DLAB set. Cheap clones
957 * set bit 5 without DLAB set.
958 */
959 serial_out(up, UART_LCR, 0);
960 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
961 status1 = serial_in(up, UART_IIR) >> 5;
962 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
963 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
964 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
965 status2 = serial_in(up, UART_IIR) >> 5;
966 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
967 serial_out(up, UART_LCR, 0);
968
969 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
970
971 if (status1 == 6 && status2 == 7) {
972 up->port.type = PORT_16750;
973 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
974 return;
975 }
976
977 /*
978 * Try writing and reading the UART_IER_UUE bit (b6).
979 * If it works, this is probably one of the Xscale platform's
980 * internal UARTs.
981 * We're going to explicitly set the UUE bit to 0 before
982 * trying to write and read a 1 just to make sure it's not
983 * already a 1 and maybe locked there before we even start start.
984 */
985 iersave = serial_in(up, UART_IER);
986 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
987 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
988 /*
989 * OK it's in a known zero state, try writing and reading
990 * without disturbing the current state of the other bits.
991 */
992 serial_out(up, UART_IER, iersave | UART_IER_UUE);
993 if (serial_in(up, UART_IER) & UART_IER_UUE) {
994 /*
995 * It's an Xscale.
996 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
997 */
998 DEBUG_AUTOCONF("Xscale ");
999 up->port.type = PORT_XSCALE;
1000 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1001 return;
1002 }
1003 } else {
1004 /*
1005 * If we got here we couldn't force the IER_UUE bit to 0.
1006 * Log it and continue.
1007 */
1008 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1009 }
1010 serial_out(up, UART_IER, iersave);
1011
1012 /*
1013 * Exar uarts have EFR in a weird location
1014 */
1015 if (up->port.flags & UPF_EXAR_EFR) {
1016 up->port.type = PORT_XR17D15X;
1017 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR;
1018 }
1019
1020 /*
1021 * We distinguish between 16550A and U6 16550A by counting
1022 * how many bytes are in the FIFO.
1023 */
1024 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1025 up->port.type = PORT_U6_16550A;
1026 up->capabilities |= UART_CAP_AFE;
1027 }
1028 }
1029
1030 /*
1031 * This routine is called by rs_init() to initialize a specific serial
1032 * port. It determines what type of UART chip this serial port is
1033 * using: 8250, 16450, 16550, 16550A. The important question is
1034 * whether or not this UART is a 16550A or not, since this will
1035 * determine whether or not we can use its FIFO features or not.
1036 */
1037 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1038 {
1039 unsigned char status1, scratch, scratch2, scratch3;
1040 unsigned char save_lcr, save_mcr;
1041 struct uart_port *port = &up->port;
1042 unsigned long flags;
1043 unsigned int old_capabilities;
1044
1045 if (!port->iobase && !port->mapbase && !port->membase)
1046 return;
1047
1048 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1049 serial_index(port), port->iobase, port->membase);
1050
1051 /*
1052 * We really do need global IRQs disabled here - we're going to
1053 * be frobbing the chips IRQ enable register to see if it exists.
1054 */
1055 spin_lock_irqsave(&port->lock, flags);
1056
1057 up->capabilities = 0;
1058 up->bugs = 0;
1059
1060 if (!(port->flags & UPF_BUGGY_UART)) {
1061 /*
1062 * Do a simple existence test first; if we fail this,
1063 * there's no point trying anything else.
1064 *
1065 * 0x80 is used as a nonsense port to prevent against
1066 * false positives due to ISA bus float. The
1067 * assumption is that 0x80 is a non-existent port;
1068 * which should be safe since include/asm/io.h also
1069 * makes this assumption.
1070 *
1071 * Note: this is safe as long as MCR bit 4 is clear
1072 * and the device is in "PC" mode.
1073 */
1074 scratch = serial_in(up, UART_IER);
1075 serial_out(up, UART_IER, 0);
1076 #ifdef __i386__
1077 outb(0xff, 0x080);
1078 #endif
1079 /*
1080 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1081 * 16C754B) allow only to modify them if an EFR bit is set.
1082 */
1083 scratch2 = serial_in(up, UART_IER) & 0x0f;
1084 serial_out(up, UART_IER, 0x0F);
1085 #ifdef __i386__
1086 outb(0, 0x080);
1087 #endif
1088 scratch3 = serial_in(up, UART_IER) & 0x0f;
1089 serial_out(up, UART_IER, scratch);
1090 if (scratch2 != 0 || scratch3 != 0x0F) {
1091 /*
1092 * We failed; there's nothing here
1093 */
1094 spin_unlock_irqrestore(&port->lock, flags);
1095 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1096 scratch2, scratch3);
1097 goto out;
1098 }
1099 }
1100
1101 save_mcr = serial_in(up, UART_MCR);
1102 save_lcr = serial_in(up, UART_LCR);
1103
1104 /*
1105 * Check to see if a UART is really there. Certain broken
1106 * internal modems based on the Rockwell chipset fail this
1107 * test, because they apparently don't implement the loopback
1108 * test mode. So this test is skipped on the COM 1 through
1109 * COM 4 ports. This *should* be safe, since no board
1110 * manufacturer would be stupid enough to design a board
1111 * that conflicts with COM 1-4 --- we hope!
1112 */
1113 if (!(port->flags & UPF_SKIP_TEST)) {
1114 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1115 status1 = serial_in(up, UART_MSR) & 0xF0;
1116 serial_out(up, UART_MCR, save_mcr);
1117 if (status1 != 0x90) {
1118 spin_unlock_irqrestore(&port->lock, flags);
1119 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1120 status1);
1121 goto out;
1122 }
1123 }
1124
1125 /*
1126 * We're pretty sure there's a port here. Lets find out what
1127 * type of port it is. The IIR top two bits allows us to find
1128 * out if it's 8250 or 16450, 16550, 16550A or later. This
1129 * determines what we test for next.
1130 *
1131 * We also initialise the EFR (if any) to zero for later. The
1132 * EFR occupies the same register location as the FCR and IIR.
1133 */
1134 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1135 serial_out(up, UART_EFR, 0);
1136 serial_out(up, UART_LCR, 0);
1137
1138 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1139 scratch = serial_in(up, UART_IIR) >> 6;
1140
1141 switch (scratch) {
1142 case 0:
1143 autoconfig_8250(up);
1144 break;
1145 case 1:
1146 port->type = PORT_UNKNOWN;
1147 break;
1148 case 2:
1149 port->type = PORT_16550;
1150 break;
1151 case 3:
1152 autoconfig_16550a(up);
1153 break;
1154 }
1155
1156 #ifdef CONFIG_SERIAL_8250_RSA
1157 /*
1158 * Only probe for RSA ports if we got the region.
1159 */
1160 if (port->type == PORT_16550A && probeflags & PROBE_RSA) {
1161 int i;
1162
1163 for (i = 0 ; i < probe_rsa_count; ++i) {
1164 if (probe_rsa[i] == port->iobase && __enable_rsa(up)) {
1165 port->type = PORT_RSA;
1166 break;
1167 }
1168 }
1169 }
1170 #endif
1171
1172 serial_out(up, UART_LCR, save_lcr);
1173
1174 port->fifosize = uart_config[up->port.type].fifo_size;
1175 old_capabilities = up->capabilities;
1176 up->capabilities = uart_config[port->type].flags;
1177 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1178
1179 if (port->type == PORT_UNKNOWN)
1180 goto out_lock;
1181
1182 /*
1183 * Reset the UART.
1184 */
1185 #ifdef CONFIG_SERIAL_8250_RSA
1186 if (port->type == PORT_RSA)
1187 serial_out(up, UART_RSA_FRR, 0);
1188 #endif
1189 serial_out(up, UART_MCR, save_mcr);
1190 serial8250_clear_fifos(up);
1191 serial_in(up, UART_RX);
1192 if (up->capabilities & UART_CAP_UUE)
1193 serial_out(up, UART_IER, UART_IER_UUE);
1194 else
1195 serial_out(up, UART_IER, 0);
1196
1197 out_lock:
1198 spin_unlock_irqrestore(&port->lock, flags);
1199 if (up->capabilities != old_capabilities) {
1200 printk(KERN_WARNING
1201 "ttyS%d: detected caps %08x should be %08x\n",
1202 serial_index(port), old_capabilities,
1203 up->capabilities);
1204 }
1205 out:
1206 DEBUG_AUTOCONF("iir=%d ", scratch);
1207 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1208 }
1209
1210 static void autoconfig_irq(struct uart_8250_port *up)
1211 {
1212 struct uart_port *port = &up->port;
1213 unsigned char save_mcr, save_ier;
1214 unsigned char save_ICP = 0;
1215 unsigned int ICP = 0;
1216 unsigned long irqs;
1217 int irq;
1218
1219 if (port->flags & UPF_FOURPORT) {
1220 ICP = (port->iobase & 0xfe0) | 0x1f;
1221 save_ICP = inb_p(ICP);
1222 outb_p(0x80, ICP);
1223 inb_p(ICP);
1224 }
1225
1226 /* forget possible initially masked and pending IRQ */
1227 probe_irq_off(probe_irq_on());
1228 save_mcr = serial_in(up, UART_MCR);
1229 save_ier = serial_in(up, UART_IER);
1230 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1231
1232 irqs = probe_irq_on();
1233 serial_out(up, UART_MCR, 0);
1234 udelay(10);
1235 if (port->flags & UPF_FOURPORT) {
1236 serial_out(up, UART_MCR,
1237 UART_MCR_DTR | UART_MCR_RTS);
1238 } else {
1239 serial_out(up, UART_MCR,
1240 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1241 }
1242 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1243 serial_in(up, UART_LSR);
1244 serial_in(up, UART_RX);
1245 serial_in(up, UART_IIR);
1246 serial_in(up, UART_MSR);
1247 serial_out(up, UART_TX, 0xFF);
1248 udelay(20);
1249 irq = probe_irq_off(irqs);
1250
1251 serial_out(up, UART_MCR, save_mcr);
1252 serial_out(up, UART_IER, save_ier);
1253
1254 if (port->flags & UPF_FOURPORT)
1255 outb_p(save_ICP, ICP);
1256
1257 port->irq = (irq > 0) ? irq : 0;
1258 }
1259
1260 static inline void __stop_tx(struct uart_8250_port *p)
1261 {
1262 if (p->ier & UART_IER_THRI) {
1263 p->ier &= ~UART_IER_THRI;
1264 serial_out(p, UART_IER, p->ier);
1265 }
1266 }
1267
1268 static void serial8250_stop_tx(struct uart_port *port)
1269 {
1270 struct uart_8250_port *up =
1271 container_of(port, struct uart_8250_port, port);
1272
1273 __stop_tx(up);
1274
1275 /*
1276 * We really want to stop the transmitter from sending.
1277 */
1278 if (port->type == PORT_16C950) {
1279 up->acr |= UART_ACR_TXDIS;
1280 serial_icr_write(up, UART_ACR, up->acr);
1281 }
1282 }
1283
1284 static void serial8250_start_tx(struct uart_port *port)
1285 {
1286 struct uart_8250_port *up =
1287 container_of(port, struct uart_8250_port, port);
1288
1289 if (!(up->ier & UART_IER_THRI)) {
1290 up->ier |= UART_IER_THRI;
1291 serial_port_out(port, UART_IER, up->ier);
1292
1293 if (up->bugs & UART_BUG_TXEN) {
1294 unsigned char lsr;
1295 lsr = serial_in(up, UART_LSR);
1296 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1297 if ((port->type == PORT_RM9000) ?
1298 (lsr & UART_LSR_THRE) :
1299 (lsr & UART_LSR_TEMT))
1300 serial8250_tx_chars(up);
1301 }
1302 }
1303
1304 /*
1305 * Re-enable the transmitter if we disabled it.
1306 */
1307 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1308 up->acr &= ~UART_ACR_TXDIS;
1309 serial_icr_write(up, UART_ACR, up->acr);
1310 }
1311 }
1312
1313 static void serial8250_stop_rx(struct uart_port *port)
1314 {
1315 struct uart_8250_port *up =
1316 container_of(port, struct uart_8250_port, port);
1317
1318 up->ier &= ~UART_IER_RLSI;
1319 up->port.read_status_mask &= ~UART_LSR_DR;
1320 serial_port_out(port, UART_IER, up->ier);
1321 }
1322
1323 static void serial8250_enable_ms(struct uart_port *port)
1324 {
1325 struct uart_8250_port *up =
1326 container_of(port, struct uart_8250_port, port);
1327
1328 /* no MSR capabilities */
1329 if (up->bugs & UART_BUG_NOMSR)
1330 return;
1331
1332 up->ier |= UART_IER_MSI;
1333 serial_port_out(port, UART_IER, up->ier);
1334 }
1335
1336 /*
1337 * serial8250_rx_chars: processes according to the passed in LSR
1338 * value, and returns the remaining LSR bits not handled
1339 * by this Rx routine.
1340 */
1341 unsigned char
1342 serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1343 {
1344 struct uart_port *port = &up->port;
1345 struct tty_struct *tty = port->state->port.tty;
1346 unsigned char ch;
1347 int max_count = 256;
1348 char flag;
1349
1350 do {
1351 if (likely(lsr & UART_LSR_DR))
1352 ch = serial_in(up, UART_RX);
1353 else
1354 /*
1355 * Intel 82571 has a Serial Over Lan device that will
1356 * set UART_LSR_BI without setting UART_LSR_DR when
1357 * it receives a break. To avoid reading from the
1358 * receive buffer without UART_LSR_DR bit set, we
1359 * just force the read character to be 0
1360 */
1361 ch = 0;
1362
1363 flag = TTY_NORMAL;
1364 port->icount.rx++;
1365
1366 lsr |= up->lsr_saved_flags;
1367 up->lsr_saved_flags = 0;
1368
1369 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1370 if (lsr & UART_LSR_BI) {
1371 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1372 port->icount.brk++;
1373 /*
1374 * We do the SysRQ and SAK checking
1375 * here because otherwise the break
1376 * may get masked by ignore_status_mask
1377 * or read_status_mask.
1378 */
1379 if (uart_handle_break(port))
1380 goto ignore_char;
1381 } else if (lsr & UART_LSR_PE)
1382 port->icount.parity++;
1383 else if (lsr & UART_LSR_FE)
1384 port->icount.frame++;
1385 if (lsr & UART_LSR_OE)
1386 port->icount.overrun++;
1387
1388 /*
1389 * Mask off conditions which should be ignored.
1390 */
1391 lsr &= port->read_status_mask;
1392
1393 if (lsr & UART_LSR_BI) {
1394 DEBUG_INTR("handling break....");
1395 flag = TTY_BREAK;
1396 } else if (lsr & UART_LSR_PE)
1397 flag = TTY_PARITY;
1398 else if (lsr & UART_LSR_FE)
1399 flag = TTY_FRAME;
1400 }
1401 if (uart_handle_sysrq_char(port, ch))
1402 goto ignore_char;
1403
1404 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1405
1406 ignore_char:
1407 lsr = serial_in(up, UART_LSR);
1408 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1409 spin_unlock(&port->lock);
1410 tty_flip_buffer_push(tty);
1411 spin_lock(&port->lock);
1412 return lsr;
1413 }
1414 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1415
1416 void serial8250_tx_chars(struct uart_8250_port *up)
1417 {
1418 struct uart_port *port = &up->port;
1419 struct circ_buf *xmit = &port->state->xmit;
1420 int count;
1421
1422 if (port->x_char) {
1423 serial_out(up, UART_TX, port->x_char);
1424 port->icount.tx++;
1425 port->x_char = 0;
1426 return;
1427 }
1428 if (uart_tx_stopped(port)) {
1429 serial8250_stop_tx(port);
1430 return;
1431 }
1432 if (uart_circ_empty(xmit)) {
1433 __stop_tx(up);
1434 return;
1435 }
1436
1437 count = up->tx_loadsz;
1438 do {
1439 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1440 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1441 port->icount.tx++;
1442 if (uart_circ_empty(xmit))
1443 break;
1444 } while (--count > 0);
1445
1446 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1447 uart_write_wakeup(port);
1448
1449 DEBUG_INTR("THRE...");
1450
1451 if (uart_circ_empty(xmit))
1452 __stop_tx(up);
1453 }
1454 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1455
1456 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1457 {
1458 struct uart_port *port = &up->port;
1459 unsigned int status = serial_in(up, UART_MSR);
1460
1461 status |= up->msr_saved_flags;
1462 up->msr_saved_flags = 0;
1463 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1464 port->state != NULL) {
1465 if (status & UART_MSR_TERI)
1466 port->icount.rng++;
1467 if (status & UART_MSR_DDSR)
1468 port->icount.dsr++;
1469 if (status & UART_MSR_DDCD)
1470 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1471 if (status & UART_MSR_DCTS)
1472 uart_handle_cts_change(port, status & UART_MSR_CTS);
1473
1474 wake_up_interruptible(&port->state->port.delta_msr_wait);
1475 }
1476
1477 return status;
1478 }
1479 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1480
1481 /*
1482 * This handles the interrupt from one port.
1483 */
1484 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1485 {
1486 unsigned char status;
1487 unsigned long flags;
1488 struct uart_8250_port *up =
1489 container_of(port, struct uart_8250_port, port);
1490
1491 if (iir & UART_IIR_NO_INT)
1492 return 0;
1493
1494 spin_lock_irqsave(&port->lock, flags);
1495
1496 status = serial_port_in(port, UART_LSR);
1497
1498 DEBUG_INTR("status = %x...", status);
1499
1500 if (status & (UART_LSR_DR | UART_LSR_BI))
1501 status = serial8250_rx_chars(up, status);
1502 serial8250_modem_status(up);
1503 if (status & UART_LSR_THRE)
1504 serial8250_tx_chars(up);
1505
1506 spin_unlock_irqrestore(&port->lock, flags);
1507 return 1;
1508 }
1509 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1510
1511 static int serial8250_default_handle_irq(struct uart_port *port)
1512 {
1513 unsigned int iir = serial_port_in(port, UART_IIR);
1514
1515 return serial8250_handle_irq(port, iir);
1516 }
1517
1518 /*
1519 * This is the serial driver's interrupt routine.
1520 *
1521 * Arjan thinks the old way was overly complex, so it got simplified.
1522 * Alan disagrees, saying that need the complexity to handle the weird
1523 * nature of ISA shared interrupts. (This is a special exception.)
1524 *
1525 * In order to handle ISA shared interrupts properly, we need to check
1526 * that all ports have been serviced, and therefore the ISA interrupt
1527 * line has been de-asserted.
1528 *
1529 * This means we need to loop through all ports. checking that they
1530 * don't have an interrupt pending.
1531 */
1532 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1533 {
1534 struct irq_info *i = dev_id;
1535 struct list_head *l, *end = NULL;
1536 int pass_counter = 0, handled = 0;
1537
1538 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1539
1540 spin_lock(&i->lock);
1541
1542 l = i->head;
1543 do {
1544 struct uart_8250_port *up;
1545 struct uart_port *port;
1546
1547 up = list_entry(l, struct uart_8250_port, list);
1548 port = &up->port;
1549
1550 if (port->handle_irq(port)) {
1551 handled = 1;
1552 end = NULL;
1553 } else if (end == NULL)
1554 end = l;
1555
1556 l = l->next;
1557
1558 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1559 /* If we hit this, we're dead. */
1560 printk_ratelimited(KERN_ERR
1561 "serial8250: too much work for irq%d\n", irq);
1562 break;
1563 }
1564 } while (l != end);
1565
1566 spin_unlock(&i->lock);
1567
1568 DEBUG_INTR("end.\n");
1569
1570 return IRQ_RETVAL(handled);
1571 }
1572
1573 /*
1574 * To support ISA shared interrupts, we need to have one interrupt
1575 * handler that ensures that the IRQ line has been deasserted
1576 * before returning. Failing to do this will result in the IRQ
1577 * line being stuck active, and, since ISA irqs are edge triggered,
1578 * no more IRQs will be seen.
1579 */
1580 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1581 {
1582 spin_lock_irq(&i->lock);
1583
1584 if (!list_empty(i->head)) {
1585 if (i->head == &up->list)
1586 i->head = i->head->next;
1587 list_del(&up->list);
1588 } else {
1589 BUG_ON(i->head != &up->list);
1590 i->head = NULL;
1591 }
1592 spin_unlock_irq(&i->lock);
1593 /* List empty so throw away the hash node */
1594 if (i->head == NULL) {
1595 hlist_del(&i->node);
1596 kfree(i);
1597 }
1598 }
1599
1600 static int serial_link_irq_chain(struct uart_8250_port *up)
1601 {
1602 struct hlist_head *h;
1603 struct hlist_node *n;
1604 struct irq_info *i;
1605 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1606
1607 mutex_lock(&hash_mutex);
1608
1609 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1610
1611 hlist_for_each(n, h) {
1612 i = hlist_entry(n, struct irq_info, node);
1613 if (i->irq == up->port.irq)
1614 break;
1615 }
1616
1617 if (n == NULL) {
1618 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1619 if (i == NULL) {
1620 mutex_unlock(&hash_mutex);
1621 return -ENOMEM;
1622 }
1623 spin_lock_init(&i->lock);
1624 i->irq = up->port.irq;
1625 hlist_add_head(&i->node, h);
1626 }
1627 mutex_unlock(&hash_mutex);
1628
1629 spin_lock_irq(&i->lock);
1630
1631 if (i->head) {
1632 list_add(&up->list, i->head);
1633 spin_unlock_irq(&i->lock);
1634
1635 ret = 0;
1636 } else {
1637 INIT_LIST_HEAD(&up->list);
1638 i->head = &up->list;
1639 spin_unlock_irq(&i->lock);
1640 irq_flags |= up->port.irqflags;
1641 ret = request_irq(up->port.irq, serial8250_interrupt,
1642 irq_flags, "serial", i);
1643 if (ret < 0)
1644 serial_do_unlink(i, up);
1645 }
1646
1647 return ret;
1648 }
1649
1650 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1651 {
1652 struct irq_info *i;
1653 struct hlist_node *n;
1654 struct hlist_head *h;
1655
1656 mutex_lock(&hash_mutex);
1657
1658 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1659
1660 hlist_for_each(n, h) {
1661 i = hlist_entry(n, struct irq_info, node);
1662 if (i->irq == up->port.irq)
1663 break;
1664 }
1665
1666 BUG_ON(n == NULL);
1667 BUG_ON(i->head == NULL);
1668
1669 if (list_empty(i->head))
1670 free_irq(up->port.irq, i);
1671
1672 serial_do_unlink(i, up);
1673 mutex_unlock(&hash_mutex);
1674 }
1675
1676 /*
1677 * This function is used to handle ports that do not have an
1678 * interrupt. This doesn't work very well for 16450's, but gives
1679 * barely passable results for a 16550A. (Although at the expense
1680 * of much CPU overhead).
1681 */
1682 static void serial8250_timeout(unsigned long data)
1683 {
1684 struct uart_8250_port *up = (struct uart_8250_port *)data;
1685
1686 up->port.handle_irq(&up->port);
1687 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1688 }
1689
1690 static void serial8250_backup_timeout(unsigned long data)
1691 {
1692 struct uart_8250_port *up = (struct uart_8250_port *)data;
1693 unsigned int iir, ier = 0, lsr;
1694 unsigned long flags;
1695
1696 spin_lock_irqsave(&up->port.lock, flags);
1697
1698 /*
1699 * Must disable interrupts or else we risk racing with the interrupt
1700 * based handler.
1701 */
1702 if (up->port.irq) {
1703 ier = serial_in(up, UART_IER);
1704 serial_out(up, UART_IER, 0);
1705 }
1706
1707 iir = serial_in(up, UART_IIR);
1708
1709 /*
1710 * This should be a safe test for anyone who doesn't trust the
1711 * IIR bits on their UART, but it's specifically designed for
1712 * the "Diva" UART used on the management processor on many HP
1713 * ia64 and parisc boxes.
1714 */
1715 lsr = serial_in(up, UART_LSR);
1716 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1717 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1718 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1719 (lsr & UART_LSR_THRE)) {
1720 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1721 iir |= UART_IIR_THRI;
1722 }
1723
1724 if (!(iir & UART_IIR_NO_INT))
1725 serial8250_tx_chars(up);
1726
1727 if (up->port.irq)
1728 serial_out(up, UART_IER, ier);
1729
1730 spin_unlock_irqrestore(&up->port.lock, flags);
1731
1732 /* Standard timer interval plus 0.2s to keep the port running */
1733 mod_timer(&up->timer,
1734 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1735 }
1736
1737 static unsigned int serial8250_tx_empty(struct uart_port *port)
1738 {
1739 struct uart_8250_port *up =
1740 container_of(port, struct uart_8250_port, port);
1741 unsigned long flags;
1742 unsigned int lsr;
1743
1744 spin_lock_irqsave(&port->lock, flags);
1745 lsr = serial_port_in(port, UART_LSR);
1746 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1747 spin_unlock_irqrestore(&port->lock, flags);
1748
1749 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1750 }
1751
1752 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1753 {
1754 struct uart_8250_port *up =
1755 container_of(port, struct uart_8250_port, port);
1756 unsigned int status;
1757 unsigned int ret;
1758
1759 status = serial8250_modem_status(up);
1760
1761 ret = 0;
1762 if (status & UART_MSR_DCD)
1763 ret |= TIOCM_CAR;
1764 if (status & UART_MSR_RI)
1765 ret |= TIOCM_RNG;
1766 if (status & UART_MSR_DSR)
1767 ret |= TIOCM_DSR;
1768 if (status & UART_MSR_CTS)
1769 ret |= TIOCM_CTS;
1770 return ret;
1771 }
1772
1773 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1774 {
1775 struct uart_8250_port *up =
1776 container_of(port, struct uart_8250_port, port);
1777 unsigned char mcr = 0;
1778
1779 if (mctrl & TIOCM_RTS)
1780 mcr |= UART_MCR_RTS;
1781 if (mctrl & TIOCM_DTR)
1782 mcr |= UART_MCR_DTR;
1783 if (mctrl & TIOCM_OUT1)
1784 mcr |= UART_MCR_OUT1;
1785 if (mctrl & TIOCM_OUT2)
1786 mcr |= UART_MCR_OUT2;
1787 if (mctrl & TIOCM_LOOP)
1788 mcr |= UART_MCR_LOOP;
1789
1790 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1791
1792 serial_port_out(port, UART_MCR, mcr);
1793 }
1794
1795 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1796 {
1797 struct uart_8250_port *up =
1798 container_of(port, struct uart_8250_port, port);
1799 unsigned long flags;
1800
1801 spin_lock_irqsave(&port->lock, flags);
1802 if (break_state == -1)
1803 up->lcr |= UART_LCR_SBC;
1804 else
1805 up->lcr &= ~UART_LCR_SBC;
1806 serial_port_out(port, UART_LCR, up->lcr);
1807 spin_unlock_irqrestore(&port->lock, flags);
1808 }
1809
1810 /*
1811 * Wait for transmitter & holding register to empty
1812 */
1813 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1814 {
1815 unsigned int status, tmout = 10000;
1816
1817 /* Wait up to 10ms for the character(s) to be sent. */
1818 for (;;) {
1819 status = serial_in(up, UART_LSR);
1820
1821 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1822
1823 if ((status & bits) == bits)
1824 break;
1825 if (--tmout == 0)
1826 break;
1827 udelay(1);
1828 }
1829
1830 /* Wait up to 1s for flow control if necessary */
1831 if (up->port.flags & UPF_CONS_FLOW) {
1832 unsigned int tmout;
1833 for (tmout = 1000000; tmout; tmout--) {
1834 unsigned int msr = serial_in(up, UART_MSR);
1835 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1836 if (msr & UART_MSR_CTS)
1837 break;
1838 udelay(1);
1839 touch_nmi_watchdog();
1840 }
1841 }
1842 }
1843
1844 #ifdef CONFIG_CONSOLE_POLL
1845 /*
1846 * Console polling routines for writing and reading from the uart while
1847 * in an interrupt or debug context.
1848 */
1849
1850 static int serial8250_get_poll_char(struct uart_port *port)
1851 {
1852 unsigned char lsr = serial_port_in(port, UART_LSR);
1853
1854 if (!(lsr & UART_LSR_DR))
1855 return NO_POLL_CHAR;
1856
1857 return serial_port_in(port, UART_RX);
1858 }
1859
1860
1861 static void serial8250_put_poll_char(struct uart_port *port,
1862 unsigned char c)
1863 {
1864 unsigned int ier;
1865 struct uart_8250_port *up =
1866 container_of(port, struct uart_8250_port, port);
1867
1868 /*
1869 * First save the IER then disable the interrupts
1870 */
1871 ier = serial_port_in(port, UART_IER);
1872 if (up->capabilities & UART_CAP_UUE)
1873 serial_port_out(port, UART_IER, UART_IER_UUE);
1874 else
1875 serial_port_out(port, UART_IER, 0);
1876
1877 wait_for_xmitr(up, BOTH_EMPTY);
1878 /*
1879 * Send the character out.
1880 * If a LF, also do CR...
1881 */
1882 serial_port_out(port, UART_TX, c);
1883 if (c == 10) {
1884 wait_for_xmitr(up, BOTH_EMPTY);
1885 serial_port_out(port, UART_TX, 13);
1886 }
1887
1888 /*
1889 * Finally, wait for transmitter to become empty
1890 * and restore the IER
1891 */
1892 wait_for_xmitr(up, BOTH_EMPTY);
1893 serial_port_out(port, UART_IER, ier);
1894 }
1895
1896 #endif /* CONFIG_CONSOLE_POLL */
1897
1898 static int serial8250_startup(struct uart_port *port)
1899 {
1900 struct uart_8250_port *up =
1901 container_of(port, struct uart_8250_port, port);
1902 unsigned long flags;
1903 unsigned char lsr, iir;
1904 int retval;
1905
1906 if (port->type == PORT_8250_CIR)
1907 return -ENODEV;
1908
1909 port->fifosize = uart_config[up->port.type].fifo_size;
1910 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1911 up->capabilities = uart_config[up->port.type].flags;
1912 up->mcr = 0;
1913
1914 if (port->iotype != up->cur_iotype)
1915 set_io_from_upio(port);
1916
1917 if (port->type == PORT_16C950) {
1918 /* Wake up and initialize UART */
1919 up->acr = 0;
1920 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1921 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1922 serial_port_out(port, UART_IER, 0);
1923 serial_port_out(port, UART_LCR, 0);
1924 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1925 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1926 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1927 serial_port_out(port, UART_LCR, 0);
1928 }
1929
1930 #ifdef CONFIG_SERIAL_8250_RSA
1931 /*
1932 * If this is an RSA port, see if we can kick it up to the
1933 * higher speed clock.
1934 */
1935 enable_rsa(up);
1936 #endif
1937
1938 /*
1939 * Clear the FIFO buffers and disable them.
1940 * (they will be reenabled in set_termios())
1941 */
1942 serial8250_clear_fifos(up);
1943
1944 /*
1945 * Clear the interrupt registers.
1946 */
1947 serial_port_in(port, UART_LSR);
1948 serial_port_in(port, UART_RX);
1949 serial_port_in(port, UART_IIR);
1950 serial_port_in(port, UART_MSR);
1951
1952 /*
1953 * At this point, there's no way the LSR could still be 0xff;
1954 * if it is, then bail out, because there's likely no UART
1955 * here.
1956 */
1957 if (!(port->flags & UPF_BUGGY_UART) &&
1958 (serial_port_in(port, UART_LSR) == 0xff)) {
1959 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
1960 serial_index(port));
1961 return -ENODEV;
1962 }
1963
1964 /*
1965 * For a XR16C850, we need to set the trigger levels
1966 */
1967 if (port->type == PORT_16850) {
1968 unsigned char fctr;
1969
1970 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1971
1972 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1973 serial_port_out(port, UART_FCTR,
1974 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1975 serial_port_out(port, UART_TRG, UART_TRG_96);
1976 serial_port_out(port, UART_FCTR,
1977 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1978 serial_port_out(port, UART_TRG, UART_TRG_96);
1979
1980 serial_port_out(port, UART_LCR, 0);
1981 }
1982
1983 if (port->irq) {
1984 unsigned char iir1;
1985 /*
1986 * Test for UARTs that do not reassert THRE when the
1987 * transmitter is idle and the interrupt has already
1988 * been cleared. Real 16550s should always reassert
1989 * this interrupt whenever the transmitter is idle and
1990 * the interrupt is enabled. Delays are necessary to
1991 * allow register changes to become visible.
1992 */
1993 spin_lock_irqsave(&port->lock, flags);
1994 if (up->port.irqflags & IRQF_SHARED)
1995 disable_irq_nosync(port->irq);
1996
1997 wait_for_xmitr(up, UART_LSR_THRE);
1998 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
1999 udelay(1); /* allow THRE to set */
2000 iir1 = serial_port_in(port, UART_IIR);
2001 serial_port_out(port, UART_IER, 0);
2002 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2003 udelay(1); /* allow a working UART time to re-assert THRE */
2004 iir = serial_port_in(port, UART_IIR);
2005 serial_port_out(port, UART_IER, 0);
2006
2007 if (port->irqflags & IRQF_SHARED)
2008 enable_irq(port->irq);
2009 spin_unlock_irqrestore(&port->lock, flags);
2010
2011 /*
2012 * If the interrupt is not reasserted, or we otherwise
2013 * don't trust the iir, setup a timer to kick the UART
2014 * on a regular basis.
2015 */
2016 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2017 up->port.flags & UPF_BUG_THRE) {
2018 up->bugs |= UART_BUG_THRE;
2019 pr_debug("ttyS%d - using backup timer\n",
2020 serial_index(port));
2021 }
2022 }
2023
2024 /*
2025 * The above check will only give an accurate result the first time
2026 * the port is opened so this value needs to be preserved.
2027 */
2028 if (up->bugs & UART_BUG_THRE) {
2029 up->timer.function = serial8250_backup_timeout;
2030 up->timer.data = (unsigned long)up;
2031 mod_timer(&up->timer, jiffies +
2032 uart_poll_timeout(port) + HZ / 5);
2033 }
2034
2035 /*
2036 * If the "interrupt" for this port doesn't correspond with any
2037 * hardware interrupt, we use a timer-based system. The original
2038 * driver used to do this with IRQ0.
2039 */
2040 if (!port->irq) {
2041 up->timer.data = (unsigned long)up;
2042 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2043 } else {
2044 retval = serial_link_irq_chain(up);
2045 if (retval)
2046 return retval;
2047 }
2048
2049 /*
2050 * Now, initialize the UART
2051 */
2052 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2053
2054 spin_lock_irqsave(&port->lock, flags);
2055 if (up->port.flags & UPF_FOURPORT) {
2056 if (!up->port.irq)
2057 up->port.mctrl |= TIOCM_OUT1;
2058 } else
2059 /*
2060 * Most PC uarts need OUT2 raised to enable interrupts.
2061 */
2062 if (port->irq)
2063 up->port.mctrl |= TIOCM_OUT2;
2064
2065 serial8250_set_mctrl(port, port->mctrl);
2066
2067 /* Serial over Lan (SoL) hack:
2068 Intel 8257x Gigabit ethernet chips have a
2069 16550 emulation, to be used for Serial Over Lan.
2070 Those chips take a longer time than a normal
2071 serial device to signalize that a transmission
2072 data was queued. Due to that, the above test generally
2073 fails. One solution would be to delay the reading of
2074 iir. However, this is not reliable, since the timeout
2075 is variable. So, let's just don't test if we receive
2076 TX irq. This way, we'll never enable UART_BUG_TXEN.
2077 */
2078 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2079 goto dont_test_tx_en;
2080
2081 /*
2082 * Do a quick test to see if we receive an
2083 * interrupt when we enable the TX irq.
2084 */
2085 serial_port_out(port, UART_IER, UART_IER_THRI);
2086 lsr = serial_port_in(port, UART_LSR);
2087 iir = serial_port_in(port, UART_IIR);
2088 serial_port_out(port, UART_IER, 0);
2089
2090 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2091 if (!(up->bugs & UART_BUG_TXEN)) {
2092 up->bugs |= UART_BUG_TXEN;
2093 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2094 serial_index(port));
2095 }
2096 } else {
2097 up->bugs &= ~UART_BUG_TXEN;
2098 }
2099
2100 dont_test_tx_en:
2101 spin_unlock_irqrestore(&port->lock, flags);
2102
2103 /*
2104 * Clear the interrupt registers again for luck, and clear the
2105 * saved flags to avoid getting false values from polling
2106 * routines or the previous session.
2107 */
2108 serial_port_in(port, UART_LSR);
2109 serial_port_in(port, UART_RX);
2110 serial_port_in(port, UART_IIR);
2111 serial_port_in(port, UART_MSR);
2112 up->lsr_saved_flags = 0;
2113 up->msr_saved_flags = 0;
2114
2115 /*
2116 * Finally, enable interrupts. Note: Modem status interrupts
2117 * are set via set_termios(), which will be occurring imminently
2118 * anyway, so we don't enable them here.
2119 */
2120 up->ier = UART_IER_RLSI | UART_IER_RDI;
2121 serial_port_out(port, UART_IER, up->ier);
2122
2123 if (port->flags & UPF_FOURPORT) {
2124 unsigned int icp;
2125 /*
2126 * Enable interrupts on the AST Fourport board
2127 */
2128 icp = (port->iobase & 0xfe0) | 0x01f;
2129 outb_p(0x80, icp);
2130 inb_p(icp);
2131 }
2132
2133 return 0;
2134 }
2135
2136 static void serial8250_shutdown(struct uart_port *port)
2137 {
2138 struct uart_8250_port *up =
2139 container_of(port, struct uart_8250_port, port);
2140 unsigned long flags;
2141
2142 /*
2143 * Disable interrupts from this port
2144 */
2145 up->ier = 0;
2146 serial_port_out(port, UART_IER, 0);
2147
2148 spin_lock_irqsave(&port->lock, flags);
2149 if (port->flags & UPF_FOURPORT) {
2150 /* reset interrupts on the AST Fourport board */
2151 inb((port->iobase & 0xfe0) | 0x1f);
2152 port->mctrl |= TIOCM_OUT1;
2153 } else
2154 port->mctrl &= ~TIOCM_OUT2;
2155
2156 serial8250_set_mctrl(port, port->mctrl);
2157 spin_unlock_irqrestore(&port->lock, flags);
2158
2159 /*
2160 * Disable break condition and FIFOs
2161 */
2162 serial_port_out(port, UART_LCR,
2163 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2164 serial8250_clear_fifos(up);
2165
2166 #ifdef CONFIG_SERIAL_8250_RSA
2167 /*
2168 * Reset the RSA board back to 115kbps compat mode.
2169 */
2170 disable_rsa(up);
2171 #endif
2172
2173 /*
2174 * Read data port to reset things, and then unlink from
2175 * the IRQ chain.
2176 */
2177 serial_port_in(port, UART_RX);
2178
2179 del_timer_sync(&up->timer);
2180 up->timer.function = serial8250_timeout;
2181 if (port->irq)
2182 serial_unlink_irq_chain(up);
2183 }
2184
2185 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2186 {
2187 unsigned int quot;
2188
2189 /*
2190 * Handle magic divisors for baud rates above baud_base on
2191 * SMSC SuperIO chips.
2192 */
2193 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2194 baud == (port->uartclk/4))
2195 quot = 0x8001;
2196 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2197 baud == (port->uartclk/8))
2198 quot = 0x8002;
2199 else
2200 quot = uart_get_divisor(port, baud);
2201
2202 return quot;
2203 }
2204
2205 void
2206 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2207 struct ktermios *old)
2208 {
2209 struct uart_8250_port *up =
2210 container_of(port, struct uart_8250_port, port);
2211 unsigned char cval, fcr = 0;
2212 unsigned long flags;
2213 unsigned int baud, quot;
2214 int fifo_bug = 0;
2215
2216 switch (termios->c_cflag & CSIZE) {
2217 case CS5:
2218 cval = UART_LCR_WLEN5;
2219 break;
2220 case CS6:
2221 cval = UART_LCR_WLEN6;
2222 break;
2223 case CS7:
2224 cval = UART_LCR_WLEN7;
2225 break;
2226 default:
2227 case CS8:
2228 cval = UART_LCR_WLEN8;
2229 break;
2230 }
2231
2232 if (termios->c_cflag & CSTOPB)
2233 cval |= UART_LCR_STOP;
2234 if (termios->c_cflag & PARENB) {
2235 cval |= UART_LCR_PARITY;
2236 if (up->bugs & UART_BUG_PARITY)
2237 fifo_bug = 1;
2238 }
2239 if (!(termios->c_cflag & PARODD))
2240 cval |= UART_LCR_EPAR;
2241 #ifdef CMSPAR
2242 if (termios->c_cflag & CMSPAR)
2243 cval |= UART_LCR_SPAR;
2244 #endif
2245
2246 /*
2247 * Ask the core to calculate the divisor for us.
2248 */
2249 baud = uart_get_baud_rate(port, termios, old,
2250 port->uartclk / 16 / 0xffff,
2251 port->uartclk / 16);
2252 quot = serial8250_get_divisor(port, baud);
2253
2254 /*
2255 * Oxford Semi 952 rev B workaround
2256 */
2257 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2258 quot++;
2259
2260 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2261 fcr = uart_config[port->type].fcr;
2262 if (baud < 2400 || fifo_bug) {
2263 fcr &= ~UART_FCR_TRIGGER_MASK;
2264 fcr |= UART_FCR_TRIGGER_1;
2265 }
2266 }
2267
2268 /*
2269 * MCR-based auto flow control. When AFE is enabled, RTS will be
2270 * deasserted when the receive FIFO contains more characters than
2271 * the trigger, or the MCR RTS bit is cleared. In the case where
2272 * the remote UART is not using CTS auto flow control, we must
2273 * have sufficient FIFO entries for the latency of the remote
2274 * UART to respond. IOW, at least 32 bytes of FIFO.
2275 */
2276 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
2277 up->mcr &= ~UART_MCR_AFE;
2278 if (termios->c_cflag & CRTSCTS)
2279 up->mcr |= UART_MCR_AFE;
2280 }
2281
2282 /*
2283 * Ok, we're now changing the port state. Do it with
2284 * interrupts disabled.
2285 */
2286 spin_lock_irqsave(&port->lock, flags);
2287
2288 /*
2289 * Update the per-port timeout.
2290 */
2291 uart_update_timeout(port, termios->c_cflag, baud);
2292
2293 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2294 if (termios->c_iflag & INPCK)
2295 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2296 if (termios->c_iflag & (BRKINT | PARMRK))
2297 port->read_status_mask |= UART_LSR_BI;
2298
2299 /*
2300 * Characteres to ignore
2301 */
2302 port->ignore_status_mask = 0;
2303 if (termios->c_iflag & IGNPAR)
2304 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2305 if (termios->c_iflag & IGNBRK) {
2306 port->ignore_status_mask |= UART_LSR_BI;
2307 /*
2308 * If we're ignoring parity and break indicators,
2309 * ignore overruns too (for real raw support).
2310 */
2311 if (termios->c_iflag & IGNPAR)
2312 port->ignore_status_mask |= UART_LSR_OE;
2313 }
2314
2315 /*
2316 * ignore all characters if CREAD is not set
2317 */
2318 if ((termios->c_cflag & CREAD) == 0)
2319 port->ignore_status_mask |= UART_LSR_DR;
2320
2321 /*
2322 * CTS flow control flag and modem status interrupts
2323 */
2324 up->ier &= ~UART_IER_MSI;
2325 if (!(up->bugs & UART_BUG_NOMSR) &&
2326 UART_ENABLE_MS(&up->port, termios->c_cflag))
2327 up->ier |= UART_IER_MSI;
2328 if (up->capabilities & UART_CAP_UUE)
2329 up->ier |= UART_IER_UUE;
2330 if (up->capabilities & UART_CAP_RTOIE)
2331 up->ier |= UART_IER_RTOIE;
2332
2333 serial_port_out(port, UART_IER, up->ier);
2334
2335 if (up->capabilities & UART_CAP_EFR) {
2336 unsigned char efr = 0;
2337 /*
2338 * TI16C752/Startech hardware flow control. FIXME:
2339 * - TI16C752 requires control thresholds to be set.
2340 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2341 */
2342 if (termios->c_cflag & CRTSCTS)
2343 efr |= UART_EFR_CTS;
2344
2345 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2346 if (port->flags & UPF_EXAR_EFR)
2347 serial_port_out(port, UART_XR_EFR, efr);
2348 else
2349 serial_port_out(port, UART_EFR, efr);
2350 }
2351
2352 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2353 if (is_omap1510_8250(up)) {
2354 if (baud == 115200) {
2355 quot = 1;
2356 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2357 } else
2358 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2359 }
2360
2361 /*
2362 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2363 * otherwise just set DLAB
2364 */
2365 if (up->capabilities & UART_NATSEMI)
2366 serial_port_out(port, UART_LCR, 0xe0);
2367 else
2368 serial_port_out(port, UART_LCR, cval | UART_LCR_DLAB);
2369
2370 serial_dl_write(up, quot);
2371
2372 /*
2373 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2374 * is written without DLAB set, this mode will be disabled.
2375 */
2376 if (port->type == PORT_16750)
2377 serial_port_out(port, UART_FCR, fcr);
2378
2379 serial_port_out(port, UART_LCR, cval); /* reset DLAB */
2380 up->lcr = cval; /* Save LCR */
2381 if (port->type != PORT_16750) {
2382 /* emulated UARTs (Lucent Venus 167x) need two steps */
2383 if (fcr & UART_FCR_ENABLE_FIFO)
2384 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2385 serial_port_out(port, UART_FCR, fcr); /* set fcr */
2386 }
2387 serial8250_set_mctrl(port, port->mctrl);
2388 spin_unlock_irqrestore(&port->lock, flags);
2389 /* Don't rewrite B0 */
2390 if (tty_termios_baud_rate(termios))
2391 tty_termios_encode_baud_rate(termios, baud, baud);
2392 }
2393 EXPORT_SYMBOL(serial8250_do_set_termios);
2394
2395 static void
2396 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2397 struct ktermios *old)
2398 {
2399 if (port->set_termios)
2400 port->set_termios(port, termios, old);
2401 else
2402 serial8250_do_set_termios(port, termios, old);
2403 }
2404
2405 static void
2406 serial8250_set_ldisc(struct uart_port *port, int new)
2407 {
2408 if (new == N_PPS) {
2409 port->flags |= UPF_HARDPPS_CD;
2410 serial8250_enable_ms(port);
2411 } else
2412 port->flags &= ~UPF_HARDPPS_CD;
2413 }
2414
2415
2416 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2417 unsigned int oldstate)
2418 {
2419 struct uart_8250_port *p =
2420 container_of(port, struct uart_8250_port, port);
2421
2422 serial8250_set_sleep(p, state != 0);
2423 }
2424 EXPORT_SYMBOL(serial8250_do_pm);
2425
2426 static void
2427 serial8250_pm(struct uart_port *port, unsigned int state,
2428 unsigned int oldstate)
2429 {
2430 if (port->pm)
2431 port->pm(port, state, oldstate);
2432 else
2433 serial8250_do_pm(port, state, oldstate);
2434 }
2435
2436 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2437 {
2438 if (pt->port.iotype == UPIO_AU)
2439 return 0x1000;
2440 if (is_omap1_8250(pt))
2441 return 0x16 << pt->port.regshift;
2442
2443 return 8 << pt->port.regshift;
2444 }
2445
2446 /*
2447 * Resource handling.
2448 */
2449 static int serial8250_request_std_resource(struct uart_8250_port *up)
2450 {
2451 unsigned int size = serial8250_port_size(up);
2452 struct uart_port *port = &up->port;
2453 int ret = 0;
2454
2455 switch (port->iotype) {
2456 case UPIO_AU:
2457 case UPIO_TSI:
2458 case UPIO_MEM32:
2459 case UPIO_MEM:
2460 if (!port->mapbase)
2461 break;
2462
2463 if (!request_mem_region(port->mapbase, size, "serial")) {
2464 ret = -EBUSY;
2465 break;
2466 }
2467
2468 if (port->flags & UPF_IOREMAP) {
2469 port->membase = ioremap_nocache(port->mapbase, size);
2470 if (!port->membase) {
2471 release_mem_region(port->mapbase, size);
2472 ret = -ENOMEM;
2473 }
2474 }
2475 break;
2476
2477 case UPIO_HUB6:
2478 case UPIO_PORT:
2479 if (!request_region(port->iobase, size, "serial"))
2480 ret = -EBUSY;
2481 break;
2482 }
2483 return ret;
2484 }
2485
2486 static void serial8250_release_std_resource(struct uart_8250_port *up)
2487 {
2488 unsigned int size = serial8250_port_size(up);
2489 struct uart_port *port = &up->port;
2490
2491 switch (port->iotype) {
2492 case UPIO_AU:
2493 case UPIO_TSI:
2494 case UPIO_MEM32:
2495 case UPIO_MEM:
2496 if (!port->mapbase)
2497 break;
2498
2499 if (port->flags & UPF_IOREMAP) {
2500 iounmap(port->membase);
2501 port->membase = NULL;
2502 }
2503
2504 release_mem_region(port->mapbase, size);
2505 break;
2506
2507 case UPIO_HUB6:
2508 case UPIO_PORT:
2509 release_region(port->iobase, size);
2510 break;
2511 }
2512 }
2513
2514 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2515 {
2516 unsigned long start = UART_RSA_BASE << up->port.regshift;
2517 unsigned int size = 8 << up->port.regshift;
2518 struct uart_port *port = &up->port;
2519 int ret = -EINVAL;
2520
2521 switch (port->iotype) {
2522 case UPIO_HUB6:
2523 case UPIO_PORT:
2524 start += port->iobase;
2525 if (request_region(start, size, "serial-rsa"))
2526 ret = 0;
2527 else
2528 ret = -EBUSY;
2529 break;
2530 }
2531
2532 return ret;
2533 }
2534
2535 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2536 {
2537 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2538 unsigned int size = 8 << up->port.regshift;
2539 struct uart_port *port = &up->port;
2540
2541 switch (port->iotype) {
2542 case UPIO_HUB6:
2543 case UPIO_PORT:
2544 release_region(port->iobase + offset, size);
2545 break;
2546 }
2547 }
2548
2549 static void serial8250_release_port(struct uart_port *port)
2550 {
2551 struct uart_8250_port *up =
2552 container_of(port, struct uart_8250_port, port);
2553
2554 serial8250_release_std_resource(up);
2555 if (port->type == PORT_RSA)
2556 serial8250_release_rsa_resource(up);
2557 }
2558
2559 static int serial8250_request_port(struct uart_port *port)
2560 {
2561 struct uart_8250_port *up =
2562 container_of(port, struct uart_8250_port, port);
2563 int ret;
2564
2565 if (port->type == PORT_8250_CIR)
2566 return -ENODEV;
2567
2568 ret = serial8250_request_std_resource(up);
2569 if (ret == 0 && port->type == PORT_RSA) {
2570 ret = serial8250_request_rsa_resource(up);
2571 if (ret < 0)
2572 serial8250_release_std_resource(up);
2573 }
2574
2575 return ret;
2576 }
2577
2578 static void serial8250_config_port(struct uart_port *port, int flags)
2579 {
2580 struct uart_8250_port *up =
2581 container_of(port, struct uart_8250_port, port);
2582 int probeflags = PROBE_ANY;
2583 int ret;
2584
2585 if (port->type == PORT_8250_CIR)
2586 return;
2587
2588 /*
2589 * Find the region that we can probe for. This in turn
2590 * tells us whether we can probe for the type of port.
2591 */
2592 ret = serial8250_request_std_resource(up);
2593 if (ret < 0)
2594 return;
2595
2596 ret = serial8250_request_rsa_resource(up);
2597 if (ret < 0)
2598 probeflags &= ~PROBE_RSA;
2599
2600 if (port->iotype != up->cur_iotype)
2601 set_io_from_upio(port);
2602
2603 if (flags & UART_CONFIG_TYPE)
2604 autoconfig(up, probeflags);
2605
2606 /* if access method is AU, it is a 16550 with a quirk */
2607 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
2608 up->bugs |= UART_BUG_NOMSR;
2609
2610 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2611 autoconfig_irq(up);
2612
2613 if (port->type != PORT_RSA && probeflags & PROBE_RSA)
2614 serial8250_release_rsa_resource(up);
2615 if (port->type == PORT_UNKNOWN)
2616 serial8250_release_std_resource(up);
2617 }
2618
2619 static int
2620 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2621 {
2622 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2623 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2624 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2625 ser->type == PORT_STARTECH)
2626 return -EINVAL;
2627 return 0;
2628 }
2629
2630 static const char *
2631 serial8250_type(struct uart_port *port)
2632 {
2633 int type = port->type;
2634
2635 if (type >= ARRAY_SIZE(uart_config))
2636 type = 0;
2637 return uart_config[type].name;
2638 }
2639
2640 static struct uart_ops serial8250_pops = {
2641 .tx_empty = serial8250_tx_empty,
2642 .set_mctrl = serial8250_set_mctrl,
2643 .get_mctrl = serial8250_get_mctrl,
2644 .stop_tx = serial8250_stop_tx,
2645 .start_tx = serial8250_start_tx,
2646 .stop_rx = serial8250_stop_rx,
2647 .enable_ms = serial8250_enable_ms,
2648 .break_ctl = serial8250_break_ctl,
2649 .startup = serial8250_startup,
2650 .shutdown = serial8250_shutdown,
2651 .set_termios = serial8250_set_termios,
2652 .set_ldisc = serial8250_set_ldisc,
2653 .pm = serial8250_pm,
2654 .type = serial8250_type,
2655 .release_port = serial8250_release_port,
2656 .request_port = serial8250_request_port,
2657 .config_port = serial8250_config_port,
2658 .verify_port = serial8250_verify_port,
2659 #ifdef CONFIG_CONSOLE_POLL
2660 .poll_get_char = serial8250_get_poll_char,
2661 .poll_put_char = serial8250_put_poll_char,
2662 #endif
2663 };
2664
2665 static struct uart_8250_port serial8250_ports[UART_NR];
2666
2667 static void (*serial8250_isa_config)(int port, struct uart_port *up,
2668 unsigned short *capabilities);
2669
2670 void serial8250_set_isa_configurator(
2671 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2672 {
2673 serial8250_isa_config = v;
2674 }
2675 EXPORT_SYMBOL(serial8250_set_isa_configurator);
2676
2677 static void __init serial8250_isa_init_ports(void)
2678 {
2679 struct uart_8250_port *up;
2680 static int first = 1;
2681 int i, irqflag = 0;
2682
2683 if (!first)
2684 return;
2685 first = 0;
2686
2687 if (nr_uarts > UART_NR)
2688 nr_uarts = UART_NR;
2689
2690 for (i = 0; i < nr_uarts; i++) {
2691 struct uart_8250_port *up = &serial8250_ports[i];
2692 struct uart_port *port = &up->port;
2693
2694 port->line = i;
2695 spin_lock_init(&port->lock);
2696
2697 init_timer(&up->timer);
2698 up->timer.function = serial8250_timeout;
2699 up->cur_iotype = 0xFF;
2700
2701 /*
2702 * ALPHA_KLUDGE_MCR needs to be killed.
2703 */
2704 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2705 up->mcr_force = ALPHA_KLUDGE_MCR;
2706
2707 port->ops = &serial8250_pops;
2708 }
2709
2710 if (share_irqs)
2711 irqflag = IRQF_SHARED;
2712
2713 for (i = 0, up = serial8250_ports;
2714 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2715 i++, up++) {
2716 struct uart_port *port = &up->port;
2717
2718 port->iobase = old_serial_port[i].port;
2719 port->irq = irq_canonicalize(old_serial_port[i].irq);
2720 port->irqflags = old_serial_port[i].irqflags;
2721 port->uartclk = old_serial_port[i].baud_base * 16;
2722 port->flags = old_serial_port[i].flags;
2723 port->hub6 = old_serial_port[i].hub6;
2724 port->membase = old_serial_port[i].iomem_base;
2725 port->iotype = old_serial_port[i].io_type;
2726 port->regshift = old_serial_port[i].iomem_reg_shift;
2727 set_io_from_upio(port);
2728 port->irqflags |= irqflag;
2729 if (serial8250_isa_config != NULL)
2730 serial8250_isa_config(i, &up->port, &up->capabilities);
2731
2732 }
2733 }
2734
2735 static void
2736 serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2737 {
2738 up->port.type = type;
2739 up->port.fifosize = uart_config[type].fifo_size;
2740 up->capabilities = uart_config[type].flags;
2741 up->tx_loadsz = uart_config[type].tx_loadsz;
2742 }
2743
2744 static void __init
2745 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2746 {
2747 int i;
2748
2749 for (i = 0; i < nr_uarts; i++) {
2750 struct uart_8250_port *up = &serial8250_ports[i];
2751
2752 if (up->port.dev)
2753 continue;
2754
2755 up->port.dev = dev;
2756
2757 if (up->port.flags & UPF_FIXED_TYPE)
2758 serial8250_init_fixed_type_port(up, up->port.type);
2759
2760 uart_add_one_port(drv, &up->port);
2761 }
2762 }
2763
2764 #ifdef CONFIG_SERIAL_8250_CONSOLE
2765
2766 static void serial8250_console_putchar(struct uart_port *port, int ch)
2767 {
2768 struct uart_8250_port *up =
2769 container_of(port, struct uart_8250_port, port);
2770
2771 wait_for_xmitr(up, UART_LSR_THRE);
2772 serial_port_out(port, UART_TX, ch);
2773 }
2774
2775 /*
2776 * Print a string to the serial port trying not to disturb
2777 * any possible real use of the port...
2778 *
2779 * The console_lock must be held when we get here.
2780 */
2781 static void
2782 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2783 {
2784 struct uart_8250_port *up = &serial8250_ports[co->index];
2785 struct uart_port *port = &up->port;
2786 unsigned long flags;
2787 unsigned int ier;
2788 int locked = 1;
2789
2790 touch_nmi_watchdog();
2791
2792 local_irq_save(flags);
2793 if (port->sysrq) {
2794 /* serial8250_handle_irq() already took the lock */
2795 locked = 0;
2796 } else if (oops_in_progress) {
2797 locked = spin_trylock(&port->lock);
2798 } else
2799 spin_lock(&port->lock);
2800
2801 /*
2802 * First save the IER then disable the interrupts
2803 */
2804 ier = serial_port_in(port, UART_IER);
2805
2806 if (up->capabilities & UART_CAP_UUE)
2807 serial_port_out(port, UART_IER, UART_IER_UUE);
2808 else
2809 serial_port_out(port, UART_IER, 0);
2810
2811 uart_console_write(port, s, count, serial8250_console_putchar);
2812
2813 /*
2814 * Finally, wait for transmitter to become empty
2815 * and restore the IER
2816 */
2817 wait_for_xmitr(up, BOTH_EMPTY);
2818 serial_port_out(port, UART_IER, ier);
2819
2820 /*
2821 * The receive handling will happen properly because the
2822 * receive ready bit will still be set; it is not cleared
2823 * on read. However, modem control will not, we must
2824 * call it if we have saved something in the saved flags
2825 * while processing with interrupts off.
2826 */
2827 if (up->msr_saved_flags)
2828 serial8250_modem_status(up);
2829
2830 if (locked)
2831 spin_unlock(&port->lock);
2832 local_irq_restore(flags);
2833 }
2834
2835 static int __init serial8250_console_setup(struct console *co, char *options)
2836 {
2837 struct uart_port *port;
2838 int baud = 9600;
2839 int bits = 8;
2840 int parity = 'n';
2841 int flow = 'n';
2842
2843 /*
2844 * Check whether an invalid uart number has been specified, and
2845 * if so, search for the first available port that does have
2846 * console support.
2847 */
2848 if (co->index >= nr_uarts)
2849 co->index = 0;
2850 port = &serial8250_ports[co->index].port;
2851 if (!port->iobase && !port->membase)
2852 return -ENODEV;
2853
2854 if (options)
2855 uart_parse_options(options, &baud, &parity, &bits, &flow);
2856
2857 return uart_set_options(port, co, baud, parity, bits, flow);
2858 }
2859
2860 static int serial8250_console_early_setup(void)
2861 {
2862 return serial8250_find_port_for_earlycon();
2863 }
2864
2865 static struct console serial8250_console = {
2866 .name = "ttyS",
2867 .write = serial8250_console_write,
2868 .device = uart_console_device,
2869 .setup = serial8250_console_setup,
2870 .early_setup = serial8250_console_early_setup,
2871 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2872 .index = -1,
2873 .data = &serial8250_reg,
2874 };
2875
2876 static int __init serial8250_console_init(void)
2877 {
2878 serial8250_isa_init_ports();
2879 register_console(&serial8250_console);
2880 return 0;
2881 }
2882 console_initcall(serial8250_console_init);
2883
2884 int serial8250_find_port(struct uart_port *p)
2885 {
2886 int line;
2887 struct uart_port *port;
2888
2889 for (line = 0; line < nr_uarts; line++) {
2890 port = &serial8250_ports[line].port;
2891 if (uart_match_port(p, port))
2892 return line;
2893 }
2894 return -ENODEV;
2895 }
2896
2897 #define SERIAL8250_CONSOLE &serial8250_console
2898 #else
2899 #define SERIAL8250_CONSOLE NULL
2900 #endif
2901
2902 static struct uart_driver serial8250_reg = {
2903 .owner = THIS_MODULE,
2904 .driver_name = "serial",
2905 .dev_name = "ttyS",
2906 .major = TTY_MAJOR,
2907 .minor = 64,
2908 .cons = SERIAL8250_CONSOLE,
2909 };
2910
2911 /*
2912 * early_serial_setup - early registration for 8250 ports
2913 *
2914 * Setup an 8250 port structure prior to console initialisation. Use
2915 * after console initialisation will cause undefined behaviour.
2916 */
2917 int __init early_serial_setup(struct uart_port *port)
2918 {
2919 struct uart_port *p;
2920
2921 if (port->line >= ARRAY_SIZE(serial8250_ports))
2922 return -ENODEV;
2923
2924 serial8250_isa_init_ports();
2925 p = &serial8250_ports[port->line].port;
2926 p->iobase = port->iobase;
2927 p->membase = port->membase;
2928 p->irq = port->irq;
2929 p->irqflags = port->irqflags;
2930 p->uartclk = port->uartclk;
2931 p->fifosize = port->fifosize;
2932 p->regshift = port->regshift;
2933 p->iotype = port->iotype;
2934 p->flags = port->flags;
2935 p->mapbase = port->mapbase;
2936 p->private_data = port->private_data;
2937 p->type = port->type;
2938 p->line = port->line;
2939
2940 set_io_from_upio(p);
2941 if (port->serial_in)
2942 p->serial_in = port->serial_in;
2943 if (port->serial_out)
2944 p->serial_out = port->serial_out;
2945 if (port->handle_irq)
2946 p->handle_irq = port->handle_irq;
2947 else
2948 p->handle_irq = serial8250_default_handle_irq;
2949
2950 return 0;
2951 }
2952
2953 /**
2954 * serial8250_suspend_port - suspend one serial port
2955 * @line: serial line number
2956 *
2957 * Suspend one serial port.
2958 */
2959 void serial8250_suspend_port(int line)
2960 {
2961 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2962 }
2963
2964 /**
2965 * serial8250_resume_port - resume one serial port
2966 * @line: serial line number
2967 *
2968 * Resume one serial port.
2969 */
2970 void serial8250_resume_port(int line)
2971 {
2972 struct uart_8250_port *up = &serial8250_ports[line];
2973 struct uart_port *port = &up->port;
2974
2975 if (up->capabilities & UART_NATSEMI) {
2976 /* Ensure it's still in high speed mode */
2977 serial_port_out(port, UART_LCR, 0xE0);
2978
2979 ns16550a_goto_highspeed(up);
2980
2981 serial_port_out(port, UART_LCR, 0);
2982 port->uartclk = 921600*16;
2983 }
2984 uart_resume_port(&serial8250_reg, port);
2985 }
2986
2987 /*
2988 * Register a set of serial devices attached to a platform device. The
2989 * list is terminated with a zero flags entry, which means we expect
2990 * all entries to have at least UPF_BOOT_AUTOCONF set.
2991 */
2992 static int serial8250_probe(struct platform_device *dev)
2993 {
2994 struct plat_serial8250_port *p = dev->dev.platform_data;
2995 struct uart_8250_port uart;
2996 int ret, i, irqflag = 0;
2997
2998 memset(&uart, 0, sizeof(uart));
2999
3000 if (share_irqs)
3001 irqflag = IRQF_SHARED;
3002
3003 for (i = 0; p && p->flags != 0; p++, i++) {
3004 uart.port.iobase = p->iobase;
3005 uart.port.membase = p->membase;
3006 uart.port.irq = p->irq;
3007 uart.port.irqflags = p->irqflags;
3008 uart.port.uartclk = p->uartclk;
3009 uart.port.regshift = p->regshift;
3010 uart.port.iotype = p->iotype;
3011 uart.port.flags = p->flags;
3012 uart.port.mapbase = p->mapbase;
3013 uart.port.hub6 = p->hub6;
3014 uart.port.private_data = p->private_data;
3015 uart.port.type = p->type;
3016 uart.port.serial_in = p->serial_in;
3017 uart.port.serial_out = p->serial_out;
3018 uart.port.handle_irq = p->handle_irq;
3019 uart.port.handle_break = p->handle_break;
3020 uart.port.set_termios = p->set_termios;
3021 uart.port.pm = p->pm;
3022 uart.port.dev = &dev->dev;
3023 uart.port.irqflags |= irqflag;
3024 ret = serial8250_register_8250_port(&uart);
3025 if (ret < 0) {
3026 dev_err(&dev->dev, "unable to register port at index %d "
3027 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3028 p->iobase, (unsigned long long)p->mapbase,
3029 p->irq, ret);
3030 }
3031 }
3032 return 0;
3033 }
3034
3035 /*
3036 * Remove serial ports registered against a platform device.
3037 */
3038 static int serial8250_remove(struct platform_device *dev)
3039 {
3040 int i;
3041
3042 for (i = 0; i < nr_uarts; i++) {
3043 struct uart_8250_port *up = &serial8250_ports[i];
3044
3045 if (up->port.dev == &dev->dev)
3046 serial8250_unregister_port(i);
3047 }
3048 return 0;
3049 }
3050
3051 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3052 {
3053 int i;
3054
3055 for (i = 0; i < UART_NR; i++) {
3056 struct uart_8250_port *up = &serial8250_ports[i];
3057
3058 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3059 uart_suspend_port(&serial8250_reg, &up->port);
3060 }
3061
3062 return 0;
3063 }
3064
3065 static int serial8250_resume(struct platform_device *dev)
3066 {
3067 int i;
3068
3069 for (i = 0; i < UART_NR; i++) {
3070 struct uart_8250_port *up = &serial8250_ports[i];
3071
3072 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3073 serial8250_resume_port(i);
3074 }
3075
3076 return 0;
3077 }
3078
3079 static struct platform_driver serial8250_isa_driver = {
3080 .probe = serial8250_probe,
3081 .remove = serial8250_remove,
3082 .suspend = serial8250_suspend,
3083 .resume = serial8250_resume,
3084 .driver = {
3085 .name = "serial8250",
3086 .owner = THIS_MODULE,
3087 },
3088 };
3089
3090 /*
3091 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3092 * in the table in include/asm/serial.h
3093 */
3094 static struct platform_device *serial8250_isa_devs;
3095
3096 /*
3097 * serial8250_register_8250_port and serial8250_unregister_port allows for
3098 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3099 * modems and PCI multiport cards.
3100 */
3101 static DEFINE_MUTEX(serial_mutex);
3102
3103 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3104 {
3105 int i;
3106
3107 /*
3108 * First, find a port entry which matches.
3109 */
3110 for (i = 0; i < nr_uarts; i++)
3111 if (uart_match_port(&serial8250_ports[i].port, port))
3112 return &serial8250_ports[i];
3113
3114 /*
3115 * We didn't find a matching entry, so look for the first
3116 * free entry. We look for one which hasn't been previously
3117 * used (indicated by zero iobase).
3118 */
3119 for (i = 0; i < nr_uarts; i++)
3120 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3121 serial8250_ports[i].port.iobase == 0)
3122 return &serial8250_ports[i];
3123
3124 /*
3125 * That also failed. Last resort is to find any entry which
3126 * doesn't have a real port associated with it.
3127 */
3128 for (i = 0; i < nr_uarts; i++)
3129 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3130 return &serial8250_ports[i];
3131
3132 return NULL;
3133 }
3134
3135 /**
3136 * serial8250_register_8250_port - register a serial port
3137 * @up: serial port template
3138 *
3139 * Configure the serial port specified by the request. If the
3140 * port exists and is in use, it is hung up and unregistered
3141 * first.
3142 *
3143 * The port is then probed and if necessary the IRQ is autodetected
3144 * If this fails an error is returned.
3145 *
3146 * On success the port is ready to use and the line number is returned.
3147 */
3148 int serial8250_register_8250_port(struct uart_8250_port *up)
3149 {
3150 struct uart_8250_port *uart;
3151 int ret = -ENOSPC;
3152
3153 if (up->port.uartclk == 0)
3154 return -EINVAL;
3155
3156 mutex_lock(&serial_mutex);
3157
3158 uart = serial8250_find_match_or_unused(&up->port);
3159 if (uart && uart->port.type != PORT_8250_CIR) {
3160 if (uart->port.dev)
3161 uart_remove_one_port(&serial8250_reg, &uart->port);
3162
3163 uart->port.iobase = up->port.iobase;
3164 uart->port.membase = up->port.membase;
3165 uart->port.irq = up->port.irq;
3166 uart->port.irqflags = up->port.irqflags;
3167 uart->port.uartclk = up->port.uartclk;
3168 uart->port.fifosize = up->port.fifosize;
3169 uart->port.regshift = up->port.regshift;
3170 uart->port.iotype = up->port.iotype;
3171 uart->port.flags = up->port.flags | UPF_BOOT_AUTOCONF;
3172 uart->bugs = up->bugs;
3173 uart->port.mapbase = up->port.mapbase;
3174 uart->port.private_data = up->port.private_data;
3175 if (up->port.dev)
3176 uart->port.dev = up->port.dev;
3177
3178 if (up->port.flags & UPF_FIXED_TYPE)
3179 serial8250_init_fixed_type_port(uart, up->port.type);
3180
3181 set_io_from_upio(&uart->port);
3182 /* Possibly override default I/O functions. */
3183 if (up->port.serial_in)
3184 uart->port.serial_in = up->port.serial_in;
3185 if (up->port.serial_out)
3186 uart->port.serial_out = up->port.serial_out;
3187 if (up->port.handle_irq)
3188 uart->port.handle_irq = up->port.handle_irq;
3189 /* Possibly override set_termios call */
3190 if (up->port.set_termios)
3191 uart->port.set_termios = up->port.set_termios;
3192 if (up->port.pm)
3193 uart->port.pm = up->port.pm;
3194 if (up->port.handle_break)
3195 uart->port.handle_break = up->port.handle_break;
3196 if (up->dl_read)
3197 uart->dl_read = up->dl_read;
3198 if (up->dl_write)
3199 uart->dl_write = up->dl_write;
3200
3201 if (serial8250_isa_config != NULL)
3202 serial8250_isa_config(0, &uart->port,
3203 &uart->capabilities);
3204
3205 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3206 if (ret == 0)
3207 ret = uart->port.line;
3208 }
3209 mutex_unlock(&serial_mutex);
3210
3211 return ret;
3212 }
3213 EXPORT_SYMBOL(serial8250_register_8250_port);
3214
3215 /**
3216 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3217 * @line: serial line number
3218 *
3219 * Remove one serial port. This may not be called from interrupt
3220 * context. We hand the port back to the our control.
3221 */
3222 void serial8250_unregister_port(int line)
3223 {
3224 struct uart_8250_port *uart = &serial8250_ports[line];
3225
3226 mutex_lock(&serial_mutex);
3227 uart_remove_one_port(&serial8250_reg, &uart->port);
3228 if (serial8250_isa_devs) {
3229 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3230 uart->port.type = PORT_UNKNOWN;
3231 uart->port.dev = &serial8250_isa_devs->dev;
3232 uart->capabilities = uart_config[uart->port.type].flags;
3233 uart_add_one_port(&serial8250_reg, &uart->port);
3234 } else {
3235 uart->port.dev = NULL;
3236 }
3237 mutex_unlock(&serial_mutex);
3238 }
3239 EXPORT_SYMBOL(serial8250_unregister_port);
3240
3241 static int __init serial8250_init(void)
3242 {
3243 int ret;
3244
3245 serial8250_isa_init_ports();
3246
3247 printk(KERN_INFO "Serial: 8250/16550 driver, "
3248 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3249 share_irqs ? "en" : "dis");
3250
3251 #ifdef CONFIG_SPARC
3252 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3253 #else
3254 serial8250_reg.nr = UART_NR;
3255 ret = uart_register_driver(&serial8250_reg);
3256 #endif
3257 if (ret)
3258 goto out;
3259
3260 ret = serial8250_pnp_init();
3261 if (ret)
3262 goto unreg_uart_drv;
3263
3264 serial8250_isa_devs = platform_device_alloc("serial8250",
3265 PLAT8250_DEV_LEGACY);
3266 if (!serial8250_isa_devs) {
3267 ret = -ENOMEM;
3268 goto unreg_pnp;
3269 }
3270
3271 ret = platform_device_add(serial8250_isa_devs);
3272 if (ret)
3273 goto put_dev;
3274
3275 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3276
3277 ret = platform_driver_register(&serial8250_isa_driver);
3278 if (ret == 0)
3279 goto out;
3280
3281 platform_device_del(serial8250_isa_devs);
3282 put_dev:
3283 platform_device_put(serial8250_isa_devs);
3284 unreg_pnp:
3285 serial8250_pnp_exit();
3286 unreg_uart_drv:
3287 #ifdef CONFIG_SPARC
3288 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3289 #else
3290 uart_unregister_driver(&serial8250_reg);
3291 #endif
3292 out:
3293 return ret;
3294 }
3295
3296 static void __exit serial8250_exit(void)
3297 {
3298 struct platform_device *isa_dev = serial8250_isa_devs;
3299
3300 /*
3301 * This tells serial8250_unregister_port() not to re-register
3302 * the ports (thereby making serial8250_isa_driver permanently
3303 * in use.)
3304 */
3305 serial8250_isa_devs = NULL;
3306
3307 platform_driver_unregister(&serial8250_isa_driver);
3308 platform_device_unregister(isa_dev);
3309
3310 serial8250_pnp_exit();
3311
3312 #ifdef CONFIG_SPARC
3313 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3314 #else
3315 uart_unregister_driver(&serial8250_reg);
3316 #endif
3317 }
3318
3319 module_init(serial8250_init);
3320 module_exit(serial8250_exit);
3321
3322 EXPORT_SYMBOL(serial8250_suspend_port);
3323 EXPORT_SYMBOL(serial8250_resume_port);
3324
3325 MODULE_LICENSE("GPL");
3326 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3327
3328 module_param(share_irqs, uint, 0644);
3329 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3330 " (unsafe)");
3331
3332 module_param(nr_uarts, uint, 0644);
3333 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3334
3335 module_param(skip_txen_test, uint, 0644);
3336 MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3337
3338 #ifdef CONFIG_SERIAL_8250_RSA
3339 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3340 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3341 #endif
3342 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
Linux kernel - Deliverables
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