drivers/tty/serial/8250/8250_dw.c

   1 /*
   2  * Synopsys DesignWare 8250 driver.
   3  *
   4  * Copyright 2011 Picochip, Jamie Iles.
   5  * Copyright 2013 Intel Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
  13  * LCR is written whilst busy.  If it is, then a busy detect interrupt is
  14  * raised, the LCR needs to be rewritten and the uart status register read.
  15  */
  16 #include <linux/device.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/serial_8250.h>
  20 #include <linux/serial_core.h>
  21 #include <linux/serial_reg.h>
  22 #include <linux/of.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/of_platform.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include <linux/acpi.h>
  28 #include <linux/clk.h>
  29 #include <linux/reset.h>
  30 #include <linux/pm_runtime.h>
  31
  32 #include <asm/byteorder.h>
  33
  34 #include "8250.h"
  35
  36 /* Offsets for the DesignWare specific registers */
  37 #define DW_UART_USR     0x1f /* UART Status Register */
  38 #define DW_UART_CPR     0xf4 /* Component Parameter Register */
  39 #define DW_UART_UCV     0xf8 /* UART Component Version */
  40
  41 /* Component Parameter Register bits */
  42 #define DW_UART_CPR_ABP_DATA_WIDTH      (3 << 0)
  43 #define DW_UART_CPR_AFCE_MODE           (1 << 4)
  44 #define DW_UART_CPR_THRE_MODE           (1 << 5)
  45 #define DW_UART_CPR_SIR_MODE            (1 << 6)
  46 #define DW_UART_CPR_SIR_LP_MODE         (1 << 7)
  47 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
  48 #define DW_UART_CPR_FIFO_ACCESS         (1 << 9)
  49 #define DW_UART_CPR_FIFO_STAT           (1 << 10)
  50 #define DW_UART_CPR_SHADOW              (1 << 11)
  51 #define DW_UART_CPR_ENCODED_PARMS       (1 << 12)
  52 #define DW_UART_CPR_DMA_EXTRA           (1 << 13)
  53 #define DW_UART_CPR_FIFO_MODE           (0xff << 16)
  54 /* Helper for fifo size calculation */
  55 #define DW_UART_CPR_FIFO_SIZE(a)        (((a >> 16) & 0xff) * 16)
  56
  57
  58 struct dw8250_data {
  59         u8                      usr_reg;
  60         int                     last_mcr;
  61         int                     line;
  62         int                     msr_mask_on;
  63         int                     msr_mask_off;
  64         struct clk              *clk;
  65         struct clk              *pclk;
  66         struct reset_control    *rst;
  67         struct uart_8250_dma    dma;
  68 };
  69
  70 #define BYT_PRV_CLK                     0x800
  71 #define BYT_PRV_CLK_EN                  (1 << 0)
  72 #define BYT_PRV_CLK_M_VAL_SHIFT         1
  73 #define BYT_PRV_CLK_N_VAL_SHIFT         16
  74 #define BYT_PRV_CLK_UPDATE              (1 << 31)
  75
  76 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
  77 {
  78         struct dw8250_data *d = p->private_data;
  79
  80         /* If reading MSR, report CTS asserted when auto-CTS/RTS enabled */
  81         if (offset == UART_MSR && d->last_mcr & UART_MCR_AFE) {
  82                 value |= UART_MSR_CTS;
  83                 value &= ~UART_MSR_DCTS;
  84         }
  85
  86         /* Override any modem control signals if needed */
  87         if (offset == UART_MSR) {
  88                 value |= d->msr_mask_on;
  89                 value &= ~d->msr_mask_off;
  90         }
  91
  92         return value;
  93 }
  94
  95 static void dw8250_force_idle(struct uart_port *p)
  96 {
  97         struct uart_8250_port *up = up_to_u8250p(p);
  98
  99         serial8250_clear_and_reinit_fifos(up);
 100         (void)p->serial_in(p, UART_RX);
 101 }
 102
 103 static void dw8250_serial_out(struct uart_port *p, int offset, int value)
 104 {
 105         struct dw8250_data *d = p->private_data;
 106
 107         if (offset == UART_MCR)
 108                 d->last_mcr = value;
 109
 110         writeb(value, p->membase + (offset << p->regshift));
 111
 112         /* Make sure LCR write wasn't ignored */
 113         if (offset == UART_LCR) {
 114                 int tries = 1000;
 115                 while (tries--) {
 116                         unsigned int lcr = p->serial_in(p, UART_LCR);
 117                         if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
 118                                 return;
 119                         dw8250_force_idle(p);
 120                         writeb(value, p->membase + (UART_LCR << p->regshift));
 121                 }
 122                 dev_err(p->dev, "Couldn't set LCR to %d\n", value);
 123         }
 124 }
 125
 126 static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
 127 {
 128         unsigned int value = readb(p->membase + (offset << p->regshift));
 129
 130         return dw8250_modify_msr(p, offset, value);
 131 }
 132
 133 #ifdef CONFIG_64BIT
 134 static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
 135 {
 136         unsigned int value;
 137
 138         value = (u8)__raw_readq(p->membase + (offset << p->regshift));
 139
 140         return dw8250_modify_msr(p, offset, value);
 141 }
 142
 143 static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
 144 {
 145         struct dw8250_data *d = p->private_data;
 146
 147         if (offset == UART_MCR)
 148                 d->last_mcr = value;
 149
 150         value &= 0xff;
 151         __raw_writeq(value, p->membase + (offset << p->regshift));
 152         /* Read back to ensure register write ordering. */
 153         __raw_readq(p->membase + (UART_LCR << p->regshift));
 154
 155         /* Make sure LCR write wasn't ignored */
 156         if (offset == UART_LCR) {
 157                 int tries = 1000;
 158                 while (tries--) {
 159                         unsigned int lcr = p->serial_in(p, UART_LCR);
 160                         if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
 161                                 return;
 162                         dw8250_force_idle(p);
 163                         __raw_writeq(value & 0xff,
 164                                      p->membase + (UART_LCR << p->regshift));
 165                 }
 166                 dev_err(p->dev, "Couldn't set LCR to %d\n", value);
 167         }
 168 }
 169 #endif /* CONFIG_64BIT */
 170
 171 static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
 172 {
 173         struct dw8250_data *d = p->private_data;
 174
 175         if (offset == UART_MCR)
 176                 d->last_mcr = value;
 177
 178         writel(value, p->membase + (offset << p->regshift));
 179
 180         /* Make sure LCR write wasn't ignored */
 181         if (offset == UART_LCR) {
 182                 int tries = 1000;
 183                 while (tries--) {
 184                         unsigned int lcr = p->serial_in(p, UART_LCR);
 185                         if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
 186                                 return;
 187                         dw8250_force_idle(p);
 188                         writel(value, p->membase + (UART_LCR << p->regshift));
 189                 }
 190                 dev_err(p->dev, "Couldn't set LCR to %d\n", value);
 191         }
 192 }
 193
 194 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
 195 {
 196         unsigned int value = readl(p->membase + (offset << p->regshift));
 197
 198         return dw8250_modify_msr(p, offset, value);
 199 }
 200
 201 static int dw8250_handle_irq(struct uart_port *p)
 202 {
 203         struct dw8250_data *d = p->private_data;
 204         unsigned int iir = p->serial_in(p, UART_IIR);
 205
 206         if (serial8250_handle_irq(p, iir)) {
 207                 return 1;
 208         } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
 209                 /* Clear the USR */
 210                 (void)p->serial_in(p, d->usr_reg);
 211
 212                 return 1;
 213         }
 214
 215         return 0;
 216 }
 217
 218 static void
 219 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
 220 {
 221         if (!state)
 222                 pm_runtime_get_sync(port->dev);
 223
 224         serial8250_do_pm(port, state, old);
 225
 226         if (state)
 227                 pm_runtime_put_sync_suspend(port->dev);
 228 }
 229
 230 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
 231                                struct ktermios *old)
 232 {
 233         unsigned int baud = tty_termios_baud_rate(termios);
 234         struct dw8250_data *d = p->private_data;
 235         unsigned int rate;
 236         int ret;
 237
 238         if (IS_ERR(d->clk) || !old)
 239                 goto out;
 240
 241         /* Not requesting clock rates below 1.8432Mhz */
 242         if (baud < 115200)
 243                 baud = 115200;
 244
 245         clk_disable_unprepare(d->clk);
 246         rate = clk_round_rate(d->clk, baud * 16);
 247         ret = clk_set_rate(d->clk, rate);
 248         clk_prepare_enable(d->clk);
 249
 250         if (!ret)
 251                 p->uartclk = rate;
 252 out:
 253         serial8250_do_set_termios(p, termios, old);
 254 }
 255
 256 static bool dw8250_dma_filter(struct dma_chan *chan, void *param)
 257 {
 258         return false;
 259 }
 260
 261 static void dw8250_setup_port(struct uart_8250_port *up)
 262 {
 263         struct uart_port        *p = &up->port;
 264         u32                     reg = readl(p->membase + DW_UART_UCV);
 265
 266         /*
 267          * If the Component Version Register returns zero, we know that
 268          * ADDITIONAL_FEATURES are not enabled. No need to go any further.
 269          */
 270         if (!reg)
 271                 return;
 272
 273         dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n",
 274                 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
 275
 276         reg = readl(p->membase + DW_UART_CPR);
 277         if (!reg)
 278                 return;
 279
 280         /* Select the type based on fifo */
 281         if (reg & DW_UART_CPR_FIFO_MODE) {
 282                 p->type = PORT_16550A;
 283                 p->flags |= UPF_FIXED_TYPE;
 284                 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
 285                 up->tx_loadsz = p->fifosize;
 286                 up->capabilities = UART_CAP_FIFO;
 287         }
 288
 289         if (reg & DW_UART_CPR_AFCE_MODE)
 290                 up->capabilities |= UART_CAP_AFE;
 291 }
 292
 293 static int dw8250_probe_of(struct uart_port *p,
 294                            struct dw8250_data *data)
 295 {
 296         struct device_node      *np = p->dev->of_node;
 297         struct uart_8250_port *up = up_to_u8250p(p);
 298         u32                     val;
 299         bool has_ucv = true;
 300         int id;
 301
 302 #ifdef CONFIG_64BIT
 303         if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
 304                 p->serial_in = dw8250_serial_inq;
 305                 p->serial_out = dw8250_serial_outq;
 306                 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
 307                 p->type = PORT_OCTEON;
 308                 data->usr_reg = 0x27;
 309                 has_ucv = false;
 310         } else
 311 #endif
 312         if (!of_property_read_u32(np, "reg-io-width", &val)) {
 313                 switch (val) {
 314                 case 1:
 315                         break;
 316                 case 4:
 317                         p->iotype = UPIO_MEM32;
 318                         p->serial_in = dw8250_serial_in32;
 319                         p->serial_out = dw8250_serial_out32;
 320                         break;
 321                 default:
 322                         dev_err(p->dev, "unsupported reg-io-width (%u)\n", val);
 323                         return -EINVAL;
 324                 }
 325         }
 326         if (has_ucv)
 327                 dw8250_setup_port(up);
 328
 329         /* if we have a valid fifosize, try hooking up DMA here */
 330         if (p->fifosize) {
 331                 up->dma = &data->dma;
 332
 333                 up->dma->rxconf.src_maxburst = p->fifosize / 4;
 334                 up->dma->txconf.dst_maxburst = p->fifosize / 4;
 335         }
 336
 337         if (!of_property_read_u32(np, "reg-shift", &val))
 338                 p->regshift = val;
 339
 340         /* get index of serial line, if found in DT aliases */
 341         id = of_alias_get_id(np, "serial");
 342         if (id >= 0)
 343                 p->line = id;
 344
 345         if (of_property_read_bool(np, "dcd-override")) {
 346                 /* Always report DCD as active */
 347                 data->msr_mask_on |= UART_MSR_DCD;
 348                 data->msr_mask_off |= UART_MSR_DDCD;
 349         }
 350
 351         if (of_property_read_bool(np, "dsr-override")) {
 352                 /* Always report DSR as active */
 353                 data->msr_mask_on |= UART_MSR_DSR;
 354                 data->msr_mask_off |= UART_MSR_DDSR;
 355         }
 356
 357         if (of_property_read_bool(np, "cts-override")) {
 358                 /* Always report DSR as active */
 359                 data->msr_mask_on |= UART_MSR_DSR;
 360                 data->msr_mask_off |= UART_MSR_DDSR;
 361         }
 362
 363         if (of_property_read_bool(np, "ri-override")) {
 364                 /* Always report Ring indicator as inactive */
 365                 data->msr_mask_off |= UART_MSR_RI;
 366                 data->msr_mask_off |= UART_MSR_TERI;
 367         }
 368
 369         /* clock got configured through clk api, all done */
 370         if (p->uartclk)
 371                 return 0;
 372
 373         /* try to find out clock frequency from DT as fallback */
 374         if (of_property_read_u32(np, "clock-frequency", &val)) {
 375                 dev_err(p->dev, "clk or clock-frequency not defined\n");
 376                 return -EINVAL;
 377         }
 378         p->uartclk = val;
 379
 380         return 0;
 381 }
 382
 383 static int dw8250_probe_acpi(struct uart_8250_port *up,
 384                              struct dw8250_data *data)
 385 {
 386         const struct acpi_device_id *id;
 387         struct uart_port *p = &up->port;
 388
 389         dw8250_setup_port(up);
 390
 391         id = acpi_match_device(p->dev->driver->acpi_match_table, p->dev);
 392         if (!id)
 393                 return -ENODEV;
 394
 395         if (!p->uartclk)
 396                 if (device_property_read_u32(p->dev, "clock-frequency",
 397                                              &p->uartclk))
 398                         return -EINVAL;
 399
 400         p->iotype = UPIO_MEM32;
 401         p->serial_in = dw8250_serial_in32;
 402         p->serial_out = dw8250_serial_out32;
 403         p->regshift = 2;
 404
 405         up->dma = &data->dma;
 406
 407         up->dma->rxconf.src_maxburst = p->fifosize / 4;
 408         up->dma->txconf.dst_maxburst = p->fifosize / 4;
 409
 410         up->port.set_termios = dw8250_set_termios;
 411
 412         return 0;
 413 }
 414
 415 static int dw8250_probe(struct platform_device *pdev)
 416 {
 417         struct uart_8250_port uart = {};
 418         struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 419         struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 420         struct dw8250_data *data;
 421         int err;
 422
 423         if (!regs || !irq) {
 424                 dev_err(&pdev->dev, "no registers/irq defined\n");
 425                 return -EINVAL;
 426         }
 427
 428         spin_lock_init(&uart.port.lock);
 429         uart.port.mapbase = regs->start;
 430         uart.port.irq = irq->start;
 431         uart.port.handle_irq = dw8250_handle_irq;
 432         uart.port.pm = dw8250_do_pm;
 433         uart.port.type = PORT_8250;
 434         uart.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
 435         uart.port.dev = &pdev->dev;
 436
 437         uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
 438                                          resource_size(regs));
 439         if (!uart.port.membase)
 440                 return -ENOMEM;
 441
 442         data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
 443         if (!data)
 444                 return -ENOMEM;
 445
 446         data->usr_reg = DW_UART_USR;
 447         data->clk = devm_clk_get(&pdev->dev, "baudclk");
 448         if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER)
 449                 data->clk = devm_clk_get(&pdev->dev, NULL);
 450         if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER)
 451                 return -EPROBE_DEFER;
 452         if (!IS_ERR(data->clk)) {
 453                 err = clk_prepare_enable(data->clk);
 454                 if (err)
 455                         dev_warn(&pdev->dev, "could not enable optional baudclk: %d\n",
 456                                  err);
 457                 else
 458                         uart.port.uartclk = clk_get_rate(data->clk);
 459         }
 460
 461         data->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
 462         if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) {
 463                 err = -EPROBE_DEFER;
 464                 goto err_clk;
 465         }
 466         if (!IS_ERR(data->pclk)) {
 467                 err = clk_prepare_enable(data->pclk);
 468                 if (err) {
 469                         dev_err(&pdev->dev, "could not enable apb_pclk\n");
 470                         goto err_clk;
 471                 }
 472         }
 473
 474         data->rst = devm_reset_control_get_optional(&pdev->dev, NULL);
 475         if (IS_ERR(data->rst) && PTR_ERR(data->rst) == -EPROBE_DEFER) {
 476                 err = -EPROBE_DEFER;
 477                 goto err_pclk;
 478         }
 479         if (!IS_ERR(data->rst))
 480                 reset_control_deassert(data->rst);
 481
 482         data->dma.rx_param = data;
 483         data->dma.tx_param = data;
 484         data->dma.fn = dw8250_dma_filter;
 485
 486         uart.port.iotype = UPIO_MEM;
 487         uart.port.serial_in = dw8250_serial_in;
 488         uart.port.serial_out = dw8250_serial_out;
 489         uart.port.private_data = data;
 490
 491         if (pdev->dev.of_node) {
 492                 err = dw8250_probe_of(&uart.port, data);
 493                 if (err)
 494                         goto err_reset;
 495         } else if (ACPI_HANDLE(&pdev->dev)) {
 496                 err = dw8250_probe_acpi(&uart, data);
 497                 if (err)
 498                         goto err_reset;
 499         } else {
 500                 err = -ENODEV;
 501                 goto err_reset;
 502         }
 503
 504         data->line = serial8250_register_8250_port(&uart);
 505         if (data->line < 0) {
 506                 err = data->line;
 507                 goto err_reset;
 508         }
 509
 510         platform_set_drvdata(pdev, data);
 511
 512         pm_runtime_set_active(&pdev->dev);
 513         pm_runtime_enable(&pdev->dev);
 514
 515         return 0;
 516
 517 err_reset:
 518         if (!IS_ERR(data->rst))
 519                 reset_control_assert(data->rst);
 520
 521 err_pclk:
 522         if (!IS_ERR(data->pclk))
 523                 clk_disable_unprepare(data->pclk);
 524
 525 err_clk:
 526         if (!IS_ERR(data->clk))
 527                 clk_disable_unprepare(data->clk);
 528
 529         return err;
 530 }
 531
 532 static int dw8250_remove(struct platform_device *pdev)
 533 {
 534         struct dw8250_data *data = platform_get_drvdata(pdev);
 535
 536         pm_runtime_get_sync(&pdev->dev);
 537
 538         serial8250_unregister_port(data->line);
 539
 540         if (!IS_ERR(data->rst))
 541                 reset_control_assert(data->rst);
 542
 543         if (!IS_ERR(data->pclk))
 544                 clk_disable_unprepare(data->pclk);
 545
 546         if (!IS_ERR(data->clk))
 547                 clk_disable_unprepare(data->clk);
 548
 549         pm_runtime_disable(&pdev->dev);
 550         pm_runtime_put_noidle(&pdev->dev);
 551
 552         return 0;
 553 }
 554
 555 #ifdef CONFIG_PM_SLEEP
 556 static int dw8250_suspend(struct device *dev)
 557 {
 558         struct dw8250_data *data = dev_get_drvdata(dev);
 559
 560         serial8250_suspend_port(data->line);
 561
 562         return 0;
 563 }
 564
 565 static int dw8250_resume(struct device *dev)
 566 {
 567         struct dw8250_data *data = dev_get_drvdata(dev);
 568
 569         serial8250_resume_port(data->line);
 570
 571         return 0;
 572 }
 573 #endif /* CONFIG_PM_SLEEP */
 574
 575 #ifdef CONFIG_PM
 576 static int dw8250_runtime_suspend(struct device *dev)
 577 {
 578         struct dw8250_data *data = dev_get_drvdata(dev);
 579
 580         if (!IS_ERR(data->clk))
 581                 clk_disable_unprepare(data->clk);
 582
 583         if (!IS_ERR(data->pclk))
 584                 clk_disable_unprepare(data->pclk);
 585
 586         return 0;
 587 }
 588
 589 static int dw8250_runtime_resume(struct device *dev)
 590 {
 591         struct dw8250_data *data = dev_get_drvdata(dev);
 592
 593         if (!IS_ERR(data->pclk))
 594                 clk_prepare_enable(data->pclk);
 595
 596         if (!IS_ERR(data->clk))
 597                 clk_prepare_enable(data->clk);
 598
 599         return 0;
 600 }
 601 #endif
 602
 603 static const struct dev_pm_ops dw8250_pm_ops = {
 604         SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
 605         SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
 606 };
 607
 608 static const struct of_device_id dw8250_of_match[] = {
 609         { .compatible = "snps,dw-apb-uart" },
 610         { .compatible = "cavium,octeon-3860-uart" },
 611         { /* Sentinel */ }
 612 };
 613 MODULE_DEVICE_TABLE(of, dw8250_of_match);
 614
 615 static const struct acpi_device_id dw8250_acpi_match[] = {
 616         { "INT33C4", 0 },
 617         { "INT33C5", 0 },
 618         { "INT3434", 0 },
 619         { "INT3435", 0 },
 620         { "80860F0A", 0 },
 621         { "8086228A", 0 },
 622         { "APMC0D08", 0},
 623         { },
 624 };
 625 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
 626
 627 static struct platform_driver dw8250_platform_driver = {
 628         .driver = {
 629                 .name           = "dw-apb-uart",
 630                 .pm             = &dw8250_pm_ops,
 631                 .of_match_table = dw8250_of_match,
 632                 .acpi_match_table = ACPI_PTR(dw8250_acpi_match),
 633         },
 634         .probe                  = dw8250_probe,
 635         .remove                 = dw8250_remove,
 636 };
 637
 638 module_platform_driver(dw8250_platform_driver);
 639
 640 MODULE_AUTHOR("Jamie Iles");
 641 MODULE_LICENSE("GPL");
 642 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");