drivers/tty/serial/8250/8250_dw.c

   1 /*
   2  * Synopsys DesignWare 8250 driver.
   3  *
   4  * Copyright 2011 Picochip, Jamie Iles.
   5  * Copyright 2013 Intel Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
  13  * LCR is written whilst busy.  If it is, then a busy detect interrupt is
  14  * raised, the LCR needs to be rewritten and the uart status register read.
  15  */
  16 #include <linux/device.h>
  17 #include <linux/io.h>
  18 #include <linux/module.h>
  19 #include <linux/serial_8250.h>
  20 #include <linux/serial_core.h>
  21 #include <linux/serial_reg.h>
  22 #include <linux/of.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/of_platform.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include <linux/acpi.h>
  28 #include <linux/clk.h>
  29 #include <linux/pm_runtime.h>
  30
  31 #include <asm/byteorder.h>
  32
  33 #include "8250.h"
  34
  35 /* Offsets for the DesignWare specific registers */
  36 #define DW_UART_USR     0x1f /* UART Status Register */
  37 #define DW_UART_CPR     0xf4 /* Component Parameter Register */
  38 #define DW_UART_UCV     0xf8 /* UART Component Version */
  39
  40 /* Component Parameter Register bits */
  41 #define DW_UART_CPR_ABP_DATA_WIDTH      (3 << 0)
  42 #define DW_UART_CPR_AFCE_MODE           (1 << 4)
  43 #define DW_UART_CPR_THRE_MODE           (1 << 5)
  44 #define DW_UART_CPR_SIR_MODE            (1 << 6)
  45 #define DW_UART_CPR_SIR_LP_MODE         (1 << 7)
  46 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
  47 #define DW_UART_CPR_FIFO_ACCESS         (1 << 9)
  48 #define DW_UART_CPR_FIFO_STAT           (1 << 10)
  49 #define DW_UART_CPR_SHADOW              (1 << 11)
  50 #define DW_UART_CPR_ENCODED_PARMS       (1 << 12)
  51 #define DW_UART_CPR_DMA_EXTRA           (1 << 13)
  52 #define DW_UART_CPR_FIFO_MODE           (0xff << 16)
  53 /* Helper for fifo size calculation */
  54 #define DW_UART_CPR_FIFO_SIZE(a)        (((a >> 16) & 0xff) * 16)
  55
  56
  57 struct dw8250_data {
  58         u8                      usr_reg;
  59         int                     last_mcr;
  60         int                     line;
  61         struct clk              *clk;
  62         struct uart_8250_dma    dma;
  63 };
  64
  65 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
  66 {
  67         struct dw8250_data *d = p->private_data;
  68
  69         /* If reading MSR, report CTS asserted when auto-CTS/RTS enabled */
  70         if (offset == UART_MSR && d->last_mcr & UART_MCR_AFE) {
  71                 value |= UART_MSR_CTS;
  72                 value &= ~UART_MSR_DCTS;
  73         }
  74
  75         return value;
  76 }
  77
  78 static void dw8250_force_idle(struct uart_port *p)
  79 {
  80         serial8250_clear_and_reinit_fifos(container_of
  81                                           (p, struct uart_8250_port, port));
  82         (void)p->serial_in(p, UART_RX);
  83 }
  84
  85 static void dw8250_serial_out(struct uart_port *p, int offset, int value)
  86 {
  87         struct dw8250_data *d = p->private_data;
  88
  89         if (offset == UART_MCR)
  90                 d->last_mcr = value;
  91
  92         writeb(value, p->membase + (offset << p->regshift));
  93
  94         /* Make sure LCR write wasn't ignored */
  95         if (offset == UART_LCR) {
  96                 int tries = 1000;
  97                 while (tries--) {
  98                         unsigned int lcr = p->serial_in(p, UART_LCR);
  99                         if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
 100                                 return;
 101                         dw8250_force_idle(p);
 102                         writeb(value, p->membase + (UART_LCR << p->regshift));
 103                 }
 104                 dev_err(p->dev, "Couldn't set LCR to %d\n", value);
 105         }
 106 }
 107
 108 static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
 109 {
 110         unsigned int value = readb(p->membase + (offset << p->regshift));
 111
 112         return dw8250_modify_msr(p, offset, value);
 113 }
 114
 115 /* Read Back (rb) version to ensure register access ording. */
 116 static void dw8250_serial_out_rb(struct uart_port *p, int offset, int value)
 117 {
 118         dw8250_serial_out(p, offset, value);
 119         dw8250_serial_in(p, UART_LCR);
 120 }
 121
 122 static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
 123 {
 124         struct dw8250_data *d = p->private_data;
 125
 126         if (offset == UART_MCR)
 127                 d->last_mcr = value;
 128
 129         writel(value, p->membase + (offset << p->regshift));
 130
 131         /* Make sure LCR write wasn't ignored */
 132         if (offset == UART_LCR) {
 133                 int tries = 1000;
 134                 while (tries--) {
 135                         unsigned int lcr = p->serial_in(p, UART_LCR);
 136                         if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
 137                                 return;
 138                         dw8250_force_idle(p);
 139                         writel(value, p->membase + (UART_LCR << p->regshift));
 140                 }
 141                 dev_err(p->dev, "Couldn't set LCR to %d\n", value);
 142         }
 143 }
 144
 145 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
 146 {
 147         unsigned int value = readl(p->membase + (offset << p->regshift));
 148
 149         return dw8250_modify_msr(p, offset, value);
 150 }
 151
 152 static int dw8250_handle_irq(struct uart_port *p)
 153 {
 154         struct dw8250_data *d = p->private_data;
 155         unsigned int iir = p->serial_in(p, UART_IIR);
 156
 157         if (serial8250_handle_irq(p, iir)) {
 158                 return 1;
 159         } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
 160                 /* Clear the USR */
 161                 (void)p->serial_in(p, d->usr_reg);
 162
 163                 return 1;
 164         }
 165
 166         return 0;
 167 }
 168
 169 static void
 170 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
 171 {
 172         if (!state)
 173                 pm_runtime_get_sync(port->dev);
 174
 175         serial8250_do_pm(port, state, old);
 176
 177         if (state)
 178                 pm_runtime_put_sync_suspend(port->dev);
 179 }
 180
 181 static bool dw8250_dma_filter(struct dma_chan *chan, void *param)
 182 {
 183         struct dw8250_data *data = param;
 184
 185         return chan->chan_id == data->dma.tx_chan_id ||
 186                chan->chan_id == data->dma.rx_chan_id;
 187 }
 188
 189 static void dw8250_setup_port(struct uart_8250_port *up)
 190 {
 191         struct uart_port        *p = &up->port;
 192         u32                     reg = readl(p->membase + DW_UART_UCV);
 193
 194         /*
 195          * If the Component Version Register returns zero, we know that
 196          * ADDITIONAL_FEATURES are not enabled. No need to go any further.
 197          */
 198         if (!reg)
 199                 return;
 200
 201         dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n",
 202                 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
 203
 204         reg = readl(p->membase + DW_UART_CPR);
 205         if (!reg)
 206                 return;
 207
 208         /* Select the type based on fifo */
 209         if (reg & DW_UART_CPR_FIFO_MODE) {
 210                 p->type = PORT_16550A;
 211                 p->flags |= UPF_FIXED_TYPE;
 212                 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
 213                 up->tx_loadsz = p->fifosize;
 214                 up->capabilities = UART_CAP_FIFO;
 215         }
 216
 217         if (reg & DW_UART_CPR_AFCE_MODE)
 218                 up->capabilities |= UART_CAP_AFE;
 219 }
 220
 221 static int dw8250_probe_of(struct uart_port *p,
 222                            struct dw8250_data *data)
 223 {
 224         struct device_node      *np = p->dev->of_node;
 225         u32                     val;
 226         bool has_ucv = true;
 227
 228         if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
 229 #ifdef __BIG_ENDIAN
 230                 /*
 231                  * Low order bits of these 64-bit registers, when
 232                  * accessed as a byte, are 7 bytes further down in the
 233                  * address space in big endian mode.
 234                  */
 235                 p->membase += 7;
 236 #endif
 237                 p->serial_out = dw8250_serial_out_rb;
 238                 p->flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
 239                 p->type = PORT_OCTEON;
 240                 data->usr_reg = 0x27;
 241                 has_ucv = false;
 242         } else if (!of_property_read_u32(np, "reg-io-width", &val)) {
 243                 switch (val) {
 244                 case 1:
 245                         break;
 246                 case 4:
 247                         p->iotype = UPIO_MEM32;
 248                         p->serial_in = dw8250_serial_in32;
 249                         p->serial_out = dw8250_serial_out32;
 250                         break;
 251                 default:
 252                         dev_err(p->dev, "unsupported reg-io-width (%u)\n", val);
 253                         return -EINVAL;
 254                 }
 255         }
 256         if (has_ucv)
 257                 dw8250_setup_port(container_of(p, struct uart_8250_port, port));
 258
 259         if (!of_property_read_u32(np, "reg-shift", &val))
 260                 p->regshift = val;
 261
 262         /* clock got configured through clk api, all done */
 263         if (p->uartclk)
 264                 return 0;
 265
 266         /* try to find out clock frequency from DT as fallback */
 267         if (of_property_read_u32(np, "clock-frequency", &val)) {
 268                 dev_err(p->dev, "clk or clock-frequency not defined\n");
 269                 return -EINVAL;
 270         }
 271         p->uartclk = val;
 272
 273         return 0;
 274 }
 275
 276 static int dw8250_probe_acpi(struct uart_8250_port *up,
 277                              struct dw8250_data *data)
 278 {
 279         const struct acpi_device_id *id;
 280         struct uart_port *p = &up->port;
 281
 282         dw8250_setup_port(up);
 283
 284         id = acpi_match_device(p->dev->driver->acpi_match_table, p->dev);
 285         if (!id)
 286                 return -ENODEV;
 287
 288         p->iotype = UPIO_MEM32;
 289         p->serial_in = dw8250_serial_in32;
 290         p->serial_out = dw8250_serial_out32;
 291         p->regshift = 2;
 292
 293         if (!p->uartclk)
 294                 p->uartclk = (unsigned int)id->driver_data;
 295
 296         up->dma = &data->dma;
 297
 298         up->dma->rxconf.src_maxburst = p->fifosize / 4;
 299         up->dma->txconf.dst_maxburst = p->fifosize / 4;
 300
 301         return 0;
 302 }
 303
 304 static int dw8250_probe(struct platform_device *pdev)
 305 {
 306         struct uart_8250_port uart = {};
 307         struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 308         struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 309         struct dw8250_data *data;
 310         int err;
 311
 312         if (!regs || !irq) {
 313                 dev_err(&pdev->dev, "no registers/irq defined\n");
 314                 return -EINVAL;
 315         }
 316
 317         spin_lock_init(&uart.port.lock);
 318         uart.port.mapbase = regs->start;
 319         uart.port.irq = irq->start;
 320         uart.port.handle_irq = dw8250_handle_irq;
 321         uart.port.pm = dw8250_do_pm;
 322         uart.port.type = PORT_8250;
 323         uart.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
 324         uart.port.dev = &pdev->dev;
 325
 326         uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
 327                                          resource_size(regs));
 328         if (!uart.port.membase)
 329                 return -ENOMEM;
 330
 331         data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
 332         if (!data)
 333                 return -ENOMEM;
 334
 335         data->usr_reg = DW_UART_USR;
 336         data->clk = devm_clk_get(&pdev->dev, NULL);
 337         if (!IS_ERR(data->clk)) {
 338                 clk_prepare_enable(data->clk);
 339                 uart.port.uartclk = clk_get_rate(data->clk);
 340         }
 341
 342         data->dma.rx_chan_id = -1;
 343         data->dma.tx_chan_id = -1;
 344         data->dma.rx_param = data;
 345         data->dma.tx_param = data;
 346         data->dma.fn = dw8250_dma_filter;
 347
 348         uart.port.iotype = UPIO_MEM;
 349         uart.port.serial_in = dw8250_serial_in;
 350         uart.port.serial_out = dw8250_serial_out;
 351         uart.port.private_data = data;
 352
 353         if (pdev->dev.of_node) {
 354                 err = dw8250_probe_of(&uart.port, data);
 355                 if (err)
 356                         return err;
 357         } else if (ACPI_HANDLE(&pdev->dev)) {
 358                 err = dw8250_probe_acpi(&uart, data);
 359                 if (err)
 360                         return err;
 361         } else {
 362                 return -ENODEV;
 363         }
 364
 365         data->line = serial8250_register_8250_port(&uart);
 366         if (data->line < 0)
 367                 return data->line;
 368
 369         platform_set_drvdata(pdev, data);
 370
 371         pm_runtime_set_active(&pdev->dev);
 372         pm_runtime_enable(&pdev->dev);
 373
 374         return 0;
 375 }
 376
 377 static int dw8250_remove(struct platform_device *pdev)
 378 {
 379         struct dw8250_data *data = platform_get_drvdata(pdev);
 380
 381         pm_runtime_get_sync(&pdev->dev);
 382
 383         serial8250_unregister_port(data->line);
 384
 385         if (!IS_ERR(data->clk))
 386                 clk_disable_unprepare(data->clk);
 387
 388         pm_runtime_disable(&pdev->dev);
 389         pm_runtime_put_noidle(&pdev->dev);
 390
 391         return 0;
 392 }
 393
 394 #ifdef CONFIG_PM
 395 static int dw8250_suspend(struct device *dev)
 396 {
 397         struct dw8250_data *data = dev_get_drvdata(dev);
 398
 399         serial8250_suspend_port(data->line);
 400
 401         return 0;
 402 }
 403
 404 static int dw8250_resume(struct device *dev)
 405 {
 406         struct dw8250_data *data = dev_get_drvdata(dev);
 407
 408         serial8250_resume_port(data->line);
 409
 410         return 0;
 411 }
 412 #endif /* CONFIG_PM */
 413
 414 #ifdef CONFIG_PM_RUNTIME
 415 static int dw8250_runtime_suspend(struct device *dev)
 416 {
 417         struct dw8250_data *data = dev_get_drvdata(dev);
 418
 419         if (!IS_ERR(data->clk))
 420                 clk_disable_unprepare(data->clk);
 421
 422         return 0;
 423 }
 424
 425 static int dw8250_runtime_resume(struct device *dev)
 426 {
 427         struct dw8250_data *data = dev_get_drvdata(dev);
 428
 429         if (!IS_ERR(data->clk))
 430                 clk_prepare_enable(data->clk);
 431
 432         return 0;
 433 }
 434 #endif
 435
 436 static const struct dev_pm_ops dw8250_pm_ops = {
 437         SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
 438         SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
 439 };
 440
 441 static const struct of_device_id dw8250_of_match[] = {
 442         { .compatible = "snps,dw-apb-uart" },
 443         { .compatible = "cavium,octeon-3860-uart" },
 444         { /* Sentinel */ }
 445 };
 446 MODULE_DEVICE_TABLE(of, dw8250_of_match);
 447
 448 static const struct acpi_device_id dw8250_acpi_match[] = {
 449         { "INT33C4", 0 },
 450         { "INT33C5", 0 },
 451         { "INT3434", 0 },
 452         { "INT3435", 0 },
 453         { "80860F0A", 0 },
 454         { },
 455 };
 456 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
 457
 458 static struct platform_driver dw8250_platform_driver = {
 459         .driver = {
 460                 .name           = "dw-apb-uart",
 461                 .owner          = THIS_MODULE,
 462                 .pm             = &dw8250_pm_ops,
 463                 .of_match_table = dw8250_of_match,
 464                 .acpi_match_table = ACPI_PTR(dw8250_acpi_match),
 465         },
 466         .probe                  = dw8250_probe,
 467         .remove                 = dw8250_remove,
 468 };
 469
 470 module_platform_driver(dw8250_platform_driver);
 471
 472 MODULE_AUTHOR("Jamie Iles");
 473 MODULE_LICENSE("GPL");
 474 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");