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Merge 3.8-rc5 into tty-next
[deliverable/linux.git] / drivers / tty / serial / 8250 / 8250_pci.c
1 /*
2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
11 */
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_reg.h>
21 #include <linux/serial_core.h>
22 #include <linux/8250_pci.h>
23 #include <linux/bitops.h>
24
25 #include <asm/byteorder.h>
26 #include <asm/io.h>
27
28 #include "8250.h"
29
30 #undef SERIAL_DEBUG_PCI
31
32 /*
33 * init function returns:
34 * > 0 - number of ports
35 * = 0 - use board->num_ports
36 * < 0 - error
37 */
38 struct pci_serial_quirk {
39 u32 vendor;
40 u32 device;
41 u32 subvendor;
42 u32 subdevice;
43 int (*probe)(struct pci_dev *dev);
44 int (*init)(struct pci_dev *dev);
45 int (*setup)(struct serial_private *,
46 const struct pciserial_board *,
47 struct uart_8250_port *, int);
48 void (*exit)(struct pci_dev *dev);
49 };
50
51 #define PCI_NUM_BAR_RESOURCES 6
52
53 struct serial_private {
54 struct pci_dev *dev;
55 unsigned int nr;
56 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
57 struct pci_serial_quirk *quirk;
58 int line[0];
59 };
60
61 static int pci_default_setup(struct serial_private*,
62 const struct pciserial_board*, struct uart_8250_port *, int);
63
64 static void moan_device(const char *str, struct pci_dev *dev)
65 {
66 printk(KERN_WARNING
67 "%s: %s\n"
68 "Please send the output of lspci -vv, this\n"
69 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
70 "manufacturer and name of serial board or\n"
71 "modem board to rmk+serial@arm.linux.org.uk.\n",
72 pci_name(dev), str, dev->vendor, dev->device,
73 dev->subsystem_vendor, dev->subsystem_device);
74 }
75
76 static int
77 setup_port(struct serial_private *priv, struct uart_8250_port *port,
78 int bar, int offset, int regshift)
79 {
80 struct pci_dev *dev = priv->dev;
81 unsigned long base, len;
82
83 if (bar >= PCI_NUM_BAR_RESOURCES)
84 return -EINVAL;
85
86 base = pci_resource_start(dev, bar);
87
88 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
89 len = pci_resource_len(dev, bar);
90
91 if (!priv->remapped_bar[bar])
92 priv->remapped_bar[bar] = ioremap_nocache(base, len);
93 if (!priv->remapped_bar[bar])
94 return -ENOMEM;
95
96 port->port.iotype = UPIO_MEM;
97 port->port.iobase = 0;
98 port->port.mapbase = base + offset;
99 port->port.membase = priv->remapped_bar[bar] + offset;
100 port->port.regshift = regshift;
101 } else {
102 port->port.iotype = UPIO_PORT;
103 port->port.iobase = base + offset;
104 port->port.mapbase = 0;
105 port->port.membase = NULL;
106 port->port.regshift = 0;
107 }
108 return 0;
109 }
110
111 /*
112 * ADDI-DATA GmbH communication cards <info@addi-data.com>
113 */
114 static int addidata_apci7800_setup(struct serial_private *priv,
115 const struct pciserial_board *board,
116 struct uart_8250_port *port, int idx)
117 {
118 unsigned int bar = 0, offset = board->first_offset;
119 bar = FL_GET_BASE(board->flags);
120
121 if (idx < 2) {
122 offset += idx * board->uart_offset;
123 } else if ((idx >= 2) && (idx < 4)) {
124 bar += 1;
125 offset += ((idx - 2) * board->uart_offset);
126 } else if ((idx >= 4) && (idx < 6)) {
127 bar += 2;
128 offset += ((idx - 4) * board->uart_offset);
129 } else if (idx >= 6) {
130 bar += 3;
131 offset += ((idx - 6) * board->uart_offset);
132 }
133
134 return setup_port(priv, port, bar, offset, board->reg_shift);
135 }
136
137 /*
138 * AFAVLAB uses a different mixture of BARs and offsets
139 * Not that ugly ;) -- HW
140 */
141 static int
142 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
143 struct uart_8250_port *port, int idx)
144 {
145 unsigned int bar, offset = board->first_offset;
146
147 bar = FL_GET_BASE(board->flags);
148 if (idx < 4)
149 bar += idx;
150 else {
151 bar = 4;
152 offset += (idx - 4) * board->uart_offset;
153 }
154
155 return setup_port(priv, port, bar, offset, board->reg_shift);
156 }
157
158 /*
159 * HP's Remote Management Console. The Diva chip came in several
160 * different versions. N-class, L2000 and A500 have two Diva chips, each
161 * with 3 UARTs (the third UART on the second chip is unused). Superdome
162 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
163 * one Diva chip, but it has been expanded to 5 UARTs.
164 */
165 static int pci_hp_diva_init(struct pci_dev *dev)
166 {
167 int rc = 0;
168
169 switch (dev->subsystem_device) {
170 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
171 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
172 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
173 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
174 rc = 3;
175 break;
176 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
177 rc = 2;
178 break;
179 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
180 rc = 4;
181 break;
182 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
183 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
184 rc = 1;
185 break;
186 }
187
188 return rc;
189 }
190
191 /*
192 * HP's Diva chip puts the 4th/5th serial port further out, and
193 * some serial ports are supposed to be hidden on certain models.
194 */
195 static int
196 pci_hp_diva_setup(struct serial_private *priv,
197 const struct pciserial_board *board,
198 struct uart_8250_port *port, int idx)
199 {
200 unsigned int offset = board->first_offset;
201 unsigned int bar = FL_GET_BASE(board->flags);
202
203 switch (priv->dev->subsystem_device) {
204 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
205 if (idx == 3)
206 idx++;
207 break;
208 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
209 if (idx > 0)
210 idx++;
211 if (idx > 2)
212 idx++;
213 break;
214 }
215 if (idx > 2)
216 offset = 0x18;
217
218 offset += idx * board->uart_offset;
219
220 return setup_port(priv, port, bar, offset, board->reg_shift);
221 }
222
223 /*
224 * Added for EKF Intel i960 serial boards
225 */
226 static int pci_inteli960ni_init(struct pci_dev *dev)
227 {
228 unsigned long oldval;
229
230 if (!(dev->subsystem_device & 0x1000))
231 return -ENODEV;
232
233 /* is firmware started? */
234 pci_read_config_dword(dev, 0x44, (void *)&oldval);
235 if (oldval == 0x00001000L) { /* RESET value */
236 printk(KERN_DEBUG "Local i960 firmware missing");
237 return -ENODEV;
238 }
239 return 0;
240 }
241
242 /*
243 * Some PCI serial cards using the PLX 9050 PCI interface chip require
244 * that the card interrupt be explicitly enabled or disabled. This
245 * seems to be mainly needed on card using the PLX which also use I/O
246 * mapped memory.
247 */
248 static int pci_plx9050_init(struct pci_dev *dev)
249 {
250 u8 irq_config;
251 void __iomem *p;
252
253 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
254 moan_device("no memory in bar 0", dev);
255 return 0;
256 }
257
258 irq_config = 0x41;
259 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
260 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
261 irq_config = 0x43;
262
263 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
264 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
265 /*
266 * As the megawolf cards have the int pins active
267 * high, and have 2 UART chips, both ints must be
268 * enabled on the 9050. Also, the UARTS are set in
269 * 16450 mode by default, so we have to enable the
270 * 16C950 'enhanced' mode so that we can use the
271 * deep FIFOs
272 */
273 irq_config = 0x5b;
274 /*
275 * enable/disable interrupts
276 */
277 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
278 if (p == NULL)
279 return -ENOMEM;
280 writel(irq_config, p + 0x4c);
281
282 /*
283 * Read the register back to ensure that it took effect.
284 */
285 readl(p + 0x4c);
286 iounmap(p);
287
288 return 0;
289 }
290
291 static void pci_plx9050_exit(struct pci_dev *dev)
292 {
293 u8 __iomem *p;
294
295 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
296 return;
297
298 /*
299 * disable interrupts
300 */
301 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
302 if (p != NULL) {
303 writel(0, p + 0x4c);
304
305 /*
306 * Read the register back to ensure that it took effect.
307 */
308 readl(p + 0x4c);
309 iounmap(p);
310 }
311 }
312
313 #define NI8420_INT_ENABLE_REG 0x38
314 #define NI8420_INT_ENABLE_BIT 0x2000
315
316 static void pci_ni8420_exit(struct pci_dev *dev)
317 {
318 void __iomem *p;
319 unsigned long base, len;
320 unsigned int bar = 0;
321
322 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
323 moan_device("no memory in bar", dev);
324 return;
325 }
326
327 base = pci_resource_start(dev, bar);
328 len = pci_resource_len(dev, bar);
329 p = ioremap_nocache(base, len);
330 if (p == NULL)
331 return;
332
333 /* Disable the CPU Interrupt */
334 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
335 p + NI8420_INT_ENABLE_REG);
336 iounmap(p);
337 }
338
339
340 /* MITE registers */
341 #define MITE_IOWBSR1 0xc4
342 #define MITE_IOWCR1 0xf4
343 #define MITE_LCIMR1 0x08
344 #define MITE_LCIMR2 0x10
345
346 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
347
348 static void pci_ni8430_exit(struct pci_dev *dev)
349 {
350 void __iomem *p;
351 unsigned long base, len;
352 unsigned int bar = 0;
353
354 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
355 moan_device("no memory in bar", dev);
356 return;
357 }
358
359 base = pci_resource_start(dev, bar);
360 len = pci_resource_len(dev, bar);
361 p = ioremap_nocache(base, len);
362 if (p == NULL)
363 return;
364
365 /* Disable the CPU Interrupt */
366 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
367 iounmap(p);
368 }
369
370 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
371 static int
372 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
373 struct uart_8250_port *port, int idx)
374 {
375 unsigned int bar, offset = board->first_offset;
376
377 bar = 0;
378
379 if (idx < 4) {
380 /* first four channels map to 0, 0x100, 0x200, 0x300 */
381 offset += idx * board->uart_offset;
382 } else if (idx < 8) {
383 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
384 offset += idx * board->uart_offset + 0xC00;
385 } else /* we have only 8 ports on PMC-OCTALPRO */
386 return 1;
387
388 return setup_port(priv, port, bar, offset, board->reg_shift);
389 }
390
391 /*
392 * This does initialization for PMC OCTALPRO cards:
393 * maps the device memory, resets the UARTs (needed, bc
394 * if the module is removed and inserted again, the card
395 * is in the sleep mode) and enables global interrupt.
396 */
397
398 /* global control register offset for SBS PMC-OctalPro */
399 #define OCT_REG_CR_OFF 0x500
400
401 static int sbs_init(struct pci_dev *dev)
402 {
403 u8 __iomem *p;
404
405 p = pci_ioremap_bar(dev, 0);
406
407 if (p == NULL)
408 return -ENOMEM;
409 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
410 writeb(0x10, p + OCT_REG_CR_OFF);
411 udelay(50);
412 writeb(0x0, p + OCT_REG_CR_OFF);
413
414 /* Set bit-2 (INTENABLE) of Control Register */
415 writeb(0x4, p + OCT_REG_CR_OFF);
416 iounmap(p);
417
418 return 0;
419 }
420
421 /*
422 * Disables the global interrupt of PMC-OctalPro
423 */
424
425 static void sbs_exit(struct pci_dev *dev)
426 {
427 u8 __iomem *p;
428
429 p = pci_ioremap_bar(dev, 0);
430 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
431 if (p != NULL)
432 writeb(0, p + OCT_REG_CR_OFF);
433 iounmap(p);
434 }
435
436 /*
437 * SIIG serial cards have an PCI interface chip which also controls
438 * the UART clocking frequency. Each UART can be clocked independently
439 * (except cards equipped with 4 UARTs) and initial clocking settings
440 * are stored in the EEPROM chip. It can cause problems because this
441 * version of serial driver doesn't support differently clocked UART's
442 * on single PCI card. To prevent this, initialization functions set
443 * high frequency clocking for all UART's on given card. It is safe (I
444 * hope) because it doesn't touch EEPROM settings to prevent conflicts
445 * with other OSes (like M$ DOS).
446 *
447 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
448 *
449 * There is two family of SIIG serial cards with different PCI
450 * interface chip and different configuration methods:
451 * - 10x cards have control registers in IO and/or memory space;
452 * - 20x cards have control registers in standard PCI configuration space.
453 *
454 * Note: all 10x cards have PCI device ids 0x10..
455 * all 20x cards have PCI device ids 0x20..
456 *
457 * There are also Quartet Serial cards which use Oxford Semiconductor
458 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
459 *
460 * Note: some SIIG cards are probed by the parport_serial object.
461 */
462
463 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
464 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
465
466 static int pci_siig10x_init(struct pci_dev *dev)
467 {
468 u16 data;
469 void __iomem *p;
470
471 switch (dev->device & 0xfff8) {
472 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
473 data = 0xffdf;
474 break;
475 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
476 data = 0xf7ff;
477 break;
478 default: /* 1S1P, 4S */
479 data = 0xfffb;
480 break;
481 }
482
483 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
484 if (p == NULL)
485 return -ENOMEM;
486
487 writew(readw(p + 0x28) & data, p + 0x28);
488 readw(p + 0x28);
489 iounmap(p);
490 return 0;
491 }
492
493 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
494 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
495
496 static int pci_siig20x_init(struct pci_dev *dev)
497 {
498 u8 data;
499
500 /* Change clock frequency for the first UART. */
501 pci_read_config_byte(dev, 0x6f, &data);
502 pci_write_config_byte(dev, 0x6f, data & 0xef);
503
504 /* If this card has 2 UART, we have to do the same with second UART. */
505 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
506 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
507 pci_read_config_byte(dev, 0x73, &data);
508 pci_write_config_byte(dev, 0x73, data & 0xef);
509 }
510 return 0;
511 }
512
513 static int pci_siig_init(struct pci_dev *dev)
514 {
515 unsigned int type = dev->device & 0xff00;
516
517 if (type == 0x1000)
518 return pci_siig10x_init(dev);
519 else if (type == 0x2000)
520 return pci_siig20x_init(dev);
521
522 moan_device("Unknown SIIG card", dev);
523 return -ENODEV;
524 }
525
526 static int pci_siig_setup(struct serial_private *priv,
527 const struct pciserial_board *board,
528 struct uart_8250_port *port, int idx)
529 {
530 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
531
532 if (idx > 3) {
533 bar = 4;
534 offset = (idx - 4) * 8;
535 }
536
537 return setup_port(priv, port, bar, offset, 0);
538 }
539
540 /*
541 * Timedia has an explosion of boards, and to avoid the PCI table from
542 * growing *huge*, we use this function to collapse some 70 entries
543 * in the PCI table into one, for sanity's and compactness's sake.
544 */
545 static const unsigned short timedia_single_port[] = {
546 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
547 };
548
549 static const unsigned short timedia_dual_port[] = {
550 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
551 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
552 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
553 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
554 0xD079, 0
555 };
556
557 static const unsigned short timedia_quad_port[] = {
558 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
559 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
560 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
561 0xB157, 0
562 };
563
564 static const unsigned short timedia_eight_port[] = {
565 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
566 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
567 };
568
569 static const struct timedia_struct {
570 int num;
571 const unsigned short *ids;
572 } timedia_data[] = {
573 { 1, timedia_single_port },
574 { 2, timedia_dual_port },
575 { 4, timedia_quad_port },
576 { 8, timedia_eight_port }
577 };
578
579 /*
580 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
581 * listing them individually, this driver merely grabs them all with
582 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
583 * and should be left free to be claimed by parport_serial instead.
584 */
585 static int pci_timedia_probe(struct pci_dev *dev)
586 {
587 /*
588 * Check the third digit of the subdevice ID
589 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
590 */
591 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
592 dev_info(&dev->dev,
593 "ignoring Timedia subdevice %04x for parport_serial\n",
594 dev->subsystem_device);
595 return -ENODEV;
596 }
597
598 return 0;
599 }
600
601 static int pci_timedia_init(struct pci_dev *dev)
602 {
603 const unsigned short *ids;
604 int i, j;
605
606 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
607 ids = timedia_data[i].ids;
608 for (j = 0; ids[j]; j++)
609 if (dev->subsystem_device == ids[j])
610 return timedia_data[i].num;
611 }
612 return 0;
613 }
614
615 /*
616 * Timedia/SUNIX uses a mixture of BARs and offsets
617 * Ugh, this is ugly as all hell --- TYT
618 */
619 static int
620 pci_timedia_setup(struct serial_private *priv,
621 const struct pciserial_board *board,
622 struct uart_8250_port *port, int idx)
623 {
624 unsigned int bar = 0, offset = board->first_offset;
625
626 switch (idx) {
627 case 0:
628 bar = 0;
629 break;
630 case 1:
631 offset = board->uart_offset;
632 bar = 0;
633 break;
634 case 2:
635 bar = 1;
636 break;
637 case 3:
638 offset = board->uart_offset;
639 /* FALLTHROUGH */
640 case 4: /* BAR 2 */
641 case 5: /* BAR 3 */
642 case 6: /* BAR 4 */
643 case 7: /* BAR 5 */
644 bar = idx - 2;
645 }
646
647 return setup_port(priv, port, bar, offset, board->reg_shift);
648 }
649
650 /*
651 * Some Titan cards are also a little weird
652 */
653 static int
654 titan_400l_800l_setup(struct serial_private *priv,
655 const struct pciserial_board *board,
656 struct uart_8250_port *port, int idx)
657 {
658 unsigned int bar, offset = board->first_offset;
659
660 switch (idx) {
661 case 0:
662 bar = 1;
663 break;
664 case 1:
665 bar = 2;
666 break;
667 default:
668 bar = 4;
669 offset = (idx - 2) * board->uart_offset;
670 }
671
672 return setup_port(priv, port, bar, offset, board->reg_shift);
673 }
674
675 static int pci_xircom_init(struct pci_dev *dev)
676 {
677 msleep(100);
678 return 0;
679 }
680
681 static int pci_ni8420_init(struct pci_dev *dev)
682 {
683 void __iomem *p;
684 unsigned long base, len;
685 unsigned int bar = 0;
686
687 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
688 moan_device("no memory in bar", dev);
689 return 0;
690 }
691
692 base = pci_resource_start(dev, bar);
693 len = pci_resource_len(dev, bar);
694 p = ioremap_nocache(base, len);
695 if (p == NULL)
696 return -ENOMEM;
697
698 /* Enable CPU Interrupt */
699 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
700 p + NI8420_INT_ENABLE_REG);
701
702 iounmap(p);
703 return 0;
704 }
705
706 #define MITE_IOWBSR1_WSIZE 0xa
707 #define MITE_IOWBSR1_WIN_OFFSET 0x800
708 #define MITE_IOWBSR1_WENAB (1 << 7)
709 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
710 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
711 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
712
713 static int pci_ni8430_init(struct pci_dev *dev)
714 {
715 void __iomem *p;
716 unsigned long base, len;
717 u32 device_window;
718 unsigned int bar = 0;
719
720 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
721 moan_device("no memory in bar", dev);
722 return 0;
723 }
724
725 base = pci_resource_start(dev, bar);
726 len = pci_resource_len(dev, bar);
727 p = ioremap_nocache(base, len);
728 if (p == NULL)
729 return -ENOMEM;
730
731 /* Set device window address and size in BAR0 */
732 device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
733 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
734 writel(device_window, p + MITE_IOWBSR1);
735
736 /* Set window access to go to RAMSEL IO address space */
737 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
738 p + MITE_IOWCR1);
739
740 /* Enable IO Bus Interrupt 0 */
741 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
742
743 /* Enable CPU Interrupt */
744 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
745
746 iounmap(p);
747 return 0;
748 }
749
750 /* UART Port Control Register */
751 #define NI8430_PORTCON 0x0f
752 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
753
754 static int
755 pci_ni8430_setup(struct serial_private *priv,
756 const struct pciserial_board *board,
757 struct uart_8250_port *port, int idx)
758 {
759 void __iomem *p;
760 unsigned long base, len;
761 unsigned int bar, offset = board->first_offset;
762
763 if (idx >= board->num_ports)
764 return 1;
765
766 bar = FL_GET_BASE(board->flags);
767 offset += idx * board->uart_offset;
768
769 base = pci_resource_start(priv->dev, bar);
770 len = pci_resource_len(priv->dev, bar);
771 p = ioremap_nocache(base, len);
772
773 /* enable the transceiver */
774 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
775 p + offset + NI8430_PORTCON);
776
777 iounmap(p);
778
779 return setup_port(priv, port, bar, offset, board->reg_shift);
780 }
781
782 static int pci_netmos_9900_setup(struct serial_private *priv,
783 const struct pciserial_board *board,
784 struct uart_8250_port *port, int idx)
785 {
786 unsigned int bar;
787
788 if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
789 /* netmos apparently orders BARs by datasheet layout, so serial
790 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
791 */
792 bar = 3 * idx;
793
794 return setup_port(priv, port, bar, 0, board->reg_shift);
795 } else {
796 return pci_default_setup(priv, board, port, idx);
797 }
798 }
799
800 /* the 99xx series comes with a range of device IDs and a variety
801 * of capabilities:
802 *
803 * 9900 has varying capabilities and can cascade to sub-controllers
804 * (cascading should be purely internal)
805 * 9904 is hardwired with 4 serial ports
806 * 9912 and 9922 are hardwired with 2 serial ports
807 */
808 static int pci_netmos_9900_numports(struct pci_dev *dev)
809 {
810 unsigned int c = dev->class;
811 unsigned int pi;
812 unsigned short sub_serports;
813
814 pi = (c & 0xff);
815
816 if (pi == 2) {
817 return 1;
818 } else if ((pi == 0) &&
819 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
820 /* two possibilities: 0x30ps encodes number of parallel and
821 * serial ports, or 0x1000 indicates *something*. This is not
822 * immediately obvious, since the 2s1p+4s configuration seems
823 * to offer all functionality on functions 0..2, while still
824 * advertising the same function 3 as the 4s+2s1p config.
825 */
826 sub_serports = dev->subsystem_device & 0xf;
827 if (sub_serports > 0) {
828 return sub_serports;
829 } else {
830 printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
831 return 0;
832 }
833 }
834
835 moan_device("unknown NetMos/Mostech program interface", dev);
836 return 0;
837 }
838
839 static int pci_netmos_init(struct pci_dev *dev)
840 {
841 /* subdevice 0x00PS means <P> parallel, <S> serial */
842 unsigned int num_serial = dev->subsystem_device & 0xf;
843
844 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
845 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
846 return 0;
847
848 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
849 dev->subsystem_device == 0x0299)
850 return 0;
851
852 switch (dev->device) { /* FALLTHROUGH on all */
853 case PCI_DEVICE_ID_NETMOS_9904:
854 case PCI_DEVICE_ID_NETMOS_9912:
855 case PCI_DEVICE_ID_NETMOS_9922:
856 case PCI_DEVICE_ID_NETMOS_9900:
857 num_serial = pci_netmos_9900_numports(dev);
858 break;
859
860 default:
861 if (num_serial == 0 ) {
862 moan_device("unknown NetMos/Mostech device", dev);
863 }
864 }
865
866 if (num_serial == 0)
867 return -ENODEV;
868
869 return num_serial;
870 }
871
872 /*
873 * These chips are available with optionally one parallel port and up to
874 * two serial ports. Unfortunately they all have the same product id.
875 *
876 * Basic configuration is done over a region of 32 I/O ports. The base
877 * ioport is called INTA or INTC, depending on docs/other drivers.
878 *
879 * The region of the 32 I/O ports is configured in POSIO0R...
880 */
881
882 /* registers */
883 #define ITE_887x_MISCR 0x9c
884 #define ITE_887x_INTCBAR 0x78
885 #define ITE_887x_UARTBAR 0x7c
886 #define ITE_887x_PS0BAR 0x10
887 #define ITE_887x_POSIO0 0x60
888
889 /* I/O space size */
890 #define ITE_887x_IOSIZE 32
891 /* I/O space size (bits 26-24; 8 bytes = 011b) */
892 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
893 /* I/O space size (bits 26-24; 32 bytes = 101b) */
894 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
895 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
896 #define ITE_887x_POSIO_SPEED (3 << 29)
897 /* enable IO_Space bit */
898 #define ITE_887x_POSIO_ENABLE (1 << 31)
899
900 static int pci_ite887x_init(struct pci_dev *dev)
901 {
902 /* inta_addr are the configuration addresses of the ITE */
903 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
904 0x200, 0x280, 0 };
905 int ret, i, type;
906 struct resource *iobase = NULL;
907 u32 miscr, uartbar, ioport;
908
909 /* search for the base-ioport */
910 i = 0;
911 while (inta_addr[i] && iobase == NULL) {
912 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
913 "ite887x");
914 if (iobase != NULL) {
915 /* write POSIO0R - speed | size | ioport */
916 pci_write_config_dword(dev, ITE_887x_POSIO0,
917 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
918 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
919 /* write INTCBAR - ioport */
920 pci_write_config_dword(dev, ITE_887x_INTCBAR,
921 inta_addr[i]);
922 ret = inb(inta_addr[i]);
923 if (ret != 0xff) {
924 /* ioport connected */
925 break;
926 }
927 release_region(iobase->start, ITE_887x_IOSIZE);
928 iobase = NULL;
929 }
930 i++;
931 }
932
933 if (!inta_addr[i]) {
934 printk(KERN_ERR "ite887x: could not find iobase\n");
935 return -ENODEV;
936 }
937
938 /* start of undocumented type checking (see parport_pc.c) */
939 type = inb(iobase->start + 0x18) & 0x0f;
940
941 switch (type) {
942 case 0x2: /* ITE8871 (1P) */
943 case 0xa: /* ITE8875 (1P) */
944 ret = 0;
945 break;
946 case 0xe: /* ITE8872 (2S1P) */
947 ret = 2;
948 break;
949 case 0x6: /* ITE8873 (1S) */
950 ret = 1;
951 break;
952 case 0x8: /* ITE8874 (2S) */
953 ret = 2;
954 break;
955 default:
956 moan_device("Unknown ITE887x", dev);
957 ret = -ENODEV;
958 }
959
960 /* configure all serial ports */
961 for (i = 0; i < ret; i++) {
962 /* read the I/O port from the device */
963 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
964 &ioport);
965 ioport &= 0x0000FF00; /* the actual base address */
966 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
967 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
968 ITE_887x_POSIO_IOSIZE_8 | ioport);
969
970 /* write the ioport to the UARTBAR */
971 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
972 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
973 uartbar |= (ioport << (16 * i)); /* set the ioport */
974 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
975
976 /* get current config */
977 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
978 /* disable interrupts (UARTx_Routing[3:0]) */
979 miscr &= ~(0xf << (12 - 4 * i));
980 /* activate the UART (UARTx_En) */
981 miscr |= 1 << (23 - i);
982 /* write new config with activated UART */
983 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
984 }
985
986 if (ret <= 0) {
987 /* the device has no UARTs if we get here */
988 release_region(iobase->start, ITE_887x_IOSIZE);
989 }
990
991 return ret;
992 }
993
994 static void pci_ite887x_exit(struct pci_dev *dev)
995 {
996 u32 ioport;
997 /* the ioport is bit 0-15 in POSIO0R */
998 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
999 ioport &= 0xffff;
1000 release_region(ioport, ITE_887x_IOSIZE);
1001 }
1002
1003 /*
1004 * Oxford Semiconductor Inc.
1005 * Check that device is part of the Tornado range of devices, then determine
1006 * the number of ports available on the device.
1007 */
1008 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1009 {
1010 u8 __iomem *p;
1011 unsigned long deviceID;
1012 unsigned int number_uarts = 0;
1013
1014 /* OxSemi Tornado devices are all 0xCxxx */
1015 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1016 (dev->device & 0xF000) != 0xC000)
1017 return 0;
1018
1019 p = pci_iomap(dev, 0, 5);
1020 if (p == NULL)
1021 return -ENOMEM;
1022
1023 deviceID = ioread32(p);
1024 /* Tornado device */
1025 if (deviceID == 0x07000200) {
1026 number_uarts = ioread8(p + 4);
1027 printk(KERN_DEBUG
1028 "%d ports detected on Oxford PCI Express device\n",
1029 number_uarts);
1030 }
1031 pci_iounmap(dev, p);
1032 return number_uarts;
1033 }
1034
1035 static int pci_asix_setup(struct serial_private *priv,
1036 const struct pciserial_board *board,
1037 struct uart_8250_port *port, int idx)
1038 {
1039 port->bugs |= UART_BUG_PARITY;
1040 return pci_default_setup(priv, board, port, idx);
1041 }
1042
1043 /* Quatech devices have their own extra interface features */
1044
1045 struct quatech_feature {
1046 u16 devid;
1047 bool amcc;
1048 };
1049
1050 #define QPCR_TEST_FOR1 0x3F
1051 #define QPCR_TEST_GET1 0x00
1052 #define QPCR_TEST_FOR2 0x40
1053 #define QPCR_TEST_GET2 0x40
1054 #define QPCR_TEST_FOR3 0x80
1055 #define QPCR_TEST_GET3 0x40
1056 #define QPCR_TEST_FOR4 0xC0
1057 #define QPCR_TEST_GET4 0x80
1058
1059 #define QOPR_CLOCK_X1 0x0000
1060 #define QOPR_CLOCK_X2 0x0001
1061 #define QOPR_CLOCK_X4 0x0002
1062 #define QOPR_CLOCK_X8 0x0003
1063 #define QOPR_CLOCK_RATE_MASK 0x0003
1064
1065
1066 static struct quatech_feature quatech_cards[] = {
1067 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1068 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1069 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1070 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1071 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1072 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1073 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1074 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1075 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1076 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1077 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1078 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1079 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1080 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1081 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1082 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1083 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1084 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1085 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1086 { 0, }
1087 };
1088
1089 static int pci_quatech_amcc(u16 devid)
1090 {
1091 struct quatech_feature *qf = &quatech_cards[0];
1092 while (qf->devid) {
1093 if (qf->devid == devid)
1094 return qf->amcc;
1095 qf++;
1096 }
1097 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1098 return 0;
1099 };
1100
1101 static int pci_quatech_rqopr(struct uart_8250_port *port)
1102 {
1103 unsigned long base = port->port.iobase;
1104 u8 LCR, val;
1105
1106 LCR = inb(base + UART_LCR);
1107 outb(0xBF, base + UART_LCR);
1108 val = inb(base + UART_SCR);
1109 outb(LCR, base + UART_LCR);
1110 return val;
1111 }
1112
1113 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1114 {
1115 unsigned long base = port->port.iobase;
1116 u8 LCR, val;
1117
1118 LCR = inb(base + UART_LCR);
1119 outb(0xBF, base + UART_LCR);
1120 val = inb(base + UART_SCR);
1121 outb(qopr, base + UART_SCR);
1122 outb(LCR, base + UART_LCR);
1123 }
1124
1125 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1126 {
1127 unsigned long base = port->port.iobase;
1128 u8 LCR, val, qmcr;
1129
1130 LCR = inb(base + UART_LCR);
1131 outb(0xBF, base + UART_LCR);
1132 val = inb(base + UART_SCR);
1133 outb(val | 0x10, base + UART_SCR);
1134 qmcr = inb(base + UART_MCR);
1135 outb(val, base + UART_SCR);
1136 outb(LCR, base + UART_LCR);
1137
1138 return qmcr;
1139 }
1140
1141 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1142 {
1143 unsigned long base = port->port.iobase;
1144 u8 LCR, val;
1145
1146 LCR = inb(base + UART_LCR);
1147 outb(0xBF, base + UART_LCR);
1148 val = inb(base + UART_SCR);
1149 outb(val | 0x10, base + UART_SCR);
1150 outb(qmcr, base + UART_MCR);
1151 outb(val, base + UART_SCR);
1152 outb(LCR, base + UART_LCR);
1153 }
1154
1155 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1156 {
1157 unsigned long base = port->port.iobase;
1158 u8 LCR, val;
1159
1160 LCR = inb(base + UART_LCR);
1161 outb(0xBF, base + UART_LCR);
1162 val = inb(base + UART_SCR);
1163 if (val & 0x20) {
1164 outb(0x80, UART_LCR);
1165 if (!(inb(UART_SCR) & 0x20)) {
1166 outb(LCR, base + UART_LCR);
1167 return 1;
1168 }
1169 }
1170 return 0;
1171 }
1172
1173 static int pci_quatech_test(struct uart_8250_port *port)
1174 {
1175 u8 reg;
1176 u8 qopr = pci_quatech_rqopr(port);
1177 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1178 reg = pci_quatech_rqopr(port) & 0xC0;
1179 if (reg != QPCR_TEST_GET1)
1180 return -EINVAL;
1181 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1182 reg = pci_quatech_rqopr(port) & 0xC0;
1183 if (reg != QPCR_TEST_GET2)
1184 return -EINVAL;
1185 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1186 reg = pci_quatech_rqopr(port) & 0xC0;
1187 if (reg != QPCR_TEST_GET3)
1188 return -EINVAL;
1189 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1190 reg = pci_quatech_rqopr(port) & 0xC0;
1191 if (reg != QPCR_TEST_GET4)
1192 return -EINVAL;
1193
1194 pci_quatech_wqopr(port, qopr);
1195 return 0;
1196 }
1197
1198 static int pci_quatech_clock(struct uart_8250_port *port)
1199 {
1200 u8 qopr, reg, set;
1201 unsigned long clock;
1202
1203 if (pci_quatech_test(port) < 0)
1204 return 1843200;
1205
1206 qopr = pci_quatech_rqopr(port);
1207
1208 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1209 reg = pci_quatech_rqopr(port);
1210 if (reg & QOPR_CLOCK_X8) {
1211 clock = 1843200;
1212 goto out;
1213 }
1214 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1215 reg = pci_quatech_rqopr(port);
1216 if (!(reg & QOPR_CLOCK_X8)) {
1217 clock = 1843200;
1218 goto out;
1219 }
1220 reg &= QOPR_CLOCK_X8;
1221 if (reg == QOPR_CLOCK_X2) {
1222 clock = 3685400;
1223 set = QOPR_CLOCK_X2;
1224 } else if (reg == QOPR_CLOCK_X4) {
1225 clock = 7372800;
1226 set = QOPR_CLOCK_X4;
1227 } else if (reg == QOPR_CLOCK_X8) {
1228 clock = 14745600;
1229 set = QOPR_CLOCK_X8;
1230 } else {
1231 clock = 1843200;
1232 set = QOPR_CLOCK_X1;
1233 }
1234 qopr &= ~QOPR_CLOCK_RATE_MASK;
1235 qopr |= set;
1236
1237 out:
1238 pci_quatech_wqopr(port, qopr);
1239 return clock;
1240 }
1241
1242 static int pci_quatech_rs422(struct uart_8250_port *port)
1243 {
1244 u8 qmcr;
1245 int rs422 = 0;
1246
1247 if (!pci_quatech_has_qmcr(port))
1248 return 0;
1249 qmcr = pci_quatech_rqmcr(port);
1250 pci_quatech_wqmcr(port, 0xFF);
1251 if (pci_quatech_rqmcr(port))
1252 rs422 = 1;
1253 pci_quatech_wqmcr(port, qmcr);
1254 return rs422;
1255 }
1256
1257 static int pci_quatech_init(struct pci_dev *dev)
1258 {
1259 if (pci_quatech_amcc(dev->device)) {
1260 unsigned long base = pci_resource_start(dev, 0);
1261 if (base) {
1262 u32 tmp;
1263 outl(inl(base + 0x38), base + 0x38);
1264 tmp = inl(base + 0x3c);
1265 outl(tmp | 0x01000000, base + 0x3c);
1266 outl(tmp, base + 0x3c);
1267 }
1268 }
1269 return 0;
1270 }
1271
1272 static int pci_quatech_setup(struct serial_private *priv,
1273 const struct pciserial_board *board,
1274 struct uart_8250_port *port, int idx)
1275 {
1276 /* Needed by pci_quatech calls below */
1277 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1278 /* Set up the clocking */
1279 port->port.uartclk = pci_quatech_clock(port);
1280 /* For now just warn about RS422 */
1281 if (pci_quatech_rs422(port))
1282 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1283 return pci_default_setup(priv, board, port, idx);
1284 }
1285
1286 static void pci_quatech_exit(struct pci_dev *dev)
1287 {
1288 }
1289
1290 static int pci_default_setup(struct serial_private *priv,
1291 const struct pciserial_board *board,
1292 struct uart_8250_port *port, int idx)
1293 {
1294 unsigned int bar, offset = board->first_offset, maxnr;
1295
1296 bar = FL_GET_BASE(board->flags);
1297 if (board->flags & FL_BASE_BARS)
1298 bar += idx;
1299 else
1300 offset += idx * board->uart_offset;
1301
1302 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1303 (board->reg_shift + 3);
1304
1305 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1306 return 1;
1307
1308 return setup_port(priv, port, bar, offset, board->reg_shift);
1309 }
1310
1311 static int
1312 ce4100_serial_setup(struct serial_private *priv,
1313 const struct pciserial_board *board,
1314 struct uart_8250_port *port, int idx)
1315 {
1316 int ret;
1317
1318 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1319 port->port.iotype = UPIO_MEM32;
1320 port->port.type = PORT_XSCALE;
1321 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1322 port->port.regshift = 2;
1323
1324 return ret;
1325 }
1326
1327 static int
1328 pci_omegapci_setup(struct serial_private *priv,
1329 const struct pciserial_board *board,
1330 struct uart_8250_port *port, int idx)
1331 {
1332 return setup_port(priv, port, 2, idx * 8, 0);
1333 }
1334
1335 static int
1336 pci_brcm_trumanage_setup(struct serial_private *priv,
1337 const struct pciserial_board *board,
1338 struct uart_8250_port *port, int idx)
1339 {
1340 int ret = pci_default_setup(priv, board, port, idx);
1341
1342 port->port.type = PORT_BRCM_TRUMANAGE;
1343 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1344 return ret;
1345 }
1346
1347 static int skip_tx_en_setup(struct serial_private *priv,
1348 const struct pciserial_board *board,
1349 struct uart_8250_port *port, int idx)
1350 {
1351 port->port.flags |= UPF_NO_TXEN_TEST;
1352 printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1353 "[%04x:%04x] subsystem [%04x:%04x]\n",
1354 priv->dev->vendor,
1355 priv->dev->device,
1356 priv->dev->subsystem_vendor,
1357 priv->dev->subsystem_device);
1358
1359 return pci_default_setup(priv, board, port, idx);
1360 }
1361
1362 static void kt_handle_break(struct uart_port *p)
1363 {
1364 struct uart_8250_port *up =
1365 container_of(p, struct uart_8250_port, port);
1366 /*
1367 * On receipt of a BI, serial device in Intel ME (Intel
1368 * management engine) needs to have its fifos cleared for sane
1369 * SOL (Serial Over Lan) output.
1370 */
1371 serial8250_clear_and_reinit_fifos(up);
1372 }
1373
1374 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1375 {
1376 struct uart_8250_port *up =
1377 container_of(p, struct uart_8250_port, port);
1378 unsigned int val;
1379
1380 /*
1381 * When the Intel ME (management engine) gets reset its serial
1382 * port registers could return 0 momentarily. Functions like
1383 * serial8250_console_write, read and save the IER, perform
1384 * some operation and then restore it. In order to avoid
1385 * setting IER register inadvertently to 0, if the value read
1386 * is 0, double check with ier value in uart_8250_port and use
1387 * that instead. up->ier should be the same value as what is
1388 * currently configured.
1389 */
1390 val = inb(p->iobase + offset);
1391 if (offset == UART_IER) {
1392 if (val == 0)
1393 val = up->ier;
1394 }
1395 return val;
1396 }
1397
1398 static int kt_serial_setup(struct serial_private *priv,
1399 const struct pciserial_board *board,
1400 struct uart_8250_port *port, int idx)
1401 {
1402 port->port.flags |= UPF_BUG_THRE;
1403 port->port.serial_in = kt_serial_in;
1404 port->port.handle_break = kt_handle_break;
1405 return skip_tx_en_setup(priv, board, port, idx);
1406 }
1407
1408 static int pci_eg20t_init(struct pci_dev *dev)
1409 {
1410 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1411 return -ENODEV;
1412 #else
1413 return 0;
1414 #endif
1415 }
1416
1417 static int
1418 pci_xr17c154_setup(struct serial_private *priv,
1419 const struct pciserial_board *board,
1420 struct uart_8250_port *port, int idx)
1421 {
1422 port->port.flags |= UPF_EXAR_EFR;
1423 return pci_default_setup(priv, board, port, idx);
1424 }
1425
1426 static int
1427 pci_xr17v35x_setup(struct serial_private *priv,
1428 const struct pciserial_board *board,
1429 struct uart_8250_port *port, int idx)
1430 {
1431 u8 __iomem *p;
1432
1433 p = pci_ioremap_bar(priv->dev, 0);
1434 if (p == NULL)
1435 return -ENOMEM;
1436
1437 port->port.flags |= UPF_EXAR_EFR;
1438
1439 /*
1440 * Setup Multipurpose Input/Output pins.
1441 */
1442 if (idx == 0) {
1443 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1444 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1445 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1446 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1447 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1448 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1449 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1450 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1451 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1452 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1453 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1454 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1455 }
1456 writeb(0x00, p + UART_EXAR_8XMODE);
1457 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1458 writeb(128, p + UART_EXAR_TXTRG);
1459 writeb(128, p + UART_EXAR_RXTRG);
1460 iounmap(p);
1461
1462 return pci_default_setup(priv, board, port, idx);
1463 }
1464
1465 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1466 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1467 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1468 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1469
1470 static int
1471 pci_fastcom335_setup(struct serial_private *priv,
1472 const struct pciserial_board *board,
1473 struct uart_8250_port *port, int idx)
1474 {
1475 u8 __iomem *p;
1476
1477 p = pci_ioremap_bar(priv->dev, 0);
1478 if (p == NULL)
1479 return -ENOMEM;
1480
1481 port->port.flags |= UPF_EXAR_EFR;
1482
1483 /*
1484 * Setup Multipurpose Input/Output pins.
1485 */
1486 if (idx == 0) {
1487 switch (priv->dev->device) {
1488 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1489 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1490 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1491 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1492 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1493 break;
1494 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1495 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1496 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1497 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1498 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1499 break;
1500 }
1501 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1502 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1503 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1504 }
1505 writeb(0x00, p + UART_EXAR_8XMODE);
1506 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1507 writeb(32, p + UART_EXAR_TXTRG);
1508 writeb(32, p + UART_EXAR_RXTRG);
1509 iounmap(p);
1510
1511 return pci_default_setup(priv, board, port, idx);
1512 }
1513
1514 static int
1515 pci_wch_ch353_setup(struct serial_private *priv,
1516 const struct pciserial_board *board,
1517 struct uart_8250_port *port, int idx)
1518 {
1519 port->port.flags |= UPF_FIXED_TYPE;
1520 port->port.type = PORT_16550A;
1521 return pci_default_setup(priv, board, port, idx);
1522 }
1523
1524 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1525 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1526 #define PCI_DEVICE_ID_OCTPRO 0x0001
1527 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1528 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1529 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1530 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1531 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1532 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1533 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1534 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1535 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1536 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1537 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1538 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1539 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1540 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1541 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1542 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1543 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1544 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1545 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1546 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1547 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1548 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1549 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1550 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1551 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1552 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1553 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1554 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1555 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1556 #define PCI_VENDOR_ID_WCH 0x4348
1557 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1558 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1559 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1560 #define PCI_VENDOR_ID_AGESTAR 0x5372
1561 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1562 #define PCI_VENDOR_ID_ASIX 0x9710
1563 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1564 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1565 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1566 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1567
1568
1569 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1570 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1571
1572 /*
1573 * Master list of serial port init/setup/exit quirks.
1574 * This does not describe the general nature of the port.
1575 * (ie, baud base, number and location of ports, etc)
1576 *
1577 * This list is ordered alphabetically by vendor then device.
1578 * Specific entries must come before more generic entries.
1579 */
1580 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1581 /*
1582 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1583 */
1584 {
1585 .vendor = PCI_VENDOR_ID_ADDIDATA_OLD,
1586 .device = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1587 .subvendor = PCI_ANY_ID,
1588 .subdevice = PCI_ANY_ID,
1589 .setup = addidata_apci7800_setup,
1590 },
1591 /*
1592 * AFAVLAB cards - these may be called via parport_serial
1593 * It is not clear whether this applies to all products.
1594 */
1595 {
1596 .vendor = PCI_VENDOR_ID_AFAVLAB,
1597 .device = PCI_ANY_ID,
1598 .subvendor = PCI_ANY_ID,
1599 .subdevice = PCI_ANY_ID,
1600 .setup = afavlab_setup,
1601 },
1602 /*
1603 * HP Diva
1604 */
1605 {
1606 .vendor = PCI_VENDOR_ID_HP,
1607 .device = PCI_DEVICE_ID_HP_DIVA,
1608 .subvendor = PCI_ANY_ID,
1609 .subdevice = PCI_ANY_ID,
1610 .init = pci_hp_diva_init,
1611 .setup = pci_hp_diva_setup,
1612 },
1613 /*
1614 * Intel
1615 */
1616 {
1617 .vendor = PCI_VENDOR_ID_INTEL,
1618 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1619 .subvendor = 0xe4bf,
1620 .subdevice = PCI_ANY_ID,
1621 .init = pci_inteli960ni_init,
1622 .setup = pci_default_setup,
1623 },
1624 {
1625 .vendor = PCI_VENDOR_ID_INTEL,
1626 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1627 .subvendor = PCI_ANY_ID,
1628 .subdevice = PCI_ANY_ID,
1629 .setup = skip_tx_en_setup,
1630 },
1631 {
1632 .vendor = PCI_VENDOR_ID_INTEL,
1633 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1634 .subvendor = PCI_ANY_ID,
1635 .subdevice = PCI_ANY_ID,
1636 .setup = skip_tx_en_setup,
1637 },
1638 {
1639 .vendor = PCI_VENDOR_ID_INTEL,
1640 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1641 .subvendor = PCI_ANY_ID,
1642 .subdevice = PCI_ANY_ID,
1643 .setup = skip_tx_en_setup,
1644 },
1645 {
1646 .vendor = PCI_VENDOR_ID_INTEL,
1647 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1648 .subvendor = PCI_ANY_ID,
1649 .subdevice = PCI_ANY_ID,
1650 .setup = ce4100_serial_setup,
1651 },
1652 {
1653 .vendor = PCI_VENDOR_ID_INTEL,
1654 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1655 .subvendor = PCI_ANY_ID,
1656 .subdevice = PCI_ANY_ID,
1657 .setup = kt_serial_setup,
1658 },
1659 /*
1660 * ITE
1661 */
1662 {
1663 .vendor = PCI_VENDOR_ID_ITE,
1664 .device = PCI_DEVICE_ID_ITE_8872,
1665 .subvendor = PCI_ANY_ID,
1666 .subdevice = PCI_ANY_ID,
1667 .init = pci_ite887x_init,
1668 .setup = pci_default_setup,
1669 .exit = pci_ite887x_exit,
1670 },
1671 /*
1672 * National Instruments
1673 */
1674 {
1675 .vendor = PCI_VENDOR_ID_NI,
1676 .device = PCI_DEVICE_ID_NI_PCI23216,
1677 .subvendor = PCI_ANY_ID,
1678 .subdevice = PCI_ANY_ID,
1679 .init = pci_ni8420_init,
1680 .setup = pci_default_setup,
1681 .exit = pci_ni8420_exit,
1682 },
1683 {
1684 .vendor = PCI_VENDOR_ID_NI,
1685 .device = PCI_DEVICE_ID_NI_PCI2328,
1686 .subvendor = PCI_ANY_ID,
1687 .subdevice = PCI_ANY_ID,
1688 .init = pci_ni8420_init,
1689 .setup = pci_default_setup,
1690 .exit = pci_ni8420_exit,
1691 },
1692 {
1693 .vendor = PCI_VENDOR_ID_NI,
1694 .device = PCI_DEVICE_ID_NI_PCI2324,
1695 .subvendor = PCI_ANY_ID,
1696 .subdevice = PCI_ANY_ID,
1697 .init = pci_ni8420_init,
1698 .setup = pci_default_setup,
1699 .exit = pci_ni8420_exit,
1700 },
1701 {
1702 .vendor = PCI_VENDOR_ID_NI,
1703 .device = PCI_DEVICE_ID_NI_PCI2322,
1704 .subvendor = PCI_ANY_ID,
1705 .subdevice = PCI_ANY_ID,
1706 .init = pci_ni8420_init,
1707 .setup = pci_default_setup,
1708 .exit = pci_ni8420_exit,
1709 },
1710 {
1711 .vendor = PCI_VENDOR_ID_NI,
1712 .device = PCI_DEVICE_ID_NI_PCI2324I,
1713 .subvendor = PCI_ANY_ID,
1714 .subdevice = PCI_ANY_ID,
1715 .init = pci_ni8420_init,
1716 .setup = pci_default_setup,
1717 .exit = pci_ni8420_exit,
1718 },
1719 {
1720 .vendor = PCI_VENDOR_ID_NI,
1721 .device = PCI_DEVICE_ID_NI_PCI2322I,
1722 .subvendor = PCI_ANY_ID,
1723 .subdevice = PCI_ANY_ID,
1724 .init = pci_ni8420_init,
1725 .setup = pci_default_setup,
1726 .exit = pci_ni8420_exit,
1727 },
1728 {
1729 .vendor = PCI_VENDOR_ID_NI,
1730 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1731 .subvendor = PCI_ANY_ID,
1732 .subdevice = PCI_ANY_ID,
1733 .init = pci_ni8420_init,
1734 .setup = pci_default_setup,
1735 .exit = pci_ni8420_exit,
1736 },
1737 {
1738 .vendor = PCI_VENDOR_ID_NI,
1739 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1740 .subvendor = PCI_ANY_ID,
1741 .subdevice = PCI_ANY_ID,
1742 .init = pci_ni8420_init,
1743 .setup = pci_default_setup,
1744 .exit = pci_ni8420_exit,
1745 },
1746 {
1747 .vendor = PCI_VENDOR_ID_NI,
1748 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1749 .subvendor = PCI_ANY_ID,
1750 .subdevice = PCI_ANY_ID,
1751 .init = pci_ni8420_init,
1752 .setup = pci_default_setup,
1753 .exit = pci_ni8420_exit,
1754 },
1755 {
1756 .vendor = PCI_VENDOR_ID_NI,
1757 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1758 .subvendor = PCI_ANY_ID,
1759 .subdevice = PCI_ANY_ID,
1760 .init = pci_ni8420_init,
1761 .setup = pci_default_setup,
1762 .exit = pci_ni8420_exit,
1763 },
1764 {
1765 .vendor = PCI_VENDOR_ID_NI,
1766 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1767 .subvendor = PCI_ANY_ID,
1768 .subdevice = PCI_ANY_ID,
1769 .init = pci_ni8420_init,
1770 .setup = pci_default_setup,
1771 .exit = pci_ni8420_exit,
1772 },
1773 {
1774 .vendor = PCI_VENDOR_ID_NI,
1775 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1776 .subvendor = PCI_ANY_ID,
1777 .subdevice = PCI_ANY_ID,
1778 .init = pci_ni8420_init,
1779 .setup = pci_default_setup,
1780 .exit = pci_ni8420_exit,
1781 },
1782 {
1783 .vendor = PCI_VENDOR_ID_NI,
1784 .device = PCI_ANY_ID,
1785 .subvendor = PCI_ANY_ID,
1786 .subdevice = PCI_ANY_ID,
1787 .init = pci_ni8430_init,
1788 .setup = pci_ni8430_setup,
1789 .exit = pci_ni8430_exit,
1790 },
1791 /* Quatech */
1792 {
1793 .vendor = PCI_VENDOR_ID_QUATECH,
1794 .device = PCI_ANY_ID,
1795 .subvendor = PCI_ANY_ID,
1796 .subdevice = PCI_ANY_ID,
1797 .init = pci_quatech_init,
1798 .setup = pci_quatech_setup,
1799 .exit = pci_quatech_exit,
1800 },
1801 /*
1802 * Panacom
1803 */
1804 {
1805 .vendor = PCI_VENDOR_ID_PANACOM,
1806 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1807 .subvendor = PCI_ANY_ID,
1808 .subdevice = PCI_ANY_ID,
1809 .init = pci_plx9050_init,
1810 .setup = pci_default_setup,
1811 .exit = pci_plx9050_exit,
1812 },
1813 {
1814 .vendor = PCI_VENDOR_ID_PANACOM,
1815 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1816 .subvendor = PCI_ANY_ID,
1817 .subdevice = PCI_ANY_ID,
1818 .init = pci_plx9050_init,
1819 .setup = pci_default_setup,
1820 .exit = pci_plx9050_exit,
1821 },
1822 /*
1823 * PLX
1824 */
1825 {
1826 .vendor = PCI_VENDOR_ID_PLX,
1827 .device = PCI_DEVICE_ID_PLX_9030,
1828 .subvendor = PCI_SUBVENDOR_ID_PERLE,
1829 .subdevice = PCI_ANY_ID,
1830 .setup = pci_default_setup,
1831 },
1832 {
1833 .vendor = PCI_VENDOR_ID_PLX,
1834 .device = PCI_DEVICE_ID_PLX_9050,
1835 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
1836 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
1837 .init = pci_plx9050_init,
1838 .setup = pci_default_setup,
1839 .exit = pci_plx9050_exit,
1840 },
1841 {
1842 .vendor = PCI_VENDOR_ID_PLX,
1843 .device = PCI_DEVICE_ID_PLX_9050,
1844 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
1845 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1846 .init = pci_plx9050_init,
1847 .setup = pci_default_setup,
1848 .exit = pci_plx9050_exit,
1849 },
1850 {
1851 .vendor = PCI_VENDOR_ID_PLX,
1852 .device = PCI_DEVICE_ID_PLX_9050,
1853 .subvendor = PCI_VENDOR_ID_PLX,
1854 .subdevice = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1855 .init = pci_plx9050_init,
1856 .setup = pci_default_setup,
1857 .exit = pci_plx9050_exit,
1858 },
1859 {
1860 .vendor = PCI_VENDOR_ID_PLX,
1861 .device = PCI_DEVICE_ID_PLX_ROMULUS,
1862 .subvendor = PCI_VENDOR_ID_PLX,
1863 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
1864 .init = pci_plx9050_init,
1865 .setup = pci_default_setup,
1866 .exit = pci_plx9050_exit,
1867 },
1868 /*
1869 * SBS Technologies, Inc., PMC-OCTALPRO 232
1870 */
1871 {
1872 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1873 .device = PCI_DEVICE_ID_OCTPRO,
1874 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1875 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
1876 .init = sbs_init,
1877 .setup = sbs_setup,
1878 .exit = sbs_exit,
1879 },
1880 /*
1881 * SBS Technologies, Inc., PMC-OCTALPRO 422
1882 */
1883 {
1884 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1885 .device = PCI_DEVICE_ID_OCTPRO,
1886 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1887 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
1888 .init = sbs_init,
1889 .setup = sbs_setup,
1890 .exit = sbs_exit,
1891 },
1892 /*
1893 * SBS Technologies, Inc., P-Octal 232
1894 */
1895 {
1896 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1897 .device = PCI_DEVICE_ID_OCTPRO,
1898 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1899 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
1900 .init = sbs_init,
1901 .setup = sbs_setup,
1902 .exit = sbs_exit,
1903 },
1904 /*
1905 * SBS Technologies, Inc., P-Octal 422
1906 */
1907 {
1908 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
1909 .device = PCI_DEVICE_ID_OCTPRO,
1910 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
1911 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
1912 .init = sbs_init,
1913 .setup = sbs_setup,
1914 .exit = sbs_exit,
1915 },
1916 /*
1917 * SIIG cards - these may be called via parport_serial
1918 */
1919 {
1920 .vendor = PCI_VENDOR_ID_SIIG,
1921 .device = PCI_ANY_ID,
1922 .subvendor = PCI_ANY_ID,
1923 .subdevice = PCI_ANY_ID,
1924 .init = pci_siig_init,
1925 .setup = pci_siig_setup,
1926 },
1927 /*
1928 * Titan cards
1929 */
1930 {
1931 .vendor = PCI_VENDOR_ID_TITAN,
1932 .device = PCI_DEVICE_ID_TITAN_400L,
1933 .subvendor = PCI_ANY_ID,
1934 .subdevice = PCI_ANY_ID,
1935 .setup = titan_400l_800l_setup,
1936 },
1937 {
1938 .vendor = PCI_VENDOR_ID_TITAN,
1939 .device = PCI_DEVICE_ID_TITAN_800L,
1940 .subvendor = PCI_ANY_ID,
1941 .subdevice = PCI_ANY_ID,
1942 .setup = titan_400l_800l_setup,
1943 },
1944 /*
1945 * Timedia cards
1946 */
1947 {
1948 .vendor = PCI_VENDOR_ID_TIMEDIA,
1949 .device = PCI_DEVICE_ID_TIMEDIA_1889,
1950 .subvendor = PCI_VENDOR_ID_TIMEDIA,
1951 .subdevice = PCI_ANY_ID,
1952 .probe = pci_timedia_probe,
1953 .init = pci_timedia_init,
1954 .setup = pci_timedia_setup,
1955 },
1956 {
1957 .vendor = PCI_VENDOR_ID_TIMEDIA,
1958 .device = PCI_ANY_ID,
1959 .subvendor = PCI_ANY_ID,
1960 .subdevice = PCI_ANY_ID,
1961 .setup = pci_timedia_setup,
1962 },
1963 /*
1964 * Exar cards
1965 */
1966 {
1967 .vendor = PCI_VENDOR_ID_EXAR,
1968 .device = PCI_DEVICE_ID_EXAR_XR17C152,
1969 .subvendor = PCI_ANY_ID,
1970 .subdevice = PCI_ANY_ID,
1971 .setup = pci_xr17c154_setup,
1972 },
1973 {
1974 .vendor = PCI_VENDOR_ID_EXAR,
1975 .device = PCI_DEVICE_ID_EXAR_XR17C154,
1976 .subvendor = PCI_ANY_ID,
1977 .subdevice = PCI_ANY_ID,
1978 .setup = pci_xr17c154_setup,
1979 },
1980 {
1981 .vendor = PCI_VENDOR_ID_EXAR,
1982 .device = PCI_DEVICE_ID_EXAR_XR17C158,
1983 .subvendor = PCI_ANY_ID,
1984 .subdevice = PCI_ANY_ID,
1985 .setup = pci_xr17c154_setup,
1986 },
1987 {
1988 .vendor = PCI_VENDOR_ID_EXAR,
1989 .device = PCI_DEVICE_ID_EXAR_XR17V352,
1990 .subvendor = PCI_ANY_ID,
1991 .subdevice = PCI_ANY_ID,
1992 .setup = pci_xr17v35x_setup,
1993 },
1994 {
1995 .vendor = PCI_VENDOR_ID_EXAR,
1996 .device = PCI_DEVICE_ID_EXAR_XR17V354,
1997 .subvendor = PCI_ANY_ID,
1998 .subdevice = PCI_ANY_ID,
1999 .setup = pci_xr17v35x_setup,
2000 },
2001 {
2002 .vendor = PCI_VENDOR_ID_EXAR,
2003 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2004 .subvendor = PCI_ANY_ID,
2005 .subdevice = PCI_ANY_ID,
2006 .setup = pci_xr17v35x_setup,
2007 },
2008 /*
2009 * Xircom cards
2010 */
2011 {
2012 .vendor = PCI_VENDOR_ID_XIRCOM,
2013 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2014 .subvendor = PCI_ANY_ID,
2015 .subdevice = PCI_ANY_ID,
2016 .init = pci_xircom_init,
2017 .setup = pci_default_setup,
2018 },
2019 /*
2020 * Netmos cards - these may be called via parport_serial
2021 */
2022 {
2023 .vendor = PCI_VENDOR_ID_NETMOS,
2024 .device = PCI_ANY_ID,
2025 .subvendor = PCI_ANY_ID,
2026 .subdevice = PCI_ANY_ID,
2027 .init = pci_netmos_init,
2028 .setup = pci_netmos_9900_setup,
2029 },
2030 /*
2031 * For Oxford Semiconductor Tornado based devices
2032 */
2033 {
2034 .vendor = PCI_VENDOR_ID_OXSEMI,
2035 .device = PCI_ANY_ID,
2036 .subvendor = PCI_ANY_ID,
2037 .subdevice = PCI_ANY_ID,
2038 .init = pci_oxsemi_tornado_init,
2039 .setup = pci_default_setup,
2040 },
2041 {
2042 .vendor = PCI_VENDOR_ID_MAINPINE,
2043 .device = PCI_ANY_ID,
2044 .subvendor = PCI_ANY_ID,
2045 .subdevice = PCI_ANY_ID,
2046 .init = pci_oxsemi_tornado_init,
2047 .setup = pci_default_setup,
2048 },
2049 {
2050 .vendor = PCI_VENDOR_ID_DIGI,
2051 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2052 .subvendor = PCI_SUBVENDOR_ID_IBM,
2053 .subdevice = PCI_ANY_ID,
2054 .init = pci_oxsemi_tornado_init,
2055 .setup = pci_default_setup,
2056 },
2057 {
2058 .vendor = PCI_VENDOR_ID_INTEL,
2059 .device = 0x8811,
2060 .subvendor = PCI_ANY_ID,
2061 .subdevice = PCI_ANY_ID,
2062 .init = pci_eg20t_init,
2063 .setup = pci_default_setup,
2064 },
2065 {
2066 .vendor = PCI_VENDOR_ID_INTEL,
2067 .device = 0x8812,
2068 .subvendor = PCI_ANY_ID,
2069 .subdevice = PCI_ANY_ID,
2070 .init = pci_eg20t_init,
2071 .setup = pci_default_setup,
2072 },
2073 {
2074 .vendor = PCI_VENDOR_ID_INTEL,
2075 .device = 0x8813,
2076 .subvendor = PCI_ANY_ID,
2077 .subdevice = PCI_ANY_ID,
2078 .init = pci_eg20t_init,
2079 .setup = pci_default_setup,
2080 },
2081 {
2082 .vendor = PCI_VENDOR_ID_INTEL,
2083 .device = 0x8814,
2084 .subvendor = PCI_ANY_ID,
2085 .subdevice = PCI_ANY_ID,
2086 .init = pci_eg20t_init,
2087 .setup = pci_default_setup,
2088 },
2089 {
2090 .vendor = 0x10DB,
2091 .device = 0x8027,
2092 .subvendor = PCI_ANY_ID,
2093 .subdevice = PCI_ANY_ID,
2094 .init = pci_eg20t_init,
2095 .setup = pci_default_setup,
2096 },
2097 {
2098 .vendor = 0x10DB,
2099 .device = 0x8028,
2100 .subvendor = PCI_ANY_ID,
2101 .subdevice = PCI_ANY_ID,
2102 .init = pci_eg20t_init,
2103 .setup = pci_default_setup,
2104 },
2105 {
2106 .vendor = 0x10DB,
2107 .device = 0x8029,
2108 .subvendor = PCI_ANY_ID,
2109 .subdevice = PCI_ANY_ID,
2110 .init = pci_eg20t_init,
2111 .setup = pci_default_setup,
2112 },
2113 {
2114 .vendor = 0x10DB,
2115 .device = 0x800C,
2116 .subvendor = PCI_ANY_ID,
2117 .subdevice = PCI_ANY_ID,
2118 .init = pci_eg20t_init,
2119 .setup = pci_default_setup,
2120 },
2121 {
2122 .vendor = 0x10DB,
2123 .device = 0x800D,
2124 .subvendor = PCI_ANY_ID,
2125 .subdevice = PCI_ANY_ID,
2126 .init = pci_eg20t_init,
2127 .setup = pci_default_setup,
2128 },
2129 /*
2130 * Cronyx Omega PCI (PLX-chip based)
2131 */
2132 {
2133 .vendor = PCI_VENDOR_ID_PLX,
2134 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2135 .subvendor = PCI_ANY_ID,
2136 .subdevice = PCI_ANY_ID,
2137 .setup = pci_omegapci_setup,
2138 },
2139 /* WCH CH353 2S1P card (16550 clone) */
2140 {
2141 .vendor = PCI_VENDOR_ID_WCH,
2142 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2143 .subvendor = PCI_ANY_ID,
2144 .subdevice = PCI_ANY_ID,
2145 .setup = pci_wch_ch353_setup,
2146 },
2147 /* WCH CH353 4S card (16550 clone) */
2148 {
2149 .vendor = PCI_VENDOR_ID_WCH,
2150 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2151 .subvendor = PCI_ANY_ID,
2152 .subdevice = PCI_ANY_ID,
2153 .setup = pci_wch_ch353_setup,
2154 },
2155 /* WCH CH353 2S1PF card (16550 clone) */
2156 {
2157 .vendor = PCI_VENDOR_ID_WCH,
2158 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2159 .subvendor = PCI_ANY_ID,
2160 .subdevice = PCI_ANY_ID,
2161 .setup = pci_wch_ch353_setup,
2162 },
2163 /*
2164 * ASIX devices with FIFO bug
2165 */
2166 {
2167 .vendor = PCI_VENDOR_ID_ASIX,
2168 .device = PCI_ANY_ID,
2169 .subvendor = PCI_ANY_ID,
2170 .subdevice = PCI_ANY_ID,
2171 .setup = pci_asix_setup,
2172 },
2173 /*
2174 * Commtech, Inc. Fastcom adapters
2175 *
2176 */
2177 {
2178 .vendor = PCI_VENDOR_ID_COMMTECH,
2179 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2180 .subvendor = PCI_ANY_ID,
2181 .subdevice = PCI_ANY_ID,
2182 .setup = pci_fastcom335_setup,
2183 },
2184 {
2185 .vendor = PCI_VENDOR_ID_COMMTECH,
2186 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2187 .subvendor = PCI_ANY_ID,
2188 .subdevice = PCI_ANY_ID,
2189 .setup = pci_fastcom335_setup,
2190 },
2191 {
2192 .vendor = PCI_VENDOR_ID_COMMTECH,
2193 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2194 .subvendor = PCI_ANY_ID,
2195 .subdevice = PCI_ANY_ID,
2196 .setup = pci_fastcom335_setup,
2197 },
2198 {
2199 .vendor = PCI_VENDOR_ID_COMMTECH,
2200 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2201 .subvendor = PCI_ANY_ID,
2202 .subdevice = PCI_ANY_ID,
2203 .setup = pci_fastcom335_setup,
2204 },
2205 {
2206 .vendor = PCI_VENDOR_ID_COMMTECH,
2207 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2208 .subvendor = PCI_ANY_ID,
2209 .subdevice = PCI_ANY_ID,
2210 .setup = pci_xr17v35x_setup,
2211 },
2212 {
2213 .vendor = PCI_VENDOR_ID_COMMTECH,
2214 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2215 .subvendor = PCI_ANY_ID,
2216 .subdevice = PCI_ANY_ID,
2217 .setup = pci_xr17v35x_setup,
2218 },
2219 {
2220 .vendor = PCI_VENDOR_ID_COMMTECH,
2221 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2222 .subvendor = PCI_ANY_ID,
2223 .subdevice = PCI_ANY_ID,
2224 .setup = pci_xr17v35x_setup,
2225 },
2226 /*
2227 * Broadcom TruManage (NetXtreme)
2228 */
2229 {
2230 .vendor = PCI_VENDOR_ID_BROADCOM,
2231 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2232 .subvendor = PCI_ANY_ID,
2233 .subdevice = PCI_ANY_ID,
2234 .setup = pci_brcm_trumanage_setup,
2235 },
2236
2237 /*
2238 * Default "match everything" terminator entry
2239 */
2240 {
2241 .vendor = PCI_ANY_ID,
2242 .device = PCI_ANY_ID,
2243 .subvendor = PCI_ANY_ID,
2244 .subdevice = PCI_ANY_ID,
2245 .setup = pci_default_setup,
2246 }
2247 };
2248
2249 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2250 {
2251 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2252 }
2253
2254 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2255 {
2256 struct pci_serial_quirk *quirk;
2257
2258 for (quirk = pci_serial_quirks; ; quirk++)
2259 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2260 quirk_id_matches(quirk->device, dev->device) &&
2261 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2262 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2263 break;
2264 return quirk;
2265 }
2266
2267 static inline int get_pci_irq(struct pci_dev *dev,
2268 const struct pciserial_board *board)
2269 {
2270 if (board->flags & FL_NOIRQ)
2271 return 0;
2272 else
2273 return dev->irq;
2274 }
2275
2276 /*
2277 * This is the configuration table for all of the PCI serial boards
2278 * which we support. It is directly indexed by the pci_board_num_t enum
2279 * value, which is encoded in the pci_device_id PCI probe table's
2280 * driver_data member.
2281 *
2282 * The makeup of these names are:
2283 * pbn_bn{_bt}_n_baud{_offsetinhex}
2284 *
2285 * bn = PCI BAR number
2286 * bt = Index using PCI BARs
2287 * n = number of serial ports
2288 * baud = baud rate
2289 * offsetinhex = offset for each sequential port (in hex)
2290 *
2291 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2292 *
2293 * Please note: in theory if n = 1, _bt infix should make no difference.
2294 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2295 */
2296 enum pci_board_num_t {
2297 pbn_default = 0,
2298
2299 pbn_b0_1_115200,
2300 pbn_b0_2_115200,
2301 pbn_b0_4_115200,
2302 pbn_b0_5_115200,
2303 pbn_b0_8_115200,
2304
2305 pbn_b0_1_921600,
2306 pbn_b0_2_921600,
2307 pbn_b0_4_921600,
2308
2309 pbn_b0_2_1130000,
2310
2311 pbn_b0_4_1152000,
2312
2313 pbn_b0_2_1152000_200,
2314 pbn_b0_4_1152000_200,
2315 pbn_b0_8_1152000_200,
2316
2317 pbn_b0_2_1843200,
2318 pbn_b0_4_1843200,
2319
2320 pbn_b0_2_1843200_200,
2321 pbn_b0_4_1843200_200,
2322 pbn_b0_8_1843200_200,
2323
2324 pbn_b0_1_4000000,
2325
2326 pbn_b0_bt_1_115200,
2327 pbn_b0_bt_2_115200,
2328 pbn_b0_bt_4_115200,
2329 pbn_b0_bt_8_115200,
2330
2331 pbn_b0_bt_1_460800,
2332 pbn_b0_bt_2_460800,
2333 pbn_b0_bt_4_460800,
2334
2335 pbn_b0_bt_1_921600,
2336 pbn_b0_bt_2_921600,
2337 pbn_b0_bt_4_921600,
2338 pbn_b0_bt_8_921600,
2339
2340 pbn_b1_1_115200,
2341 pbn_b1_2_115200,
2342 pbn_b1_4_115200,
2343 pbn_b1_8_115200,
2344 pbn_b1_16_115200,
2345
2346 pbn_b1_1_921600,
2347 pbn_b1_2_921600,
2348 pbn_b1_4_921600,
2349 pbn_b1_8_921600,
2350
2351 pbn_b1_2_1250000,
2352
2353 pbn_b1_bt_1_115200,
2354 pbn_b1_bt_2_115200,
2355 pbn_b1_bt_4_115200,
2356
2357 pbn_b1_bt_2_921600,
2358
2359 pbn_b1_1_1382400,
2360 pbn_b1_2_1382400,
2361 pbn_b1_4_1382400,
2362 pbn_b1_8_1382400,
2363
2364 pbn_b2_1_115200,
2365 pbn_b2_2_115200,
2366 pbn_b2_4_115200,
2367 pbn_b2_8_115200,
2368
2369 pbn_b2_1_460800,
2370 pbn_b2_4_460800,
2371 pbn_b2_8_460800,
2372 pbn_b2_16_460800,
2373
2374 pbn_b2_1_921600,
2375 pbn_b2_4_921600,
2376 pbn_b2_8_921600,
2377
2378 pbn_b2_8_1152000,
2379
2380 pbn_b2_bt_1_115200,
2381 pbn_b2_bt_2_115200,
2382 pbn_b2_bt_4_115200,
2383
2384 pbn_b2_bt_2_921600,
2385 pbn_b2_bt_4_921600,
2386
2387 pbn_b3_2_115200,
2388 pbn_b3_4_115200,
2389 pbn_b3_8_115200,
2390
2391 pbn_b4_bt_2_921600,
2392 pbn_b4_bt_4_921600,
2393 pbn_b4_bt_8_921600,
2394
2395 /*
2396 * Board-specific versions.
2397 */
2398 pbn_panacom,
2399 pbn_panacom2,
2400 pbn_panacom4,
2401 pbn_plx_romulus,
2402 pbn_oxsemi,
2403 pbn_oxsemi_1_4000000,
2404 pbn_oxsemi_2_4000000,
2405 pbn_oxsemi_4_4000000,
2406 pbn_oxsemi_8_4000000,
2407 pbn_intel_i960,
2408 pbn_sgi_ioc3,
2409 pbn_computone_4,
2410 pbn_computone_6,
2411 pbn_computone_8,
2412 pbn_sbsxrsio,
2413 pbn_exar_XR17C152,
2414 pbn_exar_XR17C154,
2415 pbn_exar_XR17C158,
2416 pbn_exar_XR17V352,
2417 pbn_exar_XR17V354,
2418 pbn_exar_XR17V358,
2419 pbn_exar_ibm_saturn,
2420 pbn_pasemi_1682M,
2421 pbn_ni8430_2,
2422 pbn_ni8430_4,
2423 pbn_ni8430_8,
2424 pbn_ni8430_16,
2425 pbn_ADDIDATA_PCIe_1_3906250,
2426 pbn_ADDIDATA_PCIe_2_3906250,
2427 pbn_ADDIDATA_PCIe_4_3906250,
2428 pbn_ADDIDATA_PCIe_8_3906250,
2429 pbn_ce4100_1_115200,
2430 pbn_omegapci,
2431 pbn_NETMOS9900_2s_115200,
2432 pbn_brcm_trumanage,
2433 };
2434
2435 /*
2436 * uart_offset - the space between channels
2437 * reg_shift - describes how the UART registers are mapped
2438 * to PCI memory by the card.
2439 * For example IER register on SBS, Inc. PMC-OctPro is located at
2440 * offset 0x10 from the UART base, while UART_IER is defined as 1
2441 * in include/linux/serial_reg.h,
2442 * see first lines of serial_in() and serial_out() in 8250.c
2443 */
2444
2445 static struct pciserial_board pci_boards[] = {
2446 [pbn_default] = {
2447 .flags = FL_BASE0,
2448 .num_ports = 1,
2449 .base_baud = 115200,
2450 .uart_offset = 8,
2451 },
2452 [pbn_b0_1_115200] = {
2453 .flags = FL_BASE0,
2454 .num_ports = 1,
2455 .base_baud = 115200,
2456 .uart_offset = 8,
2457 },
2458 [pbn_b0_2_115200] = {
2459 .flags = FL_BASE0,
2460 .num_ports = 2,
2461 .base_baud = 115200,
2462 .uart_offset = 8,
2463 },
2464 [pbn_b0_4_115200] = {
2465 .flags = FL_BASE0,
2466 .num_ports = 4,
2467 .base_baud = 115200,
2468 .uart_offset = 8,
2469 },
2470 [pbn_b0_5_115200] = {
2471 .flags = FL_BASE0,
2472 .num_ports = 5,
2473 .base_baud = 115200,
2474 .uart_offset = 8,
2475 },
2476 [pbn_b0_8_115200] = {
2477 .flags = FL_BASE0,
2478 .num_ports = 8,
2479 .base_baud = 115200,
2480 .uart_offset = 8,
2481 },
2482 [pbn_b0_1_921600] = {
2483 .flags = FL_BASE0,
2484 .num_ports = 1,
2485 .base_baud = 921600,
2486 .uart_offset = 8,
2487 },
2488 [pbn_b0_2_921600] = {
2489 .flags = FL_BASE0,
2490 .num_ports = 2,
2491 .base_baud = 921600,
2492 .uart_offset = 8,
2493 },
2494 [pbn_b0_4_921600] = {
2495 .flags = FL_BASE0,
2496 .num_ports = 4,
2497 .base_baud = 921600,
2498 .uart_offset = 8,
2499 },
2500
2501 [pbn_b0_2_1130000] = {
2502 .flags = FL_BASE0,
2503 .num_ports = 2,
2504 .base_baud = 1130000,
2505 .uart_offset = 8,
2506 },
2507
2508 [pbn_b0_4_1152000] = {
2509 .flags = FL_BASE0,
2510 .num_ports = 4,
2511 .base_baud = 1152000,
2512 .uart_offset = 8,
2513 },
2514
2515 [pbn_b0_2_1152000_200] = {
2516 .flags = FL_BASE0,
2517 .num_ports = 2,
2518 .base_baud = 1152000,
2519 .uart_offset = 0x200,
2520 },
2521
2522 [pbn_b0_4_1152000_200] = {
2523 .flags = FL_BASE0,
2524 .num_ports = 4,
2525 .base_baud = 1152000,
2526 .uart_offset = 0x200,
2527 },
2528
2529 [pbn_b0_8_1152000_200] = {
2530 .flags = FL_BASE0,
2531 .num_ports = 8,
2532 .base_baud = 1152000,
2533 .uart_offset = 0x200,
2534 },
2535
2536 [pbn_b0_2_1843200] = {
2537 .flags = FL_BASE0,
2538 .num_ports = 2,
2539 .base_baud = 1843200,
2540 .uart_offset = 8,
2541 },
2542 [pbn_b0_4_1843200] = {
2543 .flags = FL_BASE0,
2544 .num_ports = 4,
2545 .base_baud = 1843200,
2546 .uart_offset = 8,
2547 },
2548
2549 [pbn_b0_2_1843200_200] = {
2550 .flags = FL_BASE0,
2551 .num_ports = 2,
2552 .base_baud = 1843200,
2553 .uart_offset = 0x200,
2554 },
2555 [pbn_b0_4_1843200_200] = {
2556 .flags = FL_BASE0,
2557 .num_ports = 4,
2558 .base_baud = 1843200,
2559 .uart_offset = 0x200,
2560 },
2561 [pbn_b0_8_1843200_200] = {
2562 .flags = FL_BASE0,
2563 .num_ports = 8,
2564 .base_baud = 1843200,
2565 .uart_offset = 0x200,
2566 },
2567 [pbn_b0_1_4000000] = {
2568 .flags = FL_BASE0,
2569 .num_ports = 1,
2570 .base_baud = 4000000,
2571 .uart_offset = 8,
2572 },
2573
2574 [pbn_b0_bt_1_115200] = {
2575 .flags = FL_BASE0|FL_BASE_BARS,
2576 .num_ports = 1,
2577 .base_baud = 115200,
2578 .uart_offset = 8,
2579 },
2580 [pbn_b0_bt_2_115200] = {
2581 .flags = FL_BASE0|FL_BASE_BARS,
2582 .num_ports = 2,
2583 .base_baud = 115200,
2584 .uart_offset = 8,
2585 },
2586 [pbn_b0_bt_4_115200] = {
2587 .flags = FL_BASE0|FL_BASE_BARS,
2588 .num_ports = 4,
2589 .base_baud = 115200,
2590 .uart_offset = 8,
2591 },
2592 [pbn_b0_bt_8_115200] = {
2593 .flags = FL_BASE0|FL_BASE_BARS,
2594 .num_ports = 8,
2595 .base_baud = 115200,
2596 .uart_offset = 8,
2597 },
2598
2599 [pbn_b0_bt_1_460800] = {
2600 .flags = FL_BASE0|FL_BASE_BARS,
2601 .num_ports = 1,
2602 .base_baud = 460800,
2603 .uart_offset = 8,
2604 },
2605 [pbn_b0_bt_2_460800] = {
2606 .flags = FL_BASE0|FL_BASE_BARS,
2607 .num_ports = 2,
2608 .base_baud = 460800,
2609 .uart_offset = 8,
2610 },
2611 [pbn_b0_bt_4_460800] = {
2612 .flags = FL_BASE0|FL_BASE_BARS,
2613 .num_ports = 4,
2614 .base_baud = 460800,
2615 .uart_offset = 8,
2616 },
2617
2618 [pbn_b0_bt_1_921600] = {
2619 .flags = FL_BASE0|FL_BASE_BARS,
2620 .num_ports = 1,
2621 .base_baud = 921600,
2622 .uart_offset = 8,
2623 },
2624 [pbn_b0_bt_2_921600] = {
2625 .flags = FL_BASE0|FL_BASE_BARS,
2626 .num_ports = 2,
2627 .base_baud = 921600,
2628 .uart_offset = 8,
2629 },
2630 [pbn_b0_bt_4_921600] = {
2631 .flags = FL_BASE0|FL_BASE_BARS,
2632 .num_ports = 4,
2633 .base_baud = 921600,
2634 .uart_offset = 8,
2635 },
2636 [pbn_b0_bt_8_921600] = {
2637 .flags = FL_BASE0|FL_BASE_BARS,
2638 .num_ports = 8,
2639 .base_baud = 921600,
2640 .uart_offset = 8,
2641 },
2642
2643 [pbn_b1_1_115200] = {
2644 .flags = FL_BASE1,
2645 .num_ports = 1,
2646 .base_baud = 115200,
2647 .uart_offset = 8,
2648 },
2649 [pbn_b1_2_115200] = {
2650 .flags = FL_BASE1,
2651 .num_ports = 2,
2652 .base_baud = 115200,
2653 .uart_offset = 8,
2654 },
2655 [pbn_b1_4_115200] = {
2656 .flags = FL_BASE1,
2657 .num_ports = 4,
2658 .base_baud = 115200,
2659 .uart_offset = 8,
2660 },
2661 [pbn_b1_8_115200] = {
2662 .flags = FL_BASE1,
2663 .num_ports = 8,
2664 .base_baud = 115200,
2665 .uart_offset = 8,
2666 },
2667 [pbn_b1_16_115200] = {
2668 .flags = FL_BASE1,
2669 .num_ports = 16,
2670 .base_baud = 115200,
2671 .uart_offset = 8,
2672 },
2673
2674 [pbn_b1_1_921600] = {
2675 .flags = FL_BASE1,
2676 .num_ports = 1,
2677 .base_baud = 921600,
2678 .uart_offset = 8,
2679 },
2680 [pbn_b1_2_921600] = {
2681 .flags = FL_BASE1,
2682 .num_ports = 2,
2683 .base_baud = 921600,
2684 .uart_offset = 8,
2685 },
2686 [pbn_b1_4_921600] = {
2687 .flags = FL_BASE1,
2688 .num_ports = 4,
2689 .base_baud = 921600,
2690 .uart_offset = 8,
2691 },
2692 [pbn_b1_8_921600] = {
2693 .flags = FL_BASE1,
2694 .num_ports = 8,
2695 .base_baud = 921600,
2696 .uart_offset = 8,
2697 },
2698 [pbn_b1_2_1250000] = {
2699 .flags = FL_BASE1,
2700 .num_ports = 2,
2701 .base_baud = 1250000,
2702 .uart_offset = 8,
2703 },
2704
2705 [pbn_b1_bt_1_115200] = {
2706 .flags = FL_BASE1|FL_BASE_BARS,
2707 .num_ports = 1,
2708 .base_baud = 115200,
2709 .uart_offset = 8,
2710 },
2711 [pbn_b1_bt_2_115200] = {
2712 .flags = FL_BASE1|FL_BASE_BARS,
2713 .num_ports = 2,
2714 .base_baud = 115200,
2715 .uart_offset = 8,
2716 },
2717 [pbn_b1_bt_4_115200] = {
2718 .flags = FL_BASE1|FL_BASE_BARS,
2719 .num_ports = 4,
2720 .base_baud = 115200,
2721 .uart_offset = 8,
2722 },
2723
2724 [pbn_b1_bt_2_921600] = {
2725 .flags = FL_BASE1|FL_BASE_BARS,
2726 .num_ports = 2,
2727 .base_baud = 921600,
2728 .uart_offset = 8,
2729 },
2730
2731 [pbn_b1_1_1382400] = {
2732 .flags = FL_BASE1,
2733 .num_ports = 1,
2734 .base_baud = 1382400,
2735 .uart_offset = 8,
2736 },
2737 [pbn_b1_2_1382400] = {
2738 .flags = FL_BASE1,
2739 .num_ports = 2,
2740 .base_baud = 1382400,
2741 .uart_offset = 8,
2742 },
2743 [pbn_b1_4_1382400] = {
2744 .flags = FL_BASE1,
2745 .num_ports = 4,
2746 .base_baud = 1382400,
2747 .uart_offset = 8,
2748 },
2749 [pbn_b1_8_1382400] = {
2750 .flags = FL_BASE1,
2751 .num_ports = 8,
2752 .base_baud = 1382400,
2753 .uart_offset = 8,
2754 },
2755
2756 [pbn_b2_1_115200] = {
2757 .flags = FL_BASE2,
2758 .num_ports = 1,
2759 .base_baud = 115200,
2760 .uart_offset = 8,
2761 },
2762 [pbn_b2_2_115200] = {
2763 .flags = FL_BASE2,
2764 .num_ports = 2,
2765 .base_baud = 115200,
2766 .uart_offset = 8,
2767 },
2768 [pbn_b2_4_115200] = {
2769 .flags = FL_BASE2,
2770 .num_ports = 4,
2771 .base_baud = 115200,
2772 .uart_offset = 8,
2773 },
2774 [pbn_b2_8_115200] = {
2775 .flags = FL_BASE2,
2776 .num_ports = 8,
2777 .base_baud = 115200,
2778 .uart_offset = 8,
2779 },
2780
2781 [pbn_b2_1_460800] = {
2782 .flags = FL_BASE2,
2783 .num_ports = 1,
2784 .base_baud = 460800,
2785 .uart_offset = 8,
2786 },
2787 [pbn_b2_4_460800] = {
2788 .flags = FL_BASE2,
2789 .num_ports = 4,
2790 .base_baud = 460800,
2791 .uart_offset = 8,
2792 },
2793 [pbn_b2_8_460800] = {
2794 .flags = FL_BASE2,
2795 .num_ports = 8,
2796 .base_baud = 460800,
2797 .uart_offset = 8,
2798 },
2799 [pbn_b2_16_460800] = {
2800 .flags = FL_BASE2,
2801 .num_ports = 16,
2802 .base_baud = 460800,
2803 .uart_offset = 8,
2804 },
2805
2806 [pbn_b2_1_921600] = {
2807 .flags = FL_BASE2,
2808 .num_ports = 1,
2809 .base_baud = 921600,
2810 .uart_offset = 8,
2811 },
2812 [pbn_b2_4_921600] = {
2813 .flags = FL_BASE2,
2814 .num_ports = 4,
2815 .base_baud = 921600,
2816 .uart_offset = 8,
2817 },
2818 [pbn_b2_8_921600] = {
2819 .flags = FL_BASE2,
2820 .num_ports = 8,
2821 .base_baud = 921600,
2822 .uart_offset = 8,
2823 },
2824
2825 [pbn_b2_8_1152000] = {
2826 .flags = FL_BASE2,
2827 .num_ports = 8,
2828 .base_baud = 1152000,
2829 .uart_offset = 8,
2830 },
2831
2832 [pbn_b2_bt_1_115200] = {
2833 .flags = FL_BASE2|FL_BASE_BARS,
2834 .num_ports = 1,
2835 .base_baud = 115200,
2836 .uart_offset = 8,
2837 },
2838 [pbn_b2_bt_2_115200] = {
2839 .flags = FL_BASE2|FL_BASE_BARS,
2840 .num_ports = 2,
2841 .base_baud = 115200,
2842 .uart_offset = 8,
2843 },
2844 [pbn_b2_bt_4_115200] = {
2845 .flags = FL_BASE2|FL_BASE_BARS,
2846 .num_ports = 4,
2847 .base_baud = 115200,
2848 .uart_offset = 8,
2849 },
2850
2851 [pbn_b2_bt_2_921600] = {
2852 .flags = FL_BASE2|FL_BASE_BARS,
2853 .num_ports = 2,
2854 .base_baud = 921600,
2855 .uart_offset = 8,
2856 },
2857 [pbn_b2_bt_4_921600] = {
2858 .flags = FL_BASE2|FL_BASE_BARS,
2859 .num_ports = 4,
2860 .base_baud = 921600,
2861 .uart_offset = 8,
2862 },
2863
2864 [pbn_b3_2_115200] = {
2865 .flags = FL_BASE3,
2866 .num_ports = 2,
2867 .base_baud = 115200,
2868 .uart_offset = 8,
2869 },
2870 [pbn_b3_4_115200] = {
2871 .flags = FL_BASE3,
2872 .num_ports = 4,
2873 .base_baud = 115200,
2874 .uart_offset = 8,
2875 },
2876 [pbn_b3_8_115200] = {
2877 .flags = FL_BASE3,
2878 .num_ports = 8,
2879 .base_baud = 115200,
2880 .uart_offset = 8,
2881 },
2882
2883 [pbn_b4_bt_2_921600] = {
2884 .flags = FL_BASE4,
2885 .num_ports = 2,
2886 .base_baud = 921600,
2887 .uart_offset = 8,
2888 },
2889 [pbn_b4_bt_4_921600] = {
2890 .flags = FL_BASE4,
2891 .num_ports = 4,
2892 .base_baud = 921600,
2893 .uart_offset = 8,
2894 },
2895 [pbn_b4_bt_8_921600] = {
2896 .flags = FL_BASE4,
2897 .num_ports = 8,
2898 .base_baud = 921600,
2899 .uart_offset = 8,
2900 },
2901
2902 /*
2903 * Entries following this are board-specific.
2904 */
2905
2906 /*
2907 * Panacom - IOMEM
2908 */
2909 [pbn_panacom] = {
2910 .flags = FL_BASE2,
2911 .num_ports = 2,
2912 .base_baud = 921600,
2913 .uart_offset = 0x400,
2914 .reg_shift = 7,
2915 },
2916 [pbn_panacom2] = {
2917 .flags = FL_BASE2|FL_BASE_BARS,
2918 .num_ports = 2,
2919 .base_baud = 921600,
2920 .uart_offset = 0x400,
2921 .reg_shift = 7,
2922 },
2923 [pbn_panacom4] = {
2924 .flags = FL_BASE2|FL_BASE_BARS,
2925 .num_ports = 4,
2926 .base_baud = 921600,
2927 .uart_offset = 0x400,
2928 .reg_shift = 7,
2929 },
2930
2931 /* I think this entry is broken - the first_offset looks wrong --rmk */
2932 [pbn_plx_romulus] = {
2933 .flags = FL_BASE2,
2934 .num_ports = 4,
2935 .base_baud = 921600,
2936 .uart_offset = 8 << 2,
2937 .reg_shift = 2,
2938 .first_offset = 0x03,
2939 },
2940
2941 /*
2942 * This board uses the size of PCI Base region 0 to
2943 * signal now many ports are available
2944 */
2945 [pbn_oxsemi] = {
2946 .flags = FL_BASE0|FL_REGION_SZ_CAP,
2947 .num_ports = 32,
2948 .base_baud = 115200,
2949 .uart_offset = 8,
2950 },
2951 [pbn_oxsemi_1_4000000] = {
2952 .flags = FL_BASE0,
2953 .num_ports = 1,
2954 .base_baud = 4000000,
2955 .uart_offset = 0x200,
2956 .first_offset = 0x1000,
2957 },
2958 [pbn_oxsemi_2_4000000] = {
2959 .flags = FL_BASE0,
2960 .num_ports = 2,
2961 .base_baud = 4000000,
2962 .uart_offset = 0x200,
2963 .first_offset = 0x1000,
2964 },
2965 [pbn_oxsemi_4_4000000] = {
2966 .flags = FL_BASE0,
2967 .num_ports = 4,
2968 .base_baud = 4000000,
2969 .uart_offset = 0x200,
2970 .first_offset = 0x1000,
2971 },
2972 [pbn_oxsemi_8_4000000] = {
2973 .flags = FL_BASE0,
2974 .num_ports = 8,
2975 .base_baud = 4000000,
2976 .uart_offset = 0x200,
2977 .first_offset = 0x1000,
2978 },
2979
2980
2981 /*
2982 * EKF addition for i960 Boards form EKF with serial port.
2983 * Max 256 ports.
2984 */
2985 [pbn_intel_i960] = {
2986 .flags = FL_BASE0,
2987 .num_ports = 32,
2988 .base_baud = 921600,
2989 .uart_offset = 8 << 2,
2990 .reg_shift = 2,
2991 .first_offset = 0x10000,
2992 },
2993 [pbn_sgi_ioc3] = {
2994 .flags = FL_BASE0|FL_NOIRQ,
2995 .num_ports = 1,
2996 .base_baud = 458333,
2997 .uart_offset = 8,
2998 .reg_shift = 0,
2999 .first_offset = 0x20178,
3000 },
3001
3002 /*
3003 * Computone - uses IOMEM.
3004 */
3005 [pbn_computone_4] = {
3006 .flags = FL_BASE0,
3007 .num_ports = 4,
3008 .base_baud = 921600,
3009 .uart_offset = 0x40,
3010 .reg_shift = 2,
3011 .first_offset = 0x200,
3012 },
3013 [pbn_computone_6] = {
3014 .flags = FL_BASE0,
3015 .num_ports = 6,
3016 .base_baud = 921600,
3017 .uart_offset = 0x40,
3018 .reg_shift = 2,
3019 .first_offset = 0x200,
3020 },
3021 [pbn_computone_8] = {
3022 .flags = FL_BASE0,
3023 .num_ports = 8,
3024 .base_baud = 921600,
3025 .uart_offset = 0x40,
3026 .reg_shift = 2,
3027 .first_offset = 0x200,
3028 },
3029 [pbn_sbsxrsio] = {
3030 .flags = FL_BASE0,
3031 .num_ports = 8,
3032 .base_baud = 460800,
3033 .uart_offset = 256,
3034 .reg_shift = 4,
3035 },
3036 /*
3037 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3038 * Only basic 16550A support.
3039 * XR17C15[24] are not tested, but they should work.
3040 */
3041 [pbn_exar_XR17C152] = {
3042 .flags = FL_BASE0,
3043 .num_ports = 2,
3044 .base_baud = 921600,
3045 .uart_offset = 0x200,
3046 },
3047 [pbn_exar_XR17C154] = {
3048 .flags = FL_BASE0,
3049 .num_ports = 4,
3050 .base_baud = 921600,
3051 .uart_offset = 0x200,
3052 },
3053 [pbn_exar_XR17C158] = {
3054 .flags = FL_BASE0,
3055 .num_ports = 8,
3056 .base_baud = 921600,
3057 .uart_offset = 0x200,
3058 },
3059 [pbn_exar_XR17V352] = {
3060 .flags = FL_BASE0,
3061 .num_ports = 2,
3062 .base_baud = 7812500,
3063 .uart_offset = 0x400,
3064 .reg_shift = 0,
3065 .first_offset = 0,
3066 },
3067 [pbn_exar_XR17V354] = {
3068 .flags = FL_BASE0,
3069 .num_ports = 4,
3070 .base_baud = 7812500,
3071 .uart_offset = 0x400,
3072 .reg_shift = 0,
3073 .first_offset = 0,
3074 },
3075 [pbn_exar_XR17V358] = {
3076 .flags = FL_BASE0,
3077 .num_ports = 8,
3078 .base_baud = 7812500,
3079 .uart_offset = 0x400,
3080 .reg_shift = 0,
3081 .first_offset = 0,
3082 },
3083 [pbn_exar_ibm_saturn] = {
3084 .flags = FL_BASE0,
3085 .num_ports = 1,
3086 .base_baud = 921600,
3087 .uart_offset = 0x200,
3088 },
3089
3090 /*
3091 * PA Semi PWRficient PA6T-1682M on-chip UART
3092 */
3093 [pbn_pasemi_1682M] = {
3094 .flags = FL_BASE0,
3095 .num_ports = 1,
3096 .base_baud = 8333333,
3097 },
3098 /*
3099 * National Instruments 843x
3100 */
3101 [pbn_ni8430_16] = {
3102 .flags = FL_BASE0,
3103 .num_ports = 16,
3104 .base_baud = 3686400,
3105 .uart_offset = 0x10,
3106 .first_offset = 0x800,
3107 },
3108 [pbn_ni8430_8] = {
3109 .flags = FL_BASE0,
3110 .num_ports = 8,
3111 .base_baud = 3686400,
3112 .uart_offset = 0x10,
3113 .first_offset = 0x800,
3114 },
3115 [pbn_ni8430_4] = {
3116 .flags = FL_BASE0,
3117 .num_ports = 4,
3118 .base_baud = 3686400,
3119 .uart_offset = 0x10,
3120 .first_offset = 0x800,
3121 },
3122 [pbn_ni8430_2] = {
3123 .flags = FL_BASE0,
3124 .num_ports = 2,
3125 .base_baud = 3686400,
3126 .uart_offset = 0x10,
3127 .first_offset = 0x800,
3128 },
3129 /*
3130 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3131 */
3132 [pbn_ADDIDATA_PCIe_1_3906250] = {
3133 .flags = FL_BASE0,
3134 .num_ports = 1,
3135 .base_baud = 3906250,
3136 .uart_offset = 0x200,
3137 .first_offset = 0x1000,
3138 },
3139 [pbn_ADDIDATA_PCIe_2_3906250] = {
3140 .flags = FL_BASE0,
3141 .num_ports = 2,
3142 .base_baud = 3906250,
3143 .uart_offset = 0x200,
3144 .first_offset = 0x1000,
3145 },
3146 [pbn_ADDIDATA_PCIe_4_3906250] = {
3147 .flags = FL_BASE0,
3148 .num_ports = 4,
3149 .base_baud = 3906250,
3150 .uart_offset = 0x200,
3151 .first_offset = 0x1000,
3152 },
3153 [pbn_ADDIDATA_PCIe_8_3906250] = {
3154 .flags = FL_BASE0,
3155 .num_ports = 8,
3156 .base_baud = 3906250,
3157 .uart_offset = 0x200,
3158 .first_offset = 0x1000,
3159 },
3160 [pbn_ce4100_1_115200] = {
3161 .flags = FL_BASE_BARS,
3162 .num_ports = 2,
3163 .base_baud = 921600,
3164 .reg_shift = 2,
3165 },
3166 [pbn_omegapci] = {
3167 .flags = FL_BASE0,
3168 .num_ports = 8,
3169 .base_baud = 115200,
3170 .uart_offset = 0x200,
3171 },
3172 [pbn_NETMOS9900_2s_115200] = {
3173 .flags = FL_BASE0,
3174 .num_ports = 2,
3175 .base_baud = 115200,
3176 },
3177 [pbn_brcm_trumanage] = {
3178 .flags = FL_BASE0,
3179 .num_ports = 1,
3180 .reg_shift = 2,
3181 .base_baud = 115200,
3182 },
3183 };
3184
3185 static const struct pci_device_id blacklist[] = {
3186 /* softmodems */
3187 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3188 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3189 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3190
3191 /* multi-io cards handled by parport_serial */
3192 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3193 };
3194
3195 /*
3196 * Given a complete unknown PCI device, try to use some heuristics to
3197 * guess what the configuration might be, based on the pitiful PCI
3198 * serial specs. Returns 0 on success, 1 on failure.
3199 */
3200 static int
3201 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3202 {
3203 const struct pci_device_id *bldev;
3204 int num_iomem, num_port, first_port = -1, i;
3205
3206 /*
3207 * If it is not a communications device or the programming
3208 * interface is greater than 6, give up.
3209 *
3210 * (Should we try to make guesses for multiport serial devices
3211 * later?)
3212 */
3213 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3214 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3215 (dev->class & 0xff) > 6)
3216 return -ENODEV;
3217
3218 /*
3219 * Do not access blacklisted devices that are known not to
3220 * feature serial ports or are handled by other modules.
3221 */
3222 for (bldev = blacklist;
3223 bldev < blacklist + ARRAY_SIZE(blacklist);
3224 bldev++) {
3225 if (dev->vendor == bldev->vendor &&
3226 dev->device == bldev->device)
3227 return -ENODEV;
3228 }
3229
3230 num_iomem = num_port = 0;
3231 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3232 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3233 num_port++;
3234 if (first_port == -1)
3235 first_port = i;
3236 }
3237 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3238 num_iomem++;
3239 }
3240
3241 /*
3242 * If there is 1 or 0 iomem regions, and exactly one port,
3243 * use it. We guess the number of ports based on the IO
3244 * region size.
3245 */
3246 if (num_iomem <= 1 && num_port == 1) {
3247 board->flags = first_port;
3248 board->num_ports = pci_resource_len(dev, first_port) / 8;
3249 return 0;
3250 }
3251
3252 /*
3253 * Now guess if we've got a board which indexes by BARs.
3254 * Each IO BAR should be 8 bytes, and they should follow
3255 * consecutively.
3256 */
3257 first_port = -1;
3258 num_port = 0;
3259 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3260 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3261 pci_resource_len(dev, i) == 8 &&
3262 (first_port == -1 || (first_port + num_port) == i)) {
3263 num_port++;
3264 if (first_port == -1)
3265 first_port = i;
3266 }
3267 }
3268
3269 if (num_port > 1) {
3270 board->flags = first_port | FL_BASE_BARS;
3271 board->num_ports = num_port;
3272 return 0;
3273 }
3274
3275 return -ENODEV;
3276 }
3277
3278 static inline int
3279 serial_pci_matches(const struct pciserial_board *board,
3280 const struct pciserial_board *guessed)
3281 {
3282 return
3283 board->num_ports == guessed->num_ports &&
3284 board->base_baud == guessed->base_baud &&
3285 board->uart_offset == guessed->uart_offset &&
3286 board->reg_shift == guessed->reg_shift &&
3287 board->first_offset == guessed->first_offset;
3288 }
3289
3290 struct serial_private *
3291 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3292 {
3293 struct uart_8250_port uart;
3294 struct serial_private *priv;
3295 struct pci_serial_quirk *quirk;
3296 int rc, nr_ports, i;
3297
3298 nr_ports = board->num_ports;
3299
3300 /*
3301 * Find an init and setup quirks.
3302 */
3303 quirk = find_quirk(dev);
3304
3305 /*
3306 * Run the new-style initialization function.
3307 * The initialization function returns:
3308 * <0 - error
3309 * 0 - use board->num_ports
3310 * >0 - number of ports
3311 */
3312 if (quirk->init) {
3313 rc = quirk->init(dev);
3314 if (rc < 0) {
3315 priv = ERR_PTR(rc);
3316 goto err_out;
3317 }
3318 if (rc)
3319 nr_ports = rc;
3320 }
3321
3322 priv = kzalloc(sizeof(struct serial_private) +
3323 sizeof(unsigned int) * nr_ports,
3324 GFP_KERNEL);
3325 if (!priv) {
3326 priv = ERR_PTR(-ENOMEM);
3327 goto err_deinit;
3328 }
3329
3330 priv->dev = dev;
3331 priv->quirk = quirk;
3332
3333 memset(&uart, 0, sizeof(uart));
3334 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3335 uart.port.uartclk = board->base_baud * 16;
3336 uart.port.irq = get_pci_irq(dev, board);
3337 uart.port.dev = &dev->dev;
3338
3339 for (i = 0; i < nr_ports; i++) {
3340 if (quirk->setup(priv, board, &uart, i))
3341 break;
3342
3343 #ifdef SERIAL_DEBUG_PCI
3344 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
3345 uart.port.iobase, uart.port.irq, uart.port.iotype);
3346 #endif
3347
3348 priv->line[i] = serial8250_register_8250_port(&uart);
3349 if (priv->line[i] < 0) {
3350 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
3351 break;
3352 }
3353 }
3354 priv->nr = i;
3355 return priv;
3356
3357 err_deinit:
3358 if (quirk->exit)
3359 quirk->exit(dev);
3360 err_out:
3361 return priv;
3362 }
3363 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3364
3365 void pciserial_remove_ports(struct serial_private *priv)
3366 {
3367 struct pci_serial_quirk *quirk;
3368 int i;
3369
3370 for (i = 0; i < priv->nr; i++)
3371 serial8250_unregister_port(priv->line[i]);
3372
3373 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3374 if (priv->remapped_bar[i])
3375 iounmap(priv->remapped_bar[i]);
3376 priv->remapped_bar[i] = NULL;
3377 }
3378
3379 /*
3380 * Find the exit quirks.
3381 */
3382 quirk = find_quirk(priv->dev);
3383 if (quirk->exit)
3384 quirk->exit(priv->dev);
3385
3386 kfree(priv);
3387 }
3388 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3389
3390 void pciserial_suspend_ports(struct serial_private *priv)
3391 {
3392 int i;
3393
3394 for (i = 0; i < priv->nr; i++)
3395 if (priv->line[i] >= 0)
3396 serial8250_suspend_port(priv->line[i]);
3397
3398 /*
3399 * Ensure that every init quirk is properly torn down
3400 */
3401 if (priv->quirk->exit)
3402 priv->quirk->exit(priv->dev);
3403 }
3404 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3405
3406 void pciserial_resume_ports(struct serial_private *priv)
3407 {
3408 int i;
3409
3410 /*
3411 * Ensure that the board is correctly configured.
3412 */
3413 if (priv->quirk->init)
3414 priv->quirk->init(priv->dev);
3415
3416 for (i = 0; i < priv->nr; i++)
3417 if (priv->line[i] >= 0)
3418 serial8250_resume_port(priv->line[i]);
3419 }
3420 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3421
3422 /*
3423 * Probe one serial board. Unfortunately, there is no rhyme nor reason
3424 * to the arrangement of serial ports on a PCI card.
3425 */
3426 static int
3427 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3428 {
3429 struct pci_serial_quirk *quirk;
3430 struct serial_private *priv;
3431 const struct pciserial_board *board;
3432 struct pciserial_board tmp;
3433 int rc;
3434
3435 quirk = find_quirk(dev);
3436 if (quirk->probe) {
3437 rc = quirk->probe(dev);
3438 if (rc)
3439 return rc;
3440 }
3441
3442 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3443 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
3444 ent->driver_data);
3445 return -EINVAL;
3446 }
3447
3448 board = &pci_boards[ent->driver_data];
3449
3450 rc = pci_enable_device(dev);
3451 pci_save_state(dev);
3452 if (rc)
3453 return rc;
3454
3455 if (ent->driver_data == pbn_default) {
3456 /*
3457 * Use a copy of the pci_board entry for this;
3458 * avoid changing entries in the table.
3459 */
3460 memcpy(&tmp, board, sizeof(struct pciserial_board));
3461 board = &tmp;
3462
3463 /*
3464 * We matched one of our class entries. Try to
3465 * determine the parameters of this board.
3466 */
3467 rc = serial_pci_guess_board(dev, &tmp);
3468 if (rc)
3469 goto disable;
3470 } else {
3471 /*
3472 * We matched an explicit entry. If we are able to
3473 * detect this boards settings with our heuristic,
3474 * then we no longer need this entry.
3475 */
3476 memcpy(&tmp, &pci_boards[pbn_default],
3477 sizeof(struct pciserial_board));
3478 rc = serial_pci_guess_board(dev, &tmp);
3479 if (rc == 0 && serial_pci_matches(board, &tmp))
3480 moan_device("Redundant entry in serial pci_table.",
3481 dev);
3482 }
3483
3484 priv = pciserial_init_ports(dev, board);
3485 if (!IS_ERR(priv)) {
3486 pci_set_drvdata(dev, priv);
3487 return 0;
3488 }
3489
3490 rc = PTR_ERR(priv);
3491
3492 disable:
3493 pci_disable_device(dev);
3494 return rc;
3495 }
3496
3497 static void pciserial_remove_one(struct pci_dev *dev)
3498 {
3499 struct serial_private *priv = pci_get_drvdata(dev);
3500
3501 pci_set_drvdata(dev, NULL);
3502
3503 pciserial_remove_ports(priv);
3504
3505 pci_disable_device(dev);
3506 }
3507
3508 #ifdef CONFIG_PM
3509 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
3510 {
3511 struct serial_private *priv = pci_get_drvdata(dev);
3512
3513 if (priv)
3514 pciserial_suspend_ports(priv);
3515
3516 pci_save_state(dev);
3517 pci_set_power_state(dev, pci_choose_state(dev, state));
3518 return 0;
3519 }
3520
3521 static int pciserial_resume_one(struct pci_dev *dev)
3522 {
3523 int err;
3524 struct serial_private *priv = pci_get_drvdata(dev);
3525
3526 pci_set_power_state(dev, PCI_D0);
3527 pci_restore_state(dev);
3528
3529 if (priv) {
3530 /*
3531 * The device may have been disabled. Re-enable it.
3532 */
3533 err = pci_enable_device(dev);
3534 /* FIXME: We cannot simply error out here */
3535 if (err)
3536 printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
3537 pciserial_resume_ports(priv);
3538 }
3539 return 0;
3540 }
3541 #endif
3542
3543 static struct pci_device_id serial_pci_tbl[] = {
3544 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3545 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3546 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3547 pbn_b2_8_921600 },
3548 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3549 PCI_SUBVENDOR_ID_CONNECT_TECH,
3550 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3551 pbn_b1_8_1382400 },
3552 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3553 PCI_SUBVENDOR_ID_CONNECT_TECH,
3554 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3555 pbn_b1_4_1382400 },
3556 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3557 PCI_SUBVENDOR_ID_CONNECT_TECH,
3558 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3559 pbn_b1_2_1382400 },
3560 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3561 PCI_SUBVENDOR_ID_CONNECT_TECH,
3562 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3563 pbn_b1_8_1382400 },
3564 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3565 PCI_SUBVENDOR_ID_CONNECT_TECH,
3566 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3567 pbn_b1_4_1382400 },
3568 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3569 PCI_SUBVENDOR_ID_CONNECT_TECH,
3570 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3571 pbn_b1_2_1382400 },
3572 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3573 PCI_SUBVENDOR_ID_CONNECT_TECH,
3574 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3575 pbn_b1_8_921600 },
3576 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3577 PCI_SUBVENDOR_ID_CONNECT_TECH,
3578 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3579 pbn_b1_8_921600 },
3580 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3581 PCI_SUBVENDOR_ID_CONNECT_TECH,
3582 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3583 pbn_b1_4_921600 },
3584 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3585 PCI_SUBVENDOR_ID_CONNECT_TECH,
3586 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3587 pbn_b1_4_921600 },
3588 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3589 PCI_SUBVENDOR_ID_CONNECT_TECH,
3590 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3591 pbn_b1_2_921600 },
3592 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3593 PCI_SUBVENDOR_ID_CONNECT_TECH,
3594 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3595 pbn_b1_8_921600 },
3596 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3597 PCI_SUBVENDOR_ID_CONNECT_TECH,
3598 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3599 pbn_b1_8_921600 },
3600 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3601 PCI_SUBVENDOR_ID_CONNECT_TECH,
3602 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3603 pbn_b1_4_921600 },
3604 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3605 PCI_SUBVENDOR_ID_CONNECT_TECH,
3606 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3607 pbn_b1_2_1250000 },
3608 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3609 PCI_SUBVENDOR_ID_CONNECT_TECH,
3610 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3611 pbn_b0_2_1843200 },
3612 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3613 PCI_SUBVENDOR_ID_CONNECT_TECH,
3614 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3615 pbn_b0_4_1843200 },
3616 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3617 PCI_VENDOR_ID_AFAVLAB,
3618 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3619 pbn_b0_4_1152000 },
3620 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3621 PCI_SUBVENDOR_ID_CONNECT_TECH,
3622 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3623 pbn_b0_2_1843200_200 },
3624 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3625 PCI_SUBVENDOR_ID_CONNECT_TECH,
3626 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3627 pbn_b0_4_1843200_200 },
3628 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3629 PCI_SUBVENDOR_ID_CONNECT_TECH,
3630 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3631 pbn_b0_8_1843200_200 },
3632 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3633 PCI_SUBVENDOR_ID_CONNECT_TECH,
3634 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3635 pbn_b0_2_1843200_200 },
3636 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3637 PCI_SUBVENDOR_ID_CONNECT_TECH,
3638 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3639 pbn_b0_4_1843200_200 },
3640 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3641 PCI_SUBVENDOR_ID_CONNECT_TECH,
3642 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3643 pbn_b0_8_1843200_200 },
3644 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3645 PCI_SUBVENDOR_ID_CONNECT_TECH,
3646 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3647 pbn_b0_2_1843200_200 },
3648 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3649 PCI_SUBVENDOR_ID_CONNECT_TECH,
3650 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3651 pbn_b0_4_1843200_200 },
3652 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3653 PCI_SUBVENDOR_ID_CONNECT_TECH,
3654 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3655 pbn_b0_8_1843200_200 },
3656 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3657 PCI_SUBVENDOR_ID_CONNECT_TECH,
3658 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3659 pbn_b0_2_1843200_200 },
3660 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3661 PCI_SUBVENDOR_ID_CONNECT_TECH,
3662 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3663 pbn_b0_4_1843200_200 },
3664 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3665 PCI_SUBVENDOR_ID_CONNECT_TECH,
3666 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3667 pbn_b0_8_1843200_200 },
3668 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3669 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3670 0, 0, pbn_exar_ibm_saturn },
3671
3672 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3673 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3674 pbn_b2_bt_1_115200 },
3675 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3676 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3677 pbn_b2_bt_2_115200 },
3678 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3679 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3680 pbn_b2_bt_4_115200 },
3681 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3682 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3683 pbn_b2_bt_2_115200 },
3684 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3685 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3686 pbn_b2_bt_4_115200 },
3687 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3688 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3689 pbn_b2_8_115200 },
3690 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3691 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3692 pbn_b2_8_460800 },
3693 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3694 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3695 pbn_b2_8_115200 },
3696
3697 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3698 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3699 pbn_b2_bt_2_115200 },
3700 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3701 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3702 pbn_b2_bt_2_921600 },
3703 /*
3704 * VScom SPCOM800, from sl@s.pl
3705 */
3706 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3707 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3708 pbn_b2_8_921600 },
3709 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
3710 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3711 pbn_b2_4_921600 },
3712 /* Unknown card - subdevice 0x1584 */
3713 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3714 PCI_VENDOR_ID_PLX,
3715 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3716 pbn_b0_4_115200 },
3717 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3718 PCI_SUBVENDOR_ID_KEYSPAN,
3719 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3720 pbn_panacom },
3721 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3722 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3723 pbn_panacom4 },
3724 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3725 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3726 pbn_panacom2 },
3727 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3728 PCI_VENDOR_ID_ESDGMBH,
3729 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3730 pbn_b2_4_115200 },
3731 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3732 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3733 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
3734 pbn_b2_4_460800 },
3735 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3736 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3737 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
3738 pbn_b2_8_460800 },
3739 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3740 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3741 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
3742 pbn_b2_16_460800 },
3743 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3744 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3745 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
3746 pbn_b2_16_460800 },
3747 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3748 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3749 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
3750 pbn_b2_4_460800 },
3751 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3752 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3753 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
3754 pbn_b2_8_460800 },
3755 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3756 PCI_SUBVENDOR_ID_EXSYS,
3757 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3758 pbn_b2_4_115200 },
3759 /*
3760 * Megawolf Romulus PCI Serial Card, from Mike Hudson
3761 * (Exoray@isys.ca)
3762 */
3763 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3764 0x10b5, 0x106a, 0, 0,
3765 pbn_plx_romulus },
3766 /*
3767 * Quatech cards. These actually have configurable clocks but for
3768 * now we just use the default.
3769 *
3770 * 100 series are RS232, 200 series RS422,
3771 */
3772 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3773 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3774 pbn_b1_4_115200 },
3775 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3776 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3777 pbn_b1_2_115200 },
3778 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
3779 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3780 pbn_b2_2_115200 },
3781 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
3782 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3783 pbn_b1_2_115200 },
3784 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
3785 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3786 pbn_b2_2_115200 },
3787 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
3788 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3789 pbn_b1_4_115200 },
3790 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3791 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3792 pbn_b1_8_115200 },
3793 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3794 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3795 pbn_b1_8_115200 },
3796 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
3797 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3798 pbn_b1_4_115200 },
3799 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
3800 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3801 pbn_b1_2_115200 },
3802 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
3803 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3804 pbn_b1_4_115200 },
3805 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
3806 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3807 pbn_b1_2_115200 },
3808 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
3809 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3810 pbn_b2_4_115200 },
3811 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
3812 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3813 pbn_b2_2_115200 },
3814 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
3815 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3816 pbn_b2_1_115200 },
3817 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
3818 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3819 pbn_b2_4_115200 },
3820 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
3821 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3822 pbn_b2_2_115200 },
3823 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
3824 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3825 pbn_b2_1_115200 },
3826 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
3827 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3828 pbn_b0_8_115200 },
3829
3830 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
3831 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3832 0, 0,
3833 pbn_b0_4_921600 },
3834 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3835 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3836 0, 0,
3837 pbn_b0_4_1152000 },
3838 { PCI_VENDOR_ID_OXSEMI, 0x9505,
3839 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3840 pbn_b0_bt_2_921600 },
3841
3842 /*
3843 * The below card is a little controversial since it is the
3844 * subject of a PCI vendor/device ID clash. (See
3845 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3846 * For now just used the hex ID 0x950a.
3847 */
3848 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3849 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
3850 0, 0, pbn_b0_2_115200 },
3851 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3852 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
3853 0, 0, pbn_b0_2_115200 },
3854 { PCI_VENDOR_ID_OXSEMI, 0x950a,
3855 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3856 pbn_b0_2_1130000 },
3857 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3858 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3859 pbn_b0_1_921600 },
3860 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3861 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3862 pbn_b0_4_115200 },
3863 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3864 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3865 pbn_b0_bt_2_921600 },
3866 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3867 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3868 pbn_b2_8_1152000 },
3869
3870 /*
3871 * Oxford Semiconductor Inc. Tornado PCI express device range.
3872 */
3873 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
3874 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3875 pbn_b0_1_4000000 },
3876 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
3877 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3878 pbn_b0_1_4000000 },
3879 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
3880 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3881 pbn_oxsemi_1_4000000 },
3882 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
3883 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3884 pbn_oxsemi_1_4000000 },
3885 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
3886 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3887 pbn_b0_1_4000000 },
3888 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
3889 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3890 pbn_b0_1_4000000 },
3891 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
3892 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3893 pbn_oxsemi_1_4000000 },
3894 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
3895 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3896 pbn_oxsemi_1_4000000 },
3897 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
3898 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3899 pbn_b0_1_4000000 },
3900 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
3901 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3902 pbn_b0_1_4000000 },
3903 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
3904 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3905 pbn_b0_1_4000000 },
3906 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
3907 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3908 pbn_b0_1_4000000 },
3909 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
3910 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3911 pbn_oxsemi_2_4000000 },
3912 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
3913 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3914 pbn_oxsemi_2_4000000 },
3915 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
3916 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3917 pbn_oxsemi_4_4000000 },
3918 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
3919 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3920 pbn_oxsemi_4_4000000 },
3921 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
3922 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3923 pbn_oxsemi_8_4000000 },
3924 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
3925 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3926 pbn_oxsemi_8_4000000 },
3927 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
3928 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3929 pbn_oxsemi_1_4000000 },
3930 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
3931 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3932 pbn_oxsemi_1_4000000 },
3933 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
3934 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3935 pbn_oxsemi_1_4000000 },
3936 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
3937 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3938 pbn_oxsemi_1_4000000 },
3939 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
3940 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3941 pbn_oxsemi_1_4000000 },
3942 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
3943 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3944 pbn_oxsemi_1_4000000 },
3945 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
3946 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3947 pbn_oxsemi_1_4000000 },
3948 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
3949 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3950 pbn_oxsemi_1_4000000 },
3951 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
3952 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3953 pbn_oxsemi_1_4000000 },
3954 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
3955 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3956 pbn_oxsemi_1_4000000 },
3957 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
3958 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3959 pbn_oxsemi_1_4000000 },
3960 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
3961 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3962 pbn_oxsemi_1_4000000 },
3963 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
3964 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3965 pbn_oxsemi_1_4000000 },
3966 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
3967 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3968 pbn_oxsemi_1_4000000 },
3969 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
3970 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3971 pbn_oxsemi_1_4000000 },
3972 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
3973 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3974 pbn_oxsemi_1_4000000 },
3975 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
3976 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3977 pbn_oxsemi_1_4000000 },
3978 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
3979 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3980 pbn_oxsemi_1_4000000 },
3981 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
3982 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3983 pbn_oxsemi_1_4000000 },
3984 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
3985 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3986 pbn_oxsemi_1_4000000 },
3987 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
3988 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3989 pbn_oxsemi_1_4000000 },
3990 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
3991 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3992 pbn_oxsemi_1_4000000 },
3993 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
3994 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3995 pbn_oxsemi_1_4000000 },
3996 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
3997 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3998 pbn_oxsemi_1_4000000 },
3999 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4000 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4001 pbn_oxsemi_1_4000000 },
4002 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4003 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4004 pbn_oxsemi_1_4000000 },
4005 /*
4006 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4007 */
4008 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4009 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4010 pbn_oxsemi_1_4000000 },
4011 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4012 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4013 pbn_oxsemi_2_4000000 },
4014 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4015 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4016 pbn_oxsemi_4_4000000 },
4017 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4018 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4019 pbn_oxsemi_8_4000000 },
4020
4021 /*
4022 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4023 */
4024 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4025 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4026 pbn_oxsemi_2_4000000 },
4027
4028 /*
4029 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4030 * from skokodyn@yahoo.com
4031 */
4032 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4033 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4034 pbn_sbsxrsio },
4035 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4036 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4037 pbn_sbsxrsio },
4038 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4039 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4040 pbn_sbsxrsio },
4041 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4042 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4043 pbn_sbsxrsio },
4044
4045 /*
4046 * Digitan DS560-558, from jimd@esoft.com
4047 */
4048 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4049 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4050 pbn_b1_1_115200 },
4051
4052 /*
4053 * Titan Electronic cards
4054 * The 400L and 800L have a custom setup quirk.
4055 */
4056 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4057 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4058 pbn_b0_1_921600 },
4059 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4060 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4061 pbn_b0_2_921600 },
4062 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4063 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4064 pbn_b0_4_921600 },
4065 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4066 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4067 pbn_b0_4_921600 },
4068 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4069 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4070 pbn_b1_1_921600 },
4071 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4072 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4073 pbn_b1_bt_2_921600 },
4074 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4075 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4076 pbn_b0_bt_4_921600 },
4077 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4078 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4079 pbn_b0_bt_8_921600 },
4080 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4081 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4082 pbn_b4_bt_2_921600 },
4083 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4084 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4085 pbn_b4_bt_4_921600 },
4086 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4087 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4088 pbn_b4_bt_8_921600 },
4089 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4090 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4091 pbn_b0_4_921600 },
4092 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4093 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4094 pbn_b0_4_921600 },
4095 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4096 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4097 pbn_b0_4_921600 },
4098 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4099 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4100 pbn_oxsemi_1_4000000 },
4101 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4102 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4103 pbn_oxsemi_2_4000000 },
4104 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4105 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4106 pbn_oxsemi_4_4000000 },
4107 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4108 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4109 pbn_oxsemi_8_4000000 },
4110 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4111 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4112 pbn_oxsemi_2_4000000 },
4113 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4114 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4115 pbn_oxsemi_2_4000000 },
4116 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4117 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4118 pbn_b0_4_921600 },
4119 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4120 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4121 pbn_b0_4_921600 },
4122 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4123 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4124 pbn_b0_4_921600 },
4125 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4126 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4127 pbn_b0_4_921600 },
4128
4129 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4130 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4131 pbn_b2_1_460800 },
4132 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4133 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4134 pbn_b2_1_460800 },
4135 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4136 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4137 pbn_b2_1_460800 },
4138 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4139 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4140 pbn_b2_bt_2_921600 },
4141 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4142 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4143 pbn_b2_bt_2_921600 },
4144 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4145 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4146 pbn_b2_bt_2_921600 },
4147 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4148 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4149 pbn_b2_bt_4_921600 },
4150 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4151 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4152 pbn_b2_bt_4_921600 },
4153 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4154 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4155 pbn_b2_bt_4_921600 },
4156 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4157 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4158 pbn_b0_1_921600 },
4159 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4160 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4161 pbn_b0_1_921600 },
4162 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4163 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4164 pbn_b0_1_921600 },
4165 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4166 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4167 pbn_b0_bt_2_921600 },
4168 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4169 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4170 pbn_b0_bt_2_921600 },
4171 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4172 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4173 pbn_b0_bt_2_921600 },
4174 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4175 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4176 pbn_b0_bt_4_921600 },
4177 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4178 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4179 pbn_b0_bt_4_921600 },
4180 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4181 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4182 pbn_b0_bt_4_921600 },
4183 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4184 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4185 pbn_b0_bt_8_921600 },
4186 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4187 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4188 pbn_b0_bt_8_921600 },
4189 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4190 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4191 pbn_b0_bt_8_921600 },
4192
4193 /*
4194 * Computone devices submitted by Doug McNash dmcnash@computone.com
4195 */
4196 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4197 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4198 0, 0, pbn_computone_4 },
4199 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4200 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4201 0, 0, pbn_computone_8 },
4202 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4203 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4204 0, 0, pbn_computone_6 },
4205
4206 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4207 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4208 pbn_oxsemi },
4209 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4210 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4211 pbn_b0_bt_1_921600 },
4212
4213 /*
4214 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4215 */
4216 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4217 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4218 pbn_b0_bt_8_115200 },
4219 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4220 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4221 pbn_b0_bt_8_115200 },
4222
4223 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4224 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4225 pbn_b0_bt_2_115200 },
4226 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4227 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4228 pbn_b0_bt_2_115200 },
4229 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4230 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4231 pbn_b0_bt_2_115200 },
4232 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4233 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4234 pbn_b0_bt_2_115200 },
4235 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4236 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4237 pbn_b0_bt_2_115200 },
4238 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4239 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4240 pbn_b0_bt_4_460800 },
4241 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4242 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4243 pbn_b0_bt_4_460800 },
4244 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4245 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4246 pbn_b0_bt_2_460800 },
4247 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4248 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4249 pbn_b0_bt_2_460800 },
4250 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4251 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4252 pbn_b0_bt_2_460800 },
4253 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4254 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4255 pbn_b0_bt_1_115200 },
4256 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4257 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4258 pbn_b0_bt_1_460800 },
4259
4260 /*
4261 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4262 * Cards are identified by their subsystem vendor IDs, which
4263 * (in hex) match the model number.
4264 *
4265 * Note that JC140x are RS422/485 cards which require ox950
4266 * ACR = 0x10, and as such are not currently fully supported.
4267 */
4268 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4269 0x1204, 0x0004, 0, 0,
4270 pbn_b0_4_921600 },
4271 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4272 0x1208, 0x0004, 0, 0,
4273 pbn_b0_4_921600 },
4274 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4275 0x1402, 0x0002, 0, 0,
4276 pbn_b0_2_921600 }, */
4277 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4278 0x1404, 0x0004, 0, 0,
4279 pbn_b0_4_921600 }, */
4280 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4281 0x1208, 0x0004, 0, 0,
4282 pbn_b0_4_921600 },
4283
4284 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4285 0x1204, 0x0004, 0, 0,
4286 pbn_b0_4_921600 },
4287 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4288 0x1208, 0x0004, 0, 0,
4289 pbn_b0_4_921600 },
4290 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4291 0x1208, 0x0004, 0, 0,
4292 pbn_b0_4_921600 },
4293 /*
4294 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4295 */
4296 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4297 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4298 pbn_b1_1_1382400 },
4299
4300 /*
4301 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4302 */
4303 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4304 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4305 pbn_b1_1_1382400 },
4306
4307 /*
4308 * RAStel 2 port modem, gerg@moreton.com.au
4309 */
4310 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4311 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4312 pbn_b2_bt_2_115200 },
4313
4314 /*
4315 * EKF addition for i960 Boards form EKF with serial port
4316 */
4317 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4318 0xE4BF, PCI_ANY_ID, 0, 0,
4319 pbn_intel_i960 },
4320
4321 /*
4322 * Xircom Cardbus/Ethernet combos
4323 */
4324 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4325 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4326 pbn_b0_1_115200 },
4327 /*
4328 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4329 */
4330 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4331 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4332 pbn_b0_1_115200 },
4333
4334 /*
4335 * Untested PCI modems, sent in from various folks...
4336 */
4337
4338 /*
4339 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4340 */
4341 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4342 0x1048, 0x1500, 0, 0,
4343 pbn_b1_1_115200 },
4344
4345 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4346 0xFF00, 0, 0, 0,
4347 pbn_sgi_ioc3 },
4348
4349 /*
4350 * HP Diva card
4351 */
4352 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4353 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4354 pbn_b1_1_115200 },
4355 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4356 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4357 pbn_b0_5_115200 },
4358 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4359 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4360 pbn_b2_1_115200 },
4361
4362 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4363 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4364 pbn_b3_2_115200 },
4365 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4366 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4367 pbn_b3_4_115200 },
4368 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4369 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4370 pbn_b3_8_115200 },
4371
4372 /*
4373 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
4374 */
4375 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4376 PCI_ANY_ID, PCI_ANY_ID,
4377 0,
4378 0, pbn_exar_XR17C152 },
4379 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4380 PCI_ANY_ID, PCI_ANY_ID,
4381 0,
4382 0, pbn_exar_XR17C154 },
4383 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4384 PCI_ANY_ID, PCI_ANY_ID,
4385 0,
4386 0, pbn_exar_XR17C158 },
4387 /*
4388 * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs
4389 */
4390 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
4391 PCI_ANY_ID, PCI_ANY_ID,
4392 0,
4393 0, pbn_exar_XR17V352 },
4394 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
4395 PCI_ANY_ID, PCI_ANY_ID,
4396 0,
4397 0, pbn_exar_XR17V354 },
4398 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
4399 PCI_ANY_ID, PCI_ANY_ID,
4400 0,
4401 0, pbn_exar_XR17V358 },
4402
4403 /*
4404 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4405 */
4406 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4407 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4408 pbn_b0_1_115200 },
4409 /*
4410 * ITE
4411 */
4412 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4413 PCI_ANY_ID, PCI_ANY_ID,
4414 0, 0,
4415 pbn_b1_bt_1_115200 },
4416
4417 /*
4418 * IntaShield IS-200
4419 */
4420 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4421 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
4422 pbn_b2_2_115200 },
4423 /*
4424 * IntaShield IS-400
4425 */
4426 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4427 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
4428 pbn_b2_4_115200 },
4429 /*
4430 * Perle PCI-RAS cards
4431 */
4432 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4433 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4434 0, 0, pbn_b2_4_921600 },
4435 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4436 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4437 0, 0, pbn_b2_8_921600 },
4438
4439 /*
4440 * Mainpine series cards: Fairly standard layout but fools
4441 * parts of the autodetect in some cases and uses otherwise
4442 * unmatched communications subclasses in the PCI Express case
4443 */
4444
4445 { /* RockForceDUO */
4446 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4447 PCI_VENDOR_ID_MAINPINE, 0x0200,
4448 0, 0, pbn_b0_2_115200 },
4449 { /* RockForceQUATRO */
4450 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4451 PCI_VENDOR_ID_MAINPINE, 0x0300,
4452 0, 0, pbn_b0_4_115200 },
4453 { /* RockForceDUO+ */
4454 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4455 PCI_VENDOR_ID_MAINPINE, 0x0400,
4456 0, 0, pbn_b0_2_115200 },
4457 { /* RockForceQUATRO+ */
4458 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4459 PCI_VENDOR_ID_MAINPINE, 0x0500,
4460 0, 0, pbn_b0_4_115200 },
4461 { /* RockForce+ */
4462 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4463 PCI_VENDOR_ID_MAINPINE, 0x0600,
4464 0, 0, pbn_b0_2_115200 },
4465 { /* RockForce+ */
4466 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4467 PCI_VENDOR_ID_MAINPINE, 0x0700,
4468 0, 0, pbn_b0_4_115200 },
4469 { /* RockForceOCTO+ */
4470 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4471 PCI_VENDOR_ID_MAINPINE, 0x0800,
4472 0, 0, pbn_b0_8_115200 },
4473 { /* RockForceDUO+ */
4474 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4475 PCI_VENDOR_ID_MAINPINE, 0x0C00,
4476 0, 0, pbn_b0_2_115200 },
4477 { /* RockForceQUARTRO+ */
4478 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4479 PCI_VENDOR_ID_MAINPINE, 0x0D00,
4480 0, 0, pbn_b0_4_115200 },
4481 { /* RockForceOCTO+ */
4482 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4483 PCI_VENDOR_ID_MAINPINE, 0x1D00,
4484 0, 0, pbn_b0_8_115200 },
4485 { /* RockForceD1 */
4486 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4487 PCI_VENDOR_ID_MAINPINE, 0x2000,
4488 0, 0, pbn_b0_1_115200 },
4489 { /* RockForceF1 */
4490 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4491 PCI_VENDOR_ID_MAINPINE, 0x2100,
4492 0, 0, pbn_b0_1_115200 },
4493 { /* RockForceD2 */
4494 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4495 PCI_VENDOR_ID_MAINPINE, 0x2200,
4496 0, 0, pbn_b0_2_115200 },
4497 { /* RockForceF2 */
4498 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4499 PCI_VENDOR_ID_MAINPINE, 0x2300,
4500 0, 0, pbn_b0_2_115200 },
4501 { /* RockForceD4 */
4502 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4503 PCI_VENDOR_ID_MAINPINE, 0x2400,
4504 0, 0, pbn_b0_4_115200 },
4505 { /* RockForceF4 */
4506 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4507 PCI_VENDOR_ID_MAINPINE, 0x2500,
4508 0, 0, pbn_b0_4_115200 },
4509 { /* RockForceD8 */
4510 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4511 PCI_VENDOR_ID_MAINPINE, 0x2600,
4512 0, 0, pbn_b0_8_115200 },
4513 { /* RockForceF8 */
4514 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4515 PCI_VENDOR_ID_MAINPINE, 0x2700,
4516 0, 0, pbn_b0_8_115200 },
4517 { /* IQ Express D1 */
4518 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4519 PCI_VENDOR_ID_MAINPINE, 0x3000,
4520 0, 0, pbn_b0_1_115200 },
4521 { /* IQ Express F1 */
4522 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4523 PCI_VENDOR_ID_MAINPINE, 0x3100,
4524 0, 0, pbn_b0_1_115200 },
4525 { /* IQ Express D2 */
4526 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4527 PCI_VENDOR_ID_MAINPINE, 0x3200,
4528 0, 0, pbn_b0_2_115200 },
4529 { /* IQ Express F2 */
4530 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4531 PCI_VENDOR_ID_MAINPINE, 0x3300,
4532 0, 0, pbn_b0_2_115200 },
4533 { /* IQ Express D4 */
4534 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4535 PCI_VENDOR_ID_MAINPINE, 0x3400,
4536 0, 0, pbn_b0_4_115200 },
4537 { /* IQ Express F4 */
4538 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4539 PCI_VENDOR_ID_MAINPINE, 0x3500,
4540 0, 0, pbn_b0_4_115200 },
4541 { /* IQ Express D8 */
4542 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4543 PCI_VENDOR_ID_MAINPINE, 0x3C00,
4544 0, 0, pbn_b0_8_115200 },
4545 { /* IQ Express F8 */
4546 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4547 PCI_VENDOR_ID_MAINPINE, 0x3D00,
4548 0, 0, pbn_b0_8_115200 },
4549
4550
4551 /*
4552 * PA Semi PA6T-1682M on-chip UART
4553 */
4554 { PCI_VENDOR_ID_PASEMI, 0xa004,
4555 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4556 pbn_pasemi_1682M },
4557
4558 /*
4559 * National Instruments
4560 */
4561 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
4562 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4563 pbn_b1_16_115200 },
4564 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
4565 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4566 pbn_b1_8_115200 },
4567 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
4568 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4569 pbn_b1_bt_4_115200 },
4570 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
4571 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4572 pbn_b1_bt_2_115200 },
4573 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
4574 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4575 pbn_b1_bt_4_115200 },
4576 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
4577 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4578 pbn_b1_bt_2_115200 },
4579 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
4580 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4581 pbn_b1_16_115200 },
4582 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
4583 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4584 pbn_b1_8_115200 },
4585 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
4586 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4587 pbn_b1_bt_4_115200 },
4588 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
4589 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4590 pbn_b1_bt_2_115200 },
4591 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
4592 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4593 pbn_b1_bt_4_115200 },
4594 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
4595 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4596 pbn_b1_bt_2_115200 },
4597 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
4598 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4599 pbn_ni8430_2 },
4600 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
4601 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4602 pbn_ni8430_2 },
4603 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
4604 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4605 pbn_ni8430_4 },
4606 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
4607 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4608 pbn_ni8430_4 },
4609 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
4610 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4611 pbn_ni8430_8 },
4612 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
4613 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4614 pbn_ni8430_8 },
4615 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
4616 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4617 pbn_ni8430_16 },
4618 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
4619 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4620 pbn_ni8430_16 },
4621 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
4622 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4623 pbn_ni8430_2 },
4624 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
4625 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4626 pbn_ni8430_2 },
4627 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
4628 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4629 pbn_ni8430_4 },
4630 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
4631 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4632 pbn_ni8430_4 },
4633
4634 /*
4635 * ADDI-DATA GmbH communication cards <info@addi-data.com>
4636 */
4637 { PCI_VENDOR_ID_ADDIDATA,
4638 PCI_DEVICE_ID_ADDIDATA_APCI7500,
4639 PCI_ANY_ID,
4640 PCI_ANY_ID,
4641 0,
4642 0,
4643 pbn_b0_4_115200 },
4644
4645 { PCI_VENDOR_ID_ADDIDATA,
4646 PCI_DEVICE_ID_ADDIDATA_APCI7420,
4647 PCI_ANY_ID,
4648 PCI_ANY_ID,
4649 0,
4650 0,
4651 pbn_b0_2_115200 },
4652
4653 { PCI_VENDOR_ID_ADDIDATA,
4654 PCI_DEVICE_ID_ADDIDATA_APCI7300,
4655 PCI_ANY_ID,
4656 PCI_ANY_ID,
4657 0,
4658 0,
4659 pbn_b0_1_115200 },
4660
4661 { PCI_VENDOR_ID_ADDIDATA_OLD,
4662 PCI_DEVICE_ID_ADDIDATA_APCI7800,
4663 PCI_ANY_ID,
4664 PCI_ANY_ID,
4665 0,
4666 0,
4667 pbn_b1_8_115200 },
4668
4669 { PCI_VENDOR_ID_ADDIDATA,
4670 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
4671 PCI_ANY_ID,
4672 PCI_ANY_ID,
4673 0,
4674 0,
4675 pbn_b0_4_115200 },
4676
4677 { PCI_VENDOR_ID_ADDIDATA,
4678 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
4679 PCI_ANY_ID,
4680 PCI_ANY_ID,
4681 0,
4682 0,
4683 pbn_b0_2_115200 },
4684
4685 { PCI_VENDOR_ID_ADDIDATA,
4686 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
4687 PCI_ANY_ID,
4688 PCI_ANY_ID,
4689 0,
4690 0,
4691 pbn_b0_1_115200 },
4692
4693 { PCI_VENDOR_ID_ADDIDATA,
4694 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
4695 PCI_ANY_ID,
4696 PCI_ANY_ID,
4697 0,
4698 0,
4699 pbn_b0_4_115200 },
4700
4701 { PCI_VENDOR_ID_ADDIDATA,
4702 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
4703 PCI_ANY_ID,
4704 PCI_ANY_ID,
4705 0,
4706 0,
4707 pbn_b0_2_115200 },
4708
4709 { PCI_VENDOR_ID_ADDIDATA,
4710 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
4711 PCI_ANY_ID,
4712 PCI_ANY_ID,
4713 0,
4714 0,
4715 pbn_b0_1_115200 },
4716
4717 { PCI_VENDOR_ID_ADDIDATA,
4718 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
4719 PCI_ANY_ID,
4720 PCI_ANY_ID,
4721 0,
4722 0,
4723 pbn_b0_8_115200 },
4724
4725 { PCI_VENDOR_ID_ADDIDATA,
4726 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
4727 PCI_ANY_ID,
4728 PCI_ANY_ID,
4729 0,
4730 0,
4731 pbn_ADDIDATA_PCIe_4_3906250 },
4732
4733 { PCI_VENDOR_ID_ADDIDATA,
4734 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
4735 PCI_ANY_ID,
4736 PCI_ANY_ID,
4737 0,
4738 0,
4739 pbn_ADDIDATA_PCIe_2_3906250 },
4740
4741 { PCI_VENDOR_ID_ADDIDATA,
4742 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
4743 PCI_ANY_ID,
4744 PCI_ANY_ID,
4745 0,
4746 0,
4747 pbn_ADDIDATA_PCIe_1_3906250 },
4748
4749 { PCI_VENDOR_ID_ADDIDATA,
4750 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
4751 PCI_ANY_ID,
4752 PCI_ANY_ID,
4753 0,
4754 0,
4755 pbn_ADDIDATA_PCIe_8_3906250 },
4756
4757 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
4758 PCI_VENDOR_ID_IBM, 0x0299,
4759 0, 0, pbn_b0_bt_2_115200 },
4760
4761 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
4762 0xA000, 0x1000,
4763 0, 0, pbn_b0_1_115200 },
4764
4765 /* the 9901 is a rebranded 9912 */
4766 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
4767 0xA000, 0x1000,
4768 0, 0, pbn_b0_1_115200 },
4769
4770 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
4771 0xA000, 0x1000,
4772 0, 0, pbn_b0_1_115200 },
4773
4774 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
4775 0xA000, 0x1000,
4776 0, 0, pbn_b0_1_115200 },
4777
4778 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4779 0xA000, 0x1000,
4780 0, 0, pbn_b0_1_115200 },
4781
4782 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4783 0xA000, 0x3002,
4784 0, 0, pbn_NETMOS9900_2s_115200 },
4785
4786 /*
4787 * Best Connectivity and Rosewill PCI Multi I/O cards
4788 */
4789
4790 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4791 0xA000, 0x1000,
4792 0, 0, pbn_b0_1_115200 },
4793
4794 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4795 0xA000, 0x3002,
4796 0, 0, pbn_b0_bt_2_115200 },
4797
4798 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4799 0xA000, 0x3004,
4800 0, 0, pbn_b0_bt_4_115200 },
4801 /* Intel CE4100 */
4802 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
4803 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4804 pbn_ce4100_1_115200 },
4805
4806 /*
4807 * Cronyx Omega PCI
4808 */
4809 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
4810 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4811 pbn_omegapci },
4812
4813 /*
4814 * Broadcom TruManage
4815 */
4816 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
4817 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4818 pbn_brcm_trumanage },
4819
4820 /*
4821 * AgeStar as-prs2-009
4822 */
4823 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
4824 PCI_ANY_ID, PCI_ANY_ID,
4825 0, 0, pbn_b0_bt_2_115200 },
4826
4827 /*
4828 * WCH CH353 series devices: The 2S1P is handled by parport_serial
4829 * so not listed here.
4830 */
4831 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
4832 PCI_ANY_ID, PCI_ANY_ID,
4833 0, 0, pbn_b0_bt_4_115200 },
4834
4835 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
4836 PCI_ANY_ID, PCI_ANY_ID,
4837 0, 0, pbn_b0_bt_2_115200 },
4838
4839 /*
4840 * Commtech, Inc. Fastcom adapters
4841 */
4842 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
4843 PCI_ANY_ID, PCI_ANY_ID,
4844 0,
4845 0, pbn_b0_2_1152000_200 },
4846 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
4847 PCI_ANY_ID, PCI_ANY_ID,
4848 0,
4849 0, pbn_b0_4_1152000_200 },
4850 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
4851 PCI_ANY_ID, PCI_ANY_ID,
4852 0,
4853 0, pbn_b0_4_1152000_200 },
4854 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
4855 PCI_ANY_ID, PCI_ANY_ID,
4856 0,
4857 0, pbn_b0_8_1152000_200 },
4858 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
4859 PCI_ANY_ID, PCI_ANY_ID,
4860 0,
4861 0, pbn_exar_XR17V352 },
4862 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
4863 PCI_ANY_ID, PCI_ANY_ID,
4864 0,
4865 0, pbn_exar_XR17V354 },
4866 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
4867 PCI_ANY_ID, PCI_ANY_ID,
4868 0,
4869 0, pbn_exar_XR17V358 },
4870
4871 /*
4872 * These entries match devices with class COMMUNICATION_SERIAL,
4873 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
4874 */
4875 { PCI_ANY_ID, PCI_ANY_ID,
4876 PCI_ANY_ID, PCI_ANY_ID,
4877 PCI_CLASS_COMMUNICATION_SERIAL << 8,
4878 0xffff00, pbn_default },
4879 { PCI_ANY_ID, PCI_ANY_ID,
4880 PCI_ANY_ID, PCI_ANY_ID,
4881 PCI_CLASS_COMMUNICATION_MODEM << 8,
4882 0xffff00, pbn_default },
4883 { PCI_ANY_ID, PCI_ANY_ID,
4884 PCI_ANY_ID, PCI_ANY_ID,
4885 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
4886 0xffff00, pbn_default },
4887 { 0, }
4888 };
4889
4890 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
4891 pci_channel_state_t state)
4892 {
4893 struct serial_private *priv = pci_get_drvdata(dev);
4894
4895 if (state == pci_channel_io_perm_failure)
4896 return PCI_ERS_RESULT_DISCONNECT;
4897
4898 if (priv)
4899 pciserial_suspend_ports(priv);
4900
4901 pci_disable_device(dev);
4902
4903 return PCI_ERS_RESULT_NEED_RESET;
4904 }
4905
4906 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
4907 {
4908 int rc;
4909
4910 rc = pci_enable_device(dev);
4911
4912 if (rc)
4913 return PCI_ERS_RESULT_DISCONNECT;
4914
4915 pci_restore_state(dev);
4916 pci_save_state(dev);
4917
4918 return PCI_ERS_RESULT_RECOVERED;
4919 }
4920
4921 static void serial8250_io_resume(struct pci_dev *dev)
4922 {
4923 struct serial_private *priv = pci_get_drvdata(dev);
4924
4925 if (priv)
4926 pciserial_resume_ports(priv);
4927 }
4928
4929 static const struct pci_error_handlers serial8250_err_handler = {
4930 .error_detected = serial8250_io_error_detected,
4931 .slot_reset = serial8250_io_slot_reset,
4932 .resume = serial8250_io_resume,
4933 };
4934
4935 static struct pci_driver serial_pci_driver = {
4936 .name = "serial",
4937 .probe = pciserial_init_one,
4938 .remove = pciserial_remove_one,
4939 #ifdef CONFIG_PM
4940 .suspend = pciserial_suspend_one,
4941 .resume = pciserial_resume_one,
4942 #endif
4943 .id_table = serial_pci_tbl,
4944 .err_handler = &serial8250_err_handler,
4945 };
4946
4947 module_pci_driver(serial_pci_driver);
4948
4949 MODULE_LICENSE("GPL");
4950 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
4951 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Linux kernel - Deliverables
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