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Merge git://git.kernel.org/pub/scm/linux/kernel/git/nab/target-pending
[deliverable/linux.git] / drivers / tty / serial / 8250 / 8250_pci.c
1 /*
2 * Probe module for 8250/16550-type PCI serial ports.
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King, All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
11 */
12 #undef DEBUG
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/delay.h>
19 #include <linux/tty.h>
20 #include <linux/serial_reg.h>
21 #include <linux/serial_core.h>
22 #include <linux/8250_pci.h>
23 #include <linux/bitops.h>
24
25 #include <asm/byteorder.h>
26 #include <asm/io.h>
27
28 #include <linux/dmaengine.h>
29 #include <linux/platform_data/dma-dw.h>
30
31 #include "8250.h"
32
33 /*
34 * init function returns:
35 * > 0 - number of ports
36 * = 0 - use board->num_ports
37 * < 0 - error
38 */
39 struct pci_serial_quirk {
40 u32 vendor;
41 u32 device;
42 u32 subvendor;
43 u32 subdevice;
44 int (*probe)(struct pci_dev *dev);
45 int (*init)(struct pci_dev *dev);
46 int (*setup)(struct serial_private *,
47 const struct pciserial_board *,
48 struct uart_8250_port *, int);
49 void (*exit)(struct pci_dev *dev);
50 };
51
52 #define PCI_NUM_BAR_RESOURCES 6
53
54 struct serial_private {
55 struct pci_dev *dev;
56 unsigned int nr;
57 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
58 struct pci_serial_quirk *quirk;
59 int line[0];
60 };
61
62 static int pci_default_setup(struct serial_private*,
63 const struct pciserial_board*, struct uart_8250_port *, int);
64
65 static void moan_device(const char *str, struct pci_dev *dev)
66 {
67 dev_err(&dev->dev,
68 "%s: %s\n"
69 "Please send the output of lspci -vv, this\n"
70 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
71 "manufacturer and name of serial board or\n"
72 "modem board to <linux-serial@vger.kernel.org>.\n",
73 pci_name(dev), str, dev->vendor, dev->device,
74 dev->subsystem_vendor, dev->subsystem_device);
75 }
76
77 static int
78 setup_port(struct serial_private *priv, struct uart_8250_port *port,
79 int bar, int offset, int regshift)
80 {
81 struct pci_dev *dev = priv->dev;
82
83 if (bar >= PCI_NUM_BAR_RESOURCES)
84 return -EINVAL;
85
86 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
87 if (!priv->remapped_bar[bar])
88 priv->remapped_bar[bar] = pci_ioremap_bar(dev, bar);
89 if (!priv->remapped_bar[bar])
90 return -ENOMEM;
91
92 port->port.iotype = UPIO_MEM;
93 port->port.iobase = 0;
94 port->port.mapbase = pci_resource_start(dev, bar) + offset;
95 port->port.membase = priv->remapped_bar[bar] + offset;
96 port->port.regshift = regshift;
97 } else {
98 port->port.iotype = UPIO_PORT;
99 port->port.iobase = pci_resource_start(dev, bar) + offset;
100 port->port.mapbase = 0;
101 port->port.membase = NULL;
102 port->port.regshift = 0;
103 }
104 return 0;
105 }
106
107 /*
108 * ADDI-DATA GmbH communication cards <info@addi-data.com>
109 */
110 static int addidata_apci7800_setup(struct serial_private *priv,
111 const struct pciserial_board *board,
112 struct uart_8250_port *port, int idx)
113 {
114 unsigned int bar = 0, offset = board->first_offset;
115 bar = FL_GET_BASE(board->flags);
116
117 if (idx < 2) {
118 offset += idx * board->uart_offset;
119 } else if ((idx >= 2) && (idx < 4)) {
120 bar += 1;
121 offset += ((idx - 2) * board->uart_offset);
122 } else if ((idx >= 4) && (idx < 6)) {
123 bar += 2;
124 offset += ((idx - 4) * board->uart_offset);
125 } else if (idx >= 6) {
126 bar += 3;
127 offset += ((idx - 6) * board->uart_offset);
128 }
129
130 return setup_port(priv, port, bar, offset, board->reg_shift);
131 }
132
133 /*
134 * AFAVLAB uses a different mixture of BARs and offsets
135 * Not that ugly ;) -- HW
136 */
137 static int
138 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
139 struct uart_8250_port *port, int idx)
140 {
141 unsigned int bar, offset = board->first_offset;
142
143 bar = FL_GET_BASE(board->flags);
144 if (idx < 4)
145 bar += idx;
146 else {
147 bar = 4;
148 offset += (idx - 4) * board->uart_offset;
149 }
150
151 return setup_port(priv, port, bar, offset, board->reg_shift);
152 }
153
154 /*
155 * HP's Remote Management Console. The Diva chip came in several
156 * different versions. N-class, L2000 and A500 have two Diva chips, each
157 * with 3 UARTs (the third UART on the second chip is unused). Superdome
158 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
159 * one Diva chip, but it has been expanded to 5 UARTs.
160 */
161 static int pci_hp_diva_init(struct pci_dev *dev)
162 {
163 int rc = 0;
164
165 switch (dev->subsystem_device) {
166 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
167 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
168 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
169 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
170 rc = 3;
171 break;
172 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
173 rc = 2;
174 break;
175 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
176 rc = 4;
177 break;
178 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
179 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
180 rc = 1;
181 break;
182 }
183
184 return rc;
185 }
186
187 /*
188 * HP's Diva chip puts the 4th/5th serial port further out, and
189 * some serial ports are supposed to be hidden on certain models.
190 */
191 static int
192 pci_hp_diva_setup(struct serial_private *priv,
193 const struct pciserial_board *board,
194 struct uart_8250_port *port, int idx)
195 {
196 unsigned int offset = board->first_offset;
197 unsigned int bar = FL_GET_BASE(board->flags);
198
199 switch (priv->dev->subsystem_device) {
200 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
201 if (idx == 3)
202 idx++;
203 break;
204 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
205 if (idx > 0)
206 idx++;
207 if (idx > 2)
208 idx++;
209 break;
210 }
211 if (idx > 2)
212 offset = 0x18;
213
214 offset += idx * board->uart_offset;
215
216 return setup_port(priv, port, bar, offset, board->reg_shift);
217 }
218
219 /*
220 * Added for EKF Intel i960 serial boards
221 */
222 static int pci_inteli960ni_init(struct pci_dev *dev)
223 {
224 u32 oldval;
225
226 if (!(dev->subsystem_device & 0x1000))
227 return -ENODEV;
228
229 /* is firmware started? */
230 pci_read_config_dword(dev, 0x44, &oldval);
231 if (oldval == 0x00001000L) { /* RESET value */
232 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
233 return -ENODEV;
234 }
235 return 0;
236 }
237
238 /*
239 * Some PCI serial cards using the PLX 9050 PCI interface chip require
240 * that the card interrupt be explicitly enabled or disabled. This
241 * seems to be mainly needed on card using the PLX which also use I/O
242 * mapped memory.
243 */
244 static int pci_plx9050_init(struct pci_dev *dev)
245 {
246 u8 irq_config;
247 void __iomem *p;
248
249 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
250 moan_device("no memory in bar 0", dev);
251 return 0;
252 }
253
254 irq_config = 0x41;
255 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
256 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
257 irq_config = 0x43;
258
259 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
260 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
261 /*
262 * As the megawolf cards have the int pins active
263 * high, and have 2 UART chips, both ints must be
264 * enabled on the 9050. Also, the UARTS are set in
265 * 16450 mode by default, so we have to enable the
266 * 16C950 'enhanced' mode so that we can use the
267 * deep FIFOs
268 */
269 irq_config = 0x5b;
270 /*
271 * enable/disable interrupts
272 */
273 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
274 if (p == NULL)
275 return -ENOMEM;
276 writel(irq_config, p + 0x4c);
277
278 /*
279 * Read the register back to ensure that it took effect.
280 */
281 readl(p + 0x4c);
282 iounmap(p);
283
284 return 0;
285 }
286
287 static void pci_plx9050_exit(struct pci_dev *dev)
288 {
289 u8 __iomem *p;
290
291 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
292 return;
293
294 /*
295 * disable interrupts
296 */
297 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
298 if (p != NULL) {
299 writel(0, p + 0x4c);
300
301 /*
302 * Read the register back to ensure that it took effect.
303 */
304 readl(p + 0x4c);
305 iounmap(p);
306 }
307 }
308
309 #define NI8420_INT_ENABLE_REG 0x38
310 #define NI8420_INT_ENABLE_BIT 0x2000
311
312 static void pci_ni8420_exit(struct pci_dev *dev)
313 {
314 void __iomem *p;
315 unsigned int bar = 0;
316
317 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
318 moan_device("no memory in bar", dev);
319 return;
320 }
321
322 p = pci_ioremap_bar(dev, bar);
323 if (p == NULL)
324 return;
325
326 /* Disable the CPU Interrupt */
327 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
328 p + NI8420_INT_ENABLE_REG);
329 iounmap(p);
330 }
331
332
333 /* MITE registers */
334 #define MITE_IOWBSR1 0xc4
335 #define MITE_IOWCR1 0xf4
336 #define MITE_LCIMR1 0x08
337 #define MITE_LCIMR2 0x10
338
339 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
340
341 static void pci_ni8430_exit(struct pci_dev *dev)
342 {
343 void __iomem *p;
344 unsigned int bar = 0;
345
346 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
347 moan_device("no memory in bar", dev);
348 return;
349 }
350
351 p = pci_ioremap_bar(dev, bar);
352 if (p == NULL)
353 return;
354
355 /* Disable the CPU Interrupt */
356 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
357 iounmap(p);
358 }
359
360 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
361 static int
362 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
363 struct uart_8250_port *port, int idx)
364 {
365 unsigned int bar, offset = board->first_offset;
366
367 bar = 0;
368
369 if (idx < 4) {
370 /* first four channels map to 0, 0x100, 0x200, 0x300 */
371 offset += idx * board->uart_offset;
372 } else if (idx < 8) {
373 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
374 offset += idx * board->uart_offset + 0xC00;
375 } else /* we have only 8 ports on PMC-OCTALPRO */
376 return 1;
377
378 return setup_port(priv, port, bar, offset, board->reg_shift);
379 }
380
381 /*
382 * This does initialization for PMC OCTALPRO cards:
383 * maps the device memory, resets the UARTs (needed, bc
384 * if the module is removed and inserted again, the card
385 * is in the sleep mode) and enables global interrupt.
386 */
387
388 /* global control register offset for SBS PMC-OctalPro */
389 #define OCT_REG_CR_OFF 0x500
390
391 static int sbs_init(struct pci_dev *dev)
392 {
393 u8 __iomem *p;
394
395 p = pci_ioremap_bar(dev, 0);
396
397 if (p == NULL)
398 return -ENOMEM;
399 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
400 writeb(0x10, p + OCT_REG_CR_OFF);
401 udelay(50);
402 writeb(0x0, p + OCT_REG_CR_OFF);
403
404 /* Set bit-2 (INTENABLE) of Control Register */
405 writeb(0x4, p + OCT_REG_CR_OFF);
406 iounmap(p);
407
408 return 0;
409 }
410
411 /*
412 * Disables the global interrupt of PMC-OctalPro
413 */
414
415 static void sbs_exit(struct pci_dev *dev)
416 {
417 u8 __iomem *p;
418
419 p = pci_ioremap_bar(dev, 0);
420 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
421 if (p != NULL)
422 writeb(0, p + OCT_REG_CR_OFF);
423 iounmap(p);
424 }
425
426 /*
427 * SIIG serial cards have an PCI interface chip which also controls
428 * the UART clocking frequency. Each UART can be clocked independently
429 * (except cards equipped with 4 UARTs) and initial clocking settings
430 * are stored in the EEPROM chip. It can cause problems because this
431 * version of serial driver doesn't support differently clocked UART's
432 * on single PCI card. To prevent this, initialization functions set
433 * high frequency clocking for all UART's on given card. It is safe (I
434 * hope) because it doesn't touch EEPROM settings to prevent conflicts
435 * with other OSes (like M$ DOS).
436 *
437 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
438 *
439 * There is two family of SIIG serial cards with different PCI
440 * interface chip and different configuration methods:
441 * - 10x cards have control registers in IO and/or memory space;
442 * - 20x cards have control registers in standard PCI configuration space.
443 *
444 * Note: all 10x cards have PCI device ids 0x10..
445 * all 20x cards have PCI device ids 0x20..
446 *
447 * There are also Quartet Serial cards which use Oxford Semiconductor
448 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
449 *
450 * Note: some SIIG cards are probed by the parport_serial object.
451 */
452
453 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
454 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
455
456 static int pci_siig10x_init(struct pci_dev *dev)
457 {
458 u16 data;
459 void __iomem *p;
460
461 switch (dev->device & 0xfff8) {
462 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
463 data = 0xffdf;
464 break;
465 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
466 data = 0xf7ff;
467 break;
468 default: /* 1S1P, 4S */
469 data = 0xfffb;
470 break;
471 }
472
473 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
474 if (p == NULL)
475 return -ENOMEM;
476
477 writew(readw(p + 0x28) & data, p + 0x28);
478 readw(p + 0x28);
479 iounmap(p);
480 return 0;
481 }
482
483 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
484 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
485
486 static int pci_siig20x_init(struct pci_dev *dev)
487 {
488 u8 data;
489
490 /* Change clock frequency for the first UART. */
491 pci_read_config_byte(dev, 0x6f, &data);
492 pci_write_config_byte(dev, 0x6f, data & 0xef);
493
494 /* If this card has 2 UART, we have to do the same with second UART. */
495 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
496 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
497 pci_read_config_byte(dev, 0x73, &data);
498 pci_write_config_byte(dev, 0x73, data & 0xef);
499 }
500 return 0;
501 }
502
503 static int pci_siig_init(struct pci_dev *dev)
504 {
505 unsigned int type = dev->device & 0xff00;
506
507 if (type == 0x1000)
508 return pci_siig10x_init(dev);
509 else if (type == 0x2000)
510 return pci_siig20x_init(dev);
511
512 moan_device("Unknown SIIG card", dev);
513 return -ENODEV;
514 }
515
516 static int pci_siig_setup(struct serial_private *priv,
517 const struct pciserial_board *board,
518 struct uart_8250_port *port, int idx)
519 {
520 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
521
522 if (idx > 3) {
523 bar = 4;
524 offset = (idx - 4) * 8;
525 }
526
527 return setup_port(priv, port, bar, offset, 0);
528 }
529
530 /*
531 * Timedia has an explosion of boards, and to avoid the PCI table from
532 * growing *huge*, we use this function to collapse some 70 entries
533 * in the PCI table into one, for sanity's and compactness's sake.
534 */
535 static const unsigned short timedia_single_port[] = {
536 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
537 };
538
539 static const unsigned short timedia_dual_port[] = {
540 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
541 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
542 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
543 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
544 0xD079, 0
545 };
546
547 static const unsigned short timedia_quad_port[] = {
548 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
549 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
550 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
551 0xB157, 0
552 };
553
554 static const unsigned short timedia_eight_port[] = {
555 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
556 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
557 };
558
559 static const struct timedia_struct {
560 int num;
561 const unsigned short *ids;
562 } timedia_data[] = {
563 { 1, timedia_single_port },
564 { 2, timedia_dual_port },
565 { 4, timedia_quad_port },
566 { 8, timedia_eight_port }
567 };
568
569 /*
570 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
571 * listing them individually, this driver merely grabs them all with
572 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
573 * and should be left free to be claimed by parport_serial instead.
574 */
575 static int pci_timedia_probe(struct pci_dev *dev)
576 {
577 /*
578 * Check the third digit of the subdevice ID
579 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
580 */
581 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
582 dev_info(&dev->dev,
583 "ignoring Timedia subdevice %04x for parport_serial\n",
584 dev->subsystem_device);
585 return -ENODEV;
586 }
587
588 return 0;
589 }
590
591 static int pci_timedia_init(struct pci_dev *dev)
592 {
593 const unsigned short *ids;
594 int i, j;
595
596 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
597 ids = timedia_data[i].ids;
598 for (j = 0; ids[j]; j++)
599 if (dev->subsystem_device == ids[j])
600 return timedia_data[i].num;
601 }
602 return 0;
603 }
604
605 /*
606 * Timedia/SUNIX uses a mixture of BARs and offsets
607 * Ugh, this is ugly as all hell --- TYT
608 */
609 static int
610 pci_timedia_setup(struct serial_private *priv,
611 const struct pciserial_board *board,
612 struct uart_8250_port *port, int idx)
613 {
614 unsigned int bar = 0, offset = board->first_offset;
615
616 switch (idx) {
617 case 0:
618 bar = 0;
619 break;
620 case 1:
621 offset = board->uart_offset;
622 bar = 0;
623 break;
624 case 2:
625 bar = 1;
626 break;
627 case 3:
628 offset = board->uart_offset;
629 /* FALLTHROUGH */
630 case 4: /* BAR 2 */
631 case 5: /* BAR 3 */
632 case 6: /* BAR 4 */
633 case 7: /* BAR 5 */
634 bar = idx - 2;
635 }
636
637 return setup_port(priv, port, bar, offset, board->reg_shift);
638 }
639
640 /*
641 * Some Titan cards are also a little weird
642 */
643 static int
644 titan_400l_800l_setup(struct serial_private *priv,
645 const struct pciserial_board *board,
646 struct uart_8250_port *port, int idx)
647 {
648 unsigned int bar, offset = board->first_offset;
649
650 switch (idx) {
651 case 0:
652 bar = 1;
653 break;
654 case 1:
655 bar = 2;
656 break;
657 default:
658 bar = 4;
659 offset = (idx - 2) * board->uart_offset;
660 }
661
662 return setup_port(priv, port, bar, offset, board->reg_shift);
663 }
664
665 static int pci_xircom_init(struct pci_dev *dev)
666 {
667 msleep(100);
668 return 0;
669 }
670
671 static int pci_ni8420_init(struct pci_dev *dev)
672 {
673 void __iomem *p;
674 unsigned int bar = 0;
675
676 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
677 moan_device("no memory in bar", dev);
678 return 0;
679 }
680
681 p = pci_ioremap_bar(dev, bar);
682 if (p == NULL)
683 return -ENOMEM;
684
685 /* Enable CPU Interrupt */
686 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
687 p + NI8420_INT_ENABLE_REG);
688
689 iounmap(p);
690 return 0;
691 }
692
693 #define MITE_IOWBSR1_WSIZE 0xa
694 #define MITE_IOWBSR1_WIN_OFFSET 0x800
695 #define MITE_IOWBSR1_WENAB (1 << 7)
696 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
697 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
698 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
699
700 static int pci_ni8430_init(struct pci_dev *dev)
701 {
702 void __iomem *p;
703 struct pci_bus_region region;
704 u32 device_window;
705 unsigned int bar = 0;
706
707 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
708 moan_device("no memory in bar", dev);
709 return 0;
710 }
711
712 p = pci_ioremap_bar(dev, bar);
713 if (p == NULL)
714 return -ENOMEM;
715
716 /*
717 * Set device window address and size in BAR0, while acknowledging that
718 * the resource structure may contain a translated address that differs
719 * from the address the device responds to.
720 */
721 pcibios_resource_to_bus(dev->bus, &region, &dev->resource[bar]);
722 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
723 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
724 writel(device_window, p + MITE_IOWBSR1);
725
726 /* Set window access to go to RAMSEL IO address space */
727 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
728 p + MITE_IOWCR1);
729
730 /* Enable IO Bus Interrupt 0 */
731 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
732
733 /* Enable CPU Interrupt */
734 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
735
736 iounmap(p);
737 return 0;
738 }
739
740 /* UART Port Control Register */
741 #define NI8430_PORTCON 0x0f
742 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
743
744 static int
745 pci_ni8430_setup(struct serial_private *priv,
746 const struct pciserial_board *board,
747 struct uart_8250_port *port, int idx)
748 {
749 struct pci_dev *dev = priv->dev;
750 void __iomem *p;
751 unsigned int bar, offset = board->first_offset;
752
753 if (idx >= board->num_ports)
754 return 1;
755
756 bar = FL_GET_BASE(board->flags);
757 offset += idx * board->uart_offset;
758
759 p = pci_ioremap_bar(dev, bar);
760 if (!p)
761 return -ENOMEM;
762
763 /* enable the transceiver */
764 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
765 p + offset + NI8430_PORTCON);
766
767 iounmap(p);
768
769 return setup_port(priv, port, bar, offset, board->reg_shift);
770 }
771
772 static int pci_netmos_9900_setup(struct serial_private *priv,
773 const struct pciserial_board *board,
774 struct uart_8250_port *port, int idx)
775 {
776 unsigned int bar;
777
778 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
779 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
780 /* netmos apparently orders BARs by datasheet layout, so serial
781 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
782 */
783 bar = 3 * idx;
784
785 return setup_port(priv, port, bar, 0, board->reg_shift);
786 } else {
787 return pci_default_setup(priv, board, port, idx);
788 }
789 }
790
791 /* the 99xx series comes with a range of device IDs and a variety
792 * of capabilities:
793 *
794 * 9900 has varying capabilities and can cascade to sub-controllers
795 * (cascading should be purely internal)
796 * 9904 is hardwired with 4 serial ports
797 * 9912 and 9922 are hardwired with 2 serial ports
798 */
799 static int pci_netmos_9900_numports(struct pci_dev *dev)
800 {
801 unsigned int c = dev->class;
802 unsigned int pi;
803 unsigned short sub_serports;
804
805 pi = (c & 0xff);
806
807 if (pi == 2) {
808 return 1;
809 } else if ((pi == 0) &&
810 (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
811 /* two possibilities: 0x30ps encodes number of parallel and
812 * serial ports, or 0x1000 indicates *something*. This is not
813 * immediately obvious, since the 2s1p+4s configuration seems
814 * to offer all functionality on functions 0..2, while still
815 * advertising the same function 3 as the 4s+2s1p config.
816 */
817 sub_serports = dev->subsystem_device & 0xf;
818 if (sub_serports > 0) {
819 return sub_serports;
820 } else {
821 dev_err(&dev->dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
822 return 0;
823 }
824 }
825
826 moan_device("unknown NetMos/Mostech program interface", dev);
827 return 0;
828 }
829
830 static int pci_netmos_init(struct pci_dev *dev)
831 {
832 /* subdevice 0x00PS means <P> parallel, <S> serial */
833 unsigned int num_serial = dev->subsystem_device & 0xf;
834
835 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
836 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
837 return 0;
838
839 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
840 dev->subsystem_device == 0x0299)
841 return 0;
842
843 switch (dev->device) { /* FALLTHROUGH on all */
844 case PCI_DEVICE_ID_NETMOS_9904:
845 case PCI_DEVICE_ID_NETMOS_9912:
846 case PCI_DEVICE_ID_NETMOS_9922:
847 case PCI_DEVICE_ID_NETMOS_9900:
848 num_serial = pci_netmos_9900_numports(dev);
849 break;
850
851 default:
852 if (num_serial == 0 ) {
853 moan_device("unknown NetMos/Mostech device", dev);
854 }
855 }
856
857 if (num_serial == 0)
858 return -ENODEV;
859
860 return num_serial;
861 }
862
863 /*
864 * These chips are available with optionally one parallel port and up to
865 * two serial ports. Unfortunately they all have the same product id.
866 *
867 * Basic configuration is done over a region of 32 I/O ports. The base
868 * ioport is called INTA or INTC, depending on docs/other drivers.
869 *
870 * The region of the 32 I/O ports is configured in POSIO0R...
871 */
872
873 /* registers */
874 #define ITE_887x_MISCR 0x9c
875 #define ITE_887x_INTCBAR 0x78
876 #define ITE_887x_UARTBAR 0x7c
877 #define ITE_887x_PS0BAR 0x10
878 #define ITE_887x_POSIO0 0x60
879
880 /* I/O space size */
881 #define ITE_887x_IOSIZE 32
882 /* I/O space size (bits 26-24; 8 bytes = 011b) */
883 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
884 /* I/O space size (bits 26-24; 32 bytes = 101b) */
885 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
886 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
887 #define ITE_887x_POSIO_SPEED (3 << 29)
888 /* enable IO_Space bit */
889 #define ITE_887x_POSIO_ENABLE (1 << 31)
890
891 static int pci_ite887x_init(struct pci_dev *dev)
892 {
893 /* inta_addr are the configuration addresses of the ITE */
894 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
895 0x200, 0x280, 0 };
896 int ret, i, type;
897 struct resource *iobase = NULL;
898 u32 miscr, uartbar, ioport;
899
900 /* search for the base-ioport */
901 i = 0;
902 while (inta_addr[i] && iobase == NULL) {
903 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
904 "ite887x");
905 if (iobase != NULL) {
906 /* write POSIO0R - speed | size | ioport */
907 pci_write_config_dword(dev, ITE_887x_POSIO0,
908 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
909 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
910 /* write INTCBAR - ioport */
911 pci_write_config_dword(dev, ITE_887x_INTCBAR,
912 inta_addr[i]);
913 ret = inb(inta_addr[i]);
914 if (ret != 0xff) {
915 /* ioport connected */
916 break;
917 }
918 release_region(iobase->start, ITE_887x_IOSIZE);
919 iobase = NULL;
920 }
921 i++;
922 }
923
924 if (!inta_addr[i]) {
925 dev_err(&dev->dev, "ite887x: could not find iobase\n");
926 return -ENODEV;
927 }
928
929 /* start of undocumented type checking (see parport_pc.c) */
930 type = inb(iobase->start + 0x18) & 0x0f;
931
932 switch (type) {
933 case 0x2: /* ITE8871 (1P) */
934 case 0xa: /* ITE8875 (1P) */
935 ret = 0;
936 break;
937 case 0xe: /* ITE8872 (2S1P) */
938 ret = 2;
939 break;
940 case 0x6: /* ITE8873 (1S) */
941 ret = 1;
942 break;
943 case 0x8: /* ITE8874 (2S) */
944 ret = 2;
945 break;
946 default:
947 moan_device("Unknown ITE887x", dev);
948 ret = -ENODEV;
949 }
950
951 /* configure all serial ports */
952 for (i = 0; i < ret; i++) {
953 /* read the I/O port from the device */
954 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
955 &ioport);
956 ioport &= 0x0000FF00; /* the actual base address */
957 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
958 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
959 ITE_887x_POSIO_IOSIZE_8 | ioport);
960
961 /* write the ioport to the UARTBAR */
962 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
963 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
964 uartbar |= (ioport << (16 * i)); /* set the ioport */
965 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
966
967 /* get current config */
968 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
969 /* disable interrupts (UARTx_Routing[3:0]) */
970 miscr &= ~(0xf << (12 - 4 * i));
971 /* activate the UART (UARTx_En) */
972 miscr |= 1 << (23 - i);
973 /* write new config with activated UART */
974 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
975 }
976
977 if (ret <= 0) {
978 /* the device has no UARTs if we get here */
979 release_region(iobase->start, ITE_887x_IOSIZE);
980 }
981
982 return ret;
983 }
984
985 static void pci_ite887x_exit(struct pci_dev *dev)
986 {
987 u32 ioport;
988 /* the ioport is bit 0-15 in POSIO0R */
989 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
990 ioport &= 0xffff;
991 release_region(ioport, ITE_887x_IOSIZE);
992 }
993
994 /*
995 * EndRun Technologies.
996 * Determine the number of ports available on the device.
997 */
998 #define PCI_VENDOR_ID_ENDRUN 0x7401
999 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1000
1001 static int pci_endrun_init(struct pci_dev *dev)
1002 {
1003 u8 __iomem *p;
1004 unsigned long deviceID;
1005 unsigned int number_uarts = 0;
1006
1007 /* EndRun device is all 0xexxx */
1008 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1009 (dev->device & 0xf000) != 0xe000)
1010 return 0;
1011
1012 p = pci_iomap(dev, 0, 5);
1013 if (p == NULL)
1014 return -ENOMEM;
1015
1016 deviceID = ioread32(p);
1017 /* EndRun device */
1018 if (deviceID == 0x07000200) {
1019 number_uarts = ioread8(p + 4);
1020 dev_dbg(&dev->dev,
1021 "%d ports detected on EndRun PCI Express device\n",
1022 number_uarts);
1023 }
1024 pci_iounmap(dev, p);
1025 return number_uarts;
1026 }
1027
1028 /*
1029 * Oxford Semiconductor Inc.
1030 * Check that device is part of the Tornado range of devices, then determine
1031 * the number of ports available on the device.
1032 */
1033 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1034 {
1035 u8 __iomem *p;
1036 unsigned long deviceID;
1037 unsigned int number_uarts = 0;
1038
1039 /* OxSemi Tornado devices are all 0xCxxx */
1040 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1041 (dev->device & 0xF000) != 0xC000)
1042 return 0;
1043
1044 p = pci_iomap(dev, 0, 5);
1045 if (p == NULL)
1046 return -ENOMEM;
1047
1048 deviceID = ioread32(p);
1049 /* Tornado device */
1050 if (deviceID == 0x07000200) {
1051 number_uarts = ioread8(p + 4);
1052 dev_dbg(&dev->dev,
1053 "%d ports detected on Oxford PCI Express device\n",
1054 number_uarts);
1055 }
1056 pci_iounmap(dev, p);
1057 return number_uarts;
1058 }
1059
1060 static int pci_asix_setup(struct serial_private *priv,
1061 const struct pciserial_board *board,
1062 struct uart_8250_port *port, int idx)
1063 {
1064 port->bugs |= UART_BUG_PARITY;
1065 return pci_default_setup(priv, board, port, idx);
1066 }
1067
1068 /* Quatech devices have their own extra interface features */
1069
1070 struct quatech_feature {
1071 u16 devid;
1072 bool amcc;
1073 };
1074
1075 #define QPCR_TEST_FOR1 0x3F
1076 #define QPCR_TEST_GET1 0x00
1077 #define QPCR_TEST_FOR2 0x40
1078 #define QPCR_TEST_GET2 0x40
1079 #define QPCR_TEST_FOR3 0x80
1080 #define QPCR_TEST_GET3 0x40
1081 #define QPCR_TEST_FOR4 0xC0
1082 #define QPCR_TEST_GET4 0x80
1083
1084 #define QOPR_CLOCK_X1 0x0000
1085 #define QOPR_CLOCK_X2 0x0001
1086 #define QOPR_CLOCK_X4 0x0002
1087 #define QOPR_CLOCK_X8 0x0003
1088 #define QOPR_CLOCK_RATE_MASK 0x0003
1089
1090
1091 static struct quatech_feature quatech_cards[] = {
1092 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1093 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1094 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1095 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1096 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1097 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1098 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1099 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1100 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1101 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1102 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1103 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1104 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1105 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1106 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1107 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1108 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1109 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1110 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1111 { 0, }
1112 };
1113
1114 static int pci_quatech_amcc(u16 devid)
1115 {
1116 struct quatech_feature *qf = &quatech_cards[0];
1117 while (qf->devid) {
1118 if (qf->devid == devid)
1119 return qf->amcc;
1120 qf++;
1121 }
1122 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1123 return 0;
1124 };
1125
1126 static int pci_quatech_rqopr(struct uart_8250_port *port)
1127 {
1128 unsigned long base = port->port.iobase;
1129 u8 LCR, val;
1130
1131 LCR = inb(base + UART_LCR);
1132 outb(0xBF, base + UART_LCR);
1133 val = inb(base + UART_SCR);
1134 outb(LCR, base + UART_LCR);
1135 return val;
1136 }
1137
1138 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1139 {
1140 unsigned long base = port->port.iobase;
1141 u8 LCR, val;
1142
1143 LCR = inb(base + UART_LCR);
1144 outb(0xBF, base + UART_LCR);
1145 val = inb(base + UART_SCR);
1146 outb(qopr, base + UART_SCR);
1147 outb(LCR, base + UART_LCR);
1148 }
1149
1150 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1151 {
1152 unsigned long base = port->port.iobase;
1153 u8 LCR, val, qmcr;
1154
1155 LCR = inb(base + UART_LCR);
1156 outb(0xBF, base + UART_LCR);
1157 val = inb(base + UART_SCR);
1158 outb(val | 0x10, base + UART_SCR);
1159 qmcr = inb(base + UART_MCR);
1160 outb(val, base + UART_SCR);
1161 outb(LCR, base + UART_LCR);
1162
1163 return qmcr;
1164 }
1165
1166 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1167 {
1168 unsigned long base = port->port.iobase;
1169 u8 LCR, val;
1170
1171 LCR = inb(base + UART_LCR);
1172 outb(0xBF, base + UART_LCR);
1173 val = inb(base + UART_SCR);
1174 outb(val | 0x10, base + UART_SCR);
1175 outb(qmcr, base + UART_MCR);
1176 outb(val, base + UART_SCR);
1177 outb(LCR, base + UART_LCR);
1178 }
1179
1180 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1181 {
1182 unsigned long base = port->port.iobase;
1183 u8 LCR, val;
1184
1185 LCR = inb(base + UART_LCR);
1186 outb(0xBF, base + UART_LCR);
1187 val = inb(base + UART_SCR);
1188 if (val & 0x20) {
1189 outb(0x80, UART_LCR);
1190 if (!(inb(UART_SCR) & 0x20)) {
1191 outb(LCR, base + UART_LCR);
1192 return 1;
1193 }
1194 }
1195 return 0;
1196 }
1197
1198 static int pci_quatech_test(struct uart_8250_port *port)
1199 {
1200 u8 reg;
1201 u8 qopr = pci_quatech_rqopr(port);
1202 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1203 reg = pci_quatech_rqopr(port) & 0xC0;
1204 if (reg != QPCR_TEST_GET1)
1205 return -EINVAL;
1206 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1207 reg = pci_quatech_rqopr(port) & 0xC0;
1208 if (reg != QPCR_TEST_GET2)
1209 return -EINVAL;
1210 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1211 reg = pci_quatech_rqopr(port) & 0xC0;
1212 if (reg != QPCR_TEST_GET3)
1213 return -EINVAL;
1214 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1215 reg = pci_quatech_rqopr(port) & 0xC0;
1216 if (reg != QPCR_TEST_GET4)
1217 return -EINVAL;
1218
1219 pci_quatech_wqopr(port, qopr);
1220 return 0;
1221 }
1222
1223 static int pci_quatech_clock(struct uart_8250_port *port)
1224 {
1225 u8 qopr, reg, set;
1226 unsigned long clock;
1227
1228 if (pci_quatech_test(port) < 0)
1229 return 1843200;
1230
1231 qopr = pci_quatech_rqopr(port);
1232
1233 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1234 reg = pci_quatech_rqopr(port);
1235 if (reg & QOPR_CLOCK_X8) {
1236 clock = 1843200;
1237 goto out;
1238 }
1239 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1240 reg = pci_quatech_rqopr(port);
1241 if (!(reg & QOPR_CLOCK_X8)) {
1242 clock = 1843200;
1243 goto out;
1244 }
1245 reg &= QOPR_CLOCK_X8;
1246 if (reg == QOPR_CLOCK_X2) {
1247 clock = 3685400;
1248 set = QOPR_CLOCK_X2;
1249 } else if (reg == QOPR_CLOCK_X4) {
1250 clock = 7372800;
1251 set = QOPR_CLOCK_X4;
1252 } else if (reg == QOPR_CLOCK_X8) {
1253 clock = 14745600;
1254 set = QOPR_CLOCK_X8;
1255 } else {
1256 clock = 1843200;
1257 set = QOPR_CLOCK_X1;
1258 }
1259 qopr &= ~QOPR_CLOCK_RATE_MASK;
1260 qopr |= set;
1261
1262 out:
1263 pci_quatech_wqopr(port, qopr);
1264 return clock;
1265 }
1266
1267 static int pci_quatech_rs422(struct uart_8250_port *port)
1268 {
1269 u8 qmcr;
1270 int rs422 = 0;
1271
1272 if (!pci_quatech_has_qmcr(port))
1273 return 0;
1274 qmcr = pci_quatech_rqmcr(port);
1275 pci_quatech_wqmcr(port, 0xFF);
1276 if (pci_quatech_rqmcr(port))
1277 rs422 = 1;
1278 pci_quatech_wqmcr(port, qmcr);
1279 return rs422;
1280 }
1281
1282 static int pci_quatech_init(struct pci_dev *dev)
1283 {
1284 if (pci_quatech_amcc(dev->device)) {
1285 unsigned long base = pci_resource_start(dev, 0);
1286 if (base) {
1287 u32 tmp;
1288 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1289 tmp = inl(base + 0x3c);
1290 outl(tmp | 0x01000000, base + 0x3c);
1291 outl(tmp &= ~0x01000000, base + 0x3c);
1292 }
1293 }
1294 return 0;
1295 }
1296
1297 static int pci_quatech_setup(struct serial_private *priv,
1298 const struct pciserial_board *board,
1299 struct uart_8250_port *port, int idx)
1300 {
1301 /* Needed by pci_quatech calls below */
1302 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1303 /* Set up the clocking */
1304 port->port.uartclk = pci_quatech_clock(port);
1305 /* For now just warn about RS422 */
1306 if (pci_quatech_rs422(port))
1307 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1308 return pci_default_setup(priv, board, port, idx);
1309 }
1310
1311 static void pci_quatech_exit(struct pci_dev *dev)
1312 {
1313 }
1314
1315 static int pci_default_setup(struct serial_private *priv,
1316 const struct pciserial_board *board,
1317 struct uart_8250_port *port, int idx)
1318 {
1319 unsigned int bar, offset = board->first_offset, maxnr;
1320
1321 bar = FL_GET_BASE(board->flags);
1322 if (board->flags & FL_BASE_BARS)
1323 bar += idx;
1324 else
1325 offset += idx * board->uart_offset;
1326
1327 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1328 (board->reg_shift + 3);
1329
1330 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1331 return 1;
1332
1333 return setup_port(priv, port, bar, offset, board->reg_shift);
1334 }
1335
1336 static int pci_pericom_setup(struct serial_private *priv,
1337 const struct pciserial_board *board,
1338 struct uart_8250_port *port, int idx)
1339 {
1340 unsigned int bar, offset = board->first_offset, maxnr;
1341
1342 bar = FL_GET_BASE(board->flags);
1343 if (board->flags & FL_BASE_BARS)
1344 bar += idx;
1345 else
1346 offset += idx * board->uart_offset;
1347
1348 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1349 (board->reg_shift + 3);
1350
1351 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1352 return 1;
1353
1354 port->port.uartclk = 14745600;
1355
1356 return setup_port(priv, port, bar, offset, board->reg_shift);
1357 }
1358
1359 static int
1360 ce4100_serial_setup(struct serial_private *priv,
1361 const struct pciserial_board *board,
1362 struct uart_8250_port *port, int idx)
1363 {
1364 int ret;
1365
1366 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1367 port->port.iotype = UPIO_MEM32;
1368 port->port.type = PORT_XSCALE;
1369 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1370 port->port.regshift = 2;
1371
1372 return ret;
1373 }
1374
1375 #define PCI_DEVICE_ID_INTEL_BYT_UART1 0x0f0a
1376 #define PCI_DEVICE_ID_INTEL_BYT_UART2 0x0f0c
1377
1378 #define PCI_DEVICE_ID_INTEL_BSW_UART1 0x228a
1379 #define PCI_DEVICE_ID_INTEL_BSW_UART2 0x228c
1380
1381 #define BYT_PRV_CLK 0x800
1382 #define BYT_PRV_CLK_EN (1 << 0)
1383 #define BYT_PRV_CLK_M_VAL_SHIFT 1
1384 #define BYT_PRV_CLK_N_VAL_SHIFT 16
1385 #define BYT_PRV_CLK_UPDATE (1 << 31)
1386
1387 #define BYT_TX_OVF_INT 0x820
1388 #define BYT_TX_OVF_INT_MASK (1 << 1)
1389
1390 static void
1391 byt_set_termios(struct uart_port *p, struct ktermios *termios,
1392 struct ktermios *old)
1393 {
1394 unsigned int baud = tty_termios_baud_rate(termios);
1395 unsigned int m, n;
1396 u32 reg;
1397
1398 /*
1399 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the
1400 * dividers must be adjusted.
1401 *
1402 * uartclk = (m / n) * 100 MHz, where m <= n
1403 */
1404 switch (baud) {
1405 case 500000:
1406 case 1000000:
1407 case 2000000:
1408 case 4000000:
1409 m = 64;
1410 n = 100;
1411 p->uartclk = 64000000;
1412 break;
1413 case 3500000:
1414 m = 56;
1415 n = 100;
1416 p->uartclk = 56000000;
1417 break;
1418 case 1500000:
1419 case 3000000:
1420 m = 48;
1421 n = 100;
1422 p->uartclk = 48000000;
1423 break;
1424 case 2500000:
1425 m = 40;
1426 n = 100;
1427 p->uartclk = 40000000;
1428 break;
1429 default:
1430 m = 2304;
1431 n = 3125;
1432 p->uartclk = 73728000;
1433 }
1434
1435 /* Reset the clock */
1436 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
1437 writel(reg, p->membase + BYT_PRV_CLK);
1438 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
1439 writel(reg, p->membase + BYT_PRV_CLK);
1440
1441 serial8250_do_set_termios(p, termios, old);
1442 }
1443
1444 static bool byt_dma_filter(struct dma_chan *chan, void *param)
1445 {
1446 struct dw_dma_slave *dws = param;
1447
1448 if (dws->dma_dev != chan->device->dev)
1449 return false;
1450
1451 chan->private = dws;
1452 return true;
1453 }
1454
1455 static int
1456 byt_serial_setup(struct serial_private *priv,
1457 const struct pciserial_board *board,
1458 struct uart_8250_port *port, int idx)
1459 {
1460 struct pci_dev *pdev = priv->dev;
1461 struct device *dev = port->port.dev;
1462 struct uart_8250_dma *dma;
1463 struct dw_dma_slave *tx_param, *rx_param;
1464 struct pci_dev *dma_dev;
1465 int ret;
1466
1467 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
1468 if (!dma)
1469 return -ENOMEM;
1470
1471 tx_param = devm_kzalloc(dev, sizeof(*tx_param), GFP_KERNEL);
1472 if (!tx_param)
1473 return -ENOMEM;
1474
1475 rx_param = devm_kzalloc(dev, sizeof(*rx_param), GFP_KERNEL);
1476 if (!rx_param)
1477 return -ENOMEM;
1478
1479 switch (pdev->device) {
1480 case PCI_DEVICE_ID_INTEL_BYT_UART1:
1481 case PCI_DEVICE_ID_INTEL_BSW_UART1:
1482 rx_param->src_id = 3;
1483 tx_param->dst_id = 2;
1484 break;
1485 case PCI_DEVICE_ID_INTEL_BYT_UART2:
1486 case PCI_DEVICE_ID_INTEL_BSW_UART2:
1487 rx_param->src_id = 5;
1488 tx_param->dst_id = 4;
1489 break;
1490 default:
1491 return -EINVAL;
1492 }
1493
1494 rx_param->src_master = 1;
1495 rx_param->dst_master = 0;
1496
1497 dma->rxconf.src_maxburst = 16;
1498
1499 tx_param->src_master = 1;
1500 tx_param->dst_master = 0;
1501
1502 dma->txconf.dst_maxburst = 16;
1503
1504 dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
1505 rx_param->dma_dev = &dma_dev->dev;
1506 tx_param->dma_dev = &dma_dev->dev;
1507
1508 dma->fn = byt_dma_filter;
1509 dma->rx_param = rx_param;
1510 dma->tx_param = tx_param;
1511
1512 ret = pci_default_setup(priv, board, port, idx);
1513 port->port.iotype = UPIO_MEM;
1514 port->port.type = PORT_16550A;
1515 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1516 port->port.set_termios = byt_set_termios;
1517 port->port.fifosize = 64;
1518 port->tx_loadsz = 64;
1519 port->dma = dma;
1520 port->capabilities = UART_CAP_FIFO | UART_CAP_AFE;
1521
1522 /* Disable Tx counter interrupts */
1523 writel(BYT_TX_OVF_INT_MASK, port->port.membase + BYT_TX_OVF_INT);
1524
1525 return ret;
1526 }
1527
1528 static int
1529 pci_omegapci_setup(struct serial_private *priv,
1530 const struct pciserial_board *board,
1531 struct uart_8250_port *port, int idx)
1532 {
1533 return setup_port(priv, port, 2, idx * 8, 0);
1534 }
1535
1536 static int
1537 pci_brcm_trumanage_setup(struct serial_private *priv,
1538 const struct pciserial_board *board,
1539 struct uart_8250_port *port, int idx)
1540 {
1541 int ret = pci_default_setup(priv, board, port, idx);
1542
1543 port->port.type = PORT_BRCM_TRUMANAGE;
1544 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1545 return ret;
1546 }
1547
1548 static int pci_fintek_setup(struct serial_private *priv,
1549 const struct pciserial_board *board,
1550 struct uart_8250_port *port, int idx)
1551 {
1552 struct pci_dev *pdev = priv->dev;
1553 unsigned long base;
1554 unsigned long iobase;
1555 unsigned long ciobase = 0;
1556 u8 config_base;
1557 u32 bar_data[3];
1558
1559 /*
1560 * Find each UARTs offset in PCI configuraion space
1561 */
1562 switch (idx) {
1563 case 0:
1564 config_base = 0x40;
1565 break;
1566 case 1:
1567 config_base = 0x48;
1568 break;
1569 case 2:
1570 config_base = 0x50;
1571 break;
1572 case 3:
1573 config_base = 0x58;
1574 break;
1575 case 4:
1576 config_base = 0x60;
1577 break;
1578 case 5:
1579 config_base = 0x68;
1580 break;
1581 case 6:
1582 config_base = 0x70;
1583 break;
1584 case 7:
1585 config_base = 0x78;
1586 break;
1587 case 8:
1588 config_base = 0x80;
1589 break;
1590 case 9:
1591 config_base = 0x88;
1592 break;
1593 case 10:
1594 config_base = 0x90;
1595 break;
1596 case 11:
1597 config_base = 0x98;
1598 break;
1599 default:
1600 /* Unknown number of ports, get out of here */
1601 return -EINVAL;
1602 }
1603
1604 if (idx < 4) {
1605 base = pci_resource_start(priv->dev, 3);
1606 ciobase = (int)(base + (0x8 * idx));
1607 }
1608
1609 /* Get the io address dispatch from the BIOS */
1610 pci_read_config_dword(pdev, 0x24, &bar_data[0]);
1611 pci_read_config_dword(pdev, 0x20, &bar_data[1]);
1612 pci_read_config_dword(pdev, 0x1c, &bar_data[2]);
1613
1614 /* Calculate Real IO Port */
1615 iobase = (bar_data[idx/4] & 0xffffffe0) + (idx % 4) * 8;
1616
1617 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%lx ciobase=0x%lx config_base=0x%2x\n",
1618 __func__, idx, iobase, ciobase, config_base);
1619
1620 /* Enable UART I/O port */
1621 pci_write_config_byte(pdev, config_base + 0x00, 0x01);
1622
1623 /* Select 128-byte FIFO and 8x FIFO threshold */
1624 pci_write_config_byte(pdev, config_base + 0x01, 0x33);
1625
1626 /* LSB UART */
1627 pci_write_config_byte(pdev, config_base + 0x04, (u8)(iobase & 0xff));
1628
1629 /* MSB UART */
1630 pci_write_config_byte(pdev, config_base + 0x05, (u8)((iobase & 0xff00) >> 8));
1631
1632 /* irq number, this usually fails, but the spec says to do it anyway. */
1633 pci_write_config_byte(pdev, config_base + 0x06, pdev->irq);
1634
1635 port->port.iotype = UPIO_PORT;
1636 port->port.iobase = iobase;
1637 port->port.mapbase = 0;
1638 port->port.membase = NULL;
1639 port->port.regshift = 0;
1640
1641 return 0;
1642 }
1643
1644 static int skip_tx_en_setup(struct serial_private *priv,
1645 const struct pciserial_board *board,
1646 struct uart_8250_port *port, int idx)
1647 {
1648 port->port.flags |= UPF_NO_TXEN_TEST;
1649 dev_dbg(&priv->dev->dev,
1650 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1651 priv->dev->vendor, priv->dev->device,
1652 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1653
1654 return pci_default_setup(priv, board, port, idx);
1655 }
1656
1657 static void kt_handle_break(struct uart_port *p)
1658 {
1659 struct uart_8250_port *up = up_to_u8250p(p);
1660 /*
1661 * On receipt of a BI, serial device in Intel ME (Intel
1662 * management engine) needs to have its fifos cleared for sane
1663 * SOL (Serial Over Lan) output.
1664 */
1665 serial8250_clear_and_reinit_fifos(up);
1666 }
1667
1668 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1669 {
1670 struct uart_8250_port *up = up_to_u8250p(p);
1671 unsigned int val;
1672
1673 /*
1674 * When the Intel ME (management engine) gets reset its serial
1675 * port registers could return 0 momentarily. Functions like
1676 * serial8250_console_write, read and save the IER, perform
1677 * some operation and then restore it. In order to avoid
1678 * setting IER register inadvertently to 0, if the value read
1679 * is 0, double check with ier value in uart_8250_port and use
1680 * that instead. up->ier should be the same value as what is
1681 * currently configured.
1682 */
1683 val = inb(p->iobase + offset);
1684 if (offset == UART_IER) {
1685 if (val == 0)
1686 val = up->ier;
1687 }
1688 return val;
1689 }
1690
1691 static int kt_serial_setup(struct serial_private *priv,
1692 const struct pciserial_board *board,
1693 struct uart_8250_port *port, int idx)
1694 {
1695 port->port.flags |= UPF_BUG_THRE;
1696 port->port.serial_in = kt_serial_in;
1697 port->port.handle_break = kt_handle_break;
1698 return skip_tx_en_setup(priv, board, port, idx);
1699 }
1700
1701 static int pci_eg20t_init(struct pci_dev *dev)
1702 {
1703 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1704 return -ENODEV;
1705 #else
1706 return 0;
1707 #endif
1708 }
1709
1710 static int
1711 pci_xr17c154_setup(struct serial_private *priv,
1712 const struct pciserial_board *board,
1713 struct uart_8250_port *port, int idx)
1714 {
1715 port->port.flags |= UPF_EXAR_EFR;
1716 return pci_default_setup(priv, board, port, idx);
1717 }
1718
1719 static int
1720 pci_xr17v35x_setup(struct serial_private *priv,
1721 const struct pciserial_board *board,
1722 struct uart_8250_port *port, int idx)
1723 {
1724 u8 __iomem *p;
1725
1726 p = pci_ioremap_bar(priv->dev, 0);
1727 if (p == NULL)
1728 return -ENOMEM;
1729
1730 port->port.flags |= UPF_EXAR_EFR;
1731
1732 /*
1733 * Setup Multipurpose Input/Output pins.
1734 */
1735 if (idx == 0) {
1736 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1737 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1738 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1739 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1740 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1741 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1742 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1743 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1744 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1745 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1746 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1747 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1748 }
1749 writeb(0x00, p + UART_EXAR_8XMODE);
1750 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1751 writeb(128, p + UART_EXAR_TXTRG);
1752 writeb(128, p + UART_EXAR_RXTRG);
1753 iounmap(p);
1754
1755 return pci_default_setup(priv, board, port, idx);
1756 }
1757
1758 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1759 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1760 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1761 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1762
1763 static int
1764 pci_fastcom335_setup(struct serial_private *priv,
1765 const struct pciserial_board *board,
1766 struct uart_8250_port *port, int idx)
1767 {
1768 u8 __iomem *p;
1769
1770 p = pci_ioremap_bar(priv->dev, 0);
1771 if (p == NULL)
1772 return -ENOMEM;
1773
1774 port->port.flags |= UPF_EXAR_EFR;
1775
1776 /*
1777 * Setup Multipurpose Input/Output pins.
1778 */
1779 if (idx == 0) {
1780 switch (priv->dev->device) {
1781 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1782 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1783 writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1784 writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1785 writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1786 break;
1787 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1788 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1789 writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1790 writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1791 writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1792 break;
1793 }
1794 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1795 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1796 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1797 }
1798 writeb(0x00, p + UART_EXAR_8XMODE);
1799 writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1800 writeb(32, p + UART_EXAR_TXTRG);
1801 writeb(32, p + UART_EXAR_RXTRG);
1802 iounmap(p);
1803
1804 return pci_default_setup(priv, board, port, idx);
1805 }
1806
1807 static int
1808 pci_wch_ch353_setup(struct serial_private *priv,
1809 const struct pciserial_board *board,
1810 struct uart_8250_port *port, int idx)
1811 {
1812 port->port.flags |= UPF_FIXED_TYPE;
1813 port->port.type = PORT_16550A;
1814 return pci_default_setup(priv, board, port, idx);
1815 }
1816
1817 static int
1818 pci_wch_ch38x_setup(struct serial_private *priv,
1819 const struct pciserial_board *board,
1820 struct uart_8250_port *port, int idx)
1821 {
1822 port->port.flags |= UPF_FIXED_TYPE;
1823 port->port.type = PORT_16850;
1824 return pci_default_setup(priv, board, port, idx);
1825 }
1826
1827 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1828 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1829 #define PCI_DEVICE_ID_OCTPRO 0x0001
1830 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1831 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1832 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1833 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1834 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1835 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1836 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1837 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1838 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1839 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1840 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1841 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1842 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1843 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1844 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1845 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1846 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1847 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1848 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1849 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1850 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1851 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1852 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1853 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1854 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1855 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1856 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1857 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1858 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1859 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1860 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1861 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1862 #define PCI_VENDOR_ID_WCH 0x4348
1863 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1864 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1865 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1866 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
1867 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1868 #define PCI_VENDOR_ID_AGESTAR 0x5372
1869 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1870 #define PCI_VENDOR_ID_ASIX 0x9710
1871 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1872 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1873 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1874 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1875 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1876 #define PCI_DEVICE_ID_INTEL_QRK_UART 0x0936
1877
1878 #define PCI_VENDOR_ID_SUNIX 0x1fd4
1879 #define PCI_DEVICE_ID_SUNIX_1999 0x1999
1880
1881 #define PCIE_VENDOR_ID_WCH 0x1c00
1882 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
1883 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
1884
1885 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1886 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1887 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1888
1889 /*
1890 * Master list of serial port init/setup/exit quirks.
1891 * This does not describe the general nature of the port.
1892 * (ie, baud base, number and location of ports, etc)
1893 *
1894 * This list is ordered alphabetically by vendor then device.
1895 * Specific entries must come before more generic entries.
1896 */
1897 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1898 /*
1899 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1900 */
1901 {
1902 .vendor = PCI_VENDOR_ID_AMCC,
1903 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1904 .subvendor = PCI_ANY_ID,
1905 .subdevice = PCI_ANY_ID,
1906 .setup = addidata_apci7800_setup,
1907 },
1908 /*
1909 * AFAVLAB cards - these may be called via parport_serial
1910 * It is not clear whether this applies to all products.
1911 */
1912 {
1913 .vendor = PCI_VENDOR_ID_AFAVLAB,
1914 .device = PCI_ANY_ID,
1915 .subvendor = PCI_ANY_ID,
1916 .subdevice = PCI_ANY_ID,
1917 .setup = afavlab_setup,
1918 },
1919 /*
1920 * HP Diva
1921 */
1922 {
1923 .vendor = PCI_VENDOR_ID_HP,
1924 .device = PCI_DEVICE_ID_HP_DIVA,
1925 .subvendor = PCI_ANY_ID,
1926 .subdevice = PCI_ANY_ID,
1927 .init = pci_hp_diva_init,
1928 .setup = pci_hp_diva_setup,
1929 },
1930 /*
1931 * Intel
1932 */
1933 {
1934 .vendor = PCI_VENDOR_ID_INTEL,
1935 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1936 .subvendor = 0xe4bf,
1937 .subdevice = PCI_ANY_ID,
1938 .init = pci_inteli960ni_init,
1939 .setup = pci_default_setup,
1940 },
1941 {
1942 .vendor = PCI_VENDOR_ID_INTEL,
1943 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1944 .subvendor = PCI_ANY_ID,
1945 .subdevice = PCI_ANY_ID,
1946 .setup = skip_tx_en_setup,
1947 },
1948 {
1949 .vendor = PCI_VENDOR_ID_INTEL,
1950 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1951 .subvendor = PCI_ANY_ID,
1952 .subdevice = PCI_ANY_ID,
1953 .setup = skip_tx_en_setup,
1954 },
1955 {
1956 .vendor = PCI_VENDOR_ID_INTEL,
1957 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1958 .subvendor = PCI_ANY_ID,
1959 .subdevice = PCI_ANY_ID,
1960 .setup = skip_tx_en_setup,
1961 },
1962 {
1963 .vendor = PCI_VENDOR_ID_INTEL,
1964 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1965 .subvendor = PCI_ANY_ID,
1966 .subdevice = PCI_ANY_ID,
1967 .setup = ce4100_serial_setup,
1968 },
1969 {
1970 .vendor = PCI_VENDOR_ID_INTEL,
1971 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1972 .subvendor = PCI_ANY_ID,
1973 .subdevice = PCI_ANY_ID,
1974 .setup = kt_serial_setup,
1975 },
1976 {
1977 .vendor = PCI_VENDOR_ID_INTEL,
1978 .device = PCI_DEVICE_ID_INTEL_BYT_UART1,
1979 .subvendor = PCI_ANY_ID,
1980 .subdevice = PCI_ANY_ID,
1981 .setup = byt_serial_setup,
1982 },
1983 {
1984 .vendor = PCI_VENDOR_ID_INTEL,
1985 .device = PCI_DEVICE_ID_INTEL_BYT_UART2,
1986 .subvendor = PCI_ANY_ID,
1987 .subdevice = PCI_ANY_ID,
1988 .setup = byt_serial_setup,
1989 },
1990 {
1991 .vendor = PCI_VENDOR_ID_INTEL,
1992 .device = PCI_DEVICE_ID_INTEL_BSW_UART1,
1993 .subvendor = PCI_ANY_ID,
1994 .subdevice = PCI_ANY_ID,
1995 .setup = byt_serial_setup,
1996 },
1997 {
1998 .vendor = PCI_VENDOR_ID_INTEL,
1999 .device = PCI_DEVICE_ID_INTEL_BSW_UART2,
2000 .subvendor = PCI_ANY_ID,
2001 .subdevice = PCI_ANY_ID,
2002 .setup = byt_serial_setup,
2003 },
2004 /*
2005 * ITE
2006 */
2007 {
2008 .vendor = PCI_VENDOR_ID_ITE,
2009 .device = PCI_DEVICE_ID_ITE_8872,
2010 .subvendor = PCI_ANY_ID,
2011 .subdevice = PCI_ANY_ID,
2012 .init = pci_ite887x_init,
2013 .setup = pci_default_setup,
2014 .exit = pci_ite887x_exit,
2015 },
2016 /*
2017 * National Instruments
2018 */
2019 {
2020 .vendor = PCI_VENDOR_ID_NI,
2021 .device = PCI_DEVICE_ID_NI_PCI23216,
2022 .subvendor = PCI_ANY_ID,
2023 .subdevice = PCI_ANY_ID,
2024 .init = pci_ni8420_init,
2025 .setup = pci_default_setup,
2026 .exit = pci_ni8420_exit,
2027 },
2028 {
2029 .vendor = PCI_VENDOR_ID_NI,
2030 .device = PCI_DEVICE_ID_NI_PCI2328,
2031 .subvendor = PCI_ANY_ID,
2032 .subdevice = PCI_ANY_ID,
2033 .init = pci_ni8420_init,
2034 .setup = pci_default_setup,
2035 .exit = pci_ni8420_exit,
2036 },
2037 {
2038 .vendor = PCI_VENDOR_ID_NI,
2039 .device = PCI_DEVICE_ID_NI_PCI2324,
2040 .subvendor = PCI_ANY_ID,
2041 .subdevice = PCI_ANY_ID,
2042 .init = pci_ni8420_init,
2043 .setup = pci_default_setup,
2044 .exit = pci_ni8420_exit,
2045 },
2046 {
2047 .vendor = PCI_VENDOR_ID_NI,
2048 .device = PCI_DEVICE_ID_NI_PCI2322,
2049 .subvendor = PCI_ANY_ID,
2050 .subdevice = PCI_ANY_ID,
2051 .init = pci_ni8420_init,
2052 .setup = pci_default_setup,
2053 .exit = pci_ni8420_exit,
2054 },
2055 {
2056 .vendor = PCI_VENDOR_ID_NI,
2057 .device = PCI_DEVICE_ID_NI_PCI2324I,
2058 .subvendor = PCI_ANY_ID,
2059 .subdevice = PCI_ANY_ID,
2060 .init = pci_ni8420_init,
2061 .setup = pci_default_setup,
2062 .exit = pci_ni8420_exit,
2063 },
2064 {
2065 .vendor = PCI_VENDOR_ID_NI,
2066 .device = PCI_DEVICE_ID_NI_PCI2322I,
2067 .subvendor = PCI_ANY_ID,
2068 .subdevice = PCI_ANY_ID,
2069 .init = pci_ni8420_init,
2070 .setup = pci_default_setup,
2071 .exit = pci_ni8420_exit,
2072 },
2073 {
2074 .vendor = PCI_VENDOR_ID_NI,
2075 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2076 .subvendor = PCI_ANY_ID,
2077 .subdevice = PCI_ANY_ID,
2078 .init = pci_ni8420_init,
2079 .setup = pci_default_setup,
2080 .exit = pci_ni8420_exit,
2081 },
2082 {
2083 .vendor = PCI_VENDOR_ID_NI,
2084 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2085 .subvendor = PCI_ANY_ID,
2086 .subdevice = PCI_ANY_ID,
2087 .init = pci_ni8420_init,
2088 .setup = pci_default_setup,
2089 .exit = pci_ni8420_exit,
2090 },
2091 {
2092 .vendor = PCI_VENDOR_ID_NI,
2093 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2094 .subvendor = PCI_ANY_ID,
2095 .subdevice = PCI_ANY_ID,
2096 .init = pci_ni8420_init,
2097 .setup = pci_default_setup,
2098 .exit = pci_ni8420_exit,
2099 },
2100 {
2101 .vendor = PCI_VENDOR_ID_NI,
2102 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2103 .subvendor = PCI_ANY_ID,
2104 .subdevice = PCI_ANY_ID,
2105 .init = pci_ni8420_init,
2106 .setup = pci_default_setup,
2107 .exit = pci_ni8420_exit,
2108 },
2109 {
2110 .vendor = PCI_VENDOR_ID_NI,
2111 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2112 .subvendor = PCI_ANY_ID,
2113 .subdevice = PCI_ANY_ID,
2114 .init = pci_ni8420_init,
2115 .setup = pci_default_setup,
2116 .exit = pci_ni8420_exit,
2117 },
2118 {
2119 .vendor = PCI_VENDOR_ID_NI,
2120 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2121 .subvendor = PCI_ANY_ID,
2122 .subdevice = PCI_ANY_ID,
2123 .init = pci_ni8420_init,
2124 .setup = pci_default_setup,
2125 .exit = pci_ni8420_exit,
2126 },
2127 {
2128 .vendor = PCI_VENDOR_ID_NI,
2129 .device = PCI_ANY_ID,
2130 .subvendor = PCI_ANY_ID,
2131 .subdevice = PCI_ANY_ID,
2132 .init = pci_ni8430_init,
2133 .setup = pci_ni8430_setup,
2134 .exit = pci_ni8430_exit,
2135 },
2136 /* Quatech */
2137 {
2138 .vendor = PCI_VENDOR_ID_QUATECH,
2139 .device = PCI_ANY_ID,
2140 .subvendor = PCI_ANY_ID,
2141 .subdevice = PCI_ANY_ID,
2142 .init = pci_quatech_init,
2143 .setup = pci_quatech_setup,
2144 .exit = pci_quatech_exit,
2145 },
2146 /*
2147 * Panacom
2148 */
2149 {
2150 .vendor = PCI_VENDOR_ID_PANACOM,
2151 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2152 .subvendor = PCI_ANY_ID,
2153 .subdevice = PCI_ANY_ID,
2154 .init = pci_plx9050_init,
2155 .setup = pci_default_setup,
2156 .exit = pci_plx9050_exit,
2157 },
2158 {
2159 .vendor = PCI_VENDOR_ID_PANACOM,
2160 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2161 .subvendor = PCI_ANY_ID,
2162 .subdevice = PCI_ANY_ID,
2163 .init = pci_plx9050_init,
2164 .setup = pci_default_setup,
2165 .exit = pci_plx9050_exit,
2166 },
2167 /*
2168 * Pericom
2169 */
2170 {
2171 .vendor = 0x12d8,
2172 .device = 0x7952,
2173 .subvendor = PCI_ANY_ID,
2174 .subdevice = PCI_ANY_ID,
2175 .setup = pci_pericom_setup,
2176 },
2177 {
2178 .vendor = 0x12d8,
2179 .device = 0x7954,
2180 .subvendor = PCI_ANY_ID,
2181 .subdevice = PCI_ANY_ID,
2182 .setup = pci_pericom_setup,
2183 },
2184 {
2185 .vendor = 0x12d8,
2186 .device = 0x7958,
2187 .subvendor = PCI_ANY_ID,
2188 .subdevice = PCI_ANY_ID,
2189 .setup = pci_pericom_setup,
2190 },
2191
2192 /*
2193 * PLX
2194 */
2195 {
2196 .vendor = PCI_VENDOR_ID_PLX,
2197 .device = PCI_DEVICE_ID_PLX_9050,
2198 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2199 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2200 .init = pci_plx9050_init,
2201 .setup = pci_default_setup,
2202 .exit = pci_plx9050_exit,
2203 },
2204 {
2205 .vendor = PCI_VENDOR_ID_PLX,
2206 .device = PCI_DEVICE_ID_PLX_9050,
2207 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2208 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2209 .init = pci_plx9050_init,
2210 .setup = pci_default_setup,
2211 .exit = pci_plx9050_exit,
2212 },
2213 {
2214 .vendor = PCI_VENDOR_ID_PLX,
2215 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2216 .subvendor = PCI_VENDOR_ID_PLX,
2217 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2218 .init = pci_plx9050_init,
2219 .setup = pci_default_setup,
2220 .exit = pci_plx9050_exit,
2221 },
2222 /*
2223 * SBS Technologies, Inc., PMC-OCTALPRO 232
2224 */
2225 {
2226 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2227 .device = PCI_DEVICE_ID_OCTPRO,
2228 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2229 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2230 .init = sbs_init,
2231 .setup = sbs_setup,
2232 .exit = sbs_exit,
2233 },
2234 /*
2235 * SBS Technologies, Inc., PMC-OCTALPRO 422
2236 */
2237 {
2238 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2239 .device = PCI_DEVICE_ID_OCTPRO,
2240 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2241 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2242 .init = sbs_init,
2243 .setup = sbs_setup,
2244 .exit = sbs_exit,
2245 },
2246 /*
2247 * SBS Technologies, Inc., P-Octal 232
2248 */
2249 {
2250 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2251 .device = PCI_DEVICE_ID_OCTPRO,
2252 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2253 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2254 .init = sbs_init,
2255 .setup = sbs_setup,
2256 .exit = sbs_exit,
2257 },
2258 /*
2259 * SBS Technologies, Inc., P-Octal 422
2260 */
2261 {
2262 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2263 .device = PCI_DEVICE_ID_OCTPRO,
2264 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2265 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2266 .init = sbs_init,
2267 .setup = sbs_setup,
2268 .exit = sbs_exit,
2269 },
2270 /*
2271 * SIIG cards - these may be called via parport_serial
2272 */
2273 {
2274 .vendor = PCI_VENDOR_ID_SIIG,
2275 .device = PCI_ANY_ID,
2276 .subvendor = PCI_ANY_ID,
2277 .subdevice = PCI_ANY_ID,
2278 .init = pci_siig_init,
2279 .setup = pci_siig_setup,
2280 },
2281 /*
2282 * Titan cards
2283 */
2284 {
2285 .vendor = PCI_VENDOR_ID_TITAN,
2286 .device = PCI_DEVICE_ID_TITAN_400L,
2287 .subvendor = PCI_ANY_ID,
2288 .subdevice = PCI_ANY_ID,
2289 .setup = titan_400l_800l_setup,
2290 },
2291 {
2292 .vendor = PCI_VENDOR_ID_TITAN,
2293 .device = PCI_DEVICE_ID_TITAN_800L,
2294 .subvendor = PCI_ANY_ID,
2295 .subdevice = PCI_ANY_ID,
2296 .setup = titan_400l_800l_setup,
2297 },
2298 /*
2299 * Timedia cards
2300 */
2301 {
2302 .vendor = PCI_VENDOR_ID_TIMEDIA,
2303 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2304 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2305 .subdevice = PCI_ANY_ID,
2306 .probe = pci_timedia_probe,
2307 .init = pci_timedia_init,
2308 .setup = pci_timedia_setup,
2309 },
2310 {
2311 .vendor = PCI_VENDOR_ID_TIMEDIA,
2312 .device = PCI_ANY_ID,
2313 .subvendor = PCI_ANY_ID,
2314 .subdevice = PCI_ANY_ID,
2315 .setup = pci_timedia_setup,
2316 },
2317 /*
2318 * SUNIX (Timedia) cards
2319 * Do not "probe" for these cards as there is at least one combination
2320 * card that should be handled by parport_pc that doesn't match the
2321 * rule in pci_timedia_probe.
2322 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2323 * There are some boards with part number SER5037AL that report
2324 * subdevice ID 0x0002.
2325 */
2326 {
2327 .vendor = PCI_VENDOR_ID_SUNIX,
2328 .device = PCI_DEVICE_ID_SUNIX_1999,
2329 .subvendor = PCI_VENDOR_ID_SUNIX,
2330 .subdevice = PCI_ANY_ID,
2331 .init = pci_timedia_init,
2332 .setup = pci_timedia_setup,
2333 },
2334 /*
2335 * Exar cards
2336 */
2337 {
2338 .vendor = PCI_VENDOR_ID_EXAR,
2339 .device = PCI_DEVICE_ID_EXAR_XR17C152,
2340 .subvendor = PCI_ANY_ID,
2341 .subdevice = PCI_ANY_ID,
2342 .setup = pci_xr17c154_setup,
2343 },
2344 {
2345 .vendor = PCI_VENDOR_ID_EXAR,
2346 .device = PCI_DEVICE_ID_EXAR_XR17C154,
2347 .subvendor = PCI_ANY_ID,
2348 .subdevice = PCI_ANY_ID,
2349 .setup = pci_xr17c154_setup,
2350 },
2351 {
2352 .vendor = PCI_VENDOR_ID_EXAR,
2353 .device = PCI_DEVICE_ID_EXAR_XR17C158,
2354 .subvendor = PCI_ANY_ID,
2355 .subdevice = PCI_ANY_ID,
2356 .setup = pci_xr17c154_setup,
2357 },
2358 {
2359 .vendor = PCI_VENDOR_ID_EXAR,
2360 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2361 .subvendor = PCI_ANY_ID,
2362 .subdevice = PCI_ANY_ID,
2363 .setup = pci_xr17v35x_setup,
2364 },
2365 {
2366 .vendor = PCI_VENDOR_ID_EXAR,
2367 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2368 .subvendor = PCI_ANY_ID,
2369 .subdevice = PCI_ANY_ID,
2370 .setup = pci_xr17v35x_setup,
2371 },
2372 {
2373 .vendor = PCI_VENDOR_ID_EXAR,
2374 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2375 .subvendor = PCI_ANY_ID,
2376 .subdevice = PCI_ANY_ID,
2377 .setup = pci_xr17v35x_setup,
2378 },
2379 /*
2380 * Xircom cards
2381 */
2382 {
2383 .vendor = PCI_VENDOR_ID_XIRCOM,
2384 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2385 .subvendor = PCI_ANY_ID,
2386 .subdevice = PCI_ANY_ID,
2387 .init = pci_xircom_init,
2388 .setup = pci_default_setup,
2389 },
2390 /*
2391 * Netmos cards - these may be called via parport_serial
2392 */
2393 {
2394 .vendor = PCI_VENDOR_ID_NETMOS,
2395 .device = PCI_ANY_ID,
2396 .subvendor = PCI_ANY_ID,
2397 .subdevice = PCI_ANY_ID,
2398 .init = pci_netmos_init,
2399 .setup = pci_netmos_9900_setup,
2400 },
2401 /*
2402 * EndRun Technologies
2403 */
2404 {
2405 .vendor = PCI_VENDOR_ID_ENDRUN,
2406 .device = PCI_ANY_ID,
2407 .subvendor = PCI_ANY_ID,
2408 .subdevice = PCI_ANY_ID,
2409 .init = pci_endrun_init,
2410 .setup = pci_default_setup,
2411 },
2412 /*
2413 * For Oxford Semiconductor Tornado based devices
2414 */
2415 {
2416 .vendor = PCI_VENDOR_ID_OXSEMI,
2417 .device = PCI_ANY_ID,
2418 .subvendor = PCI_ANY_ID,
2419 .subdevice = PCI_ANY_ID,
2420 .init = pci_oxsemi_tornado_init,
2421 .setup = pci_default_setup,
2422 },
2423 {
2424 .vendor = PCI_VENDOR_ID_MAINPINE,
2425 .device = PCI_ANY_ID,
2426 .subvendor = PCI_ANY_ID,
2427 .subdevice = PCI_ANY_ID,
2428 .init = pci_oxsemi_tornado_init,
2429 .setup = pci_default_setup,
2430 },
2431 {
2432 .vendor = PCI_VENDOR_ID_DIGI,
2433 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2434 .subvendor = PCI_SUBVENDOR_ID_IBM,
2435 .subdevice = PCI_ANY_ID,
2436 .init = pci_oxsemi_tornado_init,
2437 .setup = pci_default_setup,
2438 },
2439 {
2440 .vendor = PCI_VENDOR_ID_INTEL,
2441 .device = 0x8811,
2442 .subvendor = PCI_ANY_ID,
2443 .subdevice = PCI_ANY_ID,
2444 .init = pci_eg20t_init,
2445 .setup = pci_default_setup,
2446 },
2447 {
2448 .vendor = PCI_VENDOR_ID_INTEL,
2449 .device = 0x8812,
2450 .subvendor = PCI_ANY_ID,
2451 .subdevice = PCI_ANY_ID,
2452 .init = pci_eg20t_init,
2453 .setup = pci_default_setup,
2454 },
2455 {
2456 .vendor = PCI_VENDOR_ID_INTEL,
2457 .device = 0x8813,
2458 .subvendor = PCI_ANY_ID,
2459 .subdevice = PCI_ANY_ID,
2460 .init = pci_eg20t_init,
2461 .setup = pci_default_setup,
2462 },
2463 {
2464 .vendor = PCI_VENDOR_ID_INTEL,
2465 .device = 0x8814,
2466 .subvendor = PCI_ANY_ID,
2467 .subdevice = PCI_ANY_ID,
2468 .init = pci_eg20t_init,
2469 .setup = pci_default_setup,
2470 },
2471 {
2472 .vendor = 0x10DB,
2473 .device = 0x8027,
2474 .subvendor = PCI_ANY_ID,
2475 .subdevice = PCI_ANY_ID,
2476 .init = pci_eg20t_init,
2477 .setup = pci_default_setup,
2478 },
2479 {
2480 .vendor = 0x10DB,
2481 .device = 0x8028,
2482 .subvendor = PCI_ANY_ID,
2483 .subdevice = PCI_ANY_ID,
2484 .init = pci_eg20t_init,
2485 .setup = pci_default_setup,
2486 },
2487 {
2488 .vendor = 0x10DB,
2489 .device = 0x8029,
2490 .subvendor = PCI_ANY_ID,
2491 .subdevice = PCI_ANY_ID,
2492 .init = pci_eg20t_init,
2493 .setup = pci_default_setup,
2494 },
2495 {
2496 .vendor = 0x10DB,
2497 .device = 0x800C,
2498 .subvendor = PCI_ANY_ID,
2499 .subdevice = PCI_ANY_ID,
2500 .init = pci_eg20t_init,
2501 .setup = pci_default_setup,
2502 },
2503 {
2504 .vendor = 0x10DB,
2505 .device = 0x800D,
2506 .subvendor = PCI_ANY_ID,
2507 .subdevice = PCI_ANY_ID,
2508 .init = pci_eg20t_init,
2509 .setup = pci_default_setup,
2510 },
2511 /*
2512 * Cronyx Omega PCI (PLX-chip based)
2513 */
2514 {
2515 .vendor = PCI_VENDOR_ID_PLX,
2516 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2517 .subvendor = PCI_ANY_ID,
2518 .subdevice = PCI_ANY_ID,
2519 .setup = pci_omegapci_setup,
2520 },
2521 /* WCH CH353 1S1P card (16550 clone) */
2522 {
2523 .vendor = PCI_VENDOR_ID_WCH,
2524 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2525 .subvendor = PCI_ANY_ID,
2526 .subdevice = PCI_ANY_ID,
2527 .setup = pci_wch_ch353_setup,
2528 },
2529 /* WCH CH353 2S1P card (16550 clone) */
2530 {
2531 .vendor = PCI_VENDOR_ID_WCH,
2532 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2533 .subvendor = PCI_ANY_ID,
2534 .subdevice = PCI_ANY_ID,
2535 .setup = pci_wch_ch353_setup,
2536 },
2537 /* WCH CH353 4S card (16550 clone) */
2538 {
2539 .vendor = PCI_VENDOR_ID_WCH,
2540 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2541 .subvendor = PCI_ANY_ID,
2542 .subdevice = PCI_ANY_ID,
2543 .setup = pci_wch_ch353_setup,
2544 },
2545 /* WCH CH353 2S1PF card (16550 clone) */
2546 {
2547 .vendor = PCI_VENDOR_ID_WCH,
2548 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2549 .subvendor = PCI_ANY_ID,
2550 .subdevice = PCI_ANY_ID,
2551 .setup = pci_wch_ch353_setup,
2552 },
2553 /* WCH CH352 2S card (16550 clone) */
2554 {
2555 .vendor = PCI_VENDOR_ID_WCH,
2556 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2557 .subvendor = PCI_ANY_ID,
2558 .subdevice = PCI_ANY_ID,
2559 .setup = pci_wch_ch353_setup,
2560 },
2561 /* WCH CH382 2S1P card (16850 clone) */
2562 {
2563 .vendor = PCIE_VENDOR_ID_WCH,
2564 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2565 .subvendor = PCI_ANY_ID,
2566 .subdevice = PCI_ANY_ID,
2567 .setup = pci_wch_ch38x_setup,
2568 },
2569 /* WCH CH384 4S card (16850 clone) */
2570 {
2571 .vendor = PCIE_VENDOR_ID_WCH,
2572 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2573 .subvendor = PCI_ANY_ID,
2574 .subdevice = PCI_ANY_ID,
2575 .setup = pci_wch_ch38x_setup,
2576 },
2577 /*
2578 * ASIX devices with FIFO bug
2579 */
2580 {
2581 .vendor = PCI_VENDOR_ID_ASIX,
2582 .device = PCI_ANY_ID,
2583 .subvendor = PCI_ANY_ID,
2584 .subdevice = PCI_ANY_ID,
2585 .setup = pci_asix_setup,
2586 },
2587 /*
2588 * Commtech, Inc. Fastcom adapters
2589 *
2590 */
2591 {
2592 .vendor = PCI_VENDOR_ID_COMMTECH,
2593 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2594 .subvendor = PCI_ANY_ID,
2595 .subdevice = PCI_ANY_ID,
2596 .setup = pci_fastcom335_setup,
2597 },
2598 {
2599 .vendor = PCI_VENDOR_ID_COMMTECH,
2600 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2601 .subvendor = PCI_ANY_ID,
2602 .subdevice = PCI_ANY_ID,
2603 .setup = pci_fastcom335_setup,
2604 },
2605 {
2606 .vendor = PCI_VENDOR_ID_COMMTECH,
2607 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2608 .subvendor = PCI_ANY_ID,
2609 .subdevice = PCI_ANY_ID,
2610 .setup = pci_fastcom335_setup,
2611 },
2612 {
2613 .vendor = PCI_VENDOR_ID_COMMTECH,
2614 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2615 .subvendor = PCI_ANY_ID,
2616 .subdevice = PCI_ANY_ID,
2617 .setup = pci_fastcom335_setup,
2618 },
2619 {
2620 .vendor = PCI_VENDOR_ID_COMMTECH,
2621 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2622 .subvendor = PCI_ANY_ID,
2623 .subdevice = PCI_ANY_ID,
2624 .setup = pci_xr17v35x_setup,
2625 },
2626 {
2627 .vendor = PCI_VENDOR_ID_COMMTECH,
2628 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2629 .subvendor = PCI_ANY_ID,
2630 .subdevice = PCI_ANY_ID,
2631 .setup = pci_xr17v35x_setup,
2632 },
2633 {
2634 .vendor = PCI_VENDOR_ID_COMMTECH,
2635 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2636 .subvendor = PCI_ANY_ID,
2637 .subdevice = PCI_ANY_ID,
2638 .setup = pci_xr17v35x_setup,
2639 },
2640 /*
2641 * Broadcom TruManage (NetXtreme)
2642 */
2643 {
2644 .vendor = PCI_VENDOR_ID_BROADCOM,
2645 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2646 .subvendor = PCI_ANY_ID,
2647 .subdevice = PCI_ANY_ID,
2648 .setup = pci_brcm_trumanage_setup,
2649 },
2650 {
2651 .vendor = 0x1c29,
2652 .device = 0x1104,
2653 .subvendor = PCI_ANY_ID,
2654 .subdevice = PCI_ANY_ID,
2655 .setup = pci_fintek_setup,
2656 },
2657 {
2658 .vendor = 0x1c29,
2659 .device = 0x1108,
2660 .subvendor = PCI_ANY_ID,
2661 .subdevice = PCI_ANY_ID,
2662 .setup = pci_fintek_setup,
2663 },
2664 {
2665 .vendor = 0x1c29,
2666 .device = 0x1112,
2667 .subvendor = PCI_ANY_ID,
2668 .subdevice = PCI_ANY_ID,
2669 .setup = pci_fintek_setup,
2670 },
2671
2672 /*
2673 * Default "match everything" terminator entry
2674 */
2675 {
2676 .vendor = PCI_ANY_ID,
2677 .device = PCI_ANY_ID,
2678 .subvendor = PCI_ANY_ID,
2679 .subdevice = PCI_ANY_ID,
2680 .setup = pci_default_setup,
2681 }
2682 };
2683
2684 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2685 {
2686 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2687 }
2688
2689 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2690 {
2691 struct pci_serial_quirk *quirk;
2692
2693 for (quirk = pci_serial_quirks; ; quirk++)
2694 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2695 quirk_id_matches(quirk->device, dev->device) &&
2696 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2697 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2698 break;
2699 return quirk;
2700 }
2701
2702 static inline int get_pci_irq(struct pci_dev *dev,
2703 const struct pciserial_board *board)
2704 {
2705 if (board->flags & FL_NOIRQ)
2706 return 0;
2707 else
2708 return dev->irq;
2709 }
2710
2711 /*
2712 * This is the configuration table for all of the PCI serial boards
2713 * which we support. It is directly indexed by the pci_board_num_t enum
2714 * value, which is encoded in the pci_device_id PCI probe table's
2715 * driver_data member.
2716 *
2717 * The makeup of these names are:
2718 * pbn_bn{_bt}_n_baud{_offsetinhex}
2719 *
2720 * bn = PCI BAR number
2721 * bt = Index using PCI BARs
2722 * n = number of serial ports
2723 * baud = baud rate
2724 * offsetinhex = offset for each sequential port (in hex)
2725 *
2726 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2727 *
2728 * Please note: in theory if n = 1, _bt infix should make no difference.
2729 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2730 */
2731 enum pci_board_num_t {
2732 pbn_default = 0,
2733
2734 pbn_b0_1_115200,
2735 pbn_b0_2_115200,
2736 pbn_b0_4_115200,
2737 pbn_b0_5_115200,
2738 pbn_b0_8_115200,
2739
2740 pbn_b0_1_921600,
2741 pbn_b0_2_921600,
2742 pbn_b0_4_921600,
2743
2744 pbn_b0_2_1130000,
2745
2746 pbn_b0_4_1152000,
2747
2748 pbn_b0_2_1152000_200,
2749 pbn_b0_4_1152000_200,
2750 pbn_b0_8_1152000_200,
2751
2752 pbn_b0_2_1843200,
2753 pbn_b0_4_1843200,
2754
2755 pbn_b0_2_1843200_200,
2756 pbn_b0_4_1843200_200,
2757 pbn_b0_8_1843200_200,
2758
2759 pbn_b0_1_4000000,
2760
2761 pbn_b0_bt_1_115200,
2762 pbn_b0_bt_2_115200,
2763 pbn_b0_bt_4_115200,
2764 pbn_b0_bt_8_115200,
2765
2766 pbn_b0_bt_1_460800,
2767 pbn_b0_bt_2_460800,
2768 pbn_b0_bt_4_460800,
2769
2770 pbn_b0_bt_1_921600,
2771 pbn_b0_bt_2_921600,
2772 pbn_b0_bt_4_921600,
2773 pbn_b0_bt_8_921600,
2774
2775 pbn_b1_1_115200,
2776 pbn_b1_2_115200,
2777 pbn_b1_4_115200,
2778 pbn_b1_8_115200,
2779 pbn_b1_16_115200,
2780
2781 pbn_b1_1_921600,
2782 pbn_b1_2_921600,
2783 pbn_b1_4_921600,
2784 pbn_b1_8_921600,
2785
2786 pbn_b1_2_1250000,
2787
2788 pbn_b1_bt_1_115200,
2789 pbn_b1_bt_2_115200,
2790 pbn_b1_bt_4_115200,
2791
2792 pbn_b1_bt_2_921600,
2793
2794 pbn_b1_1_1382400,
2795 pbn_b1_2_1382400,
2796 pbn_b1_4_1382400,
2797 pbn_b1_8_1382400,
2798
2799 pbn_b2_1_115200,
2800 pbn_b2_2_115200,
2801 pbn_b2_4_115200,
2802 pbn_b2_8_115200,
2803
2804 pbn_b2_1_460800,
2805 pbn_b2_4_460800,
2806 pbn_b2_8_460800,
2807 pbn_b2_16_460800,
2808
2809 pbn_b2_1_921600,
2810 pbn_b2_4_921600,
2811 pbn_b2_8_921600,
2812
2813 pbn_b2_8_1152000,
2814
2815 pbn_b2_bt_1_115200,
2816 pbn_b2_bt_2_115200,
2817 pbn_b2_bt_4_115200,
2818
2819 pbn_b2_bt_2_921600,
2820 pbn_b2_bt_4_921600,
2821
2822 pbn_b3_2_115200,
2823 pbn_b3_4_115200,
2824 pbn_b3_8_115200,
2825
2826 pbn_b4_bt_2_921600,
2827 pbn_b4_bt_4_921600,
2828 pbn_b4_bt_8_921600,
2829
2830 /*
2831 * Board-specific versions.
2832 */
2833 pbn_panacom,
2834 pbn_panacom2,
2835 pbn_panacom4,
2836 pbn_plx_romulus,
2837 pbn_endrun_2_4000000,
2838 pbn_oxsemi,
2839 pbn_oxsemi_1_4000000,
2840 pbn_oxsemi_2_4000000,
2841 pbn_oxsemi_4_4000000,
2842 pbn_oxsemi_8_4000000,
2843 pbn_intel_i960,
2844 pbn_sgi_ioc3,
2845 pbn_computone_4,
2846 pbn_computone_6,
2847 pbn_computone_8,
2848 pbn_sbsxrsio,
2849 pbn_exar_XR17C152,
2850 pbn_exar_XR17C154,
2851 pbn_exar_XR17C158,
2852 pbn_exar_XR17V352,
2853 pbn_exar_XR17V354,
2854 pbn_exar_XR17V358,
2855 pbn_exar_ibm_saturn,
2856 pbn_pasemi_1682M,
2857 pbn_ni8430_2,
2858 pbn_ni8430_4,
2859 pbn_ni8430_8,
2860 pbn_ni8430_16,
2861 pbn_ADDIDATA_PCIe_1_3906250,
2862 pbn_ADDIDATA_PCIe_2_3906250,
2863 pbn_ADDIDATA_PCIe_4_3906250,
2864 pbn_ADDIDATA_PCIe_8_3906250,
2865 pbn_ce4100_1_115200,
2866 pbn_byt,
2867 pbn_qrk,
2868 pbn_omegapci,
2869 pbn_NETMOS9900_2s_115200,
2870 pbn_brcm_trumanage,
2871 pbn_fintek_4,
2872 pbn_fintek_8,
2873 pbn_fintek_12,
2874 pbn_wch384_4,
2875 };
2876
2877 /*
2878 * uart_offset - the space between channels
2879 * reg_shift - describes how the UART registers are mapped
2880 * to PCI memory by the card.
2881 * For example IER register on SBS, Inc. PMC-OctPro is located at
2882 * offset 0x10 from the UART base, while UART_IER is defined as 1
2883 * in include/linux/serial_reg.h,
2884 * see first lines of serial_in() and serial_out() in 8250.c
2885 */
2886
2887 static struct pciserial_board pci_boards[] = {
2888 [pbn_default] = {
2889 .flags = FL_BASE0,
2890 .num_ports = 1,
2891 .base_baud = 115200,
2892 .uart_offset = 8,
2893 },
2894 [pbn_b0_1_115200] = {
2895 .flags = FL_BASE0,
2896 .num_ports = 1,
2897 .base_baud = 115200,
2898 .uart_offset = 8,
2899 },
2900 [pbn_b0_2_115200] = {
2901 .flags = FL_BASE0,
2902 .num_ports = 2,
2903 .base_baud = 115200,
2904 .uart_offset = 8,
2905 },
2906 [pbn_b0_4_115200] = {
2907 .flags = FL_BASE0,
2908 .num_ports = 4,
2909 .base_baud = 115200,
2910 .uart_offset = 8,
2911 },
2912 [pbn_b0_5_115200] = {
2913 .flags = FL_BASE0,
2914 .num_ports = 5,
2915 .base_baud = 115200,
2916 .uart_offset = 8,
2917 },
2918 [pbn_b0_8_115200] = {
2919 .flags = FL_BASE0,
2920 .num_ports = 8,
2921 .base_baud = 115200,
2922 .uart_offset = 8,
2923 },
2924 [pbn_b0_1_921600] = {
2925 .flags = FL_BASE0,
2926 .num_ports = 1,
2927 .base_baud = 921600,
2928 .uart_offset = 8,
2929 },
2930 [pbn_b0_2_921600] = {
2931 .flags = FL_BASE0,
2932 .num_ports = 2,
2933 .base_baud = 921600,
2934 .uart_offset = 8,
2935 },
2936 [pbn_b0_4_921600] = {
2937 .flags = FL_BASE0,
2938 .num_ports = 4,
2939 .base_baud = 921600,
2940 .uart_offset = 8,
2941 },
2942
2943 [pbn_b0_2_1130000] = {
2944 .flags = FL_BASE0,
2945 .num_ports = 2,
2946 .base_baud = 1130000,
2947 .uart_offset = 8,
2948 },
2949
2950 [pbn_b0_4_1152000] = {
2951 .flags = FL_BASE0,
2952 .num_ports = 4,
2953 .base_baud = 1152000,
2954 .uart_offset = 8,
2955 },
2956
2957 [pbn_b0_2_1152000_200] = {
2958 .flags = FL_BASE0,
2959 .num_ports = 2,
2960 .base_baud = 1152000,
2961 .uart_offset = 0x200,
2962 },
2963
2964 [pbn_b0_4_1152000_200] = {
2965 .flags = FL_BASE0,
2966 .num_ports = 4,
2967 .base_baud = 1152000,
2968 .uart_offset = 0x200,
2969 },
2970
2971 [pbn_b0_8_1152000_200] = {
2972 .flags = FL_BASE0,
2973 .num_ports = 8,
2974 .base_baud = 1152000,
2975 .uart_offset = 0x200,
2976 },
2977
2978 [pbn_b0_2_1843200] = {
2979 .flags = FL_BASE0,
2980 .num_ports = 2,
2981 .base_baud = 1843200,
2982 .uart_offset = 8,
2983 },
2984 [pbn_b0_4_1843200] = {
2985 .flags = FL_BASE0,
2986 .num_ports = 4,
2987 .base_baud = 1843200,
2988 .uart_offset = 8,
2989 },
2990
2991 [pbn_b0_2_1843200_200] = {
2992 .flags = FL_BASE0,
2993 .num_ports = 2,
2994 .base_baud = 1843200,
2995 .uart_offset = 0x200,
2996 },
2997 [pbn_b0_4_1843200_200] = {
2998 .flags = FL_BASE0,
2999 .num_ports = 4,
3000 .base_baud = 1843200,
3001 .uart_offset = 0x200,
3002 },
3003 [pbn_b0_8_1843200_200] = {
3004 .flags = FL_BASE0,
3005 .num_ports = 8,
3006 .base_baud = 1843200,
3007 .uart_offset = 0x200,
3008 },
3009 [pbn_b0_1_4000000] = {
3010 .flags = FL_BASE0,
3011 .num_ports = 1,
3012 .base_baud = 4000000,
3013 .uart_offset = 8,
3014 },
3015
3016 [pbn_b0_bt_1_115200] = {
3017 .flags = FL_BASE0|FL_BASE_BARS,
3018 .num_ports = 1,
3019 .base_baud = 115200,
3020 .uart_offset = 8,
3021 },
3022 [pbn_b0_bt_2_115200] = {
3023 .flags = FL_BASE0|FL_BASE_BARS,
3024 .num_ports = 2,
3025 .base_baud = 115200,
3026 .uart_offset = 8,
3027 },
3028 [pbn_b0_bt_4_115200] = {
3029 .flags = FL_BASE0|FL_BASE_BARS,
3030 .num_ports = 4,
3031 .base_baud = 115200,
3032 .uart_offset = 8,
3033 },
3034 [pbn_b0_bt_8_115200] = {
3035 .flags = FL_BASE0|FL_BASE_BARS,
3036 .num_ports = 8,
3037 .base_baud = 115200,
3038 .uart_offset = 8,
3039 },
3040
3041 [pbn_b0_bt_1_460800] = {
3042 .flags = FL_BASE0|FL_BASE_BARS,
3043 .num_ports = 1,
3044 .base_baud = 460800,
3045 .uart_offset = 8,
3046 },
3047 [pbn_b0_bt_2_460800] = {
3048 .flags = FL_BASE0|FL_BASE_BARS,
3049 .num_ports = 2,
3050 .base_baud = 460800,
3051 .uart_offset = 8,
3052 },
3053 [pbn_b0_bt_4_460800] = {
3054 .flags = FL_BASE0|FL_BASE_BARS,
3055 .num_ports = 4,
3056 .base_baud = 460800,
3057 .uart_offset = 8,
3058 },
3059
3060 [pbn_b0_bt_1_921600] = {
3061 .flags = FL_BASE0|FL_BASE_BARS,
3062 .num_ports = 1,
3063 .base_baud = 921600,
3064 .uart_offset = 8,
3065 },
3066 [pbn_b0_bt_2_921600] = {
3067 .flags = FL_BASE0|FL_BASE_BARS,
3068 .num_ports = 2,
3069 .base_baud = 921600,
3070 .uart_offset = 8,
3071 },
3072 [pbn_b0_bt_4_921600] = {
3073 .flags = FL_BASE0|FL_BASE_BARS,
3074 .num_ports = 4,
3075 .base_baud = 921600,
3076 .uart_offset = 8,
3077 },
3078 [pbn_b0_bt_8_921600] = {
3079 .flags = FL_BASE0|FL_BASE_BARS,
3080 .num_ports = 8,
3081 .base_baud = 921600,
3082 .uart_offset = 8,
3083 },
3084
3085 [pbn_b1_1_115200] = {
3086 .flags = FL_BASE1,
3087 .num_ports = 1,
3088 .base_baud = 115200,
3089 .uart_offset = 8,
3090 },
3091 [pbn_b1_2_115200] = {
3092 .flags = FL_BASE1,
3093 .num_ports = 2,
3094 .base_baud = 115200,
3095 .uart_offset = 8,
3096 },
3097 [pbn_b1_4_115200] = {
3098 .flags = FL_BASE1,
3099 .num_ports = 4,
3100 .base_baud = 115200,
3101 .uart_offset = 8,
3102 },
3103 [pbn_b1_8_115200] = {
3104 .flags = FL_BASE1,
3105 .num_ports = 8,
3106 .base_baud = 115200,
3107 .uart_offset = 8,
3108 },
3109 [pbn_b1_16_115200] = {
3110 .flags = FL_BASE1,
3111 .num_ports = 16,
3112 .base_baud = 115200,
3113 .uart_offset = 8,
3114 },
3115
3116 [pbn_b1_1_921600] = {
3117 .flags = FL_BASE1,
3118 .num_ports = 1,
3119 .base_baud = 921600,
3120 .uart_offset = 8,
3121 },
3122 [pbn_b1_2_921600] = {
3123 .flags = FL_BASE1,
3124 .num_ports = 2,
3125 .base_baud = 921600,
3126 .uart_offset = 8,
3127 },
3128 [pbn_b1_4_921600] = {
3129 .flags = FL_BASE1,
3130 .num_ports = 4,
3131 .base_baud = 921600,
3132 .uart_offset = 8,
3133 },
3134 [pbn_b1_8_921600] = {
3135 .flags = FL_BASE1,
3136 .num_ports = 8,
3137 .base_baud = 921600,
3138 .uart_offset = 8,
3139 },
3140 [pbn_b1_2_1250000] = {
3141 .flags = FL_BASE1,
3142 .num_ports = 2,
3143 .base_baud = 1250000,
3144 .uart_offset = 8,
3145 },
3146
3147 [pbn_b1_bt_1_115200] = {
3148 .flags = FL_BASE1|FL_BASE_BARS,
3149 .num_ports = 1,
3150 .base_baud = 115200,
3151 .uart_offset = 8,
3152 },
3153 [pbn_b1_bt_2_115200] = {
3154 .flags = FL_BASE1|FL_BASE_BARS,
3155 .num_ports = 2,
3156 .base_baud = 115200,
3157 .uart_offset = 8,
3158 },
3159 [pbn_b1_bt_4_115200] = {
3160 .flags = FL_BASE1|FL_BASE_BARS,
3161 .num_ports = 4,
3162 .base_baud = 115200,
3163 .uart_offset = 8,
3164 },
3165
3166 [pbn_b1_bt_2_921600] = {
3167 .flags = FL_BASE1|FL_BASE_BARS,
3168 .num_ports = 2,
3169 .base_baud = 921600,
3170 .uart_offset = 8,
3171 },
3172
3173 [pbn_b1_1_1382400] = {
3174 .flags = FL_BASE1,
3175 .num_ports = 1,
3176 .base_baud = 1382400,
3177 .uart_offset = 8,
3178 },
3179 [pbn_b1_2_1382400] = {
3180 .flags = FL_BASE1,
3181 .num_ports = 2,
3182 .base_baud = 1382400,
3183 .uart_offset = 8,
3184 },
3185 [pbn_b1_4_1382400] = {
3186 .flags = FL_BASE1,
3187 .num_ports = 4,
3188 .base_baud = 1382400,
3189 .uart_offset = 8,
3190 },
3191 [pbn_b1_8_1382400] = {
3192 .flags = FL_BASE1,
3193 .num_ports = 8,
3194 .base_baud = 1382400,
3195 .uart_offset = 8,
3196 },
3197
3198 [pbn_b2_1_115200] = {
3199 .flags = FL_BASE2,
3200 .num_ports = 1,
3201 .base_baud = 115200,
3202 .uart_offset = 8,
3203 },
3204 [pbn_b2_2_115200] = {
3205 .flags = FL_BASE2,
3206 .num_ports = 2,
3207 .base_baud = 115200,
3208 .uart_offset = 8,
3209 },
3210 [pbn_b2_4_115200] = {
3211 .flags = FL_BASE2,
3212 .num_ports = 4,
3213 .base_baud = 115200,
3214 .uart_offset = 8,
3215 },
3216 [pbn_b2_8_115200] = {
3217 .flags = FL_BASE2,
3218 .num_ports = 8,
3219 .base_baud = 115200,
3220 .uart_offset = 8,
3221 },
3222
3223 [pbn_b2_1_460800] = {
3224 .flags = FL_BASE2,
3225 .num_ports = 1,
3226 .base_baud = 460800,
3227 .uart_offset = 8,
3228 },
3229 [pbn_b2_4_460800] = {
3230 .flags = FL_BASE2,
3231 .num_ports = 4,
3232 .base_baud = 460800,
3233 .uart_offset = 8,
3234 },
3235 [pbn_b2_8_460800] = {
3236 .flags = FL_BASE2,
3237 .num_ports = 8,
3238 .base_baud = 460800,
3239 .uart_offset = 8,
3240 },
3241 [pbn_b2_16_460800] = {
3242 .flags = FL_BASE2,
3243 .num_ports = 16,
3244 .base_baud = 460800,
3245 .uart_offset = 8,
3246 },
3247
3248 [pbn_b2_1_921600] = {
3249 .flags = FL_BASE2,
3250 .num_ports = 1,
3251 .base_baud = 921600,
3252 .uart_offset = 8,
3253 },
3254 [pbn_b2_4_921600] = {
3255 .flags = FL_BASE2,
3256 .num_ports = 4,
3257 .base_baud = 921600,
3258 .uart_offset = 8,
3259 },
3260 [pbn_b2_8_921600] = {
3261 .flags = FL_BASE2,
3262 .num_ports = 8,
3263 .base_baud = 921600,
3264 .uart_offset = 8,
3265 },
3266
3267 [pbn_b2_8_1152000] = {
3268 .flags = FL_BASE2,
3269 .num_ports = 8,
3270 .base_baud = 1152000,
3271 .uart_offset = 8,
3272 },
3273
3274 [pbn_b2_bt_1_115200] = {
3275 .flags = FL_BASE2|FL_BASE_BARS,
3276 .num_ports = 1,
3277 .base_baud = 115200,
3278 .uart_offset = 8,
3279 },
3280 [pbn_b2_bt_2_115200] = {
3281 .flags = FL_BASE2|FL_BASE_BARS,
3282 .num_ports = 2,
3283 .base_baud = 115200,
3284 .uart_offset = 8,
3285 },
3286 [pbn_b2_bt_4_115200] = {
3287 .flags = FL_BASE2|FL_BASE_BARS,
3288 .num_ports = 4,
3289 .base_baud = 115200,
3290 .uart_offset = 8,
3291 },
3292
3293 [pbn_b2_bt_2_921600] = {
3294 .flags = FL_BASE2|FL_BASE_BARS,
3295 .num_ports = 2,
3296 .base_baud = 921600,
3297 .uart_offset = 8,
3298 },
3299 [pbn_b2_bt_4_921600] = {
3300 .flags = FL_BASE2|FL_BASE_BARS,
3301 .num_ports = 4,
3302 .base_baud = 921600,
3303 .uart_offset = 8,
3304 },
3305
3306 [pbn_b3_2_115200] = {
3307 .flags = FL_BASE3,
3308 .num_ports = 2,
3309 .base_baud = 115200,
3310 .uart_offset = 8,
3311 },
3312 [pbn_b3_4_115200] = {
3313 .flags = FL_BASE3,
3314 .num_ports = 4,
3315 .base_baud = 115200,
3316 .uart_offset = 8,
3317 },
3318 [pbn_b3_8_115200] = {
3319 .flags = FL_BASE3,
3320 .num_ports = 8,
3321 .base_baud = 115200,
3322 .uart_offset = 8,
3323 },
3324
3325 [pbn_b4_bt_2_921600] = {
3326 .flags = FL_BASE4,
3327 .num_ports = 2,
3328 .base_baud = 921600,
3329 .uart_offset = 8,
3330 },
3331 [pbn_b4_bt_4_921600] = {
3332 .flags = FL_BASE4,
3333 .num_ports = 4,
3334 .base_baud = 921600,
3335 .uart_offset = 8,
3336 },
3337 [pbn_b4_bt_8_921600] = {
3338 .flags = FL_BASE4,
3339 .num_ports = 8,
3340 .base_baud = 921600,
3341 .uart_offset = 8,
3342 },
3343
3344 /*
3345 * Entries following this are board-specific.
3346 */
3347
3348 /*
3349 * Panacom - IOMEM
3350 */
3351 [pbn_panacom] = {
3352 .flags = FL_BASE2,
3353 .num_ports = 2,
3354 .base_baud = 921600,
3355 .uart_offset = 0x400,
3356 .reg_shift = 7,
3357 },
3358 [pbn_panacom2] = {
3359 .flags = FL_BASE2|FL_BASE_BARS,
3360 .num_ports = 2,
3361 .base_baud = 921600,
3362 .uart_offset = 0x400,
3363 .reg_shift = 7,
3364 },
3365 [pbn_panacom4] = {
3366 .flags = FL_BASE2|FL_BASE_BARS,
3367 .num_ports = 4,
3368 .base_baud = 921600,
3369 .uart_offset = 0x400,
3370 .reg_shift = 7,
3371 },
3372
3373 /* I think this entry is broken - the first_offset looks wrong --rmk */
3374 [pbn_plx_romulus] = {
3375 .flags = FL_BASE2,
3376 .num_ports = 4,
3377 .base_baud = 921600,
3378 .uart_offset = 8 << 2,
3379 .reg_shift = 2,
3380 .first_offset = 0x03,
3381 },
3382
3383 /*
3384 * EndRun Technologies
3385 * Uses the size of PCI Base region 0 to
3386 * signal now many ports are available
3387 * 2 port 952 Uart support
3388 */
3389 [pbn_endrun_2_4000000] = {
3390 .flags = FL_BASE0,
3391 .num_ports = 2,
3392 .base_baud = 4000000,
3393 .uart_offset = 0x200,
3394 .first_offset = 0x1000,
3395 },
3396
3397 /*
3398 * This board uses the size of PCI Base region 0 to
3399 * signal now many ports are available
3400 */
3401 [pbn_oxsemi] = {
3402 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3403 .num_ports = 32,
3404 .base_baud = 115200,
3405 .uart_offset = 8,
3406 },
3407 [pbn_oxsemi_1_4000000] = {
3408 .flags = FL_BASE0,
3409 .num_ports = 1,
3410 .base_baud = 4000000,
3411 .uart_offset = 0x200,
3412 .first_offset = 0x1000,
3413 },
3414 [pbn_oxsemi_2_4000000] = {
3415 .flags = FL_BASE0,
3416 .num_ports = 2,
3417 .base_baud = 4000000,
3418 .uart_offset = 0x200,
3419 .first_offset = 0x1000,
3420 },
3421 [pbn_oxsemi_4_4000000] = {
3422 .flags = FL_BASE0,
3423 .num_ports = 4,
3424 .base_baud = 4000000,
3425 .uart_offset = 0x200,
3426 .first_offset = 0x1000,
3427 },
3428 [pbn_oxsemi_8_4000000] = {
3429 .flags = FL_BASE0,
3430 .num_ports = 8,
3431 .base_baud = 4000000,
3432 .uart_offset = 0x200,
3433 .first_offset = 0x1000,
3434 },
3435
3436
3437 /*
3438 * EKF addition for i960 Boards form EKF with serial port.
3439 * Max 256 ports.
3440 */
3441 [pbn_intel_i960] = {
3442 .flags = FL_BASE0,
3443 .num_ports = 32,
3444 .base_baud = 921600,
3445 .uart_offset = 8 << 2,
3446 .reg_shift = 2,
3447 .first_offset = 0x10000,
3448 },
3449 [pbn_sgi_ioc3] = {
3450 .flags = FL_BASE0|FL_NOIRQ,
3451 .num_ports = 1,
3452 .base_baud = 458333,
3453 .uart_offset = 8,
3454 .reg_shift = 0,
3455 .first_offset = 0x20178,
3456 },
3457
3458 /*
3459 * Computone - uses IOMEM.
3460 */
3461 [pbn_computone_4] = {
3462 .flags = FL_BASE0,
3463 .num_ports = 4,
3464 .base_baud = 921600,
3465 .uart_offset = 0x40,
3466 .reg_shift = 2,
3467 .first_offset = 0x200,
3468 },
3469 [pbn_computone_6] = {
3470 .flags = FL_BASE0,
3471 .num_ports = 6,
3472 .base_baud = 921600,
3473 .uart_offset = 0x40,
3474 .reg_shift = 2,
3475 .first_offset = 0x200,
3476 },
3477 [pbn_computone_8] = {
3478 .flags = FL_BASE0,
3479 .num_ports = 8,
3480 .base_baud = 921600,
3481 .uart_offset = 0x40,
3482 .reg_shift = 2,
3483 .first_offset = 0x200,
3484 },
3485 [pbn_sbsxrsio] = {
3486 .flags = FL_BASE0,
3487 .num_ports = 8,
3488 .base_baud = 460800,
3489 .uart_offset = 256,
3490 .reg_shift = 4,
3491 },
3492 /*
3493 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3494 * Only basic 16550A support.
3495 * XR17C15[24] are not tested, but they should work.
3496 */
3497 [pbn_exar_XR17C152] = {
3498 .flags = FL_BASE0,
3499 .num_ports = 2,
3500 .base_baud = 921600,
3501 .uart_offset = 0x200,
3502 },
3503 [pbn_exar_XR17C154] = {
3504 .flags = FL_BASE0,
3505 .num_ports = 4,
3506 .base_baud = 921600,
3507 .uart_offset = 0x200,
3508 },
3509 [pbn_exar_XR17C158] = {
3510 .flags = FL_BASE0,
3511 .num_ports = 8,
3512 .base_baud = 921600,
3513 .uart_offset = 0x200,
3514 },
3515 [pbn_exar_XR17V352] = {
3516 .flags = FL_BASE0,
3517 .num_ports = 2,
3518 .base_baud = 7812500,
3519 .uart_offset = 0x400,
3520 .reg_shift = 0,
3521 .first_offset = 0,
3522 },
3523 [pbn_exar_XR17V354] = {
3524 .flags = FL_BASE0,
3525 .num_ports = 4,
3526 .base_baud = 7812500,
3527 .uart_offset = 0x400,
3528 .reg_shift = 0,
3529 .first_offset = 0,
3530 },
3531 [pbn_exar_XR17V358] = {
3532 .flags = FL_BASE0,
3533 .num_ports = 8,
3534 .base_baud = 7812500,
3535 .uart_offset = 0x400,
3536 .reg_shift = 0,
3537 .first_offset = 0,
3538 },
3539 [pbn_exar_ibm_saturn] = {
3540 .flags = FL_BASE0,
3541 .num_ports = 1,
3542 .base_baud = 921600,
3543 .uart_offset = 0x200,
3544 },
3545
3546 /*
3547 * PA Semi PWRficient PA6T-1682M on-chip UART
3548 */
3549 [pbn_pasemi_1682M] = {
3550 .flags = FL_BASE0,
3551 .num_ports = 1,
3552 .base_baud = 8333333,
3553 },
3554 /*
3555 * National Instruments 843x
3556 */
3557 [pbn_ni8430_16] = {
3558 .flags = FL_BASE0,
3559 .num_ports = 16,
3560 .base_baud = 3686400,
3561 .uart_offset = 0x10,
3562 .first_offset = 0x800,
3563 },
3564 [pbn_ni8430_8] = {
3565 .flags = FL_BASE0,
3566 .num_ports = 8,
3567 .base_baud = 3686400,
3568 .uart_offset = 0x10,
3569 .first_offset = 0x800,
3570 },
3571 [pbn_ni8430_4] = {
3572 .flags = FL_BASE0,
3573 .num_ports = 4,
3574 .base_baud = 3686400,
3575 .uart_offset = 0x10,
3576 .first_offset = 0x800,
3577 },
3578 [pbn_ni8430_2] = {
3579 .flags = FL_BASE0,
3580 .num_ports = 2,
3581 .base_baud = 3686400,
3582 .uart_offset = 0x10,
3583 .first_offset = 0x800,
3584 },
3585 /*
3586 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3587 */
3588 [pbn_ADDIDATA_PCIe_1_3906250] = {
3589 .flags = FL_BASE0,
3590 .num_ports = 1,
3591 .base_baud = 3906250,
3592 .uart_offset = 0x200,
3593 .first_offset = 0x1000,
3594 },
3595 [pbn_ADDIDATA_PCIe_2_3906250] = {
3596 .flags = FL_BASE0,
3597 .num_ports = 2,
3598 .base_baud = 3906250,
3599 .uart_offset = 0x200,
3600 .first_offset = 0x1000,
3601 },
3602 [pbn_ADDIDATA_PCIe_4_3906250] = {
3603 .flags = FL_BASE0,
3604 .num_ports = 4,
3605 .base_baud = 3906250,
3606 .uart_offset = 0x200,
3607 .first_offset = 0x1000,
3608 },
3609 [pbn_ADDIDATA_PCIe_8_3906250] = {
3610 .flags = FL_BASE0,
3611 .num_ports = 8,
3612 .base_baud = 3906250,
3613 .uart_offset = 0x200,
3614 .first_offset = 0x1000,
3615 },
3616 [pbn_ce4100_1_115200] = {
3617 .flags = FL_BASE_BARS,
3618 .num_ports = 2,
3619 .base_baud = 921600,
3620 .reg_shift = 2,
3621 },
3622 /*
3623 * Intel BayTrail HSUART reference clock is 44.2368 MHz at power-on,
3624 * but is overridden by byt_set_termios.
3625 */
3626 [pbn_byt] = {
3627 .flags = FL_BASE0,
3628 .num_ports = 1,
3629 .base_baud = 2764800,
3630 .uart_offset = 0x80,
3631 .reg_shift = 2,
3632 },
3633 [pbn_qrk] = {
3634 .flags = FL_BASE0,
3635 .num_ports = 1,
3636 .base_baud = 2764800,
3637 .reg_shift = 2,
3638 },
3639 [pbn_omegapci] = {
3640 .flags = FL_BASE0,
3641 .num_ports = 8,
3642 .base_baud = 115200,
3643 .uart_offset = 0x200,
3644 },
3645 [pbn_NETMOS9900_2s_115200] = {
3646 .flags = FL_BASE0,
3647 .num_ports = 2,
3648 .base_baud = 115200,
3649 },
3650 [pbn_brcm_trumanage] = {
3651 .flags = FL_BASE0,
3652 .num_ports = 1,
3653 .reg_shift = 2,
3654 .base_baud = 115200,
3655 },
3656 [pbn_fintek_4] = {
3657 .num_ports = 4,
3658 .uart_offset = 8,
3659 .base_baud = 115200,
3660 .first_offset = 0x40,
3661 },
3662 [pbn_fintek_8] = {
3663 .num_ports = 8,
3664 .uart_offset = 8,
3665 .base_baud = 115200,
3666 .first_offset = 0x40,
3667 },
3668 [pbn_fintek_12] = {
3669 .num_ports = 12,
3670 .uart_offset = 8,
3671 .base_baud = 115200,
3672 .first_offset = 0x40,
3673 },
3674
3675 [pbn_wch384_4] = {
3676 .flags = FL_BASE0,
3677 .num_ports = 4,
3678 .base_baud = 115200,
3679 .uart_offset = 8,
3680 .first_offset = 0xC0,
3681 },
3682 };
3683
3684 static const struct pci_device_id blacklist[] = {
3685 /* softmodems */
3686 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3687 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3688 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3689
3690 /* multi-io cards handled by parport_serial */
3691 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3692 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3693 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3694 { PCI_DEVICE(0x1c00, 0x3470), }, /* WCH CH384 4S */
3695 };
3696
3697 /*
3698 * Given a complete unknown PCI device, try to use some heuristics to
3699 * guess what the configuration might be, based on the pitiful PCI
3700 * serial specs. Returns 0 on success, 1 on failure.
3701 */
3702 static int
3703 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3704 {
3705 const struct pci_device_id *bldev;
3706 int num_iomem, num_port, first_port = -1, i;
3707
3708 /*
3709 * If it is not a communications device or the programming
3710 * interface is greater than 6, give up.
3711 *
3712 * (Should we try to make guesses for multiport serial devices
3713 * later?)
3714 */
3715 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3716 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3717 (dev->class & 0xff) > 6)
3718 return -ENODEV;
3719
3720 /*
3721 * Do not access blacklisted devices that are known not to
3722 * feature serial ports or are handled by other modules.
3723 */
3724 for (bldev = blacklist;
3725 bldev < blacklist + ARRAY_SIZE(blacklist);
3726 bldev++) {
3727 if (dev->vendor == bldev->vendor &&
3728 dev->device == bldev->device)
3729 return -ENODEV;
3730 }
3731
3732 num_iomem = num_port = 0;
3733 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3734 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3735 num_port++;
3736 if (first_port == -1)
3737 first_port = i;
3738 }
3739 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3740 num_iomem++;
3741 }
3742
3743 /*
3744 * If there is 1 or 0 iomem regions, and exactly one port,
3745 * use it. We guess the number of ports based on the IO
3746 * region size.
3747 */
3748 if (num_iomem <= 1 && num_port == 1) {
3749 board->flags = first_port;
3750 board->num_ports = pci_resource_len(dev, first_port) / 8;
3751 return 0;
3752 }
3753
3754 /*
3755 * Now guess if we've got a board which indexes by BARs.
3756 * Each IO BAR should be 8 bytes, and they should follow
3757 * consecutively.
3758 */
3759 first_port = -1;
3760 num_port = 0;
3761 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3762 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3763 pci_resource_len(dev, i) == 8 &&
3764 (first_port == -1 || (first_port + num_port) == i)) {
3765 num_port++;
3766 if (first_port == -1)
3767 first_port = i;
3768 }
3769 }
3770
3771 if (num_port > 1) {
3772 board->flags = first_port | FL_BASE_BARS;
3773 board->num_ports = num_port;
3774 return 0;
3775 }
3776
3777 return -ENODEV;
3778 }
3779
3780 static inline int
3781 serial_pci_matches(const struct pciserial_board *board,
3782 const struct pciserial_board *guessed)
3783 {
3784 return
3785 board->num_ports == guessed->num_ports &&
3786 board->base_baud == guessed->base_baud &&
3787 board->uart_offset == guessed->uart_offset &&
3788 board->reg_shift == guessed->reg_shift &&
3789 board->first_offset == guessed->first_offset;
3790 }
3791
3792 struct serial_private *
3793 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3794 {
3795 struct uart_8250_port uart;
3796 struct serial_private *priv;
3797 struct pci_serial_quirk *quirk;
3798 int rc, nr_ports, i;
3799
3800 nr_ports = board->num_ports;
3801
3802 /*
3803 * Find an init and setup quirks.
3804 */
3805 quirk = find_quirk(dev);
3806
3807 /*
3808 * Run the new-style initialization function.
3809 * The initialization function returns:
3810 * <0 - error
3811 * 0 - use board->num_ports
3812 * >0 - number of ports
3813 */
3814 if (quirk->init) {
3815 rc = quirk->init(dev);
3816 if (rc < 0) {
3817 priv = ERR_PTR(rc);
3818 goto err_out;
3819 }
3820 if (rc)
3821 nr_ports = rc;
3822 }
3823
3824 priv = kzalloc(sizeof(struct serial_private) +
3825 sizeof(unsigned int) * nr_ports,
3826 GFP_KERNEL);
3827 if (!priv) {
3828 priv = ERR_PTR(-ENOMEM);
3829 goto err_deinit;
3830 }
3831
3832 priv->dev = dev;
3833 priv->quirk = quirk;
3834
3835 memset(&uart, 0, sizeof(uart));
3836 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3837 uart.port.uartclk = board->base_baud * 16;
3838 uart.port.irq = get_pci_irq(dev, board);
3839 uart.port.dev = &dev->dev;
3840
3841 for (i = 0; i < nr_ports; i++) {
3842 if (quirk->setup(priv, board, &uart, i))
3843 break;
3844
3845 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3846 uart.port.iobase, uart.port.irq, uart.port.iotype);
3847
3848 priv->line[i] = serial8250_register_8250_port(&uart);
3849 if (priv->line[i] < 0) {
3850 dev_err(&dev->dev,
3851 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3852 uart.port.iobase, uart.port.irq,
3853 uart.port.iotype, priv->line[i]);
3854 break;
3855 }
3856 }
3857 priv->nr = i;
3858 return priv;
3859
3860 err_deinit:
3861 if (quirk->exit)
3862 quirk->exit(dev);
3863 err_out:
3864 return priv;
3865 }
3866 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3867
3868 void pciserial_remove_ports(struct serial_private *priv)
3869 {
3870 struct pci_serial_quirk *quirk;
3871 int i;
3872
3873 for (i = 0; i < priv->nr; i++)
3874 serial8250_unregister_port(priv->line[i]);
3875
3876 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3877 if (priv->remapped_bar[i])
3878 iounmap(priv->remapped_bar[i]);
3879 priv->remapped_bar[i] = NULL;
3880 }
3881
3882 /*
3883 * Find the exit quirks.
3884 */
3885 quirk = find_quirk(priv->dev);
3886 if (quirk->exit)
3887 quirk->exit(priv->dev);
3888
3889 kfree(priv);
3890 }
3891 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3892
3893 void pciserial_suspend_ports(struct serial_private *priv)
3894 {
3895 int i;
3896
3897 for (i = 0; i < priv->nr; i++)
3898 if (priv->line[i] >= 0)
3899 serial8250_suspend_port(priv->line[i]);
3900
3901 /*
3902 * Ensure that every init quirk is properly torn down
3903 */
3904 if (priv->quirk->exit)
3905 priv->quirk->exit(priv->dev);
3906 }
3907 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3908
3909 void pciserial_resume_ports(struct serial_private *priv)
3910 {
3911 int i;
3912
3913 /*
3914 * Ensure that the board is correctly configured.
3915 */
3916 if (priv->quirk->init)
3917 priv->quirk->init(priv->dev);
3918
3919 for (i = 0; i < priv->nr; i++)
3920 if (priv->line[i] >= 0)
3921 serial8250_resume_port(priv->line[i]);
3922 }
3923 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3924
3925 /*
3926 * Probe one serial board. Unfortunately, there is no rhyme nor reason
3927 * to the arrangement of serial ports on a PCI card.
3928 */
3929 static int
3930 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3931 {
3932 struct pci_serial_quirk *quirk;
3933 struct serial_private *priv;
3934 const struct pciserial_board *board;
3935 struct pciserial_board tmp;
3936 int rc;
3937
3938 quirk = find_quirk(dev);
3939 if (quirk->probe) {
3940 rc = quirk->probe(dev);
3941 if (rc)
3942 return rc;
3943 }
3944
3945 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3946 dev_err(&dev->dev, "invalid driver_data: %ld\n",
3947 ent->driver_data);
3948 return -EINVAL;
3949 }
3950
3951 board = &pci_boards[ent->driver_data];
3952
3953 rc = pci_enable_device(dev);
3954 pci_save_state(dev);
3955 if (rc)
3956 return rc;
3957
3958 if (ent->driver_data == pbn_default) {
3959 /*
3960 * Use a copy of the pci_board entry for this;
3961 * avoid changing entries in the table.
3962 */
3963 memcpy(&tmp, board, sizeof(struct pciserial_board));
3964 board = &tmp;
3965
3966 /*
3967 * We matched one of our class entries. Try to
3968 * determine the parameters of this board.
3969 */
3970 rc = serial_pci_guess_board(dev, &tmp);
3971 if (rc)
3972 goto disable;
3973 } else {
3974 /*
3975 * We matched an explicit entry. If we are able to
3976 * detect this boards settings with our heuristic,
3977 * then we no longer need this entry.
3978 */
3979 memcpy(&tmp, &pci_boards[pbn_default],
3980 sizeof(struct pciserial_board));
3981 rc = serial_pci_guess_board(dev, &tmp);
3982 if (rc == 0 && serial_pci_matches(board, &tmp))
3983 moan_device("Redundant entry in serial pci_table.",
3984 dev);
3985 }
3986
3987 priv = pciserial_init_ports(dev, board);
3988 if (!IS_ERR(priv)) {
3989 pci_set_drvdata(dev, priv);
3990 return 0;
3991 }
3992
3993 rc = PTR_ERR(priv);
3994
3995 disable:
3996 pci_disable_device(dev);
3997 return rc;
3998 }
3999
4000 static void pciserial_remove_one(struct pci_dev *dev)
4001 {
4002 struct serial_private *priv = pci_get_drvdata(dev);
4003
4004 pciserial_remove_ports(priv);
4005
4006 pci_disable_device(dev);
4007 }
4008
4009 #ifdef CONFIG_PM
4010 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
4011 {
4012 struct serial_private *priv = pci_get_drvdata(dev);
4013
4014 if (priv)
4015 pciserial_suspend_ports(priv);
4016
4017 pci_save_state(dev);
4018 pci_set_power_state(dev, pci_choose_state(dev, state));
4019 return 0;
4020 }
4021
4022 static int pciserial_resume_one(struct pci_dev *dev)
4023 {
4024 int err;
4025 struct serial_private *priv = pci_get_drvdata(dev);
4026
4027 pci_set_power_state(dev, PCI_D0);
4028 pci_restore_state(dev);
4029
4030 if (priv) {
4031 /*
4032 * The device may have been disabled. Re-enable it.
4033 */
4034 err = pci_enable_device(dev);
4035 /* FIXME: We cannot simply error out here */
4036 if (err)
4037 dev_err(&dev->dev, "Unable to re-enable ports, trying to continue.\n");
4038 pciserial_resume_ports(priv);
4039 }
4040 return 0;
4041 }
4042 #endif
4043
4044 static struct pci_device_id serial_pci_tbl[] = {
4045 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4046 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4047 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4048 pbn_b2_8_921600 },
4049 /* Advantech also use 0x3618 and 0xf618 */
4050 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4051 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4052 pbn_b0_4_921600 },
4053 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4054 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4055 pbn_b0_4_921600 },
4056 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4057 PCI_SUBVENDOR_ID_CONNECT_TECH,
4058 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4059 pbn_b1_8_1382400 },
4060 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4061 PCI_SUBVENDOR_ID_CONNECT_TECH,
4062 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4063 pbn_b1_4_1382400 },
4064 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4065 PCI_SUBVENDOR_ID_CONNECT_TECH,
4066 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4067 pbn_b1_2_1382400 },
4068 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4069 PCI_SUBVENDOR_ID_CONNECT_TECH,
4070 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4071 pbn_b1_8_1382400 },
4072 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4073 PCI_SUBVENDOR_ID_CONNECT_TECH,
4074 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4075 pbn_b1_4_1382400 },
4076 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4077 PCI_SUBVENDOR_ID_CONNECT_TECH,
4078 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4079 pbn_b1_2_1382400 },
4080 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4081 PCI_SUBVENDOR_ID_CONNECT_TECH,
4082 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4083 pbn_b1_8_921600 },
4084 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4085 PCI_SUBVENDOR_ID_CONNECT_TECH,
4086 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4087 pbn_b1_8_921600 },
4088 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4089 PCI_SUBVENDOR_ID_CONNECT_TECH,
4090 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4091 pbn_b1_4_921600 },
4092 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4093 PCI_SUBVENDOR_ID_CONNECT_TECH,
4094 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4095 pbn_b1_4_921600 },
4096 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4097 PCI_SUBVENDOR_ID_CONNECT_TECH,
4098 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4099 pbn_b1_2_921600 },
4100 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4101 PCI_SUBVENDOR_ID_CONNECT_TECH,
4102 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4103 pbn_b1_8_921600 },
4104 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4105 PCI_SUBVENDOR_ID_CONNECT_TECH,
4106 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4107 pbn_b1_8_921600 },
4108 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4109 PCI_SUBVENDOR_ID_CONNECT_TECH,
4110 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4111 pbn_b1_4_921600 },
4112 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4113 PCI_SUBVENDOR_ID_CONNECT_TECH,
4114 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4115 pbn_b1_2_1250000 },
4116 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4117 PCI_SUBVENDOR_ID_CONNECT_TECH,
4118 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4119 pbn_b0_2_1843200 },
4120 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4121 PCI_SUBVENDOR_ID_CONNECT_TECH,
4122 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4123 pbn_b0_4_1843200 },
4124 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4125 PCI_VENDOR_ID_AFAVLAB,
4126 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4127 pbn_b0_4_1152000 },
4128 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4129 PCI_SUBVENDOR_ID_CONNECT_TECH,
4130 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
4131 pbn_b0_2_1843200_200 },
4132 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4133 PCI_SUBVENDOR_ID_CONNECT_TECH,
4134 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
4135 pbn_b0_4_1843200_200 },
4136 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4137 PCI_SUBVENDOR_ID_CONNECT_TECH,
4138 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
4139 pbn_b0_8_1843200_200 },
4140 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4141 PCI_SUBVENDOR_ID_CONNECT_TECH,
4142 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
4143 pbn_b0_2_1843200_200 },
4144 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4145 PCI_SUBVENDOR_ID_CONNECT_TECH,
4146 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
4147 pbn_b0_4_1843200_200 },
4148 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4149 PCI_SUBVENDOR_ID_CONNECT_TECH,
4150 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
4151 pbn_b0_8_1843200_200 },
4152 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4153 PCI_SUBVENDOR_ID_CONNECT_TECH,
4154 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
4155 pbn_b0_2_1843200_200 },
4156 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4157 PCI_SUBVENDOR_ID_CONNECT_TECH,
4158 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
4159 pbn_b0_4_1843200_200 },
4160 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4161 PCI_SUBVENDOR_ID_CONNECT_TECH,
4162 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
4163 pbn_b0_8_1843200_200 },
4164 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4165 PCI_SUBVENDOR_ID_CONNECT_TECH,
4166 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
4167 pbn_b0_2_1843200_200 },
4168 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4169 PCI_SUBVENDOR_ID_CONNECT_TECH,
4170 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
4171 pbn_b0_4_1843200_200 },
4172 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4173 PCI_SUBVENDOR_ID_CONNECT_TECH,
4174 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
4175 pbn_b0_8_1843200_200 },
4176 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4177 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
4178 0, 0, pbn_exar_ibm_saturn },
4179
4180 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4181 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4182 pbn_b2_bt_1_115200 },
4183 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4184 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4185 pbn_b2_bt_2_115200 },
4186 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4187 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4188 pbn_b2_bt_4_115200 },
4189 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4190 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4191 pbn_b2_bt_2_115200 },
4192 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4193 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4194 pbn_b2_bt_4_115200 },
4195 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4196 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4197 pbn_b2_8_115200 },
4198 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4199 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4200 pbn_b2_8_460800 },
4201 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4202 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4203 pbn_b2_8_115200 },
4204
4205 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4206 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4207 pbn_b2_bt_2_115200 },
4208 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4209 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4210 pbn_b2_bt_2_921600 },
4211 /*
4212 * VScom SPCOM800, from sl@s.pl
4213 */
4214 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4215 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4216 pbn_b2_8_921600 },
4217 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4218 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4219 pbn_b2_4_921600 },
4220 /* Unknown card - subdevice 0x1584 */
4221 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4222 PCI_VENDOR_ID_PLX,
4223 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4224 pbn_b2_4_115200 },
4225 /* Unknown card - subdevice 0x1588 */
4226 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4227 PCI_VENDOR_ID_PLX,
4228 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4229 pbn_b2_8_115200 },
4230 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4231 PCI_SUBVENDOR_ID_KEYSPAN,
4232 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4233 pbn_panacom },
4234 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4235 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4236 pbn_panacom4 },
4237 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4238 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4239 pbn_panacom2 },
4240 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4241 PCI_VENDOR_ID_ESDGMBH,
4242 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4243 pbn_b2_4_115200 },
4244 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4245 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4246 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4247 pbn_b2_4_460800 },
4248 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4249 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4250 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4251 pbn_b2_8_460800 },
4252 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4253 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4254 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4255 pbn_b2_16_460800 },
4256 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4257 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4258 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4259 pbn_b2_16_460800 },
4260 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4261 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4262 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4263 pbn_b2_4_460800 },
4264 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4265 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4266 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4267 pbn_b2_8_460800 },
4268 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4269 PCI_SUBVENDOR_ID_EXSYS,
4270 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4271 pbn_b2_4_115200 },
4272 /*
4273 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4274 * (Exoray@isys.ca)
4275 */
4276 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4277 0x10b5, 0x106a, 0, 0,
4278 pbn_plx_romulus },
4279 /*
4280 * EndRun Technologies. PCI express device range.
4281 * EndRun PTP/1588 has 2 Native UARTs.
4282 */
4283 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4284 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4285 pbn_endrun_2_4000000 },
4286 /*
4287 * Quatech cards. These actually have configurable clocks but for
4288 * now we just use the default.
4289 *
4290 * 100 series are RS232, 200 series RS422,
4291 */
4292 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4293 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4294 pbn_b1_4_115200 },
4295 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4296 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4297 pbn_b1_2_115200 },
4298 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4299 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4300 pbn_b2_2_115200 },
4301 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4302 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4303 pbn_b1_2_115200 },
4304 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4305 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4306 pbn_b2_2_115200 },
4307 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4308 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4309 pbn_b1_4_115200 },
4310 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4311 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4312 pbn_b1_8_115200 },
4313 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4314 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4315 pbn_b1_8_115200 },
4316 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4317 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4318 pbn_b1_4_115200 },
4319 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4320 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4321 pbn_b1_2_115200 },
4322 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4323 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4324 pbn_b1_4_115200 },
4325 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4326 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4327 pbn_b1_2_115200 },
4328 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4329 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4330 pbn_b2_4_115200 },
4331 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4332 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4333 pbn_b2_2_115200 },
4334 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4335 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4336 pbn_b2_1_115200 },
4337 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4338 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4339 pbn_b2_4_115200 },
4340 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4341 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4342 pbn_b2_2_115200 },
4343 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4344 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4345 pbn_b2_1_115200 },
4346 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4347 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4348 pbn_b0_8_115200 },
4349
4350 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4351 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4352 0, 0,
4353 pbn_b0_4_921600 },
4354 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4355 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4356 0, 0,
4357 pbn_b0_4_1152000 },
4358 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4359 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4360 pbn_b0_bt_2_921600 },
4361
4362 /*
4363 * The below card is a little controversial since it is the
4364 * subject of a PCI vendor/device ID clash. (See
4365 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4366 * For now just used the hex ID 0x950a.
4367 */
4368 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4369 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4370 0, 0, pbn_b0_2_115200 },
4371 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4372 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4373 0, 0, pbn_b0_2_115200 },
4374 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4375 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4376 pbn_b0_2_1130000 },
4377 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4378 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4379 pbn_b0_1_921600 },
4380 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4381 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4382 pbn_b0_4_115200 },
4383 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4384 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4385 pbn_b0_bt_2_921600 },
4386 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4387 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
4388 pbn_b2_8_1152000 },
4389
4390 /*
4391 * Oxford Semiconductor Inc. Tornado PCI express device range.
4392 */
4393 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4394 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4395 pbn_b0_1_4000000 },
4396 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4397 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4398 pbn_b0_1_4000000 },
4399 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4400 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4401 pbn_oxsemi_1_4000000 },
4402 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4403 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4404 pbn_oxsemi_1_4000000 },
4405 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4406 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4407 pbn_b0_1_4000000 },
4408 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4409 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4410 pbn_b0_1_4000000 },
4411 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4412 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4413 pbn_oxsemi_1_4000000 },
4414 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4415 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4416 pbn_oxsemi_1_4000000 },
4417 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4418 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4419 pbn_b0_1_4000000 },
4420 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4421 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4422 pbn_b0_1_4000000 },
4423 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4424 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4425 pbn_b0_1_4000000 },
4426 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4427 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4428 pbn_b0_1_4000000 },
4429 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4430 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4431 pbn_oxsemi_2_4000000 },
4432 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4433 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4434 pbn_oxsemi_2_4000000 },
4435 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4436 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4437 pbn_oxsemi_4_4000000 },
4438 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4439 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4440 pbn_oxsemi_4_4000000 },
4441 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4442 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4443 pbn_oxsemi_8_4000000 },
4444 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4445 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4446 pbn_oxsemi_8_4000000 },
4447 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4448 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4449 pbn_oxsemi_1_4000000 },
4450 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4451 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4452 pbn_oxsemi_1_4000000 },
4453 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4454 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4455 pbn_oxsemi_1_4000000 },
4456 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4457 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4458 pbn_oxsemi_1_4000000 },
4459 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4460 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4461 pbn_oxsemi_1_4000000 },
4462 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4463 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4464 pbn_oxsemi_1_4000000 },
4465 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4466 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4467 pbn_oxsemi_1_4000000 },
4468 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4469 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4470 pbn_oxsemi_1_4000000 },
4471 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4472 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4473 pbn_oxsemi_1_4000000 },
4474 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4475 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4476 pbn_oxsemi_1_4000000 },
4477 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4478 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4479 pbn_oxsemi_1_4000000 },
4480 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4481 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4482 pbn_oxsemi_1_4000000 },
4483 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4484 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4485 pbn_oxsemi_1_4000000 },
4486 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4487 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4488 pbn_oxsemi_1_4000000 },
4489 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4490 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4491 pbn_oxsemi_1_4000000 },
4492 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4493 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4494 pbn_oxsemi_1_4000000 },
4495 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4496 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4497 pbn_oxsemi_1_4000000 },
4498 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4499 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4500 pbn_oxsemi_1_4000000 },
4501 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4502 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4503 pbn_oxsemi_1_4000000 },
4504 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4505 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4506 pbn_oxsemi_1_4000000 },
4507 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4508 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4509 pbn_oxsemi_1_4000000 },
4510 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4511 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4512 pbn_oxsemi_1_4000000 },
4513 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4514 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4515 pbn_oxsemi_1_4000000 },
4516 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4517 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4518 pbn_oxsemi_1_4000000 },
4519 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4520 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4521 pbn_oxsemi_1_4000000 },
4522 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4523 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4524 pbn_oxsemi_1_4000000 },
4525 /*
4526 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4527 */
4528 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4529 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4530 pbn_oxsemi_1_4000000 },
4531 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4532 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4533 pbn_oxsemi_2_4000000 },
4534 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4535 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4536 pbn_oxsemi_4_4000000 },
4537 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4538 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4539 pbn_oxsemi_8_4000000 },
4540
4541 /*
4542 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4543 */
4544 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4545 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4546 pbn_oxsemi_2_4000000 },
4547
4548 /*
4549 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4550 * from skokodyn@yahoo.com
4551 */
4552 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4553 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4554 pbn_sbsxrsio },
4555 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4556 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4557 pbn_sbsxrsio },
4558 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4559 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4560 pbn_sbsxrsio },
4561 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4562 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4563 pbn_sbsxrsio },
4564
4565 /*
4566 * Digitan DS560-558, from jimd@esoft.com
4567 */
4568 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4569 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4570 pbn_b1_1_115200 },
4571
4572 /*
4573 * Titan Electronic cards
4574 * The 400L and 800L have a custom setup quirk.
4575 */
4576 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4577 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4578 pbn_b0_1_921600 },
4579 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4580 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4581 pbn_b0_2_921600 },
4582 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4583 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4584 pbn_b0_4_921600 },
4585 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4586 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4587 pbn_b0_4_921600 },
4588 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4589 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4590 pbn_b1_1_921600 },
4591 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4592 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4593 pbn_b1_bt_2_921600 },
4594 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4595 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4596 pbn_b0_bt_4_921600 },
4597 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4598 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4599 pbn_b0_bt_8_921600 },
4600 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4601 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4602 pbn_b4_bt_2_921600 },
4603 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4604 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4605 pbn_b4_bt_4_921600 },
4606 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4607 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4608 pbn_b4_bt_8_921600 },
4609 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4610 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4611 pbn_b0_4_921600 },
4612 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4613 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4614 pbn_b0_4_921600 },
4615 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4616 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4617 pbn_b0_4_921600 },
4618 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4619 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4620 pbn_oxsemi_1_4000000 },
4621 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4622 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4623 pbn_oxsemi_2_4000000 },
4624 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4625 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4626 pbn_oxsemi_4_4000000 },
4627 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4628 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4629 pbn_oxsemi_8_4000000 },
4630 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4631 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4632 pbn_oxsemi_2_4000000 },
4633 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4634 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4635 pbn_oxsemi_2_4000000 },
4636 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4637 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4638 pbn_b0_bt_2_921600 },
4639 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4640 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4641 pbn_b0_4_921600 },
4642 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4643 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4644 pbn_b0_4_921600 },
4645 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4646 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4647 pbn_b0_4_921600 },
4648 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4649 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4650 pbn_b0_4_921600 },
4651
4652 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4653 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4654 pbn_b2_1_460800 },
4655 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4656 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4657 pbn_b2_1_460800 },
4658 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4659 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4660 pbn_b2_1_460800 },
4661 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4662 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4663 pbn_b2_bt_2_921600 },
4664 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4665 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4666 pbn_b2_bt_2_921600 },
4667 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4668 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4669 pbn_b2_bt_2_921600 },
4670 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4671 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4672 pbn_b2_bt_4_921600 },
4673 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4674 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4675 pbn_b2_bt_4_921600 },
4676 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4677 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4678 pbn_b2_bt_4_921600 },
4679 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4680 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4681 pbn_b0_1_921600 },
4682 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4683 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4684 pbn_b0_1_921600 },
4685 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4686 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4687 pbn_b0_1_921600 },
4688 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4689 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4690 pbn_b0_bt_2_921600 },
4691 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4692 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4693 pbn_b0_bt_2_921600 },
4694 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4695 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4696 pbn_b0_bt_2_921600 },
4697 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4698 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4699 pbn_b0_bt_4_921600 },
4700 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4701 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4702 pbn_b0_bt_4_921600 },
4703 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4704 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4705 pbn_b0_bt_4_921600 },
4706 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4707 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4708 pbn_b0_bt_8_921600 },
4709 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4710 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4711 pbn_b0_bt_8_921600 },
4712 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4713 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4714 pbn_b0_bt_8_921600 },
4715
4716 /*
4717 * Computone devices submitted by Doug McNash dmcnash@computone.com
4718 */
4719 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4720 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4721 0, 0, pbn_computone_4 },
4722 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4723 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4724 0, 0, pbn_computone_8 },
4725 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4726 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4727 0, 0, pbn_computone_6 },
4728
4729 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4730 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4731 pbn_oxsemi },
4732 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4733 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4734 pbn_b0_bt_1_921600 },
4735
4736 /*
4737 * SUNIX (TIMEDIA)
4738 */
4739 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4740 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4741 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4742 pbn_b0_bt_1_921600 },
4743
4744 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4745 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4746 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4747 pbn_b0_bt_1_921600 },
4748
4749 /*
4750 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4751 */
4752 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4753 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4754 pbn_b0_bt_8_115200 },
4755 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4756 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4757 pbn_b0_bt_8_115200 },
4758
4759 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4760 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4761 pbn_b0_bt_2_115200 },
4762 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4763 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4764 pbn_b0_bt_2_115200 },
4765 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4766 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4767 pbn_b0_bt_2_115200 },
4768 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4769 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4770 pbn_b0_bt_2_115200 },
4771 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4772 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4773 pbn_b0_bt_2_115200 },
4774 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4775 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4776 pbn_b0_bt_4_460800 },
4777 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4778 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4779 pbn_b0_bt_4_460800 },
4780 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4781 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4782 pbn_b0_bt_2_460800 },
4783 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4784 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4785 pbn_b0_bt_2_460800 },
4786 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4787 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4788 pbn_b0_bt_2_460800 },
4789 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4790 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4791 pbn_b0_bt_1_115200 },
4792 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4793 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4794 pbn_b0_bt_1_460800 },
4795
4796 /*
4797 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4798 * Cards are identified by their subsystem vendor IDs, which
4799 * (in hex) match the model number.
4800 *
4801 * Note that JC140x are RS422/485 cards which require ox950
4802 * ACR = 0x10, and as such are not currently fully supported.
4803 */
4804 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4805 0x1204, 0x0004, 0, 0,
4806 pbn_b0_4_921600 },
4807 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4808 0x1208, 0x0004, 0, 0,
4809 pbn_b0_4_921600 },
4810 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4811 0x1402, 0x0002, 0, 0,
4812 pbn_b0_2_921600 }, */
4813 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4814 0x1404, 0x0004, 0, 0,
4815 pbn_b0_4_921600 }, */
4816 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4817 0x1208, 0x0004, 0, 0,
4818 pbn_b0_4_921600 },
4819
4820 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4821 0x1204, 0x0004, 0, 0,
4822 pbn_b0_4_921600 },
4823 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4824 0x1208, 0x0004, 0, 0,
4825 pbn_b0_4_921600 },
4826 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4827 0x1208, 0x0004, 0, 0,
4828 pbn_b0_4_921600 },
4829 /*
4830 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4831 */
4832 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4833 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4834 pbn_b1_1_1382400 },
4835
4836 /*
4837 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4838 */
4839 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4840 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4841 pbn_b1_1_1382400 },
4842
4843 /*
4844 * RAStel 2 port modem, gerg@moreton.com.au
4845 */
4846 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4847 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4848 pbn_b2_bt_2_115200 },
4849
4850 /*
4851 * EKF addition for i960 Boards form EKF with serial port
4852 */
4853 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4854 0xE4BF, PCI_ANY_ID, 0, 0,
4855 pbn_intel_i960 },
4856
4857 /*
4858 * Xircom Cardbus/Ethernet combos
4859 */
4860 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4861 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4862 pbn_b0_1_115200 },
4863 /*
4864 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4865 */
4866 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4867 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4868 pbn_b0_1_115200 },
4869
4870 /*
4871 * Untested PCI modems, sent in from various folks...
4872 */
4873
4874 /*
4875 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4876 */
4877 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4878 0x1048, 0x1500, 0, 0,
4879 pbn_b1_1_115200 },
4880
4881 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4882 0xFF00, 0, 0, 0,
4883 pbn_sgi_ioc3 },
4884
4885 /*
4886 * HP Diva card
4887 */
4888 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4889 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4890 pbn_b1_1_115200 },
4891 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4892 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4893 pbn_b0_5_115200 },
4894 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4895 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4896 pbn_b2_1_115200 },
4897
4898 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4899 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4900 pbn_b3_2_115200 },
4901 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4902 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4903 pbn_b3_4_115200 },
4904 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4905 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4906 pbn_b3_8_115200 },
4907
4908 /*
4909 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
4910 */
4911 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4912 PCI_ANY_ID, PCI_ANY_ID,
4913 0,
4914 0, pbn_exar_XR17C152 },
4915 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4916 PCI_ANY_ID, PCI_ANY_ID,
4917 0,
4918 0, pbn_exar_XR17C154 },
4919 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4920 PCI_ANY_ID, PCI_ANY_ID,
4921 0,
4922 0, pbn_exar_XR17C158 },
4923 /*
4924 * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs
4925 */
4926 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
4927 PCI_ANY_ID, PCI_ANY_ID,
4928 0,
4929 0, pbn_exar_XR17V352 },
4930 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
4931 PCI_ANY_ID, PCI_ANY_ID,
4932 0,
4933 0, pbn_exar_XR17V354 },
4934 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
4935 PCI_ANY_ID, PCI_ANY_ID,
4936 0,
4937 0, pbn_exar_XR17V358 },
4938
4939 /*
4940 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4941 */
4942 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4943 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4944 pbn_b0_1_115200 },
4945 /*
4946 * ITE
4947 */
4948 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4949 PCI_ANY_ID, PCI_ANY_ID,
4950 0, 0,
4951 pbn_b1_bt_1_115200 },
4952
4953 /*
4954 * IntaShield IS-200
4955 */
4956 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4957 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
4958 pbn_b2_2_115200 },
4959 /*
4960 * IntaShield IS-400
4961 */
4962 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4963 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
4964 pbn_b2_4_115200 },
4965 /*
4966 * Perle PCI-RAS cards
4967 */
4968 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4969 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4970 0, 0, pbn_b2_4_921600 },
4971 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4972 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4973 0, 0, pbn_b2_8_921600 },
4974
4975 /*
4976 * Mainpine series cards: Fairly standard layout but fools
4977 * parts of the autodetect in some cases and uses otherwise
4978 * unmatched communications subclasses in the PCI Express case
4979 */
4980
4981 { /* RockForceDUO */
4982 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4983 PCI_VENDOR_ID_MAINPINE, 0x0200,
4984 0, 0, pbn_b0_2_115200 },
4985 { /* RockForceQUATRO */
4986 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4987 PCI_VENDOR_ID_MAINPINE, 0x0300,
4988 0, 0, pbn_b0_4_115200 },
4989 { /* RockForceDUO+ */
4990 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4991 PCI_VENDOR_ID_MAINPINE, 0x0400,
4992 0, 0, pbn_b0_2_115200 },
4993 { /* RockForceQUATRO+ */
4994 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4995 PCI_VENDOR_ID_MAINPINE, 0x0500,
4996 0, 0, pbn_b0_4_115200 },
4997 { /* RockForce+ */
4998 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4999 PCI_VENDOR_ID_MAINPINE, 0x0600,
5000 0, 0, pbn_b0_2_115200 },
5001 { /* RockForce+ */
5002 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5003 PCI_VENDOR_ID_MAINPINE, 0x0700,
5004 0, 0, pbn_b0_4_115200 },
5005 { /* RockForceOCTO+ */
5006 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5007 PCI_VENDOR_ID_MAINPINE, 0x0800,
5008 0, 0, pbn_b0_8_115200 },
5009 { /* RockForceDUO+ */
5010 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5011 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5012 0, 0, pbn_b0_2_115200 },
5013 { /* RockForceQUARTRO+ */
5014 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5015 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5016 0, 0, pbn_b0_4_115200 },
5017 { /* RockForceOCTO+ */
5018 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5019 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5020 0, 0, pbn_b0_8_115200 },
5021 { /* RockForceD1 */
5022 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5023 PCI_VENDOR_ID_MAINPINE, 0x2000,
5024 0, 0, pbn_b0_1_115200 },
5025 { /* RockForceF1 */
5026 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5027 PCI_VENDOR_ID_MAINPINE, 0x2100,
5028 0, 0, pbn_b0_1_115200 },
5029 { /* RockForceD2 */
5030 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5031 PCI_VENDOR_ID_MAINPINE, 0x2200,
5032 0, 0, pbn_b0_2_115200 },
5033 { /* RockForceF2 */
5034 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5035 PCI_VENDOR_ID_MAINPINE, 0x2300,
5036 0, 0, pbn_b0_2_115200 },
5037 { /* RockForceD4 */
5038 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5039 PCI_VENDOR_ID_MAINPINE, 0x2400,
5040 0, 0, pbn_b0_4_115200 },
5041 { /* RockForceF4 */
5042 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5043 PCI_VENDOR_ID_MAINPINE, 0x2500,
5044 0, 0, pbn_b0_4_115200 },
5045 { /* RockForceD8 */
5046 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5047 PCI_VENDOR_ID_MAINPINE, 0x2600,
5048 0, 0, pbn_b0_8_115200 },
5049 { /* RockForceF8 */
5050 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5051 PCI_VENDOR_ID_MAINPINE, 0x2700,
5052 0, 0, pbn_b0_8_115200 },
5053 { /* IQ Express D1 */
5054 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5055 PCI_VENDOR_ID_MAINPINE, 0x3000,
5056 0, 0, pbn_b0_1_115200 },
5057 { /* IQ Express F1 */
5058 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5059 PCI_VENDOR_ID_MAINPINE, 0x3100,
5060 0, 0, pbn_b0_1_115200 },
5061 { /* IQ Express D2 */
5062 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5063 PCI_VENDOR_ID_MAINPINE, 0x3200,
5064 0, 0, pbn_b0_2_115200 },
5065 { /* IQ Express F2 */
5066 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5067 PCI_VENDOR_ID_MAINPINE, 0x3300,
5068 0, 0, pbn_b0_2_115200 },
5069 { /* IQ Express D4 */
5070 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5071 PCI_VENDOR_ID_MAINPINE, 0x3400,
5072 0, 0, pbn_b0_4_115200 },
5073 { /* IQ Express F4 */
5074 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5075 PCI_VENDOR_ID_MAINPINE, 0x3500,
5076 0, 0, pbn_b0_4_115200 },
5077 { /* IQ Express D8 */
5078 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5079 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5080 0, 0, pbn_b0_8_115200 },
5081 { /* IQ Express F8 */
5082 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5083 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5084 0, 0, pbn_b0_8_115200 },
5085
5086
5087 /*
5088 * PA Semi PA6T-1682M on-chip UART
5089 */
5090 { PCI_VENDOR_ID_PASEMI, 0xa004,
5091 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5092 pbn_pasemi_1682M },
5093
5094 /*
5095 * National Instruments
5096 */
5097 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5098 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5099 pbn_b1_16_115200 },
5100 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5101 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5102 pbn_b1_8_115200 },
5103 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5104 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5105 pbn_b1_bt_4_115200 },
5106 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5107 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5108 pbn_b1_bt_2_115200 },
5109 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5110 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5111 pbn_b1_bt_4_115200 },
5112 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5113 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5114 pbn_b1_bt_2_115200 },
5115 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5116 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5117 pbn_b1_16_115200 },
5118 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5119 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5120 pbn_b1_8_115200 },
5121 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5122 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5123 pbn_b1_bt_4_115200 },
5124 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5125 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5126 pbn_b1_bt_2_115200 },
5127 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5128 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5129 pbn_b1_bt_4_115200 },
5130 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5131 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5132 pbn_b1_bt_2_115200 },
5133 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5134 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5135 pbn_ni8430_2 },
5136 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5137 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5138 pbn_ni8430_2 },
5139 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5140 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5141 pbn_ni8430_4 },
5142 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5143 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5144 pbn_ni8430_4 },
5145 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5146 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5147 pbn_ni8430_8 },
5148 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5149 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5150 pbn_ni8430_8 },
5151 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5152 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5153 pbn_ni8430_16 },
5154 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5155 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5156 pbn_ni8430_16 },
5157 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5158 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5159 pbn_ni8430_2 },
5160 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5161 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5162 pbn_ni8430_2 },
5163 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5164 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5165 pbn_ni8430_4 },
5166 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5167 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5168 pbn_ni8430_4 },
5169
5170 /*
5171 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5172 */
5173 { PCI_VENDOR_ID_ADDIDATA,
5174 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5175 PCI_ANY_ID,
5176 PCI_ANY_ID,
5177 0,
5178 0,
5179 pbn_b0_4_115200 },
5180
5181 { PCI_VENDOR_ID_ADDIDATA,
5182 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5183 PCI_ANY_ID,
5184 PCI_ANY_ID,
5185 0,
5186 0,
5187 pbn_b0_2_115200 },
5188
5189 { PCI_VENDOR_ID_ADDIDATA,
5190 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5191 PCI_ANY_ID,
5192 PCI_ANY_ID,
5193 0,
5194 0,
5195 pbn_b0_1_115200 },
5196
5197 { PCI_VENDOR_ID_AMCC,
5198 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5199 PCI_ANY_ID,
5200 PCI_ANY_ID,
5201 0,
5202 0,
5203 pbn_b1_8_115200 },
5204
5205 { PCI_VENDOR_ID_ADDIDATA,
5206 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5207 PCI_ANY_ID,
5208 PCI_ANY_ID,
5209 0,
5210 0,
5211 pbn_b0_4_115200 },
5212
5213 { PCI_VENDOR_ID_ADDIDATA,
5214 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5215 PCI_ANY_ID,
5216 PCI_ANY_ID,
5217 0,
5218 0,
5219 pbn_b0_2_115200 },
5220
5221 { PCI_VENDOR_ID_ADDIDATA,
5222 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5223 PCI_ANY_ID,
5224 PCI_ANY_ID,
5225 0,
5226 0,
5227 pbn_b0_1_115200 },
5228
5229 { PCI_VENDOR_ID_ADDIDATA,
5230 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5231 PCI_ANY_ID,
5232 PCI_ANY_ID,
5233 0,
5234 0,
5235 pbn_b0_4_115200 },
5236
5237 { PCI_VENDOR_ID_ADDIDATA,
5238 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5239 PCI_ANY_ID,
5240 PCI_ANY_ID,
5241 0,
5242 0,
5243 pbn_b0_2_115200 },
5244
5245 { PCI_VENDOR_ID_ADDIDATA,
5246 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5247 PCI_ANY_ID,
5248 PCI_ANY_ID,
5249 0,
5250 0,
5251 pbn_b0_1_115200 },
5252
5253 { PCI_VENDOR_ID_ADDIDATA,
5254 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5255 PCI_ANY_ID,
5256 PCI_ANY_ID,
5257 0,
5258 0,
5259 pbn_b0_8_115200 },
5260
5261 { PCI_VENDOR_ID_ADDIDATA,
5262 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5263 PCI_ANY_ID,
5264 PCI_ANY_ID,
5265 0,
5266 0,
5267 pbn_ADDIDATA_PCIe_4_3906250 },
5268
5269 { PCI_VENDOR_ID_ADDIDATA,
5270 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5271 PCI_ANY_ID,
5272 PCI_ANY_ID,
5273 0,
5274 0,
5275 pbn_ADDIDATA_PCIe_2_3906250 },
5276
5277 { PCI_VENDOR_ID_ADDIDATA,
5278 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5279 PCI_ANY_ID,
5280 PCI_ANY_ID,
5281 0,
5282 0,
5283 pbn_ADDIDATA_PCIe_1_3906250 },
5284
5285 { PCI_VENDOR_ID_ADDIDATA,
5286 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5287 PCI_ANY_ID,
5288 PCI_ANY_ID,
5289 0,
5290 0,
5291 pbn_ADDIDATA_PCIe_8_3906250 },
5292
5293 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5294 PCI_VENDOR_ID_IBM, 0x0299,
5295 0, 0, pbn_b0_bt_2_115200 },
5296
5297 /*
5298 * other NetMos 9835 devices are most likely handled by the
5299 * parport_serial driver, check drivers/parport/parport_serial.c
5300 * before adding them here.
5301 */
5302
5303 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5304 0xA000, 0x1000,
5305 0, 0, pbn_b0_1_115200 },
5306
5307 /* the 9901 is a rebranded 9912 */
5308 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5309 0xA000, 0x1000,
5310 0, 0, pbn_b0_1_115200 },
5311
5312 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5313 0xA000, 0x1000,
5314 0, 0, pbn_b0_1_115200 },
5315
5316 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5317 0xA000, 0x1000,
5318 0, 0, pbn_b0_1_115200 },
5319
5320 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5321 0xA000, 0x1000,
5322 0, 0, pbn_b0_1_115200 },
5323
5324 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5325 0xA000, 0x3002,
5326 0, 0, pbn_NETMOS9900_2s_115200 },
5327
5328 /*
5329 * Best Connectivity and Rosewill PCI Multi I/O cards
5330 */
5331
5332 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5333 0xA000, 0x1000,
5334 0, 0, pbn_b0_1_115200 },
5335
5336 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5337 0xA000, 0x3002,
5338 0, 0, pbn_b0_bt_2_115200 },
5339
5340 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5341 0xA000, 0x3004,
5342 0, 0, pbn_b0_bt_4_115200 },
5343 /* Intel CE4100 */
5344 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5345 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5346 pbn_ce4100_1_115200 },
5347 /* Intel BayTrail */
5348 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART1,
5349 PCI_ANY_ID, PCI_ANY_ID,
5350 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5351 pbn_byt },
5352 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_UART2,
5353 PCI_ANY_ID, PCI_ANY_ID,
5354 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5355 pbn_byt },
5356 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART1,
5357 PCI_ANY_ID, PCI_ANY_ID,
5358 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5359 pbn_byt },
5360 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BSW_UART2,
5361 PCI_ANY_ID, PCI_ANY_ID,
5362 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xff0000,
5363 pbn_byt },
5364
5365 /*
5366 * Intel Quark x1000
5367 */
5368 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_UART,
5369 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5370 pbn_qrk },
5371 /*
5372 * Cronyx Omega PCI
5373 */
5374 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5375 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5376 pbn_omegapci },
5377
5378 /*
5379 * Broadcom TruManage
5380 */
5381 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5382 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5383 pbn_brcm_trumanage },
5384
5385 /*
5386 * AgeStar as-prs2-009
5387 */
5388 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5389 PCI_ANY_ID, PCI_ANY_ID,
5390 0, 0, pbn_b0_bt_2_115200 },
5391
5392 /*
5393 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5394 * so not listed here.
5395 */
5396 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5397 PCI_ANY_ID, PCI_ANY_ID,
5398 0, 0, pbn_b0_bt_4_115200 },
5399
5400 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5401 PCI_ANY_ID, PCI_ANY_ID,
5402 0, 0, pbn_b0_bt_2_115200 },
5403
5404 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5405 PCI_ANY_ID, PCI_ANY_ID,
5406 0, 0, pbn_wch384_4 },
5407
5408 /*
5409 * Commtech, Inc. Fastcom adapters
5410 */
5411 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
5412 PCI_ANY_ID, PCI_ANY_ID,
5413 0,
5414 0, pbn_b0_2_1152000_200 },
5415 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
5416 PCI_ANY_ID, PCI_ANY_ID,
5417 0,
5418 0, pbn_b0_4_1152000_200 },
5419 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
5420 PCI_ANY_ID, PCI_ANY_ID,
5421 0,
5422 0, pbn_b0_4_1152000_200 },
5423 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
5424 PCI_ANY_ID, PCI_ANY_ID,
5425 0,
5426 0, pbn_b0_8_1152000_200 },
5427 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
5428 PCI_ANY_ID, PCI_ANY_ID,
5429 0,
5430 0, pbn_exar_XR17V352 },
5431 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
5432 PCI_ANY_ID, PCI_ANY_ID,
5433 0,
5434 0, pbn_exar_XR17V354 },
5435 { PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
5436 PCI_ANY_ID, PCI_ANY_ID,
5437 0,
5438 0, pbn_exar_XR17V358 },
5439
5440 /* Fintek PCI serial cards */
5441 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5442 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5443 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5444
5445 /*
5446 * These entries match devices with class COMMUNICATION_SERIAL,
5447 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5448 */
5449 { PCI_ANY_ID, PCI_ANY_ID,
5450 PCI_ANY_ID, PCI_ANY_ID,
5451 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5452 0xffff00, pbn_default },
5453 { PCI_ANY_ID, PCI_ANY_ID,
5454 PCI_ANY_ID, PCI_ANY_ID,
5455 PCI_CLASS_COMMUNICATION_MODEM << 8,
5456 0xffff00, pbn_default },
5457 { PCI_ANY_ID, PCI_ANY_ID,
5458 PCI_ANY_ID, PCI_ANY_ID,
5459 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5460 0xffff00, pbn_default },
5461 { 0, }
5462 };
5463
5464 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5465 pci_channel_state_t state)
5466 {
5467 struct serial_private *priv = pci_get_drvdata(dev);
5468
5469 if (state == pci_channel_io_perm_failure)
5470 return PCI_ERS_RESULT_DISCONNECT;
5471
5472 if (priv)
5473 pciserial_suspend_ports(priv);
5474
5475 pci_disable_device(dev);
5476
5477 return PCI_ERS_RESULT_NEED_RESET;
5478 }
5479
5480 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5481 {
5482 int rc;
5483
5484 rc = pci_enable_device(dev);
5485
5486 if (rc)
5487 return PCI_ERS_RESULT_DISCONNECT;
5488
5489 pci_restore_state(dev);
5490 pci_save_state(dev);
5491
5492 return PCI_ERS_RESULT_RECOVERED;
5493 }
5494
5495 static void serial8250_io_resume(struct pci_dev *dev)
5496 {
5497 struct serial_private *priv = pci_get_drvdata(dev);
5498
5499 if (priv)
5500 pciserial_resume_ports(priv);
5501 }
5502
5503 static const struct pci_error_handlers serial8250_err_handler = {
5504 .error_detected = serial8250_io_error_detected,
5505 .slot_reset = serial8250_io_slot_reset,
5506 .resume = serial8250_io_resume,
5507 };
5508
5509 static struct pci_driver serial_pci_driver = {
5510 .name = "serial",
5511 .probe = pciserial_init_one,
5512 .remove = pciserial_remove_one,
5513 #ifdef CONFIG_PM
5514 .suspend = pciserial_suspend_one,
5515 .resume = pciserial_resume_one,
5516 #endif
5517 .id_table = serial_pci_tbl,
5518 .err_handler = &serial8250_err_handler,
5519 };
5520
5521 module_pci_driver(serial_pci_driver);
5522
5523 MODULE_LICENSE("GPL");
5524 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5525 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Linux kernel - Deliverables
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