drivers/tty/serial/8250/8250_uniphier.c

   1 /*
   2  * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/clk.h>
  16 #include <linux/io.h>
  17 #include <linux/module.h>
  18 #include <linux/of.h>
  19 #include <linux/platform_device.h>
  20
  21 #include "8250.h"
  22
  23 /* Most (but not all) of UniPhier UART devices have 64-depth FIFO. */
  24 #define UNIPHIER_UART_DEFAULT_FIFO_SIZE 64
  25
  26 #define UNIPHIER_UART_CHAR_FCR  3       /* Character / FIFO Control Register */
  27 #define UNIPHIER_UART_LCR_MCR   4       /* Line/Modem Control Register */
  28 #define   UNIPHIER_UART_LCR_SHIFT       8
  29 #define UNIPHIER_UART_DLR       9       /* Divisor Latch Register */
  30
  31 struct uniphier8250_priv {
  32         int line;
  33         struct clk *clk;
  34         spinlock_t atomic_write_lock;
  35 };
  36
  37 /*
  38  * The register map is slightly different from that of 8250.
  39  * IO callbacks must be overridden for correct access to FCR, LCR, and MCR.
  40  */
  41 static unsigned int uniphier_serial_in(struct uart_port *p, int offset)
  42 {
  43         unsigned int valshift = 0;
  44
  45         switch (offset) {
  46         case UART_LCR:
  47                 valshift = UNIPHIER_UART_LCR_SHIFT;
  48                 /* fall through */
  49         case UART_MCR:
  50                 offset = UNIPHIER_UART_LCR_MCR;
  51                 break;
  52         default:
  53                 break;
  54         }
  55
  56         offset <<= p->regshift;
  57
  58         /*
  59          * The return value must be masked with 0xff because LCR and MCR reside
  60          * in the same register that must be accessed by 32-bit write/read.
  61          * 8 or 16 bit access to this hardware result in unexpected behavior.
  62          */
  63         return (readl(p->membase + offset) >> valshift) & 0xff;
  64 }
  65
  66 static void uniphier_serial_out(struct uart_port *p, int offset, int value)
  67 {
  68         unsigned int valshift = 0;
  69         bool normal = false;
  70
  71         switch (offset) {
  72         case UART_FCR:
  73                 offset = UNIPHIER_UART_CHAR_FCR;
  74                 break;
  75         case UART_LCR:
  76                 valshift = UNIPHIER_UART_LCR_SHIFT;
  77                 /* Divisor latch access bit does not exist. */
  78                 value &= ~(UART_LCR_DLAB << valshift);
  79                 /* fall through */
  80         case UART_MCR:
  81                 offset = UNIPHIER_UART_LCR_MCR;
  82                 break;
  83         default:
  84                 normal = true;
  85                 break;
  86         }
  87
  88         offset <<= p->regshift;
  89
  90         if (normal) {
  91                 writel(value, p->membase + offset);
  92         } else {
  93                 /*
  94                  * Special case: two registers share the same address that
  95                  * must be 32-bit accessed.  As this is not longer atomic safe,
  96                  * take a lock just in case.
  97                  */
  98                 struct uniphier8250_priv *priv = p->private_data;
  99                 unsigned long flags;
 100                 u32 tmp;
 101
 102                 spin_lock_irqsave(&priv->atomic_write_lock, flags);
 103                 tmp = readl(p->membase + offset);
 104                 tmp &= ~(0xff << valshift);
 105                 tmp |= value << valshift;
 106                 writel(tmp, p->membase + offset);
 107                 spin_unlock_irqrestore(&priv->atomic_write_lock, flags);
 108         }
 109 }
 110
 111 /*
 112  * This hardware does not have the divisor latch access bit.
 113  * The divisor latch register exists at different address.
 114  * Override dl_read/write callbacks.
 115  */
 116 static int uniphier_serial_dl_read(struct uart_8250_port *up)
 117 {
 118         int offset = UNIPHIER_UART_DLR << up->port.regshift;
 119
 120         return readl(up->port.membase + offset);
 121 }
 122
 123 static void uniphier_serial_dl_write(struct uart_8250_port *up, int value)
 124 {
 125         int offset = UNIPHIER_UART_DLR << up->port.regshift;
 126
 127         writel(value, up->port.membase + offset);
 128 }
 129
 130 static int uniphier_of_serial_setup(struct device *dev, struct uart_port *port,
 131                                     struct uniphier8250_priv *priv)
 132 {
 133         int ret;
 134         u32 prop;
 135         struct device_node *np = dev->of_node;
 136
 137         ret = of_alias_get_id(np, "serial");
 138         if (ret < 0) {
 139                 dev_err(dev, "failed to get alias id\n");
 140                 return ret;
 141         }
 142         port->line = priv->line = ret;
 143
 144         /* Get clk rate through clk driver */
 145         priv->clk = devm_clk_get(dev, NULL);
 146         if (IS_ERR(priv->clk)) {
 147                 dev_err(dev, "failed to get clock\n");
 148                 return PTR_ERR(priv->clk);
 149         }
 150
 151         ret = clk_prepare_enable(priv->clk);
 152         if (ret < 0)
 153                 return ret;
 154
 155         port->uartclk = clk_get_rate(priv->clk);
 156
 157         /* Check for fifo size */
 158         if (of_property_read_u32(np, "fifo-size", &prop) == 0)
 159                 port->fifosize = prop;
 160         else
 161                 port->fifosize = UNIPHIER_UART_DEFAULT_FIFO_SIZE;
 162
 163         return 0;
 164 }
 165
 166 static int uniphier_uart_probe(struct platform_device *pdev)
 167 {
 168         struct device *dev = &pdev->dev;
 169         struct uart_8250_port up;
 170         struct uniphier8250_priv *priv;
 171         struct resource *regs;
 172         void __iomem *membase;
 173         int irq;
 174         int ret;
 175
 176         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 177         if (!regs) {
 178                 dev_err(dev, "failed to get memory resource");
 179                 return -EINVAL;
 180         }
 181
 182         membase = devm_ioremap(dev, regs->start, resource_size(regs));
 183         if (!membase)
 184                 return -ENOMEM;
 185
 186         irq = platform_get_irq(pdev, 0);
 187         if (irq < 0) {
 188                 dev_err(dev, "failed to get IRQ number");
 189                 return irq;
 190         }
 191
 192         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 193         if (!priv)
 194                 return -ENOMEM;
 195
 196         memset(&up, 0, sizeof(up));
 197
 198         ret = uniphier_of_serial_setup(dev, &up.port, priv);
 199         if (ret < 0)
 200                 return ret;
 201
 202         spin_lock_init(&priv->atomic_write_lock);
 203
 204         up.port.dev = dev;
 205         up.port.private_data = priv;
 206         up.port.mapbase = regs->start;
 207         up.port.mapsize = resource_size(regs);
 208         up.port.membase = membase;
 209         up.port.irq = irq;
 210
 211         up.port.type = PORT_16550A;
 212         up.port.iotype = UPIO_MEM32;
 213         up.port.regshift = 2;
 214         up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE;
 215         up.capabilities = UART_CAP_FIFO;
 216
 217         up.port.serial_in = uniphier_serial_in;
 218         up.port.serial_out = uniphier_serial_out;
 219         up.dl_read = uniphier_serial_dl_read;
 220         up.dl_write = uniphier_serial_dl_write;
 221
 222         ret = serial8250_register_8250_port(&up);
 223         if (ret < 0) {
 224                 dev_err(dev, "failed to register 8250 port\n");
 225                 clk_disable_unprepare(priv->clk);
 226                 return ret;
 227         }
 228
 229         platform_set_drvdata(pdev, priv);
 230
 231         return 0;
 232 }
 233
 234 static int uniphier_uart_remove(struct platform_device *pdev)
 235 {
 236         struct uniphier8250_priv *priv = platform_get_drvdata(pdev);
 237
 238         serial8250_unregister_port(priv->line);
 239         clk_disable_unprepare(priv->clk);
 240
 241         return 0;
 242 }
 243
 244 static const struct of_device_id uniphier_uart_match[] = {
 245         { .compatible = "socionext,uniphier-uart" },
 246         { /* sentinel */ }
 247 };
 248 MODULE_DEVICE_TABLE(of, uniphier_uart_match);
 249
 250 static struct platform_driver uniphier_uart_platform_driver = {
 251         .probe          = uniphier_uart_probe,
 252         .remove         = uniphier_uart_remove,
 253         .driver = {
 254                 .name   = "uniphier-uart",
 255                 .of_match_table = uniphier_uart_match,
 256         },
 257 };
 258 module_platform_driver(uniphier_uart_platform_driver);
 259
 260 MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
 261 MODULE_DESCRIPTION("UniPhier UART driver");
 262 MODULE_LICENSE("GPL");