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tty/serial: Prevent drop of DCD on suspend for Tegra UARTs
[deliverable/linux.git] / drivers / tty / serial / 8250.c
1 /*
2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * A note about mapbase / membase
14 *
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
17 */
18
19 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20 #define SUPPORT_SYSRQ
21 #endif
22
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/delay.h>
30 #include <linux/platform_device.h>
31 #include <linux/tty.h>
32 #include <linux/ratelimit.h>
33 #include <linux/tty_flip.h>
34 #include <linux/serial_reg.h>
35 #include <linux/serial_core.h>
36 #include <linux/serial.h>
37 #include <linux/serial_8250.h>
38 #include <linux/nmi.h>
39 #include <linux/mutex.h>
40 #include <linux/slab.h>
41
42 #include <asm/io.h>
43 #include <asm/irq.h>
44
45 #include "8250.h"
46
47 #ifdef CONFIG_SPARC
48 #include "suncore.h"
49 #endif
50
51 /*
52 * Configuration:
53 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
54 * is unsafe when used on edge-triggered interrupts.
55 */
56 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
57
58 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59
60 static struct uart_driver serial8250_reg;
61
62 static int serial_index(struct uart_port *port)
63 {
64 return (serial8250_reg.minor - 64) + port->line;
65 }
66
67 static unsigned int skip_txen_test; /* force skip of txen test at init time */
68
69 /*
70 * Debugging.
71 */
72 #if 0
73 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
74 #else
75 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
76 #endif
77
78 #if 0
79 #define DEBUG_INTR(fmt...) printk(fmt)
80 #else
81 #define DEBUG_INTR(fmt...) do { } while (0)
82 #endif
83
84 #define PASS_LIMIT 512
85
86 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
87
88
89 /*
90 * We default to IRQ0 for the "no irq" hack. Some
91 * machine types want others as well - they're free
92 * to redefine this in their header file.
93 */
94 #define is_real_interrupt(irq) ((irq) != 0)
95
96 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
97 #define CONFIG_SERIAL_DETECT_IRQ 1
98 #endif
99 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
100 #define CONFIG_SERIAL_MANY_PORTS 1
101 #endif
102
103 /*
104 * HUB6 is always on. This will be removed once the header
105 * files have been cleaned.
106 */
107 #define CONFIG_HUB6 1
108
109 #include <asm/serial.h>
110 /*
111 * SERIAL_PORT_DFNS tells us about built-in ports that have no
112 * standard enumeration mechanism. Platforms that can find all
113 * serial ports via mechanisms like ACPI or PCI need not supply it.
114 */
115 #ifndef SERIAL_PORT_DFNS
116 #define SERIAL_PORT_DFNS
117 #endif
118
119 static const struct old_serial_port old_serial_port[] = {
120 SERIAL_PORT_DFNS /* defined in asm/serial.h */
121 };
122
123 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
124
125 #ifdef CONFIG_SERIAL_8250_RSA
126
127 #define PORT_RSA_MAX 4
128 static unsigned long probe_rsa[PORT_RSA_MAX];
129 static unsigned int probe_rsa_count;
130 #endif /* CONFIG_SERIAL_8250_RSA */
131
132 struct uart_8250_port {
133 struct uart_port port;
134 struct timer_list timer; /* "no irq" timer */
135 struct list_head list; /* ports on this IRQ */
136 unsigned short capabilities; /* port capabilities */
137 unsigned short bugs; /* port bugs */
138 unsigned int tx_loadsz; /* transmit fifo load size */
139 unsigned char acr;
140 unsigned char ier;
141 unsigned char lcr;
142 unsigned char mcr;
143 unsigned char mcr_mask; /* mask of user bits */
144 unsigned char mcr_force; /* mask of forced bits */
145 unsigned char cur_iotype; /* Running I/O type */
146
147 /*
148 * Some bits in registers are cleared on a read, so they must
149 * be saved whenever the register is read but the bits will not
150 * be immediately processed.
151 */
152 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
153 unsigned char lsr_saved_flags;
154 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
155 unsigned char msr_saved_flags;
156 };
157
158 struct irq_info {
159 struct hlist_node node;
160 int irq;
161 spinlock_t lock; /* Protects list not the hash */
162 struct list_head *head;
163 };
164
165 #define NR_IRQ_HASH 32 /* Can be adjusted later */
166 static struct hlist_head irq_lists[NR_IRQ_HASH];
167 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
168
169 /*
170 * Here we define the default xmit fifo size used for each type of UART.
171 */
172 static const struct serial8250_config uart_config[] = {
173 [PORT_UNKNOWN] = {
174 .name = "unknown",
175 .fifo_size = 1,
176 .tx_loadsz = 1,
177 },
178 [PORT_8250] = {
179 .name = "8250",
180 .fifo_size = 1,
181 .tx_loadsz = 1,
182 },
183 [PORT_16450] = {
184 .name = "16450",
185 .fifo_size = 1,
186 .tx_loadsz = 1,
187 },
188 [PORT_16550] = {
189 .name = "16550",
190 .fifo_size = 1,
191 .tx_loadsz = 1,
192 },
193 [PORT_16550A] = {
194 .name = "16550A",
195 .fifo_size = 16,
196 .tx_loadsz = 16,
197 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
198 .flags = UART_CAP_FIFO,
199 },
200 [PORT_CIRRUS] = {
201 .name = "Cirrus",
202 .fifo_size = 1,
203 .tx_loadsz = 1,
204 },
205 [PORT_16650] = {
206 .name = "ST16650",
207 .fifo_size = 1,
208 .tx_loadsz = 1,
209 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
210 },
211 [PORT_16650V2] = {
212 .name = "ST16650V2",
213 .fifo_size = 32,
214 .tx_loadsz = 16,
215 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
216 UART_FCR_T_TRIG_00,
217 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
218 },
219 [PORT_16750] = {
220 .name = "TI16750",
221 .fifo_size = 64,
222 .tx_loadsz = 64,
223 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
224 UART_FCR7_64BYTE,
225 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
226 },
227 [PORT_STARTECH] = {
228 .name = "Startech",
229 .fifo_size = 1,
230 .tx_loadsz = 1,
231 },
232 [PORT_16C950] = {
233 .name = "16C950/954",
234 .fifo_size = 128,
235 .tx_loadsz = 128,
236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
237 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
238 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
239 },
240 [PORT_16654] = {
241 .name = "ST16654",
242 .fifo_size = 64,
243 .tx_loadsz = 32,
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
245 UART_FCR_T_TRIG_10,
246 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
247 },
248 [PORT_16850] = {
249 .name = "XR16850",
250 .fifo_size = 128,
251 .tx_loadsz = 128,
252 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
253 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
254 },
255 [PORT_RSA] = {
256 .name = "RSA",
257 .fifo_size = 2048,
258 .tx_loadsz = 2048,
259 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
260 .flags = UART_CAP_FIFO,
261 },
262 [PORT_NS16550A] = {
263 .name = "NS16550A",
264 .fifo_size = 16,
265 .tx_loadsz = 16,
266 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
267 .flags = UART_CAP_FIFO | UART_NATSEMI,
268 },
269 [PORT_XSCALE] = {
270 .name = "XScale",
271 .fifo_size = 32,
272 .tx_loadsz = 32,
273 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
274 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
275 },
276 [PORT_RM9000] = {
277 .name = "RM9000",
278 .fifo_size = 16,
279 .tx_loadsz = 16,
280 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
281 .flags = UART_CAP_FIFO,
282 },
283 [PORT_OCTEON] = {
284 .name = "OCTEON",
285 .fifo_size = 64,
286 .tx_loadsz = 64,
287 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
288 .flags = UART_CAP_FIFO,
289 },
290 [PORT_AR7] = {
291 .name = "AR7",
292 .fifo_size = 16,
293 .tx_loadsz = 16,
294 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
295 .flags = UART_CAP_FIFO | UART_CAP_AFE,
296 },
297 [PORT_U6_16550A] = {
298 .name = "U6_16550A",
299 .fifo_size = 64,
300 .tx_loadsz = 64,
301 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
302 .flags = UART_CAP_FIFO | UART_CAP_AFE,
303 },
304 [PORT_TEGRA] = {
305 .name = "Tegra",
306 .fifo_size = 32,
307 .tx_loadsz = 8,
308 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
309 UART_FCR_T_TRIG_01,
310 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
311 .mcr_mask = ~UART_MCR_DTR,
312 .mcr_force = UART_MCR_DTR,
313 },
314 [PORT_XR17D15X] = {
315 .name = "XR17D15X",
316 .fifo_size = 64,
317 .tx_loadsz = 64,
318 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
319 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
320 },
321 };
322
323 #if defined(CONFIG_MIPS_ALCHEMY)
324
325 /* Au1x00 UART hardware has a weird register layout */
326 static const u8 au_io_in_map[] = {
327 [UART_RX] = 0,
328 [UART_IER] = 2,
329 [UART_IIR] = 3,
330 [UART_LCR] = 5,
331 [UART_MCR] = 6,
332 [UART_LSR] = 7,
333 [UART_MSR] = 8,
334 };
335
336 static const u8 au_io_out_map[] = {
337 [UART_TX] = 1,
338 [UART_IER] = 2,
339 [UART_FCR] = 4,
340 [UART_LCR] = 5,
341 [UART_MCR] = 6,
342 };
343
344 /* sane hardware needs no mapping */
345 static inline int map_8250_in_reg(struct uart_port *p, int offset)
346 {
347 if (p->iotype != UPIO_AU)
348 return offset;
349 return au_io_in_map[offset];
350 }
351
352 static inline int map_8250_out_reg(struct uart_port *p, int offset)
353 {
354 if (p->iotype != UPIO_AU)
355 return offset;
356 return au_io_out_map[offset];
357 }
358
359 #elif defined(CONFIG_SERIAL_8250_RM9K)
360
361 static const u8
362 regmap_in[8] = {
363 [UART_RX] = 0x00,
364 [UART_IER] = 0x0c,
365 [UART_IIR] = 0x14,
366 [UART_LCR] = 0x1c,
367 [UART_MCR] = 0x20,
368 [UART_LSR] = 0x24,
369 [UART_MSR] = 0x28,
370 [UART_SCR] = 0x2c
371 },
372 regmap_out[8] = {
373 [UART_TX] = 0x04,
374 [UART_IER] = 0x0c,
375 [UART_FCR] = 0x18,
376 [UART_LCR] = 0x1c,
377 [UART_MCR] = 0x20,
378 [UART_LSR] = 0x24,
379 [UART_MSR] = 0x28,
380 [UART_SCR] = 0x2c
381 };
382
383 static inline int map_8250_in_reg(struct uart_port *p, int offset)
384 {
385 if (p->iotype != UPIO_RM9000)
386 return offset;
387 return regmap_in[offset];
388 }
389
390 static inline int map_8250_out_reg(struct uart_port *p, int offset)
391 {
392 if (p->iotype != UPIO_RM9000)
393 return offset;
394 return regmap_out[offset];
395 }
396
397 #else
398
399 /* sane hardware needs no mapping */
400 #define map_8250_in_reg(up, offset) (offset)
401 #define map_8250_out_reg(up, offset) (offset)
402
403 #endif
404
405 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
406 {
407 offset = map_8250_in_reg(p, offset) << p->regshift;
408 outb(p->hub6 - 1 + offset, p->iobase);
409 return inb(p->iobase + 1);
410 }
411
412 static void hub6_serial_out(struct uart_port *p, int offset, int value)
413 {
414 offset = map_8250_out_reg(p, offset) << p->regshift;
415 outb(p->hub6 - 1 + offset, p->iobase);
416 outb(value, p->iobase + 1);
417 }
418
419 static unsigned int mem_serial_in(struct uart_port *p, int offset)
420 {
421 offset = map_8250_in_reg(p, offset) << p->regshift;
422 return readb(p->membase + offset);
423 }
424
425 static void mem_serial_out(struct uart_port *p, int offset, int value)
426 {
427 offset = map_8250_out_reg(p, offset) << p->regshift;
428 writeb(value, p->membase + offset);
429 }
430
431 static void mem32_serial_out(struct uart_port *p, int offset, int value)
432 {
433 offset = map_8250_out_reg(p, offset) << p->regshift;
434 writel(value, p->membase + offset);
435 }
436
437 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
438 {
439 offset = map_8250_in_reg(p, offset) << p->regshift;
440 return readl(p->membase + offset);
441 }
442
443 static unsigned int au_serial_in(struct uart_port *p, int offset)
444 {
445 offset = map_8250_in_reg(p, offset) << p->regshift;
446 return __raw_readl(p->membase + offset);
447 }
448
449 static void au_serial_out(struct uart_port *p, int offset, int value)
450 {
451 offset = map_8250_out_reg(p, offset) << p->regshift;
452 __raw_writel(value, p->membase + offset);
453 }
454
455 static unsigned int io_serial_in(struct uart_port *p, int offset)
456 {
457 offset = map_8250_in_reg(p, offset) << p->regshift;
458 return inb(p->iobase + offset);
459 }
460
461 static void io_serial_out(struct uart_port *p, int offset, int value)
462 {
463 offset = map_8250_out_reg(p, offset) << p->regshift;
464 outb(value, p->iobase + offset);
465 }
466
467 static int serial8250_default_handle_irq(struct uart_port *port);
468
469 static void set_io_from_upio(struct uart_port *p)
470 {
471 struct uart_8250_port *up =
472 container_of(p, struct uart_8250_port, port);
473 switch (p->iotype) {
474 case UPIO_HUB6:
475 p->serial_in = hub6_serial_in;
476 p->serial_out = hub6_serial_out;
477 break;
478
479 case UPIO_MEM:
480 p->serial_in = mem_serial_in;
481 p->serial_out = mem_serial_out;
482 break;
483
484 case UPIO_RM9000:
485 case UPIO_MEM32:
486 p->serial_in = mem32_serial_in;
487 p->serial_out = mem32_serial_out;
488 break;
489
490 case UPIO_AU:
491 p->serial_in = au_serial_in;
492 p->serial_out = au_serial_out;
493 break;
494
495 default:
496 p->serial_in = io_serial_in;
497 p->serial_out = io_serial_out;
498 break;
499 }
500 /* Remember loaded iotype */
501 up->cur_iotype = p->iotype;
502 p->handle_irq = serial8250_default_handle_irq;
503 }
504
505 static void
506 serial_out_sync(struct uart_8250_port *up, int offset, int value)
507 {
508 struct uart_port *p = &up->port;
509 switch (p->iotype) {
510 case UPIO_MEM:
511 case UPIO_MEM32:
512 case UPIO_AU:
513 p->serial_out(p, offset, value);
514 p->serial_in(p, UART_LCR); /* safe, no side-effects */
515 break;
516 default:
517 p->serial_out(p, offset, value);
518 }
519 }
520
521 #define serial_in(up, offset) \
522 (up->port.serial_in(&(up)->port, (offset)))
523 #define serial_out(up, offset, value) \
524 (up->port.serial_out(&(up)->port, (offset), (value)))
525 /*
526 * We used to support using pause I/O for certain machines. We
527 * haven't supported this for a while, but just in case it's badly
528 * needed for certain old 386 machines, I've left these #define's
529 * in....
530 */
531 #define serial_inp(up, offset) serial_in(up, offset)
532 #define serial_outp(up, offset, value) serial_out(up, offset, value)
533
534 /* Uart divisor latch read */
535 static inline int _serial_dl_read(struct uart_8250_port *up)
536 {
537 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
538 }
539
540 /* Uart divisor latch write */
541 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
542 {
543 serial_outp(up, UART_DLL, value & 0xff);
544 serial_outp(up, UART_DLM, value >> 8 & 0xff);
545 }
546
547 #if defined(CONFIG_MIPS_ALCHEMY)
548 /* Au1x00 haven't got a standard divisor latch */
549 static int serial_dl_read(struct uart_8250_port *up)
550 {
551 if (up->port.iotype == UPIO_AU)
552 return __raw_readl(up->port.membase + 0x28);
553 else
554 return _serial_dl_read(up);
555 }
556
557 static void serial_dl_write(struct uart_8250_port *up, int value)
558 {
559 if (up->port.iotype == UPIO_AU)
560 __raw_writel(value, up->port.membase + 0x28);
561 else
562 _serial_dl_write(up, value);
563 }
564 #elif defined(CONFIG_SERIAL_8250_RM9K)
565 static int serial_dl_read(struct uart_8250_port *up)
566 {
567 return (up->port.iotype == UPIO_RM9000) ?
568 (((__raw_readl(up->port.membase + 0x10) << 8) |
569 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
570 _serial_dl_read(up);
571 }
572
573 static void serial_dl_write(struct uart_8250_port *up, int value)
574 {
575 if (up->port.iotype == UPIO_RM9000) {
576 __raw_writel(value, up->port.membase + 0x08);
577 __raw_writel(value >> 8, up->port.membase + 0x10);
578 } else {
579 _serial_dl_write(up, value);
580 }
581 }
582 #else
583 #define serial_dl_read(up) _serial_dl_read(up)
584 #define serial_dl_write(up, value) _serial_dl_write(up, value)
585 #endif
586
587 /*
588 * For the 16C950
589 */
590 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
591 {
592 serial_out(up, UART_SCR, offset);
593 serial_out(up, UART_ICR, value);
594 }
595
596 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
597 {
598 unsigned int value;
599
600 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
601 serial_out(up, UART_SCR, offset);
602 value = serial_in(up, UART_ICR);
603 serial_icr_write(up, UART_ACR, up->acr);
604
605 return value;
606 }
607
608 /*
609 * FIFO support.
610 */
611 static void serial8250_clear_fifos(struct uart_8250_port *p)
612 {
613 if (p->capabilities & UART_CAP_FIFO) {
614 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
615 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
616 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
617 serial_outp(p, UART_FCR, 0);
618 }
619 }
620
621 /*
622 * IER sleep support. UARTs which have EFRs need the "extended
623 * capability" bit enabled. Note that on XR16C850s, we need to
624 * reset LCR to write to IER.
625 */
626 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
627 {
628 if (p->capabilities & UART_CAP_SLEEP) {
629 if (p->capabilities & UART_CAP_EFR) {
630 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
631 serial_outp(p, UART_EFR, UART_EFR_ECB);
632 serial_outp(p, UART_LCR, 0);
633 }
634 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
635 if (p->capabilities & UART_CAP_EFR) {
636 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
637 serial_outp(p, UART_EFR, 0);
638 serial_outp(p, UART_LCR, 0);
639 }
640 }
641 }
642
643 #ifdef CONFIG_SERIAL_8250_RSA
644 /*
645 * Attempts to turn on the RSA FIFO. Returns zero on failure.
646 * We set the port uart clock rate if we succeed.
647 */
648 static int __enable_rsa(struct uart_8250_port *up)
649 {
650 unsigned char mode;
651 int result;
652
653 mode = serial_inp(up, UART_RSA_MSR);
654 result = mode & UART_RSA_MSR_FIFO;
655
656 if (!result) {
657 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
658 mode = serial_inp(up, UART_RSA_MSR);
659 result = mode & UART_RSA_MSR_FIFO;
660 }
661
662 if (result)
663 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
664
665 return result;
666 }
667
668 static void enable_rsa(struct uart_8250_port *up)
669 {
670 if (up->port.type == PORT_RSA) {
671 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
672 spin_lock_irq(&up->port.lock);
673 __enable_rsa(up);
674 spin_unlock_irq(&up->port.lock);
675 }
676 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
677 serial_outp(up, UART_RSA_FRR, 0);
678 }
679 }
680
681 /*
682 * Attempts to turn off the RSA FIFO. Returns zero on failure.
683 * It is unknown why interrupts were disabled in here. However,
684 * the caller is expected to preserve this behaviour by grabbing
685 * the spinlock before calling this function.
686 */
687 static void disable_rsa(struct uart_8250_port *up)
688 {
689 unsigned char mode;
690 int result;
691
692 if (up->port.type == PORT_RSA &&
693 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
694 spin_lock_irq(&up->port.lock);
695
696 mode = serial_inp(up, UART_RSA_MSR);
697 result = !(mode & UART_RSA_MSR_FIFO);
698
699 if (!result) {
700 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
701 mode = serial_inp(up, UART_RSA_MSR);
702 result = !(mode & UART_RSA_MSR_FIFO);
703 }
704
705 if (result)
706 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
707 spin_unlock_irq(&up->port.lock);
708 }
709 }
710 #endif /* CONFIG_SERIAL_8250_RSA */
711
712 /*
713 * This is a quickie test to see how big the FIFO is.
714 * It doesn't work at all the time, more's the pity.
715 */
716 static int size_fifo(struct uart_8250_port *up)
717 {
718 unsigned char old_fcr, old_mcr, old_lcr;
719 unsigned short old_dl;
720 int count;
721
722 old_lcr = serial_inp(up, UART_LCR);
723 serial_outp(up, UART_LCR, 0);
724 old_fcr = serial_inp(up, UART_FCR);
725 old_mcr = serial_inp(up, UART_MCR);
726 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
727 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
728 serial_outp(up, UART_MCR, UART_MCR_LOOP);
729 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
730 old_dl = serial_dl_read(up);
731 serial_dl_write(up, 0x0001);
732 serial_outp(up, UART_LCR, 0x03);
733 for (count = 0; count < 256; count++)
734 serial_outp(up, UART_TX, count);
735 mdelay(20);/* FIXME - schedule_timeout */
736 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
737 (count < 256); count++)
738 serial_inp(up, UART_RX);
739 serial_outp(up, UART_FCR, old_fcr);
740 serial_outp(up, UART_MCR, old_mcr);
741 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
742 serial_dl_write(up, old_dl);
743 serial_outp(up, UART_LCR, old_lcr);
744
745 return count;
746 }
747
748 /*
749 * Read UART ID using the divisor method - set DLL and DLM to zero
750 * and the revision will be in DLL and device type in DLM. We
751 * preserve the device state across this.
752 */
753 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
754 {
755 unsigned char old_dll, old_dlm, old_lcr;
756 unsigned int id;
757
758 old_lcr = serial_inp(p, UART_LCR);
759 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_A);
760
761 old_dll = serial_inp(p, UART_DLL);
762 old_dlm = serial_inp(p, UART_DLM);
763
764 serial_outp(p, UART_DLL, 0);
765 serial_outp(p, UART_DLM, 0);
766
767 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
768
769 serial_outp(p, UART_DLL, old_dll);
770 serial_outp(p, UART_DLM, old_dlm);
771 serial_outp(p, UART_LCR, old_lcr);
772
773 return id;
774 }
775
776 /*
777 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
778 * When this function is called we know it is at least a StarTech
779 * 16650 V2, but it might be one of several StarTech UARTs, or one of
780 * its clones. (We treat the broken original StarTech 16650 V1 as a
781 * 16550, and why not? Startech doesn't seem to even acknowledge its
782 * existence.)
783 *
784 * What evil have men's minds wrought...
785 */
786 static void autoconfig_has_efr(struct uart_8250_port *up)
787 {
788 unsigned int id1, id2, id3, rev;
789
790 /*
791 * Everything with an EFR has SLEEP
792 */
793 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
794
795 /*
796 * First we check to see if it's an Oxford Semiconductor UART.
797 *
798 * If we have to do this here because some non-National
799 * Semiconductor clone chips lock up if you try writing to the
800 * LSR register (which serial_icr_read does)
801 */
802
803 /*
804 * Check for Oxford Semiconductor 16C950.
805 *
806 * EFR [4] must be set else this test fails.
807 *
808 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
809 * claims that it's needed for 952 dual UART's (which are not
810 * recommended for new designs).
811 */
812 up->acr = 0;
813 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
814 serial_out(up, UART_EFR, UART_EFR_ECB);
815 serial_out(up, UART_LCR, 0x00);
816 id1 = serial_icr_read(up, UART_ID1);
817 id2 = serial_icr_read(up, UART_ID2);
818 id3 = serial_icr_read(up, UART_ID3);
819 rev = serial_icr_read(up, UART_REV);
820
821 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
822
823 if (id1 == 0x16 && id2 == 0xC9 &&
824 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
825 up->port.type = PORT_16C950;
826
827 /*
828 * Enable work around for the Oxford Semiconductor 952 rev B
829 * chip which causes it to seriously miscalculate baud rates
830 * when DLL is 0.
831 */
832 if (id3 == 0x52 && rev == 0x01)
833 up->bugs |= UART_BUG_QUOT;
834 return;
835 }
836
837 /*
838 * We check for a XR16C850 by setting DLL and DLM to 0, and then
839 * reading back DLL and DLM. The chip type depends on the DLM
840 * value read back:
841 * 0x10 - XR16C850 and the DLL contains the chip revision.
842 * 0x12 - XR16C2850.
843 * 0x14 - XR16C854.
844 */
845 id1 = autoconfig_read_divisor_id(up);
846 DEBUG_AUTOCONF("850id=%04x ", id1);
847
848 id2 = id1 >> 8;
849 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
850 up->port.type = PORT_16850;
851 return;
852 }
853
854 /*
855 * It wasn't an XR16C850.
856 *
857 * We distinguish between the '654 and the '650 by counting
858 * how many bytes are in the FIFO. I'm using this for now,
859 * since that's the technique that was sent to me in the
860 * serial driver update, but I'm not convinced this works.
861 * I've had problems doing this in the past. -TYT
862 */
863 if (size_fifo(up) == 64)
864 up->port.type = PORT_16654;
865 else
866 up->port.type = PORT_16650V2;
867 }
868
869 /*
870 * We detected a chip without a FIFO. Only two fall into
871 * this category - the original 8250 and the 16450. The
872 * 16450 has a scratch register (accessible with LCR=0)
873 */
874 static void autoconfig_8250(struct uart_8250_port *up)
875 {
876 unsigned char scratch, status1, status2;
877
878 up->port.type = PORT_8250;
879
880 scratch = serial_in(up, UART_SCR);
881 serial_outp(up, UART_SCR, 0xa5);
882 status1 = serial_in(up, UART_SCR);
883 serial_outp(up, UART_SCR, 0x5a);
884 status2 = serial_in(up, UART_SCR);
885 serial_outp(up, UART_SCR, scratch);
886
887 if (status1 == 0xa5 && status2 == 0x5a)
888 up->port.type = PORT_16450;
889 }
890
891 static int broken_efr(struct uart_8250_port *up)
892 {
893 /*
894 * Exar ST16C2550 "A2" devices incorrectly detect as
895 * having an EFR, and report an ID of 0x0201. See
896 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
897 */
898 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
899 return 1;
900
901 return 0;
902 }
903
904 static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
905 {
906 unsigned char status;
907
908 status = serial_in(up, 0x04); /* EXCR2 */
909 #define PRESL(x) ((x) & 0x30)
910 if (PRESL(status) == 0x10) {
911 /* already in high speed mode */
912 return 0;
913 } else {
914 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
915 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
916 serial_outp(up, 0x04, status);
917 }
918 return 1;
919 }
920
921 /*
922 * We know that the chip has FIFOs. Does it have an EFR? The
923 * EFR is located in the same register position as the IIR and
924 * we know the top two bits of the IIR are currently set. The
925 * EFR should contain zero. Try to read the EFR.
926 */
927 static void autoconfig_16550a(struct uart_8250_port *up)
928 {
929 unsigned char status1, status2;
930 unsigned int iersave;
931
932 up->port.type = PORT_16550A;
933 up->capabilities |= UART_CAP_FIFO;
934
935 /*
936 * Check for presence of the EFR when DLAB is set.
937 * Only ST16C650V1 UARTs pass this test.
938 */
939 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
940 if (serial_in(up, UART_EFR) == 0) {
941 serial_outp(up, UART_EFR, 0xA8);
942 if (serial_in(up, UART_EFR) != 0) {
943 DEBUG_AUTOCONF("EFRv1 ");
944 up->port.type = PORT_16650;
945 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
946 } else {
947 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
948 }
949 serial_outp(up, UART_EFR, 0);
950 return;
951 }
952
953 /*
954 * Maybe it requires 0xbf to be written to the LCR.
955 * (other ST16C650V2 UARTs, TI16C752A, etc)
956 */
957 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
958 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
959 DEBUG_AUTOCONF("EFRv2 ");
960 autoconfig_has_efr(up);
961 return;
962 }
963
964 /*
965 * Check for a National Semiconductor SuperIO chip.
966 * Attempt to switch to bank 2, read the value of the LOOP bit
967 * from EXCR1. Switch back to bank 0, change it in MCR. Then
968 * switch back to bank 2, read it from EXCR1 again and check
969 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
970 */
971 serial_outp(up, UART_LCR, 0);
972 status1 = serial_in(up, UART_MCR);
973 serial_outp(up, UART_LCR, 0xE0);
974 status2 = serial_in(up, 0x02); /* EXCR1 */
975
976 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
977 serial_outp(up, UART_LCR, 0);
978 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
979 serial_outp(up, UART_LCR, 0xE0);
980 status2 = serial_in(up, 0x02); /* EXCR1 */
981 serial_outp(up, UART_LCR, 0);
982 serial_outp(up, UART_MCR, status1);
983
984 if ((status2 ^ status1) & UART_MCR_LOOP) {
985 unsigned short quot;
986
987 serial_outp(up, UART_LCR, 0xE0);
988
989 quot = serial_dl_read(up);
990 quot <<= 3;
991
992 if (ns16550a_goto_highspeed(up))
993 serial_dl_write(up, quot);
994
995 serial_outp(up, UART_LCR, 0);
996
997 up->port.uartclk = 921600*16;
998 up->port.type = PORT_NS16550A;
999 up->capabilities |= UART_NATSEMI;
1000 return;
1001 }
1002 }
1003
1004 /*
1005 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1006 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1007 * Try setting it with and without DLAB set. Cheap clones
1008 * set bit 5 without DLAB set.
1009 */
1010 serial_outp(up, UART_LCR, 0);
1011 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1012 status1 = serial_in(up, UART_IIR) >> 5;
1013 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1014 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
1015 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1016 status2 = serial_in(up, UART_IIR) >> 5;
1017 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1018 serial_outp(up, UART_LCR, 0);
1019
1020 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1021
1022 if (status1 == 6 && status2 == 7) {
1023 up->port.type = PORT_16750;
1024 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1025 return;
1026 }
1027
1028 /*
1029 * Try writing and reading the UART_IER_UUE bit (b6).
1030 * If it works, this is probably one of the Xscale platform's
1031 * internal UARTs.
1032 * We're going to explicitly set the UUE bit to 0 before
1033 * trying to write and read a 1 just to make sure it's not
1034 * already a 1 and maybe locked there before we even start start.
1035 */
1036 iersave = serial_in(up, UART_IER);
1037 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1038 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1039 /*
1040 * OK it's in a known zero state, try writing and reading
1041 * without disturbing the current state of the other bits.
1042 */
1043 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1044 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1045 /*
1046 * It's an Xscale.
1047 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1048 */
1049 DEBUG_AUTOCONF("Xscale ");
1050 up->port.type = PORT_XSCALE;
1051 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1052 return;
1053 }
1054 } else {
1055 /*
1056 * If we got here we couldn't force the IER_UUE bit to 0.
1057 * Log it and continue.
1058 */
1059 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1060 }
1061 serial_outp(up, UART_IER, iersave);
1062
1063 /*
1064 * Exar uarts have EFR in a weird location
1065 */
1066 if (up->port.flags & UPF_EXAR_EFR) {
1067 up->port.type = PORT_XR17D15X;
1068 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR;
1069 }
1070
1071 /*
1072 * We distinguish between 16550A and U6 16550A by counting
1073 * how many bytes are in the FIFO.
1074 */
1075 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1076 up->port.type = PORT_U6_16550A;
1077 up->capabilities |= UART_CAP_AFE;
1078 }
1079 }
1080
1081 /*
1082 * This routine is called by rs_init() to initialize a specific serial
1083 * port. It determines what type of UART chip this serial port is
1084 * using: 8250, 16450, 16550, 16550A. The important question is
1085 * whether or not this UART is a 16550A or not, since this will
1086 * determine whether or not we can use its FIFO features or not.
1087 */
1088 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1089 {
1090 unsigned char status1, scratch, scratch2, scratch3;
1091 unsigned char save_lcr, save_mcr;
1092 unsigned long flags;
1093
1094 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1095 return;
1096
1097 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1098 serial_index(&up->port), up->port.iobase, up->port.membase);
1099
1100 /*
1101 * We really do need global IRQs disabled here - we're going to
1102 * be frobbing the chips IRQ enable register to see if it exists.
1103 */
1104 spin_lock_irqsave(&up->port.lock, flags);
1105
1106 up->capabilities = 0;
1107 up->bugs = 0;
1108
1109 if (!(up->port.flags & UPF_BUGGY_UART)) {
1110 /*
1111 * Do a simple existence test first; if we fail this,
1112 * there's no point trying anything else.
1113 *
1114 * 0x80 is used as a nonsense port to prevent against
1115 * false positives due to ISA bus float. The
1116 * assumption is that 0x80 is a non-existent port;
1117 * which should be safe since include/asm/io.h also
1118 * makes this assumption.
1119 *
1120 * Note: this is safe as long as MCR bit 4 is clear
1121 * and the device is in "PC" mode.
1122 */
1123 scratch = serial_inp(up, UART_IER);
1124 serial_outp(up, UART_IER, 0);
1125 #ifdef __i386__
1126 outb(0xff, 0x080);
1127 #endif
1128 /*
1129 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1130 * 16C754B) allow only to modify them if an EFR bit is set.
1131 */
1132 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1133 serial_outp(up, UART_IER, 0x0F);
1134 #ifdef __i386__
1135 outb(0, 0x080);
1136 #endif
1137 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1138 serial_outp(up, UART_IER, scratch);
1139 if (scratch2 != 0 || scratch3 != 0x0F) {
1140 /*
1141 * We failed; there's nothing here
1142 */
1143 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1144 scratch2, scratch3);
1145 goto out;
1146 }
1147 }
1148
1149 save_mcr = serial_in(up, UART_MCR);
1150 save_lcr = serial_in(up, UART_LCR);
1151
1152 /*
1153 * Check to see if a UART is really there. Certain broken
1154 * internal modems based on the Rockwell chipset fail this
1155 * test, because they apparently don't implement the loopback
1156 * test mode. So this test is skipped on the COM 1 through
1157 * COM 4 ports. This *should* be safe, since no board
1158 * manufacturer would be stupid enough to design a board
1159 * that conflicts with COM 1-4 --- we hope!
1160 */
1161 if (!(up->port.flags & UPF_SKIP_TEST)) {
1162 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1163 status1 = serial_inp(up, UART_MSR) & 0xF0;
1164 serial_outp(up, UART_MCR, save_mcr);
1165 if (status1 != 0x90) {
1166 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1167 status1);
1168 goto out;
1169 }
1170 }
1171
1172 /*
1173 * We're pretty sure there's a port here. Lets find out what
1174 * type of port it is. The IIR top two bits allows us to find
1175 * out if it's 8250 or 16450, 16550, 16550A or later. This
1176 * determines what we test for next.
1177 *
1178 * We also initialise the EFR (if any) to zero for later. The
1179 * EFR occupies the same register location as the FCR and IIR.
1180 */
1181 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1182 serial_outp(up, UART_EFR, 0);
1183 serial_outp(up, UART_LCR, 0);
1184
1185 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1186 scratch = serial_in(up, UART_IIR) >> 6;
1187
1188 DEBUG_AUTOCONF("iir=%d ", scratch);
1189
1190 switch (scratch) {
1191 case 0:
1192 autoconfig_8250(up);
1193 break;
1194 case 1:
1195 up->port.type = PORT_UNKNOWN;
1196 break;
1197 case 2:
1198 up->port.type = PORT_16550;
1199 break;
1200 case 3:
1201 autoconfig_16550a(up);
1202 break;
1203 }
1204
1205 #ifdef CONFIG_SERIAL_8250_RSA
1206 /*
1207 * Only probe for RSA ports if we got the region.
1208 */
1209 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1210 int i;
1211
1212 for (i = 0 ; i < probe_rsa_count; ++i) {
1213 if (probe_rsa[i] == up->port.iobase &&
1214 __enable_rsa(up)) {
1215 up->port.type = PORT_RSA;
1216 break;
1217 }
1218 }
1219 }
1220 #endif
1221
1222 serial_outp(up, UART_LCR, save_lcr);
1223
1224 if (up->capabilities != uart_config[up->port.type].flags) {
1225 printk(KERN_WARNING
1226 "ttyS%d: detected caps %08x should be %08x\n",
1227 serial_index(&up->port), up->capabilities,
1228 uart_config[up->port.type].flags);
1229 }
1230
1231 up->port.fifosize = uart_config[up->port.type].fifo_size;
1232 up->capabilities = uart_config[up->port.type].flags;
1233 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1234 if (!ALPHA_KLUDGE_MCR) {
1235 up->mcr_mask = uart_config[up->port.type].mcr_mask;
1236 up->mcr_force = uart_config[up->port.type].mcr_force;
1237 }
1238
1239 if (up->port.type == PORT_UNKNOWN)
1240 goto out;
1241
1242 /*
1243 * Reset the UART.
1244 */
1245 #ifdef CONFIG_SERIAL_8250_RSA
1246 if (up->port.type == PORT_RSA)
1247 serial_outp(up, UART_RSA_FRR, 0);
1248 #endif
1249 serial_outp(up, UART_MCR, save_mcr);
1250 serial8250_clear_fifos(up);
1251 serial_in(up, UART_RX);
1252 if (up->capabilities & UART_CAP_UUE)
1253 serial_outp(up, UART_IER, UART_IER_UUE);
1254 else
1255 serial_outp(up, UART_IER, 0);
1256
1257 out:
1258 spin_unlock_irqrestore(&up->port.lock, flags);
1259 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1260 }
1261
1262 static void autoconfig_irq(struct uart_8250_port *up)
1263 {
1264 unsigned char save_mcr, save_ier;
1265 unsigned char save_ICP = 0;
1266 unsigned int ICP = 0;
1267 unsigned long irqs;
1268 int irq;
1269
1270 if (up->port.flags & UPF_FOURPORT) {
1271 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1272 save_ICP = inb_p(ICP);
1273 outb_p(0x80, ICP);
1274 (void) inb_p(ICP);
1275 }
1276
1277 /* forget possible initially masked and pending IRQ */
1278 probe_irq_off(probe_irq_on());
1279 save_mcr = serial_inp(up, UART_MCR);
1280 save_ier = serial_inp(up, UART_IER);
1281 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1282
1283 irqs = probe_irq_on();
1284 serial_outp(up, UART_MCR, 0);
1285 udelay(10);
1286 if (up->port.flags & UPF_FOURPORT) {
1287 serial_outp(up, UART_MCR,
1288 UART_MCR_DTR | UART_MCR_RTS);
1289 } else {
1290 serial_outp(up, UART_MCR,
1291 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1292 }
1293 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1294 (void)serial_inp(up, UART_LSR);
1295 (void)serial_inp(up, UART_RX);
1296 (void)serial_inp(up, UART_IIR);
1297 (void)serial_inp(up, UART_MSR);
1298 serial_outp(up, UART_TX, 0xFF);
1299 udelay(20);
1300 irq = probe_irq_off(irqs);
1301
1302 serial_outp(up, UART_MCR, save_mcr);
1303 serial_outp(up, UART_IER, save_ier);
1304
1305 if (up->port.flags & UPF_FOURPORT)
1306 outb_p(save_ICP, ICP);
1307
1308 up->port.irq = (irq > 0) ? irq : 0;
1309 }
1310
1311 static inline void __stop_tx(struct uart_8250_port *p)
1312 {
1313 if (p->ier & UART_IER_THRI) {
1314 p->ier &= ~UART_IER_THRI;
1315 serial_out(p, UART_IER, p->ier);
1316 }
1317 }
1318
1319 static void serial8250_stop_tx(struct uart_port *port)
1320 {
1321 struct uart_8250_port *up =
1322 container_of(port, struct uart_8250_port, port);
1323
1324 __stop_tx(up);
1325
1326 /*
1327 * We really want to stop the transmitter from sending.
1328 */
1329 if (up->port.type == PORT_16C950) {
1330 up->acr |= UART_ACR_TXDIS;
1331 serial_icr_write(up, UART_ACR, up->acr);
1332 }
1333 }
1334
1335 static void transmit_chars(struct uart_8250_port *up);
1336
1337 static void serial8250_start_tx(struct uart_port *port)
1338 {
1339 struct uart_8250_port *up =
1340 container_of(port, struct uart_8250_port, port);
1341
1342 if (!(up->ier & UART_IER_THRI)) {
1343 up->ier |= UART_IER_THRI;
1344 serial_out(up, UART_IER, up->ier);
1345
1346 if (up->bugs & UART_BUG_TXEN) {
1347 unsigned char lsr;
1348 lsr = serial_in(up, UART_LSR);
1349 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1350 if ((up->port.type == PORT_RM9000) ?
1351 (lsr & UART_LSR_THRE) :
1352 (lsr & UART_LSR_TEMT))
1353 transmit_chars(up);
1354 }
1355 }
1356
1357 /*
1358 * Re-enable the transmitter if we disabled it.
1359 */
1360 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1361 up->acr &= ~UART_ACR_TXDIS;
1362 serial_icr_write(up, UART_ACR, up->acr);
1363 }
1364 }
1365
1366 static void serial8250_stop_rx(struct uart_port *port)
1367 {
1368 struct uart_8250_port *up =
1369 container_of(port, struct uart_8250_port, port);
1370
1371 up->ier &= ~UART_IER_RLSI;
1372 up->port.read_status_mask &= ~UART_LSR_DR;
1373 serial_out(up, UART_IER, up->ier);
1374 }
1375
1376 static void serial8250_enable_ms(struct uart_port *port)
1377 {
1378 struct uart_8250_port *up =
1379 container_of(port, struct uart_8250_port, port);
1380
1381 /* no MSR capabilities */
1382 if (up->bugs & UART_BUG_NOMSR)
1383 return;
1384
1385 up->ier |= UART_IER_MSI;
1386 serial_out(up, UART_IER, up->ier);
1387 }
1388
1389 /*
1390 * Clear the Tegra rx fifo after a break
1391 *
1392 * FIXME: This needs to become a port specific callback once we have a
1393 * framework for this
1394 */
1395 static void clear_rx_fifo(struct uart_8250_port *up)
1396 {
1397 unsigned int status, tmout = 10000;
1398 do {
1399 status = serial_in(up, UART_LSR);
1400 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
1401 status = serial_in(up, UART_RX);
1402 else
1403 break;
1404 if (--tmout == 0)
1405 break;
1406 udelay(1);
1407 } while (1);
1408 }
1409
1410 static void
1411 receive_chars(struct uart_8250_port *up, unsigned int *status)
1412 {
1413 struct tty_struct *tty = up->port.state->port.tty;
1414 unsigned char ch, lsr = *status;
1415 int max_count = 256;
1416 char flag;
1417
1418 do {
1419 if (likely(lsr & UART_LSR_DR))
1420 ch = serial_inp(up, UART_RX);
1421 else
1422 /*
1423 * Intel 82571 has a Serial Over Lan device that will
1424 * set UART_LSR_BI without setting UART_LSR_DR when
1425 * it receives a break. To avoid reading from the
1426 * receive buffer without UART_LSR_DR bit set, we
1427 * just force the read character to be 0
1428 */
1429 ch = 0;
1430
1431 flag = TTY_NORMAL;
1432 up->port.icount.rx++;
1433
1434 lsr |= up->lsr_saved_flags;
1435 up->lsr_saved_flags = 0;
1436
1437 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1438 /*
1439 * For statistics only
1440 */
1441 if (lsr & UART_LSR_BI) {
1442 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1443 up->port.icount.brk++;
1444 /*
1445 * If tegra port then clear the rx fifo to
1446 * accept another break/character.
1447 */
1448 if (up->port.type == PORT_TEGRA)
1449 clear_rx_fifo(up);
1450
1451 /*
1452 * We do the SysRQ and SAK checking
1453 * here because otherwise the break
1454 * may get masked by ignore_status_mask
1455 * or read_status_mask.
1456 */
1457 if (uart_handle_break(&up->port))
1458 goto ignore_char;
1459 } else if (lsr & UART_LSR_PE)
1460 up->port.icount.parity++;
1461 else if (lsr & UART_LSR_FE)
1462 up->port.icount.frame++;
1463 if (lsr & UART_LSR_OE)
1464 up->port.icount.overrun++;
1465
1466 /*
1467 * Mask off conditions which should be ignored.
1468 */
1469 lsr &= up->port.read_status_mask;
1470
1471 if (lsr & UART_LSR_BI) {
1472 DEBUG_INTR("handling break....");
1473 flag = TTY_BREAK;
1474 } else if (lsr & UART_LSR_PE)
1475 flag = TTY_PARITY;
1476 else if (lsr & UART_LSR_FE)
1477 flag = TTY_FRAME;
1478 }
1479 if (uart_handle_sysrq_char(&up->port, ch))
1480 goto ignore_char;
1481
1482 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1483
1484 ignore_char:
1485 lsr = serial_inp(up, UART_LSR);
1486 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1487 spin_unlock(&up->port.lock);
1488 tty_flip_buffer_push(tty);
1489 spin_lock(&up->port.lock);
1490 *status = lsr;
1491 }
1492
1493 static void transmit_chars(struct uart_8250_port *up)
1494 {
1495 struct circ_buf *xmit = &up->port.state->xmit;
1496 int count;
1497
1498 if (up->port.x_char) {
1499 serial_outp(up, UART_TX, up->port.x_char);
1500 up->port.icount.tx++;
1501 up->port.x_char = 0;
1502 return;
1503 }
1504 if (uart_tx_stopped(&up->port)) {
1505 serial8250_stop_tx(&up->port);
1506 return;
1507 }
1508 if (uart_circ_empty(xmit)) {
1509 __stop_tx(up);
1510 return;
1511 }
1512
1513 count = up->tx_loadsz;
1514 do {
1515 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1516 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1517 up->port.icount.tx++;
1518 if (uart_circ_empty(xmit))
1519 break;
1520 } while (--count > 0);
1521
1522 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1523 uart_write_wakeup(&up->port);
1524
1525 DEBUG_INTR("THRE...");
1526
1527 if (uart_circ_empty(xmit))
1528 __stop_tx(up);
1529 }
1530
1531 static unsigned int check_modem_status(struct uart_8250_port *up)
1532 {
1533 unsigned int status = serial_in(up, UART_MSR);
1534
1535 status |= up->msr_saved_flags;
1536 up->msr_saved_flags = 0;
1537 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1538 up->port.state != NULL) {
1539 if (status & UART_MSR_TERI)
1540 up->port.icount.rng++;
1541 if (status & UART_MSR_DDSR)
1542 up->port.icount.dsr++;
1543 if (status & UART_MSR_DDCD)
1544 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1545 if (status & UART_MSR_DCTS)
1546 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1547
1548 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
1549 }
1550
1551 return status;
1552 }
1553
1554 /*
1555 * This handles the interrupt from one port.
1556 */
1557 static void serial8250_handle_port(struct uart_8250_port *up)
1558 {
1559 unsigned int status;
1560 unsigned long flags;
1561
1562 spin_lock_irqsave(&up->port.lock, flags);
1563
1564 status = serial_inp(up, UART_LSR);
1565
1566 DEBUG_INTR("status = %x...", status);
1567
1568 if (status & (UART_LSR_DR | UART_LSR_BI))
1569 receive_chars(up, &status);
1570 check_modem_status(up);
1571 if (status & UART_LSR_THRE)
1572 transmit_chars(up);
1573
1574 spin_unlock_irqrestore(&up->port.lock, flags);
1575 }
1576
1577 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1578 {
1579 struct uart_8250_port *up =
1580 container_of(port, struct uart_8250_port, port);
1581
1582 if (!(iir & UART_IIR_NO_INT)) {
1583 serial8250_handle_port(up);
1584 return 1;
1585 }
1586
1587 return 0;
1588 }
1589 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1590
1591 static int serial8250_default_handle_irq(struct uart_port *port)
1592 {
1593 struct uart_8250_port *up =
1594 container_of(port, struct uart_8250_port, port);
1595 unsigned int iir = serial_in(up, UART_IIR);
1596
1597 return serial8250_handle_irq(port, iir);
1598 }
1599
1600 /*
1601 * This is the serial driver's interrupt routine.
1602 *
1603 * Arjan thinks the old way was overly complex, so it got simplified.
1604 * Alan disagrees, saying that need the complexity to handle the weird
1605 * nature of ISA shared interrupts. (This is a special exception.)
1606 *
1607 * In order to handle ISA shared interrupts properly, we need to check
1608 * that all ports have been serviced, and therefore the ISA interrupt
1609 * line has been de-asserted.
1610 *
1611 * This means we need to loop through all ports. checking that they
1612 * don't have an interrupt pending.
1613 */
1614 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1615 {
1616 struct irq_info *i = dev_id;
1617 struct list_head *l, *end = NULL;
1618 int pass_counter = 0, handled = 0;
1619
1620 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1621
1622 spin_lock(&i->lock);
1623
1624 l = i->head;
1625 do {
1626 struct uart_8250_port *up;
1627 struct uart_port *port;
1628
1629 up = list_entry(l, struct uart_8250_port, list);
1630 port = &up->port;
1631
1632 if (port->handle_irq(port)) {
1633 handled = 1;
1634 end = NULL;
1635 } else if (end == NULL)
1636 end = l;
1637
1638 l = l->next;
1639
1640 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1641 /* If we hit this, we're dead. */
1642 printk_ratelimited(KERN_ERR
1643 "serial8250: too much work for irq%d\n", irq);
1644 break;
1645 }
1646 } while (l != end);
1647
1648 spin_unlock(&i->lock);
1649
1650 DEBUG_INTR("end.\n");
1651
1652 return IRQ_RETVAL(handled);
1653 }
1654
1655 /*
1656 * To support ISA shared interrupts, we need to have one interrupt
1657 * handler that ensures that the IRQ line has been deasserted
1658 * before returning. Failing to do this will result in the IRQ
1659 * line being stuck active, and, since ISA irqs are edge triggered,
1660 * no more IRQs will be seen.
1661 */
1662 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1663 {
1664 spin_lock_irq(&i->lock);
1665
1666 if (!list_empty(i->head)) {
1667 if (i->head == &up->list)
1668 i->head = i->head->next;
1669 list_del(&up->list);
1670 } else {
1671 BUG_ON(i->head != &up->list);
1672 i->head = NULL;
1673 }
1674 spin_unlock_irq(&i->lock);
1675 /* List empty so throw away the hash node */
1676 if (i->head == NULL) {
1677 hlist_del(&i->node);
1678 kfree(i);
1679 }
1680 }
1681
1682 static int serial_link_irq_chain(struct uart_8250_port *up)
1683 {
1684 struct hlist_head *h;
1685 struct hlist_node *n;
1686 struct irq_info *i;
1687 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1688
1689 mutex_lock(&hash_mutex);
1690
1691 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1692
1693 hlist_for_each(n, h) {
1694 i = hlist_entry(n, struct irq_info, node);
1695 if (i->irq == up->port.irq)
1696 break;
1697 }
1698
1699 if (n == NULL) {
1700 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1701 if (i == NULL) {
1702 mutex_unlock(&hash_mutex);
1703 return -ENOMEM;
1704 }
1705 spin_lock_init(&i->lock);
1706 i->irq = up->port.irq;
1707 hlist_add_head(&i->node, h);
1708 }
1709 mutex_unlock(&hash_mutex);
1710
1711 spin_lock_irq(&i->lock);
1712
1713 if (i->head) {
1714 list_add(&up->list, i->head);
1715 spin_unlock_irq(&i->lock);
1716
1717 ret = 0;
1718 } else {
1719 INIT_LIST_HEAD(&up->list);
1720 i->head = &up->list;
1721 spin_unlock_irq(&i->lock);
1722 irq_flags |= up->port.irqflags;
1723 ret = request_irq(up->port.irq, serial8250_interrupt,
1724 irq_flags, "serial", i);
1725 if (ret < 0)
1726 serial_do_unlink(i, up);
1727 }
1728
1729 return ret;
1730 }
1731
1732 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1733 {
1734 struct irq_info *i;
1735 struct hlist_node *n;
1736 struct hlist_head *h;
1737
1738 mutex_lock(&hash_mutex);
1739
1740 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1741
1742 hlist_for_each(n, h) {
1743 i = hlist_entry(n, struct irq_info, node);
1744 if (i->irq == up->port.irq)
1745 break;
1746 }
1747
1748 BUG_ON(n == NULL);
1749 BUG_ON(i->head == NULL);
1750
1751 if (list_empty(i->head))
1752 free_irq(up->port.irq, i);
1753
1754 serial_do_unlink(i, up);
1755 mutex_unlock(&hash_mutex);
1756 }
1757
1758 /*
1759 * This function is used to handle ports that do not have an
1760 * interrupt. This doesn't work very well for 16450's, but gives
1761 * barely passable results for a 16550A. (Although at the expense
1762 * of much CPU overhead).
1763 */
1764 static void serial8250_timeout(unsigned long data)
1765 {
1766 struct uart_8250_port *up = (struct uart_8250_port *)data;
1767 unsigned int iir;
1768
1769 iir = serial_in(up, UART_IIR);
1770 if (!(iir & UART_IIR_NO_INT))
1771 serial8250_handle_port(up);
1772 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1773 }
1774
1775 static void serial8250_backup_timeout(unsigned long data)
1776 {
1777 struct uart_8250_port *up = (struct uart_8250_port *)data;
1778 unsigned int iir, ier = 0, lsr;
1779 unsigned long flags;
1780
1781 spin_lock_irqsave(&up->port.lock, flags);
1782
1783 /*
1784 * Must disable interrupts or else we risk racing with the interrupt
1785 * based handler.
1786 */
1787 if (is_real_interrupt(up->port.irq)) {
1788 ier = serial_in(up, UART_IER);
1789 serial_out(up, UART_IER, 0);
1790 }
1791
1792 iir = serial_in(up, UART_IIR);
1793
1794 /*
1795 * This should be a safe test for anyone who doesn't trust the
1796 * IIR bits on their UART, but it's specifically designed for
1797 * the "Diva" UART used on the management processor on many HP
1798 * ia64 and parisc boxes.
1799 */
1800 lsr = serial_in(up, UART_LSR);
1801 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1802 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1803 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1804 (lsr & UART_LSR_THRE)) {
1805 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1806 iir |= UART_IIR_THRI;
1807 }
1808
1809 if (!(iir & UART_IIR_NO_INT))
1810 transmit_chars(up);
1811
1812 if (is_real_interrupt(up->port.irq))
1813 serial_out(up, UART_IER, ier);
1814
1815 spin_unlock_irqrestore(&up->port.lock, flags);
1816
1817 /* Standard timer interval plus 0.2s to keep the port running */
1818 mod_timer(&up->timer,
1819 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1820 }
1821
1822 static unsigned int serial8250_tx_empty(struct uart_port *port)
1823 {
1824 struct uart_8250_port *up =
1825 container_of(port, struct uart_8250_port, port);
1826 unsigned long flags;
1827 unsigned int lsr;
1828
1829 spin_lock_irqsave(&up->port.lock, flags);
1830 lsr = serial_in(up, UART_LSR);
1831 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1832 spin_unlock_irqrestore(&up->port.lock, flags);
1833
1834 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1835 }
1836
1837 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1838 {
1839 struct uart_8250_port *up =
1840 container_of(port, struct uart_8250_port, port);
1841 unsigned int status;
1842 unsigned int ret;
1843
1844 status = check_modem_status(up);
1845
1846 ret = 0;
1847 if (status & UART_MSR_DCD)
1848 ret |= TIOCM_CAR;
1849 if (status & UART_MSR_RI)
1850 ret |= TIOCM_RNG;
1851 if (status & UART_MSR_DSR)
1852 ret |= TIOCM_DSR;
1853 if (status & UART_MSR_CTS)
1854 ret |= TIOCM_CTS;
1855 return ret;
1856 }
1857
1858 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1859 {
1860 struct uart_8250_port *up =
1861 container_of(port, struct uart_8250_port, port);
1862 unsigned char mcr = 0;
1863
1864 if (mctrl & TIOCM_RTS)
1865 mcr |= UART_MCR_RTS;
1866 if (mctrl & TIOCM_DTR)
1867 mcr |= UART_MCR_DTR;
1868 if (mctrl & TIOCM_OUT1)
1869 mcr |= UART_MCR_OUT1;
1870 if (mctrl & TIOCM_OUT2)
1871 mcr |= UART_MCR_OUT2;
1872 if (mctrl & TIOCM_LOOP)
1873 mcr |= UART_MCR_LOOP;
1874
1875 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1876
1877 serial_out(up, UART_MCR, mcr);
1878 }
1879
1880 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1881 {
1882 struct uart_8250_port *up =
1883 container_of(port, struct uart_8250_port, port);
1884 unsigned long flags;
1885
1886 spin_lock_irqsave(&up->port.lock, flags);
1887 if (break_state == -1)
1888 up->lcr |= UART_LCR_SBC;
1889 else
1890 up->lcr &= ~UART_LCR_SBC;
1891 serial_out(up, UART_LCR, up->lcr);
1892 spin_unlock_irqrestore(&up->port.lock, flags);
1893 }
1894
1895 /*
1896 * Wait for transmitter & holding register to empty
1897 */
1898 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1899 {
1900 unsigned int status, tmout = 10000;
1901
1902 /* Wait up to 10ms for the character(s) to be sent. */
1903 for (;;) {
1904 status = serial_in(up, UART_LSR);
1905
1906 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1907
1908 if ((status & bits) == bits)
1909 break;
1910 if (--tmout == 0)
1911 break;
1912 udelay(1);
1913 }
1914
1915 /* Wait up to 1s for flow control if necessary */
1916 if (up->port.flags & UPF_CONS_FLOW) {
1917 unsigned int tmout;
1918 for (tmout = 1000000; tmout; tmout--) {
1919 unsigned int msr = serial_in(up, UART_MSR);
1920 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1921 if (msr & UART_MSR_CTS)
1922 break;
1923 udelay(1);
1924 touch_nmi_watchdog();
1925 }
1926 }
1927 }
1928
1929 #ifdef CONFIG_CONSOLE_POLL
1930 /*
1931 * Console polling routines for writing and reading from the uart while
1932 * in an interrupt or debug context.
1933 */
1934
1935 static int serial8250_get_poll_char(struct uart_port *port)
1936 {
1937 struct uart_8250_port *up =
1938 container_of(port, struct uart_8250_port, port);
1939 unsigned char lsr = serial_inp(up, UART_LSR);
1940
1941 if (!(lsr & UART_LSR_DR))
1942 return NO_POLL_CHAR;
1943
1944 return serial_inp(up, UART_RX);
1945 }
1946
1947
1948 static void serial8250_put_poll_char(struct uart_port *port,
1949 unsigned char c)
1950 {
1951 unsigned int ier;
1952 struct uart_8250_port *up =
1953 container_of(port, struct uart_8250_port, port);
1954
1955 /*
1956 * First save the IER then disable the interrupts
1957 */
1958 ier = serial_in(up, UART_IER);
1959 if (up->capabilities & UART_CAP_UUE)
1960 serial_out(up, UART_IER, UART_IER_UUE);
1961 else
1962 serial_out(up, UART_IER, 0);
1963
1964 wait_for_xmitr(up, BOTH_EMPTY);
1965 /*
1966 * Send the character out.
1967 * If a LF, also do CR...
1968 */
1969 serial_out(up, UART_TX, c);
1970 if (c == 10) {
1971 wait_for_xmitr(up, BOTH_EMPTY);
1972 serial_out(up, UART_TX, 13);
1973 }
1974
1975 /*
1976 * Finally, wait for transmitter to become empty
1977 * and restore the IER
1978 */
1979 wait_for_xmitr(up, BOTH_EMPTY);
1980 serial_out(up, UART_IER, ier);
1981 }
1982
1983 #endif /* CONFIG_CONSOLE_POLL */
1984
1985 static int serial8250_startup(struct uart_port *port)
1986 {
1987 struct uart_8250_port *up =
1988 container_of(port, struct uart_8250_port, port);
1989 unsigned long flags;
1990 unsigned char lsr, iir;
1991 int retval;
1992
1993 up->port.fifosize = uart_config[up->port.type].fifo_size;
1994 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1995 up->capabilities = uart_config[up->port.type].flags;
1996 if (!ALPHA_KLUDGE_MCR) {
1997 up->mcr_mask = uart_config[up->port.type].mcr_mask;
1998 up->mcr_force = uart_config[up->port.type].mcr_force;
1999 }
2000 up->mcr = 0;
2001
2002 if (up->port.iotype != up->cur_iotype)
2003 set_io_from_upio(port);
2004
2005 if (up->port.type == PORT_16C950) {
2006 /* Wake up and initialize UART */
2007 up->acr = 0;
2008 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2009 serial_outp(up, UART_EFR, UART_EFR_ECB);
2010 serial_outp(up, UART_IER, 0);
2011 serial_outp(up, UART_LCR, 0);
2012 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2013 serial_outp(up, UART_LCR, 0xBF);
2014 serial_outp(up, UART_EFR, UART_EFR_ECB);
2015 serial_outp(up, UART_LCR, 0);
2016 }
2017
2018 #ifdef CONFIG_SERIAL_8250_RSA
2019 /*
2020 * If this is an RSA port, see if we can kick it up to the
2021 * higher speed clock.
2022 */
2023 enable_rsa(up);
2024 #endif
2025
2026 /*
2027 * Clear the FIFO buffers and disable them.
2028 * (they will be reenabled in set_termios())
2029 */
2030 serial8250_clear_fifos(up);
2031
2032 /*
2033 * Clear the interrupt registers.
2034 */
2035 (void) serial_inp(up, UART_LSR);
2036 (void) serial_inp(up, UART_RX);
2037 (void) serial_inp(up, UART_IIR);
2038 (void) serial_inp(up, UART_MSR);
2039
2040 /*
2041 * At this point, there's no way the LSR could still be 0xff;
2042 * if it is, then bail out, because there's likely no UART
2043 * here.
2044 */
2045 if (!(up->port.flags & UPF_BUGGY_UART) &&
2046 (serial_inp(up, UART_LSR) == 0xff)) {
2047 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2048 serial_index(&up->port));
2049 return -ENODEV;
2050 }
2051
2052 /*
2053 * For a XR16C850, we need to set the trigger levels
2054 */
2055 if (up->port.type == PORT_16850) {
2056 unsigned char fctr;
2057
2058 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2059
2060 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2061 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2062 serial_outp(up, UART_TRG, UART_TRG_96);
2063 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2064 serial_outp(up, UART_TRG, UART_TRG_96);
2065
2066 serial_outp(up, UART_LCR, 0);
2067 }
2068
2069 if (is_real_interrupt(up->port.irq)) {
2070 unsigned char iir1;
2071 /*
2072 * Test for UARTs that do not reassert THRE when the
2073 * transmitter is idle and the interrupt has already
2074 * been cleared. Real 16550s should always reassert
2075 * this interrupt whenever the transmitter is idle and
2076 * the interrupt is enabled. Delays are necessary to
2077 * allow register changes to become visible.
2078 */
2079 spin_lock_irqsave(&up->port.lock, flags);
2080 if (up->port.irqflags & IRQF_SHARED)
2081 disable_irq_nosync(up->port.irq);
2082
2083 wait_for_xmitr(up, UART_LSR_THRE);
2084 serial_out_sync(up, UART_IER, UART_IER_THRI);
2085 udelay(1); /* allow THRE to set */
2086 iir1 = serial_in(up, UART_IIR);
2087 serial_out(up, UART_IER, 0);
2088 serial_out_sync(up, UART_IER, UART_IER_THRI);
2089 udelay(1); /* allow a working UART time to re-assert THRE */
2090 iir = serial_in(up, UART_IIR);
2091 serial_out(up, UART_IER, 0);
2092
2093 if (up->port.irqflags & IRQF_SHARED)
2094 enable_irq(up->port.irq);
2095 spin_unlock_irqrestore(&up->port.lock, flags);
2096
2097 /*
2098 * If the interrupt is not reasserted, setup a timer to
2099 * kick the UART on a regular basis.
2100 */
2101 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
2102 up->bugs |= UART_BUG_THRE;
2103 pr_debug("ttyS%d - using backup timer\n",
2104 serial_index(port));
2105 }
2106 }
2107
2108 /*
2109 * The above check will only give an accurate result the first time
2110 * the port is opened so this value needs to be preserved.
2111 */
2112 if (up->bugs & UART_BUG_THRE) {
2113 up->timer.function = serial8250_backup_timeout;
2114 up->timer.data = (unsigned long)up;
2115 mod_timer(&up->timer, jiffies +
2116 uart_poll_timeout(port) + HZ / 5);
2117 }
2118
2119 /*
2120 * If the "interrupt" for this port doesn't correspond with any
2121 * hardware interrupt, we use a timer-based system. The original
2122 * driver used to do this with IRQ0.
2123 */
2124 if (!is_real_interrupt(up->port.irq)) {
2125 up->timer.data = (unsigned long)up;
2126 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2127 } else {
2128 retval = serial_link_irq_chain(up);
2129 if (retval)
2130 return retval;
2131 }
2132
2133 /*
2134 * Now, initialize the UART
2135 */
2136 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2137
2138 spin_lock_irqsave(&up->port.lock, flags);
2139 if (up->port.flags & UPF_FOURPORT) {
2140 if (!is_real_interrupt(up->port.irq))
2141 up->port.mctrl |= TIOCM_OUT1;
2142 } else
2143 /*
2144 * Most PC uarts need OUT2 raised to enable interrupts.
2145 */
2146 if (is_real_interrupt(up->port.irq))
2147 up->port.mctrl |= TIOCM_OUT2;
2148
2149 serial8250_set_mctrl(&up->port, up->port.mctrl);
2150
2151 /* Serial over Lan (SoL) hack:
2152 Intel 8257x Gigabit ethernet chips have a
2153 16550 emulation, to be used for Serial Over Lan.
2154 Those chips take a longer time than a normal
2155 serial device to signalize that a transmission
2156 data was queued. Due to that, the above test generally
2157 fails. One solution would be to delay the reading of
2158 iir. However, this is not reliable, since the timeout
2159 is variable. So, let's just don't test if we receive
2160 TX irq. This way, we'll never enable UART_BUG_TXEN.
2161 */
2162 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2163 goto dont_test_tx_en;
2164
2165 /*
2166 * Do a quick test to see if we receive an
2167 * interrupt when we enable the TX irq.
2168 */
2169 serial_outp(up, UART_IER, UART_IER_THRI);
2170 lsr = serial_in(up, UART_LSR);
2171 iir = serial_in(up, UART_IIR);
2172 serial_outp(up, UART_IER, 0);
2173
2174 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2175 if (!(up->bugs & UART_BUG_TXEN)) {
2176 up->bugs |= UART_BUG_TXEN;
2177 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2178 serial_index(port));
2179 }
2180 } else {
2181 up->bugs &= ~UART_BUG_TXEN;
2182 }
2183
2184 dont_test_tx_en:
2185 spin_unlock_irqrestore(&up->port.lock, flags);
2186
2187 /*
2188 * Clear the interrupt registers again for luck, and clear the
2189 * saved flags to avoid getting false values from polling
2190 * routines or the previous session.
2191 */
2192 serial_inp(up, UART_LSR);
2193 serial_inp(up, UART_RX);
2194 serial_inp(up, UART_IIR);
2195 serial_inp(up, UART_MSR);
2196 up->lsr_saved_flags = 0;
2197 up->msr_saved_flags = 0;
2198
2199 /*
2200 * Finally, enable interrupts. Note: Modem status interrupts
2201 * are set via set_termios(), which will be occurring imminently
2202 * anyway, so we don't enable them here.
2203 */
2204 up->ier = UART_IER_RLSI | UART_IER_RDI;
2205 serial_outp(up, UART_IER, up->ier);
2206
2207 if (up->port.flags & UPF_FOURPORT) {
2208 unsigned int icp;
2209 /*
2210 * Enable interrupts on the AST Fourport board
2211 */
2212 icp = (up->port.iobase & 0xfe0) | 0x01f;
2213 outb_p(0x80, icp);
2214 (void) inb_p(icp);
2215 }
2216
2217 return 0;
2218 }
2219
2220 static void serial8250_shutdown(struct uart_port *port)
2221 {
2222 struct uart_8250_port *up =
2223 container_of(port, struct uart_8250_port, port);
2224 unsigned long flags;
2225
2226 /*
2227 * Disable interrupts from this port
2228 */
2229 up->ier = 0;
2230 serial_outp(up, UART_IER, 0);
2231
2232 spin_lock_irqsave(&up->port.lock, flags);
2233 if (up->port.flags & UPF_FOURPORT) {
2234 /* reset interrupts on the AST Fourport board */
2235 inb((up->port.iobase & 0xfe0) | 0x1f);
2236 up->port.mctrl |= TIOCM_OUT1;
2237 } else
2238 up->port.mctrl &= ~TIOCM_OUT2;
2239
2240 serial8250_set_mctrl(&up->port, up->port.mctrl);
2241 spin_unlock_irqrestore(&up->port.lock, flags);
2242
2243 /*
2244 * Disable break condition and FIFOs
2245 */
2246 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2247 serial8250_clear_fifos(up);
2248
2249 #ifdef CONFIG_SERIAL_8250_RSA
2250 /*
2251 * Reset the RSA board back to 115kbps compat mode.
2252 */
2253 disable_rsa(up);
2254 #endif
2255
2256 /*
2257 * Read data port to reset things, and then unlink from
2258 * the IRQ chain.
2259 */
2260 (void) serial_in(up, UART_RX);
2261
2262 del_timer_sync(&up->timer);
2263 up->timer.function = serial8250_timeout;
2264 if (is_real_interrupt(up->port.irq))
2265 serial_unlink_irq_chain(up);
2266 }
2267
2268 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2269 {
2270 unsigned int quot;
2271
2272 /*
2273 * Handle magic divisors for baud rates above baud_base on
2274 * SMSC SuperIO chips.
2275 */
2276 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2277 baud == (port->uartclk/4))
2278 quot = 0x8001;
2279 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2280 baud == (port->uartclk/8))
2281 quot = 0x8002;
2282 else
2283 quot = uart_get_divisor(port, baud);
2284
2285 return quot;
2286 }
2287
2288 void
2289 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2290 struct ktermios *old)
2291 {
2292 struct uart_8250_port *up =
2293 container_of(port, struct uart_8250_port, port);
2294 unsigned char cval, fcr = 0;
2295 unsigned long flags;
2296 unsigned int baud, quot;
2297
2298 switch (termios->c_cflag & CSIZE) {
2299 case CS5:
2300 cval = UART_LCR_WLEN5;
2301 break;
2302 case CS6:
2303 cval = UART_LCR_WLEN6;
2304 break;
2305 case CS7:
2306 cval = UART_LCR_WLEN7;
2307 break;
2308 default:
2309 case CS8:
2310 cval = UART_LCR_WLEN8;
2311 break;
2312 }
2313
2314 if (termios->c_cflag & CSTOPB)
2315 cval |= UART_LCR_STOP;
2316 if (termios->c_cflag & PARENB)
2317 cval |= UART_LCR_PARITY;
2318 if (!(termios->c_cflag & PARODD))
2319 cval |= UART_LCR_EPAR;
2320 #ifdef CMSPAR
2321 if (termios->c_cflag & CMSPAR)
2322 cval |= UART_LCR_SPAR;
2323 #endif
2324
2325 /*
2326 * Ask the core to calculate the divisor for us.
2327 */
2328 baud = uart_get_baud_rate(port, termios, old,
2329 port->uartclk / 16 / 0xffff,
2330 port->uartclk / 16);
2331 quot = serial8250_get_divisor(port, baud);
2332
2333 /*
2334 * Oxford Semi 952 rev B workaround
2335 */
2336 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2337 quot++;
2338
2339 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2340 if (baud < 2400)
2341 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2342 else
2343 fcr = uart_config[up->port.type].fcr;
2344 }
2345
2346 /*
2347 * MCR-based auto flow control. When AFE is enabled, RTS will be
2348 * deasserted when the receive FIFO contains more characters than
2349 * the trigger, or the MCR RTS bit is cleared. In the case where
2350 * the remote UART is not using CTS auto flow control, we must
2351 * have sufficient FIFO entries for the latency of the remote
2352 * UART to respond. IOW, at least 32 bytes of FIFO.
2353 */
2354 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2355 up->mcr &= ~UART_MCR_AFE;
2356 if (termios->c_cflag & CRTSCTS)
2357 up->mcr |= UART_MCR_AFE;
2358 }
2359
2360 /*
2361 * Ok, we're now changing the port state. Do it with
2362 * interrupts disabled.
2363 */
2364 spin_lock_irqsave(&up->port.lock, flags);
2365
2366 /*
2367 * Update the per-port timeout.
2368 */
2369 uart_update_timeout(port, termios->c_cflag, baud);
2370
2371 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2372 if (termios->c_iflag & INPCK)
2373 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2374 if (termios->c_iflag & (BRKINT | PARMRK))
2375 up->port.read_status_mask |= UART_LSR_BI;
2376
2377 /*
2378 * Characteres to ignore
2379 */
2380 up->port.ignore_status_mask = 0;
2381 if (termios->c_iflag & IGNPAR)
2382 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2383 if (termios->c_iflag & IGNBRK) {
2384 up->port.ignore_status_mask |= UART_LSR_BI;
2385 /*
2386 * If we're ignoring parity and break indicators,
2387 * ignore overruns too (for real raw support).
2388 */
2389 if (termios->c_iflag & IGNPAR)
2390 up->port.ignore_status_mask |= UART_LSR_OE;
2391 }
2392
2393 /*
2394 * ignore all characters if CREAD is not set
2395 */
2396 if ((termios->c_cflag & CREAD) == 0)
2397 up->port.ignore_status_mask |= UART_LSR_DR;
2398
2399 /*
2400 * CTS flow control flag and modem status interrupts
2401 */
2402 up->ier &= ~UART_IER_MSI;
2403 if (!(up->bugs & UART_BUG_NOMSR) &&
2404 UART_ENABLE_MS(&up->port, termios->c_cflag))
2405 up->ier |= UART_IER_MSI;
2406 if (up->capabilities & UART_CAP_UUE)
2407 up->ier |= UART_IER_UUE;
2408 if (up->capabilities & UART_CAP_RTOIE)
2409 up->ier |= UART_IER_RTOIE;
2410
2411 serial_out(up, UART_IER, up->ier);
2412
2413 if (up->capabilities & UART_CAP_EFR) {
2414 unsigned char efr = 0;
2415 /*
2416 * TI16C752/Startech hardware flow control. FIXME:
2417 * - TI16C752 requires control thresholds to be set.
2418 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2419 */
2420 if (termios->c_cflag & CRTSCTS)
2421 efr |= UART_EFR_CTS;
2422
2423 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2424 if (up->port.flags & UPF_EXAR_EFR)
2425 serial_outp(up, UART_XR_EFR, efr);
2426 else
2427 serial_outp(up, UART_EFR, efr);
2428 }
2429
2430 #ifdef CONFIG_ARCH_OMAP
2431 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2432 if (cpu_is_omap1510() && is_omap_port(up)) {
2433 if (baud == 115200) {
2434 quot = 1;
2435 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2436 } else
2437 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2438 }
2439 #endif
2440
2441 if (up->capabilities & UART_NATSEMI) {
2442 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2443 serial_outp(up, UART_LCR, 0xe0);
2444 } else {
2445 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2446 }
2447
2448 serial_dl_write(up, quot);
2449
2450 /*
2451 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2452 * is written without DLAB set, this mode will be disabled.
2453 */
2454 if (up->port.type == PORT_16750)
2455 serial_outp(up, UART_FCR, fcr);
2456
2457 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2458 up->lcr = cval; /* Save LCR */
2459 if (up->port.type != PORT_16750) {
2460 if (fcr & UART_FCR_ENABLE_FIFO) {
2461 /* emulated UARTs (Lucent Venus 167x) need two steps */
2462 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2463 }
2464 serial_outp(up, UART_FCR, fcr); /* set fcr */
2465 }
2466 serial8250_set_mctrl(&up->port, up->port.mctrl);
2467 spin_unlock_irqrestore(&up->port.lock, flags);
2468 /* Don't rewrite B0 */
2469 if (tty_termios_baud_rate(termios))
2470 tty_termios_encode_baud_rate(termios, baud, baud);
2471 }
2472 EXPORT_SYMBOL(serial8250_do_set_termios);
2473
2474 static void
2475 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2476 struct ktermios *old)
2477 {
2478 if (port->set_termios)
2479 port->set_termios(port, termios, old);
2480 else
2481 serial8250_do_set_termios(port, termios, old);
2482 }
2483
2484 static void
2485 serial8250_set_ldisc(struct uart_port *port, int new)
2486 {
2487 if (new == N_PPS) {
2488 port->flags |= UPF_HARDPPS_CD;
2489 serial8250_enable_ms(port);
2490 } else
2491 port->flags &= ~UPF_HARDPPS_CD;
2492 }
2493
2494
2495 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2496 unsigned int oldstate)
2497 {
2498 struct uart_8250_port *p =
2499 container_of(port, struct uart_8250_port, port);
2500
2501 serial8250_set_sleep(p, state != 0);
2502 }
2503 EXPORT_SYMBOL(serial8250_do_pm);
2504
2505 static void
2506 serial8250_pm(struct uart_port *port, unsigned int state,
2507 unsigned int oldstate)
2508 {
2509 if (port->pm)
2510 port->pm(port, state, oldstate);
2511 else
2512 serial8250_do_pm(port, state, oldstate);
2513 }
2514
2515 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2516 {
2517 if (pt->port.iotype == UPIO_AU)
2518 return 0x1000;
2519 #ifdef CONFIG_ARCH_OMAP
2520 if (is_omap_port(pt))
2521 return 0x16 << pt->port.regshift;
2522 #endif
2523 return 8 << pt->port.regshift;
2524 }
2525
2526 /*
2527 * Resource handling.
2528 */
2529 static int serial8250_request_std_resource(struct uart_8250_port *up)
2530 {
2531 unsigned int size = serial8250_port_size(up);
2532 int ret = 0;
2533
2534 switch (up->port.iotype) {
2535 case UPIO_AU:
2536 case UPIO_TSI:
2537 case UPIO_MEM32:
2538 case UPIO_MEM:
2539 if (!up->port.mapbase)
2540 break;
2541
2542 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2543 ret = -EBUSY;
2544 break;
2545 }
2546
2547 if (up->port.flags & UPF_IOREMAP) {
2548 up->port.membase = ioremap_nocache(up->port.mapbase,
2549 size);
2550 if (!up->port.membase) {
2551 release_mem_region(up->port.mapbase, size);
2552 ret = -ENOMEM;
2553 }
2554 }
2555 break;
2556
2557 case UPIO_HUB6:
2558 case UPIO_PORT:
2559 if (!request_region(up->port.iobase, size, "serial"))
2560 ret = -EBUSY;
2561 break;
2562 }
2563 return ret;
2564 }
2565
2566 static void serial8250_release_std_resource(struct uart_8250_port *up)
2567 {
2568 unsigned int size = serial8250_port_size(up);
2569
2570 switch (up->port.iotype) {
2571 case UPIO_AU:
2572 case UPIO_TSI:
2573 case UPIO_MEM32:
2574 case UPIO_MEM:
2575 if (!up->port.mapbase)
2576 break;
2577
2578 if (up->port.flags & UPF_IOREMAP) {
2579 iounmap(up->port.membase);
2580 up->port.membase = NULL;
2581 }
2582
2583 release_mem_region(up->port.mapbase, size);
2584 break;
2585
2586 case UPIO_HUB6:
2587 case UPIO_PORT:
2588 release_region(up->port.iobase, size);
2589 break;
2590 }
2591 }
2592
2593 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2594 {
2595 unsigned long start = UART_RSA_BASE << up->port.regshift;
2596 unsigned int size = 8 << up->port.regshift;
2597 int ret = -EINVAL;
2598
2599 switch (up->port.iotype) {
2600 case UPIO_HUB6:
2601 case UPIO_PORT:
2602 start += up->port.iobase;
2603 if (request_region(start, size, "serial-rsa"))
2604 ret = 0;
2605 else
2606 ret = -EBUSY;
2607 break;
2608 }
2609
2610 return ret;
2611 }
2612
2613 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2614 {
2615 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2616 unsigned int size = 8 << up->port.regshift;
2617
2618 switch (up->port.iotype) {
2619 case UPIO_HUB6:
2620 case UPIO_PORT:
2621 release_region(up->port.iobase + offset, size);
2622 break;
2623 }
2624 }
2625
2626 static void serial8250_release_port(struct uart_port *port)
2627 {
2628 struct uart_8250_port *up =
2629 container_of(port, struct uart_8250_port, port);
2630
2631 serial8250_release_std_resource(up);
2632 if (up->port.type == PORT_RSA)
2633 serial8250_release_rsa_resource(up);
2634 }
2635
2636 static int serial8250_request_port(struct uart_port *port)
2637 {
2638 struct uart_8250_port *up =
2639 container_of(port, struct uart_8250_port, port);
2640 int ret = 0;
2641
2642 ret = serial8250_request_std_resource(up);
2643 if (ret == 0 && up->port.type == PORT_RSA) {
2644 ret = serial8250_request_rsa_resource(up);
2645 if (ret < 0)
2646 serial8250_release_std_resource(up);
2647 }
2648
2649 return ret;
2650 }
2651
2652 static void serial8250_config_port(struct uart_port *port, int flags)
2653 {
2654 struct uart_8250_port *up =
2655 container_of(port, struct uart_8250_port, port);
2656 int probeflags = PROBE_ANY;
2657 int ret;
2658
2659 /*
2660 * Find the region that we can probe for. This in turn
2661 * tells us whether we can probe for the type of port.
2662 */
2663 ret = serial8250_request_std_resource(up);
2664 if (ret < 0)
2665 return;
2666
2667 ret = serial8250_request_rsa_resource(up);
2668 if (ret < 0)
2669 probeflags &= ~PROBE_RSA;
2670
2671 if (up->port.iotype != up->cur_iotype)
2672 set_io_from_upio(port);
2673
2674 if (flags & UART_CONFIG_TYPE)
2675 autoconfig(up, probeflags);
2676
2677 /* if access method is AU, it is a 16550 with a quirk */
2678 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2679 up->bugs |= UART_BUG_NOMSR;
2680
2681 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2682 autoconfig_irq(up);
2683
2684 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2685 serial8250_release_rsa_resource(up);
2686 if (up->port.type == PORT_UNKNOWN)
2687 serial8250_release_std_resource(up);
2688 }
2689
2690 static int
2691 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2692 {
2693 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2694 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2695 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2696 ser->type == PORT_STARTECH)
2697 return -EINVAL;
2698 return 0;
2699 }
2700
2701 static const char *
2702 serial8250_type(struct uart_port *port)
2703 {
2704 int type = port->type;
2705
2706 if (type >= ARRAY_SIZE(uart_config))
2707 type = 0;
2708 return uart_config[type].name;
2709 }
2710
2711 static struct uart_ops serial8250_pops = {
2712 .tx_empty = serial8250_tx_empty,
2713 .set_mctrl = serial8250_set_mctrl,
2714 .get_mctrl = serial8250_get_mctrl,
2715 .stop_tx = serial8250_stop_tx,
2716 .start_tx = serial8250_start_tx,
2717 .stop_rx = serial8250_stop_rx,
2718 .enable_ms = serial8250_enable_ms,
2719 .break_ctl = serial8250_break_ctl,
2720 .startup = serial8250_startup,
2721 .shutdown = serial8250_shutdown,
2722 .set_termios = serial8250_set_termios,
2723 .set_ldisc = serial8250_set_ldisc,
2724 .pm = serial8250_pm,
2725 .type = serial8250_type,
2726 .release_port = serial8250_release_port,
2727 .request_port = serial8250_request_port,
2728 .config_port = serial8250_config_port,
2729 .verify_port = serial8250_verify_port,
2730 #ifdef CONFIG_CONSOLE_POLL
2731 .poll_get_char = serial8250_get_poll_char,
2732 .poll_put_char = serial8250_put_poll_char,
2733 #endif
2734 };
2735
2736 static struct uart_8250_port serial8250_ports[UART_NR];
2737
2738 static void (*serial8250_isa_config)(int port, struct uart_port *up,
2739 unsigned short *capabilities);
2740
2741 void serial8250_set_isa_configurator(
2742 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2743 {
2744 serial8250_isa_config = v;
2745 }
2746 EXPORT_SYMBOL(serial8250_set_isa_configurator);
2747
2748 static void __init serial8250_isa_init_ports(void)
2749 {
2750 struct uart_8250_port *up;
2751 static int first = 1;
2752 int i, irqflag = 0;
2753
2754 if (!first)
2755 return;
2756 first = 0;
2757
2758 for (i = 0; i < nr_uarts; i++) {
2759 struct uart_8250_port *up = &serial8250_ports[i];
2760
2761 up->port.line = i;
2762 spin_lock_init(&up->port.lock);
2763
2764 init_timer(&up->timer);
2765 up->timer.function = serial8250_timeout;
2766
2767 /*
2768 * ALPHA_KLUDGE_MCR needs to be killed.
2769 */
2770 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2771 up->mcr_force = ALPHA_KLUDGE_MCR;
2772
2773 up->port.ops = &serial8250_pops;
2774 }
2775
2776 if (share_irqs)
2777 irqflag = IRQF_SHARED;
2778
2779 for (i = 0, up = serial8250_ports;
2780 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2781 i++, up++) {
2782 up->port.iobase = old_serial_port[i].port;
2783 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2784 up->port.irqflags = old_serial_port[i].irqflags;
2785 up->port.uartclk = old_serial_port[i].baud_base * 16;
2786 up->port.flags = old_serial_port[i].flags;
2787 up->port.hub6 = old_serial_port[i].hub6;
2788 up->port.membase = old_serial_port[i].iomem_base;
2789 up->port.iotype = old_serial_port[i].io_type;
2790 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2791 set_io_from_upio(&up->port);
2792 up->port.irqflags |= irqflag;
2793 if (serial8250_isa_config != NULL)
2794 serial8250_isa_config(i, &up->port, &up->capabilities);
2795
2796 }
2797 }
2798
2799 static void
2800 serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2801 {
2802 up->port.type = type;
2803 up->port.fifosize = uart_config[type].fifo_size;
2804 up->capabilities = uart_config[type].flags;
2805 up->tx_loadsz = uart_config[type].tx_loadsz;
2806 if (!ALPHA_KLUDGE_MCR) {
2807 up->mcr_mask = uart_config[type].mcr_mask;
2808 up->mcr_force = uart_config[type].mcr_force;
2809 }
2810 }
2811
2812 static void __init
2813 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2814 {
2815 int i;
2816
2817 for (i = 0; i < nr_uarts; i++) {
2818 struct uart_8250_port *up = &serial8250_ports[i];
2819 up->cur_iotype = 0xFF;
2820 }
2821
2822 serial8250_isa_init_ports();
2823
2824 for (i = 0; i < nr_uarts; i++) {
2825 struct uart_8250_port *up = &serial8250_ports[i];
2826
2827 up->port.dev = dev;
2828
2829 if (up->port.flags & UPF_FIXED_TYPE)
2830 serial8250_init_fixed_type_port(up, up->port.type);
2831
2832 uart_add_one_port(drv, &up->port);
2833 }
2834 }
2835
2836 #ifdef CONFIG_SERIAL_8250_CONSOLE
2837
2838 static void serial8250_console_putchar(struct uart_port *port, int ch)
2839 {
2840 struct uart_8250_port *up =
2841 container_of(port, struct uart_8250_port, port);
2842
2843 wait_for_xmitr(up, UART_LSR_THRE);
2844 serial_out(up, UART_TX, ch);
2845 }
2846
2847 /*
2848 * Print a string to the serial port trying not to disturb
2849 * any possible real use of the port...
2850 *
2851 * The console_lock must be held when we get here.
2852 */
2853 static void
2854 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2855 {
2856 struct uart_8250_port *up = &serial8250_ports[co->index];
2857 unsigned long flags;
2858 unsigned int ier;
2859 int locked = 1;
2860
2861 touch_nmi_watchdog();
2862
2863 local_irq_save(flags);
2864 if (up->port.sysrq) {
2865 /* serial8250_handle_port() already took the lock */
2866 locked = 0;
2867 } else if (oops_in_progress) {
2868 locked = spin_trylock(&up->port.lock);
2869 } else
2870 spin_lock(&up->port.lock);
2871
2872 /*
2873 * First save the IER then disable the interrupts
2874 */
2875 ier = serial_in(up, UART_IER);
2876
2877 if (up->capabilities & UART_CAP_UUE)
2878 serial_out(up, UART_IER, UART_IER_UUE);
2879 else
2880 serial_out(up, UART_IER, 0);
2881
2882 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2883
2884 /*
2885 * Finally, wait for transmitter to become empty
2886 * and restore the IER
2887 */
2888 wait_for_xmitr(up, BOTH_EMPTY);
2889 serial_out(up, UART_IER, ier);
2890
2891 /*
2892 * The receive handling will happen properly because the
2893 * receive ready bit will still be set; it is not cleared
2894 * on read. However, modem control will not, we must
2895 * call it if we have saved something in the saved flags
2896 * while processing with interrupts off.
2897 */
2898 if (up->msr_saved_flags)
2899 check_modem_status(up);
2900
2901 if (locked)
2902 spin_unlock(&up->port.lock);
2903 local_irq_restore(flags);
2904 }
2905
2906 static int __init serial8250_console_setup(struct console *co, char *options)
2907 {
2908 struct uart_port *port;
2909 int baud = 9600;
2910 int bits = 8;
2911 int parity = 'n';
2912 int flow = 'n';
2913
2914 /*
2915 * Check whether an invalid uart number has been specified, and
2916 * if so, search for the first available port that does have
2917 * console support.
2918 */
2919 if (co->index >= nr_uarts)
2920 co->index = 0;
2921 port = &serial8250_ports[co->index].port;
2922 if (!port->iobase && !port->membase)
2923 return -ENODEV;
2924
2925 if (options)
2926 uart_parse_options(options, &baud, &parity, &bits, &flow);
2927
2928 return uart_set_options(port, co, baud, parity, bits, flow);
2929 }
2930
2931 static int serial8250_console_early_setup(void)
2932 {
2933 return serial8250_find_port_for_earlycon();
2934 }
2935
2936 static struct console serial8250_console = {
2937 .name = "ttyS",
2938 .write = serial8250_console_write,
2939 .device = uart_console_device,
2940 .setup = serial8250_console_setup,
2941 .early_setup = serial8250_console_early_setup,
2942 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2943 .index = -1,
2944 .data = &serial8250_reg,
2945 };
2946
2947 static int __init serial8250_console_init(void)
2948 {
2949 if (nr_uarts > UART_NR)
2950 nr_uarts = UART_NR;
2951
2952 serial8250_isa_init_ports();
2953 register_console(&serial8250_console);
2954 return 0;
2955 }
2956 console_initcall(serial8250_console_init);
2957
2958 int serial8250_find_port(struct uart_port *p)
2959 {
2960 int line;
2961 struct uart_port *port;
2962
2963 for (line = 0; line < nr_uarts; line++) {
2964 port = &serial8250_ports[line].port;
2965 if (uart_match_port(p, port))
2966 return line;
2967 }
2968 return -ENODEV;
2969 }
2970
2971 #define SERIAL8250_CONSOLE &serial8250_console
2972 #else
2973 #define SERIAL8250_CONSOLE NULL
2974 #endif
2975
2976 static struct uart_driver serial8250_reg = {
2977 .owner = THIS_MODULE,
2978 .driver_name = "serial",
2979 .dev_name = "ttyS",
2980 .major = TTY_MAJOR,
2981 .minor = 64,
2982 .cons = SERIAL8250_CONSOLE,
2983 };
2984
2985 /*
2986 * early_serial_setup - early registration for 8250 ports
2987 *
2988 * Setup an 8250 port structure prior to console initialisation. Use
2989 * after console initialisation will cause undefined behaviour.
2990 */
2991 int __init early_serial_setup(struct uart_port *port)
2992 {
2993 struct uart_port *p;
2994
2995 if (port->line >= ARRAY_SIZE(serial8250_ports))
2996 return -ENODEV;
2997
2998 serial8250_isa_init_ports();
2999 p = &serial8250_ports[port->line].port;
3000 p->iobase = port->iobase;
3001 p->membase = port->membase;
3002 p->irq = port->irq;
3003 p->irqflags = port->irqflags;
3004 p->uartclk = port->uartclk;
3005 p->fifosize = port->fifosize;
3006 p->regshift = port->regshift;
3007 p->iotype = port->iotype;
3008 p->flags = port->flags;
3009 p->mapbase = port->mapbase;
3010 p->private_data = port->private_data;
3011 p->type = port->type;
3012 p->line = port->line;
3013
3014 set_io_from_upio(p);
3015 if (port->serial_in)
3016 p->serial_in = port->serial_in;
3017 if (port->serial_out)
3018 p->serial_out = port->serial_out;
3019 if (port->handle_irq)
3020 p->handle_irq = port->handle_irq;
3021 else
3022 p->handle_irq = serial8250_default_handle_irq;
3023
3024 return 0;
3025 }
3026
3027 /**
3028 * serial8250_suspend_port - suspend one serial port
3029 * @line: serial line number
3030 *
3031 * Suspend one serial port.
3032 */
3033 void serial8250_suspend_port(int line)
3034 {
3035 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3036 }
3037
3038 /**
3039 * serial8250_resume_port - resume one serial port
3040 * @line: serial line number
3041 *
3042 * Resume one serial port.
3043 */
3044 void serial8250_resume_port(int line)
3045 {
3046 struct uart_8250_port *up = &serial8250_ports[line];
3047
3048 if (up->capabilities & UART_NATSEMI) {
3049 /* Ensure it's still in high speed mode */
3050 serial_outp(up, UART_LCR, 0xE0);
3051
3052 ns16550a_goto_highspeed(up);
3053
3054 serial_outp(up, UART_LCR, 0);
3055 up->port.uartclk = 921600*16;
3056 }
3057 uart_resume_port(&serial8250_reg, &up->port);
3058 }
3059
3060 /*
3061 * Register a set of serial devices attached to a platform device. The
3062 * list is terminated with a zero flags entry, which means we expect
3063 * all entries to have at least UPF_BOOT_AUTOCONF set.
3064 */
3065 static int __devinit serial8250_probe(struct platform_device *dev)
3066 {
3067 struct plat_serial8250_port *p = dev->dev.platform_data;
3068 struct uart_port port;
3069 int ret, i, irqflag = 0;
3070
3071 memset(&port, 0, sizeof(struct uart_port));
3072
3073 if (share_irqs)
3074 irqflag = IRQF_SHARED;
3075
3076 for (i = 0; p && p->flags != 0; p++, i++) {
3077 port.iobase = p->iobase;
3078 port.membase = p->membase;
3079 port.irq = p->irq;
3080 port.irqflags = p->irqflags;
3081 port.uartclk = p->uartclk;
3082 port.regshift = p->regshift;
3083 port.iotype = p->iotype;
3084 port.flags = p->flags;
3085 port.mapbase = p->mapbase;
3086 port.hub6 = p->hub6;
3087 port.private_data = p->private_data;
3088 port.type = p->type;
3089 port.serial_in = p->serial_in;
3090 port.serial_out = p->serial_out;
3091 port.handle_irq = p->handle_irq;
3092 port.set_termios = p->set_termios;
3093 port.pm = p->pm;
3094 port.dev = &dev->dev;
3095 port.irqflags |= irqflag;
3096 ret = serial8250_register_port(&port);
3097 if (ret < 0) {
3098 dev_err(&dev->dev, "unable to register port at index %d "
3099 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3100 p->iobase, (unsigned long long)p->mapbase,
3101 p->irq, ret);
3102 }
3103 }
3104 return 0;
3105 }
3106
3107 /*
3108 * Remove serial ports registered against a platform device.
3109 */
3110 static int __devexit serial8250_remove(struct platform_device *dev)
3111 {
3112 int i;
3113
3114 for (i = 0; i < nr_uarts; i++) {
3115 struct uart_8250_port *up = &serial8250_ports[i];
3116
3117 if (up->port.dev == &dev->dev)
3118 serial8250_unregister_port(i);
3119 }
3120 return 0;
3121 }
3122
3123 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3124 {
3125 int i;
3126
3127 for (i = 0; i < UART_NR; i++) {
3128 struct uart_8250_port *up = &serial8250_ports[i];
3129
3130 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3131 uart_suspend_port(&serial8250_reg, &up->port);
3132 }
3133
3134 return 0;
3135 }
3136
3137 static int serial8250_resume(struct platform_device *dev)
3138 {
3139 int i;
3140
3141 for (i = 0; i < UART_NR; i++) {
3142 struct uart_8250_port *up = &serial8250_ports[i];
3143
3144 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3145 serial8250_resume_port(i);
3146 }
3147
3148 return 0;
3149 }
3150
3151 static struct platform_driver serial8250_isa_driver = {
3152 .probe = serial8250_probe,
3153 .remove = __devexit_p(serial8250_remove),
3154 .suspend = serial8250_suspend,
3155 .resume = serial8250_resume,
3156 .driver = {
3157 .name = "serial8250",
3158 .owner = THIS_MODULE,
3159 },
3160 };
3161
3162 /*
3163 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3164 * in the table in include/asm/serial.h
3165 */
3166 static struct platform_device *serial8250_isa_devs;
3167
3168 /*
3169 * serial8250_register_port and serial8250_unregister_port allows for
3170 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3171 * modems and PCI multiport cards.
3172 */
3173 static DEFINE_MUTEX(serial_mutex);
3174
3175 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3176 {
3177 int i;
3178
3179 /*
3180 * First, find a port entry which matches.
3181 */
3182 for (i = 0; i < nr_uarts; i++)
3183 if (uart_match_port(&serial8250_ports[i].port, port))
3184 return &serial8250_ports[i];
3185
3186 /*
3187 * We didn't find a matching entry, so look for the first
3188 * free entry. We look for one which hasn't been previously
3189 * used (indicated by zero iobase).
3190 */
3191 for (i = 0; i < nr_uarts; i++)
3192 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3193 serial8250_ports[i].port.iobase == 0)
3194 return &serial8250_ports[i];
3195
3196 /*
3197 * That also failed. Last resort is to find any entry which
3198 * doesn't have a real port associated with it.
3199 */
3200 for (i = 0; i < nr_uarts; i++)
3201 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3202 return &serial8250_ports[i];
3203
3204 return NULL;
3205 }
3206
3207 /**
3208 * serial8250_register_port - register a serial port
3209 * @port: serial port template
3210 *
3211 * Configure the serial port specified by the request. If the
3212 * port exists and is in use, it is hung up and unregistered
3213 * first.
3214 *
3215 * The port is then probed and if necessary the IRQ is autodetected
3216 * If this fails an error is returned.
3217 *
3218 * On success the port is ready to use and the line number is returned.
3219 */
3220 int serial8250_register_port(struct uart_port *port)
3221 {
3222 struct uart_8250_port *uart;
3223 int ret = -ENOSPC;
3224
3225 if (port->uartclk == 0)
3226 return -EINVAL;
3227
3228 mutex_lock(&serial_mutex);
3229
3230 uart = serial8250_find_match_or_unused(port);
3231 if (uart) {
3232 uart_remove_one_port(&serial8250_reg, &uart->port);
3233
3234 uart->port.iobase = port->iobase;
3235 uart->port.membase = port->membase;
3236 uart->port.irq = port->irq;
3237 uart->port.irqflags = port->irqflags;
3238 uart->port.uartclk = port->uartclk;
3239 uart->port.fifosize = port->fifosize;
3240 uart->port.regshift = port->regshift;
3241 uart->port.iotype = port->iotype;
3242 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3243 uart->port.mapbase = port->mapbase;
3244 uart->port.private_data = port->private_data;
3245 if (port->dev)
3246 uart->port.dev = port->dev;
3247
3248 if (port->flags & UPF_FIXED_TYPE)
3249 serial8250_init_fixed_type_port(uart, port->type);
3250
3251 set_io_from_upio(&uart->port);
3252 /* Possibly override default I/O functions. */
3253 if (port->serial_in)
3254 uart->port.serial_in = port->serial_in;
3255 if (port->serial_out)
3256 uart->port.serial_out = port->serial_out;
3257 if (port->handle_irq)
3258 uart->port.handle_irq = port->handle_irq;
3259 /* Possibly override set_termios call */
3260 if (port->set_termios)
3261 uart->port.set_termios = port->set_termios;
3262 if (port->pm)
3263 uart->port.pm = port->pm;
3264
3265 if (serial8250_isa_config != NULL)
3266 serial8250_isa_config(0, &uart->port,
3267 &uart->capabilities);
3268
3269 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3270 if (ret == 0)
3271 ret = uart->port.line;
3272 }
3273 mutex_unlock(&serial_mutex);
3274
3275 return ret;
3276 }
3277 EXPORT_SYMBOL(serial8250_register_port);
3278
3279 /**
3280 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3281 * @line: serial line number
3282 *
3283 * Remove one serial port. This may not be called from interrupt
3284 * context. We hand the port back to the our control.
3285 */
3286 void serial8250_unregister_port(int line)
3287 {
3288 struct uart_8250_port *uart = &serial8250_ports[line];
3289
3290 mutex_lock(&serial_mutex);
3291 uart_remove_one_port(&serial8250_reg, &uart->port);
3292 if (serial8250_isa_devs) {
3293 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3294 uart->port.type = PORT_UNKNOWN;
3295 uart->port.dev = &serial8250_isa_devs->dev;
3296 uart->capabilities = uart_config[uart->port.type].flags;
3297 uart_add_one_port(&serial8250_reg, &uart->port);
3298 } else {
3299 uart->port.dev = NULL;
3300 }
3301 mutex_unlock(&serial_mutex);
3302 }
3303 EXPORT_SYMBOL(serial8250_unregister_port);
3304
3305 static int __init serial8250_init(void)
3306 {
3307 int ret;
3308
3309 if (nr_uarts > UART_NR)
3310 nr_uarts = UART_NR;
3311
3312 printk(KERN_INFO "Serial: 8250/16550 driver, "
3313 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3314 share_irqs ? "en" : "dis");
3315
3316 #ifdef CONFIG_SPARC
3317 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3318 #else
3319 serial8250_reg.nr = UART_NR;
3320 ret = uart_register_driver(&serial8250_reg);
3321 #endif
3322 if (ret)
3323 goto out;
3324
3325 serial8250_isa_devs = platform_device_alloc("serial8250",
3326 PLAT8250_DEV_LEGACY);
3327 if (!serial8250_isa_devs) {
3328 ret = -ENOMEM;
3329 goto unreg_uart_drv;
3330 }
3331
3332 ret = platform_device_add(serial8250_isa_devs);
3333 if (ret)
3334 goto put_dev;
3335
3336 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3337
3338 ret = platform_driver_register(&serial8250_isa_driver);
3339 if (ret == 0)
3340 goto out;
3341
3342 platform_device_del(serial8250_isa_devs);
3343 put_dev:
3344 platform_device_put(serial8250_isa_devs);
3345 unreg_uart_drv:
3346 #ifdef CONFIG_SPARC
3347 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3348 #else
3349 uart_unregister_driver(&serial8250_reg);
3350 #endif
3351 out:
3352 return ret;
3353 }
3354
3355 static void __exit serial8250_exit(void)
3356 {
3357 struct platform_device *isa_dev = serial8250_isa_devs;
3358
3359 /*
3360 * This tells serial8250_unregister_port() not to re-register
3361 * the ports (thereby making serial8250_isa_driver permanently
3362 * in use.)
3363 */
3364 serial8250_isa_devs = NULL;
3365
3366 platform_driver_unregister(&serial8250_isa_driver);
3367 platform_device_unregister(isa_dev);
3368
3369 #ifdef CONFIG_SPARC
3370 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3371 #else
3372 uart_unregister_driver(&serial8250_reg);
3373 #endif
3374 }
3375
3376 module_init(serial8250_init);
3377 module_exit(serial8250_exit);
3378
3379 EXPORT_SYMBOL(serial8250_suspend_port);
3380 EXPORT_SYMBOL(serial8250_resume_port);
3381
3382 MODULE_LICENSE("GPL");
3383 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3384
3385 module_param(share_irqs, uint, 0644);
3386 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3387 " (unsafe)");
3388
3389 module_param(nr_uarts, uint, 0644);
3390 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3391
3392 module_param(skip_txen_test, uint, 0644);
3393 MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3394
3395 #ifdef CONFIG_SERIAL_8250_RSA
3396 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3397 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3398 #endif
3399 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
Linux kernel - Deliverables
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