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05c15ec7bd217a6936852a1eddb31240693b3599
[deliverable/linux.git] / drivers / tty / serial / amba-pl011.c
1 /*
2 * Driver for AMBA serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 * Copyright (C) 2010 ST-Ericsson SA
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * This is a generic driver for ARM AMBA-type serial ports. They
25 * have a lot of 16550-like features, but are not register compatible.
26 * Note that although they do have CTS, DCD and DSR inputs, they do
27 * not have an RI input, nor do they have DTR or RTS outputs. If
28 * required, these have to be supplied via some other means (eg, GPIO)
29 * and hooked into this driver.
30 */
31
32 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
33 #define SUPPORT_SYSRQ
34 #endif
35
36 #include <linux/module.h>
37 #include <linux/ioport.h>
38 #include <linux/init.h>
39 #include <linux/console.h>
40 #include <linux/sysrq.h>
41 #include <linux/device.h>
42 #include <linux/tty.h>
43 #include <linux/tty_flip.h>
44 #include <linux/serial_core.h>
45 #include <linux/serial.h>
46 #include <linux/amba/bus.h>
47 #include <linux/amba/serial.h>
48 #include <linux/clk.h>
49 #include <linux/slab.h>
50 #include <linux/dmaengine.h>
51 #include <linux/dma-mapping.h>
52 #include <linux/scatterlist.h>
53 #include <linux/delay.h>
54 #include <linux/types.h>
55 #include <linux/of.h>
56 #include <linux/of_device.h>
57 #include <linux/pinctrl/consumer.h>
58 #include <linux/sizes.h>
59
60 #include <asm/io.h>
61
62 #define UART_NR 14
63
64 #define SERIAL_AMBA_MAJOR 204
65 #define SERIAL_AMBA_MINOR 64
66 #define SERIAL_AMBA_NR UART_NR
67
68 #define AMBA_ISR_PASS_LIMIT 256
69
70 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
71 #define UART_DUMMY_DR_RX (1 << 16)
72
73 /* There is by now at least one vendor with differing details, so handle it */
74 struct vendor_data {
75 unsigned int ifls;
76 unsigned int fifosize;
77 unsigned int lcrh_tx;
78 unsigned int lcrh_rx;
79 bool oversampling;
80 bool interrupt_may_hang; /* vendor-specific */
81 bool dma_threshold;
82 bool cts_event_workaround;
83 };
84
85 static struct vendor_data vendor_arm = {
86 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
87 .fifosize = 16,
88 .lcrh_tx = UART011_LCRH,
89 .lcrh_rx = UART011_LCRH,
90 .oversampling = false,
91 .dma_threshold = false,
92 .cts_event_workaround = false,
93 };
94
95 static struct vendor_data vendor_st = {
96 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
97 .fifosize = 64,
98 .lcrh_tx = ST_UART011_LCRH_TX,
99 .lcrh_rx = ST_UART011_LCRH_RX,
100 .oversampling = true,
101 .interrupt_may_hang = true,
102 .dma_threshold = true,
103 .cts_event_workaround = true,
104 };
105
106 static struct uart_amba_port *amba_ports[UART_NR];
107
108 /* Deals with DMA transactions */
109
110 struct pl011_sgbuf {
111 struct scatterlist sg;
112 char *buf;
113 };
114
115 struct pl011_dmarx_data {
116 struct dma_chan *chan;
117 struct completion complete;
118 bool use_buf_b;
119 struct pl011_sgbuf sgbuf_a;
120 struct pl011_sgbuf sgbuf_b;
121 dma_cookie_t cookie;
122 bool running;
123 };
124
125 struct pl011_dmatx_data {
126 struct dma_chan *chan;
127 struct scatterlist sg;
128 char *buf;
129 bool queued;
130 };
131
132 /*
133 * We wrap our port structure around the generic uart_port.
134 */
135 struct uart_amba_port {
136 struct uart_port port;
137 struct clk *clk;
138 /* Two optional pin states - default & sleep */
139 struct pinctrl *pinctrl;
140 struct pinctrl_state *pins_default;
141 struct pinctrl_state *pins_sleep;
142 const struct vendor_data *vendor;
143 unsigned int dmacr; /* dma control reg */
144 unsigned int im; /* interrupt mask */
145 unsigned int old_status;
146 unsigned int fifosize; /* vendor-specific */
147 unsigned int lcrh_tx; /* vendor-specific */
148 unsigned int lcrh_rx; /* vendor-specific */
149 unsigned int old_cr; /* state during shutdown */
150 bool autorts;
151 char type[12];
152 bool interrupt_may_hang; /* vendor-specific */
153 #ifdef CONFIG_DMA_ENGINE
154 /* DMA stuff */
155 bool using_tx_dma;
156 bool using_rx_dma;
157 struct pl011_dmarx_data dmarx;
158 struct pl011_dmatx_data dmatx;
159 #endif
160 };
161
162 /*
163 * Reads up to 256 characters from the FIFO or until it's empty and
164 * inserts them into the TTY layer. Returns the number of characters
165 * read from the FIFO.
166 */
167 static int pl011_fifo_to_tty(struct uart_amba_port *uap)
168 {
169 u16 status, ch;
170 unsigned int flag, max_count = 256;
171 int fifotaken = 0;
172
173 while (max_count--) {
174 status = readw(uap->port.membase + UART01x_FR);
175 if (status & UART01x_FR_RXFE)
176 break;
177
178 /* Take chars from the FIFO and update status */
179 ch = readw(uap->port.membase + UART01x_DR) |
180 UART_DUMMY_DR_RX;
181 flag = TTY_NORMAL;
182 uap->port.icount.rx++;
183 fifotaken++;
184
185 if (unlikely(ch & UART_DR_ERROR)) {
186 if (ch & UART011_DR_BE) {
187 ch &= ~(UART011_DR_FE | UART011_DR_PE);
188 uap->port.icount.brk++;
189 if (uart_handle_break(&uap->port))
190 continue;
191 } else if (ch & UART011_DR_PE)
192 uap->port.icount.parity++;
193 else if (ch & UART011_DR_FE)
194 uap->port.icount.frame++;
195 if (ch & UART011_DR_OE)
196 uap->port.icount.overrun++;
197
198 ch &= uap->port.read_status_mask;
199
200 if (ch & UART011_DR_BE)
201 flag = TTY_BREAK;
202 else if (ch & UART011_DR_PE)
203 flag = TTY_PARITY;
204 else if (ch & UART011_DR_FE)
205 flag = TTY_FRAME;
206 }
207
208 if (uart_handle_sysrq_char(&uap->port, ch & 255))
209 continue;
210
211 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
212 }
213
214 return fifotaken;
215 }
216
217
218 /*
219 * All the DMA operation mode stuff goes inside this ifdef.
220 * This assumes that you have a generic DMA device interface,
221 * no custom DMA interfaces are supported.
222 */
223 #ifdef CONFIG_DMA_ENGINE
224
225 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE
226
227 static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
228 enum dma_data_direction dir)
229 {
230 sg->buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL);
231 if (!sg->buf)
232 return -ENOMEM;
233
234 sg_init_one(&sg->sg, sg->buf, PL011_DMA_BUFFER_SIZE);
235
236 if (dma_map_sg(chan->device->dev, &sg->sg, 1, dir) != 1) {
237 kfree(sg->buf);
238 return -EINVAL;
239 }
240 return 0;
241 }
242
243 static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
244 enum dma_data_direction dir)
245 {
246 if (sg->buf) {
247 dma_unmap_sg(chan->device->dev, &sg->sg, 1, dir);
248 kfree(sg->buf);
249 }
250 }
251
252 static void pl011_dma_probe_initcall(struct uart_amba_port *uap)
253 {
254 /* DMA is the sole user of the platform data right now */
255 struct amba_pl011_data *plat = uap->port.dev->platform_data;
256 struct dma_slave_config tx_conf = {
257 .dst_addr = uap->port.mapbase + UART01x_DR,
258 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
259 .direction = DMA_MEM_TO_DEV,
260 .dst_maxburst = uap->fifosize >> 1,
261 .device_fc = false,
262 };
263 struct dma_chan *chan;
264 dma_cap_mask_t mask;
265
266 /* We need platform data */
267 if (!plat || !plat->dma_filter) {
268 dev_info(uap->port.dev, "no DMA platform data\n");
269 return;
270 }
271
272 /* Try to acquire a generic DMA engine slave TX channel */
273 dma_cap_zero(mask);
274 dma_cap_set(DMA_SLAVE, mask);
275
276 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_tx_param);
277 if (!chan) {
278 dev_err(uap->port.dev, "no TX DMA channel!\n");
279 return;
280 }
281
282 dmaengine_slave_config(chan, &tx_conf);
283 uap->dmatx.chan = chan;
284
285 dev_info(uap->port.dev, "DMA channel TX %s\n",
286 dma_chan_name(uap->dmatx.chan));
287
288 /* Optionally make use of an RX channel as well */
289 if (plat->dma_rx_param) {
290 struct dma_slave_config rx_conf = {
291 .src_addr = uap->port.mapbase + UART01x_DR,
292 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
293 .direction = DMA_DEV_TO_MEM,
294 .src_maxburst = uap->fifosize >> 1,
295 .device_fc = false,
296 };
297
298 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
299 if (!chan) {
300 dev_err(uap->port.dev, "no RX DMA channel!\n");
301 return;
302 }
303
304 dmaengine_slave_config(chan, &rx_conf);
305 uap->dmarx.chan = chan;
306
307 dev_info(uap->port.dev, "DMA channel RX %s\n",
308 dma_chan_name(uap->dmarx.chan));
309 }
310 }
311
312 #ifndef MODULE
313 /*
314 * Stack up the UARTs and let the above initcall be done at device
315 * initcall time, because the serial driver is called as an arch
316 * initcall, and at this time the DMA subsystem is not yet registered.
317 * At this point the driver will switch over to using DMA where desired.
318 */
319 struct dma_uap {
320 struct list_head node;
321 struct uart_amba_port *uap;
322 };
323
324 static LIST_HEAD(pl011_dma_uarts);
325
326 static int __init pl011_dma_initcall(void)
327 {
328 struct list_head *node, *tmp;
329
330 list_for_each_safe(node, tmp, &pl011_dma_uarts) {
331 struct dma_uap *dmau = list_entry(node, struct dma_uap, node);
332 pl011_dma_probe_initcall(dmau->uap);
333 list_del(node);
334 kfree(dmau);
335 }
336 return 0;
337 }
338
339 device_initcall(pl011_dma_initcall);
340
341 static void pl011_dma_probe(struct uart_amba_port *uap)
342 {
343 struct dma_uap *dmau = kzalloc(sizeof(struct dma_uap), GFP_KERNEL);
344 if (dmau) {
345 dmau->uap = uap;
346 list_add_tail(&dmau->node, &pl011_dma_uarts);
347 }
348 }
349 #else
350 static void pl011_dma_probe(struct uart_amba_port *uap)
351 {
352 pl011_dma_probe_initcall(uap);
353 }
354 #endif
355
356 static void pl011_dma_remove(struct uart_amba_port *uap)
357 {
358 /* TODO: remove the initcall if it has not yet executed */
359 if (uap->dmatx.chan)
360 dma_release_channel(uap->dmatx.chan);
361 if (uap->dmarx.chan)
362 dma_release_channel(uap->dmarx.chan);
363 }
364
365 /* Forward declare this for the refill routine */
366 static int pl011_dma_tx_refill(struct uart_amba_port *uap);
367
368 /*
369 * The current DMA TX buffer has been sent.
370 * Try to queue up another DMA buffer.
371 */
372 static void pl011_dma_tx_callback(void *data)
373 {
374 struct uart_amba_port *uap = data;
375 struct pl011_dmatx_data *dmatx = &uap->dmatx;
376 unsigned long flags;
377 u16 dmacr;
378
379 spin_lock_irqsave(&uap->port.lock, flags);
380 if (uap->dmatx.queued)
381 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
382 DMA_TO_DEVICE);
383
384 dmacr = uap->dmacr;
385 uap->dmacr = dmacr & ~UART011_TXDMAE;
386 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
387
388 /*
389 * If TX DMA was disabled, it means that we've stopped the DMA for
390 * some reason (eg, XOFF received, or we want to send an X-char.)
391 *
392 * Note: we need to be careful here of a potential race between DMA
393 * and the rest of the driver - if the driver disables TX DMA while
394 * a TX buffer completing, we must update the tx queued status to
395 * get further refills (hence we check dmacr).
396 */
397 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
398 uart_circ_empty(&uap->port.state->xmit)) {
399 uap->dmatx.queued = false;
400 spin_unlock_irqrestore(&uap->port.lock, flags);
401 return;
402 }
403
404 if (pl011_dma_tx_refill(uap) <= 0) {
405 /*
406 * We didn't queue a DMA buffer for some reason, but we
407 * have data pending to be sent. Re-enable the TX IRQ.
408 */
409 uap->im |= UART011_TXIM;
410 writew(uap->im, uap->port.membase + UART011_IMSC);
411 }
412 spin_unlock_irqrestore(&uap->port.lock, flags);
413 }
414
415 /*
416 * Try to refill the TX DMA buffer.
417 * Locking: called with port lock held and IRQs disabled.
418 * Returns:
419 * 1 if we queued up a TX DMA buffer.
420 * 0 if we didn't want to handle this by DMA
421 * <0 on error
422 */
423 static int pl011_dma_tx_refill(struct uart_amba_port *uap)
424 {
425 struct pl011_dmatx_data *dmatx = &uap->dmatx;
426 struct dma_chan *chan = dmatx->chan;
427 struct dma_device *dma_dev = chan->device;
428 struct dma_async_tx_descriptor *desc;
429 struct circ_buf *xmit = &uap->port.state->xmit;
430 unsigned int count;
431
432 /*
433 * Try to avoid the overhead involved in using DMA if the
434 * transaction fits in the first half of the FIFO, by using
435 * the standard interrupt handling. This ensures that we
436 * issue a uart_write_wakeup() at the appropriate time.
437 */
438 count = uart_circ_chars_pending(xmit);
439 if (count < (uap->fifosize >> 1)) {
440 uap->dmatx.queued = false;
441 return 0;
442 }
443
444 /*
445 * Bodge: don't send the last character by DMA, as this
446 * will prevent XON from notifying us to restart DMA.
447 */
448 count -= 1;
449
450 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
451 if (count > PL011_DMA_BUFFER_SIZE)
452 count = PL011_DMA_BUFFER_SIZE;
453
454 if (xmit->tail < xmit->head)
455 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
456 else {
457 size_t first = UART_XMIT_SIZE - xmit->tail;
458 size_t second = xmit->head;
459
460 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
461 if (second)
462 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
463 }
464
465 dmatx->sg.length = count;
466
467 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
468 uap->dmatx.queued = false;
469 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
470 return -EBUSY;
471 }
472
473 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
474 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
475 if (!desc) {
476 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
477 uap->dmatx.queued = false;
478 /*
479 * If DMA cannot be used right now, we complete this
480 * transaction via IRQ and let the TTY layer retry.
481 */
482 dev_dbg(uap->port.dev, "TX DMA busy\n");
483 return -EBUSY;
484 }
485
486 /* Some data to go along to the callback */
487 desc->callback = pl011_dma_tx_callback;
488 desc->callback_param = uap;
489
490 /* All errors should happen at prepare time */
491 dmaengine_submit(desc);
492
493 /* Fire the DMA transaction */
494 dma_dev->device_issue_pending(chan);
495
496 uap->dmacr |= UART011_TXDMAE;
497 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
498 uap->dmatx.queued = true;
499
500 /*
501 * Now we know that DMA will fire, so advance the ring buffer
502 * with the stuff we just dispatched.
503 */
504 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
505 uap->port.icount.tx += count;
506
507 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
508 uart_write_wakeup(&uap->port);
509
510 return 1;
511 }
512
513 /*
514 * We received a transmit interrupt without a pending X-char but with
515 * pending characters.
516 * Locking: called with port lock held and IRQs disabled.
517 * Returns:
518 * false if we want to use PIO to transmit
519 * true if we queued a DMA buffer
520 */
521 static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
522 {
523 if (!uap->using_tx_dma)
524 return false;
525
526 /*
527 * If we already have a TX buffer queued, but received a
528 * TX interrupt, it will be because we've just sent an X-char.
529 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
530 */
531 if (uap->dmatx.queued) {
532 uap->dmacr |= UART011_TXDMAE;
533 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
534 uap->im &= ~UART011_TXIM;
535 writew(uap->im, uap->port.membase + UART011_IMSC);
536 return true;
537 }
538
539 /*
540 * We don't have a TX buffer queued, so try to queue one.
541 * If we successfully queued a buffer, mask the TX IRQ.
542 */
543 if (pl011_dma_tx_refill(uap) > 0) {
544 uap->im &= ~UART011_TXIM;
545 writew(uap->im, uap->port.membase + UART011_IMSC);
546 return true;
547 }
548 return false;
549 }
550
551 /*
552 * Stop the DMA transmit (eg, due to received XOFF).
553 * Locking: called with port lock held and IRQs disabled.
554 */
555 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
556 {
557 if (uap->dmatx.queued) {
558 uap->dmacr &= ~UART011_TXDMAE;
559 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
560 }
561 }
562
563 /*
564 * Try to start a DMA transmit, or in the case of an XON/OFF
565 * character queued for send, try to get that character out ASAP.
566 * Locking: called with port lock held and IRQs disabled.
567 * Returns:
568 * false if we want the TX IRQ to be enabled
569 * true if we have a buffer queued
570 */
571 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
572 {
573 u16 dmacr;
574
575 if (!uap->using_tx_dma)
576 return false;
577
578 if (!uap->port.x_char) {
579 /* no X-char, try to push chars out in DMA mode */
580 bool ret = true;
581
582 if (!uap->dmatx.queued) {
583 if (pl011_dma_tx_refill(uap) > 0) {
584 uap->im &= ~UART011_TXIM;
585 ret = true;
586 } else {
587 uap->im |= UART011_TXIM;
588 ret = false;
589 }
590 writew(uap->im, uap->port.membase + UART011_IMSC);
591 } else if (!(uap->dmacr & UART011_TXDMAE)) {
592 uap->dmacr |= UART011_TXDMAE;
593 writew(uap->dmacr,
594 uap->port.membase + UART011_DMACR);
595 }
596 return ret;
597 }
598
599 /*
600 * We have an X-char to send. Disable DMA to prevent it loading
601 * the TX fifo, and then see if we can stuff it into the FIFO.
602 */
603 dmacr = uap->dmacr;
604 uap->dmacr &= ~UART011_TXDMAE;
605 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
606
607 if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) {
608 /*
609 * No space in the FIFO, so enable the transmit interrupt
610 * so we know when there is space. Note that once we've
611 * loaded the character, we should just re-enable DMA.
612 */
613 return false;
614 }
615
616 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
617 uap->port.icount.tx++;
618 uap->port.x_char = 0;
619
620 /* Success - restore the DMA state */
621 uap->dmacr = dmacr;
622 writew(dmacr, uap->port.membase + UART011_DMACR);
623
624 return true;
625 }
626
627 /*
628 * Flush the transmit buffer.
629 * Locking: called with port lock held and IRQs disabled.
630 */
631 static void pl011_dma_flush_buffer(struct uart_port *port)
632 {
633 struct uart_amba_port *uap = (struct uart_amba_port *)port;
634
635 if (!uap->using_tx_dma)
636 return;
637
638 /* Avoid deadlock with the DMA engine callback */
639 spin_unlock(&uap->port.lock);
640 dmaengine_terminate_all(uap->dmatx.chan);
641 spin_lock(&uap->port.lock);
642 if (uap->dmatx.queued) {
643 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
644 DMA_TO_DEVICE);
645 uap->dmatx.queued = false;
646 uap->dmacr &= ~UART011_TXDMAE;
647 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
648 }
649 }
650
651 static void pl011_dma_rx_callback(void *data);
652
653 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
654 {
655 struct dma_chan *rxchan = uap->dmarx.chan;
656 struct pl011_dmarx_data *dmarx = &uap->dmarx;
657 struct dma_async_tx_descriptor *desc;
658 struct pl011_sgbuf *sgbuf;
659
660 if (!rxchan)
661 return -EIO;
662
663 /* Start the RX DMA job */
664 sgbuf = uap->dmarx.use_buf_b ?
665 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
666 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
667 DMA_DEV_TO_MEM,
668 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
669 /*
670 * If the DMA engine is busy and cannot prepare a
671 * channel, no big deal, the driver will fall back
672 * to interrupt mode as a result of this error code.
673 */
674 if (!desc) {
675 uap->dmarx.running = false;
676 dmaengine_terminate_all(rxchan);
677 return -EBUSY;
678 }
679
680 /* Some data to go along to the callback */
681 desc->callback = pl011_dma_rx_callback;
682 desc->callback_param = uap;
683 dmarx->cookie = dmaengine_submit(desc);
684 dma_async_issue_pending(rxchan);
685
686 uap->dmacr |= UART011_RXDMAE;
687 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
688 uap->dmarx.running = true;
689
690 uap->im &= ~UART011_RXIM;
691 writew(uap->im, uap->port.membase + UART011_IMSC);
692
693 return 0;
694 }
695
696 /*
697 * This is called when either the DMA job is complete, or
698 * the FIFO timeout interrupt occurred. This must be called
699 * with the port spinlock uap->port.lock held.
700 */
701 static void pl011_dma_rx_chars(struct uart_amba_port *uap,
702 u32 pending, bool use_buf_b,
703 bool readfifo)
704 {
705 struct tty_struct *tty = uap->port.state->port.tty;
706 struct pl011_sgbuf *sgbuf = use_buf_b ?
707 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
708 struct device *dev = uap->dmarx.chan->device->dev;
709 int dma_count = 0;
710 u32 fifotaken = 0; /* only used for vdbg() */
711
712 /* Pick everything from the DMA first */
713 if (pending) {
714 /* Sync in buffer */
715 dma_sync_sg_for_cpu(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
716
717 /*
718 * First take all chars in the DMA pipe, then look in the FIFO.
719 * Note that tty_insert_flip_buf() tries to take as many chars
720 * as it can.
721 */
722 dma_count = tty_insert_flip_string(uap->port.state->port.tty,
723 sgbuf->buf, pending);
724
725 /* Return buffer to device */
726 dma_sync_sg_for_device(dev, &sgbuf->sg, 1, DMA_FROM_DEVICE);
727
728 uap->port.icount.rx += dma_count;
729 if (dma_count < pending)
730 dev_warn(uap->port.dev,
731 "couldn't insert all characters (TTY is full?)\n");
732 }
733
734 /*
735 * Only continue with trying to read the FIFO if all DMA chars have
736 * been taken first.
737 */
738 if (dma_count == pending && readfifo) {
739 /* Clear any error flags */
740 writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
741 uap->port.membase + UART011_ICR);
742
743 /*
744 * If we read all the DMA'd characters, and we had an
745 * incomplete buffer, that could be due to an rx error, or
746 * maybe we just timed out. Read any pending chars and check
747 * the error status.
748 *
749 * Error conditions will only occur in the FIFO, these will
750 * trigger an immediate interrupt and stop the DMA job, so we
751 * will always find the error in the FIFO, never in the DMA
752 * buffer.
753 */
754 fifotaken = pl011_fifo_to_tty(uap);
755 }
756
757 spin_unlock(&uap->port.lock);
758 dev_vdbg(uap->port.dev,
759 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
760 dma_count, fifotaken);
761 tty_flip_buffer_push(tty);
762 spin_lock(&uap->port.lock);
763 }
764
765 static void pl011_dma_rx_irq(struct uart_amba_port *uap)
766 {
767 struct pl011_dmarx_data *dmarx = &uap->dmarx;
768 struct dma_chan *rxchan = dmarx->chan;
769 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
770 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
771 size_t pending;
772 struct dma_tx_state state;
773 enum dma_status dmastat;
774
775 /*
776 * Pause the transfer so we can trust the current counter,
777 * do this before we pause the PL011 block, else we may
778 * overflow the FIFO.
779 */
780 if (dmaengine_pause(rxchan))
781 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
782 dmastat = rxchan->device->device_tx_status(rxchan,
783 dmarx->cookie, &state);
784 if (dmastat != DMA_PAUSED)
785 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
786
787 /* Disable RX DMA - incoming data will wait in the FIFO */
788 uap->dmacr &= ~UART011_RXDMAE;
789 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
790 uap->dmarx.running = false;
791
792 pending = sgbuf->sg.length - state.residue;
793 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
794 /* Then we terminate the transfer - we now know our residue */
795 dmaengine_terminate_all(rxchan);
796
797 /*
798 * This will take the chars we have so far and insert
799 * into the framework.
800 */
801 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
802
803 /* Switch buffer & re-trigger DMA job */
804 dmarx->use_buf_b = !dmarx->use_buf_b;
805 if (pl011_dma_rx_trigger_dma(uap)) {
806 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
807 "fall back to interrupt mode\n");
808 uap->im |= UART011_RXIM;
809 writew(uap->im, uap->port.membase + UART011_IMSC);
810 }
811 }
812
813 static void pl011_dma_rx_callback(void *data)
814 {
815 struct uart_amba_port *uap = data;
816 struct pl011_dmarx_data *dmarx = &uap->dmarx;
817 struct dma_chan *rxchan = dmarx->chan;
818 bool lastbuf = dmarx->use_buf_b;
819 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
820 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
821 size_t pending;
822 struct dma_tx_state state;
823 int ret;
824
825 /*
826 * This completion interrupt occurs typically when the
827 * RX buffer is totally stuffed but no timeout has yet
828 * occurred. When that happens, we just want the RX
829 * routine to flush out the secondary DMA buffer while
830 * we immediately trigger the next DMA job.
831 */
832 spin_lock_irq(&uap->port.lock);
833 /*
834 * Rx data can be taken by the UART interrupts during
835 * the DMA irq handler. So we check the residue here.
836 */
837 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
838 pending = sgbuf->sg.length - state.residue;
839 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
840 /* Then we terminate the transfer - we now know our residue */
841 dmaengine_terminate_all(rxchan);
842
843 uap->dmarx.running = false;
844 dmarx->use_buf_b = !lastbuf;
845 ret = pl011_dma_rx_trigger_dma(uap);
846
847 pl011_dma_rx_chars(uap, pending, lastbuf, false);
848 spin_unlock_irq(&uap->port.lock);
849 /*
850 * Do this check after we picked the DMA chars so we don't
851 * get some IRQ immediately from RX.
852 */
853 if (ret) {
854 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
855 "fall back to interrupt mode\n");
856 uap->im |= UART011_RXIM;
857 writew(uap->im, uap->port.membase + UART011_IMSC);
858 }
859 }
860
861 /*
862 * Stop accepting received characters, when we're shutting down or
863 * suspending this port.
864 * Locking: called with port lock held and IRQs disabled.
865 */
866 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
867 {
868 /* FIXME. Just disable the DMA enable */
869 uap->dmacr &= ~UART011_RXDMAE;
870 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
871 }
872
873 static void pl011_dma_startup(struct uart_amba_port *uap)
874 {
875 int ret;
876
877 if (!uap->dmatx.chan)
878 return;
879
880 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL);
881 if (!uap->dmatx.buf) {
882 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
883 uap->port.fifosize = uap->fifosize;
884 return;
885 }
886
887 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
888
889 /* The DMA buffer is now the FIFO the TTY subsystem can use */
890 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
891 uap->using_tx_dma = true;
892
893 if (!uap->dmarx.chan)
894 goto skip_rx;
895
896 /* Allocate and map DMA RX buffers */
897 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
898 DMA_FROM_DEVICE);
899 if (ret) {
900 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
901 "RX buffer A", ret);
902 goto skip_rx;
903 }
904
905 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
906 DMA_FROM_DEVICE);
907 if (ret) {
908 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
909 "RX buffer B", ret);
910 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
911 DMA_FROM_DEVICE);
912 goto skip_rx;
913 }
914
915 uap->using_rx_dma = true;
916
917 skip_rx:
918 /* Turn on DMA error (RX/TX will be enabled on demand) */
919 uap->dmacr |= UART011_DMAONERR;
920 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
921
922 /*
923 * ST Micro variants has some specific dma burst threshold
924 * compensation. Set this to 16 bytes, so burst will only
925 * be issued above/below 16 bytes.
926 */
927 if (uap->vendor->dma_threshold)
928 writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
929 uap->port.membase + ST_UART011_DMAWM);
930
931 if (uap->using_rx_dma) {
932 if (pl011_dma_rx_trigger_dma(uap))
933 dev_dbg(uap->port.dev, "could not trigger initial "
934 "RX DMA job, fall back to interrupt mode\n");
935 }
936 }
937
938 static void pl011_dma_shutdown(struct uart_amba_port *uap)
939 {
940 if (!(uap->using_tx_dma || uap->using_rx_dma))
941 return;
942
943 /* Disable RX and TX DMA */
944 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
945 barrier();
946
947 spin_lock_irq(&uap->port.lock);
948 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
949 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
950 spin_unlock_irq(&uap->port.lock);
951
952 if (uap->using_tx_dma) {
953 /* In theory, this should already be done by pl011_dma_flush_buffer */
954 dmaengine_terminate_all(uap->dmatx.chan);
955 if (uap->dmatx.queued) {
956 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
957 DMA_TO_DEVICE);
958 uap->dmatx.queued = false;
959 }
960
961 kfree(uap->dmatx.buf);
962 uap->using_tx_dma = false;
963 }
964
965 if (uap->using_rx_dma) {
966 dmaengine_terminate_all(uap->dmarx.chan);
967 /* Clean up the RX DMA */
968 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
969 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
970 uap->using_rx_dma = false;
971 }
972 }
973
974 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
975 {
976 return uap->using_rx_dma;
977 }
978
979 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
980 {
981 return uap->using_rx_dma && uap->dmarx.running;
982 }
983
984
985 #else
986 /* Blank functions if the DMA engine is not available */
987 static inline void pl011_dma_probe(struct uart_amba_port *uap)
988 {
989 }
990
991 static inline void pl011_dma_remove(struct uart_amba_port *uap)
992 {
993 }
994
995 static inline void pl011_dma_startup(struct uart_amba_port *uap)
996 {
997 }
998
999 static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1000 {
1001 }
1002
1003 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1004 {
1005 return false;
1006 }
1007
1008 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1009 {
1010 }
1011
1012 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1013 {
1014 return false;
1015 }
1016
1017 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1018 {
1019 }
1020
1021 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1022 {
1023 }
1024
1025 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1026 {
1027 return -EIO;
1028 }
1029
1030 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1031 {
1032 return false;
1033 }
1034
1035 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1036 {
1037 return false;
1038 }
1039
1040 #define pl011_dma_flush_buffer NULL
1041 #endif
1042
1043 static void pl011_stop_tx(struct uart_port *port)
1044 {
1045 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1046
1047 uap->im &= ~UART011_TXIM;
1048 writew(uap->im, uap->port.membase + UART011_IMSC);
1049 pl011_dma_tx_stop(uap);
1050 }
1051
1052 static void pl011_start_tx(struct uart_port *port)
1053 {
1054 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1055
1056 if (!pl011_dma_tx_start(uap)) {
1057 uap->im |= UART011_TXIM;
1058 writew(uap->im, uap->port.membase + UART011_IMSC);
1059 }
1060 }
1061
1062 static void pl011_stop_rx(struct uart_port *port)
1063 {
1064 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1065
1066 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1067 UART011_PEIM|UART011_BEIM|UART011_OEIM);
1068 writew(uap->im, uap->port.membase + UART011_IMSC);
1069
1070 pl011_dma_rx_stop(uap);
1071 }
1072
1073 static void pl011_enable_ms(struct uart_port *port)
1074 {
1075 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1076
1077 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1078 writew(uap->im, uap->port.membase + UART011_IMSC);
1079 }
1080
1081 static void pl011_rx_chars(struct uart_amba_port *uap)
1082 {
1083 struct tty_struct *tty = uap->port.state->port.tty;
1084
1085 pl011_fifo_to_tty(uap);
1086
1087 spin_unlock(&uap->port.lock);
1088 tty_flip_buffer_push(tty);
1089 /*
1090 * If we were temporarily out of DMA mode for a while,
1091 * attempt to switch back to DMA mode again.
1092 */
1093 if (pl011_dma_rx_available(uap)) {
1094 if (pl011_dma_rx_trigger_dma(uap)) {
1095 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1096 "fall back to interrupt mode again\n");
1097 uap->im |= UART011_RXIM;
1098 } else
1099 uap->im &= ~UART011_RXIM;
1100 writew(uap->im, uap->port.membase + UART011_IMSC);
1101 }
1102 spin_lock(&uap->port.lock);
1103 }
1104
1105 static void pl011_tx_chars(struct uart_amba_port *uap)
1106 {
1107 struct circ_buf *xmit = &uap->port.state->xmit;
1108 int count;
1109
1110 if (uap->port.x_char) {
1111 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
1112 uap->port.icount.tx++;
1113 uap->port.x_char = 0;
1114 return;
1115 }
1116 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1117 pl011_stop_tx(&uap->port);
1118 return;
1119 }
1120
1121 /* If we are using DMA mode, try to send some characters. */
1122 if (pl011_dma_tx_irq(uap))
1123 return;
1124
1125 count = uap->fifosize >> 1;
1126 do {
1127 writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
1128 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1129 uap->port.icount.tx++;
1130 if (uart_circ_empty(xmit))
1131 break;
1132 } while (--count > 0);
1133
1134 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1135 uart_write_wakeup(&uap->port);
1136
1137 if (uart_circ_empty(xmit))
1138 pl011_stop_tx(&uap->port);
1139 }
1140
1141 static void pl011_modem_status(struct uart_amba_port *uap)
1142 {
1143 unsigned int status, delta;
1144
1145 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
1146
1147 delta = status ^ uap->old_status;
1148 uap->old_status = status;
1149
1150 if (!delta)
1151 return;
1152
1153 if (delta & UART01x_FR_DCD)
1154 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1155
1156 if (delta & UART01x_FR_DSR)
1157 uap->port.icount.dsr++;
1158
1159 if (delta & UART01x_FR_CTS)
1160 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
1161
1162 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1163 }
1164
1165 static irqreturn_t pl011_int(int irq, void *dev_id)
1166 {
1167 struct uart_amba_port *uap = dev_id;
1168 unsigned long flags;
1169 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1170 int handled = 0;
1171 unsigned int dummy_read;
1172
1173 spin_lock_irqsave(&uap->port.lock, flags);
1174
1175 status = readw(uap->port.membase + UART011_MIS);
1176 if (status) {
1177 do {
1178 if (uap->vendor->cts_event_workaround) {
1179 /* workaround to make sure that all bits are unlocked.. */
1180 writew(0x00, uap->port.membase + UART011_ICR);
1181
1182 /*
1183 * WA: introduce 26ns(1 uart clk) delay before W1C;
1184 * single apb access will incur 2 pclk(133.12Mhz) delay,
1185 * so add 2 dummy reads
1186 */
1187 dummy_read = readw(uap->port.membase + UART011_ICR);
1188 dummy_read = readw(uap->port.membase + UART011_ICR);
1189 }
1190
1191 writew(status & ~(UART011_TXIS|UART011_RTIS|
1192 UART011_RXIS),
1193 uap->port.membase + UART011_ICR);
1194
1195 if (status & (UART011_RTIS|UART011_RXIS)) {
1196 if (pl011_dma_rx_running(uap))
1197 pl011_dma_rx_irq(uap);
1198 else
1199 pl011_rx_chars(uap);
1200 }
1201 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1202 UART011_CTSMIS|UART011_RIMIS))
1203 pl011_modem_status(uap);
1204 if (status & UART011_TXIS)
1205 pl011_tx_chars(uap);
1206
1207 if (pass_counter-- == 0)
1208 break;
1209
1210 status = readw(uap->port.membase + UART011_MIS);
1211 } while (status != 0);
1212 handled = 1;
1213 }
1214
1215 spin_unlock_irqrestore(&uap->port.lock, flags);
1216
1217 return IRQ_RETVAL(handled);
1218 }
1219
1220 static unsigned int pl011_tx_empty(struct uart_port *port)
1221 {
1222 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1223 unsigned int status = readw(uap->port.membase + UART01x_FR);
1224 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
1225 }
1226
1227 static unsigned int pl011_get_mctrl(struct uart_port *port)
1228 {
1229 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1230 unsigned int result = 0;
1231 unsigned int status = readw(uap->port.membase + UART01x_FR);
1232
1233 #define TIOCMBIT(uartbit, tiocmbit) \
1234 if (status & uartbit) \
1235 result |= tiocmbit
1236
1237 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1238 TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR);
1239 TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS);
1240 TIOCMBIT(UART011_FR_RI, TIOCM_RNG);
1241 #undef TIOCMBIT
1242 return result;
1243 }
1244
1245 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1246 {
1247 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1248 unsigned int cr;
1249
1250 cr = readw(uap->port.membase + UART011_CR);
1251
1252 #define TIOCMBIT(tiocmbit, uartbit) \
1253 if (mctrl & tiocmbit) \
1254 cr |= uartbit; \
1255 else \
1256 cr &= ~uartbit
1257
1258 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1259 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1260 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1261 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1262 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
1263
1264 if (uap->autorts) {
1265 /* We need to disable auto-RTS if we want to turn RTS off */
1266 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1267 }
1268 #undef TIOCMBIT
1269
1270 writew(cr, uap->port.membase + UART011_CR);
1271 }
1272
1273 static void pl011_break_ctl(struct uart_port *port, int break_state)
1274 {
1275 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1276 unsigned long flags;
1277 unsigned int lcr_h;
1278
1279 spin_lock_irqsave(&uap->port.lock, flags);
1280 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
1281 if (break_state == -1)
1282 lcr_h |= UART01x_LCRH_BRK;
1283 else
1284 lcr_h &= ~UART01x_LCRH_BRK;
1285 writew(lcr_h, uap->port.membase + uap->lcrh_tx);
1286 spin_unlock_irqrestore(&uap->port.lock, flags);
1287 }
1288
1289 #ifdef CONFIG_CONSOLE_POLL
1290 static int pl011_get_poll_char(struct uart_port *port)
1291 {
1292 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1293 unsigned int status;
1294
1295 status = readw(uap->port.membase + UART01x_FR);
1296 if (status & UART01x_FR_RXFE)
1297 return NO_POLL_CHAR;
1298
1299 return readw(uap->port.membase + UART01x_DR);
1300 }
1301
1302 static void pl011_put_poll_char(struct uart_port *port,
1303 unsigned char ch)
1304 {
1305 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1306
1307 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
1308 barrier();
1309
1310 writew(ch, uap->port.membase + UART01x_DR);
1311 }
1312
1313 #endif /* CONFIG_CONSOLE_POLL */
1314
1315 static int pl011_startup(struct uart_port *port)
1316 {
1317 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1318 unsigned int cr;
1319 int retval;
1320
1321 /* Optionaly enable pins to be muxed in and configured */
1322 if (!IS_ERR(uap->pins_default)) {
1323 retval = pinctrl_select_state(uap->pinctrl, uap->pins_default);
1324 if (retval)
1325 dev_err(port->dev,
1326 "could not set default pins\n");
1327 }
1328
1329 /*
1330 * Try to enable the clock producer.
1331 */
1332 retval = clk_prepare_enable(uap->clk);
1333 if (retval)
1334 goto out;
1335
1336 uap->port.uartclk = clk_get_rate(uap->clk);
1337
1338 /* Clear pending error and receive interrupts */
1339 writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS |
1340 UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR);
1341
1342 /*
1343 * Allocate the IRQ
1344 */
1345 retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
1346 if (retval)
1347 goto clk_dis;
1348
1349 writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS);
1350
1351 /*
1352 * Provoke TX FIFO interrupt into asserting.
1353 */
1354 cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE;
1355 writew(cr, uap->port.membase + UART011_CR);
1356 writew(0, uap->port.membase + UART011_FBRD);
1357 writew(1, uap->port.membase + UART011_IBRD);
1358 writew(0, uap->port.membase + uap->lcrh_rx);
1359 if (uap->lcrh_tx != uap->lcrh_rx) {
1360 int i;
1361 /*
1362 * Wait 10 PCLKs before writing LCRH_TX register,
1363 * to get this delay write read only register 10 times
1364 */
1365 for (i = 0; i < 10; ++i)
1366 writew(0xff, uap->port.membase + UART011_MIS);
1367 writew(0, uap->port.membase + uap->lcrh_tx);
1368 }
1369 writew(0, uap->port.membase + UART01x_DR);
1370 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
1371 barrier();
1372
1373 /* restore RTS and DTR */
1374 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
1375 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
1376 writew(cr, uap->port.membase + UART011_CR);
1377
1378 /*
1379 * initialise the old status of the modem signals
1380 */
1381 uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
1382
1383 /* Startup DMA */
1384 pl011_dma_startup(uap);
1385
1386 /*
1387 * Finally, enable interrupts, only timeouts when using DMA
1388 * if initial RX DMA job failed, start in interrupt mode
1389 * as well.
1390 */
1391 spin_lock_irq(&uap->port.lock);
1392 /* Clear out any spuriously appearing RX interrupts */
1393 writew(UART011_RTIS | UART011_RXIS,
1394 uap->port.membase + UART011_ICR);
1395 uap->im = UART011_RTIM;
1396 if (!pl011_dma_rx_running(uap))
1397 uap->im |= UART011_RXIM;
1398 writew(uap->im, uap->port.membase + UART011_IMSC);
1399 spin_unlock_irq(&uap->port.lock);
1400
1401 if (uap->port.dev->platform_data) {
1402 struct amba_pl011_data *plat;
1403
1404 plat = uap->port.dev->platform_data;
1405 if (plat->init)
1406 plat->init();
1407 }
1408
1409 return 0;
1410
1411 clk_dis:
1412 clk_disable_unprepare(uap->clk);
1413 out:
1414 return retval;
1415 }
1416
1417 static void pl011_shutdown_channel(struct uart_amba_port *uap,
1418 unsigned int lcrh)
1419 {
1420 unsigned long val;
1421
1422 val = readw(uap->port.membase + lcrh);
1423 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1424 writew(val, uap->port.membase + lcrh);
1425 }
1426
1427 static void pl011_shutdown(struct uart_port *port)
1428 {
1429 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1430 unsigned int cr;
1431 int retval;
1432
1433 /*
1434 * disable all interrupts
1435 */
1436 spin_lock_irq(&uap->port.lock);
1437 uap->im = 0;
1438 writew(uap->im, uap->port.membase + UART011_IMSC);
1439 writew(0xffff, uap->port.membase + UART011_ICR);
1440 spin_unlock_irq(&uap->port.lock);
1441
1442 pl011_dma_shutdown(uap);
1443
1444 /*
1445 * Free the interrupt
1446 */
1447 free_irq(uap->port.irq, uap);
1448
1449 /*
1450 * disable the port
1451 * disable the port. It should not disable RTS and DTR.
1452 * Also RTS and DTR state should be preserved to restore
1453 * it during startup().
1454 */
1455 uap->autorts = false;
1456 cr = readw(uap->port.membase + UART011_CR);
1457 uap->old_cr = cr;
1458 cr &= UART011_CR_RTS | UART011_CR_DTR;
1459 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1460 writew(cr, uap->port.membase + UART011_CR);
1461
1462 /*
1463 * disable break condition and fifos
1464 */
1465 pl011_shutdown_channel(uap, uap->lcrh_rx);
1466 if (uap->lcrh_rx != uap->lcrh_tx)
1467 pl011_shutdown_channel(uap, uap->lcrh_tx);
1468
1469 /*
1470 * Shut down the clock producer
1471 */
1472 clk_disable_unprepare(uap->clk);
1473 /* Optionally let pins go into sleep states */
1474 if (!IS_ERR(uap->pins_sleep)) {
1475 retval = pinctrl_select_state(uap->pinctrl, uap->pins_sleep);
1476 if (retval)
1477 dev_err(port->dev,
1478 "could not set pins to sleep state\n");
1479 }
1480
1481
1482 if (uap->port.dev->platform_data) {
1483 struct amba_pl011_data *plat;
1484
1485 plat = uap->port.dev->platform_data;
1486 if (plat->exit)
1487 plat->exit();
1488 }
1489
1490 }
1491
1492 static void
1493 pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1494 struct ktermios *old)
1495 {
1496 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1497 unsigned int lcr_h, old_cr;
1498 unsigned long flags;
1499 unsigned int baud, quot, clkdiv;
1500
1501 if (uap->vendor->oversampling)
1502 clkdiv = 8;
1503 else
1504 clkdiv = 16;
1505
1506 /*
1507 * Ask the core to calculate the divisor for us.
1508 */
1509 baud = uart_get_baud_rate(port, termios, old, 0,
1510 port->uartclk / clkdiv);
1511
1512 if (baud > port->uartclk/16)
1513 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1514 else
1515 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1516
1517 switch (termios->c_cflag & CSIZE) {
1518 case CS5:
1519 lcr_h = UART01x_LCRH_WLEN_5;
1520 break;
1521 case CS6:
1522 lcr_h = UART01x_LCRH_WLEN_6;
1523 break;
1524 case CS7:
1525 lcr_h = UART01x_LCRH_WLEN_7;
1526 break;
1527 default: // CS8
1528 lcr_h = UART01x_LCRH_WLEN_8;
1529 break;
1530 }
1531 if (termios->c_cflag & CSTOPB)
1532 lcr_h |= UART01x_LCRH_STP2;
1533 if (termios->c_cflag & PARENB) {
1534 lcr_h |= UART01x_LCRH_PEN;
1535 if (!(termios->c_cflag & PARODD))
1536 lcr_h |= UART01x_LCRH_EPS;
1537 }
1538 if (uap->fifosize > 1)
1539 lcr_h |= UART01x_LCRH_FEN;
1540
1541 spin_lock_irqsave(&port->lock, flags);
1542
1543 /*
1544 * Update the per-port timeout.
1545 */
1546 uart_update_timeout(port, termios->c_cflag, baud);
1547
1548 port->read_status_mask = UART011_DR_OE | 255;
1549 if (termios->c_iflag & INPCK)
1550 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1551 if (termios->c_iflag & (BRKINT | PARMRK))
1552 port->read_status_mask |= UART011_DR_BE;
1553
1554 /*
1555 * Characters to ignore
1556 */
1557 port->ignore_status_mask = 0;
1558 if (termios->c_iflag & IGNPAR)
1559 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1560 if (termios->c_iflag & IGNBRK) {
1561 port->ignore_status_mask |= UART011_DR_BE;
1562 /*
1563 * If we're ignoring parity and break indicators,
1564 * ignore overruns too (for real raw support).
1565 */
1566 if (termios->c_iflag & IGNPAR)
1567 port->ignore_status_mask |= UART011_DR_OE;
1568 }
1569
1570 /*
1571 * Ignore all characters if CREAD is not set.
1572 */
1573 if ((termios->c_cflag & CREAD) == 0)
1574 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1575
1576 if (UART_ENABLE_MS(port, termios->c_cflag))
1577 pl011_enable_ms(port);
1578
1579 /* first, disable everything */
1580 old_cr = readw(port->membase + UART011_CR);
1581 writew(0, port->membase + UART011_CR);
1582
1583 if (termios->c_cflag & CRTSCTS) {
1584 if (old_cr & UART011_CR_RTS)
1585 old_cr |= UART011_CR_RTSEN;
1586
1587 old_cr |= UART011_CR_CTSEN;
1588 uap->autorts = true;
1589 } else {
1590 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
1591 uap->autorts = false;
1592 }
1593
1594 if (uap->vendor->oversampling) {
1595 if (baud > port->uartclk / 16)
1596 old_cr |= ST_UART011_CR_OVSFACT;
1597 else
1598 old_cr &= ~ST_UART011_CR_OVSFACT;
1599 }
1600
1601 /* Set baud rate */
1602 writew(quot & 0x3f, port->membase + UART011_FBRD);
1603 writew(quot >> 6, port->membase + UART011_IBRD);
1604
1605 /*
1606 * ----------v----------v----------v----------v-----
1607 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
1608 * ----------^----------^----------^----------^-----
1609 */
1610 writew(lcr_h, port->membase + uap->lcrh_rx);
1611 if (uap->lcrh_rx != uap->lcrh_tx) {
1612 int i;
1613 /*
1614 * Wait 10 PCLKs before writing LCRH_TX register,
1615 * to get this delay write read only register 10 times
1616 */
1617 for (i = 0; i < 10; ++i)
1618 writew(0xff, uap->port.membase + UART011_MIS);
1619 writew(lcr_h, port->membase + uap->lcrh_tx);
1620 }
1621 writew(old_cr, port->membase + UART011_CR);
1622
1623 spin_unlock_irqrestore(&port->lock, flags);
1624 }
1625
1626 static const char *pl011_type(struct uart_port *port)
1627 {
1628 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1629 return uap->port.type == PORT_AMBA ? uap->type : NULL;
1630 }
1631
1632 /*
1633 * Release the memory region(s) being used by 'port'
1634 */
1635 static void pl011_release_port(struct uart_port *port)
1636 {
1637 release_mem_region(port->mapbase, SZ_4K);
1638 }
1639
1640 /*
1641 * Request the memory region(s) being used by 'port'
1642 */
1643 static int pl011_request_port(struct uart_port *port)
1644 {
1645 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
1646 != NULL ? 0 : -EBUSY;
1647 }
1648
1649 /*
1650 * Configure/autoconfigure the port.
1651 */
1652 static void pl011_config_port(struct uart_port *port, int flags)
1653 {
1654 if (flags & UART_CONFIG_TYPE) {
1655 port->type = PORT_AMBA;
1656 pl011_request_port(port);
1657 }
1658 }
1659
1660 /*
1661 * verify the new serial_struct (for TIOCSSERIAL).
1662 */
1663 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
1664 {
1665 int ret = 0;
1666 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
1667 ret = -EINVAL;
1668 if (ser->irq < 0 || ser->irq >= nr_irqs)
1669 ret = -EINVAL;
1670 if (ser->baud_base < 9600)
1671 ret = -EINVAL;
1672 return ret;
1673 }
1674
1675 static struct uart_ops amba_pl011_pops = {
1676 .tx_empty = pl011_tx_empty,
1677 .set_mctrl = pl011_set_mctrl,
1678 .get_mctrl = pl011_get_mctrl,
1679 .stop_tx = pl011_stop_tx,
1680 .start_tx = pl011_start_tx,
1681 .stop_rx = pl011_stop_rx,
1682 .enable_ms = pl011_enable_ms,
1683 .break_ctl = pl011_break_ctl,
1684 .startup = pl011_startup,
1685 .shutdown = pl011_shutdown,
1686 .flush_buffer = pl011_dma_flush_buffer,
1687 .set_termios = pl011_set_termios,
1688 .type = pl011_type,
1689 .release_port = pl011_release_port,
1690 .request_port = pl011_request_port,
1691 .config_port = pl011_config_port,
1692 .verify_port = pl011_verify_port,
1693 #ifdef CONFIG_CONSOLE_POLL
1694 .poll_get_char = pl011_get_poll_char,
1695 .poll_put_char = pl011_put_poll_char,
1696 #endif
1697 };
1698
1699 static struct uart_amba_port *amba_ports[UART_NR];
1700
1701 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
1702
1703 static void pl011_console_putchar(struct uart_port *port, int ch)
1704 {
1705 struct uart_amba_port *uap = (struct uart_amba_port *)port;
1706
1707 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
1708 barrier();
1709 writew(ch, uap->port.membase + UART01x_DR);
1710 }
1711
1712 static void
1713 pl011_console_write(struct console *co, const char *s, unsigned int count)
1714 {
1715 struct uart_amba_port *uap = amba_ports[co->index];
1716 unsigned int status, old_cr, new_cr;
1717 unsigned long flags;
1718 int locked = 1;
1719
1720 clk_enable(uap->clk);
1721
1722 local_irq_save(flags);
1723 if (uap->port.sysrq)
1724 locked = 0;
1725 else if (oops_in_progress)
1726 locked = spin_trylock(&uap->port.lock);
1727 else
1728 spin_lock(&uap->port.lock);
1729
1730 /*
1731 * First save the CR then disable the interrupts
1732 */
1733 old_cr = readw(uap->port.membase + UART011_CR);
1734 new_cr = old_cr & ~UART011_CR_CTSEN;
1735 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1736 writew(new_cr, uap->port.membase + UART011_CR);
1737
1738 uart_console_write(&uap->port, s, count, pl011_console_putchar);
1739
1740 /*
1741 * Finally, wait for transmitter to become empty
1742 * and restore the TCR
1743 */
1744 do {
1745 status = readw(uap->port.membase + UART01x_FR);
1746 } while (status & UART01x_FR_BUSY);
1747 writew(old_cr, uap->port.membase + UART011_CR);
1748
1749 if (locked)
1750 spin_unlock(&uap->port.lock);
1751 local_irq_restore(flags);
1752
1753 clk_disable(uap->clk);
1754 }
1755
1756 static void __init
1757 pl011_console_get_options(struct uart_amba_port *uap, int *baud,
1758 int *parity, int *bits)
1759 {
1760 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
1761 unsigned int lcr_h, ibrd, fbrd;
1762
1763 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
1764
1765 *parity = 'n';
1766 if (lcr_h & UART01x_LCRH_PEN) {
1767 if (lcr_h & UART01x_LCRH_EPS)
1768 *parity = 'e';
1769 else
1770 *parity = 'o';
1771 }
1772
1773 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
1774 *bits = 7;
1775 else
1776 *bits = 8;
1777
1778 ibrd = readw(uap->port.membase + UART011_IBRD);
1779 fbrd = readw(uap->port.membase + UART011_FBRD);
1780
1781 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
1782
1783 if (uap->vendor->oversampling) {
1784 if (readw(uap->port.membase + UART011_CR)
1785 & ST_UART011_CR_OVSFACT)
1786 *baud *= 2;
1787 }
1788 }
1789 }
1790
1791 static int __init pl011_console_setup(struct console *co, char *options)
1792 {
1793 struct uart_amba_port *uap;
1794 int baud = 38400;
1795 int bits = 8;
1796 int parity = 'n';
1797 int flow = 'n';
1798 int ret;
1799
1800 /*
1801 * Check whether an invalid uart number has been specified, and
1802 * if so, search for the first available port that does have
1803 * console support.
1804 */
1805 if (co->index >= UART_NR)
1806 co->index = 0;
1807 uap = amba_ports[co->index];
1808 if (!uap)
1809 return -ENODEV;
1810
1811 /* Allow pins to be muxed in and configured */
1812 if (!IS_ERR(uap->pins_default)) {
1813 ret = pinctrl_select_state(uap->pinctrl, uap->pins_default);
1814 if (ret)
1815 dev_err(uap->port.dev,
1816 "could not set default pins\n");
1817 }
1818
1819 ret = clk_prepare(uap->clk);
1820 if (ret)
1821 return ret;
1822
1823 if (uap->port.dev->platform_data) {
1824 struct amba_pl011_data *plat;
1825
1826 plat = uap->port.dev->platform_data;
1827 if (plat->init)
1828 plat->init();
1829 }
1830
1831 uap->port.uartclk = clk_get_rate(uap->clk);
1832
1833 if (options)
1834 uart_parse_options(options, &baud, &parity, &bits, &flow);
1835 else
1836 pl011_console_get_options(uap, &baud, &parity, &bits);
1837
1838 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
1839 }
1840
1841 static struct uart_driver amba_reg;
1842 static struct console amba_console = {
1843 .name = "ttyAMA",
1844 .write = pl011_console_write,
1845 .device = uart_console_device,
1846 .setup = pl011_console_setup,
1847 .flags = CON_PRINTBUFFER,
1848 .index = -1,
1849 .data = &amba_reg,
1850 };
1851
1852 #define AMBA_CONSOLE (&amba_console)
1853 #else
1854 #define AMBA_CONSOLE NULL
1855 #endif
1856
1857 static struct uart_driver amba_reg = {
1858 .owner = THIS_MODULE,
1859 .driver_name = "ttyAMA",
1860 .dev_name = "ttyAMA",
1861 .major = SERIAL_AMBA_MAJOR,
1862 .minor = SERIAL_AMBA_MINOR,
1863 .nr = UART_NR,
1864 .cons = AMBA_CONSOLE,
1865 };
1866
1867 static int pl011_probe_dt_alias(int index, struct device *dev)
1868 {
1869 struct device_node *np;
1870 static bool seen_dev_with_alias = false;
1871 static bool seen_dev_without_alias = false;
1872 int ret = index;
1873
1874 if (!IS_ENABLED(CONFIG_OF))
1875 return ret;
1876
1877 np = dev->of_node;
1878 if (!np)
1879 return ret;
1880
1881 ret = of_alias_get_id(np, "serial");
1882 if (IS_ERR_VALUE(ret)) {
1883 seen_dev_without_alias = true;
1884 ret = index;
1885 } else {
1886 seen_dev_with_alias = true;
1887 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
1888 dev_warn(dev, "requested serial port %d not available.\n", ret);
1889 ret = index;
1890 }
1891 }
1892
1893 if (seen_dev_with_alias && seen_dev_without_alias)
1894 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
1895
1896 return ret;
1897 }
1898
1899 static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
1900 {
1901 struct uart_amba_port *uap;
1902 struct vendor_data *vendor = id->data;
1903 void __iomem *base;
1904 int i, ret;
1905
1906 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
1907 if (amba_ports[i] == NULL)
1908 break;
1909
1910 if (i == ARRAY_SIZE(amba_ports)) {
1911 ret = -EBUSY;
1912 goto out;
1913 }
1914
1915 uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
1916 if (uap == NULL) {
1917 ret = -ENOMEM;
1918 goto out;
1919 }
1920
1921 i = pl011_probe_dt_alias(i, &dev->dev);
1922
1923 base = ioremap(dev->res.start, resource_size(&dev->res));
1924 if (!base) {
1925 ret = -ENOMEM;
1926 goto free;
1927 }
1928
1929 uap->pinctrl = devm_pinctrl_get(&dev->dev);
1930 if (IS_ERR(uap->pinctrl)) {
1931 ret = PTR_ERR(uap->pinctrl);
1932 goto unmap;
1933 }
1934 uap->pins_default = pinctrl_lookup_state(uap->pinctrl,
1935 PINCTRL_STATE_DEFAULT);
1936 if (IS_ERR(uap->pins_default))
1937 dev_err(&dev->dev, "could not get default pinstate\n");
1938
1939 uap->pins_sleep = pinctrl_lookup_state(uap->pinctrl,
1940 PINCTRL_STATE_SLEEP);
1941 if (IS_ERR(uap->pins_sleep))
1942 dev_dbg(&dev->dev, "could not get sleep pinstate\n");
1943
1944 uap->clk = clk_get(&dev->dev, NULL);
1945 if (IS_ERR(uap->clk)) {
1946 ret = PTR_ERR(uap->clk);
1947 goto unmap;
1948 }
1949
1950 uap->vendor = vendor;
1951 uap->lcrh_rx = vendor->lcrh_rx;
1952 uap->lcrh_tx = vendor->lcrh_tx;
1953 uap->old_cr = 0;
1954 uap->fifosize = vendor->fifosize;
1955 uap->interrupt_may_hang = vendor->interrupt_may_hang;
1956 uap->port.dev = &dev->dev;
1957 uap->port.mapbase = dev->res.start;
1958 uap->port.membase = base;
1959 uap->port.iotype = UPIO_MEM;
1960 uap->port.irq = dev->irq[0];
1961 uap->port.fifosize = uap->fifosize;
1962 uap->port.ops = &amba_pl011_pops;
1963 uap->port.flags = UPF_BOOT_AUTOCONF;
1964 uap->port.line = i;
1965 pl011_dma_probe(uap);
1966
1967 /* Ensure interrupts from this UART are masked and cleared */
1968 writew(0, uap->port.membase + UART011_IMSC);
1969 writew(0xffff, uap->port.membase + UART011_ICR);
1970
1971 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
1972
1973 amba_ports[i] = uap;
1974
1975 amba_set_drvdata(dev, uap);
1976 ret = uart_add_one_port(&amba_reg, &uap->port);
1977 if (ret) {
1978 amba_set_drvdata(dev, NULL);
1979 amba_ports[i] = NULL;
1980 pl011_dma_remove(uap);
1981 clk_put(uap->clk);
1982 unmap:
1983 iounmap(base);
1984 free:
1985 kfree(uap);
1986 }
1987 out:
1988 return ret;
1989 }
1990
1991 static int pl011_remove(struct amba_device *dev)
1992 {
1993 struct uart_amba_port *uap = amba_get_drvdata(dev);
1994 int i;
1995
1996 amba_set_drvdata(dev, NULL);
1997
1998 uart_remove_one_port(&amba_reg, &uap->port);
1999
2000 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2001 if (amba_ports[i] == uap)
2002 amba_ports[i] = NULL;
2003
2004 pl011_dma_remove(uap);
2005 iounmap(uap->port.membase);
2006 clk_put(uap->clk);
2007 kfree(uap);
2008 return 0;
2009 }
2010
2011 #ifdef CONFIG_PM
2012 static int pl011_suspend(struct amba_device *dev, pm_message_t state)
2013 {
2014 struct uart_amba_port *uap = amba_get_drvdata(dev);
2015
2016 if (!uap)
2017 return -EINVAL;
2018
2019 return uart_suspend_port(&amba_reg, &uap->port);
2020 }
2021
2022 static int pl011_resume(struct amba_device *dev)
2023 {
2024 struct uart_amba_port *uap = amba_get_drvdata(dev);
2025
2026 if (!uap)
2027 return -EINVAL;
2028
2029 return uart_resume_port(&amba_reg, &uap->port);
2030 }
2031 #endif
2032
2033 static struct amba_id pl011_ids[] = {
2034 {
2035 .id = 0x00041011,
2036 .mask = 0x000fffff,
2037 .data = &vendor_arm,
2038 },
2039 {
2040 .id = 0x00380802,
2041 .mask = 0x00ffffff,
2042 .data = &vendor_st,
2043 },
2044 { 0, 0 },
2045 };
2046
2047 MODULE_DEVICE_TABLE(amba, pl011_ids);
2048
2049 static struct amba_driver pl011_driver = {
2050 .drv = {
2051 .name = "uart-pl011",
2052 },
2053 .id_table = pl011_ids,
2054 .probe = pl011_probe,
2055 .remove = pl011_remove,
2056 #ifdef CONFIG_PM
2057 .suspend = pl011_suspend,
2058 .resume = pl011_resume,
2059 #endif
2060 };
2061
2062 static int __init pl011_init(void)
2063 {
2064 int ret;
2065 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2066
2067 ret = uart_register_driver(&amba_reg);
2068 if (ret == 0) {
2069 ret = amba_driver_register(&pl011_driver);
2070 if (ret)
2071 uart_unregister_driver(&amba_reg);
2072 }
2073 return ret;
2074 }
2075
2076 static void __exit pl011_exit(void)
2077 {
2078 amba_driver_unregister(&pl011_driver);
2079 uart_unregister_driver(&amba_reg);
2080 }
2081
2082 /*
2083 * While this can be a module, if builtin it's most likely the console
2084 * So let's leave module_exit but move module_init to an earlier place
2085 */
2086 arch_initcall(pl011_init);
2087 module_exit(pl011_exit);
2088
2089 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2090 MODULE_DESCRIPTION("ARM AMBA serial port driver");
2091 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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