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[deliverable/linux.git] / drivers / tty / serial / amba-pl011.c
1 /*
2 * Driver for AMBA serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 * Copyright (C) 2010 ST-Ericsson SA
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * This is a generic driver for ARM AMBA-type serial ports. They
25 * have a lot of 16550-like features, but are not register compatible.
26 * Note that although they do have CTS, DCD and DSR inputs, they do
27 * not have an RI input, nor do they have DTR or RTS outputs. If
28 * required, these have to be supplied via some other means (eg, GPIO)
29 * and hooked into this driver.
30 */
31
32
33 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
34 #define SUPPORT_SYSRQ
35 #endif
36
37 #include <linux/module.h>
38 #include <linux/ioport.h>
39 #include <linux/init.h>
40 #include <linux/console.h>
41 #include <linux/sysrq.h>
42 #include <linux/device.h>
43 #include <linux/tty.h>
44 #include <linux/tty_flip.h>
45 #include <linux/serial_core.h>
46 #include <linux/serial.h>
47 #include <linux/amba/bus.h>
48 #include <linux/amba/serial.h>
49 #include <linux/clk.h>
50 #include <linux/slab.h>
51 #include <linux/dmaengine.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/scatterlist.h>
54 #include <linux/delay.h>
55 #include <linux/types.h>
56 #include <linux/of.h>
57 #include <linux/of_device.h>
58 #include <linux/pinctrl/consumer.h>
59 #include <linux/sizes.h>
60 #include <linux/io.h>
61 #include <linux/acpi.h>
62
63 #include "amba-pl011.h"
64
65 #define UART_NR 14
66
67 #define SERIAL_AMBA_MAJOR 204
68 #define SERIAL_AMBA_MINOR 64
69 #define SERIAL_AMBA_NR UART_NR
70
71 #define AMBA_ISR_PASS_LIMIT 256
72
73 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
74 #define UART_DUMMY_DR_RX (1 << 16)
75
76 static u16 pl011_std_offsets[REG_ARRAY_SIZE] = {
77 [REG_DR] = UART01x_DR,
78 [REG_ST_DMAWM] = ST_UART011_DMAWM,
79 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT,
80 [REG_FR] = UART01x_FR,
81 [REG_ST_LCRH_RX] = ST_UART011_LCRH_RX,
82 [REG_IBRD] = UART011_IBRD,
83 [REG_FBRD] = UART011_FBRD,
84 [REG_LCRH] = UART011_LCRH,
85 [REG_ST_LCRH_TX] = ST_UART011_LCRH_TX,
86 [REG_CR] = UART011_CR,
87 [REG_IFLS] = UART011_IFLS,
88 [REG_IMSC] = UART011_IMSC,
89 [REG_RIS] = UART011_RIS,
90 [REG_MIS] = UART011_MIS,
91 [REG_ICR] = UART011_ICR,
92 [REG_DMACR] = UART011_DMACR,
93 [REG_ST_XFCR] = ST_UART011_XFCR,
94 [REG_ST_XON1] = ST_UART011_XON1,
95 [REG_ST_XON2] = ST_UART011_XON2,
96 [REG_ST_XOFF1] = ST_UART011_XOFF1,
97 [REG_ST_XOFF2] = ST_UART011_XOFF2,
98 [REG_ST_ITCR] = ST_UART011_ITCR,
99 [REG_ST_ITIP] = ST_UART011_ITIP,
100 [REG_ST_ABCR] = ST_UART011_ABCR,
101 [REG_ST_ABIMSC] = ST_UART011_ABIMSC,
102 };
103
104 /* There is by now at least one vendor with differing details, so handle it */
105 struct vendor_data {
106 unsigned int ifls;
107 unsigned int lcrh_tx;
108 unsigned int lcrh_rx;
109 bool oversampling;
110 bool dma_threshold;
111 bool cts_event_workaround;
112 bool always_enabled;
113 bool fixed_options;
114
115 unsigned int (*get_fifosize)(struct amba_device *dev);
116 };
117
118 static unsigned int get_fifosize_arm(struct amba_device *dev)
119 {
120 return amba_rev(dev) < 3 ? 16 : 32;
121 }
122
123 static struct vendor_data vendor_arm = {
124 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
125 .lcrh_tx = REG_LCRH,
126 .lcrh_rx = REG_LCRH,
127 .oversampling = false,
128 .dma_threshold = false,
129 .cts_event_workaround = false,
130 .always_enabled = false,
131 .fixed_options = false,
132 .get_fifosize = get_fifosize_arm,
133 };
134
135 static struct vendor_data vendor_sbsa = {
136 .oversampling = false,
137 .dma_threshold = false,
138 .cts_event_workaround = false,
139 .always_enabled = true,
140 .fixed_options = true,
141 };
142
143 static unsigned int get_fifosize_st(struct amba_device *dev)
144 {
145 return 64;
146 }
147
148 static struct vendor_data vendor_st = {
149 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
150 .lcrh_tx = REG_ST_LCRH_TX,
151 .lcrh_rx = REG_ST_LCRH_RX,
152 .oversampling = true,
153 .dma_threshold = true,
154 .cts_event_workaround = true,
155 .always_enabled = false,
156 .fixed_options = false,
157 .get_fifosize = get_fifosize_st,
158 };
159
160 /* Deals with DMA transactions */
161
162 struct pl011_sgbuf {
163 struct scatterlist sg;
164 char *buf;
165 };
166
167 struct pl011_dmarx_data {
168 struct dma_chan *chan;
169 struct completion complete;
170 bool use_buf_b;
171 struct pl011_sgbuf sgbuf_a;
172 struct pl011_sgbuf sgbuf_b;
173 dma_cookie_t cookie;
174 bool running;
175 struct timer_list timer;
176 unsigned int last_residue;
177 unsigned long last_jiffies;
178 bool auto_poll_rate;
179 unsigned int poll_rate;
180 unsigned int poll_timeout;
181 };
182
183 struct pl011_dmatx_data {
184 struct dma_chan *chan;
185 struct scatterlist sg;
186 char *buf;
187 bool queued;
188 };
189
190 /*
191 * We wrap our port structure around the generic uart_port.
192 */
193 struct uart_amba_port {
194 struct uart_port port;
195 const u16 *reg_offset;
196 struct clk *clk;
197 const struct vendor_data *vendor;
198 unsigned int dmacr; /* dma control reg */
199 unsigned int im; /* interrupt mask */
200 unsigned int old_status;
201 unsigned int fifosize; /* vendor-specific */
202 unsigned int lcrh_tx; /* vendor-specific */
203 unsigned int lcrh_rx; /* vendor-specific */
204 unsigned int old_cr; /* state during shutdown */
205 bool autorts;
206 unsigned int fixed_baud; /* vendor-set fixed baud rate */
207 char type[12];
208 #ifdef CONFIG_DMA_ENGINE
209 /* DMA stuff */
210 bool using_tx_dma;
211 bool using_rx_dma;
212 struct pl011_dmarx_data dmarx;
213 struct pl011_dmatx_data dmatx;
214 bool dma_probed;
215 #endif
216 };
217
218 static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap,
219 unsigned int reg)
220 {
221 return uap->reg_offset[reg];
222 }
223
224 static unsigned int pl011_read(const struct uart_amba_port *uap,
225 unsigned int reg)
226 {
227 return readw(uap->port.membase + pl011_reg_to_offset(uap, reg));
228 }
229
230 static void pl011_write(unsigned int val, const struct uart_amba_port *uap,
231 unsigned int reg)
232 {
233 writew(val, uap->port.membase + pl011_reg_to_offset(uap, reg));
234 }
235
236 /*
237 * Reads up to 256 characters from the FIFO or until it's empty and
238 * inserts them into the TTY layer. Returns the number of characters
239 * read from the FIFO.
240 */
241 static int pl011_fifo_to_tty(struct uart_amba_port *uap)
242 {
243 u16 status;
244 unsigned int ch, flag, max_count = 256;
245 int fifotaken = 0;
246
247 while (max_count--) {
248 status = pl011_read(uap, REG_FR);
249 if (status & UART01x_FR_RXFE)
250 break;
251
252 /* Take chars from the FIFO and update status */
253 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;
254 flag = TTY_NORMAL;
255 uap->port.icount.rx++;
256 fifotaken++;
257
258 if (unlikely(ch & UART_DR_ERROR)) {
259 if (ch & UART011_DR_BE) {
260 ch &= ~(UART011_DR_FE | UART011_DR_PE);
261 uap->port.icount.brk++;
262 if (uart_handle_break(&uap->port))
263 continue;
264 } else if (ch & UART011_DR_PE)
265 uap->port.icount.parity++;
266 else if (ch & UART011_DR_FE)
267 uap->port.icount.frame++;
268 if (ch & UART011_DR_OE)
269 uap->port.icount.overrun++;
270
271 ch &= uap->port.read_status_mask;
272
273 if (ch & UART011_DR_BE)
274 flag = TTY_BREAK;
275 else if (ch & UART011_DR_PE)
276 flag = TTY_PARITY;
277 else if (ch & UART011_DR_FE)
278 flag = TTY_FRAME;
279 }
280
281 if (uart_handle_sysrq_char(&uap->port, ch & 255))
282 continue;
283
284 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
285 }
286
287 return fifotaken;
288 }
289
290
291 /*
292 * All the DMA operation mode stuff goes inside this ifdef.
293 * This assumes that you have a generic DMA device interface,
294 * no custom DMA interfaces are supported.
295 */
296 #ifdef CONFIG_DMA_ENGINE
297
298 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE
299
300 static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
301 enum dma_data_direction dir)
302 {
303 dma_addr_t dma_addr;
304
305 sg->buf = dma_alloc_coherent(chan->device->dev,
306 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
307 if (!sg->buf)
308 return -ENOMEM;
309
310 sg_init_table(&sg->sg, 1);
311 sg_set_page(&sg->sg, phys_to_page(dma_addr),
312 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
313 sg_dma_address(&sg->sg) = dma_addr;
314 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE;
315
316 return 0;
317 }
318
319 static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
320 enum dma_data_direction dir)
321 {
322 if (sg->buf) {
323 dma_free_coherent(chan->device->dev,
324 PL011_DMA_BUFFER_SIZE, sg->buf,
325 sg_dma_address(&sg->sg));
326 }
327 }
328
329 static void pl011_dma_probe(struct uart_amba_port *uap)
330 {
331 /* DMA is the sole user of the platform data right now */
332 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
333 struct device *dev = uap->port.dev;
334 struct dma_slave_config tx_conf = {
335 .dst_addr = uap->port.mapbase +
336 pl011_reg_to_offset(uap, REG_DR),
337 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
338 .direction = DMA_MEM_TO_DEV,
339 .dst_maxburst = uap->fifosize >> 1,
340 .device_fc = false,
341 };
342 struct dma_chan *chan;
343 dma_cap_mask_t mask;
344
345 uap->dma_probed = true;
346 chan = dma_request_slave_channel_reason(dev, "tx");
347 if (IS_ERR(chan)) {
348 if (PTR_ERR(chan) == -EPROBE_DEFER) {
349 uap->dma_probed = false;
350 return;
351 }
352
353 /* We need platform data */
354 if (!plat || !plat->dma_filter) {
355 dev_info(uap->port.dev, "no DMA platform data\n");
356 return;
357 }
358
359 /* Try to acquire a generic DMA engine slave TX channel */
360 dma_cap_zero(mask);
361 dma_cap_set(DMA_SLAVE, mask);
362
363 chan = dma_request_channel(mask, plat->dma_filter,
364 plat->dma_tx_param);
365 if (!chan) {
366 dev_err(uap->port.dev, "no TX DMA channel!\n");
367 return;
368 }
369 }
370
371 dmaengine_slave_config(chan, &tx_conf);
372 uap->dmatx.chan = chan;
373
374 dev_info(uap->port.dev, "DMA channel TX %s\n",
375 dma_chan_name(uap->dmatx.chan));
376
377 /* Optionally make use of an RX channel as well */
378 chan = dma_request_slave_channel(dev, "rx");
379
380 if (!chan && plat->dma_rx_param) {
381 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
382
383 if (!chan) {
384 dev_err(uap->port.dev, "no RX DMA channel!\n");
385 return;
386 }
387 }
388
389 if (chan) {
390 struct dma_slave_config rx_conf = {
391 .src_addr = uap->port.mapbase +
392 pl011_reg_to_offset(uap, REG_DR),
393 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
394 .direction = DMA_DEV_TO_MEM,
395 .src_maxburst = uap->fifosize >> 2,
396 .device_fc = false,
397 };
398 struct dma_slave_caps caps;
399
400 /*
401 * Some DMA controllers provide information on their capabilities.
402 * If the controller does, check for suitable residue processing
403 * otherwise assime all is well.
404 */
405 if (0 == dma_get_slave_caps(chan, &caps)) {
406 if (caps.residue_granularity ==
407 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
408 dma_release_channel(chan);
409 dev_info(uap->port.dev,
410 "RX DMA disabled - no residue processing\n");
411 return;
412 }
413 }
414 dmaengine_slave_config(chan, &rx_conf);
415 uap->dmarx.chan = chan;
416
417 uap->dmarx.auto_poll_rate = false;
418 if (plat && plat->dma_rx_poll_enable) {
419 /* Set poll rate if specified. */
420 if (plat->dma_rx_poll_rate) {
421 uap->dmarx.auto_poll_rate = false;
422 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
423 } else {
424 /*
425 * 100 ms defaults to poll rate if not
426 * specified. This will be adjusted with
427 * the baud rate at set_termios.
428 */
429 uap->dmarx.auto_poll_rate = true;
430 uap->dmarx.poll_rate = 100;
431 }
432 /* 3 secs defaults poll_timeout if not specified. */
433 if (plat->dma_rx_poll_timeout)
434 uap->dmarx.poll_timeout =
435 plat->dma_rx_poll_timeout;
436 else
437 uap->dmarx.poll_timeout = 3000;
438 } else if (!plat && dev->of_node) {
439 uap->dmarx.auto_poll_rate = of_property_read_bool(
440 dev->of_node, "auto-poll");
441 if (uap->dmarx.auto_poll_rate) {
442 u32 x;
443
444 if (0 == of_property_read_u32(dev->of_node,
445 "poll-rate-ms", &x))
446 uap->dmarx.poll_rate = x;
447 else
448 uap->dmarx.poll_rate = 100;
449 if (0 == of_property_read_u32(dev->of_node,
450 "poll-timeout-ms", &x))
451 uap->dmarx.poll_timeout = x;
452 else
453 uap->dmarx.poll_timeout = 3000;
454 }
455 }
456 dev_info(uap->port.dev, "DMA channel RX %s\n",
457 dma_chan_name(uap->dmarx.chan));
458 }
459 }
460
461 static void pl011_dma_remove(struct uart_amba_port *uap)
462 {
463 if (uap->dmatx.chan)
464 dma_release_channel(uap->dmatx.chan);
465 if (uap->dmarx.chan)
466 dma_release_channel(uap->dmarx.chan);
467 }
468
469 /* Forward declare these for the refill routine */
470 static int pl011_dma_tx_refill(struct uart_amba_port *uap);
471 static void pl011_start_tx_pio(struct uart_amba_port *uap);
472
473 /*
474 * The current DMA TX buffer has been sent.
475 * Try to queue up another DMA buffer.
476 */
477 static void pl011_dma_tx_callback(void *data)
478 {
479 struct uart_amba_port *uap = data;
480 struct pl011_dmatx_data *dmatx = &uap->dmatx;
481 unsigned long flags;
482 u16 dmacr;
483
484 spin_lock_irqsave(&uap->port.lock, flags);
485 if (uap->dmatx.queued)
486 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
487 DMA_TO_DEVICE);
488
489 dmacr = uap->dmacr;
490 uap->dmacr = dmacr & ~UART011_TXDMAE;
491 pl011_write(uap->dmacr, uap, REG_DMACR);
492
493 /*
494 * If TX DMA was disabled, it means that we've stopped the DMA for
495 * some reason (eg, XOFF received, or we want to send an X-char.)
496 *
497 * Note: we need to be careful here of a potential race between DMA
498 * and the rest of the driver - if the driver disables TX DMA while
499 * a TX buffer completing, we must update the tx queued status to
500 * get further refills (hence we check dmacr).
501 */
502 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
503 uart_circ_empty(&uap->port.state->xmit)) {
504 uap->dmatx.queued = false;
505 spin_unlock_irqrestore(&uap->port.lock, flags);
506 return;
507 }
508
509 if (pl011_dma_tx_refill(uap) <= 0)
510 /*
511 * We didn't queue a DMA buffer for some reason, but we
512 * have data pending to be sent. Re-enable the TX IRQ.
513 */
514 pl011_start_tx_pio(uap);
515
516 spin_unlock_irqrestore(&uap->port.lock, flags);
517 }
518
519 /*
520 * Try to refill the TX DMA buffer.
521 * Locking: called with port lock held and IRQs disabled.
522 * Returns:
523 * 1 if we queued up a TX DMA buffer.
524 * 0 if we didn't want to handle this by DMA
525 * <0 on error
526 */
527 static int pl011_dma_tx_refill(struct uart_amba_port *uap)
528 {
529 struct pl011_dmatx_data *dmatx = &uap->dmatx;
530 struct dma_chan *chan = dmatx->chan;
531 struct dma_device *dma_dev = chan->device;
532 struct dma_async_tx_descriptor *desc;
533 struct circ_buf *xmit = &uap->port.state->xmit;
534 unsigned int count;
535
536 /*
537 * Try to avoid the overhead involved in using DMA if the
538 * transaction fits in the first half of the FIFO, by using
539 * the standard interrupt handling. This ensures that we
540 * issue a uart_write_wakeup() at the appropriate time.
541 */
542 count = uart_circ_chars_pending(xmit);
543 if (count < (uap->fifosize >> 1)) {
544 uap->dmatx.queued = false;
545 return 0;
546 }
547
548 /*
549 * Bodge: don't send the last character by DMA, as this
550 * will prevent XON from notifying us to restart DMA.
551 */
552 count -= 1;
553
554 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
555 if (count > PL011_DMA_BUFFER_SIZE)
556 count = PL011_DMA_BUFFER_SIZE;
557
558 if (xmit->tail < xmit->head)
559 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
560 else {
561 size_t first = UART_XMIT_SIZE - xmit->tail;
562 size_t second;
563
564 if (first > count)
565 first = count;
566 second = count - first;
567
568 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
569 if (second)
570 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
571 }
572
573 dmatx->sg.length = count;
574
575 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
576 uap->dmatx.queued = false;
577 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
578 return -EBUSY;
579 }
580
581 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
582 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
583 if (!desc) {
584 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
585 uap->dmatx.queued = false;
586 /*
587 * If DMA cannot be used right now, we complete this
588 * transaction via IRQ and let the TTY layer retry.
589 */
590 dev_dbg(uap->port.dev, "TX DMA busy\n");
591 return -EBUSY;
592 }
593
594 /* Some data to go along to the callback */
595 desc->callback = pl011_dma_tx_callback;
596 desc->callback_param = uap;
597
598 /* All errors should happen at prepare time */
599 dmaengine_submit(desc);
600
601 /* Fire the DMA transaction */
602 dma_dev->device_issue_pending(chan);
603
604 uap->dmacr |= UART011_TXDMAE;
605 pl011_write(uap->dmacr, uap, REG_DMACR);
606 uap->dmatx.queued = true;
607
608 /*
609 * Now we know that DMA will fire, so advance the ring buffer
610 * with the stuff we just dispatched.
611 */
612 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
613 uap->port.icount.tx += count;
614
615 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
616 uart_write_wakeup(&uap->port);
617
618 return 1;
619 }
620
621 /*
622 * We received a transmit interrupt without a pending X-char but with
623 * pending characters.
624 * Locking: called with port lock held and IRQs disabled.
625 * Returns:
626 * false if we want to use PIO to transmit
627 * true if we queued a DMA buffer
628 */
629 static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
630 {
631 if (!uap->using_tx_dma)
632 return false;
633
634 /*
635 * If we already have a TX buffer queued, but received a
636 * TX interrupt, it will be because we've just sent an X-char.
637 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
638 */
639 if (uap->dmatx.queued) {
640 uap->dmacr |= UART011_TXDMAE;
641 pl011_write(uap->dmacr, uap, REG_DMACR);
642 uap->im &= ~UART011_TXIM;
643 pl011_write(uap->im, uap, REG_IMSC);
644 return true;
645 }
646
647 /*
648 * We don't have a TX buffer queued, so try to queue one.
649 * If we successfully queued a buffer, mask the TX IRQ.
650 */
651 if (pl011_dma_tx_refill(uap) > 0) {
652 uap->im &= ~UART011_TXIM;
653 pl011_write(uap->im, uap, REG_IMSC);
654 return true;
655 }
656 return false;
657 }
658
659 /*
660 * Stop the DMA transmit (eg, due to received XOFF).
661 * Locking: called with port lock held and IRQs disabled.
662 */
663 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
664 {
665 if (uap->dmatx.queued) {
666 uap->dmacr &= ~UART011_TXDMAE;
667 pl011_write(uap->dmacr, uap, REG_DMACR);
668 }
669 }
670
671 /*
672 * Try to start a DMA transmit, or in the case of an XON/OFF
673 * character queued for send, try to get that character out ASAP.
674 * Locking: called with port lock held and IRQs disabled.
675 * Returns:
676 * false if we want the TX IRQ to be enabled
677 * true if we have a buffer queued
678 */
679 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
680 {
681 u16 dmacr;
682
683 if (!uap->using_tx_dma)
684 return false;
685
686 if (!uap->port.x_char) {
687 /* no X-char, try to push chars out in DMA mode */
688 bool ret = true;
689
690 if (!uap->dmatx.queued) {
691 if (pl011_dma_tx_refill(uap) > 0) {
692 uap->im &= ~UART011_TXIM;
693 pl011_write(uap->im, uap, REG_IMSC);
694 } else
695 ret = false;
696 } else if (!(uap->dmacr & UART011_TXDMAE)) {
697 uap->dmacr |= UART011_TXDMAE;
698 pl011_write(uap->dmacr, uap, REG_DMACR);
699 }
700 return ret;
701 }
702
703 /*
704 * We have an X-char to send. Disable DMA to prevent it loading
705 * the TX fifo, and then see if we can stuff it into the FIFO.
706 */
707 dmacr = uap->dmacr;
708 uap->dmacr &= ~UART011_TXDMAE;
709 pl011_write(uap->dmacr, uap, REG_DMACR);
710
711 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {
712 /*
713 * No space in the FIFO, so enable the transmit interrupt
714 * so we know when there is space. Note that once we've
715 * loaded the character, we should just re-enable DMA.
716 */
717 return false;
718 }
719
720 pl011_write(uap->port.x_char, uap, REG_DR);
721 uap->port.icount.tx++;
722 uap->port.x_char = 0;
723
724 /* Success - restore the DMA state */
725 uap->dmacr = dmacr;
726 pl011_write(dmacr, uap, REG_DMACR);
727
728 return true;
729 }
730
731 /*
732 * Flush the transmit buffer.
733 * Locking: called with port lock held and IRQs disabled.
734 */
735 static void pl011_dma_flush_buffer(struct uart_port *port)
736 __releases(&uap->port.lock)
737 __acquires(&uap->port.lock)
738 {
739 struct uart_amba_port *uap =
740 container_of(port, struct uart_amba_port, port);
741
742 if (!uap->using_tx_dma)
743 return;
744
745 /* Avoid deadlock with the DMA engine callback */
746 spin_unlock(&uap->port.lock);
747 dmaengine_terminate_all(uap->dmatx.chan);
748 spin_lock(&uap->port.lock);
749 if (uap->dmatx.queued) {
750 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
751 DMA_TO_DEVICE);
752 uap->dmatx.queued = false;
753 uap->dmacr &= ~UART011_TXDMAE;
754 pl011_write(uap->dmacr, uap, REG_DMACR);
755 }
756 }
757
758 static void pl011_dma_rx_callback(void *data);
759
760 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
761 {
762 struct dma_chan *rxchan = uap->dmarx.chan;
763 struct pl011_dmarx_data *dmarx = &uap->dmarx;
764 struct dma_async_tx_descriptor *desc;
765 struct pl011_sgbuf *sgbuf;
766
767 if (!rxchan)
768 return -EIO;
769
770 /* Start the RX DMA job */
771 sgbuf = uap->dmarx.use_buf_b ?
772 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
773 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
774 DMA_DEV_TO_MEM,
775 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
776 /*
777 * If the DMA engine is busy and cannot prepare a
778 * channel, no big deal, the driver will fall back
779 * to interrupt mode as a result of this error code.
780 */
781 if (!desc) {
782 uap->dmarx.running = false;
783 dmaengine_terminate_all(rxchan);
784 return -EBUSY;
785 }
786
787 /* Some data to go along to the callback */
788 desc->callback = pl011_dma_rx_callback;
789 desc->callback_param = uap;
790 dmarx->cookie = dmaengine_submit(desc);
791 dma_async_issue_pending(rxchan);
792
793 uap->dmacr |= UART011_RXDMAE;
794 pl011_write(uap->dmacr, uap, REG_DMACR);
795 uap->dmarx.running = true;
796
797 uap->im &= ~UART011_RXIM;
798 pl011_write(uap->im, uap, REG_IMSC);
799
800 return 0;
801 }
802
803 /*
804 * This is called when either the DMA job is complete, or
805 * the FIFO timeout interrupt occurred. This must be called
806 * with the port spinlock uap->port.lock held.
807 */
808 static void pl011_dma_rx_chars(struct uart_amba_port *uap,
809 u32 pending, bool use_buf_b,
810 bool readfifo)
811 {
812 struct tty_port *port = &uap->port.state->port;
813 struct pl011_sgbuf *sgbuf = use_buf_b ?
814 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
815 int dma_count = 0;
816 u32 fifotaken = 0; /* only used for vdbg() */
817
818 struct pl011_dmarx_data *dmarx = &uap->dmarx;
819 int dmataken = 0;
820
821 if (uap->dmarx.poll_rate) {
822 /* The data can be taken by polling */
823 dmataken = sgbuf->sg.length - dmarx->last_residue;
824 /* Recalculate the pending size */
825 if (pending >= dmataken)
826 pending -= dmataken;
827 }
828
829 /* Pick the remain data from the DMA */
830 if (pending) {
831
832 /*
833 * First take all chars in the DMA pipe, then look in the FIFO.
834 * Note that tty_insert_flip_buf() tries to take as many chars
835 * as it can.
836 */
837 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
838 pending);
839
840 uap->port.icount.rx += dma_count;
841 if (dma_count < pending)
842 dev_warn(uap->port.dev,
843 "couldn't insert all characters (TTY is full?)\n");
844 }
845
846 /* Reset the last_residue for Rx DMA poll */
847 if (uap->dmarx.poll_rate)
848 dmarx->last_residue = sgbuf->sg.length;
849
850 /*
851 * Only continue with trying to read the FIFO if all DMA chars have
852 * been taken first.
853 */
854 if (dma_count == pending && readfifo) {
855 /* Clear any error flags */
856 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
857 UART011_FEIS, uap, REG_ICR);
858
859 /*
860 * If we read all the DMA'd characters, and we had an
861 * incomplete buffer, that could be due to an rx error, or
862 * maybe we just timed out. Read any pending chars and check
863 * the error status.
864 *
865 * Error conditions will only occur in the FIFO, these will
866 * trigger an immediate interrupt and stop the DMA job, so we
867 * will always find the error in the FIFO, never in the DMA
868 * buffer.
869 */
870 fifotaken = pl011_fifo_to_tty(uap);
871 }
872
873 spin_unlock(&uap->port.lock);
874 dev_vdbg(uap->port.dev,
875 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
876 dma_count, fifotaken);
877 tty_flip_buffer_push(port);
878 spin_lock(&uap->port.lock);
879 }
880
881 static void pl011_dma_rx_irq(struct uart_amba_port *uap)
882 {
883 struct pl011_dmarx_data *dmarx = &uap->dmarx;
884 struct dma_chan *rxchan = dmarx->chan;
885 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
886 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
887 size_t pending;
888 struct dma_tx_state state;
889 enum dma_status dmastat;
890
891 /*
892 * Pause the transfer so we can trust the current counter,
893 * do this before we pause the PL011 block, else we may
894 * overflow the FIFO.
895 */
896 if (dmaengine_pause(rxchan))
897 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
898 dmastat = rxchan->device->device_tx_status(rxchan,
899 dmarx->cookie, &state);
900 if (dmastat != DMA_PAUSED)
901 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
902
903 /* Disable RX DMA - incoming data will wait in the FIFO */
904 uap->dmacr &= ~UART011_RXDMAE;
905 pl011_write(uap->dmacr, uap, REG_DMACR);
906 uap->dmarx.running = false;
907
908 pending = sgbuf->sg.length - state.residue;
909 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
910 /* Then we terminate the transfer - we now know our residue */
911 dmaengine_terminate_all(rxchan);
912
913 /*
914 * This will take the chars we have so far and insert
915 * into the framework.
916 */
917 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
918
919 /* Switch buffer & re-trigger DMA job */
920 dmarx->use_buf_b = !dmarx->use_buf_b;
921 if (pl011_dma_rx_trigger_dma(uap)) {
922 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
923 "fall back to interrupt mode\n");
924 uap->im |= UART011_RXIM;
925 pl011_write(uap->im, uap, REG_IMSC);
926 }
927 }
928
929 static void pl011_dma_rx_callback(void *data)
930 {
931 struct uart_amba_port *uap = data;
932 struct pl011_dmarx_data *dmarx = &uap->dmarx;
933 struct dma_chan *rxchan = dmarx->chan;
934 bool lastbuf = dmarx->use_buf_b;
935 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
936 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
937 size_t pending;
938 struct dma_tx_state state;
939 int ret;
940
941 /*
942 * This completion interrupt occurs typically when the
943 * RX buffer is totally stuffed but no timeout has yet
944 * occurred. When that happens, we just want the RX
945 * routine to flush out the secondary DMA buffer while
946 * we immediately trigger the next DMA job.
947 */
948 spin_lock_irq(&uap->port.lock);
949 /*
950 * Rx data can be taken by the UART interrupts during
951 * the DMA irq handler. So we check the residue here.
952 */
953 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
954 pending = sgbuf->sg.length - state.residue;
955 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
956 /* Then we terminate the transfer - we now know our residue */
957 dmaengine_terminate_all(rxchan);
958
959 uap->dmarx.running = false;
960 dmarx->use_buf_b = !lastbuf;
961 ret = pl011_dma_rx_trigger_dma(uap);
962
963 pl011_dma_rx_chars(uap, pending, lastbuf, false);
964 spin_unlock_irq(&uap->port.lock);
965 /*
966 * Do this check after we picked the DMA chars so we don't
967 * get some IRQ immediately from RX.
968 */
969 if (ret) {
970 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
971 "fall back to interrupt mode\n");
972 uap->im |= UART011_RXIM;
973 pl011_write(uap->im, uap, REG_IMSC);
974 }
975 }
976
977 /*
978 * Stop accepting received characters, when we're shutting down or
979 * suspending this port.
980 * Locking: called with port lock held and IRQs disabled.
981 */
982 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
983 {
984 /* FIXME. Just disable the DMA enable */
985 uap->dmacr &= ~UART011_RXDMAE;
986 pl011_write(uap->dmacr, uap, REG_DMACR);
987 }
988
989 /*
990 * Timer handler for Rx DMA polling.
991 * Every polling, It checks the residue in the dma buffer and transfer
992 * data to the tty. Also, last_residue is updated for the next polling.
993 */
994 static void pl011_dma_rx_poll(unsigned long args)
995 {
996 struct uart_amba_port *uap = (struct uart_amba_port *)args;
997 struct tty_port *port = &uap->port.state->port;
998 struct pl011_dmarx_data *dmarx = &uap->dmarx;
999 struct dma_chan *rxchan = uap->dmarx.chan;
1000 unsigned long flags = 0;
1001 unsigned int dmataken = 0;
1002 unsigned int size = 0;
1003 struct pl011_sgbuf *sgbuf;
1004 int dma_count;
1005 struct dma_tx_state state;
1006
1007 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
1008 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1009 if (likely(state.residue < dmarx->last_residue)) {
1010 dmataken = sgbuf->sg.length - dmarx->last_residue;
1011 size = dmarx->last_residue - state.residue;
1012 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
1013 size);
1014 if (dma_count == size)
1015 dmarx->last_residue = state.residue;
1016 dmarx->last_jiffies = jiffies;
1017 }
1018 tty_flip_buffer_push(port);
1019
1020 /*
1021 * If no data is received in poll_timeout, the driver will fall back
1022 * to interrupt mode. We will retrigger DMA at the first interrupt.
1023 */
1024 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
1025 > uap->dmarx.poll_timeout) {
1026
1027 spin_lock_irqsave(&uap->port.lock, flags);
1028 pl011_dma_rx_stop(uap);
1029 uap->im |= UART011_RXIM;
1030 pl011_write(uap->im, uap, REG_IMSC);
1031 spin_unlock_irqrestore(&uap->port.lock, flags);
1032
1033 uap->dmarx.running = false;
1034 dmaengine_terminate_all(rxchan);
1035 del_timer(&uap->dmarx.timer);
1036 } else {
1037 mod_timer(&uap->dmarx.timer,
1038 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1039 }
1040 }
1041
1042 static void pl011_dma_startup(struct uart_amba_port *uap)
1043 {
1044 int ret;
1045
1046 if (!uap->dma_probed)
1047 pl011_dma_probe(uap);
1048
1049 if (!uap->dmatx.chan)
1050 return;
1051
1052 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
1053 if (!uap->dmatx.buf) {
1054 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
1055 uap->port.fifosize = uap->fifosize;
1056 return;
1057 }
1058
1059 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
1060
1061 /* The DMA buffer is now the FIFO the TTY subsystem can use */
1062 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
1063 uap->using_tx_dma = true;
1064
1065 if (!uap->dmarx.chan)
1066 goto skip_rx;
1067
1068 /* Allocate and map DMA RX buffers */
1069 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1070 DMA_FROM_DEVICE);
1071 if (ret) {
1072 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1073 "RX buffer A", ret);
1074 goto skip_rx;
1075 }
1076
1077 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
1078 DMA_FROM_DEVICE);
1079 if (ret) {
1080 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1081 "RX buffer B", ret);
1082 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1083 DMA_FROM_DEVICE);
1084 goto skip_rx;
1085 }
1086
1087 uap->using_rx_dma = true;
1088
1089 skip_rx:
1090 /* Turn on DMA error (RX/TX will be enabled on demand) */
1091 uap->dmacr |= UART011_DMAONERR;
1092 pl011_write(uap->dmacr, uap, REG_DMACR);
1093
1094 /*
1095 * ST Micro variants has some specific dma burst threshold
1096 * compensation. Set this to 16 bytes, so burst will only
1097 * be issued above/below 16 bytes.
1098 */
1099 if (uap->vendor->dma_threshold)
1100 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
1101 uap, REG_ST_DMAWM);
1102
1103 if (uap->using_rx_dma) {
1104 if (pl011_dma_rx_trigger_dma(uap))
1105 dev_dbg(uap->port.dev, "could not trigger initial "
1106 "RX DMA job, fall back to interrupt mode\n");
1107 if (uap->dmarx.poll_rate) {
1108 init_timer(&(uap->dmarx.timer));
1109 uap->dmarx.timer.function = pl011_dma_rx_poll;
1110 uap->dmarx.timer.data = (unsigned long)uap;
1111 mod_timer(&uap->dmarx.timer,
1112 jiffies +
1113 msecs_to_jiffies(uap->dmarx.poll_rate));
1114 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1115 uap->dmarx.last_jiffies = jiffies;
1116 }
1117 }
1118 }
1119
1120 static void pl011_dma_shutdown(struct uart_amba_port *uap)
1121 {
1122 if (!(uap->using_tx_dma || uap->using_rx_dma))
1123 return;
1124
1125 /* Disable RX and TX DMA */
1126 while (pl011_read(uap, REG_FR) & UART01x_FR_BUSY)
1127 barrier();
1128
1129 spin_lock_irq(&uap->port.lock);
1130 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
1131 pl011_write(uap->dmacr, uap, REG_DMACR);
1132 spin_unlock_irq(&uap->port.lock);
1133
1134 if (uap->using_tx_dma) {
1135 /* In theory, this should already be done by pl011_dma_flush_buffer */
1136 dmaengine_terminate_all(uap->dmatx.chan);
1137 if (uap->dmatx.queued) {
1138 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
1139 DMA_TO_DEVICE);
1140 uap->dmatx.queued = false;
1141 }
1142
1143 kfree(uap->dmatx.buf);
1144 uap->using_tx_dma = false;
1145 }
1146
1147 if (uap->using_rx_dma) {
1148 dmaengine_terminate_all(uap->dmarx.chan);
1149 /* Clean up the RX DMA */
1150 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
1151 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
1152 if (uap->dmarx.poll_rate)
1153 del_timer_sync(&uap->dmarx.timer);
1154 uap->using_rx_dma = false;
1155 }
1156 }
1157
1158 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1159 {
1160 return uap->using_rx_dma;
1161 }
1162
1163 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1164 {
1165 return uap->using_rx_dma && uap->dmarx.running;
1166 }
1167
1168 #else
1169 /* Blank functions if the DMA engine is not available */
1170 static inline void pl011_dma_probe(struct uart_amba_port *uap)
1171 {
1172 }
1173
1174 static inline void pl011_dma_remove(struct uart_amba_port *uap)
1175 {
1176 }
1177
1178 static inline void pl011_dma_startup(struct uart_amba_port *uap)
1179 {
1180 }
1181
1182 static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1183 {
1184 }
1185
1186 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1187 {
1188 return false;
1189 }
1190
1191 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1192 {
1193 }
1194
1195 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1196 {
1197 return false;
1198 }
1199
1200 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1201 {
1202 }
1203
1204 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1205 {
1206 }
1207
1208 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1209 {
1210 return -EIO;
1211 }
1212
1213 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1214 {
1215 return false;
1216 }
1217
1218 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1219 {
1220 return false;
1221 }
1222
1223 #define pl011_dma_flush_buffer NULL
1224 #endif
1225
1226 static void pl011_stop_tx(struct uart_port *port)
1227 {
1228 struct uart_amba_port *uap =
1229 container_of(port, struct uart_amba_port, port);
1230
1231 uap->im &= ~UART011_TXIM;
1232 pl011_write(uap->im, uap, REG_IMSC);
1233 pl011_dma_tx_stop(uap);
1234 }
1235
1236 static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
1237
1238 /* Start TX with programmed I/O only (no DMA) */
1239 static void pl011_start_tx_pio(struct uart_amba_port *uap)
1240 {
1241 uap->im |= UART011_TXIM;
1242 pl011_write(uap->im, uap, REG_IMSC);
1243 pl011_tx_chars(uap, false);
1244 }
1245
1246 static void pl011_start_tx(struct uart_port *port)
1247 {
1248 struct uart_amba_port *uap =
1249 container_of(port, struct uart_amba_port, port);
1250
1251 if (!pl011_dma_tx_start(uap))
1252 pl011_start_tx_pio(uap);
1253 }
1254
1255 static void pl011_stop_rx(struct uart_port *port)
1256 {
1257 struct uart_amba_port *uap =
1258 container_of(port, struct uart_amba_port, port);
1259
1260 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1261 UART011_PEIM|UART011_BEIM|UART011_OEIM);
1262 pl011_write(uap->im, uap, REG_IMSC);
1263
1264 pl011_dma_rx_stop(uap);
1265 }
1266
1267 static void pl011_enable_ms(struct uart_port *port)
1268 {
1269 struct uart_amba_port *uap =
1270 container_of(port, struct uart_amba_port, port);
1271
1272 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1273 pl011_write(uap->im, uap, REG_IMSC);
1274 }
1275
1276 static void pl011_rx_chars(struct uart_amba_port *uap)
1277 __releases(&uap->port.lock)
1278 __acquires(&uap->port.lock)
1279 {
1280 pl011_fifo_to_tty(uap);
1281
1282 spin_unlock(&uap->port.lock);
1283 tty_flip_buffer_push(&uap->port.state->port);
1284 /*
1285 * If we were temporarily out of DMA mode for a while,
1286 * attempt to switch back to DMA mode again.
1287 */
1288 if (pl011_dma_rx_available(uap)) {
1289 if (pl011_dma_rx_trigger_dma(uap)) {
1290 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1291 "fall back to interrupt mode again\n");
1292 uap->im |= UART011_RXIM;
1293 pl011_write(uap->im, uap, REG_IMSC);
1294 } else {
1295 #ifdef CONFIG_DMA_ENGINE
1296 /* Start Rx DMA poll */
1297 if (uap->dmarx.poll_rate) {
1298 uap->dmarx.last_jiffies = jiffies;
1299 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1300 mod_timer(&uap->dmarx.timer,
1301 jiffies +
1302 msecs_to_jiffies(uap->dmarx.poll_rate));
1303 }
1304 #endif
1305 }
1306 }
1307 spin_lock(&uap->port.lock);
1308 }
1309
1310 static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
1311 bool from_irq)
1312 {
1313 if (unlikely(!from_irq) &&
1314 pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1315 return false; /* unable to transmit character */
1316
1317 pl011_write(c, uap, REG_DR);
1318 uap->port.icount.tx++;
1319
1320 return true;
1321 }
1322
1323 static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)
1324 {
1325 struct circ_buf *xmit = &uap->port.state->xmit;
1326 int count = uap->fifosize >> 1;
1327
1328 if (uap->port.x_char) {
1329 if (!pl011_tx_char(uap, uap->port.x_char, from_irq))
1330 return;
1331 uap->port.x_char = 0;
1332 --count;
1333 }
1334 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1335 pl011_stop_tx(&uap->port);
1336 return;
1337 }
1338
1339 /* If we are using DMA mode, try to send some characters. */
1340 if (pl011_dma_tx_irq(uap))
1341 return;
1342
1343 do {
1344 if (likely(from_irq) && count-- == 0)
1345 break;
1346
1347 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq))
1348 break;
1349
1350 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1351 } while (!uart_circ_empty(xmit));
1352
1353 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1354 uart_write_wakeup(&uap->port);
1355
1356 if (uart_circ_empty(xmit))
1357 pl011_stop_tx(&uap->port);
1358 }
1359
1360 static void pl011_modem_status(struct uart_amba_port *uap)
1361 {
1362 unsigned int status, delta;
1363
1364 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1365
1366 delta = status ^ uap->old_status;
1367 uap->old_status = status;
1368
1369 if (!delta)
1370 return;
1371
1372 if (delta & UART01x_FR_DCD)
1373 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1374
1375 if (delta & UART01x_FR_DSR)
1376 uap->port.icount.dsr++;
1377
1378 if (delta & UART01x_FR_CTS)
1379 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
1380
1381 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1382 }
1383
1384 static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
1385 {
1386 unsigned int dummy_read;
1387
1388 if (!uap->vendor->cts_event_workaround)
1389 return;
1390
1391 /* workaround to make sure that all bits are unlocked.. */
1392 pl011_write(0x00, uap, REG_ICR);
1393
1394 /*
1395 * WA: introduce 26ns(1 uart clk) delay before W1C;
1396 * single apb access will incur 2 pclk(133.12Mhz) delay,
1397 * so add 2 dummy reads
1398 */
1399 dummy_read = pl011_read(uap, REG_ICR);
1400 dummy_read = pl011_read(uap, REG_ICR);
1401 }
1402
1403 static irqreturn_t pl011_int(int irq, void *dev_id)
1404 {
1405 struct uart_amba_port *uap = dev_id;
1406 unsigned long flags;
1407 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1408 u16 imsc;
1409 int handled = 0;
1410
1411 spin_lock_irqsave(&uap->port.lock, flags);
1412 imsc = pl011_read(uap, REG_IMSC);
1413 status = pl011_read(uap, REG_RIS) & imsc;
1414 if (status) {
1415 do {
1416 check_apply_cts_event_workaround(uap);
1417
1418 pl011_write(status & ~(UART011_TXIS|UART011_RTIS|
1419 UART011_RXIS),
1420 uap, REG_ICR);
1421
1422 if (status & (UART011_RTIS|UART011_RXIS)) {
1423 if (pl011_dma_rx_running(uap))
1424 pl011_dma_rx_irq(uap);
1425 else
1426 pl011_rx_chars(uap);
1427 }
1428 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1429 UART011_CTSMIS|UART011_RIMIS))
1430 pl011_modem_status(uap);
1431 if (status & UART011_TXIS)
1432 pl011_tx_chars(uap, true);
1433
1434 if (pass_counter-- == 0)
1435 break;
1436
1437 status = pl011_read(uap, REG_RIS) & imsc;
1438 } while (status != 0);
1439 handled = 1;
1440 }
1441
1442 spin_unlock_irqrestore(&uap->port.lock, flags);
1443
1444 return IRQ_RETVAL(handled);
1445 }
1446
1447 static unsigned int pl011_tx_empty(struct uart_port *port)
1448 {
1449 struct uart_amba_port *uap =
1450 container_of(port, struct uart_amba_port, port);
1451 unsigned int status = pl011_read(uap, REG_FR);
1452 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
1453 }
1454
1455 static unsigned int pl011_get_mctrl(struct uart_port *port)
1456 {
1457 struct uart_amba_port *uap =
1458 container_of(port, struct uart_amba_port, port);
1459 unsigned int result = 0;
1460 unsigned int status = pl011_read(uap, REG_FR);
1461
1462 #define TIOCMBIT(uartbit, tiocmbit) \
1463 if (status & uartbit) \
1464 result |= tiocmbit
1465
1466 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1467 TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR);
1468 TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS);
1469 TIOCMBIT(UART011_FR_RI, TIOCM_RNG);
1470 #undef TIOCMBIT
1471 return result;
1472 }
1473
1474 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1475 {
1476 struct uart_amba_port *uap =
1477 container_of(port, struct uart_amba_port, port);
1478 unsigned int cr;
1479
1480 cr = pl011_read(uap, REG_CR);
1481
1482 #define TIOCMBIT(tiocmbit, uartbit) \
1483 if (mctrl & tiocmbit) \
1484 cr |= uartbit; \
1485 else \
1486 cr &= ~uartbit
1487
1488 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1489 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1490 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1491 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1492 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
1493
1494 if (uap->autorts) {
1495 /* We need to disable auto-RTS if we want to turn RTS off */
1496 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1497 }
1498 #undef TIOCMBIT
1499
1500 pl011_write(cr, uap, REG_CR);
1501 }
1502
1503 static void pl011_break_ctl(struct uart_port *port, int break_state)
1504 {
1505 struct uart_amba_port *uap =
1506 container_of(port, struct uart_amba_port, port);
1507 unsigned long flags;
1508 unsigned int lcr_h;
1509
1510 spin_lock_irqsave(&uap->port.lock, flags);
1511 lcr_h = pl011_read(uap, uap->lcrh_tx);
1512 if (break_state == -1)
1513 lcr_h |= UART01x_LCRH_BRK;
1514 else
1515 lcr_h &= ~UART01x_LCRH_BRK;
1516 pl011_write(lcr_h, uap, uap->lcrh_tx);
1517 spin_unlock_irqrestore(&uap->port.lock, flags);
1518 }
1519
1520 #ifdef CONFIG_CONSOLE_POLL
1521
1522 static void pl011_quiesce_irqs(struct uart_port *port)
1523 {
1524 struct uart_amba_port *uap =
1525 container_of(port, struct uart_amba_port, port);
1526
1527 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);
1528 /*
1529 * There is no way to clear TXIM as this is "ready to transmit IRQ", so
1530 * we simply mask it. start_tx() will unmask it.
1531 *
1532 * Note we can race with start_tx(), and if the race happens, the
1533 * polling user might get another interrupt just after we clear it.
1534 * But it should be OK and can happen even w/o the race, e.g.
1535 * controller immediately got some new data and raised the IRQ.
1536 *
1537 * And whoever uses polling routines assumes that it manages the device
1538 * (including tx queue), so we're also fine with start_tx()'s caller
1539 * side.
1540 */
1541 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,
1542 REG_IMSC);
1543 }
1544
1545 static int pl011_get_poll_char(struct uart_port *port)
1546 {
1547 struct uart_amba_port *uap =
1548 container_of(port, struct uart_amba_port, port);
1549 unsigned int status;
1550
1551 /*
1552 * The caller might need IRQs lowered, e.g. if used with KDB NMI
1553 * debugger.
1554 */
1555 pl011_quiesce_irqs(port);
1556
1557 status = pl011_read(uap, REG_FR);
1558 if (status & UART01x_FR_RXFE)
1559 return NO_POLL_CHAR;
1560
1561 return pl011_read(uap, REG_DR);
1562 }
1563
1564 static void pl011_put_poll_char(struct uart_port *port,
1565 unsigned char ch)
1566 {
1567 struct uart_amba_port *uap =
1568 container_of(port, struct uart_amba_port, port);
1569
1570 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1571 barrier();
1572
1573 pl011_write(ch, uap, REG_DR);
1574 }
1575
1576 #endif /* CONFIG_CONSOLE_POLL */
1577
1578 static int pl011_hwinit(struct uart_port *port)
1579 {
1580 struct uart_amba_port *uap =
1581 container_of(port, struct uart_amba_port, port);
1582 int retval;
1583
1584 /* Optionaly enable pins to be muxed in and configured */
1585 pinctrl_pm_select_default_state(port->dev);
1586
1587 /*
1588 * Try to enable the clock producer.
1589 */
1590 retval = clk_prepare_enable(uap->clk);
1591 if (retval)
1592 return retval;
1593
1594 uap->port.uartclk = clk_get_rate(uap->clk);
1595
1596 /* Clear pending error and receive interrupts */
1597 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
1598 UART011_FEIS | UART011_RTIS | UART011_RXIS,
1599 uap, REG_ICR);
1600
1601 /*
1602 * Save interrupts enable mask, and enable RX interrupts in case if
1603 * the interrupt is used for NMI entry.
1604 */
1605 uap->im = pl011_read(uap, REG_IMSC);
1606 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC);
1607
1608 if (dev_get_platdata(uap->port.dev)) {
1609 struct amba_pl011_data *plat;
1610
1611 plat = dev_get_platdata(uap->port.dev);
1612 if (plat->init)
1613 plat->init();
1614 }
1615 return 0;
1616 }
1617
1618 static bool pl011_split_lcrh(const struct uart_amba_port *uap)
1619 {
1620 return pl011_reg_to_offset(uap, uap->lcrh_rx) !=
1621 pl011_reg_to_offset(uap, uap->lcrh_tx);
1622 }
1623
1624 static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
1625 {
1626 pl011_write(lcr_h, uap, uap->lcrh_rx);
1627 if (pl011_split_lcrh(uap)) {
1628 int i;
1629 /*
1630 * Wait 10 PCLKs before writing LCRH_TX register,
1631 * to get this delay write read only register 10 times
1632 */
1633 for (i = 0; i < 10; ++i)
1634 pl011_write(0xff, uap, REG_MIS);
1635 pl011_write(lcr_h, uap, uap->lcrh_tx);
1636 }
1637 }
1638
1639 static int pl011_allocate_irq(struct uart_amba_port *uap)
1640 {
1641 pl011_write(uap->im, uap, REG_IMSC);
1642
1643 return request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
1644 }
1645
1646 /*
1647 * Enable interrupts, only timeouts when using DMA
1648 * if initial RX DMA job failed, start in interrupt mode
1649 * as well.
1650 */
1651 static void pl011_enable_interrupts(struct uart_amba_port *uap)
1652 {
1653 spin_lock_irq(&uap->port.lock);
1654
1655 /* Clear out any spuriously appearing RX interrupts */
1656 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);
1657 uap->im = UART011_RTIM;
1658 if (!pl011_dma_rx_running(uap))
1659 uap->im |= UART011_RXIM;
1660 pl011_write(uap->im, uap, REG_IMSC);
1661 spin_unlock_irq(&uap->port.lock);
1662 }
1663
1664 static int pl011_startup(struct uart_port *port)
1665 {
1666 struct uart_amba_port *uap =
1667 container_of(port, struct uart_amba_port, port);
1668 unsigned int cr;
1669 int retval;
1670
1671 retval = pl011_hwinit(port);
1672 if (retval)
1673 goto clk_dis;
1674
1675 retval = pl011_allocate_irq(uap);
1676 if (retval)
1677 goto clk_dis;
1678
1679 pl011_write(uap->vendor->ifls, uap, REG_IFLS);
1680
1681 spin_lock_irq(&uap->port.lock);
1682
1683 /* restore RTS and DTR */
1684 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
1685 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
1686 pl011_write(cr, uap, REG_CR);
1687
1688 spin_unlock_irq(&uap->port.lock);
1689
1690 /*
1691 * initialise the old status of the modem signals
1692 */
1693 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1694
1695 /* Startup DMA */
1696 pl011_dma_startup(uap);
1697
1698 pl011_enable_interrupts(uap);
1699
1700 return 0;
1701
1702 clk_dis:
1703 clk_disable_unprepare(uap->clk);
1704 return retval;
1705 }
1706
1707 static int sbsa_uart_startup(struct uart_port *port)
1708 {
1709 struct uart_amba_port *uap =
1710 container_of(port, struct uart_amba_port, port);
1711 int retval;
1712
1713 retval = pl011_hwinit(port);
1714 if (retval)
1715 return retval;
1716
1717 retval = pl011_allocate_irq(uap);
1718 if (retval)
1719 return retval;
1720
1721 /* The SBSA UART does not support any modem status lines. */
1722 uap->old_status = 0;
1723
1724 pl011_enable_interrupts(uap);
1725
1726 return 0;
1727 }
1728
1729 static void pl011_shutdown_channel(struct uart_amba_port *uap,
1730 unsigned int lcrh)
1731 {
1732 unsigned long val;
1733
1734 val = pl011_read(uap, lcrh);
1735 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1736 pl011_write(val, uap, lcrh);
1737 }
1738
1739 /*
1740 * disable the port. It should not disable RTS and DTR.
1741 * Also RTS and DTR state should be preserved to restore
1742 * it during startup().
1743 */
1744 static void pl011_disable_uart(struct uart_amba_port *uap)
1745 {
1746 unsigned int cr;
1747
1748 uap->autorts = false;
1749 spin_lock_irq(&uap->port.lock);
1750 cr = pl011_read(uap, REG_CR);
1751 uap->old_cr = cr;
1752 cr &= UART011_CR_RTS | UART011_CR_DTR;
1753 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1754 pl011_write(cr, uap, REG_CR);
1755 spin_unlock_irq(&uap->port.lock);
1756
1757 /*
1758 * disable break condition and fifos
1759 */
1760 pl011_shutdown_channel(uap, uap->lcrh_rx);
1761 if (pl011_split_lcrh(uap))
1762 pl011_shutdown_channel(uap, uap->lcrh_tx);
1763 }
1764
1765 static void pl011_disable_interrupts(struct uart_amba_port *uap)
1766 {
1767 spin_lock_irq(&uap->port.lock);
1768
1769 /* mask all interrupts and clear all pending ones */
1770 uap->im = 0;
1771 pl011_write(uap->im, uap, REG_IMSC);
1772 pl011_write(0xffff, uap, REG_ICR);
1773
1774 spin_unlock_irq(&uap->port.lock);
1775 }
1776
1777 static void pl011_shutdown(struct uart_port *port)
1778 {
1779 struct uart_amba_port *uap =
1780 container_of(port, struct uart_amba_port, port);
1781
1782 pl011_disable_interrupts(uap);
1783
1784 pl011_dma_shutdown(uap);
1785
1786 free_irq(uap->port.irq, uap);
1787
1788 pl011_disable_uart(uap);
1789
1790 /*
1791 * Shut down the clock producer
1792 */
1793 clk_disable_unprepare(uap->clk);
1794 /* Optionally let pins go into sleep states */
1795 pinctrl_pm_select_sleep_state(port->dev);
1796
1797 if (dev_get_platdata(uap->port.dev)) {
1798 struct amba_pl011_data *plat;
1799
1800 plat = dev_get_platdata(uap->port.dev);
1801 if (plat->exit)
1802 plat->exit();
1803 }
1804
1805 if (uap->port.ops->flush_buffer)
1806 uap->port.ops->flush_buffer(port);
1807 }
1808
1809 static void sbsa_uart_shutdown(struct uart_port *port)
1810 {
1811 struct uart_amba_port *uap =
1812 container_of(port, struct uart_amba_port, port);
1813
1814 pl011_disable_interrupts(uap);
1815
1816 free_irq(uap->port.irq, uap);
1817
1818 if (uap->port.ops->flush_buffer)
1819 uap->port.ops->flush_buffer(port);
1820 }
1821
1822 static void
1823 pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios)
1824 {
1825 port->read_status_mask = UART011_DR_OE | 255;
1826 if (termios->c_iflag & INPCK)
1827 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1828 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1829 port->read_status_mask |= UART011_DR_BE;
1830
1831 /*
1832 * Characters to ignore
1833 */
1834 port->ignore_status_mask = 0;
1835 if (termios->c_iflag & IGNPAR)
1836 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1837 if (termios->c_iflag & IGNBRK) {
1838 port->ignore_status_mask |= UART011_DR_BE;
1839 /*
1840 * If we're ignoring parity and break indicators,
1841 * ignore overruns too (for real raw support).
1842 */
1843 if (termios->c_iflag & IGNPAR)
1844 port->ignore_status_mask |= UART011_DR_OE;
1845 }
1846
1847 /*
1848 * Ignore all characters if CREAD is not set.
1849 */
1850 if ((termios->c_cflag & CREAD) == 0)
1851 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1852 }
1853
1854 static void
1855 pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1856 struct ktermios *old)
1857 {
1858 struct uart_amba_port *uap =
1859 container_of(port, struct uart_amba_port, port);
1860 unsigned int lcr_h, old_cr;
1861 unsigned long flags;
1862 unsigned int baud, quot, clkdiv;
1863
1864 if (uap->vendor->oversampling)
1865 clkdiv = 8;
1866 else
1867 clkdiv = 16;
1868
1869 /*
1870 * Ask the core to calculate the divisor for us.
1871 */
1872 baud = uart_get_baud_rate(port, termios, old, 0,
1873 port->uartclk / clkdiv);
1874 #ifdef CONFIG_DMA_ENGINE
1875 /*
1876 * Adjust RX DMA polling rate with baud rate if not specified.
1877 */
1878 if (uap->dmarx.auto_poll_rate)
1879 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
1880 #endif
1881
1882 if (baud > port->uartclk/16)
1883 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1884 else
1885 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1886
1887 switch (termios->c_cflag & CSIZE) {
1888 case CS5:
1889 lcr_h = UART01x_LCRH_WLEN_5;
1890 break;
1891 case CS6:
1892 lcr_h = UART01x_LCRH_WLEN_6;
1893 break;
1894 case CS7:
1895 lcr_h = UART01x_LCRH_WLEN_7;
1896 break;
1897 default: // CS8
1898 lcr_h = UART01x_LCRH_WLEN_8;
1899 break;
1900 }
1901 if (termios->c_cflag & CSTOPB)
1902 lcr_h |= UART01x_LCRH_STP2;
1903 if (termios->c_cflag & PARENB) {
1904 lcr_h |= UART01x_LCRH_PEN;
1905 if (!(termios->c_cflag & PARODD))
1906 lcr_h |= UART01x_LCRH_EPS;
1907 }
1908 if (uap->fifosize > 1)
1909 lcr_h |= UART01x_LCRH_FEN;
1910
1911 spin_lock_irqsave(&port->lock, flags);
1912
1913 /*
1914 * Update the per-port timeout.
1915 */
1916 uart_update_timeout(port, termios->c_cflag, baud);
1917
1918 pl011_setup_status_masks(port, termios);
1919
1920 if (UART_ENABLE_MS(port, termios->c_cflag))
1921 pl011_enable_ms(port);
1922
1923 /* first, disable everything */
1924 old_cr = pl011_read(uap, REG_CR);
1925 pl011_write(0, uap, REG_CR);
1926
1927 if (termios->c_cflag & CRTSCTS) {
1928 if (old_cr & UART011_CR_RTS)
1929 old_cr |= UART011_CR_RTSEN;
1930
1931 old_cr |= UART011_CR_CTSEN;
1932 uap->autorts = true;
1933 } else {
1934 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
1935 uap->autorts = false;
1936 }
1937
1938 if (uap->vendor->oversampling) {
1939 if (baud > port->uartclk / 16)
1940 old_cr |= ST_UART011_CR_OVSFACT;
1941 else
1942 old_cr &= ~ST_UART011_CR_OVSFACT;
1943 }
1944
1945 /*
1946 * Workaround for the ST Micro oversampling variants to
1947 * increase the bitrate slightly, by lowering the divisor,
1948 * to avoid delayed sampling of start bit at high speeds,
1949 * else we see data corruption.
1950 */
1951 if (uap->vendor->oversampling) {
1952 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
1953 quot -= 1;
1954 else if ((baud > 3250000) && (quot > 2))
1955 quot -= 2;
1956 }
1957 /* Set baud rate */
1958 pl011_write(quot & 0x3f, uap, REG_FBRD);
1959 pl011_write(quot >> 6, uap, REG_IBRD);
1960
1961 /*
1962 * ----------v----------v----------v----------v-----
1963 * NOTE: lcrh_tx and lcrh_rx MUST BE WRITTEN AFTER
1964 * REG_FBRD & REG_IBRD.
1965 * ----------^----------^----------^----------^-----
1966 */
1967 pl011_write_lcr_h(uap, lcr_h);
1968 pl011_write(old_cr, uap, REG_CR);
1969
1970 spin_unlock_irqrestore(&port->lock, flags);
1971 }
1972
1973 static void
1974 sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1975 struct ktermios *old)
1976 {
1977 struct uart_amba_port *uap =
1978 container_of(port, struct uart_amba_port, port);
1979 unsigned long flags;
1980
1981 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud);
1982
1983 /* The SBSA UART only supports 8n1 without hardware flow control. */
1984 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
1985 termios->c_cflag &= ~(CMSPAR | CRTSCTS);
1986 termios->c_cflag |= CS8 | CLOCAL;
1987
1988 spin_lock_irqsave(&port->lock, flags);
1989 uart_update_timeout(port, CS8, uap->fixed_baud);
1990 pl011_setup_status_masks(port, termios);
1991 spin_unlock_irqrestore(&port->lock, flags);
1992 }
1993
1994 static const char *pl011_type(struct uart_port *port)
1995 {
1996 struct uart_amba_port *uap =
1997 container_of(port, struct uart_amba_port, port);
1998 return uap->port.type == PORT_AMBA ? uap->type : NULL;
1999 }
2000
2001 /*
2002 * Release the memory region(s) being used by 'port'
2003 */
2004 static void pl011_release_port(struct uart_port *port)
2005 {
2006 release_mem_region(port->mapbase, SZ_4K);
2007 }
2008
2009 /*
2010 * Request the memory region(s) being used by 'port'
2011 */
2012 static int pl011_request_port(struct uart_port *port)
2013 {
2014 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
2015 != NULL ? 0 : -EBUSY;
2016 }
2017
2018 /*
2019 * Configure/autoconfigure the port.
2020 */
2021 static void pl011_config_port(struct uart_port *port, int flags)
2022 {
2023 if (flags & UART_CONFIG_TYPE) {
2024 port->type = PORT_AMBA;
2025 pl011_request_port(port);
2026 }
2027 }
2028
2029 /*
2030 * verify the new serial_struct (for TIOCSSERIAL).
2031 */
2032 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
2033 {
2034 int ret = 0;
2035 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
2036 ret = -EINVAL;
2037 if (ser->irq < 0 || ser->irq >= nr_irqs)
2038 ret = -EINVAL;
2039 if (ser->baud_base < 9600)
2040 ret = -EINVAL;
2041 return ret;
2042 }
2043
2044 static struct uart_ops amba_pl011_pops = {
2045 .tx_empty = pl011_tx_empty,
2046 .set_mctrl = pl011_set_mctrl,
2047 .get_mctrl = pl011_get_mctrl,
2048 .stop_tx = pl011_stop_tx,
2049 .start_tx = pl011_start_tx,
2050 .stop_rx = pl011_stop_rx,
2051 .enable_ms = pl011_enable_ms,
2052 .break_ctl = pl011_break_ctl,
2053 .startup = pl011_startup,
2054 .shutdown = pl011_shutdown,
2055 .flush_buffer = pl011_dma_flush_buffer,
2056 .set_termios = pl011_set_termios,
2057 .type = pl011_type,
2058 .release_port = pl011_release_port,
2059 .request_port = pl011_request_port,
2060 .config_port = pl011_config_port,
2061 .verify_port = pl011_verify_port,
2062 #ifdef CONFIG_CONSOLE_POLL
2063 .poll_init = pl011_hwinit,
2064 .poll_get_char = pl011_get_poll_char,
2065 .poll_put_char = pl011_put_poll_char,
2066 #endif
2067 };
2068
2069 static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
2070 {
2071 }
2072
2073 static unsigned int sbsa_uart_get_mctrl(struct uart_port *port)
2074 {
2075 return 0;
2076 }
2077
2078 static const struct uart_ops sbsa_uart_pops = {
2079 .tx_empty = pl011_tx_empty,
2080 .set_mctrl = sbsa_uart_set_mctrl,
2081 .get_mctrl = sbsa_uart_get_mctrl,
2082 .stop_tx = pl011_stop_tx,
2083 .start_tx = pl011_start_tx,
2084 .stop_rx = pl011_stop_rx,
2085 .startup = sbsa_uart_startup,
2086 .shutdown = sbsa_uart_shutdown,
2087 .set_termios = sbsa_uart_set_termios,
2088 .type = pl011_type,
2089 .release_port = pl011_release_port,
2090 .request_port = pl011_request_port,
2091 .config_port = pl011_config_port,
2092 .verify_port = pl011_verify_port,
2093 #ifdef CONFIG_CONSOLE_POLL
2094 .poll_init = pl011_hwinit,
2095 .poll_get_char = pl011_get_poll_char,
2096 .poll_put_char = pl011_put_poll_char,
2097 #endif
2098 };
2099
2100 static struct uart_amba_port *amba_ports[UART_NR];
2101
2102 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
2103
2104 static void pl011_console_putchar(struct uart_port *port, int ch)
2105 {
2106 struct uart_amba_port *uap =
2107 container_of(port, struct uart_amba_port, port);
2108
2109 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2110 barrier();
2111 pl011_write(ch, uap, REG_DR);
2112 }
2113
2114 static void
2115 pl011_console_write(struct console *co, const char *s, unsigned int count)
2116 {
2117 struct uart_amba_port *uap = amba_ports[co->index];
2118 unsigned int status, old_cr = 0, new_cr;
2119 unsigned long flags;
2120 int locked = 1;
2121
2122 clk_enable(uap->clk);
2123
2124 local_irq_save(flags);
2125 if (uap->port.sysrq)
2126 locked = 0;
2127 else if (oops_in_progress)
2128 locked = spin_trylock(&uap->port.lock);
2129 else
2130 spin_lock(&uap->port.lock);
2131
2132 /*
2133 * First save the CR then disable the interrupts
2134 */
2135 if (!uap->vendor->always_enabled) {
2136 old_cr = pl011_read(uap, REG_CR);
2137 new_cr = old_cr & ~UART011_CR_CTSEN;
2138 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
2139 pl011_write(new_cr, uap, REG_CR);
2140 }
2141
2142 uart_console_write(&uap->port, s, count, pl011_console_putchar);
2143
2144 /*
2145 * Finally, wait for transmitter to become empty
2146 * and restore the TCR
2147 */
2148 do {
2149 status = pl011_read(uap, REG_FR);
2150 } while (status & UART01x_FR_BUSY);
2151 if (!uap->vendor->always_enabled)
2152 pl011_write(old_cr, uap, REG_CR);
2153
2154 if (locked)
2155 spin_unlock(&uap->port.lock);
2156 local_irq_restore(flags);
2157
2158 clk_disable(uap->clk);
2159 }
2160
2161 static void __init
2162 pl011_console_get_options(struct uart_amba_port *uap, int *baud,
2163 int *parity, int *bits)
2164 {
2165 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) {
2166 unsigned int lcr_h, ibrd, fbrd;
2167
2168 lcr_h = pl011_read(uap, uap->lcrh_tx);
2169
2170 *parity = 'n';
2171 if (lcr_h & UART01x_LCRH_PEN) {
2172 if (lcr_h & UART01x_LCRH_EPS)
2173 *parity = 'e';
2174 else
2175 *parity = 'o';
2176 }
2177
2178 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
2179 *bits = 7;
2180 else
2181 *bits = 8;
2182
2183 ibrd = pl011_read(uap, REG_IBRD);
2184 fbrd = pl011_read(uap, REG_FBRD);
2185
2186 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
2187
2188 if (uap->vendor->oversampling) {
2189 if (pl011_read(uap, REG_CR)
2190 & ST_UART011_CR_OVSFACT)
2191 *baud *= 2;
2192 }
2193 }
2194 }
2195
2196 static int __init pl011_console_setup(struct console *co, char *options)
2197 {
2198 struct uart_amba_port *uap;
2199 int baud = 38400;
2200 int bits = 8;
2201 int parity = 'n';
2202 int flow = 'n';
2203 int ret;
2204
2205 /*
2206 * Check whether an invalid uart number has been specified, and
2207 * if so, search for the first available port that does have
2208 * console support.
2209 */
2210 if (co->index >= UART_NR)
2211 co->index = 0;
2212 uap = amba_ports[co->index];
2213 if (!uap)
2214 return -ENODEV;
2215
2216 /* Allow pins to be muxed in and configured */
2217 pinctrl_pm_select_default_state(uap->port.dev);
2218
2219 ret = clk_prepare(uap->clk);
2220 if (ret)
2221 return ret;
2222
2223 if (dev_get_platdata(uap->port.dev)) {
2224 struct amba_pl011_data *plat;
2225
2226 plat = dev_get_platdata(uap->port.dev);
2227 if (plat->init)
2228 plat->init();
2229 }
2230
2231 uap->port.uartclk = clk_get_rate(uap->clk);
2232
2233 if (uap->vendor->fixed_options) {
2234 baud = uap->fixed_baud;
2235 } else {
2236 if (options)
2237 uart_parse_options(options,
2238 &baud, &parity, &bits, &flow);
2239 else
2240 pl011_console_get_options(uap, &baud, &parity, &bits);
2241 }
2242
2243 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2244 }
2245
2246 static struct uart_driver amba_reg;
2247 static struct console amba_console = {
2248 .name = "ttyAMA",
2249 .write = pl011_console_write,
2250 .device = uart_console_device,
2251 .setup = pl011_console_setup,
2252 .flags = CON_PRINTBUFFER,
2253 .index = -1,
2254 .data = &amba_reg,
2255 };
2256
2257 #define AMBA_CONSOLE (&amba_console)
2258
2259 static void pl011_putc(struct uart_port *port, int c)
2260 {
2261 while (readl(port->membase + REG_FR) & UART01x_FR_TXFF)
2262 ;
2263 writeb(c, port->membase + REG_DR);
2264 while (readl(port->membase + REG_FR) & UART01x_FR_BUSY)
2265 ;
2266 }
2267
2268 static void pl011_early_write(struct console *con, const char *s, unsigned n)
2269 {
2270 struct earlycon_device *dev = con->data;
2271
2272 uart_console_write(&dev->port, s, n, pl011_putc);
2273 }
2274
2275 static int __init pl011_early_console_setup(struct earlycon_device *device,
2276 const char *opt)
2277 {
2278 if (!device->port.membase)
2279 return -ENODEV;
2280
2281 device->con->write = pl011_early_write;
2282 return 0;
2283 }
2284 EARLYCON_DECLARE(pl011, pl011_early_console_setup);
2285 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
2286
2287 #else
2288 #define AMBA_CONSOLE NULL
2289 #endif
2290
2291 static struct uart_driver amba_reg = {
2292 .owner = THIS_MODULE,
2293 .driver_name = "ttyAMA",
2294 .dev_name = "ttyAMA",
2295 .major = SERIAL_AMBA_MAJOR,
2296 .minor = SERIAL_AMBA_MINOR,
2297 .nr = UART_NR,
2298 .cons = AMBA_CONSOLE,
2299 };
2300
2301 static int pl011_probe_dt_alias(int index, struct device *dev)
2302 {
2303 struct device_node *np;
2304 static bool seen_dev_with_alias = false;
2305 static bool seen_dev_without_alias = false;
2306 int ret = index;
2307
2308 if (!IS_ENABLED(CONFIG_OF))
2309 return ret;
2310
2311 np = dev->of_node;
2312 if (!np)
2313 return ret;
2314
2315 ret = of_alias_get_id(np, "serial");
2316 if (IS_ERR_VALUE(ret)) {
2317 seen_dev_without_alias = true;
2318 ret = index;
2319 } else {
2320 seen_dev_with_alias = true;
2321 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
2322 dev_warn(dev, "requested serial port %d not available.\n", ret);
2323 ret = index;
2324 }
2325 }
2326
2327 if (seen_dev_with_alias && seen_dev_without_alias)
2328 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2329
2330 return ret;
2331 }
2332
2333 /* unregisters the driver also if no more ports are left */
2334 static void pl011_unregister_port(struct uart_amba_port *uap)
2335 {
2336 int i;
2337 bool busy = false;
2338
2339 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2340 if (amba_ports[i] == uap)
2341 amba_ports[i] = NULL;
2342 else if (amba_ports[i])
2343 busy = true;
2344 }
2345 pl011_dma_remove(uap);
2346 if (!busy)
2347 uart_unregister_driver(&amba_reg);
2348 }
2349
2350 static int pl011_find_free_port(void)
2351 {
2352 int i;
2353
2354 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2355 if (amba_ports[i] == NULL)
2356 return i;
2357
2358 return -EBUSY;
2359 }
2360
2361 static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap,
2362 struct resource *mmiobase, int index)
2363 {
2364 void __iomem *base;
2365
2366 base = devm_ioremap_resource(dev, mmiobase);
2367 if (IS_ERR(base))
2368 return PTR_ERR(base);
2369
2370 index = pl011_probe_dt_alias(index, dev);
2371
2372 uap->old_cr = 0;
2373 uap->port.dev = dev;
2374 uap->port.mapbase = mmiobase->start;
2375 uap->port.membase = base;
2376 uap->port.iotype = UPIO_MEM;
2377 uap->port.fifosize = uap->fifosize;
2378 uap->port.flags = UPF_BOOT_AUTOCONF;
2379 uap->port.line = index;
2380
2381 amba_ports[index] = uap;
2382
2383 return 0;
2384 }
2385
2386 static int pl011_register_port(struct uart_amba_port *uap)
2387 {
2388 int ret;
2389
2390 /* Ensure interrupts from this UART are masked and cleared */
2391 pl011_write(0, uap, REG_IMSC);
2392 pl011_write(0xffff, uap, REG_ICR);
2393
2394 if (!amba_reg.state) {
2395 ret = uart_register_driver(&amba_reg);
2396 if (ret < 0) {
2397 dev_err(uap->port.dev,
2398 "Failed to register AMBA-PL011 driver\n");
2399 return ret;
2400 }
2401 }
2402
2403 ret = uart_add_one_port(&amba_reg, &uap->port);
2404 if (ret)
2405 pl011_unregister_port(uap);
2406
2407 return ret;
2408 }
2409
2410 static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2411 {
2412 struct uart_amba_port *uap;
2413 struct vendor_data *vendor = id->data;
2414 int portnr, ret;
2415
2416 portnr = pl011_find_free_port();
2417 if (portnr < 0)
2418 return portnr;
2419
2420 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2421 GFP_KERNEL);
2422 if (!uap)
2423 return -ENOMEM;
2424
2425 uap->clk = devm_clk_get(&dev->dev, NULL);
2426 if (IS_ERR(uap->clk))
2427 return PTR_ERR(uap->clk);
2428
2429 uap->reg_offset = pl011_std_offsets;
2430 uap->vendor = vendor;
2431 uap->lcrh_rx = vendor->lcrh_rx;
2432 uap->lcrh_tx = vendor->lcrh_tx;
2433 uap->fifosize = vendor->get_fifosize(dev);
2434 uap->port.irq = dev->irq[0];
2435 uap->port.ops = &amba_pl011_pops;
2436
2437 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2438
2439 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);
2440 if (ret)
2441 return ret;
2442
2443 amba_set_drvdata(dev, uap);
2444
2445 return pl011_register_port(uap);
2446 }
2447
2448 static int pl011_remove(struct amba_device *dev)
2449 {
2450 struct uart_amba_port *uap = amba_get_drvdata(dev);
2451
2452 uart_remove_one_port(&amba_reg, &uap->port);
2453 pl011_unregister_port(uap);
2454 return 0;
2455 }
2456
2457 #ifdef CONFIG_PM_SLEEP
2458 static int pl011_suspend(struct device *dev)
2459 {
2460 struct uart_amba_port *uap = dev_get_drvdata(dev);
2461
2462 if (!uap)
2463 return -EINVAL;
2464
2465 return uart_suspend_port(&amba_reg, &uap->port);
2466 }
2467
2468 static int pl011_resume(struct device *dev)
2469 {
2470 struct uart_amba_port *uap = dev_get_drvdata(dev);
2471
2472 if (!uap)
2473 return -EINVAL;
2474
2475 return uart_resume_port(&amba_reg, &uap->port);
2476 }
2477 #endif
2478
2479 static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume);
2480
2481 static int sbsa_uart_probe(struct platform_device *pdev)
2482 {
2483 struct uart_amba_port *uap;
2484 struct resource *r;
2485 int portnr, ret;
2486 int baudrate;
2487
2488 /*
2489 * Check the mandatory baud rate parameter in the DT node early
2490 * so that we can easily exit with the error.
2491 */
2492 if (pdev->dev.of_node) {
2493 struct device_node *np = pdev->dev.of_node;
2494
2495 ret = of_property_read_u32(np, "current-speed", &baudrate);
2496 if (ret)
2497 return ret;
2498 } else {
2499 baudrate = 115200;
2500 }
2501
2502 portnr = pl011_find_free_port();
2503 if (portnr < 0)
2504 return portnr;
2505
2506 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),
2507 GFP_KERNEL);
2508 if (!uap)
2509 return -ENOMEM;
2510
2511 uap->reg_offset = pl011_std_offsets;
2512 uap->vendor = &vendor_sbsa;
2513 uap->fifosize = 32;
2514 uap->port.irq = platform_get_irq(pdev, 0);
2515 uap->port.ops = &sbsa_uart_pops;
2516 uap->fixed_baud = baudrate;
2517
2518 snprintf(uap->type, sizeof(uap->type), "SBSA");
2519
2520 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2521
2522 ret = pl011_setup_port(&pdev->dev, uap, r, portnr);
2523 if (ret)
2524 return ret;
2525
2526 platform_set_drvdata(pdev, uap);
2527
2528 return pl011_register_port(uap);
2529 }
2530
2531 static int sbsa_uart_remove(struct platform_device *pdev)
2532 {
2533 struct uart_amba_port *uap = platform_get_drvdata(pdev);
2534
2535 uart_remove_one_port(&amba_reg, &uap->port);
2536 pl011_unregister_port(uap);
2537 return 0;
2538 }
2539
2540 static const struct of_device_id sbsa_uart_of_match[] = {
2541 { .compatible = "arm,sbsa-uart", },
2542 {},
2543 };
2544 MODULE_DEVICE_TABLE(of, sbsa_uart_of_match);
2545
2546 static const struct acpi_device_id sbsa_uart_acpi_match[] = {
2547 { "ARMH0011", 0 },
2548 {},
2549 };
2550 MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match);
2551
2552 static struct platform_driver arm_sbsa_uart_platform_driver = {
2553 .probe = sbsa_uart_probe,
2554 .remove = sbsa_uart_remove,
2555 .driver = {
2556 .name = "sbsa-uart",
2557 .of_match_table = of_match_ptr(sbsa_uart_of_match),
2558 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match),
2559 },
2560 };
2561
2562 static struct amba_id pl011_ids[] = {
2563 {
2564 .id = 0x00041011,
2565 .mask = 0x000fffff,
2566 .data = &vendor_arm,
2567 },
2568 {
2569 .id = 0x00380802,
2570 .mask = 0x00ffffff,
2571 .data = &vendor_st,
2572 },
2573 { 0, 0 },
2574 };
2575
2576 MODULE_DEVICE_TABLE(amba, pl011_ids);
2577
2578 static struct amba_driver pl011_driver = {
2579 .drv = {
2580 .name = "uart-pl011",
2581 .pm = &pl011_dev_pm_ops,
2582 },
2583 .id_table = pl011_ids,
2584 .probe = pl011_probe,
2585 .remove = pl011_remove,
2586 };
2587
2588 static int __init pl011_init(void)
2589 {
2590 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2591
2592 if (platform_driver_register(&arm_sbsa_uart_platform_driver))
2593 pr_warn("could not register SBSA UART platform driver\n");
2594 return amba_driver_register(&pl011_driver);
2595 }
2596
2597 static void __exit pl011_exit(void)
2598 {
2599 platform_driver_unregister(&arm_sbsa_uart_platform_driver);
2600 amba_driver_unregister(&pl011_driver);
2601 }
2602
2603 /*
2604 * While this can be a module, if builtin it's most likely the console
2605 * So let's leave module_exit but move module_init to an earlier place
2606 */
2607 arch_initcall(pl011_init);
2608 module_exit(pl011_exit);
2609
2610 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2611 MODULE_DESCRIPTION("ARM AMBA serial port driver");
2612 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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