2 * Driver for AMBA serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 * Copyright (C) 2010 ST-Ericsson SA
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 * This is a generic driver for ARM AMBA-type serial ports. They
25 * have a lot of 16550-like features, but are not register compatible.
26 * Note that although they do have CTS, DCD and DSR inputs, they do
27 * not have an RI input, nor do they have DTR or RTS outputs. If
28 * required, these have to be supplied via some other means (eg, GPIO)
29 * and hooked into this driver.
32 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
36 #include <linux/module.h>
37 #include <linux/ioport.h>
38 #include <linux/init.h>
39 #include <linux/console.h>
40 #include <linux/sysrq.h>
41 #include <linux/device.h>
42 #include <linux/tty.h>
43 #include <linux/tty_flip.h>
44 #include <linux/serial_core.h>
45 #include <linux/serial.h>
46 #include <linux/amba/bus.h>
47 #include <linux/amba/serial.h>
48 #include <linux/clk.h>
49 #include <linux/slab.h>
50 #include <linux/dmaengine.h>
51 #include <linux/dma-mapping.h>
52 #include <linux/scatterlist.h>
53 #include <linux/delay.h>
54 #include <linux/types.h>
55 #include <linux/pinctrl/consumer.h>
58 #include <asm/sizes.h>
62 #define SERIAL_AMBA_MAJOR 204
63 #define SERIAL_AMBA_MINOR 64
64 #define SERIAL_AMBA_NR UART_NR
66 #define AMBA_ISR_PASS_LIMIT 256
68 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
69 #define UART_DUMMY_DR_RX (1 << 16)
71 /* There is by now at least one vendor with differing details, so handle it */
74 unsigned int fifosize
;
78 bool interrupt_may_hang
; /* vendor-specific */
80 bool cts_event_workaround
;
83 static struct vendor_data vendor_arm
= {
84 .ifls
= UART011_IFLS_RX4_8
|UART011_IFLS_TX4_8
,
86 .lcrh_tx
= UART011_LCRH
,
87 .lcrh_rx
= UART011_LCRH
,
88 .oversampling
= false,
89 .dma_threshold
= false,
90 .cts_event_workaround
= false,
93 static struct vendor_data vendor_st
= {
94 .ifls
= UART011_IFLS_RX_HALF
|UART011_IFLS_TX_HALF
,
96 .lcrh_tx
= ST_UART011_LCRH_TX
,
97 .lcrh_rx
= ST_UART011_LCRH_RX
,
99 .interrupt_may_hang
= true,
100 .dma_threshold
= true,
101 .cts_event_workaround
= true,
104 static struct uart_amba_port
*amba_ports
[UART_NR
];
106 /* Deals with DMA transactions */
109 struct scatterlist sg
;
113 struct pl011_dmarx_data
{
114 struct dma_chan
*chan
;
115 struct completion complete
;
117 struct pl011_sgbuf sgbuf_a
;
118 struct pl011_sgbuf sgbuf_b
;
123 struct pl011_dmatx_data
{
124 struct dma_chan
*chan
;
125 struct scatterlist sg
;
131 * We wrap our port structure around the generic uart_port.
133 struct uart_amba_port
{
134 struct uart_port port
;
136 const struct vendor_data
*vendor
;
137 unsigned int dmacr
; /* dma control reg */
138 unsigned int im
; /* interrupt mask */
139 unsigned int old_status
;
140 unsigned int fifosize
; /* vendor-specific */
141 unsigned int lcrh_tx
; /* vendor-specific */
142 unsigned int lcrh_rx
; /* vendor-specific */
143 unsigned int old_cr
; /* state during shutdown */
146 bool interrupt_may_hang
; /* vendor-specific */
147 #ifdef CONFIG_DMA_ENGINE
151 struct pl011_dmarx_data dmarx
;
152 struct pl011_dmatx_data dmatx
;
157 * Reads up to 256 characters from the FIFO or until it's empty and
158 * inserts them into the TTY layer. Returns the number of characters
159 * read from the FIFO.
161 static int pl011_fifo_to_tty(struct uart_amba_port
*uap
)
164 unsigned int flag
, max_count
= 256;
167 while (max_count
--) {
168 status
= readw(uap
->port
.membase
+ UART01x_FR
);
169 if (status
& UART01x_FR_RXFE
)
172 /* Take chars from the FIFO and update status */
173 ch
= readw(uap
->port
.membase
+ UART01x_DR
) |
176 uap
->port
.icount
.rx
++;
179 if (unlikely(ch
& UART_DR_ERROR
)) {
180 if (ch
& UART011_DR_BE
) {
181 ch
&= ~(UART011_DR_FE
| UART011_DR_PE
);
182 uap
->port
.icount
.brk
++;
183 if (uart_handle_break(&uap
->port
))
185 } else if (ch
& UART011_DR_PE
)
186 uap
->port
.icount
.parity
++;
187 else if (ch
& UART011_DR_FE
)
188 uap
->port
.icount
.frame
++;
189 if (ch
& UART011_DR_OE
)
190 uap
->port
.icount
.overrun
++;
192 ch
&= uap
->port
.read_status_mask
;
194 if (ch
& UART011_DR_BE
)
196 else if (ch
& UART011_DR_PE
)
198 else if (ch
& UART011_DR_FE
)
202 if (uart_handle_sysrq_char(&uap
->port
, ch
& 255))
205 uart_insert_char(&uap
->port
, ch
, UART011_DR_OE
, ch
, flag
);
213 * All the DMA operation mode stuff goes inside this ifdef.
214 * This assumes that you have a generic DMA device interface,
215 * no custom DMA interfaces are supported.
217 #ifdef CONFIG_DMA_ENGINE
219 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE
221 static int pl011_sgbuf_init(struct dma_chan
*chan
, struct pl011_sgbuf
*sg
,
222 enum dma_data_direction dir
)
224 sg
->buf
= kmalloc(PL011_DMA_BUFFER_SIZE
, GFP_KERNEL
);
228 sg_init_one(&sg
->sg
, sg
->buf
, PL011_DMA_BUFFER_SIZE
);
230 if (dma_map_sg(chan
->device
->dev
, &sg
->sg
, 1, dir
) != 1) {
237 static void pl011_sgbuf_free(struct dma_chan
*chan
, struct pl011_sgbuf
*sg
,
238 enum dma_data_direction dir
)
241 dma_unmap_sg(chan
->device
->dev
, &sg
->sg
, 1, dir
);
246 static void pl011_dma_probe_initcall(struct uart_amba_port
*uap
)
248 /* DMA is the sole user of the platform data right now */
249 struct amba_pl011_data
*plat
= uap
->port
.dev
->platform_data
;
250 struct dma_slave_config tx_conf
= {
251 .dst_addr
= uap
->port
.mapbase
+ UART01x_DR
,
252 .dst_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
,
253 .direction
= DMA_MEM_TO_DEV
,
254 .dst_maxburst
= uap
->fifosize
>> 1,
257 struct dma_chan
*chan
;
260 /* We need platform data */
261 if (!plat
|| !plat
->dma_filter
) {
262 dev_info(uap
->port
.dev
, "no DMA platform data\n");
266 /* Try to acquire a generic DMA engine slave TX channel */
268 dma_cap_set(DMA_SLAVE
, mask
);
270 chan
= dma_request_channel(mask
, plat
->dma_filter
, plat
->dma_tx_param
);
272 dev_err(uap
->port
.dev
, "no TX DMA channel!\n");
276 dmaengine_slave_config(chan
, &tx_conf
);
277 uap
->dmatx
.chan
= chan
;
279 dev_info(uap
->port
.dev
, "DMA channel TX %s\n",
280 dma_chan_name(uap
->dmatx
.chan
));
282 /* Optionally make use of an RX channel as well */
283 if (plat
->dma_rx_param
) {
284 struct dma_slave_config rx_conf
= {
285 .src_addr
= uap
->port
.mapbase
+ UART01x_DR
,
286 .src_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
,
287 .direction
= DMA_DEV_TO_MEM
,
288 .src_maxburst
= uap
->fifosize
>> 1,
292 chan
= dma_request_channel(mask
, plat
->dma_filter
, plat
->dma_rx_param
);
294 dev_err(uap
->port
.dev
, "no RX DMA channel!\n");
298 dmaengine_slave_config(chan
, &rx_conf
);
299 uap
->dmarx
.chan
= chan
;
301 dev_info(uap
->port
.dev
, "DMA channel RX %s\n",
302 dma_chan_name(uap
->dmarx
.chan
));
308 * Stack up the UARTs and let the above initcall be done at device
309 * initcall time, because the serial driver is called as an arch
310 * initcall, and at this time the DMA subsystem is not yet registered.
311 * At this point the driver will switch over to using DMA where desired.
314 struct list_head node
;
315 struct uart_amba_port
*uap
;
318 static LIST_HEAD(pl011_dma_uarts
);
320 static int __init
pl011_dma_initcall(void)
322 struct list_head
*node
, *tmp
;
324 list_for_each_safe(node
, tmp
, &pl011_dma_uarts
) {
325 struct dma_uap
*dmau
= list_entry(node
, struct dma_uap
, node
);
326 pl011_dma_probe_initcall(dmau
->uap
);
333 device_initcall(pl011_dma_initcall
);
335 static void pl011_dma_probe(struct uart_amba_port
*uap
)
337 struct dma_uap
*dmau
= kzalloc(sizeof(struct dma_uap
), GFP_KERNEL
);
340 list_add_tail(&dmau
->node
, &pl011_dma_uarts
);
344 static void pl011_dma_probe(struct uart_amba_port
*uap
)
346 pl011_dma_probe_initcall(uap
);
350 static void pl011_dma_remove(struct uart_amba_port
*uap
)
352 /* TODO: remove the initcall if it has not yet executed */
354 dma_release_channel(uap
->dmatx
.chan
);
356 dma_release_channel(uap
->dmarx
.chan
);
359 /* Forward declare this for the refill routine */
360 static int pl011_dma_tx_refill(struct uart_amba_port
*uap
);
363 * The current DMA TX buffer has been sent.
364 * Try to queue up another DMA buffer.
366 static void pl011_dma_tx_callback(void *data
)
368 struct uart_amba_port
*uap
= data
;
369 struct pl011_dmatx_data
*dmatx
= &uap
->dmatx
;
373 spin_lock_irqsave(&uap
->port
.lock
, flags
);
374 if (uap
->dmatx
.queued
)
375 dma_unmap_sg(dmatx
->chan
->device
->dev
, &dmatx
->sg
, 1,
379 uap
->dmacr
= dmacr
& ~UART011_TXDMAE
;
380 writew(uap
->dmacr
, uap
->port
.membase
+ UART011_DMACR
);
383 * If TX DMA was disabled, it means that we've stopped the DMA for
384 * some reason (eg, XOFF received, or we want to send an X-char.)
386 * Note: we need to be careful here of a potential race between DMA
387 * and the rest of the driver - if the driver disables TX DMA while
388 * a TX buffer completing, we must update the tx queued status to
389 * get further refills (hence we check dmacr).
391 if (!(dmacr
& UART011_TXDMAE
) || uart_tx_stopped(&uap
->port
) ||
392 uart_circ_empty(&uap
->port
.state
->xmit
)) {
393 uap
->dmatx
.queued
= false;
394 spin_unlock_irqrestore(&uap
->port
.lock
, flags
);
398 if (pl011_dma_tx_refill(uap
) <= 0) {
400 * We didn't queue a DMA buffer for some reason, but we
401 * have data pending to be sent. Re-enable the TX IRQ.
403 uap
->im
|= UART011_TXIM
;
404 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
406 spin_unlock_irqrestore(&uap
->port
.lock
, flags
);
410 * Try to refill the TX DMA buffer.
411 * Locking: called with port lock held and IRQs disabled.
413 * 1 if we queued up a TX DMA buffer.
414 * 0 if we didn't want to handle this by DMA
417 static int pl011_dma_tx_refill(struct uart_amba_port
*uap
)
419 struct pl011_dmatx_data
*dmatx
= &uap
->dmatx
;
420 struct dma_chan
*chan
= dmatx
->chan
;
421 struct dma_device
*dma_dev
= chan
->device
;
422 struct dma_async_tx_descriptor
*desc
;
423 struct circ_buf
*xmit
= &uap
->port
.state
->xmit
;
427 * Try to avoid the overhead involved in using DMA if the
428 * transaction fits in the first half of the FIFO, by using
429 * the standard interrupt handling. This ensures that we
430 * issue a uart_write_wakeup() at the appropriate time.
432 count
= uart_circ_chars_pending(xmit
);
433 if (count
< (uap
->fifosize
>> 1)) {
434 uap
->dmatx
.queued
= false;
439 * Bodge: don't send the last character by DMA, as this
440 * will prevent XON from notifying us to restart DMA.
444 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
445 if (count
> PL011_DMA_BUFFER_SIZE
)
446 count
= PL011_DMA_BUFFER_SIZE
;
448 if (xmit
->tail
< xmit
->head
)
449 memcpy(&dmatx
->buf
[0], &xmit
->buf
[xmit
->tail
], count
);
451 size_t first
= UART_XMIT_SIZE
- xmit
->tail
;
452 size_t second
= xmit
->head
;
454 memcpy(&dmatx
->buf
[0], &xmit
->buf
[xmit
->tail
], first
);
456 memcpy(&dmatx
->buf
[first
], &xmit
->buf
[0], second
);
459 dmatx
->sg
.length
= count
;
461 if (dma_map_sg(dma_dev
->dev
, &dmatx
->sg
, 1, DMA_TO_DEVICE
) != 1) {
462 uap
->dmatx
.queued
= false;
463 dev_dbg(uap
->port
.dev
, "unable to map TX DMA\n");
467 desc
= dmaengine_prep_slave_sg(chan
, &dmatx
->sg
, 1, DMA_MEM_TO_DEV
,
468 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
470 dma_unmap_sg(dma_dev
->dev
, &dmatx
->sg
, 1, DMA_TO_DEVICE
);
471 uap
->dmatx
.queued
= false;
473 * If DMA cannot be used right now, we complete this
474 * transaction via IRQ and let the TTY layer retry.
476 dev_dbg(uap
->port
.dev
, "TX DMA busy\n");
480 /* Some data to go along to the callback */
481 desc
->callback
= pl011_dma_tx_callback
;
482 desc
->callback_param
= uap
;
484 /* All errors should happen at prepare time */
485 dmaengine_submit(desc
);
487 /* Fire the DMA transaction */
488 dma_dev
->device_issue_pending(chan
);
490 uap
->dmacr
|= UART011_TXDMAE
;
491 writew(uap
->dmacr
, uap
->port
.membase
+ UART011_DMACR
);
492 uap
->dmatx
.queued
= true;
495 * Now we know that DMA will fire, so advance the ring buffer
496 * with the stuff we just dispatched.
498 xmit
->tail
= (xmit
->tail
+ count
) & (UART_XMIT_SIZE
- 1);
499 uap
->port
.icount
.tx
+= count
;
501 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
502 uart_write_wakeup(&uap
->port
);
508 * We received a transmit interrupt without a pending X-char but with
509 * pending characters.
510 * Locking: called with port lock held and IRQs disabled.
512 * false if we want to use PIO to transmit
513 * true if we queued a DMA buffer
515 static bool pl011_dma_tx_irq(struct uart_amba_port
*uap
)
517 if (!uap
->using_tx_dma
)
521 * If we already have a TX buffer queued, but received a
522 * TX interrupt, it will be because we've just sent an X-char.
523 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
525 if (uap
->dmatx
.queued
) {
526 uap
->dmacr
|= UART011_TXDMAE
;
527 writew(uap
->dmacr
, uap
->port
.membase
+ UART011_DMACR
);
528 uap
->im
&= ~UART011_TXIM
;
529 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
534 * We don't have a TX buffer queued, so try to queue one.
535 * If we successfully queued a buffer, mask the TX IRQ.
537 if (pl011_dma_tx_refill(uap
) > 0) {
538 uap
->im
&= ~UART011_TXIM
;
539 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
546 * Stop the DMA transmit (eg, due to received XOFF).
547 * Locking: called with port lock held and IRQs disabled.
549 static inline void pl011_dma_tx_stop(struct uart_amba_port
*uap
)
551 if (uap
->dmatx
.queued
) {
552 uap
->dmacr
&= ~UART011_TXDMAE
;
553 writew(uap
->dmacr
, uap
->port
.membase
+ UART011_DMACR
);
558 * Try to start a DMA transmit, or in the case of an XON/OFF
559 * character queued for send, try to get that character out ASAP.
560 * Locking: called with port lock held and IRQs disabled.
562 * false if we want the TX IRQ to be enabled
563 * true if we have a buffer queued
565 static inline bool pl011_dma_tx_start(struct uart_amba_port
*uap
)
569 if (!uap
->using_tx_dma
)
572 if (!uap
->port
.x_char
) {
573 /* no X-char, try to push chars out in DMA mode */
576 if (!uap
->dmatx
.queued
) {
577 if (pl011_dma_tx_refill(uap
) > 0) {
578 uap
->im
&= ~UART011_TXIM
;
581 uap
->im
|= UART011_TXIM
;
584 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
585 } else if (!(uap
->dmacr
& UART011_TXDMAE
)) {
586 uap
->dmacr
|= UART011_TXDMAE
;
588 uap
->port
.membase
+ UART011_DMACR
);
594 * We have an X-char to send. Disable DMA to prevent it loading
595 * the TX fifo, and then see if we can stuff it into the FIFO.
598 uap
->dmacr
&= ~UART011_TXDMAE
;
599 writew(uap
->dmacr
, uap
->port
.membase
+ UART011_DMACR
);
601 if (readw(uap
->port
.membase
+ UART01x_FR
) & UART01x_FR_TXFF
) {
603 * No space in the FIFO, so enable the transmit interrupt
604 * so we know when there is space. Note that once we've
605 * loaded the character, we should just re-enable DMA.
610 writew(uap
->port
.x_char
, uap
->port
.membase
+ UART01x_DR
);
611 uap
->port
.icount
.tx
++;
612 uap
->port
.x_char
= 0;
614 /* Success - restore the DMA state */
616 writew(dmacr
, uap
->port
.membase
+ UART011_DMACR
);
622 * Flush the transmit buffer.
623 * Locking: called with port lock held and IRQs disabled.
625 static void pl011_dma_flush_buffer(struct uart_port
*port
)
627 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
629 if (!uap
->using_tx_dma
)
632 /* Avoid deadlock with the DMA engine callback */
633 spin_unlock(&uap
->port
.lock
);
634 dmaengine_terminate_all(uap
->dmatx
.chan
);
635 spin_lock(&uap
->port
.lock
);
636 if (uap
->dmatx
.queued
) {
637 dma_unmap_sg(uap
->dmatx
.chan
->device
->dev
, &uap
->dmatx
.sg
, 1,
639 uap
->dmatx
.queued
= false;
640 uap
->dmacr
&= ~UART011_TXDMAE
;
641 writew(uap
->dmacr
, uap
->port
.membase
+ UART011_DMACR
);
645 static void pl011_dma_rx_callback(void *data
);
647 static int pl011_dma_rx_trigger_dma(struct uart_amba_port
*uap
)
649 struct dma_chan
*rxchan
= uap
->dmarx
.chan
;
650 struct pl011_dmarx_data
*dmarx
= &uap
->dmarx
;
651 struct dma_async_tx_descriptor
*desc
;
652 struct pl011_sgbuf
*sgbuf
;
657 /* Start the RX DMA job */
658 sgbuf
= uap
->dmarx
.use_buf_b
?
659 &uap
->dmarx
.sgbuf_b
: &uap
->dmarx
.sgbuf_a
;
660 desc
= dmaengine_prep_slave_sg(rxchan
, &sgbuf
->sg
, 1,
662 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
664 * If the DMA engine is busy and cannot prepare a
665 * channel, no big deal, the driver will fall back
666 * to interrupt mode as a result of this error code.
669 uap
->dmarx
.running
= false;
670 dmaengine_terminate_all(rxchan
);
674 /* Some data to go along to the callback */
675 desc
->callback
= pl011_dma_rx_callback
;
676 desc
->callback_param
= uap
;
677 dmarx
->cookie
= dmaengine_submit(desc
);
678 dma_async_issue_pending(rxchan
);
680 uap
->dmacr
|= UART011_RXDMAE
;
681 writew(uap
->dmacr
, uap
->port
.membase
+ UART011_DMACR
);
682 uap
->dmarx
.running
= true;
684 uap
->im
&= ~UART011_RXIM
;
685 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
691 * This is called when either the DMA job is complete, or
692 * the FIFO timeout interrupt occurred. This must be called
693 * with the port spinlock uap->port.lock held.
695 static void pl011_dma_rx_chars(struct uart_amba_port
*uap
,
696 u32 pending
, bool use_buf_b
,
699 struct tty_struct
*tty
= uap
->port
.state
->port
.tty
;
700 struct pl011_sgbuf
*sgbuf
= use_buf_b
?
701 &uap
->dmarx
.sgbuf_b
: &uap
->dmarx
.sgbuf_a
;
702 struct device
*dev
= uap
->dmarx
.chan
->device
->dev
;
704 u32 fifotaken
= 0; /* only used for vdbg() */
706 /* Pick everything from the DMA first */
709 dma_sync_sg_for_cpu(dev
, &sgbuf
->sg
, 1, DMA_FROM_DEVICE
);
712 * First take all chars in the DMA pipe, then look in the FIFO.
713 * Note that tty_insert_flip_buf() tries to take as many chars
716 dma_count
= tty_insert_flip_string(uap
->port
.state
->port
.tty
,
717 sgbuf
->buf
, pending
);
719 /* Return buffer to device */
720 dma_sync_sg_for_device(dev
, &sgbuf
->sg
, 1, DMA_FROM_DEVICE
);
722 uap
->port
.icount
.rx
+= dma_count
;
723 if (dma_count
< pending
)
724 dev_warn(uap
->port
.dev
,
725 "couldn't insert all characters (TTY is full?)\n");
729 * Only continue with trying to read the FIFO if all DMA chars have
732 if (dma_count
== pending
&& readfifo
) {
733 /* Clear any error flags */
734 writew(UART011_OEIS
| UART011_BEIS
| UART011_PEIS
| UART011_FEIS
,
735 uap
->port
.membase
+ UART011_ICR
);
738 * If we read all the DMA'd characters, and we had an
739 * incomplete buffer, that could be due to an rx error, or
740 * maybe we just timed out. Read any pending chars and check
743 * Error conditions will only occur in the FIFO, these will
744 * trigger an immediate interrupt and stop the DMA job, so we
745 * will always find the error in the FIFO, never in the DMA
748 fifotaken
= pl011_fifo_to_tty(uap
);
751 spin_unlock(&uap
->port
.lock
);
752 dev_vdbg(uap
->port
.dev
,
753 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
754 dma_count
, fifotaken
);
755 tty_flip_buffer_push(tty
);
756 spin_lock(&uap
->port
.lock
);
759 static void pl011_dma_rx_irq(struct uart_amba_port
*uap
)
761 struct pl011_dmarx_data
*dmarx
= &uap
->dmarx
;
762 struct dma_chan
*rxchan
= dmarx
->chan
;
763 struct pl011_sgbuf
*sgbuf
= dmarx
->use_buf_b
?
764 &dmarx
->sgbuf_b
: &dmarx
->sgbuf_a
;
766 struct dma_tx_state state
;
767 enum dma_status dmastat
;
770 * Pause the transfer so we can trust the current counter,
771 * do this before we pause the PL011 block, else we may
774 if (dmaengine_pause(rxchan
))
775 dev_err(uap
->port
.dev
, "unable to pause DMA transfer\n");
776 dmastat
= rxchan
->device
->device_tx_status(rxchan
,
777 dmarx
->cookie
, &state
);
778 if (dmastat
!= DMA_PAUSED
)
779 dev_err(uap
->port
.dev
, "unable to pause DMA transfer\n");
781 /* Disable RX DMA - incoming data will wait in the FIFO */
782 uap
->dmacr
&= ~UART011_RXDMAE
;
783 writew(uap
->dmacr
, uap
->port
.membase
+ UART011_DMACR
);
784 uap
->dmarx
.running
= false;
786 pending
= sgbuf
->sg
.length
- state
.residue
;
787 BUG_ON(pending
> PL011_DMA_BUFFER_SIZE
);
788 /* Then we terminate the transfer - we now know our residue */
789 dmaengine_terminate_all(rxchan
);
792 * This will take the chars we have so far and insert
793 * into the framework.
795 pl011_dma_rx_chars(uap
, pending
, dmarx
->use_buf_b
, true);
797 /* Switch buffer & re-trigger DMA job */
798 dmarx
->use_buf_b
= !dmarx
->use_buf_b
;
799 if (pl011_dma_rx_trigger_dma(uap
)) {
800 dev_dbg(uap
->port
.dev
, "could not retrigger RX DMA job "
801 "fall back to interrupt mode\n");
802 uap
->im
|= UART011_RXIM
;
803 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
807 static void pl011_dma_rx_callback(void *data
)
809 struct uart_amba_port
*uap
= data
;
810 struct pl011_dmarx_data
*dmarx
= &uap
->dmarx
;
811 struct dma_chan
*rxchan
= dmarx
->chan
;
812 bool lastbuf
= dmarx
->use_buf_b
;
813 struct pl011_sgbuf
*sgbuf
= dmarx
->use_buf_b
?
814 &dmarx
->sgbuf_b
: &dmarx
->sgbuf_a
;
816 struct dma_tx_state state
;
820 * This completion interrupt occurs typically when the
821 * RX buffer is totally stuffed but no timeout has yet
822 * occurred. When that happens, we just want the RX
823 * routine to flush out the secondary DMA buffer while
824 * we immediately trigger the next DMA job.
826 spin_lock_irq(&uap
->port
.lock
);
828 * Rx data can be taken by the UART interrupts during
829 * the DMA irq handler. So we check the residue here.
831 rxchan
->device
->device_tx_status(rxchan
, dmarx
->cookie
, &state
);
832 pending
= sgbuf
->sg
.length
- state
.residue
;
833 BUG_ON(pending
> PL011_DMA_BUFFER_SIZE
);
834 /* Then we terminate the transfer - we now know our residue */
835 dmaengine_terminate_all(rxchan
);
837 uap
->dmarx
.running
= false;
838 dmarx
->use_buf_b
= !lastbuf
;
839 ret
= pl011_dma_rx_trigger_dma(uap
);
841 pl011_dma_rx_chars(uap
, pending
, lastbuf
, false);
842 spin_unlock_irq(&uap
->port
.lock
);
844 * Do this check after we picked the DMA chars so we don't
845 * get some IRQ immediately from RX.
848 dev_dbg(uap
->port
.dev
, "could not retrigger RX DMA job "
849 "fall back to interrupt mode\n");
850 uap
->im
|= UART011_RXIM
;
851 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
856 * Stop accepting received characters, when we're shutting down or
857 * suspending this port.
858 * Locking: called with port lock held and IRQs disabled.
860 static inline void pl011_dma_rx_stop(struct uart_amba_port
*uap
)
862 /* FIXME. Just disable the DMA enable */
863 uap
->dmacr
&= ~UART011_RXDMAE
;
864 writew(uap
->dmacr
, uap
->port
.membase
+ UART011_DMACR
);
867 static void pl011_dma_startup(struct uart_amba_port
*uap
)
871 if (!uap
->dmatx
.chan
)
874 uap
->dmatx
.buf
= kmalloc(PL011_DMA_BUFFER_SIZE
, GFP_KERNEL
);
875 if (!uap
->dmatx
.buf
) {
876 dev_err(uap
->port
.dev
, "no memory for DMA TX buffer\n");
877 uap
->port
.fifosize
= uap
->fifosize
;
881 sg_init_one(&uap
->dmatx
.sg
, uap
->dmatx
.buf
, PL011_DMA_BUFFER_SIZE
);
883 /* The DMA buffer is now the FIFO the TTY subsystem can use */
884 uap
->port
.fifosize
= PL011_DMA_BUFFER_SIZE
;
885 uap
->using_tx_dma
= true;
887 if (!uap
->dmarx
.chan
)
890 /* Allocate and map DMA RX buffers */
891 ret
= pl011_sgbuf_init(uap
->dmarx
.chan
, &uap
->dmarx
.sgbuf_a
,
894 dev_err(uap
->port
.dev
, "failed to init DMA %s: %d\n",
899 ret
= pl011_sgbuf_init(uap
->dmarx
.chan
, &uap
->dmarx
.sgbuf_b
,
902 dev_err(uap
->port
.dev
, "failed to init DMA %s: %d\n",
904 pl011_sgbuf_free(uap
->dmarx
.chan
, &uap
->dmarx
.sgbuf_a
,
909 uap
->using_rx_dma
= true;
912 /* Turn on DMA error (RX/TX will be enabled on demand) */
913 uap
->dmacr
|= UART011_DMAONERR
;
914 writew(uap
->dmacr
, uap
->port
.membase
+ UART011_DMACR
);
917 * ST Micro variants has some specific dma burst threshold
918 * compensation. Set this to 16 bytes, so burst will only
919 * be issued above/below 16 bytes.
921 if (uap
->vendor
->dma_threshold
)
922 writew(ST_UART011_DMAWM_RX_16
| ST_UART011_DMAWM_TX_16
,
923 uap
->port
.membase
+ ST_UART011_DMAWM
);
925 if (uap
->using_rx_dma
) {
926 if (pl011_dma_rx_trigger_dma(uap
))
927 dev_dbg(uap
->port
.dev
, "could not trigger initial "
928 "RX DMA job, fall back to interrupt mode\n");
932 static void pl011_dma_shutdown(struct uart_amba_port
*uap
)
934 if (!(uap
->using_tx_dma
|| uap
->using_rx_dma
))
937 /* Disable RX and TX DMA */
938 while (readw(uap
->port
.membase
+ UART01x_FR
) & UART01x_FR_BUSY
)
941 spin_lock_irq(&uap
->port
.lock
);
942 uap
->dmacr
&= ~(UART011_DMAONERR
| UART011_RXDMAE
| UART011_TXDMAE
);
943 writew(uap
->dmacr
, uap
->port
.membase
+ UART011_DMACR
);
944 spin_unlock_irq(&uap
->port
.lock
);
946 if (uap
->using_tx_dma
) {
947 /* In theory, this should already be done by pl011_dma_flush_buffer */
948 dmaengine_terminate_all(uap
->dmatx
.chan
);
949 if (uap
->dmatx
.queued
) {
950 dma_unmap_sg(uap
->dmatx
.chan
->device
->dev
, &uap
->dmatx
.sg
, 1,
952 uap
->dmatx
.queued
= false;
955 kfree(uap
->dmatx
.buf
);
956 uap
->using_tx_dma
= false;
959 if (uap
->using_rx_dma
) {
960 dmaengine_terminate_all(uap
->dmarx
.chan
);
961 /* Clean up the RX DMA */
962 pl011_sgbuf_free(uap
->dmarx
.chan
, &uap
->dmarx
.sgbuf_a
, DMA_FROM_DEVICE
);
963 pl011_sgbuf_free(uap
->dmarx
.chan
, &uap
->dmarx
.sgbuf_b
, DMA_FROM_DEVICE
);
964 uap
->using_rx_dma
= false;
968 static inline bool pl011_dma_rx_available(struct uart_amba_port
*uap
)
970 return uap
->using_rx_dma
;
973 static inline bool pl011_dma_rx_running(struct uart_amba_port
*uap
)
975 return uap
->using_rx_dma
&& uap
->dmarx
.running
;
980 /* Blank functions if the DMA engine is not available */
981 static inline void pl011_dma_probe(struct uart_amba_port
*uap
)
985 static inline void pl011_dma_remove(struct uart_amba_port
*uap
)
989 static inline void pl011_dma_startup(struct uart_amba_port
*uap
)
993 static inline void pl011_dma_shutdown(struct uart_amba_port
*uap
)
997 static inline bool pl011_dma_tx_irq(struct uart_amba_port
*uap
)
1002 static inline void pl011_dma_tx_stop(struct uart_amba_port
*uap
)
1006 static inline bool pl011_dma_tx_start(struct uart_amba_port
*uap
)
1011 static inline void pl011_dma_rx_irq(struct uart_amba_port
*uap
)
1015 static inline void pl011_dma_rx_stop(struct uart_amba_port
*uap
)
1019 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port
*uap
)
1024 static inline bool pl011_dma_rx_available(struct uart_amba_port
*uap
)
1029 static inline bool pl011_dma_rx_running(struct uart_amba_port
*uap
)
1034 #define pl011_dma_flush_buffer NULL
1037 static void pl011_stop_tx(struct uart_port
*port
)
1039 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
1041 uap
->im
&= ~UART011_TXIM
;
1042 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
1043 pl011_dma_tx_stop(uap
);
1046 static void pl011_start_tx(struct uart_port
*port
)
1048 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
1050 if (!pl011_dma_tx_start(uap
)) {
1051 uap
->im
|= UART011_TXIM
;
1052 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
1056 static void pl011_stop_rx(struct uart_port
*port
)
1058 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
1060 uap
->im
&= ~(UART011_RXIM
|UART011_RTIM
|UART011_FEIM
|
1061 UART011_PEIM
|UART011_BEIM
|UART011_OEIM
);
1062 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
1064 pl011_dma_rx_stop(uap
);
1067 static void pl011_enable_ms(struct uart_port
*port
)
1069 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
1071 uap
->im
|= UART011_RIMIM
|UART011_CTSMIM
|UART011_DCDMIM
|UART011_DSRMIM
;
1072 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
1075 static void pl011_rx_chars(struct uart_amba_port
*uap
)
1077 struct tty_struct
*tty
= uap
->port
.state
->port
.tty
;
1079 pl011_fifo_to_tty(uap
);
1081 spin_unlock(&uap
->port
.lock
);
1082 tty_flip_buffer_push(tty
);
1084 * If we were temporarily out of DMA mode for a while,
1085 * attempt to switch back to DMA mode again.
1087 if (pl011_dma_rx_available(uap
)) {
1088 if (pl011_dma_rx_trigger_dma(uap
)) {
1089 dev_dbg(uap
->port
.dev
, "could not trigger RX DMA job "
1090 "fall back to interrupt mode again\n");
1091 uap
->im
|= UART011_RXIM
;
1093 uap
->im
&= ~UART011_RXIM
;
1094 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
1096 spin_lock(&uap
->port
.lock
);
1099 static void pl011_tx_chars(struct uart_amba_port
*uap
)
1101 struct circ_buf
*xmit
= &uap
->port
.state
->xmit
;
1104 if (uap
->port
.x_char
) {
1105 writew(uap
->port
.x_char
, uap
->port
.membase
+ UART01x_DR
);
1106 uap
->port
.icount
.tx
++;
1107 uap
->port
.x_char
= 0;
1110 if (uart_circ_empty(xmit
) || uart_tx_stopped(&uap
->port
)) {
1111 pl011_stop_tx(&uap
->port
);
1115 /* If we are using DMA mode, try to send some characters. */
1116 if (pl011_dma_tx_irq(uap
))
1119 count
= uap
->fifosize
>> 1;
1121 writew(xmit
->buf
[xmit
->tail
], uap
->port
.membase
+ UART01x_DR
);
1122 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
1123 uap
->port
.icount
.tx
++;
1124 if (uart_circ_empty(xmit
))
1126 } while (--count
> 0);
1128 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
1129 uart_write_wakeup(&uap
->port
);
1131 if (uart_circ_empty(xmit
))
1132 pl011_stop_tx(&uap
->port
);
1135 static void pl011_modem_status(struct uart_amba_port
*uap
)
1137 unsigned int status
, delta
;
1139 status
= readw(uap
->port
.membase
+ UART01x_FR
) & UART01x_FR_MODEM_ANY
;
1141 delta
= status
^ uap
->old_status
;
1142 uap
->old_status
= status
;
1147 if (delta
& UART01x_FR_DCD
)
1148 uart_handle_dcd_change(&uap
->port
, status
& UART01x_FR_DCD
);
1150 if (delta
& UART01x_FR_DSR
)
1151 uap
->port
.icount
.dsr
++;
1153 if (delta
& UART01x_FR_CTS
)
1154 uart_handle_cts_change(&uap
->port
, status
& UART01x_FR_CTS
);
1156 wake_up_interruptible(&uap
->port
.state
->port
.delta_msr_wait
);
1159 static irqreturn_t
pl011_int(int irq
, void *dev_id
)
1161 struct uart_amba_port
*uap
= dev_id
;
1162 unsigned long flags
;
1163 unsigned int status
, pass_counter
= AMBA_ISR_PASS_LIMIT
;
1165 unsigned int dummy_read
;
1167 spin_lock_irqsave(&uap
->port
.lock
, flags
);
1169 status
= readw(uap
->port
.membase
+ UART011_MIS
);
1172 if (uap
->vendor
->cts_event_workaround
) {
1173 /* workaround to make sure that all bits are unlocked.. */
1174 writew(0x00, uap
->port
.membase
+ UART011_ICR
);
1177 * WA: introduce 26ns(1 uart clk) delay before W1C;
1178 * single apb access will incur 2 pclk(133.12Mhz) delay,
1179 * so add 2 dummy reads
1181 dummy_read
= readw(uap
->port
.membase
+ UART011_ICR
);
1182 dummy_read
= readw(uap
->port
.membase
+ UART011_ICR
);
1185 writew(status
& ~(UART011_TXIS
|UART011_RTIS
|
1187 uap
->port
.membase
+ UART011_ICR
);
1189 if (status
& (UART011_RTIS
|UART011_RXIS
)) {
1190 if (pl011_dma_rx_running(uap
))
1191 pl011_dma_rx_irq(uap
);
1193 pl011_rx_chars(uap
);
1195 if (status
& (UART011_DSRMIS
|UART011_DCDMIS
|
1196 UART011_CTSMIS
|UART011_RIMIS
))
1197 pl011_modem_status(uap
);
1198 if (status
& UART011_TXIS
)
1199 pl011_tx_chars(uap
);
1201 if (pass_counter
-- == 0)
1204 status
= readw(uap
->port
.membase
+ UART011_MIS
);
1205 } while (status
!= 0);
1209 spin_unlock_irqrestore(&uap
->port
.lock
, flags
);
1211 return IRQ_RETVAL(handled
);
1214 static unsigned int pl01x_tx_empty(struct uart_port
*port
)
1216 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
1217 unsigned int status
= readw(uap
->port
.membase
+ UART01x_FR
);
1218 return status
& (UART01x_FR_BUSY
|UART01x_FR_TXFF
) ? 0 : TIOCSER_TEMT
;
1221 static unsigned int pl01x_get_mctrl(struct uart_port
*port
)
1223 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
1224 unsigned int result
= 0;
1225 unsigned int status
= readw(uap
->port
.membase
+ UART01x_FR
);
1227 #define TIOCMBIT(uartbit, tiocmbit) \
1228 if (status & uartbit) \
1231 TIOCMBIT(UART01x_FR_DCD
, TIOCM_CAR
);
1232 TIOCMBIT(UART01x_FR_DSR
, TIOCM_DSR
);
1233 TIOCMBIT(UART01x_FR_CTS
, TIOCM_CTS
);
1234 TIOCMBIT(UART011_FR_RI
, TIOCM_RNG
);
1239 static void pl011_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
1241 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
1244 cr
= readw(uap
->port
.membase
+ UART011_CR
);
1246 #define TIOCMBIT(tiocmbit, uartbit) \
1247 if (mctrl & tiocmbit) \
1252 TIOCMBIT(TIOCM_RTS
, UART011_CR_RTS
);
1253 TIOCMBIT(TIOCM_DTR
, UART011_CR_DTR
);
1254 TIOCMBIT(TIOCM_OUT1
, UART011_CR_OUT1
);
1255 TIOCMBIT(TIOCM_OUT2
, UART011_CR_OUT2
);
1256 TIOCMBIT(TIOCM_LOOP
, UART011_CR_LBE
);
1259 /* We need to disable auto-RTS if we want to turn RTS off */
1260 TIOCMBIT(TIOCM_RTS
, UART011_CR_RTSEN
);
1264 writew(cr
, uap
->port
.membase
+ UART011_CR
);
1267 static void pl011_break_ctl(struct uart_port
*port
, int break_state
)
1269 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
1270 unsigned long flags
;
1273 spin_lock_irqsave(&uap
->port
.lock
, flags
);
1274 lcr_h
= readw(uap
->port
.membase
+ uap
->lcrh_tx
);
1275 if (break_state
== -1)
1276 lcr_h
|= UART01x_LCRH_BRK
;
1278 lcr_h
&= ~UART01x_LCRH_BRK
;
1279 writew(lcr_h
, uap
->port
.membase
+ uap
->lcrh_tx
);
1280 spin_unlock_irqrestore(&uap
->port
.lock
, flags
);
1283 #ifdef CONFIG_CONSOLE_POLL
1284 static int pl010_get_poll_char(struct uart_port
*port
)
1286 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
1287 unsigned int status
;
1289 status
= readw(uap
->port
.membase
+ UART01x_FR
);
1290 if (status
& UART01x_FR_RXFE
)
1291 return NO_POLL_CHAR
;
1293 return readw(uap
->port
.membase
+ UART01x_DR
);
1296 static void pl010_put_poll_char(struct uart_port
*port
,
1299 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
1301 while (readw(uap
->port
.membase
+ UART01x_FR
) & UART01x_FR_TXFF
)
1304 writew(ch
, uap
->port
.membase
+ UART01x_DR
);
1307 #endif /* CONFIG_CONSOLE_POLL */
1309 static int pl011_startup(struct uart_port
*port
)
1311 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
1315 retval
= clk_prepare(uap
->clk
);
1320 * Try to enable the clock producer.
1322 retval
= clk_enable(uap
->clk
);
1326 uap
->port
.uartclk
= clk_get_rate(uap
->clk
);
1328 /* Clear pending error and receive interrupts */
1329 writew(UART011_OEIS
| UART011_BEIS
| UART011_PEIS
| UART011_FEIS
|
1330 UART011_RTIS
| UART011_RXIS
, uap
->port
.membase
+ UART011_ICR
);
1335 retval
= request_irq(uap
->port
.irq
, pl011_int
, 0, "uart-pl011", uap
);
1339 writew(uap
->vendor
->ifls
, uap
->port
.membase
+ UART011_IFLS
);
1342 * Provoke TX FIFO interrupt into asserting.
1344 cr
= UART01x_CR_UARTEN
| UART011_CR_TXE
| UART011_CR_LBE
;
1345 writew(cr
, uap
->port
.membase
+ UART011_CR
);
1346 writew(0, uap
->port
.membase
+ UART011_FBRD
);
1347 writew(1, uap
->port
.membase
+ UART011_IBRD
);
1348 writew(0, uap
->port
.membase
+ uap
->lcrh_rx
);
1349 if (uap
->lcrh_tx
!= uap
->lcrh_rx
) {
1352 * Wait 10 PCLKs before writing LCRH_TX register,
1353 * to get this delay write read only register 10 times
1355 for (i
= 0; i
< 10; ++i
)
1356 writew(0xff, uap
->port
.membase
+ UART011_MIS
);
1357 writew(0, uap
->port
.membase
+ uap
->lcrh_tx
);
1359 writew(0, uap
->port
.membase
+ UART01x_DR
);
1360 while (readw(uap
->port
.membase
+ UART01x_FR
) & UART01x_FR_BUSY
)
1363 /* restore RTS and DTR */
1364 cr
= uap
->old_cr
& (UART011_CR_RTS
| UART011_CR_DTR
);
1365 cr
|= UART01x_CR_UARTEN
| UART011_CR_RXE
| UART011_CR_TXE
;
1366 writew(cr
, uap
->port
.membase
+ UART011_CR
);
1369 * initialise the old status of the modem signals
1371 uap
->old_status
= readw(uap
->port
.membase
+ UART01x_FR
) & UART01x_FR_MODEM_ANY
;
1374 pl011_dma_startup(uap
);
1377 * Finally, enable interrupts, only timeouts when using DMA
1378 * if initial RX DMA job failed, start in interrupt mode
1381 spin_lock_irq(&uap
->port
.lock
);
1382 /* Clear out any spuriously appearing RX interrupts */
1383 writew(UART011_RTIS
| UART011_RXIS
,
1384 uap
->port
.membase
+ UART011_ICR
);
1385 uap
->im
= UART011_RTIM
;
1386 if (!pl011_dma_rx_running(uap
))
1387 uap
->im
|= UART011_RXIM
;
1388 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
1389 spin_unlock_irq(&uap
->port
.lock
);
1391 if (uap
->port
.dev
->platform_data
) {
1392 struct amba_pl011_data
*plat
;
1394 plat
= uap
->port
.dev
->platform_data
;
1402 clk_disable(uap
->clk
);
1404 clk_unprepare(uap
->clk
);
1409 static void pl011_shutdown_channel(struct uart_amba_port
*uap
,
1414 val
= readw(uap
->port
.membase
+ lcrh
);
1415 val
&= ~(UART01x_LCRH_BRK
| UART01x_LCRH_FEN
);
1416 writew(val
, uap
->port
.membase
+ lcrh
);
1419 static void pl011_shutdown(struct uart_port
*port
)
1421 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
1425 * disable all interrupts
1427 spin_lock_irq(&uap
->port
.lock
);
1429 writew(uap
->im
, uap
->port
.membase
+ UART011_IMSC
);
1430 writew(0xffff, uap
->port
.membase
+ UART011_ICR
);
1431 spin_unlock_irq(&uap
->port
.lock
);
1433 pl011_dma_shutdown(uap
);
1436 * Free the interrupt
1438 free_irq(uap
->port
.irq
, uap
);
1442 * disable the port. It should not disable RTS and DTR.
1443 * Also RTS and DTR state should be preserved to restore
1444 * it during startup().
1446 uap
->autorts
= false;
1447 cr
= readw(uap
->port
.membase
+ UART011_CR
);
1449 cr
&= UART011_CR_RTS
| UART011_CR_DTR
;
1450 cr
|= UART01x_CR_UARTEN
| UART011_CR_TXE
;
1451 writew(cr
, uap
->port
.membase
+ UART011_CR
);
1454 * disable break condition and fifos
1456 pl011_shutdown_channel(uap
, uap
->lcrh_rx
);
1457 if (uap
->lcrh_rx
!= uap
->lcrh_tx
)
1458 pl011_shutdown_channel(uap
, uap
->lcrh_tx
);
1461 * Shut down the clock producer
1463 clk_disable(uap
->clk
);
1464 clk_unprepare(uap
->clk
);
1466 if (uap
->port
.dev
->platform_data
) {
1467 struct amba_pl011_data
*plat
;
1469 plat
= uap
->port
.dev
->platform_data
;
1477 pl011_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
1478 struct ktermios
*old
)
1480 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
1481 unsigned int lcr_h
, old_cr
;
1482 unsigned long flags
;
1483 unsigned int baud
, quot
, clkdiv
;
1485 if (uap
->vendor
->oversampling
)
1491 * Ask the core to calculate the divisor for us.
1493 baud
= uart_get_baud_rate(port
, termios
, old
, 0,
1494 port
->uartclk
/ clkdiv
);
1496 if (baud
> port
->uartclk
/16)
1497 quot
= DIV_ROUND_CLOSEST(port
->uartclk
* 8, baud
);
1499 quot
= DIV_ROUND_CLOSEST(port
->uartclk
* 4, baud
);
1501 switch (termios
->c_cflag
& CSIZE
) {
1503 lcr_h
= UART01x_LCRH_WLEN_5
;
1506 lcr_h
= UART01x_LCRH_WLEN_6
;
1509 lcr_h
= UART01x_LCRH_WLEN_7
;
1512 lcr_h
= UART01x_LCRH_WLEN_8
;
1515 if (termios
->c_cflag
& CSTOPB
)
1516 lcr_h
|= UART01x_LCRH_STP2
;
1517 if (termios
->c_cflag
& PARENB
) {
1518 lcr_h
|= UART01x_LCRH_PEN
;
1519 if (!(termios
->c_cflag
& PARODD
))
1520 lcr_h
|= UART01x_LCRH_EPS
;
1522 if (uap
->fifosize
> 1)
1523 lcr_h
|= UART01x_LCRH_FEN
;
1525 spin_lock_irqsave(&port
->lock
, flags
);
1528 * Update the per-port timeout.
1530 uart_update_timeout(port
, termios
->c_cflag
, baud
);
1532 port
->read_status_mask
= UART011_DR_OE
| 255;
1533 if (termios
->c_iflag
& INPCK
)
1534 port
->read_status_mask
|= UART011_DR_FE
| UART011_DR_PE
;
1535 if (termios
->c_iflag
& (BRKINT
| PARMRK
))
1536 port
->read_status_mask
|= UART011_DR_BE
;
1539 * Characters to ignore
1541 port
->ignore_status_mask
= 0;
1542 if (termios
->c_iflag
& IGNPAR
)
1543 port
->ignore_status_mask
|= UART011_DR_FE
| UART011_DR_PE
;
1544 if (termios
->c_iflag
& IGNBRK
) {
1545 port
->ignore_status_mask
|= UART011_DR_BE
;
1547 * If we're ignoring parity and break indicators,
1548 * ignore overruns too (for real raw support).
1550 if (termios
->c_iflag
& IGNPAR
)
1551 port
->ignore_status_mask
|= UART011_DR_OE
;
1555 * Ignore all characters if CREAD is not set.
1557 if ((termios
->c_cflag
& CREAD
) == 0)
1558 port
->ignore_status_mask
|= UART_DUMMY_DR_RX
;
1560 if (UART_ENABLE_MS(port
, termios
->c_cflag
))
1561 pl011_enable_ms(port
);
1563 /* first, disable everything */
1564 old_cr
= readw(port
->membase
+ UART011_CR
);
1565 writew(0, port
->membase
+ UART011_CR
);
1567 if (termios
->c_cflag
& CRTSCTS
) {
1568 if (old_cr
& UART011_CR_RTS
)
1569 old_cr
|= UART011_CR_RTSEN
;
1571 old_cr
|= UART011_CR_CTSEN
;
1572 uap
->autorts
= true;
1574 old_cr
&= ~(UART011_CR_CTSEN
| UART011_CR_RTSEN
);
1575 uap
->autorts
= false;
1578 if (uap
->vendor
->oversampling
) {
1579 if (baud
> port
->uartclk
/ 16)
1580 old_cr
|= ST_UART011_CR_OVSFACT
;
1582 old_cr
&= ~ST_UART011_CR_OVSFACT
;
1586 writew(quot
& 0x3f, port
->membase
+ UART011_FBRD
);
1587 writew(quot
>> 6, port
->membase
+ UART011_IBRD
);
1590 * ----------v----------v----------v----------v-----
1591 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
1592 * ----------^----------^----------^----------^-----
1594 writew(lcr_h
, port
->membase
+ uap
->lcrh_rx
);
1595 if (uap
->lcrh_rx
!= uap
->lcrh_tx
) {
1598 * Wait 10 PCLKs before writing LCRH_TX register,
1599 * to get this delay write read only register 10 times
1601 for (i
= 0; i
< 10; ++i
)
1602 writew(0xff, uap
->port
.membase
+ UART011_MIS
);
1603 writew(lcr_h
, port
->membase
+ uap
->lcrh_tx
);
1605 writew(old_cr
, port
->membase
+ UART011_CR
);
1607 spin_unlock_irqrestore(&port
->lock
, flags
);
1610 static const char *pl011_type(struct uart_port
*port
)
1612 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
1613 return uap
->port
.type
== PORT_AMBA
? uap
->type
: NULL
;
1617 * Release the memory region(s) being used by 'port'
1619 static void pl010_release_port(struct uart_port
*port
)
1621 release_mem_region(port
->mapbase
, SZ_4K
);
1625 * Request the memory region(s) being used by 'port'
1627 static int pl010_request_port(struct uart_port
*port
)
1629 return request_mem_region(port
->mapbase
, SZ_4K
, "uart-pl011")
1630 != NULL
? 0 : -EBUSY
;
1634 * Configure/autoconfigure the port.
1636 static void pl010_config_port(struct uart_port
*port
, int flags
)
1638 if (flags
& UART_CONFIG_TYPE
) {
1639 port
->type
= PORT_AMBA
;
1640 pl010_request_port(port
);
1645 * verify the new serial_struct (for TIOCSSERIAL).
1647 static int pl010_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
1650 if (ser
->type
!= PORT_UNKNOWN
&& ser
->type
!= PORT_AMBA
)
1652 if (ser
->irq
< 0 || ser
->irq
>= nr_irqs
)
1654 if (ser
->baud_base
< 9600)
1659 static struct uart_ops amba_pl011_pops
= {
1660 .tx_empty
= pl01x_tx_empty
,
1661 .set_mctrl
= pl011_set_mctrl
,
1662 .get_mctrl
= pl01x_get_mctrl
,
1663 .stop_tx
= pl011_stop_tx
,
1664 .start_tx
= pl011_start_tx
,
1665 .stop_rx
= pl011_stop_rx
,
1666 .enable_ms
= pl011_enable_ms
,
1667 .break_ctl
= pl011_break_ctl
,
1668 .startup
= pl011_startup
,
1669 .shutdown
= pl011_shutdown
,
1670 .flush_buffer
= pl011_dma_flush_buffer
,
1671 .set_termios
= pl011_set_termios
,
1673 .release_port
= pl010_release_port
,
1674 .request_port
= pl010_request_port
,
1675 .config_port
= pl010_config_port
,
1676 .verify_port
= pl010_verify_port
,
1677 #ifdef CONFIG_CONSOLE_POLL
1678 .poll_get_char
= pl010_get_poll_char
,
1679 .poll_put_char
= pl010_put_poll_char
,
1683 static struct uart_amba_port
*amba_ports
[UART_NR
];
1685 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
1687 static void pl011_console_putchar(struct uart_port
*port
, int ch
)
1689 struct uart_amba_port
*uap
= (struct uart_amba_port
*)port
;
1691 while (readw(uap
->port
.membase
+ UART01x_FR
) & UART01x_FR_TXFF
)
1693 writew(ch
, uap
->port
.membase
+ UART01x_DR
);
1697 pl011_console_write(struct console
*co
, const char *s
, unsigned int count
)
1699 struct uart_amba_port
*uap
= amba_ports
[co
->index
];
1700 unsigned int status
, old_cr
, new_cr
;
1701 unsigned long flags
;
1704 clk_enable(uap
->clk
);
1706 local_irq_save(flags
);
1707 if (uap
->port
.sysrq
)
1709 else if (oops_in_progress
)
1710 locked
= spin_trylock(&uap
->port
.lock
);
1712 spin_lock(&uap
->port
.lock
);
1715 * First save the CR then disable the interrupts
1717 old_cr
= readw(uap
->port
.membase
+ UART011_CR
);
1718 new_cr
= old_cr
& ~UART011_CR_CTSEN
;
1719 new_cr
|= UART01x_CR_UARTEN
| UART011_CR_TXE
;
1720 writew(new_cr
, uap
->port
.membase
+ UART011_CR
);
1722 uart_console_write(&uap
->port
, s
, count
, pl011_console_putchar
);
1725 * Finally, wait for transmitter to become empty
1726 * and restore the TCR
1729 status
= readw(uap
->port
.membase
+ UART01x_FR
);
1730 } while (status
& UART01x_FR_BUSY
);
1731 writew(old_cr
, uap
->port
.membase
+ UART011_CR
);
1734 spin_unlock(&uap
->port
.lock
);
1735 local_irq_restore(flags
);
1737 clk_disable(uap
->clk
);
1741 pl011_console_get_options(struct uart_amba_port
*uap
, int *baud
,
1742 int *parity
, int *bits
)
1744 if (readw(uap
->port
.membase
+ UART011_CR
) & UART01x_CR_UARTEN
) {
1745 unsigned int lcr_h
, ibrd
, fbrd
;
1747 lcr_h
= readw(uap
->port
.membase
+ uap
->lcrh_tx
);
1750 if (lcr_h
& UART01x_LCRH_PEN
) {
1751 if (lcr_h
& UART01x_LCRH_EPS
)
1757 if ((lcr_h
& 0x60) == UART01x_LCRH_WLEN_7
)
1762 ibrd
= readw(uap
->port
.membase
+ UART011_IBRD
);
1763 fbrd
= readw(uap
->port
.membase
+ UART011_FBRD
);
1765 *baud
= uap
->port
.uartclk
* 4 / (64 * ibrd
+ fbrd
);
1767 if (uap
->vendor
->oversampling
) {
1768 if (readw(uap
->port
.membase
+ UART011_CR
)
1769 & ST_UART011_CR_OVSFACT
)
1775 static int __init
pl011_console_setup(struct console
*co
, char *options
)
1777 struct uart_amba_port
*uap
;
1785 * Check whether an invalid uart number has been specified, and
1786 * if so, search for the first available port that does have
1789 if (co
->index
>= UART_NR
)
1791 uap
= amba_ports
[co
->index
];
1795 ret
= clk_prepare(uap
->clk
);
1799 if (uap
->port
.dev
->platform_data
) {
1800 struct amba_pl011_data
*plat
;
1802 plat
= uap
->port
.dev
->platform_data
;
1807 uap
->port
.uartclk
= clk_get_rate(uap
->clk
);
1810 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
1812 pl011_console_get_options(uap
, &baud
, &parity
, &bits
);
1814 return uart_set_options(&uap
->port
, co
, baud
, parity
, bits
, flow
);
1817 static struct uart_driver amba_reg
;
1818 static struct console amba_console
= {
1820 .write
= pl011_console_write
,
1821 .device
= uart_console_device
,
1822 .setup
= pl011_console_setup
,
1823 .flags
= CON_PRINTBUFFER
,
1828 #define AMBA_CONSOLE (&amba_console)
1830 #define AMBA_CONSOLE NULL
1833 static struct uart_driver amba_reg
= {
1834 .owner
= THIS_MODULE
,
1835 .driver_name
= "ttyAMA",
1836 .dev_name
= "ttyAMA",
1837 .major
= SERIAL_AMBA_MAJOR
,
1838 .minor
= SERIAL_AMBA_MINOR
,
1840 .cons
= AMBA_CONSOLE
,
1843 static int pl011_probe(struct amba_device
*dev
, const struct amba_id
*id
)
1845 struct uart_amba_port
*uap
;
1846 struct vendor_data
*vendor
= id
->data
;
1847 struct pinctrl
*pinctrl
;
1851 for (i
= 0; i
< ARRAY_SIZE(amba_ports
); i
++)
1852 if (amba_ports
[i
] == NULL
)
1855 if (i
== ARRAY_SIZE(amba_ports
)) {
1860 uap
= kzalloc(sizeof(struct uart_amba_port
), GFP_KERNEL
);
1866 base
= ioremap(dev
->res
.start
, resource_size(&dev
->res
));
1872 pinctrl
= devm_pinctrl_get_select_default(&dev
->dev
);
1873 if (IS_ERR(pinctrl
)) {
1874 ret
= PTR_ERR(pinctrl
);
1878 uap
->clk
= clk_get(&dev
->dev
, NULL
);
1879 if (IS_ERR(uap
->clk
)) {
1880 ret
= PTR_ERR(uap
->clk
);
1884 uap
->vendor
= vendor
;
1885 uap
->lcrh_rx
= vendor
->lcrh_rx
;
1886 uap
->lcrh_tx
= vendor
->lcrh_tx
;
1888 uap
->fifosize
= vendor
->fifosize
;
1889 uap
->interrupt_may_hang
= vendor
->interrupt_may_hang
;
1890 uap
->port
.dev
= &dev
->dev
;
1891 uap
->port
.mapbase
= dev
->res
.start
;
1892 uap
->port
.membase
= base
;
1893 uap
->port
.iotype
= UPIO_MEM
;
1894 uap
->port
.irq
= dev
->irq
[0];
1895 uap
->port
.fifosize
= uap
->fifosize
;
1896 uap
->port
.ops
= &amba_pl011_pops
;
1897 uap
->port
.flags
= UPF_BOOT_AUTOCONF
;
1899 pl011_dma_probe(uap
);
1901 /* Ensure interrupts from this UART are masked and cleared */
1902 writew(0, uap
->port
.membase
+ UART011_IMSC
);
1903 writew(0xffff, uap
->port
.membase
+ UART011_ICR
);
1905 snprintf(uap
->type
, sizeof(uap
->type
), "PL011 rev%u", amba_rev(dev
));
1907 amba_ports
[i
] = uap
;
1909 amba_set_drvdata(dev
, uap
);
1910 ret
= uart_add_one_port(&amba_reg
, &uap
->port
);
1912 amba_set_drvdata(dev
, NULL
);
1913 amba_ports
[i
] = NULL
;
1914 pl011_dma_remove(uap
);
1925 static int pl011_remove(struct amba_device
*dev
)
1927 struct uart_amba_port
*uap
= amba_get_drvdata(dev
);
1930 amba_set_drvdata(dev
, NULL
);
1932 uart_remove_one_port(&amba_reg
, &uap
->port
);
1934 for (i
= 0; i
< ARRAY_SIZE(amba_ports
); i
++)
1935 if (amba_ports
[i
] == uap
)
1936 amba_ports
[i
] = NULL
;
1938 pl011_dma_remove(uap
);
1939 iounmap(uap
->port
.membase
);
1946 static int pl011_suspend(struct amba_device
*dev
, pm_message_t state
)
1948 struct uart_amba_port
*uap
= amba_get_drvdata(dev
);
1953 return uart_suspend_port(&amba_reg
, &uap
->port
);
1956 static int pl011_resume(struct amba_device
*dev
)
1958 struct uart_amba_port
*uap
= amba_get_drvdata(dev
);
1963 return uart_resume_port(&amba_reg
, &uap
->port
);
1967 static struct amba_id pl011_ids
[] = {
1971 .data
= &vendor_arm
,
1981 MODULE_DEVICE_TABLE(amba
, pl011_ids
);
1983 static struct amba_driver pl011_driver
= {
1985 .name
= "uart-pl011",
1987 .id_table
= pl011_ids
,
1988 .probe
= pl011_probe
,
1989 .remove
= pl011_remove
,
1991 .suspend
= pl011_suspend
,
1992 .resume
= pl011_resume
,
1996 static int __init
pl011_init(void)
1999 printk(KERN_INFO
"Serial: AMBA PL011 UART driver\n");
2001 ret
= uart_register_driver(&amba_reg
);
2003 ret
= amba_driver_register(&pl011_driver
);
2005 uart_unregister_driver(&amba_reg
);
2010 static void __exit
pl011_exit(void)
2012 amba_driver_unregister(&pl011_driver
);
2013 uart_unregister_driver(&amba_reg
);
2017 * While this can be a module, if builtin it's most likely the console
2018 * So let's leave module_exit but move module_init to an earlier place
2020 arch_initcall(pl011_init
);
2021 module_exit(pl011_exit
);
2023 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2024 MODULE_DESCRIPTION("ARM AMBA serial port driver");
2025 MODULE_LICENSE("GPL");