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c4adecedde2c89632c41642d0637f33bacf45679
[deliverable/linux.git] / drivers / tty / serial / amba-pl011.c
1 /*
2 * Driver for AMBA serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 * Copyright (C) 2010 ST-Ericsson SA
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * This is a generic driver for ARM AMBA-type serial ports. They
25 * have a lot of 16550-like features, but are not register compatible.
26 * Note that although they do have CTS, DCD and DSR inputs, they do
27 * not have an RI input, nor do they have DTR or RTS outputs. If
28 * required, these have to be supplied via some other means (eg, GPIO)
29 * and hooked into this driver.
30 */
31
32
33 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
34 #define SUPPORT_SYSRQ
35 #endif
36
37 #include <linux/module.h>
38 #include <linux/ioport.h>
39 #include <linux/init.h>
40 #include <linux/console.h>
41 #include <linux/sysrq.h>
42 #include <linux/device.h>
43 #include <linux/tty.h>
44 #include <linux/tty_flip.h>
45 #include <linux/serial_core.h>
46 #include <linux/serial.h>
47 #include <linux/amba/bus.h>
48 #include <linux/amba/serial.h>
49 #include <linux/clk.h>
50 #include <linux/slab.h>
51 #include <linux/dmaengine.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/scatterlist.h>
54 #include <linux/delay.h>
55 #include <linux/types.h>
56 #include <linux/of.h>
57 #include <linux/of_device.h>
58 #include <linux/pinctrl/consumer.h>
59 #include <linux/sizes.h>
60 #include <linux/io.h>
61 #include <linux/acpi.h>
62
63 #include "amba-pl011.h"
64
65 #define UART_NR 14
66
67 #define SERIAL_AMBA_MAJOR 204
68 #define SERIAL_AMBA_MINOR 64
69 #define SERIAL_AMBA_NR UART_NR
70
71 #define AMBA_ISR_PASS_LIMIT 256
72
73 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
74 #define UART_DUMMY_DR_RX (1 << 16)
75
76 static u16 pl011_std_offsets[REG_ARRAY_SIZE] = {
77 [REG_DR] = UART01x_DR,
78 [REG_ST_DMAWM] = ST_UART011_DMAWM,
79 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT,
80 [REG_FR] = UART01x_FR,
81 [REG_ST_LCRH_RX] = ST_UART011_LCRH_RX,
82 [REG_IBRD] = UART011_IBRD,
83 [REG_FBRD] = UART011_FBRD,
84 [REG_LCRH] = UART011_LCRH,
85 [REG_ST_LCRH_TX] = ST_UART011_LCRH_TX,
86 [REG_CR] = UART011_CR,
87 [REG_IFLS] = UART011_IFLS,
88 [REG_IMSC] = UART011_IMSC,
89 [REG_RIS] = UART011_RIS,
90 [REG_MIS] = UART011_MIS,
91 [REG_ICR] = UART011_ICR,
92 [REG_DMACR] = UART011_DMACR,
93 [REG_ST_XFCR] = ST_UART011_XFCR,
94 [REG_ST_XON1] = ST_UART011_XON1,
95 [REG_ST_XON2] = ST_UART011_XON2,
96 [REG_ST_XOFF1] = ST_UART011_XOFF1,
97 [REG_ST_XOFF2] = ST_UART011_XOFF2,
98 [REG_ST_ITCR] = ST_UART011_ITCR,
99 [REG_ST_ITIP] = ST_UART011_ITIP,
100 [REG_ST_ABCR] = ST_UART011_ABCR,
101 [REG_ST_ABIMSC] = ST_UART011_ABIMSC,
102 };
103
104 /* There is by now at least one vendor with differing details, so handle it */
105 struct vendor_data {
106 const u16 *reg_offset;
107 unsigned int ifls;
108 unsigned int lcrh_tx;
109 unsigned int lcrh_rx;
110 bool oversampling;
111 bool dma_threshold;
112 bool cts_event_workaround;
113 bool always_enabled;
114 bool fixed_options;
115
116 unsigned int (*get_fifosize)(struct amba_device *dev);
117 };
118
119 static unsigned int get_fifosize_arm(struct amba_device *dev)
120 {
121 return amba_rev(dev) < 3 ? 16 : 32;
122 }
123
124 static struct vendor_data vendor_arm = {
125 .reg_offset = pl011_std_offsets,
126 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
127 .lcrh_tx = REG_LCRH,
128 .lcrh_rx = REG_LCRH,
129 .oversampling = false,
130 .dma_threshold = false,
131 .cts_event_workaround = false,
132 .always_enabled = false,
133 .fixed_options = false,
134 .get_fifosize = get_fifosize_arm,
135 };
136
137 static struct vendor_data vendor_sbsa = {
138 .reg_offset = pl011_std_offsets,
139 .oversampling = false,
140 .dma_threshold = false,
141 .cts_event_workaround = false,
142 .always_enabled = true,
143 .fixed_options = true,
144 };
145
146 static u16 pl011_st_offsets[REG_ARRAY_SIZE] = {
147 [REG_DR] = UART01x_DR,
148 [REG_ST_DMAWM] = ST_UART011_DMAWM,
149 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT,
150 [REG_FR] = UART01x_FR,
151 [REG_ST_LCRH_RX] = ST_UART011_LCRH_RX,
152 [REG_IBRD] = UART011_IBRD,
153 [REG_FBRD] = UART011_FBRD,
154 [REG_LCRH] = UART011_LCRH,
155 [REG_ST_LCRH_TX] = ST_UART011_LCRH_TX,
156 [REG_CR] = UART011_CR,
157 [REG_IFLS] = UART011_IFLS,
158 [REG_IMSC] = UART011_IMSC,
159 [REG_RIS] = UART011_RIS,
160 [REG_MIS] = UART011_MIS,
161 [REG_ICR] = UART011_ICR,
162 [REG_DMACR] = UART011_DMACR,
163 [REG_ST_XFCR] = ST_UART011_XFCR,
164 [REG_ST_XON1] = ST_UART011_XON1,
165 [REG_ST_XON2] = ST_UART011_XON2,
166 [REG_ST_XOFF1] = ST_UART011_XOFF1,
167 [REG_ST_XOFF2] = ST_UART011_XOFF2,
168 [REG_ST_ITCR] = ST_UART011_ITCR,
169 [REG_ST_ITIP] = ST_UART011_ITIP,
170 [REG_ST_ABCR] = ST_UART011_ABCR,
171 [REG_ST_ABIMSC] = ST_UART011_ABIMSC,
172 };
173
174 static unsigned int get_fifosize_st(struct amba_device *dev)
175 {
176 return 64;
177 }
178
179 static struct vendor_data vendor_st = {
180 .reg_offset = pl011_st_offsets,
181 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
182 .lcrh_tx = REG_ST_LCRH_TX,
183 .lcrh_rx = REG_ST_LCRH_RX,
184 .oversampling = true,
185 .dma_threshold = true,
186 .cts_event_workaround = true,
187 .always_enabled = false,
188 .fixed_options = false,
189 .get_fifosize = get_fifosize_st,
190 };
191
192 /* Deals with DMA transactions */
193
194 struct pl011_sgbuf {
195 struct scatterlist sg;
196 char *buf;
197 };
198
199 struct pl011_dmarx_data {
200 struct dma_chan *chan;
201 struct completion complete;
202 bool use_buf_b;
203 struct pl011_sgbuf sgbuf_a;
204 struct pl011_sgbuf sgbuf_b;
205 dma_cookie_t cookie;
206 bool running;
207 struct timer_list timer;
208 unsigned int last_residue;
209 unsigned long last_jiffies;
210 bool auto_poll_rate;
211 unsigned int poll_rate;
212 unsigned int poll_timeout;
213 };
214
215 struct pl011_dmatx_data {
216 struct dma_chan *chan;
217 struct scatterlist sg;
218 char *buf;
219 bool queued;
220 };
221
222 /*
223 * We wrap our port structure around the generic uart_port.
224 */
225 struct uart_amba_port {
226 struct uart_port port;
227 const u16 *reg_offset;
228 struct clk *clk;
229 const struct vendor_data *vendor;
230 unsigned int dmacr; /* dma control reg */
231 unsigned int im; /* interrupt mask */
232 unsigned int old_status;
233 unsigned int fifosize; /* vendor-specific */
234 unsigned int lcrh_tx; /* vendor-specific */
235 unsigned int lcrh_rx; /* vendor-specific */
236 unsigned int old_cr; /* state during shutdown */
237 bool autorts;
238 unsigned int fixed_baud; /* vendor-set fixed baud rate */
239 char type[12];
240 #ifdef CONFIG_DMA_ENGINE
241 /* DMA stuff */
242 bool using_tx_dma;
243 bool using_rx_dma;
244 struct pl011_dmarx_data dmarx;
245 struct pl011_dmatx_data dmatx;
246 bool dma_probed;
247 #endif
248 };
249
250 static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap,
251 unsigned int reg)
252 {
253 return uap->reg_offset[reg];
254 }
255
256 static unsigned int pl011_read(const struct uart_amba_port *uap,
257 unsigned int reg)
258 {
259 return readw(uap->port.membase + pl011_reg_to_offset(uap, reg));
260 }
261
262 static void pl011_write(unsigned int val, const struct uart_amba_port *uap,
263 unsigned int reg)
264 {
265 writew(val, uap->port.membase + pl011_reg_to_offset(uap, reg));
266 }
267
268 /*
269 * Reads up to 256 characters from the FIFO or until it's empty and
270 * inserts them into the TTY layer. Returns the number of characters
271 * read from the FIFO.
272 */
273 static int pl011_fifo_to_tty(struct uart_amba_port *uap)
274 {
275 u16 status;
276 unsigned int ch, flag, max_count = 256;
277 int fifotaken = 0;
278
279 while (max_count--) {
280 status = pl011_read(uap, REG_FR);
281 if (status & UART01x_FR_RXFE)
282 break;
283
284 /* Take chars from the FIFO and update status */
285 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;
286 flag = TTY_NORMAL;
287 uap->port.icount.rx++;
288 fifotaken++;
289
290 if (unlikely(ch & UART_DR_ERROR)) {
291 if (ch & UART011_DR_BE) {
292 ch &= ~(UART011_DR_FE | UART011_DR_PE);
293 uap->port.icount.brk++;
294 if (uart_handle_break(&uap->port))
295 continue;
296 } else if (ch & UART011_DR_PE)
297 uap->port.icount.parity++;
298 else if (ch & UART011_DR_FE)
299 uap->port.icount.frame++;
300 if (ch & UART011_DR_OE)
301 uap->port.icount.overrun++;
302
303 ch &= uap->port.read_status_mask;
304
305 if (ch & UART011_DR_BE)
306 flag = TTY_BREAK;
307 else if (ch & UART011_DR_PE)
308 flag = TTY_PARITY;
309 else if (ch & UART011_DR_FE)
310 flag = TTY_FRAME;
311 }
312
313 if (uart_handle_sysrq_char(&uap->port, ch & 255))
314 continue;
315
316 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
317 }
318
319 return fifotaken;
320 }
321
322
323 /*
324 * All the DMA operation mode stuff goes inside this ifdef.
325 * This assumes that you have a generic DMA device interface,
326 * no custom DMA interfaces are supported.
327 */
328 #ifdef CONFIG_DMA_ENGINE
329
330 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE
331
332 static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
333 enum dma_data_direction dir)
334 {
335 dma_addr_t dma_addr;
336
337 sg->buf = dma_alloc_coherent(chan->device->dev,
338 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
339 if (!sg->buf)
340 return -ENOMEM;
341
342 sg_init_table(&sg->sg, 1);
343 sg_set_page(&sg->sg, phys_to_page(dma_addr),
344 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
345 sg_dma_address(&sg->sg) = dma_addr;
346 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE;
347
348 return 0;
349 }
350
351 static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
352 enum dma_data_direction dir)
353 {
354 if (sg->buf) {
355 dma_free_coherent(chan->device->dev,
356 PL011_DMA_BUFFER_SIZE, sg->buf,
357 sg_dma_address(&sg->sg));
358 }
359 }
360
361 static void pl011_dma_probe(struct uart_amba_port *uap)
362 {
363 /* DMA is the sole user of the platform data right now */
364 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
365 struct device *dev = uap->port.dev;
366 struct dma_slave_config tx_conf = {
367 .dst_addr = uap->port.mapbase +
368 pl011_reg_to_offset(uap, REG_DR),
369 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
370 .direction = DMA_MEM_TO_DEV,
371 .dst_maxburst = uap->fifosize >> 1,
372 .device_fc = false,
373 };
374 struct dma_chan *chan;
375 dma_cap_mask_t mask;
376
377 uap->dma_probed = true;
378 chan = dma_request_slave_channel_reason(dev, "tx");
379 if (IS_ERR(chan)) {
380 if (PTR_ERR(chan) == -EPROBE_DEFER) {
381 uap->dma_probed = false;
382 return;
383 }
384
385 /* We need platform data */
386 if (!plat || !plat->dma_filter) {
387 dev_info(uap->port.dev, "no DMA platform data\n");
388 return;
389 }
390
391 /* Try to acquire a generic DMA engine slave TX channel */
392 dma_cap_zero(mask);
393 dma_cap_set(DMA_SLAVE, mask);
394
395 chan = dma_request_channel(mask, plat->dma_filter,
396 plat->dma_tx_param);
397 if (!chan) {
398 dev_err(uap->port.dev, "no TX DMA channel!\n");
399 return;
400 }
401 }
402
403 dmaengine_slave_config(chan, &tx_conf);
404 uap->dmatx.chan = chan;
405
406 dev_info(uap->port.dev, "DMA channel TX %s\n",
407 dma_chan_name(uap->dmatx.chan));
408
409 /* Optionally make use of an RX channel as well */
410 chan = dma_request_slave_channel(dev, "rx");
411
412 if (!chan && plat->dma_rx_param) {
413 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
414
415 if (!chan) {
416 dev_err(uap->port.dev, "no RX DMA channel!\n");
417 return;
418 }
419 }
420
421 if (chan) {
422 struct dma_slave_config rx_conf = {
423 .src_addr = uap->port.mapbase +
424 pl011_reg_to_offset(uap, REG_DR),
425 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
426 .direction = DMA_DEV_TO_MEM,
427 .src_maxburst = uap->fifosize >> 2,
428 .device_fc = false,
429 };
430 struct dma_slave_caps caps;
431
432 /*
433 * Some DMA controllers provide information on their capabilities.
434 * If the controller does, check for suitable residue processing
435 * otherwise assime all is well.
436 */
437 if (0 == dma_get_slave_caps(chan, &caps)) {
438 if (caps.residue_granularity ==
439 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
440 dma_release_channel(chan);
441 dev_info(uap->port.dev,
442 "RX DMA disabled - no residue processing\n");
443 return;
444 }
445 }
446 dmaengine_slave_config(chan, &rx_conf);
447 uap->dmarx.chan = chan;
448
449 uap->dmarx.auto_poll_rate = false;
450 if (plat && plat->dma_rx_poll_enable) {
451 /* Set poll rate if specified. */
452 if (plat->dma_rx_poll_rate) {
453 uap->dmarx.auto_poll_rate = false;
454 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
455 } else {
456 /*
457 * 100 ms defaults to poll rate if not
458 * specified. This will be adjusted with
459 * the baud rate at set_termios.
460 */
461 uap->dmarx.auto_poll_rate = true;
462 uap->dmarx.poll_rate = 100;
463 }
464 /* 3 secs defaults poll_timeout if not specified. */
465 if (plat->dma_rx_poll_timeout)
466 uap->dmarx.poll_timeout =
467 plat->dma_rx_poll_timeout;
468 else
469 uap->dmarx.poll_timeout = 3000;
470 } else if (!plat && dev->of_node) {
471 uap->dmarx.auto_poll_rate = of_property_read_bool(
472 dev->of_node, "auto-poll");
473 if (uap->dmarx.auto_poll_rate) {
474 u32 x;
475
476 if (0 == of_property_read_u32(dev->of_node,
477 "poll-rate-ms", &x))
478 uap->dmarx.poll_rate = x;
479 else
480 uap->dmarx.poll_rate = 100;
481 if (0 == of_property_read_u32(dev->of_node,
482 "poll-timeout-ms", &x))
483 uap->dmarx.poll_timeout = x;
484 else
485 uap->dmarx.poll_timeout = 3000;
486 }
487 }
488 dev_info(uap->port.dev, "DMA channel RX %s\n",
489 dma_chan_name(uap->dmarx.chan));
490 }
491 }
492
493 static void pl011_dma_remove(struct uart_amba_port *uap)
494 {
495 if (uap->dmatx.chan)
496 dma_release_channel(uap->dmatx.chan);
497 if (uap->dmarx.chan)
498 dma_release_channel(uap->dmarx.chan);
499 }
500
501 /* Forward declare these for the refill routine */
502 static int pl011_dma_tx_refill(struct uart_amba_port *uap);
503 static void pl011_start_tx_pio(struct uart_amba_port *uap);
504
505 /*
506 * The current DMA TX buffer has been sent.
507 * Try to queue up another DMA buffer.
508 */
509 static void pl011_dma_tx_callback(void *data)
510 {
511 struct uart_amba_port *uap = data;
512 struct pl011_dmatx_data *dmatx = &uap->dmatx;
513 unsigned long flags;
514 u16 dmacr;
515
516 spin_lock_irqsave(&uap->port.lock, flags);
517 if (uap->dmatx.queued)
518 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
519 DMA_TO_DEVICE);
520
521 dmacr = uap->dmacr;
522 uap->dmacr = dmacr & ~UART011_TXDMAE;
523 pl011_write(uap->dmacr, uap, REG_DMACR);
524
525 /*
526 * If TX DMA was disabled, it means that we've stopped the DMA for
527 * some reason (eg, XOFF received, or we want to send an X-char.)
528 *
529 * Note: we need to be careful here of a potential race between DMA
530 * and the rest of the driver - if the driver disables TX DMA while
531 * a TX buffer completing, we must update the tx queued status to
532 * get further refills (hence we check dmacr).
533 */
534 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
535 uart_circ_empty(&uap->port.state->xmit)) {
536 uap->dmatx.queued = false;
537 spin_unlock_irqrestore(&uap->port.lock, flags);
538 return;
539 }
540
541 if (pl011_dma_tx_refill(uap) <= 0)
542 /*
543 * We didn't queue a DMA buffer for some reason, but we
544 * have data pending to be sent. Re-enable the TX IRQ.
545 */
546 pl011_start_tx_pio(uap);
547
548 spin_unlock_irqrestore(&uap->port.lock, flags);
549 }
550
551 /*
552 * Try to refill the TX DMA buffer.
553 * Locking: called with port lock held and IRQs disabled.
554 * Returns:
555 * 1 if we queued up a TX DMA buffer.
556 * 0 if we didn't want to handle this by DMA
557 * <0 on error
558 */
559 static int pl011_dma_tx_refill(struct uart_amba_port *uap)
560 {
561 struct pl011_dmatx_data *dmatx = &uap->dmatx;
562 struct dma_chan *chan = dmatx->chan;
563 struct dma_device *dma_dev = chan->device;
564 struct dma_async_tx_descriptor *desc;
565 struct circ_buf *xmit = &uap->port.state->xmit;
566 unsigned int count;
567
568 /*
569 * Try to avoid the overhead involved in using DMA if the
570 * transaction fits in the first half of the FIFO, by using
571 * the standard interrupt handling. This ensures that we
572 * issue a uart_write_wakeup() at the appropriate time.
573 */
574 count = uart_circ_chars_pending(xmit);
575 if (count < (uap->fifosize >> 1)) {
576 uap->dmatx.queued = false;
577 return 0;
578 }
579
580 /*
581 * Bodge: don't send the last character by DMA, as this
582 * will prevent XON from notifying us to restart DMA.
583 */
584 count -= 1;
585
586 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
587 if (count > PL011_DMA_BUFFER_SIZE)
588 count = PL011_DMA_BUFFER_SIZE;
589
590 if (xmit->tail < xmit->head)
591 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
592 else {
593 size_t first = UART_XMIT_SIZE - xmit->tail;
594 size_t second;
595
596 if (first > count)
597 first = count;
598 second = count - first;
599
600 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
601 if (second)
602 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
603 }
604
605 dmatx->sg.length = count;
606
607 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
608 uap->dmatx.queued = false;
609 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
610 return -EBUSY;
611 }
612
613 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
614 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
615 if (!desc) {
616 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
617 uap->dmatx.queued = false;
618 /*
619 * If DMA cannot be used right now, we complete this
620 * transaction via IRQ and let the TTY layer retry.
621 */
622 dev_dbg(uap->port.dev, "TX DMA busy\n");
623 return -EBUSY;
624 }
625
626 /* Some data to go along to the callback */
627 desc->callback = pl011_dma_tx_callback;
628 desc->callback_param = uap;
629
630 /* All errors should happen at prepare time */
631 dmaengine_submit(desc);
632
633 /* Fire the DMA transaction */
634 dma_dev->device_issue_pending(chan);
635
636 uap->dmacr |= UART011_TXDMAE;
637 pl011_write(uap->dmacr, uap, REG_DMACR);
638 uap->dmatx.queued = true;
639
640 /*
641 * Now we know that DMA will fire, so advance the ring buffer
642 * with the stuff we just dispatched.
643 */
644 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
645 uap->port.icount.tx += count;
646
647 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
648 uart_write_wakeup(&uap->port);
649
650 return 1;
651 }
652
653 /*
654 * We received a transmit interrupt without a pending X-char but with
655 * pending characters.
656 * Locking: called with port lock held and IRQs disabled.
657 * Returns:
658 * false if we want to use PIO to transmit
659 * true if we queued a DMA buffer
660 */
661 static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
662 {
663 if (!uap->using_tx_dma)
664 return false;
665
666 /*
667 * If we already have a TX buffer queued, but received a
668 * TX interrupt, it will be because we've just sent an X-char.
669 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
670 */
671 if (uap->dmatx.queued) {
672 uap->dmacr |= UART011_TXDMAE;
673 pl011_write(uap->dmacr, uap, REG_DMACR);
674 uap->im &= ~UART011_TXIM;
675 pl011_write(uap->im, uap, REG_IMSC);
676 return true;
677 }
678
679 /*
680 * We don't have a TX buffer queued, so try to queue one.
681 * If we successfully queued a buffer, mask the TX IRQ.
682 */
683 if (pl011_dma_tx_refill(uap) > 0) {
684 uap->im &= ~UART011_TXIM;
685 pl011_write(uap->im, uap, REG_IMSC);
686 return true;
687 }
688 return false;
689 }
690
691 /*
692 * Stop the DMA transmit (eg, due to received XOFF).
693 * Locking: called with port lock held and IRQs disabled.
694 */
695 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
696 {
697 if (uap->dmatx.queued) {
698 uap->dmacr &= ~UART011_TXDMAE;
699 pl011_write(uap->dmacr, uap, REG_DMACR);
700 }
701 }
702
703 /*
704 * Try to start a DMA transmit, or in the case of an XON/OFF
705 * character queued for send, try to get that character out ASAP.
706 * Locking: called with port lock held and IRQs disabled.
707 * Returns:
708 * false if we want the TX IRQ to be enabled
709 * true if we have a buffer queued
710 */
711 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
712 {
713 u16 dmacr;
714
715 if (!uap->using_tx_dma)
716 return false;
717
718 if (!uap->port.x_char) {
719 /* no X-char, try to push chars out in DMA mode */
720 bool ret = true;
721
722 if (!uap->dmatx.queued) {
723 if (pl011_dma_tx_refill(uap) > 0) {
724 uap->im &= ~UART011_TXIM;
725 pl011_write(uap->im, uap, REG_IMSC);
726 } else
727 ret = false;
728 } else if (!(uap->dmacr & UART011_TXDMAE)) {
729 uap->dmacr |= UART011_TXDMAE;
730 pl011_write(uap->dmacr, uap, REG_DMACR);
731 }
732 return ret;
733 }
734
735 /*
736 * We have an X-char to send. Disable DMA to prevent it loading
737 * the TX fifo, and then see if we can stuff it into the FIFO.
738 */
739 dmacr = uap->dmacr;
740 uap->dmacr &= ~UART011_TXDMAE;
741 pl011_write(uap->dmacr, uap, REG_DMACR);
742
743 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {
744 /*
745 * No space in the FIFO, so enable the transmit interrupt
746 * so we know when there is space. Note that once we've
747 * loaded the character, we should just re-enable DMA.
748 */
749 return false;
750 }
751
752 pl011_write(uap->port.x_char, uap, REG_DR);
753 uap->port.icount.tx++;
754 uap->port.x_char = 0;
755
756 /* Success - restore the DMA state */
757 uap->dmacr = dmacr;
758 pl011_write(dmacr, uap, REG_DMACR);
759
760 return true;
761 }
762
763 /*
764 * Flush the transmit buffer.
765 * Locking: called with port lock held and IRQs disabled.
766 */
767 static void pl011_dma_flush_buffer(struct uart_port *port)
768 __releases(&uap->port.lock)
769 __acquires(&uap->port.lock)
770 {
771 struct uart_amba_port *uap =
772 container_of(port, struct uart_amba_port, port);
773
774 if (!uap->using_tx_dma)
775 return;
776
777 /* Avoid deadlock with the DMA engine callback */
778 spin_unlock(&uap->port.lock);
779 dmaengine_terminate_all(uap->dmatx.chan);
780 spin_lock(&uap->port.lock);
781 if (uap->dmatx.queued) {
782 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
783 DMA_TO_DEVICE);
784 uap->dmatx.queued = false;
785 uap->dmacr &= ~UART011_TXDMAE;
786 pl011_write(uap->dmacr, uap, REG_DMACR);
787 }
788 }
789
790 static void pl011_dma_rx_callback(void *data);
791
792 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
793 {
794 struct dma_chan *rxchan = uap->dmarx.chan;
795 struct pl011_dmarx_data *dmarx = &uap->dmarx;
796 struct dma_async_tx_descriptor *desc;
797 struct pl011_sgbuf *sgbuf;
798
799 if (!rxchan)
800 return -EIO;
801
802 /* Start the RX DMA job */
803 sgbuf = uap->dmarx.use_buf_b ?
804 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
805 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
806 DMA_DEV_TO_MEM,
807 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
808 /*
809 * If the DMA engine is busy and cannot prepare a
810 * channel, no big deal, the driver will fall back
811 * to interrupt mode as a result of this error code.
812 */
813 if (!desc) {
814 uap->dmarx.running = false;
815 dmaengine_terminate_all(rxchan);
816 return -EBUSY;
817 }
818
819 /* Some data to go along to the callback */
820 desc->callback = pl011_dma_rx_callback;
821 desc->callback_param = uap;
822 dmarx->cookie = dmaengine_submit(desc);
823 dma_async_issue_pending(rxchan);
824
825 uap->dmacr |= UART011_RXDMAE;
826 pl011_write(uap->dmacr, uap, REG_DMACR);
827 uap->dmarx.running = true;
828
829 uap->im &= ~UART011_RXIM;
830 pl011_write(uap->im, uap, REG_IMSC);
831
832 return 0;
833 }
834
835 /*
836 * This is called when either the DMA job is complete, or
837 * the FIFO timeout interrupt occurred. This must be called
838 * with the port spinlock uap->port.lock held.
839 */
840 static void pl011_dma_rx_chars(struct uart_amba_port *uap,
841 u32 pending, bool use_buf_b,
842 bool readfifo)
843 {
844 struct tty_port *port = &uap->port.state->port;
845 struct pl011_sgbuf *sgbuf = use_buf_b ?
846 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
847 int dma_count = 0;
848 u32 fifotaken = 0; /* only used for vdbg() */
849
850 struct pl011_dmarx_data *dmarx = &uap->dmarx;
851 int dmataken = 0;
852
853 if (uap->dmarx.poll_rate) {
854 /* The data can be taken by polling */
855 dmataken = sgbuf->sg.length - dmarx->last_residue;
856 /* Recalculate the pending size */
857 if (pending >= dmataken)
858 pending -= dmataken;
859 }
860
861 /* Pick the remain data from the DMA */
862 if (pending) {
863
864 /*
865 * First take all chars in the DMA pipe, then look in the FIFO.
866 * Note that tty_insert_flip_buf() tries to take as many chars
867 * as it can.
868 */
869 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
870 pending);
871
872 uap->port.icount.rx += dma_count;
873 if (dma_count < pending)
874 dev_warn(uap->port.dev,
875 "couldn't insert all characters (TTY is full?)\n");
876 }
877
878 /* Reset the last_residue for Rx DMA poll */
879 if (uap->dmarx.poll_rate)
880 dmarx->last_residue = sgbuf->sg.length;
881
882 /*
883 * Only continue with trying to read the FIFO if all DMA chars have
884 * been taken first.
885 */
886 if (dma_count == pending && readfifo) {
887 /* Clear any error flags */
888 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
889 UART011_FEIS, uap, REG_ICR);
890
891 /*
892 * If we read all the DMA'd characters, and we had an
893 * incomplete buffer, that could be due to an rx error, or
894 * maybe we just timed out. Read any pending chars and check
895 * the error status.
896 *
897 * Error conditions will only occur in the FIFO, these will
898 * trigger an immediate interrupt and stop the DMA job, so we
899 * will always find the error in the FIFO, never in the DMA
900 * buffer.
901 */
902 fifotaken = pl011_fifo_to_tty(uap);
903 }
904
905 spin_unlock(&uap->port.lock);
906 dev_vdbg(uap->port.dev,
907 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
908 dma_count, fifotaken);
909 tty_flip_buffer_push(port);
910 spin_lock(&uap->port.lock);
911 }
912
913 static void pl011_dma_rx_irq(struct uart_amba_port *uap)
914 {
915 struct pl011_dmarx_data *dmarx = &uap->dmarx;
916 struct dma_chan *rxchan = dmarx->chan;
917 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
918 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
919 size_t pending;
920 struct dma_tx_state state;
921 enum dma_status dmastat;
922
923 /*
924 * Pause the transfer so we can trust the current counter,
925 * do this before we pause the PL011 block, else we may
926 * overflow the FIFO.
927 */
928 if (dmaengine_pause(rxchan))
929 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
930 dmastat = rxchan->device->device_tx_status(rxchan,
931 dmarx->cookie, &state);
932 if (dmastat != DMA_PAUSED)
933 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
934
935 /* Disable RX DMA - incoming data will wait in the FIFO */
936 uap->dmacr &= ~UART011_RXDMAE;
937 pl011_write(uap->dmacr, uap, REG_DMACR);
938 uap->dmarx.running = false;
939
940 pending = sgbuf->sg.length - state.residue;
941 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
942 /* Then we terminate the transfer - we now know our residue */
943 dmaengine_terminate_all(rxchan);
944
945 /*
946 * This will take the chars we have so far and insert
947 * into the framework.
948 */
949 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
950
951 /* Switch buffer & re-trigger DMA job */
952 dmarx->use_buf_b = !dmarx->use_buf_b;
953 if (pl011_dma_rx_trigger_dma(uap)) {
954 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
955 "fall back to interrupt mode\n");
956 uap->im |= UART011_RXIM;
957 pl011_write(uap->im, uap, REG_IMSC);
958 }
959 }
960
961 static void pl011_dma_rx_callback(void *data)
962 {
963 struct uart_amba_port *uap = data;
964 struct pl011_dmarx_data *dmarx = &uap->dmarx;
965 struct dma_chan *rxchan = dmarx->chan;
966 bool lastbuf = dmarx->use_buf_b;
967 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
968 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
969 size_t pending;
970 struct dma_tx_state state;
971 int ret;
972
973 /*
974 * This completion interrupt occurs typically when the
975 * RX buffer is totally stuffed but no timeout has yet
976 * occurred. When that happens, we just want the RX
977 * routine to flush out the secondary DMA buffer while
978 * we immediately trigger the next DMA job.
979 */
980 spin_lock_irq(&uap->port.lock);
981 /*
982 * Rx data can be taken by the UART interrupts during
983 * the DMA irq handler. So we check the residue here.
984 */
985 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
986 pending = sgbuf->sg.length - state.residue;
987 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
988 /* Then we terminate the transfer - we now know our residue */
989 dmaengine_terminate_all(rxchan);
990
991 uap->dmarx.running = false;
992 dmarx->use_buf_b = !lastbuf;
993 ret = pl011_dma_rx_trigger_dma(uap);
994
995 pl011_dma_rx_chars(uap, pending, lastbuf, false);
996 spin_unlock_irq(&uap->port.lock);
997 /*
998 * Do this check after we picked the DMA chars so we don't
999 * get some IRQ immediately from RX.
1000 */
1001 if (ret) {
1002 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
1003 "fall back to interrupt mode\n");
1004 uap->im |= UART011_RXIM;
1005 pl011_write(uap->im, uap, REG_IMSC);
1006 }
1007 }
1008
1009 /*
1010 * Stop accepting received characters, when we're shutting down or
1011 * suspending this port.
1012 * Locking: called with port lock held and IRQs disabled.
1013 */
1014 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1015 {
1016 /* FIXME. Just disable the DMA enable */
1017 uap->dmacr &= ~UART011_RXDMAE;
1018 pl011_write(uap->dmacr, uap, REG_DMACR);
1019 }
1020
1021 /*
1022 * Timer handler for Rx DMA polling.
1023 * Every polling, It checks the residue in the dma buffer and transfer
1024 * data to the tty. Also, last_residue is updated for the next polling.
1025 */
1026 static void pl011_dma_rx_poll(unsigned long args)
1027 {
1028 struct uart_amba_port *uap = (struct uart_amba_port *)args;
1029 struct tty_port *port = &uap->port.state->port;
1030 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1031 struct dma_chan *rxchan = uap->dmarx.chan;
1032 unsigned long flags = 0;
1033 unsigned int dmataken = 0;
1034 unsigned int size = 0;
1035 struct pl011_sgbuf *sgbuf;
1036 int dma_count;
1037 struct dma_tx_state state;
1038
1039 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
1040 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1041 if (likely(state.residue < dmarx->last_residue)) {
1042 dmataken = sgbuf->sg.length - dmarx->last_residue;
1043 size = dmarx->last_residue - state.residue;
1044 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
1045 size);
1046 if (dma_count == size)
1047 dmarx->last_residue = state.residue;
1048 dmarx->last_jiffies = jiffies;
1049 }
1050 tty_flip_buffer_push(port);
1051
1052 /*
1053 * If no data is received in poll_timeout, the driver will fall back
1054 * to interrupt mode. We will retrigger DMA at the first interrupt.
1055 */
1056 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
1057 > uap->dmarx.poll_timeout) {
1058
1059 spin_lock_irqsave(&uap->port.lock, flags);
1060 pl011_dma_rx_stop(uap);
1061 uap->im |= UART011_RXIM;
1062 pl011_write(uap->im, uap, REG_IMSC);
1063 spin_unlock_irqrestore(&uap->port.lock, flags);
1064
1065 uap->dmarx.running = false;
1066 dmaengine_terminate_all(rxchan);
1067 del_timer(&uap->dmarx.timer);
1068 } else {
1069 mod_timer(&uap->dmarx.timer,
1070 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1071 }
1072 }
1073
1074 static void pl011_dma_startup(struct uart_amba_port *uap)
1075 {
1076 int ret;
1077
1078 if (!uap->dma_probed)
1079 pl011_dma_probe(uap);
1080
1081 if (!uap->dmatx.chan)
1082 return;
1083
1084 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
1085 if (!uap->dmatx.buf) {
1086 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
1087 uap->port.fifosize = uap->fifosize;
1088 return;
1089 }
1090
1091 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
1092
1093 /* The DMA buffer is now the FIFO the TTY subsystem can use */
1094 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
1095 uap->using_tx_dma = true;
1096
1097 if (!uap->dmarx.chan)
1098 goto skip_rx;
1099
1100 /* Allocate and map DMA RX buffers */
1101 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1102 DMA_FROM_DEVICE);
1103 if (ret) {
1104 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1105 "RX buffer A", ret);
1106 goto skip_rx;
1107 }
1108
1109 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
1110 DMA_FROM_DEVICE);
1111 if (ret) {
1112 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1113 "RX buffer B", ret);
1114 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1115 DMA_FROM_DEVICE);
1116 goto skip_rx;
1117 }
1118
1119 uap->using_rx_dma = true;
1120
1121 skip_rx:
1122 /* Turn on DMA error (RX/TX will be enabled on demand) */
1123 uap->dmacr |= UART011_DMAONERR;
1124 pl011_write(uap->dmacr, uap, REG_DMACR);
1125
1126 /*
1127 * ST Micro variants has some specific dma burst threshold
1128 * compensation. Set this to 16 bytes, so burst will only
1129 * be issued above/below 16 bytes.
1130 */
1131 if (uap->vendor->dma_threshold)
1132 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
1133 uap, REG_ST_DMAWM);
1134
1135 if (uap->using_rx_dma) {
1136 if (pl011_dma_rx_trigger_dma(uap))
1137 dev_dbg(uap->port.dev, "could not trigger initial "
1138 "RX DMA job, fall back to interrupt mode\n");
1139 if (uap->dmarx.poll_rate) {
1140 init_timer(&(uap->dmarx.timer));
1141 uap->dmarx.timer.function = pl011_dma_rx_poll;
1142 uap->dmarx.timer.data = (unsigned long)uap;
1143 mod_timer(&uap->dmarx.timer,
1144 jiffies +
1145 msecs_to_jiffies(uap->dmarx.poll_rate));
1146 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1147 uap->dmarx.last_jiffies = jiffies;
1148 }
1149 }
1150 }
1151
1152 static void pl011_dma_shutdown(struct uart_amba_port *uap)
1153 {
1154 if (!(uap->using_tx_dma || uap->using_rx_dma))
1155 return;
1156
1157 /* Disable RX and TX DMA */
1158 while (pl011_read(uap, REG_FR) & UART01x_FR_BUSY)
1159 barrier();
1160
1161 spin_lock_irq(&uap->port.lock);
1162 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
1163 pl011_write(uap->dmacr, uap, REG_DMACR);
1164 spin_unlock_irq(&uap->port.lock);
1165
1166 if (uap->using_tx_dma) {
1167 /* In theory, this should already be done by pl011_dma_flush_buffer */
1168 dmaengine_terminate_all(uap->dmatx.chan);
1169 if (uap->dmatx.queued) {
1170 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
1171 DMA_TO_DEVICE);
1172 uap->dmatx.queued = false;
1173 }
1174
1175 kfree(uap->dmatx.buf);
1176 uap->using_tx_dma = false;
1177 }
1178
1179 if (uap->using_rx_dma) {
1180 dmaengine_terminate_all(uap->dmarx.chan);
1181 /* Clean up the RX DMA */
1182 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
1183 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
1184 if (uap->dmarx.poll_rate)
1185 del_timer_sync(&uap->dmarx.timer);
1186 uap->using_rx_dma = false;
1187 }
1188 }
1189
1190 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1191 {
1192 return uap->using_rx_dma;
1193 }
1194
1195 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1196 {
1197 return uap->using_rx_dma && uap->dmarx.running;
1198 }
1199
1200 #else
1201 /* Blank functions if the DMA engine is not available */
1202 static inline void pl011_dma_probe(struct uart_amba_port *uap)
1203 {
1204 }
1205
1206 static inline void pl011_dma_remove(struct uart_amba_port *uap)
1207 {
1208 }
1209
1210 static inline void pl011_dma_startup(struct uart_amba_port *uap)
1211 {
1212 }
1213
1214 static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1215 {
1216 }
1217
1218 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1219 {
1220 return false;
1221 }
1222
1223 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1224 {
1225 }
1226
1227 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1228 {
1229 return false;
1230 }
1231
1232 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1233 {
1234 }
1235
1236 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1237 {
1238 }
1239
1240 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1241 {
1242 return -EIO;
1243 }
1244
1245 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1246 {
1247 return false;
1248 }
1249
1250 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1251 {
1252 return false;
1253 }
1254
1255 #define pl011_dma_flush_buffer NULL
1256 #endif
1257
1258 static void pl011_stop_tx(struct uart_port *port)
1259 {
1260 struct uart_amba_port *uap =
1261 container_of(port, struct uart_amba_port, port);
1262
1263 uap->im &= ~UART011_TXIM;
1264 pl011_write(uap->im, uap, REG_IMSC);
1265 pl011_dma_tx_stop(uap);
1266 }
1267
1268 static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
1269
1270 /* Start TX with programmed I/O only (no DMA) */
1271 static void pl011_start_tx_pio(struct uart_amba_port *uap)
1272 {
1273 uap->im |= UART011_TXIM;
1274 pl011_write(uap->im, uap, REG_IMSC);
1275 pl011_tx_chars(uap, false);
1276 }
1277
1278 static void pl011_start_tx(struct uart_port *port)
1279 {
1280 struct uart_amba_port *uap =
1281 container_of(port, struct uart_amba_port, port);
1282
1283 if (!pl011_dma_tx_start(uap))
1284 pl011_start_tx_pio(uap);
1285 }
1286
1287 static void pl011_stop_rx(struct uart_port *port)
1288 {
1289 struct uart_amba_port *uap =
1290 container_of(port, struct uart_amba_port, port);
1291
1292 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1293 UART011_PEIM|UART011_BEIM|UART011_OEIM);
1294 pl011_write(uap->im, uap, REG_IMSC);
1295
1296 pl011_dma_rx_stop(uap);
1297 }
1298
1299 static void pl011_enable_ms(struct uart_port *port)
1300 {
1301 struct uart_amba_port *uap =
1302 container_of(port, struct uart_amba_port, port);
1303
1304 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1305 pl011_write(uap->im, uap, REG_IMSC);
1306 }
1307
1308 static void pl011_rx_chars(struct uart_amba_port *uap)
1309 __releases(&uap->port.lock)
1310 __acquires(&uap->port.lock)
1311 {
1312 pl011_fifo_to_tty(uap);
1313
1314 spin_unlock(&uap->port.lock);
1315 tty_flip_buffer_push(&uap->port.state->port);
1316 /*
1317 * If we were temporarily out of DMA mode for a while,
1318 * attempt to switch back to DMA mode again.
1319 */
1320 if (pl011_dma_rx_available(uap)) {
1321 if (pl011_dma_rx_trigger_dma(uap)) {
1322 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1323 "fall back to interrupt mode again\n");
1324 uap->im |= UART011_RXIM;
1325 pl011_write(uap->im, uap, REG_IMSC);
1326 } else {
1327 #ifdef CONFIG_DMA_ENGINE
1328 /* Start Rx DMA poll */
1329 if (uap->dmarx.poll_rate) {
1330 uap->dmarx.last_jiffies = jiffies;
1331 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1332 mod_timer(&uap->dmarx.timer,
1333 jiffies +
1334 msecs_to_jiffies(uap->dmarx.poll_rate));
1335 }
1336 #endif
1337 }
1338 }
1339 spin_lock(&uap->port.lock);
1340 }
1341
1342 static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
1343 bool from_irq)
1344 {
1345 if (unlikely(!from_irq) &&
1346 pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1347 return false; /* unable to transmit character */
1348
1349 pl011_write(c, uap, REG_DR);
1350 uap->port.icount.tx++;
1351
1352 return true;
1353 }
1354
1355 static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)
1356 {
1357 struct circ_buf *xmit = &uap->port.state->xmit;
1358 int count = uap->fifosize >> 1;
1359
1360 if (uap->port.x_char) {
1361 if (!pl011_tx_char(uap, uap->port.x_char, from_irq))
1362 return;
1363 uap->port.x_char = 0;
1364 --count;
1365 }
1366 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1367 pl011_stop_tx(&uap->port);
1368 return;
1369 }
1370
1371 /* If we are using DMA mode, try to send some characters. */
1372 if (pl011_dma_tx_irq(uap))
1373 return;
1374
1375 do {
1376 if (likely(from_irq) && count-- == 0)
1377 break;
1378
1379 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq))
1380 break;
1381
1382 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1383 } while (!uart_circ_empty(xmit));
1384
1385 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1386 uart_write_wakeup(&uap->port);
1387
1388 if (uart_circ_empty(xmit))
1389 pl011_stop_tx(&uap->port);
1390 }
1391
1392 static void pl011_modem_status(struct uart_amba_port *uap)
1393 {
1394 unsigned int status, delta;
1395
1396 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1397
1398 delta = status ^ uap->old_status;
1399 uap->old_status = status;
1400
1401 if (!delta)
1402 return;
1403
1404 if (delta & UART01x_FR_DCD)
1405 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1406
1407 if (delta & UART01x_FR_DSR)
1408 uap->port.icount.dsr++;
1409
1410 if (delta & UART01x_FR_CTS)
1411 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
1412
1413 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1414 }
1415
1416 static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
1417 {
1418 unsigned int dummy_read;
1419
1420 if (!uap->vendor->cts_event_workaround)
1421 return;
1422
1423 /* workaround to make sure that all bits are unlocked.. */
1424 pl011_write(0x00, uap, REG_ICR);
1425
1426 /*
1427 * WA: introduce 26ns(1 uart clk) delay before W1C;
1428 * single apb access will incur 2 pclk(133.12Mhz) delay,
1429 * so add 2 dummy reads
1430 */
1431 dummy_read = pl011_read(uap, REG_ICR);
1432 dummy_read = pl011_read(uap, REG_ICR);
1433 }
1434
1435 static irqreturn_t pl011_int(int irq, void *dev_id)
1436 {
1437 struct uart_amba_port *uap = dev_id;
1438 unsigned long flags;
1439 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1440 u16 imsc;
1441 int handled = 0;
1442
1443 spin_lock_irqsave(&uap->port.lock, flags);
1444 imsc = pl011_read(uap, REG_IMSC);
1445 status = pl011_read(uap, REG_RIS) & imsc;
1446 if (status) {
1447 do {
1448 check_apply_cts_event_workaround(uap);
1449
1450 pl011_write(status & ~(UART011_TXIS|UART011_RTIS|
1451 UART011_RXIS),
1452 uap, REG_ICR);
1453
1454 if (status & (UART011_RTIS|UART011_RXIS)) {
1455 if (pl011_dma_rx_running(uap))
1456 pl011_dma_rx_irq(uap);
1457 else
1458 pl011_rx_chars(uap);
1459 }
1460 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1461 UART011_CTSMIS|UART011_RIMIS))
1462 pl011_modem_status(uap);
1463 if (status & UART011_TXIS)
1464 pl011_tx_chars(uap, true);
1465
1466 if (pass_counter-- == 0)
1467 break;
1468
1469 status = pl011_read(uap, REG_RIS) & imsc;
1470 } while (status != 0);
1471 handled = 1;
1472 }
1473
1474 spin_unlock_irqrestore(&uap->port.lock, flags);
1475
1476 return IRQ_RETVAL(handled);
1477 }
1478
1479 static unsigned int pl011_tx_empty(struct uart_port *port)
1480 {
1481 struct uart_amba_port *uap =
1482 container_of(port, struct uart_amba_port, port);
1483 unsigned int status = pl011_read(uap, REG_FR);
1484 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
1485 }
1486
1487 static unsigned int pl011_get_mctrl(struct uart_port *port)
1488 {
1489 struct uart_amba_port *uap =
1490 container_of(port, struct uart_amba_port, port);
1491 unsigned int result = 0;
1492 unsigned int status = pl011_read(uap, REG_FR);
1493
1494 #define TIOCMBIT(uartbit, tiocmbit) \
1495 if (status & uartbit) \
1496 result |= tiocmbit
1497
1498 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1499 TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR);
1500 TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS);
1501 TIOCMBIT(UART011_FR_RI, TIOCM_RNG);
1502 #undef TIOCMBIT
1503 return result;
1504 }
1505
1506 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1507 {
1508 struct uart_amba_port *uap =
1509 container_of(port, struct uart_amba_port, port);
1510 unsigned int cr;
1511
1512 cr = pl011_read(uap, REG_CR);
1513
1514 #define TIOCMBIT(tiocmbit, uartbit) \
1515 if (mctrl & tiocmbit) \
1516 cr |= uartbit; \
1517 else \
1518 cr &= ~uartbit
1519
1520 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1521 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1522 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1523 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1524 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
1525
1526 if (uap->autorts) {
1527 /* We need to disable auto-RTS if we want to turn RTS off */
1528 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1529 }
1530 #undef TIOCMBIT
1531
1532 pl011_write(cr, uap, REG_CR);
1533 }
1534
1535 static void pl011_break_ctl(struct uart_port *port, int break_state)
1536 {
1537 struct uart_amba_port *uap =
1538 container_of(port, struct uart_amba_port, port);
1539 unsigned long flags;
1540 unsigned int lcr_h;
1541
1542 spin_lock_irqsave(&uap->port.lock, flags);
1543 lcr_h = pl011_read(uap, uap->lcrh_tx);
1544 if (break_state == -1)
1545 lcr_h |= UART01x_LCRH_BRK;
1546 else
1547 lcr_h &= ~UART01x_LCRH_BRK;
1548 pl011_write(lcr_h, uap, uap->lcrh_tx);
1549 spin_unlock_irqrestore(&uap->port.lock, flags);
1550 }
1551
1552 #ifdef CONFIG_CONSOLE_POLL
1553
1554 static void pl011_quiesce_irqs(struct uart_port *port)
1555 {
1556 struct uart_amba_port *uap =
1557 container_of(port, struct uart_amba_port, port);
1558
1559 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);
1560 /*
1561 * There is no way to clear TXIM as this is "ready to transmit IRQ", so
1562 * we simply mask it. start_tx() will unmask it.
1563 *
1564 * Note we can race with start_tx(), and if the race happens, the
1565 * polling user might get another interrupt just after we clear it.
1566 * But it should be OK and can happen even w/o the race, e.g.
1567 * controller immediately got some new data and raised the IRQ.
1568 *
1569 * And whoever uses polling routines assumes that it manages the device
1570 * (including tx queue), so we're also fine with start_tx()'s caller
1571 * side.
1572 */
1573 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,
1574 REG_IMSC);
1575 }
1576
1577 static int pl011_get_poll_char(struct uart_port *port)
1578 {
1579 struct uart_amba_port *uap =
1580 container_of(port, struct uart_amba_port, port);
1581 unsigned int status;
1582
1583 /*
1584 * The caller might need IRQs lowered, e.g. if used with KDB NMI
1585 * debugger.
1586 */
1587 pl011_quiesce_irqs(port);
1588
1589 status = pl011_read(uap, REG_FR);
1590 if (status & UART01x_FR_RXFE)
1591 return NO_POLL_CHAR;
1592
1593 return pl011_read(uap, REG_DR);
1594 }
1595
1596 static void pl011_put_poll_char(struct uart_port *port,
1597 unsigned char ch)
1598 {
1599 struct uart_amba_port *uap =
1600 container_of(port, struct uart_amba_port, port);
1601
1602 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1603 barrier();
1604
1605 pl011_write(ch, uap, REG_DR);
1606 }
1607
1608 #endif /* CONFIG_CONSOLE_POLL */
1609
1610 static int pl011_hwinit(struct uart_port *port)
1611 {
1612 struct uart_amba_port *uap =
1613 container_of(port, struct uart_amba_port, port);
1614 int retval;
1615
1616 /* Optionaly enable pins to be muxed in and configured */
1617 pinctrl_pm_select_default_state(port->dev);
1618
1619 /*
1620 * Try to enable the clock producer.
1621 */
1622 retval = clk_prepare_enable(uap->clk);
1623 if (retval)
1624 return retval;
1625
1626 uap->port.uartclk = clk_get_rate(uap->clk);
1627
1628 /* Clear pending error and receive interrupts */
1629 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
1630 UART011_FEIS | UART011_RTIS | UART011_RXIS,
1631 uap, REG_ICR);
1632
1633 /*
1634 * Save interrupts enable mask, and enable RX interrupts in case if
1635 * the interrupt is used for NMI entry.
1636 */
1637 uap->im = pl011_read(uap, REG_IMSC);
1638 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC);
1639
1640 if (dev_get_platdata(uap->port.dev)) {
1641 struct amba_pl011_data *plat;
1642
1643 plat = dev_get_platdata(uap->port.dev);
1644 if (plat->init)
1645 plat->init();
1646 }
1647 return 0;
1648 }
1649
1650 static bool pl011_split_lcrh(const struct uart_amba_port *uap)
1651 {
1652 return pl011_reg_to_offset(uap, uap->lcrh_rx) !=
1653 pl011_reg_to_offset(uap, uap->lcrh_tx);
1654 }
1655
1656 static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
1657 {
1658 pl011_write(lcr_h, uap, uap->lcrh_rx);
1659 if (pl011_split_lcrh(uap)) {
1660 int i;
1661 /*
1662 * Wait 10 PCLKs before writing LCRH_TX register,
1663 * to get this delay write read only register 10 times
1664 */
1665 for (i = 0; i < 10; ++i)
1666 pl011_write(0xff, uap, REG_MIS);
1667 pl011_write(lcr_h, uap, uap->lcrh_tx);
1668 }
1669 }
1670
1671 static int pl011_allocate_irq(struct uart_amba_port *uap)
1672 {
1673 pl011_write(uap->im, uap, REG_IMSC);
1674
1675 return request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
1676 }
1677
1678 /*
1679 * Enable interrupts, only timeouts when using DMA
1680 * if initial RX DMA job failed, start in interrupt mode
1681 * as well.
1682 */
1683 static void pl011_enable_interrupts(struct uart_amba_port *uap)
1684 {
1685 spin_lock_irq(&uap->port.lock);
1686
1687 /* Clear out any spuriously appearing RX interrupts */
1688 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);
1689 uap->im = UART011_RTIM;
1690 if (!pl011_dma_rx_running(uap))
1691 uap->im |= UART011_RXIM;
1692 pl011_write(uap->im, uap, REG_IMSC);
1693 spin_unlock_irq(&uap->port.lock);
1694 }
1695
1696 static int pl011_startup(struct uart_port *port)
1697 {
1698 struct uart_amba_port *uap =
1699 container_of(port, struct uart_amba_port, port);
1700 unsigned int cr;
1701 int retval;
1702
1703 retval = pl011_hwinit(port);
1704 if (retval)
1705 goto clk_dis;
1706
1707 retval = pl011_allocate_irq(uap);
1708 if (retval)
1709 goto clk_dis;
1710
1711 pl011_write(uap->vendor->ifls, uap, REG_IFLS);
1712
1713 spin_lock_irq(&uap->port.lock);
1714
1715 /* restore RTS and DTR */
1716 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
1717 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
1718 pl011_write(cr, uap, REG_CR);
1719
1720 spin_unlock_irq(&uap->port.lock);
1721
1722 /*
1723 * initialise the old status of the modem signals
1724 */
1725 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1726
1727 /* Startup DMA */
1728 pl011_dma_startup(uap);
1729
1730 pl011_enable_interrupts(uap);
1731
1732 return 0;
1733
1734 clk_dis:
1735 clk_disable_unprepare(uap->clk);
1736 return retval;
1737 }
1738
1739 static int sbsa_uart_startup(struct uart_port *port)
1740 {
1741 struct uart_amba_port *uap =
1742 container_of(port, struct uart_amba_port, port);
1743 int retval;
1744
1745 retval = pl011_hwinit(port);
1746 if (retval)
1747 return retval;
1748
1749 retval = pl011_allocate_irq(uap);
1750 if (retval)
1751 return retval;
1752
1753 /* The SBSA UART does not support any modem status lines. */
1754 uap->old_status = 0;
1755
1756 pl011_enable_interrupts(uap);
1757
1758 return 0;
1759 }
1760
1761 static void pl011_shutdown_channel(struct uart_amba_port *uap,
1762 unsigned int lcrh)
1763 {
1764 unsigned long val;
1765
1766 val = pl011_read(uap, lcrh);
1767 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1768 pl011_write(val, uap, lcrh);
1769 }
1770
1771 /*
1772 * disable the port. It should not disable RTS and DTR.
1773 * Also RTS and DTR state should be preserved to restore
1774 * it during startup().
1775 */
1776 static void pl011_disable_uart(struct uart_amba_port *uap)
1777 {
1778 unsigned int cr;
1779
1780 uap->autorts = false;
1781 spin_lock_irq(&uap->port.lock);
1782 cr = pl011_read(uap, REG_CR);
1783 uap->old_cr = cr;
1784 cr &= UART011_CR_RTS | UART011_CR_DTR;
1785 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1786 pl011_write(cr, uap, REG_CR);
1787 spin_unlock_irq(&uap->port.lock);
1788
1789 /*
1790 * disable break condition and fifos
1791 */
1792 pl011_shutdown_channel(uap, uap->lcrh_rx);
1793 if (pl011_split_lcrh(uap))
1794 pl011_shutdown_channel(uap, uap->lcrh_tx);
1795 }
1796
1797 static void pl011_disable_interrupts(struct uart_amba_port *uap)
1798 {
1799 spin_lock_irq(&uap->port.lock);
1800
1801 /* mask all interrupts and clear all pending ones */
1802 uap->im = 0;
1803 pl011_write(uap->im, uap, REG_IMSC);
1804 pl011_write(0xffff, uap, REG_ICR);
1805
1806 spin_unlock_irq(&uap->port.lock);
1807 }
1808
1809 static void pl011_shutdown(struct uart_port *port)
1810 {
1811 struct uart_amba_port *uap =
1812 container_of(port, struct uart_amba_port, port);
1813
1814 pl011_disable_interrupts(uap);
1815
1816 pl011_dma_shutdown(uap);
1817
1818 free_irq(uap->port.irq, uap);
1819
1820 pl011_disable_uart(uap);
1821
1822 /*
1823 * Shut down the clock producer
1824 */
1825 clk_disable_unprepare(uap->clk);
1826 /* Optionally let pins go into sleep states */
1827 pinctrl_pm_select_sleep_state(port->dev);
1828
1829 if (dev_get_platdata(uap->port.dev)) {
1830 struct amba_pl011_data *plat;
1831
1832 plat = dev_get_platdata(uap->port.dev);
1833 if (plat->exit)
1834 plat->exit();
1835 }
1836
1837 if (uap->port.ops->flush_buffer)
1838 uap->port.ops->flush_buffer(port);
1839 }
1840
1841 static void sbsa_uart_shutdown(struct uart_port *port)
1842 {
1843 struct uart_amba_port *uap =
1844 container_of(port, struct uart_amba_port, port);
1845
1846 pl011_disable_interrupts(uap);
1847
1848 free_irq(uap->port.irq, uap);
1849
1850 if (uap->port.ops->flush_buffer)
1851 uap->port.ops->flush_buffer(port);
1852 }
1853
1854 static void
1855 pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios)
1856 {
1857 port->read_status_mask = UART011_DR_OE | 255;
1858 if (termios->c_iflag & INPCK)
1859 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1860 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1861 port->read_status_mask |= UART011_DR_BE;
1862
1863 /*
1864 * Characters to ignore
1865 */
1866 port->ignore_status_mask = 0;
1867 if (termios->c_iflag & IGNPAR)
1868 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1869 if (termios->c_iflag & IGNBRK) {
1870 port->ignore_status_mask |= UART011_DR_BE;
1871 /*
1872 * If we're ignoring parity and break indicators,
1873 * ignore overruns too (for real raw support).
1874 */
1875 if (termios->c_iflag & IGNPAR)
1876 port->ignore_status_mask |= UART011_DR_OE;
1877 }
1878
1879 /*
1880 * Ignore all characters if CREAD is not set.
1881 */
1882 if ((termios->c_cflag & CREAD) == 0)
1883 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1884 }
1885
1886 static void
1887 pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1888 struct ktermios *old)
1889 {
1890 struct uart_amba_port *uap =
1891 container_of(port, struct uart_amba_port, port);
1892 unsigned int lcr_h, old_cr;
1893 unsigned long flags;
1894 unsigned int baud, quot, clkdiv;
1895
1896 if (uap->vendor->oversampling)
1897 clkdiv = 8;
1898 else
1899 clkdiv = 16;
1900
1901 /*
1902 * Ask the core to calculate the divisor for us.
1903 */
1904 baud = uart_get_baud_rate(port, termios, old, 0,
1905 port->uartclk / clkdiv);
1906 #ifdef CONFIG_DMA_ENGINE
1907 /*
1908 * Adjust RX DMA polling rate with baud rate if not specified.
1909 */
1910 if (uap->dmarx.auto_poll_rate)
1911 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
1912 #endif
1913
1914 if (baud > port->uartclk/16)
1915 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1916 else
1917 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1918
1919 switch (termios->c_cflag & CSIZE) {
1920 case CS5:
1921 lcr_h = UART01x_LCRH_WLEN_5;
1922 break;
1923 case CS6:
1924 lcr_h = UART01x_LCRH_WLEN_6;
1925 break;
1926 case CS7:
1927 lcr_h = UART01x_LCRH_WLEN_7;
1928 break;
1929 default: // CS8
1930 lcr_h = UART01x_LCRH_WLEN_8;
1931 break;
1932 }
1933 if (termios->c_cflag & CSTOPB)
1934 lcr_h |= UART01x_LCRH_STP2;
1935 if (termios->c_cflag & PARENB) {
1936 lcr_h |= UART01x_LCRH_PEN;
1937 if (!(termios->c_cflag & PARODD))
1938 lcr_h |= UART01x_LCRH_EPS;
1939 }
1940 if (uap->fifosize > 1)
1941 lcr_h |= UART01x_LCRH_FEN;
1942
1943 spin_lock_irqsave(&port->lock, flags);
1944
1945 /*
1946 * Update the per-port timeout.
1947 */
1948 uart_update_timeout(port, termios->c_cflag, baud);
1949
1950 pl011_setup_status_masks(port, termios);
1951
1952 if (UART_ENABLE_MS(port, termios->c_cflag))
1953 pl011_enable_ms(port);
1954
1955 /* first, disable everything */
1956 old_cr = pl011_read(uap, REG_CR);
1957 pl011_write(0, uap, REG_CR);
1958
1959 if (termios->c_cflag & CRTSCTS) {
1960 if (old_cr & UART011_CR_RTS)
1961 old_cr |= UART011_CR_RTSEN;
1962
1963 old_cr |= UART011_CR_CTSEN;
1964 uap->autorts = true;
1965 } else {
1966 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
1967 uap->autorts = false;
1968 }
1969
1970 if (uap->vendor->oversampling) {
1971 if (baud > port->uartclk / 16)
1972 old_cr |= ST_UART011_CR_OVSFACT;
1973 else
1974 old_cr &= ~ST_UART011_CR_OVSFACT;
1975 }
1976
1977 /*
1978 * Workaround for the ST Micro oversampling variants to
1979 * increase the bitrate slightly, by lowering the divisor,
1980 * to avoid delayed sampling of start bit at high speeds,
1981 * else we see data corruption.
1982 */
1983 if (uap->vendor->oversampling) {
1984 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
1985 quot -= 1;
1986 else if ((baud > 3250000) && (quot > 2))
1987 quot -= 2;
1988 }
1989 /* Set baud rate */
1990 pl011_write(quot & 0x3f, uap, REG_FBRD);
1991 pl011_write(quot >> 6, uap, REG_IBRD);
1992
1993 /*
1994 * ----------v----------v----------v----------v-----
1995 * NOTE: lcrh_tx and lcrh_rx MUST BE WRITTEN AFTER
1996 * REG_FBRD & REG_IBRD.
1997 * ----------^----------^----------^----------^-----
1998 */
1999 pl011_write_lcr_h(uap, lcr_h);
2000 pl011_write(old_cr, uap, REG_CR);
2001
2002 spin_unlock_irqrestore(&port->lock, flags);
2003 }
2004
2005 static void
2006 sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios,
2007 struct ktermios *old)
2008 {
2009 struct uart_amba_port *uap =
2010 container_of(port, struct uart_amba_port, port);
2011 unsigned long flags;
2012
2013 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud);
2014
2015 /* The SBSA UART only supports 8n1 without hardware flow control. */
2016 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
2017 termios->c_cflag &= ~(CMSPAR | CRTSCTS);
2018 termios->c_cflag |= CS8 | CLOCAL;
2019
2020 spin_lock_irqsave(&port->lock, flags);
2021 uart_update_timeout(port, CS8, uap->fixed_baud);
2022 pl011_setup_status_masks(port, termios);
2023 spin_unlock_irqrestore(&port->lock, flags);
2024 }
2025
2026 static const char *pl011_type(struct uart_port *port)
2027 {
2028 struct uart_amba_port *uap =
2029 container_of(port, struct uart_amba_port, port);
2030 return uap->port.type == PORT_AMBA ? uap->type : NULL;
2031 }
2032
2033 /*
2034 * Release the memory region(s) being used by 'port'
2035 */
2036 static void pl011_release_port(struct uart_port *port)
2037 {
2038 release_mem_region(port->mapbase, SZ_4K);
2039 }
2040
2041 /*
2042 * Request the memory region(s) being used by 'port'
2043 */
2044 static int pl011_request_port(struct uart_port *port)
2045 {
2046 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
2047 != NULL ? 0 : -EBUSY;
2048 }
2049
2050 /*
2051 * Configure/autoconfigure the port.
2052 */
2053 static void pl011_config_port(struct uart_port *port, int flags)
2054 {
2055 if (flags & UART_CONFIG_TYPE) {
2056 port->type = PORT_AMBA;
2057 pl011_request_port(port);
2058 }
2059 }
2060
2061 /*
2062 * verify the new serial_struct (for TIOCSSERIAL).
2063 */
2064 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
2065 {
2066 int ret = 0;
2067 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
2068 ret = -EINVAL;
2069 if (ser->irq < 0 || ser->irq >= nr_irqs)
2070 ret = -EINVAL;
2071 if (ser->baud_base < 9600)
2072 ret = -EINVAL;
2073 return ret;
2074 }
2075
2076 static struct uart_ops amba_pl011_pops = {
2077 .tx_empty = pl011_tx_empty,
2078 .set_mctrl = pl011_set_mctrl,
2079 .get_mctrl = pl011_get_mctrl,
2080 .stop_tx = pl011_stop_tx,
2081 .start_tx = pl011_start_tx,
2082 .stop_rx = pl011_stop_rx,
2083 .enable_ms = pl011_enable_ms,
2084 .break_ctl = pl011_break_ctl,
2085 .startup = pl011_startup,
2086 .shutdown = pl011_shutdown,
2087 .flush_buffer = pl011_dma_flush_buffer,
2088 .set_termios = pl011_set_termios,
2089 .type = pl011_type,
2090 .release_port = pl011_release_port,
2091 .request_port = pl011_request_port,
2092 .config_port = pl011_config_port,
2093 .verify_port = pl011_verify_port,
2094 #ifdef CONFIG_CONSOLE_POLL
2095 .poll_init = pl011_hwinit,
2096 .poll_get_char = pl011_get_poll_char,
2097 .poll_put_char = pl011_put_poll_char,
2098 #endif
2099 };
2100
2101 static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
2102 {
2103 }
2104
2105 static unsigned int sbsa_uart_get_mctrl(struct uart_port *port)
2106 {
2107 return 0;
2108 }
2109
2110 static const struct uart_ops sbsa_uart_pops = {
2111 .tx_empty = pl011_tx_empty,
2112 .set_mctrl = sbsa_uart_set_mctrl,
2113 .get_mctrl = sbsa_uart_get_mctrl,
2114 .stop_tx = pl011_stop_tx,
2115 .start_tx = pl011_start_tx,
2116 .stop_rx = pl011_stop_rx,
2117 .startup = sbsa_uart_startup,
2118 .shutdown = sbsa_uart_shutdown,
2119 .set_termios = sbsa_uart_set_termios,
2120 .type = pl011_type,
2121 .release_port = pl011_release_port,
2122 .request_port = pl011_request_port,
2123 .config_port = pl011_config_port,
2124 .verify_port = pl011_verify_port,
2125 #ifdef CONFIG_CONSOLE_POLL
2126 .poll_init = pl011_hwinit,
2127 .poll_get_char = pl011_get_poll_char,
2128 .poll_put_char = pl011_put_poll_char,
2129 #endif
2130 };
2131
2132 static struct uart_amba_port *amba_ports[UART_NR];
2133
2134 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
2135
2136 static void pl011_console_putchar(struct uart_port *port, int ch)
2137 {
2138 struct uart_amba_port *uap =
2139 container_of(port, struct uart_amba_port, port);
2140
2141 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2142 barrier();
2143 pl011_write(ch, uap, REG_DR);
2144 }
2145
2146 static void
2147 pl011_console_write(struct console *co, const char *s, unsigned int count)
2148 {
2149 struct uart_amba_port *uap = amba_ports[co->index];
2150 unsigned int status, old_cr = 0, new_cr;
2151 unsigned long flags;
2152 int locked = 1;
2153
2154 clk_enable(uap->clk);
2155
2156 local_irq_save(flags);
2157 if (uap->port.sysrq)
2158 locked = 0;
2159 else if (oops_in_progress)
2160 locked = spin_trylock(&uap->port.lock);
2161 else
2162 spin_lock(&uap->port.lock);
2163
2164 /*
2165 * First save the CR then disable the interrupts
2166 */
2167 if (!uap->vendor->always_enabled) {
2168 old_cr = pl011_read(uap, REG_CR);
2169 new_cr = old_cr & ~UART011_CR_CTSEN;
2170 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
2171 pl011_write(new_cr, uap, REG_CR);
2172 }
2173
2174 uart_console_write(&uap->port, s, count, pl011_console_putchar);
2175
2176 /*
2177 * Finally, wait for transmitter to become empty
2178 * and restore the TCR
2179 */
2180 do {
2181 status = pl011_read(uap, REG_FR);
2182 } while (status & UART01x_FR_BUSY);
2183 if (!uap->vendor->always_enabled)
2184 pl011_write(old_cr, uap, REG_CR);
2185
2186 if (locked)
2187 spin_unlock(&uap->port.lock);
2188 local_irq_restore(flags);
2189
2190 clk_disable(uap->clk);
2191 }
2192
2193 static void __init
2194 pl011_console_get_options(struct uart_amba_port *uap, int *baud,
2195 int *parity, int *bits)
2196 {
2197 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) {
2198 unsigned int lcr_h, ibrd, fbrd;
2199
2200 lcr_h = pl011_read(uap, uap->lcrh_tx);
2201
2202 *parity = 'n';
2203 if (lcr_h & UART01x_LCRH_PEN) {
2204 if (lcr_h & UART01x_LCRH_EPS)
2205 *parity = 'e';
2206 else
2207 *parity = 'o';
2208 }
2209
2210 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
2211 *bits = 7;
2212 else
2213 *bits = 8;
2214
2215 ibrd = pl011_read(uap, REG_IBRD);
2216 fbrd = pl011_read(uap, REG_FBRD);
2217
2218 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
2219
2220 if (uap->vendor->oversampling) {
2221 if (pl011_read(uap, REG_CR)
2222 & ST_UART011_CR_OVSFACT)
2223 *baud *= 2;
2224 }
2225 }
2226 }
2227
2228 static int __init pl011_console_setup(struct console *co, char *options)
2229 {
2230 struct uart_amba_port *uap;
2231 int baud = 38400;
2232 int bits = 8;
2233 int parity = 'n';
2234 int flow = 'n';
2235 int ret;
2236
2237 /*
2238 * Check whether an invalid uart number has been specified, and
2239 * if so, search for the first available port that does have
2240 * console support.
2241 */
2242 if (co->index >= UART_NR)
2243 co->index = 0;
2244 uap = amba_ports[co->index];
2245 if (!uap)
2246 return -ENODEV;
2247
2248 /* Allow pins to be muxed in and configured */
2249 pinctrl_pm_select_default_state(uap->port.dev);
2250
2251 ret = clk_prepare(uap->clk);
2252 if (ret)
2253 return ret;
2254
2255 if (dev_get_platdata(uap->port.dev)) {
2256 struct amba_pl011_data *plat;
2257
2258 plat = dev_get_platdata(uap->port.dev);
2259 if (plat->init)
2260 plat->init();
2261 }
2262
2263 uap->port.uartclk = clk_get_rate(uap->clk);
2264
2265 if (uap->vendor->fixed_options) {
2266 baud = uap->fixed_baud;
2267 } else {
2268 if (options)
2269 uart_parse_options(options,
2270 &baud, &parity, &bits, &flow);
2271 else
2272 pl011_console_get_options(uap, &baud, &parity, &bits);
2273 }
2274
2275 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2276 }
2277
2278 static struct uart_driver amba_reg;
2279 static struct console amba_console = {
2280 .name = "ttyAMA",
2281 .write = pl011_console_write,
2282 .device = uart_console_device,
2283 .setup = pl011_console_setup,
2284 .flags = CON_PRINTBUFFER,
2285 .index = -1,
2286 .data = &amba_reg,
2287 };
2288
2289 #define AMBA_CONSOLE (&amba_console)
2290
2291 static void pl011_putc(struct uart_port *port, int c)
2292 {
2293 while (readl(port->membase + REG_FR) & UART01x_FR_TXFF)
2294 ;
2295 writeb(c, port->membase + REG_DR);
2296 while (readl(port->membase + REG_FR) & UART01x_FR_BUSY)
2297 ;
2298 }
2299
2300 static void pl011_early_write(struct console *con, const char *s, unsigned n)
2301 {
2302 struct earlycon_device *dev = con->data;
2303
2304 uart_console_write(&dev->port, s, n, pl011_putc);
2305 }
2306
2307 static int __init pl011_early_console_setup(struct earlycon_device *device,
2308 const char *opt)
2309 {
2310 if (!device->port.membase)
2311 return -ENODEV;
2312
2313 device->con->write = pl011_early_write;
2314 return 0;
2315 }
2316 EARLYCON_DECLARE(pl011, pl011_early_console_setup);
2317 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
2318
2319 #else
2320 #define AMBA_CONSOLE NULL
2321 #endif
2322
2323 static struct uart_driver amba_reg = {
2324 .owner = THIS_MODULE,
2325 .driver_name = "ttyAMA",
2326 .dev_name = "ttyAMA",
2327 .major = SERIAL_AMBA_MAJOR,
2328 .minor = SERIAL_AMBA_MINOR,
2329 .nr = UART_NR,
2330 .cons = AMBA_CONSOLE,
2331 };
2332
2333 static int pl011_probe_dt_alias(int index, struct device *dev)
2334 {
2335 struct device_node *np;
2336 static bool seen_dev_with_alias = false;
2337 static bool seen_dev_without_alias = false;
2338 int ret = index;
2339
2340 if (!IS_ENABLED(CONFIG_OF))
2341 return ret;
2342
2343 np = dev->of_node;
2344 if (!np)
2345 return ret;
2346
2347 ret = of_alias_get_id(np, "serial");
2348 if (IS_ERR_VALUE(ret)) {
2349 seen_dev_without_alias = true;
2350 ret = index;
2351 } else {
2352 seen_dev_with_alias = true;
2353 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
2354 dev_warn(dev, "requested serial port %d not available.\n", ret);
2355 ret = index;
2356 }
2357 }
2358
2359 if (seen_dev_with_alias && seen_dev_without_alias)
2360 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2361
2362 return ret;
2363 }
2364
2365 /* unregisters the driver also if no more ports are left */
2366 static void pl011_unregister_port(struct uart_amba_port *uap)
2367 {
2368 int i;
2369 bool busy = false;
2370
2371 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2372 if (amba_ports[i] == uap)
2373 amba_ports[i] = NULL;
2374 else if (amba_ports[i])
2375 busy = true;
2376 }
2377 pl011_dma_remove(uap);
2378 if (!busy)
2379 uart_unregister_driver(&amba_reg);
2380 }
2381
2382 static int pl011_find_free_port(void)
2383 {
2384 int i;
2385
2386 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2387 if (amba_ports[i] == NULL)
2388 return i;
2389
2390 return -EBUSY;
2391 }
2392
2393 static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap,
2394 struct resource *mmiobase, int index)
2395 {
2396 void __iomem *base;
2397
2398 base = devm_ioremap_resource(dev, mmiobase);
2399 if (IS_ERR(base))
2400 return PTR_ERR(base);
2401
2402 index = pl011_probe_dt_alias(index, dev);
2403
2404 uap->old_cr = 0;
2405 uap->port.dev = dev;
2406 uap->port.mapbase = mmiobase->start;
2407 uap->port.membase = base;
2408 uap->port.iotype = UPIO_MEM;
2409 uap->port.fifosize = uap->fifosize;
2410 uap->port.flags = UPF_BOOT_AUTOCONF;
2411 uap->port.line = index;
2412
2413 amba_ports[index] = uap;
2414
2415 return 0;
2416 }
2417
2418 static int pl011_register_port(struct uart_amba_port *uap)
2419 {
2420 int ret;
2421
2422 /* Ensure interrupts from this UART are masked and cleared */
2423 pl011_write(0, uap, REG_IMSC);
2424 pl011_write(0xffff, uap, REG_ICR);
2425
2426 if (!amba_reg.state) {
2427 ret = uart_register_driver(&amba_reg);
2428 if (ret < 0) {
2429 dev_err(uap->port.dev,
2430 "Failed to register AMBA-PL011 driver\n");
2431 return ret;
2432 }
2433 }
2434
2435 ret = uart_add_one_port(&amba_reg, &uap->port);
2436 if (ret)
2437 pl011_unregister_port(uap);
2438
2439 return ret;
2440 }
2441
2442 static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2443 {
2444 struct uart_amba_port *uap;
2445 struct vendor_data *vendor = id->data;
2446 int portnr, ret;
2447
2448 portnr = pl011_find_free_port();
2449 if (portnr < 0)
2450 return portnr;
2451
2452 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2453 GFP_KERNEL);
2454 if (!uap)
2455 return -ENOMEM;
2456
2457 uap->clk = devm_clk_get(&dev->dev, NULL);
2458 if (IS_ERR(uap->clk))
2459 return PTR_ERR(uap->clk);
2460
2461 uap->reg_offset = vendor->reg_offset;
2462 uap->vendor = vendor;
2463 uap->lcrh_rx = vendor->lcrh_rx;
2464 uap->lcrh_tx = vendor->lcrh_tx;
2465 uap->fifosize = vendor->get_fifosize(dev);
2466 uap->port.irq = dev->irq[0];
2467 uap->port.ops = &amba_pl011_pops;
2468
2469 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2470
2471 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);
2472 if (ret)
2473 return ret;
2474
2475 amba_set_drvdata(dev, uap);
2476
2477 return pl011_register_port(uap);
2478 }
2479
2480 static int pl011_remove(struct amba_device *dev)
2481 {
2482 struct uart_amba_port *uap = amba_get_drvdata(dev);
2483
2484 uart_remove_one_port(&amba_reg, &uap->port);
2485 pl011_unregister_port(uap);
2486 return 0;
2487 }
2488
2489 #ifdef CONFIG_PM_SLEEP
2490 static int pl011_suspend(struct device *dev)
2491 {
2492 struct uart_amba_port *uap = dev_get_drvdata(dev);
2493
2494 if (!uap)
2495 return -EINVAL;
2496
2497 return uart_suspend_port(&amba_reg, &uap->port);
2498 }
2499
2500 static int pl011_resume(struct device *dev)
2501 {
2502 struct uart_amba_port *uap = dev_get_drvdata(dev);
2503
2504 if (!uap)
2505 return -EINVAL;
2506
2507 return uart_resume_port(&amba_reg, &uap->port);
2508 }
2509 #endif
2510
2511 static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume);
2512
2513 static int sbsa_uart_probe(struct platform_device *pdev)
2514 {
2515 struct uart_amba_port *uap;
2516 struct resource *r;
2517 int portnr, ret;
2518 int baudrate;
2519
2520 /*
2521 * Check the mandatory baud rate parameter in the DT node early
2522 * so that we can easily exit with the error.
2523 */
2524 if (pdev->dev.of_node) {
2525 struct device_node *np = pdev->dev.of_node;
2526
2527 ret = of_property_read_u32(np, "current-speed", &baudrate);
2528 if (ret)
2529 return ret;
2530 } else {
2531 baudrate = 115200;
2532 }
2533
2534 portnr = pl011_find_free_port();
2535 if (portnr < 0)
2536 return portnr;
2537
2538 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),
2539 GFP_KERNEL);
2540 if (!uap)
2541 return -ENOMEM;
2542
2543 uap->reg_offset = vendor_sbsa.reg_offset;
2544 uap->vendor = &vendor_sbsa;
2545 uap->fifosize = 32;
2546 uap->port.irq = platform_get_irq(pdev, 0);
2547 uap->port.ops = &sbsa_uart_pops;
2548 uap->fixed_baud = baudrate;
2549
2550 snprintf(uap->type, sizeof(uap->type), "SBSA");
2551
2552 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2553
2554 ret = pl011_setup_port(&pdev->dev, uap, r, portnr);
2555 if (ret)
2556 return ret;
2557
2558 platform_set_drvdata(pdev, uap);
2559
2560 return pl011_register_port(uap);
2561 }
2562
2563 static int sbsa_uart_remove(struct platform_device *pdev)
2564 {
2565 struct uart_amba_port *uap = platform_get_drvdata(pdev);
2566
2567 uart_remove_one_port(&amba_reg, &uap->port);
2568 pl011_unregister_port(uap);
2569 return 0;
2570 }
2571
2572 static const struct of_device_id sbsa_uart_of_match[] = {
2573 { .compatible = "arm,sbsa-uart", },
2574 {},
2575 };
2576 MODULE_DEVICE_TABLE(of, sbsa_uart_of_match);
2577
2578 static const struct acpi_device_id sbsa_uart_acpi_match[] = {
2579 { "ARMH0011", 0 },
2580 {},
2581 };
2582 MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match);
2583
2584 static struct platform_driver arm_sbsa_uart_platform_driver = {
2585 .probe = sbsa_uart_probe,
2586 .remove = sbsa_uart_remove,
2587 .driver = {
2588 .name = "sbsa-uart",
2589 .of_match_table = of_match_ptr(sbsa_uart_of_match),
2590 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match),
2591 },
2592 };
2593
2594 static struct amba_id pl011_ids[] = {
2595 {
2596 .id = 0x00041011,
2597 .mask = 0x000fffff,
2598 .data = &vendor_arm,
2599 },
2600 {
2601 .id = 0x00380802,
2602 .mask = 0x00ffffff,
2603 .data = &vendor_st,
2604 },
2605 { 0, 0 },
2606 };
2607
2608 MODULE_DEVICE_TABLE(amba, pl011_ids);
2609
2610 static struct amba_driver pl011_driver = {
2611 .drv = {
2612 .name = "uart-pl011",
2613 .pm = &pl011_dev_pm_ops,
2614 },
2615 .id_table = pl011_ids,
2616 .probe = pl011_probe,
2617 .remove = pl011_remove,
2618 };
2619
2620 static int __init pl011_init(void)
2621 {
2622 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2623
2624 if (platform_driver_register(&arm_sbsa_uart_platform_driver))
2625 pr_warn("could not register SBSA UART platform driver\n");
2626 return amba_driver_register(&pl011_driver);
2627 }
2628
2629 static void __exit pl011_exit(void)
2630 {
2631 platform_driver_unregister(&arm_sbsa_uart_platform_driver);
2632 amba_driver_unregister(&pl011_driver);
2633 }
2634
2635 /*
2636 * While this can be a module, if builtin it's most likely the console
2637 * So let's leave module_exit but move module_init to an earlier place
2638 */
2639 arch_initcall(pl011_init);
2640 module_exit(pl011_exit);
2641
2642 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2643 MODULE_DESCRIPTION("ARM AMBA serial port driver");
2644 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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