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serial/amba-pl011: Refactor and simplify TX FIFO handling
[deliverable/linux.git] / drivers / tty / serial / amba-pl011.c
1 /*
2 * Driver for AMBA serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 * Copyright (C) 2010 ST-Ericsson SA
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * This is a generic driver for ARM AMBA-type serial ports. They
25 * have a lot of 16550-like features, but are not register compatible.
26 * Note that although they do have CTS, DCD and DSR inputs, they do
27 * not have an RI input, nor do they have DTR or RTS outputs. If
28 * required, these have to be supplied via some other means (eg, GPIO)
29 * and hooked into this driver.
30 */
31
32
33 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
34 #define SUPPORT_SYSRQ
35 #endif
36
37 #include <linux/module.h>
38 #include <linux/ioport.h>
39 #include <linux/init.h>
40 #include <linux/console.h>
41 #include <linux/sysrq.h>
42 #include <linux/device.h>
43 #include <linux/tty.h>
44 #include <linux/tty_flip.h>
45 #include <linux/serial_core.h>
46 #include <linux/serial.h>
47 #include <linux/amba/bus.h>
48 #include <linux/amba/serial.h>
49 #include <linux/clk.h>
50 #include <linux/slab.h>
51 #include <linux/dmaengine.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/scatterlist.h>
54 #include <linux/delay.h>
55 #include <linux/types.h>
56 #include <linux/of.h>
57 #include <linux/of_device.h>
58 #include <linux/pinctrl/consumer.h>
59 #include <linux/sizes.h>
60 #include <linux/io.h>
61
62 #define UART_NR 14
63
64 #define SERIAL_AMBA_MAJOR 204
65 #define SERIAL_AMBA_MINOR 64
66 #define SERIAL_AMBA_NR UART_NR
67
68 #define AMBA_ISR_PASS_LIMIT 256
69
70 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
71 #define UART_DUMMY_DR_RX (1 << 16)
72
73 /* There is by now at least one vendor with differing details, so handle it */
74 struct vendor_data {
75 unsigned int ifls;
76 unsigned int lcrh_tx;
77 unsigned int lcrh_rx;
78 bool oversampling;
79 bool dma_threshold;
80 bool cts_event_workaround;
81
82 unsigned int (*get_fifosize)(struct amba_device *dev);
83 };
84
85 static unsigned int get_fifosize_arm(struct amba_device *dev)
86 {
87 return amba_rev(dev) < 3 ? 16 : 32;
88 }
89
90 static struct vendor_data vendor_arm = {
91 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
92 .lcrh_tx = UART011_LCRH,
93 .lcrh_rx = UART011_LCRH,
94 .oversampling = false,
95 .dma_threshold = false,
96 .cts_event_workaround = false,
97 .get_fifosize = get_fifosize_arm,
98 };
99
100 static unsigned int get_fifosize_st(struct amba_device *dev)
101 {
102 return 64;
103 }
104
105 static struct vendor_data vendor_st = {
106 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
107 .lcrh_tx = ST_UART011_LCRH_TX,
108 .lcrh_rx = ST_UART011_LCRH_RX,
109 .oversampling = true,
110 .dma_threshold = true,
111 .cts_event_workaround = true,
112 .get_fifosize = get_fifosize_st,
113 };
114
115 /* Deals with DMA transactions */
116
117 struct pl011_sgbuf {
118 struct scatterlist sg;
119 char *buf;
120 };
121
122 struct pl011_dmarx_data {
123 struct dma_chan *chan;
124 struct completion complete;
125 bool use_buf_b;
126 struct pl011_sgbuf sgbuf_a;
127 struct pl011_sgbuf sgbuf_b;
128 dma_cookie_t cookie;
129 bool running;
130 struct timer_list timer;
131 unsigned int last_residue;
132 unsigned long last_jiffies;
133 bool auto_poll_rate;
134 unsigned int poll_rate;
135 unsigned int poll_timeout;
136 };
137
138 struct pl011_dmatx_data {
139 struct dma_chan *chan;
140 struct scatterlist sg;
141 char *buf;
142 bool queued;
143 };
144
145 /*
146 * We wrap our port structure around the generic uart_port.
147 */
148 struct uart_amba_port {
149 struct uart_port port;
150 struct clk *clk;
151 const struct vendor_data *vendor;
152 unsigned int dmacr; /* dma control reg */
153 unsigned int im; /* interrupt mask */
154 unsigned int old_status;
155 unsigned int fifosize; /* vendor-specific */
156 unsigned int lcrh_tx; /* vendor-specific */
157 unsigned int lcrh_rx; /* vendor-specific */
158 unsigned int old_cr; /* state during shutdown */
159 bool autorts;
160 char type[12];
161 #ifdef CONFIG_DMA_ENGINE
162 /* DMA stuff */
163 bool using_tx_dma;
164 bool using_rx_dma;
165 struct pl011_dmarx_data dmarx;
166 struct pl011_dmatx_data dmatx;
167 bool dma_probed;
168 #endif
169 };
170
171 /*
172 * Reads up to 256 characters from the FIFO or until it's empty and
173 * inserts them into the TTY layer. Returns the number of characters
174 * read from the FIFO.
175 */
176 static int pl011_fifo_to_tty(struct uart_amba_port *uap)
177 {
178 u16 status, ch;
179 unsigned int flag, max_count = 256;
180 int fifotaken = 0;
181
182 while (max_count--) {
183 status = readw(uap->port.membase + UART01x_FR);
184 if (status & UART01x_FR_RXFE)
185 break;
186
187 /* Take chars from the FIFO and update status */
188 ch = readw(uap->port.membase + UART01x_DR) |
189 UART_DUMMY_DR_RX;
190 flag = TTY_NORMAL;
191 uap->port.icount.rx++;
192 fifotaken++;
193
194 if (unlikely(ch & UART_DR_ERROR)) {
195 if (ch & UART011_DR_BE) {
196 ch &= ~(UART011_DR_FE | UART011_DR_PE);
197 uap->port.icount.brk++;
198 if (uart_handle_break(&uap->port))
199 continue;
200 } else if (ch & UART011_DR_PE)
201 uap->port.icount.parity++;
202 else if (ch & UART011_DR_FE)
203 uap->port.icount.frame++;
204 if (ch & UART011_DR_OE)
205 uap->port.icount.overrun++;
206
207 ch &= uap->port.read_status_mask;
208
209 if (ch & UART011_DR_BE)
210 flag = TTY_BREAK;
211 else if (ch & UART011_DR_PE)
212 flag = TTY_PARITY;
213 else if (ch & UART011_DR_FE)
214 flag = TTY_FRAME;
215 }
216
217 if (uart_handle_sysrq_char(&uap->port, ch & 255))
218 continue;
219
220 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
221 }
222
223 return fifotaken;
224 }
225
226
227 /*
228 * All the DMA operation mode stuff goes inside this ifdef.
229 * This assumes that you have a generic DMA device interface,
230 * no custom DMA interfaces are supported.
231 */
232 #ifdef CONFIG_DMA_ENGINE
233
234 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE
235
236 static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
237 enum dma_data_direction dir)
238 {
239 dma_addr_t dma_addr;
240
241 sg->buf = dma_alloc_coherent(chan->device->dev,
242 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
243 if (!sg->buf)
244 return -ENOMEM;
245
246 sg_init_table(&sg->sg, 1);
247 sg_set_page(&sg->sg, phys_to_page(dma_addr),
248 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
249 sg_dma_address(&sg->sg) = dma_addr;
250 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE;
251
252 return 0;
253 }
254
255 static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
256 enum dma_data_direction dir)
257 {
258 if (sg->buf) {
259 dma_free_coherent(chan->device->dev,
260 PL011_DMA_BUFFER_SIZE, sg->buf,
261 sg_dma_address(&sg->sg));
262 }
263 }
264
265 static void pl011_dma_probe(struct uart_amba_port *uap)
266 {
267 /* DMA is the sole user of the platform data right now */
268 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
269 struct device *dev = uap->port.dev;
270 struct dma_slave_config tx_conf = {
271 .dst_addr = uap->port.mapbase + UART01x_DR,
272 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
273 .direction = DMA_MEM_TO_DEV,
274 .dst_maxburst = uap->fifosize >> 1,
275 .device_fc = false,
276 };
277 struct dma_chan *chan;
278 dma_cap_mask_t mask;
279
280 uap->dma_probed = true;
281 chan = dma_request_slave_channel_reason(dev, "tx");
282 if (IS_ERR(chan)) {
283 if (PTR_ERR(chan) == -EPROBE_DEFER) {
284 uap->dma_probed = false;
285 return;
286 }
287
288 /* We need platform data */
289 if (!plat || !plat->dma_filter) {
290 dev_info(uap->port.dev, "no DMA platform data\n");
291 return;
292 }
293
294 /* Try to acquire a generic DMA engine slave TX channel */
295 dma_cap_zero(mask);
296 dma_cap_set(DMA_SLAVE, mask);
297
298 chan = dma_request_channel(mask, plat->dma_filter,
299 plat->dma_tx_param);
300 if (!chan) {
301 dev_err(uap->port.dev, "no TX DMA channel!\n");
302 return;
303 }
304 }
305
306 dmaengine_slave_config(chan, &tx_conf);
307 uap->dmatx.chan = chan;
308
309 dev_info(uap->port.dev, "DMA channel TX %s\n",
310 dma_chan_name(uap->dmatx.chan));
311
312 /* Optionally make use of an RX channel as well */
313 chan = dma_request_slave_channel(dev, "rx");
314
315 if (!chan && plat->dma_rx_param) {
316 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
317
318 if (!chan) {
319 dev_err(uap->port.dev, "no RX DMA channel!\n");
320 return;
321 }
322 }
323
324 if (chan) {
325 struct dma_slave_config rx_conf = {
326 .src_addr = uap->port.mapbase + UART01x_DR,
327 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
328 .direction = DMA_DEV_TO_MEM,
329 .src_maxburst = uap->fifosize >> 2,
330 .device_fc = false,
331 };
332 struct dma_slave_caps caps;
333
334 /*
335 * Some DMA controllers provide information on their capabilities.
336 * If the controller does, check for suitable residue processing
337 * otherwise assime all is well.
338 */
339 if (0 == dma_get_slave_caps(chan, &caps)) {
340 if (caps.residue_granularity ==
341 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
342 dma_release_channel(chan);
343 dev_info(uap->port.dev,
344 "RX DMA disabled - no residue processing\n");
345 return;
346 }
347 }
348 dmaengine_slave_config(chan, &rx_conf);
349 uap->dmarx.chan = chan;
350
351 uap->dmarx.auto_poll_rate = false;
352 if (plat && plat->dma_rx_poll_enable) {
353 /* Set poll rate if specified. */
354 if (plat->dma_rx_poll_rate) {
355 uap->dmarx.auto_poll_rate = false;
356 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
357 } else {
358 /*
359 * 100 ms defaults to poll rate if not
360 * specified. This will be adjusted with
361 * the baud rate at set_termios.
362 */
363 uap->dmarx.auto_poll_rate = true;
364 uap->dmarx.poll_rate = 100;
365 }
366 /* 3 secs defaults poll_timeout if not specified. */
367 if (plat->dma_rx_poll_timeout)
368 uap->dmarx.poll_timeout =
369 plat->dma_rx_poll_timeout;
370 else
371 uap->dmarx.poll_timeout = 3000;
372 } else if (!plat && dev->of_node) {
373 uap->dmarx.auto_poll_rate = of_property_read_bool(
374 dev->of_node, "auto-poll");
375 if (uap->dmarx.auto_poll_rate) {
376 u32 x;
377
378 if (0 == of_property_read_u32(dev->of_node,
379 "poll-rate-ms", &x))
380 uap->dmarx.poll_rate = x;
381 else
382 uap->dmarx.poll_rate = 100;
383 if (0 == of_property_read_u32(dev->of_node,
384 "poll-timeout-ms", &x))
385 uap->dmarx.poll_timeout = x;
386 else
387 uap->dmarx.poll_timeout = 3000;
388 }
389 }
390 dev_info(uap->port.dev, "DMA channel RX %s\n",
391 dma_chan_name(uap->dmarx.chan));
392 }
393 }
394
395 static void pl011_dma_remove(struct uart_amba_port *uap)
396 {
397 if (uap->dmatx.chan)
398 dma_release_channel(uap->dmatx.chan);
399 if (uap->dmarx.chan)
400 dma_release_channel(uap->dmarx.chan);
401 }
402
403 /* Forward declare these for the refill routine */
404 static int pl011_dma_tx_refill(struct uart_amba_port *uap);
405 static void pl011_start_tx_pio(struct uart_amba_port *uap);
406
407 /*
408 * The current DMA TX buffer has been sent.
409 * Try to queue up another DMA buffer.
410 */
411 static void pl011_dma_tx_callback(void *data)
412 {
413 struct uart_amba_port *uap = data;
414 struct pl011_dmatx_data *dmatx = &uap->dmatx;
415 unsigned long flags;
416 u16 dmacr;
417
418 spin_lock_irqsave(&uap->port.lock, flags);
419 if (uap->dmatx.queued)
420 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
421 DMA_TO_DEVICE);
422
423 dmacr = uap->dmacr;
424 uap->dmacr = dmacr & ~UART011_TXDMAE;
425 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
426
427 /*
428 * If TX DMA was disabled, it means that we've stopped the DMA for
429 * some reason (eg, XOFF received, or we want to send an X-char.)
430 *
431 * Note: we need to be careful here of a potential race between DMA
432 * and the rest of the driver - if the driver disables TX DMA while
433 * a TX buffer completing, we must update the tx queued status to
434 * get further refills (hence we check dmacr).
435 */
436 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
437 uart_circ_empty(&uap->port.state->xmit)) {
438 uap->dmatx.queued = false;
439 spin_unlock_irqrestore(&uap->port.lock, flags);
440 return;
441 }
442
443 if (pl011_dma_tx_refill(uap) <= 0)
444 /*
445 * We didn't queue a DMA buffer for some reason, but we
446 * have data pending to be sent. Re-enable the TX IRQ.
447 */
448 pl011_start_tx_pio(uap);
449
450 spin_unlock_irqrestore(&uap->port.lock, flags);
451 }
452
453 /*
454 * Try to refill the TX DMA buffer.
455 * Locking: called with port lock held and IRQs disabled.
456 * Returns:
457 * 1 if we queued up a TX DMA buffer.
458 * 0 if we didn't want to handle this by DMA
459 * <0 on error
460 */
461 static int pl011_dma_tx_refill(struct uart_amba_port *uap)
462 {
463 struct pl011_dmatx_data *dmatx = &uap->dmatx;
464 struct dma_chan *chan = dmatx->chan;
465 struct dma_device *dma_dev = chan->device;
466 struct dma_async_tx_descriptor *desc;
467 struct circ_buf *xmit = &uap->port.state->xmit;
468 unsigned int count;
469
470 /*
471 * Try to avoid the overhead involved in using DMA if the
472 * transaction fits in the first half of the FIFO, by using
473 * the standard interrupt handling. This ensures that we
474 * issue a uart_write_wakeup() at the appropriate time.
475 */
476 count = uart_circ_chars_pending(xmit);
477 if (count < (uap->fifosize >> 1)) {
478 uap->dmatx.queued = false;
479 return 0;
480 }
481
482 /*
483 * Bodge: don't send the last character by DMA, as this
484 * will prevent XON from notifying us to restart DMA.
485 */
486 count -= 1;
487
488 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
489 if (count > PL011_DMA_BUFFER_SIZE)
490 count = PL011_DMA_BUFFER_SIZE;
491
492 if (xmit->tail < xmit->head)
493 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
494 else {
495 size_t first = UART_XMIT_SIZE - xmit->tail;
496 size_t second;
497
498 if (first > count)
499 first = count;
500 second = count - first;
501
502 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
503 if (second)
504 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
505 }
506
507 dmatx->sg.length = count;
508
509 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
510 uap->dmatx.queued = false;
511 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
512 return -EBUSY;
513 }
514
515 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
516 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
517 if (!desc) {
518 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
519 uap->dmatx.queued = false;
520 /*
521 * If DMA cannot be used right now, we complete this
522 * transaction via IRQ and let the TTY layer retry.
523 */
524 dev_dbg(uap->port.dev, "TX DMA busy\n");
525 return -EBUSY;
526 }
527
528 /* Some data to go along to the callback */
529 desc->callback = pl011_dma_tx_callback;
530 desc->callback_param = uap;
531
532 /* All errors should happen at prepare time */
533 dmaengine_submit(desc);
534
535 /* Fire the DMA transaction */
536 dma_dev->device_issue_pending(chan);
537
538 uap->dmacr |= UART011_TXDMAE;
539 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
540 uap->dmatx.queued = true;
541
542 /*
543 * Now we know that DMA will fire, so advance the ring buffer
544 * with the stuff we just dispatched.
545 */
546 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
547 uap->port.icount.tx += count;
548
549 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
550 uart_write_wakeup(&uap->port);
551
552 return 1;
553 }
554
555 /*
556 * We received a transmit interrupt without a pending X-char but with
557 * pending characters.
558 * Locking: called with port lock held and IRQs disabled.
559 * Returns:
560 * false if we want to use PIO to transmit
561 * true if we queued a DMA buffer
562 */
563 static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
564 {
565 if (!uap->using_tx_dma)
566 return false;
567
568 /*
569 * If we already have a TX buffer queued, but received a
570 * TX interrupt, it will be because we've just sent an X-char.
571 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
572 */
573 if (uap->dmatx.queued) {
574 uap->dmacr |= UART011_TXDMAE;
575 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
576 uap->im &= ~UART011_TXIM;
577 writew(uap->im, uap->port.membase + UART011_IMSC);
578 return true;
579 }
580
581 /*
582 * We don't have a TX buffer queued, so try to queue one.
583 * If we successfully queued a buffer, mask the TX IRQ.
584 */
585 if (pl011_dma_tx_refill(uap) > 0) {
586 uap->im &= ~UART011_TXIM;
587 writew(uap->im, uap->port.membase + UART011_IMSC);
588 return true;
589 }
590 return false;
591 }
592
593 /*
594 * Stop the DMA transmit (eg, due to received XOFF).
595 * Locking: called with port lock held and IRQs disabled.
596 */
597 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
598 {
599 if (uap->dmatx.queued) {
600 uap->dmacr &= ~UART011_TXDMAE;
601 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
602 }
603 }
604
605 /*
606 * Try to start a DMA transmit, or in the case of an XON/OFF
607 * character queued for send, try to get that character out ASAP.
608 * Locking: called with port lock held and IRQs disabled.
609 * Returns:
610 * false if we want the TX IRQ to be enabled
611 * true if we have a buffer queued
612 */
613 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
614 {
615 u16 dmacr;
616
617 if (!uap->using_tx_dma)
618 return false;
619
620 if (!uap->port.x_char) {
621 /* no X-char, try to push chars out in DMA mode */
622 bool ret = true;
623
624 if (!uap->dmatx.queued) {
625 if (pl011_dma_tx_refill(uap) > 0) {
626 uap->im &= ~UART011_TXIM;
627 writew(uap->im, uap->port.membase +
628 UART011_IMSC);
629 } else
630 ret = false;
631 } else if (!(uap->dmacr & UART011_TXDMAE)) {
632 uap->dmacr |= UART011_TXDMAE;
633 writew(uap->dmacr,
634 uap->port.membase + UART011_DMACR);
635 }
636 return ret;
637 }
638
639 /*
640 * We have an X-char to send. Disable DMA to prevent it loading
641 * the TX fifo, and then see if we can stuff it into the FIFO.
642 */
643 dmacr = uap->dmacr;
644 uap->dmacr &= ~UART011_TXDMAE;
645 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
646
647 if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) {
648 /*
649 * No space in the FIFO, so enable the transmit interrupt
650 * so we know when there is space. Note that once we've
651 * loaded the character, we should just re-enable DMA.
652 */
653 return false;
654 }
655
656 writew(uap->port.x_char, uap->port.membase + UART01x_DR);
657 uap->port.icount.tx++;
658 uap->port.x_char = 0;
659
660 /* Success - restore the DMA state */
661 uap->dmacr = dmacr;
662 writew(dmacr, uap->port.membase + UART011_DMACR);
663
664 return true;
665 }
666
667 /*
668 * Flush the transmit buffer.
669 * Locking: called with port lock held and IRQs disabled.
670 */
671 static void pl011_dma_flush_buffer(struct uart_port *port)
672 __releases(&uap->port.lock)
673 __acquires(&uap->port.lock)
674 {
675 struct uart_amba_port *uap =
676 container_of(port, struct uart_amba_port, port);
677
678 if (!uap->using_tx_dma)
679 return;
680
681 /* Avoid deadlock with the DMA engine callback */
682 spin_unlock(&uap->port.lock);
683 dmaengine_terminate_all(uap->dmatx.chan);
684 spin_lock(&uap->port.lock);
685 if (uap->dmatx.queued) {
686 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
687 DMA_TO_DEVICE);
688 uap->dmatx.queued = false;
689 uap->dmacr &= ~UART011_TXDMAE;
690 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
691 }
692 }
693
694 static void pl011_dma_rx_callback(void *data);
695
696 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
697 {
698 struct dma_chan *rxchan = uap->dmarx.chan;
699 struct pl011_dmarx_data *dmarx = &uap->dmarx;
700 struct dma_async_tx_descriptor *desc;
701 struct pl011_sgbuf *sgbuf;
702
703 if (!rxchan)
704 return -EIO;
705
706 /* Start the RX DMA job */
707 sgbuf = uap->dmarx.use_buf_b ?
708 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
709 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
710 DMA_DEV_TO_MEM,
711 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
712 /*
713 * If the DMA engine is busy and cannot prepare a
714 * channel, no big deal, the driver will fall back
715 * to interrupt mode as a result of this error code.
716 */
717 if (!desc) {
718 uap->dmarx.running = false;
719 dmaengine_terminate_all(rxchan);
720 return -EBUSY;
721 }
722
723 /* Some data to go along to the callback */
724 desc->callback = pl011_dma_rx_callback;
725 desc->callback_param = uap;
726 dmarx->cookie = dmaengine_submit(desc);
727 dma_async_issue_pending(rxchan);
728
729 uap->dmacr |= UART011_RXDMAE;
730 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
731 uap->dmarx.running = true;
732
733 uap->im &= ~UART011_RXIM;
734 writew(uap->im, uap->port.membase + UART011_IMSC);
735
736 return 0;
737 }
738
739 /*
740 * This is called when either the DMA job is complete, or
741 * the FIFO timeout interrupt occurred. This must be called
742 * with the port spinlock uap->port.lock held.
743 */
744 static void pl011_dma_rx_chars(struct uart_amba_port *uap,
745 u32 pending, bool use_buf_b,
746 bool readfifo)
747 {
748 struct tty_port *port = &uap->port.state->port;
749 struct pl011_sgbuf *sgbuf = use_buf_b ?
750 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
751 int dma_count = 0;
752 u32 fifotaken = 0; /* only used for vdbg() */
753
754 struct pl011_dmarx_data *dmarx = &uap->dmarx;
755 int dmataken = 0;
756
757 if (uap->dmarx.poll_rate) {
758 /* The data can be taken by polling */
759 dmataken = sgbuf->sg.length - dmarx->last_residue;
760 /* Recalculate the pending size */
761 if (pending >= dmataken)
762 pending -= dmataken;
763 }
764
765 /* Pick the remain data from the DMA */
766 if (pending) {
767
768 /*
769 * First take all chars in the DMA pipe, then look in the FIFO.
770 * Note that tty_insert_flip_buf() tries to take as many chars
771 * as it can.
772 */
773 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
774 pending);
775
776 uap->port.icount.rx += dma_count;
777 if (dma_count < pending)
778 dev_warn(uap->port.dev,
779 "couldn't insert all characters (TTY is full?)\n");
780 }
781
782 /* Reset the last_residue for Rx DMA poll */
783 if (uap->dmarx.poll_rate)
784 dmarx->last_residue = sgbuf->sg.length;
785
786 /*
787 * Only continue with trying to read the FIFO if all DMA chars have
788 * been taken first.
789 */
790 if (dma_count == pending && readfifo) {
791 /* Clear any error flags */
792 writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
793 uap->port.membase + UART011_ICR);
794
795 /*
796 * If we read all the DMA'd characters, and we had an
797 * incomplete buffer, that could be due to an rx error, or
798 * maybe we just timed out. Read any pending chars and check
799 * the error status.
800 *
801 * Error conditions will only occur in the FIFO, these will
802 * trigger an immediate interrupt and stop the DMA job, so we
803 * will always find the error in the FIFO, never in the DMA
804 * buffer.
805 */
806 fifotaken = pl011_fifo_to_tty(uap);
807 }
808
809 spin_unlock(&uap->port.lock);
810 dev_vdbg(uap->port.dev,
811 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
812 dma_count, fifotaken);
813 tty_flip_buffer_push(port);
814 spin_lock(&uap->port.lock);
815 }
816
817 static void pl011_dma_rx_irq(struct uart_amba_port *uap)
818 {
819 struct pl011_dmarx_data *dmarx = &uap->dmarx;
820 struct dma_chan *rxchan = dmarx->chan;
821 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
822 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
823 size_t pending;
824 struct dma_tx_state state;
825 enum dma_status dmastat;
826
827 /*
828 * Pause the transfer so we can trust the current counter,
829 * do this before we pause the PL011 block, else we may
830 * overflow the FIFO.
831 */
832 if (dmaengine_pause(rxchan))
833 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
834 dmastat = rxchan->device->device_tx_status(rxchan,
835 dmarx->cookie, &state);
836 if (dmastat != DMA_PAUSED)
837 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
838
839 /* Disable RX DMA - incoming data will wait in the FIFO */
840 uap->dmacr &= ~UART011_RXDMAE;
841 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
842 uap->dmarx.running = false;
843
844 pending = sgbuf->sg.length - state.residue;
845 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
846 /* Then we terminate the transfer - we now know our residue */
847 dmaengine_terminate_all(rxchan);
848
849 /*
850 * This will take the chars we have so far and insert
851 * into the framework.
852 */
853 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
854
855 /* Switch buffer & re-trigger DMA job */
856 dmarx->use_buf_b = !dmarx->use_buf_b;
857 if (pl011_dma_rx_trigger_dma(uap)) {
858 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
859 "fall back to interrupt mode\n");
860 uap->im |= UART011_RXIM;
861 writew(uap->im, uap->port.membase + UART011_IMSC);
862 }
863 }
864
865 static void pl011_dma_rx_callback(void *data)
866 {
867 struct uart_amba_port *uap = data;
868 struct pl011_dmarx_data *dmarx = &uap->dmarx;
869 struct dma_chan *rxchan = dmarx->chan;
870 bool lastbuf = dmarx->use_buf_b;
871 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
872 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
873 size_t pending;
874 struct dma_tx_state state;
875 int ret;
876
877 /*
878 * This completion interrupt occurs typically when the
879 * RX buffer is totally stuffed but no timeout has yet
880 * occurred. When that happens, we just want the RX
881 * routine to flush out the secondary DMA buffer while
882 * we immediately trigger the next DMA job.
883 */
884 spin_lock_irq(&uap->port.lock);
885 /*
886 * Rx data can be taken by the UART interrupts during
887 * the DMA irq handler. So we check the residue here.
888 */
889 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
890 pending = sgbuf->sg.length - state.residue;
891 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
892 /* Then we terminate the transfer - we now know our residue */
893 dmaengine_terminate_all(rxchan);
894
895 uap->dmarx.running = false;
896 dmarx->use_buf_b = !lastbuf;
897 ret = pl011_dma_rx_trigger_dma(uap);
898
899 pl011_dma_rx_chars(uap, pending, lastbuf, false);
900 spin_unlock_irq(&uap->port.lock);
901 /*
902 * Do this check after we picked the DMA chars so we don't
903 * get some IRQ immediately from RX.
904 */
905 if (ret) {
906 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
907 "fall back to interrupt mode\n");
908 uap->im |= UART011_RXIM;
909 writew(uap->im, uap->port.membase + UART011_IMSC);
910 }
911 }
912
913 /*
914 * Stop accepting received characters, when we're shutting down or
915 * suspending this port.
916 * Locking: called with port lock held and IRQs disabled.
917 */
918 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
919 {
920 /* FIXME. Just disable the DMA enable */
921 uap->dmacr &= ~UART011_RXDMAE;
922 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
923 }
924
925 /*
926 * Timer handler for Rx DMA polling.
927 * Every polling, It checks the residue in the dma buffer and transfer
928 * data to the tty. Also, last_residue is updated for the next polling.
929 */
930 static void pl011_dma_rx_poll(unsigned long args)
931 {
932 struct uart_amba_port *uap = (struct uart_amba_port *)args;
933 struct tty_port *port = &uap->port.state->port;
934 struct pl011_dmarx_data *dmarx = &uap->dmarx;
935 struct dma_chan *rxchan = uap->dmarx.chan;
936 unsigned long flags = 0;
937 unsigned int dmataken = 0;
938 unsigned int size = 0;
939 struct pl011_sgbuf *sgbuf;
940 int dma_count;
941 struct dma_tx_state state;
942
943 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
944 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
945 if (likely(state.residue < dmarx->last_residue)) {
946 dmataken = sgbuf->sg.length - dmarx->last_residue;
947 size = dmarx->last_residue - state.residue;
948 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
949 size);
950 if (dma_count == size)
951 dmarx->last_residue = state.residue;
952 dmarx->last_jiffies = jiffies;
953 }
954 tty_flip_buffer_push(port);
955
956 /*
957 * If no data is received in poll_timeout, the driver will fall back
958 * to interrupt mode. We will retrigger DMA at the first interrupt.
959 */
960 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
961 > uap->dmarx.poll_timeout) {
962
963 spin_lock_irqsave(&uap->port.lock, flags);
964 pl011_dma_rx_stop(uap);
965 uap->im |= UART011_RXIM;
966 writew(uap->im, uap->port.membase + UART011_IMSC);
967 spin_unlock_irqrestore(&uap->port.lock, flags);
968
969 uap->dmarx.running = false;
970 dmaengine_terminate_all(rxchan);
971 del_timer(&uap->dmarx.timer);
972 } else {
973 mod_timer(&uap->dmarx.timer,
974 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
975 }
976 }
977
978 static void pl011_dma_startup(struct uart_amba_port *uap)
979 {
980 int ret;
981
982 if (!uap->dma_probed)
983 pl011_dma_probe(uap);
984
985 if (!uap->dmatx.chan)
986 return;
987
988 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
989 if (!uap->dmatx.buf) {
990 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
991 uap->port.fifosize = uap->fifosize;
992 return;
993 }
994
995 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
996
997 /* The DMA buffer is now the FIFO the TTY subsystem can use */
998 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
999 uap->using_tx_dma = true;
1000
1001 if (!uap->dmarx.chan)
1002 goto skip_rx;
1003
1004 /* Allocate and map DMA RX buffers */
1005 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1006 DMA_FROM_DEVICE);
1007 if (ret) {
1008 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1009 "RX buffer A", ret);
1010 goto skip_rx;
1011 }
1012
1013 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
1014 DMA_FROM_DEVICE);
1015 if (ret) {
1016 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1017 "RX buffer B", ret);
1018 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1019 DMA_FROM_DEVICE);
1020 goto skip_rx;
1021 }
1022
1023 uap->using_rx_dma = true;
1024
1025 skip_rx:
1026 /* Turn on DMA error (RX/TX will be enabled on demand) */
1027 uap->dmacr |= UART011_DMAONERR;
1028 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
1029
1030 /*
1031 * ST Micro variants has some specific dma burst threshold
1032 * compensation. Set this to 16 bytes, so burst will only
1033 * be issued above/below 16 bytes.
1034 */
1035 if (uap->vendor->dma_threshold)
1036 writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
1037 uap->port.membase + ST_UART011_DMAWM);
1038
1039 if (uap->using_rx_dma) {
1040 if (pl011_dma_rx_trigger_dma(uap))
1041 dev_dbg(uap->port.dev, "could not trigger initial "
1042 "RX DMA job, fall back to interrupt mode\n");
1043 if (uap->dmarx.poll_rate) {
1044 init_timer(&(uap->dmarx.timer));
1045 uap->dmarx.timer.function = pl011_dma_rx_poll;
1046 uap->dmarx.timer.data = (unsigned long)uap;
1047 mod_timer(&uap->dmarx.timer,
1048 jiffies +
1049 msecs_to_jiffies(uap->dmarx.poll_rate));
1050 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1051 uap->dmarx.last_jiffies = jiffies;
1052 }
1053 }
1054 }
1055
1056 static void pl011_dma_shutdown(struct uart_amba_port *uap)
1057 {
1058 if (!(uap->using_tx_dma || uap->using_rx_dma))
1059 return;
1060
1061 /* Disable RX and TX DMA */
1062 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
1063 barrier();
1064
1065 spin_lock_irq(&uap->port.lock);
1066 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
1067 writew(uap->dmacr, uap->port.membase + UART011_DMACR);
1068 spin_unlock_irq(&uap->port.lock);
1069
1070 if (uap->using_tx_dma) {
1071 /* In theory, this should already be done by pl011_dma_flush_buffer */
1072 dmaengine_terminate_all(uap->dmatx.chan);
1073 if (uap->dmatx.queued) {
1074 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
1075 DMA_TO_DEVICE);
1076 uap->dmatx.queued = false;
1077 }
1078
1079 kfree(uap->dmatx.buf);
1080 uap->using_tx_dma = false;
1081 }
1082
1083 if (uap->using_rx_dma) {
1084 dmaengine_terminate_all(uap->dmarx.chan);
1085 /* Clean up the RX DMA */
1086 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
1087 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
1088 if (uap->dmarx.poll_rate)
1089 del_timer_sync(&uap->dmarx.timer);
1090 uap->using_rx_dma = false;
1091 }
1092 }
1093
1094 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1095 {
1096 return uap->using_rx_dma;
1097 }
1098
1099 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1100 {
1101 return uap->using_rx_dma && uap->dmarx.running;
1102 }
1103
1104 #else
1105 /* Blank functions if the DMA engine is not available */
1106 static inline void pl011_dma_probe(struct uart_amba_port *uap)
1107 {
1108 }
1109
1110 static inline void pl011_dma_remove(struct uart_amba_port *uap)
1111 {
1112 }
1113
1114 static inline void pl011_dma_startup(struct uart_amba_port *uap)
1115 {
1116 }
1117
1118 static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1119 {
1120 }
1121
1122 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1123 {
1124 return false;
1125 }
1126
1127 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1128 {
1129 }
1130
1131 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1132 {
1133 return false;
1134 }
1135
1136 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1137 {
1138 }
1139
1140 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1141 {
1142 }
1143
1144 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1145 {
1146 return -EIO;
1147 }
1148
1149 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1150 {
1151 return false;
1152 }
1153
1154 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1155 {
1156 return false;
1157 }
1158
1159 #define pl011_dma_flush_buffer NULL
1160 #endif
1161
1162 static void pl011_stop_tx(struct uart_port *port)
1163 {
1164 struct uart_amba_port *uap =
1165 container_of(port, struct uart_amba_port, port);
1166
1167 uap->im &= ~UART011_TXIM;
1168 writew(uap->im, uap->port.membase + UART011_IMSC);
1169 pl011_dma_tx_stop(uap);
1170 }
1171
1172 static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
1173
1174 /* Start TX with programmed I/O only (no DMA) */
1175 static void pl011_start_tx_pio(struct uart_amba_port *uap)
1176 {
1177 uap->im |= UART011_TXIM;
1178 writew(uap->im, uap->port.membase + UART011_IMSC);
1179 pl011_tx_chars(uap, false);
1180 }
1181
1182 static void pl011_start_tx(struct uart_port *port)
1183 {
1184 struct uart_amba_port *uap =
1185 container_of(port, struct uart_amba_port, port);
1186
1187 if (!pl011_dma_tx_start(uap))
1188 pl011_start_tx_pio(uap);
1189 }
1190
1191 static void pl011_stop_rx(struct uart_port *port)
1192 {
1193 struct uart_amba_port *uap =
1194 container_of(port, struct uart_amba_port, port);
1195
1196 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1197 UART011_PEIM|UART011_BEIM|UART011_OEIM);
1198 writew(uap->im, uap->port.membase + UART011_IMSC);
1199
1200 pl011_dma_rx_stop(uap);
1201 }
1202
1203 static void pl011_enable_ms(struct uart_port *port)
1204 {
1205 struct uart_amba_port *uap =
1206 container_of(port, struct uart_amba_port, port);
1207
1208 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1209 writew(uap->im, uap->port.membase + UART011_IMSC);
1210 }
1211
1212 static void pl011_rx_chars(struct uart_amba_port *uap)
1213 __releases(&uap->port.lock)
1214 __acquires(&uap->port.lock)
1215 {
1216 pl011_fifo_to_tty(uap);
1217
1218 spin_unlock(&uap->port.lock);
1219 tty_flip_buffer_push(&uap->port.state->port);
1220 /*
1221 * If we were temporarily out of DMA mode for a while,
1222 * attempt to switch back to DMA mode again.
1223 */
1224 if (pl011_dma_rx_available(uap)) {
1225 if (pl011_dma_rx_trigger_dma(uap)) {
1226 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1227 "fall back to interrupt mode again\n");
1228 uap->im |= UART011_RXIM;
1229 writew(uap->im, uap->port.membase + UART011_IMSC);
1230 } else {
1231 #ifdef CONFIG_DMA_ENGINE
1232 /* Start Rx DMA poll */
1233 if (uap->dmarx.poll_rate) {
1234 uap->dmarx.last_jiffies = jiffies;
1235 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1236 mod_timer(&uap->dmarx.timer,
1237 jiffies +
1238 msecs_to_jiffies(uap->dmarx.poll_rate));
1239 }
1240 #endif
1241 }
1242 }
1243 spin_lock(&uap->port.lock);
1244 }
1245
1246 static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
1247 bool from_irq)
1248 {
1249 if (unlikely(!from_irq) &&
1250 readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
1251 return false; /* unable to transmit character */
1252
1253 writew(c, uap->port.membase + UART01x_DR);
1254 uap->port.icount.tx++;
1255
1256 return true;
1257 }
1258
1259 static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)
1260 {
1261 struct circ_buf *xmit = &uap->port.state->xmit;
1262 int count = uap->fifosize >> 1;
1263
1264 if (uap->port.x_char) {
1265 if (!pl011_tx_char(uap, uap->port.x_char, from_irq))
1266 return;
1267 uap->port.x_char = 0;
1268 --count;
1269 }
1270 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1271 pl011_stop_tx(&uap->port);
1272 return;
1273 }
1274
1275 /* If we are using DMA mode, try to send some characters. */
1276 if (pl011_dma_tx_irq(uap))
1277 return;
1278
1279 do {
1280 if (likely(from_irq) && count-- == 0)
1281 break;
1282
1283 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq))
1284 break;
1285
1286 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1287 } while (!uart_circ_empty(xmit));
1288
1289 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1290 uart_write_wakeup(&uap->port);
1291
1292 if (uart_circ_empty(xmit))
1293 pl011_stop_tx(&uap->port);
1294 }
1295
1296 static void pl011_modem_status(struct uart_amba_port *uap)
1297 {
1298 unsigned int status, delta;
1299
1300 status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
1301
1302 delta = status ^ uap->old_status;
1303 uap->old_status = status;
1304
1305 if (!delta)
1306 return;
1307
1308 if (delta & UART01x_FR_DCD)
1309 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1310
1311 if (delta & UART01x_FR_DSR)
1312 uap->port.icount.dsr++;
1313
1314 if (delta & UART01x_FR_CTS)
1315 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
1316
1317 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1318 }
1319
1320 static irqreturn_t pl011_int(int irq, void *dev_id)
1321 {
1322 struct uart_amba_port *uap = dev_id;
1323 unsigned long flags;
1324 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1325 int handled = 0;
1326 unsigned int dummy_read;
1327
1328 spin_lock_irqsave(&uap->port.lock, flags);
1329 status = readw(uap->port.membase + UART011_MIS);
1330 if (status) {
1331 do {
1332 if (uap->vendor->cts_event_workaround) {
1333 /* workaround to make sure that all bits are unlocked.. */
1334 writew(0x00, uap->port.membase + UART011_ICR);
1335
1336 /*
1337 * WA: introduce 26ns(1 uart clk) delay before W1C;
1338 * single apb access will incur 2 pclk(133.12Mhz) delay,
1339 * so add 2 dummy reads
1340 */
1341 dummy_read = readw(uap->port.membase + UART011_ICR);
1342 dummy_read = readw(uap->port.membase + UART011_ICR);
1343 }
1344
1345 writew(status & ~(UART011_TXIS|UART011_RTIS|
1346 UART011_RXIS),
1347 uap->port.membase + UART011_ICR);
1348
1349 if (status & (UART011_RTIS|UART011_RXIS)) {
1350 if (pl011_dma_rx_running(uap))
1351 pl011_dma_rx_irq(uap);
1352 else
1353 pl011_rx_chars(uap);
1354 }
1355 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1356 UART011_CTSMIS|UART011_RIMIS))
1357 pl011_modem_status(uap);
1358 if (status & UART011_TXIS)
1359 pl011_tx_chars(uap, true);
1360
1361 if (pass_counter-- == 0)
1362 break;
1363
1364 status = readw(uap->port.membase + UART011_MIS);
1365 } while (status != 0);
1366 handled = 1;
1367 }
1368
1369 spin_unlock_irqrestore(&uap->port.lock, flags);
1370
1371 return IRQ_RETVAL(handled);
1372 }
1373
1374 static unsigned int pl011_tx_empty(struct uart_port *port)
1375 {
1376 struct uart_amba_port *uap =
1377 container_of(port, struct uart_amba_port, port);
1378 unsigned int status = readw(uap->port.membase + UART01x_FR);
1379 return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
1380 }
1381
1382 static unsigned int pl011_get_mctrl(struct uart_port *port)
1383 {
1384 struct uart_amba_port *uap =
1385 container_of(port, struct uart_amba_port, port);
1386 unsigned int result = 0;
1387 unsigned int status = readw(uap->port.membase + UART01x_FR);
1388
1389 #define TIOCMBIT(uartbit, tiocmbit) \
1390 if (status & uartbit) \
1391 result |= tiocmbit
1392
1393 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1394 TIOCMBIT(UART01x_FR_DSR, TIOCM_DSR);
1395 TIOCMBIT(UART01x_FR_CTS, TIOCM_CTS);
1396 TIOCMBIT(UART011_FR_RI, TIOCM_RNG);
1397 #undef TIOCMBIT
1398 return result;
1399 }
1400
1401 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1402 {
1403 struct uart_amba_port *uap =
1404 container_of(port, struct uart_amba_port, port);
1405 unsigned int cr;
1406
1407 cr = readw(uap->port.membase + UART011_CR);
1408
1409 #define TIOCMBIT(tiocmbit, uartbit) \
1410 if (mctrl & tiocmbit) \
1411 cr |= uartbit; \
1412 else \
1413 cr &= ~uartbit
1414
1415 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1416 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1417 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1418 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1419 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
1420
1421 if (uap->autorts) {
1422 /* We need to disable auto-RTS if we want to turn RTS off */
1423 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1424 }
1425 #undef TIOCMBIT
1426
1427 writew(cr, uap->port.membase + UART011_CR);
1428 }
1429
1430 static void pl011_break_ctl(struct uart_port *port, int break_state)
1431 {
1432 struct uart_amba_port *uap =
1433 container_of(port, struct uart_amba_port, port);
1434 unsigned long flags;
1435 unsigned int lcr_h;
1436
1437 spin_lock_irqsave(&uap->port.lock, flags);
1438 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
1439 if (break_state == -1)
1440 lcr_h |= UART01x_LCRH_BRK;
1441 else
1442 lcr_h &= ~UART01x_LCRH_BRK;
1443 writew(lcr_h, uap->port.membase + uap->lcrh_tx);
1444 spin_unlock_irqrestore(&uap->port.lock, flags);
1445 }
1446
1447 #ifdef CONFIG_CONSOLE_POLL
1448
1449 static void pl011_quiesce_irqs(struct uart_port *port)
1450 {
1451 struct uart_amba_port *uap =
1452 container_of(port, struct uart_amba_port, port);
1453 unsigned char __iomem *regs = uap->port.membase;
1454
1455 writew(readw(regs + UART011_MIS), regs + UART011_ICR);
1456 /*
1457 * There is no way to clear TXIM as this is "ready to transmit IRQ", so
1458 * we simply mask it. start_tx() will unmask it.
1459 *
1460 * Note we can race with start_tx(), and if the race happens, the
1461 * polling user might get another interrupt just after we clear it.
1462 * But it should be OK and can happen even w/o the race, e.g.
1463 * controller immediately got some new data and raised the IRQ.
1464 *
1465 * And whoever uses polling routines assumes that it manages the device
1466 * (including tx queue), so we're also fine with start_tx()'s caller
1467 * side.
1468 */
1469 writew(readw(regs + UART011_IMSC) & ~UART011_TXIM, regs + UART011_IMSC);
1470 }
1471
1472 static int pl011_get_poll_char(struct uart_port *port)
1473 {
1474 struct uart_amba_port *uap =
1475 container_of(port, struct uart_amba_port, port);
1476 unsigned int status;
1477
1478 /*
1479 * The caller might need IRQs lowered, e.g. if used with KDB NMI
1480 * debugger.
1481 */
1482 pl011_quiesce_irqs(port);
1483
1484 status = readw(uap->port.membase + UART01x_FR);
1485 if (status & UART01x_FR_RXFE)
1486 return NO_POLL_CHAR;
1487
1488 return readw(uap->port.membase + UART01x_DR);
1489 }
1490
1491 static void pl011_put_poll_char(struct uart_port *port,
1492 unsigned char ch)
1493 {
1494 struct uart_amba_port *uap =
1495 container_of(port, struct uart_amba_port, port);
1496
1497 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
1498 barrier();
1499
1500 writew(ch, uap->port.membase + UART01x_DR);
1501 }
1502
1503 #endif /* CONFIG_CONSOLE_POLL */
1504
1505 static int pl011_hwinit(struct uart_port *port)
1506 {
1507 struct uart_amba_port *uap =
1508 container_of(port, struct uart_amba_port, port);
1509 int retval;
1510
1511 /* Optionaly enable pins to be muxed in and configured */
1512 pinctrl_pm_select_default_state(port->dev);
1513
1514 /*
1515 * Try to enable the clock producer.
1516 */
1517 retval = clk_prepare_enable(uap->clk);
1518 if (retval)
1519 return retval;
1520
1521 uap->port.uartclk = clk_get_rate(uap->clk);
1522
1523 /* Clear pending error and receive interrupts */
1524 writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS |
1525 UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR);
1526
1527 /*
1528 * Save interrupts enable mask, and enable RX interrupts in case if
1529 * the interrupt is used for NMI entry.
1530 */
1531 uap->im = readw(uap->port.membase + UART011_IMSC);
1532 writew(UART011_RTIM | UART011_RXIM, uap->port.membase + UART011_IMSC);
1533
1534 if (dev_get_platdata(uap->port.dev)) {
1535 struct amba_pl011_data *plat;
1536
1537 plat = dev_get_platdata(uap->port.dev);
1538 if (plat->init)
1539 plat->init();
1540 }
1541 return 0;
1542 }
1543
1544 static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
1545 {
1546 writew(lcr_h, uap->port.membase + uap->lcrh_rx);
1547 if (uap->lcrh_rx != uap->lcrh_tx) {
1548 int i;
1549 /*
1550 * Wait 10 PCLKs before writing LCRH_TX register,
1551 * to get this delay write read only register 10 times
1552 */
1553 for (i = 0; i < 10; ++i)
1554 writew(0xff, uap->port.membase + UART011_MIS);
1555 writew(lcr_h, uap->port.membase + uap->lcrh_tx);
1556 }
1557 }
1558
1559 static int pl011_startup(struct uart_port *port)
1560 {
1561 struct uart_amba_port *uap =
1562 container_of(port, struct uart_amba_port, port);
1563 unsigned int cr;
1564 int retval;
1565
1566 retval = pl011_hwinit(port);
1567 if (retval)
1568 goto clk_dis;
1569
1570 writew(uap->im, uap->port.membase + UART011_IMSC);
1571
1572 /*
1573 * Allocate the IRQ
1574 */
1575 retval = request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
1576 if (retval)
1577 goto clk_dis;
1578
1579 writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS);
1580
1581 spin_lock_irq(&uap->port.lock);
1582
1583 /* restore RTS and DTR */
1584 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
1585 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
1586 writew(cr, uap->port.membase + UART011_CR);
1587
1588 spin_unlock_irq(&uap->port.lock);
1589
1590 /*
1591 * initialise the old status of the modem signals
1592 */
1593 uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
1594
1595 /* Startup DMA */
1596 pl011_dma_startup(uap);
1597
1598 /*
1599 * Finally, enable interrupts, only timeouts when using DMA
1600 * if initial RX DMA job failed, start in interrupt mode
1601 * as well.
1602 */
1603 spin_lock_irq(&uap->port.lock);
1604 /* Clear out any spuriously appearing RX interrupts */
1605 writew(UART011_RTIS | UART011_RXIS,
1606 uap->port.membase + UART011_ICR);
1607 uap->im = UART011_RTIM;
1608 if (!pl011_dma_rx_running(uap))
1609 uap->im |= UART011_RXIM;
1610 writew(uap->im, uap->port.membase + UART011_IMSC);
1611 spin_unlock_irq(&uap->port.lock);
1612
1613 return 0;
1614
1615 clk_dis:
1616 clk_disable_unprepare(uap->clk);
1617 return retval;
1618 }
1619
1620 static void pl011_shutdown_channel(struct uart_amba_port *uap,
1621 unsigned int lcrh)
1622 {
1623 unsigned long val;
1624
1625 val = readw(uap->port.membase + lcrh);
1626 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1627 writew(val, uap->port.membase + lcrh);
1628 }
1629
1630 static void pl011_shutdown(struct uart_port *port)
1631 {
1632 struct uart_amba_port *uap =
1633 container_of(port, struct uart_amba_port, port);
1634 unsigned int cr;
1635
1636 /*
1637 * disable all interrupts
1638 */
1639 spin_lock_irq(&uap->port.lock);
1640 uap->im = 0;
1641 writew(uap->im, uap->port.membase + UART011_IMSC);
1642 writew(0xffff, uap->port.membase + UART011_ICR);
1643 spin_unlock_irq(&uap->port.lock);
1644
1645 pl011_dma_shutdown(uap);
1646
1647 /*
1648 * Free the interrupt
1649 */
1650 free_irq(uap->port.irq, uap);
1651
1652 /*
1653 * disable the port
1654 * disable the port. It should not disable RTS and DTR.
1655 * Also RTS and DTR state should be preserved to restore
1656 * it during startup().
1657 */
1658 uap->autorts = false;
1659 spin_lock_irq(&uap->port.lock);
1660 cr = readw(uap->port.membase + UART011_CR);
1661 uap->old_cr = cr;
1662 cr &= UART011_CR_RTS | UART011_CR_DTR;
1663 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1664 writew(cr, uap->port.membase + UART011_CR);
1665 spin_unlock_irq(&uap->port.lock);
1666
1667 /*
1668 * disable break condition and fifos
1669 */
1670 pl011_shutdown_channel(uap, uap->lcrh_rx);
1671 if (uap->lcrh_rx != uap->lcrh_tx)
1672 pl011_shutdown_channel(uap, uap->lcrh_tx);
1673
1674 /*
1675 * Shut down the clock producer
1676 */
1677 clk_disable_unprepare(uap->clk);
1678 /* Optionally let pins go into sleep states */
1679 pinctrl_pm_select_sleep_state(port->dev);
1680
1681 if (dev_get_platdata(uap->port.dev)) {
1682 struct amba_pl011_data *plat;
1683
1684 plat = dev_get_platdata(uap->port.dev);
1685 if (plat->exit)
1686 plat->exit();
1687 }
1688
1689 if (uap->port.ops->flush_buffer)
1690 uap->port.ops->flush_buffer(port);
1691 }
1692
1693 static void
1694 pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1695 struct ktermios *old)
1696 {
1697 struct uart_amba_port *uap =
1698 container_of(port, struct uart_amba_port, port);
1699 unsigned int lcr_h, old_cr;
1700 unsigned long flags;
1701 unsigned int baud, quot, clkdiv;
1702
1703 if (uap->vendor->oversampling)
1704 clkdiv = 8;
1705 else
1706 clkdiv = 16;
1707
1708 /*
1709 * Ask the core to calculate the divisor for us.
1710 */
1711 baud = uart_get_baud_rate(port, termios, old, 0,
1712 port->uartclk / clkdiv);
1713 #ifdef CONFIG_DMA_ENGINE
1714 /*
1715 * Adjust RX DMA polling rate with baud rate if not specified.
1716 */
1717 if (uap->dmarx.auto_poll_rate)
1718 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
1719 #endif
1720
1721 if (baud > port->uartclk/16)
1722 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1723 else
1724 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1725
1726 switch (termios->c_cflag & CSIZE) {
1727 case CS5:
1728 lcr_h = UART01x_LCRH_WLEN_5;
1729 break;
1730 case CS6:
1731 lcr_h = UART01x_LCRH_WLEN_6;
1732 break;
1733 case CS7:
1734 lcr_h = UART01x_LCRH_WLEN_7;
1735 break;
1736 default: // CS8
1737 lcr_h = UART01x_LCRH_WLEN_8;
1738 break;
1739 }
1740 if (termios->c_cflag & CSTOPB)
1741 lcr_h |= UART01x_LCRH_STP2;
1742 if (termios->c_cflag & PARENB) {
1743 lcr_h |= UART01x_LCRH_PEN;
1744 if (!(termios->c_cflag & PARODD))
1745 lcr_h |= UART01x_LCRH_EPS;
1746 }
1747 if (uap->fifosize > 1)
1748 lcr_h |= UART01x_LCRH_FEN;
1749
1750 spin_lock_irqsave(&port->lock, flags);
1751
1752 /*
1753 * Update the per-port timeout.
1754 */
1755 uart_update_timeout(port, termios->c_cflag, baud);
1756
1757 port->read_status_mask = UART011_DR_OE | 255;
1758 if (termios->c_iflag & INPCK)
1759 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1760 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1761 port->read_status_mask |= UART011_DR_BE;
1762
1763 /*
1764 * Characters to ignore
1765 */
1766 port->ignore_status_mask = 0;
1767 if (termios->c_iflag & IGNPAR)
1768 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1769 if (termios->c_iflag & IGNBRK) {
1770 port->ignore_status_mask |= UART011_DR_BE;
1771 /*
1772 * If we're ignoring parity and break indicators,
1773 * ignore overruns too (for real raw support).
1774 */
1775 if (termios->c_iflag & IGNPAR)
1776 port->ignore_status_mask |= UART011_DR_OE;
1777 }
1778
1779 /*
1780 * Ignore all characters if CREAD is not set.
1781 */
1782 if ((termios->c_cflag & CREAD) == 0)
1783 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1784
1785 if (UART_ENABLE_MS(port, termios->c_cflag))
1786 pl011_enable_ms(port);
1787
1788 /* first, disable everything */
1789 old_cr = readw(port->membase + UART011_CR);
1790 writew(0, port->membase + UART011_CR);
1791
1792 if (termios->c_cflag & CRTSCTS) {
1793 if (old_cr & UART011_CR_RTS)
1794 old_cr |= UART011_CR_RTSEN;
1795
1796 old_cr |= UART011_CR_CTSEN;
1797 uap->autorts = true;
1798 } else {
1799 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
1800 uap->autorts = false;
1801 }
1802
1803 if (uap->vendor->oversampling) {
1804 if (baud > port->uartclk / 16)
1805 old_cr |= ST_UART011_CR_OVSFACT;
1806 else
1807 old_cr &= ~ST_UART011_CR_OVSFACT;
1808 }
1809
1810 /*
1811 * Workaround for the ST Micro oversampling variants to
1812 * increase the bitrate slightly, by lowering the divisor,
1813 * to avoid delayed sampling of start bit at high speeds,
1814 * else we see data corruption.
1815 */
1816 if (uap->vendor->oversampling) {
1817 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
1818 quot -= 1;
1819 else if ((baud > 3250000) && (quot > 2))
1820 quot -= 2;
1821 }
1822 /* Set baud rate */
1823 writew(quot & 0x3f, port->membase + UART011_FBRD);
1824 writew(quot >> 6, port->membase + UART011_IBRD);
1825
1826 /*
1827 * ----------v----------v----------v----------v-----
1828 * NOTE: lcrh_tx and lcrh_rx MUST BE WRITTEN AFTER
1829 * UART011_FBRD & UART011_IBRD.
1830 * ----------^----------^----------^----------^-----
1831 */
1832 pl011_write_lcr_h(uap, lcr_h);
1833 writew(old_cr, port->membase + UART011_CR);
1834
1835 spin_unlock_irqrestore(&port->lock, flags);
1836 }
1837
1838 static const char *pl011_type(struct uart_port *port)
1839 {
1840 struct uart_amba_port *uap =
1841 container_of(port, struct uart_amba_port, port);
1842 return uap->port.type == PORT_AMBA ? uap->type : NULL;
1843 }
1844
1845 /*
1846 * Release the memory region(s) being used by 'port'
1847 */
1848 static void pl011_release_port(struct uart_port *port)
1849 {
1850 release_mem_region(port->mapbase, SZ_4K);
1851 }
1852
1853 /*
1854 * Request the memory region(s) being used by 'port'
1855 */
1856 static int pl011_request_port(struct uart_port *port)
1857 {
1858 return request_mem_region(port->mapbase, SZ_4K, "uart-pl011")
1859 != NULL ? 0 : -EBUSY;
1860 }
1861
1862 /*
1863 * Configure/autoconfigure the port.
1864 */
1865 static void pl011_config_port(struct uart_port *port, int flags)
1866 {
1867 if (flags & UART_CONFIG_TYPE) {
1868 port->type = PORT_AMBA;
1869 pl011_request_port(port);
1870 }
1871 }
1872
1873 /*
1874 * verify the new serial_struct (for TIOCSSERIAL).
1875 */
1876 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
1877 {
1878 int ret = 0;
1879 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
1880 ret = -EINVAL;
1881 if (ser->irq < 0 || ser->irq >= nr_irqs)
1882 ret = -EINVAL;
1883 if (ser->baud_base < 9600)
1884 ret = -EINVAL;
1885 return ret;
1886 }
1887
1888 static struct uart_ops amba_pl011_pops = {
1889 .tx_empty = pl011_tx_empty,
1890 .set_mctrl = pl011_set_mctrl,
1891 .get_mctrl = pl011_get_mctrl,
1892 .stop_tx = pl011_stop_tx,
1893 .start_tx = pl011_start_tx,
1894 .stop_rx = pl011_stop_rx,
1895 .enable_ms = pl011_enable_ms,
1896 .break_ctl = pl011_break_ctl,
1897 .startup = pl011_startup,
1898 .shutdown = pl011_shutdown,
1899 .flush_buffer = pl011_dma_flush_buffer,
1900 .set_termios = pl011_set_termios,
1901 .type = pl011_type,
1902 .release_port = pl011_release_port,
1903 .request_port = pl011_request_port,
1904 .config_port = pl011_config_port,
1905 .verify_port = pl011_verify_port,
1906 #ifdef CONFIG_CONSOLE_POLL
1907 .poll_init = pl011_hwinit,
1908 .poll_get_char = pl011_get_poll_char,
1909 .poll_put_char = pl011_put_poll_char,
1910 #endif
1911 };
1912
1913 static struct uart_amba_port *amba_ports[UART_NR];
1914
1915 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
1916
1917 static void pl011_console_putchar(struct uart_port *port, int ch)
1918 {
1919 struct uart_amba_port *uap =
1920 container_of(port, struct uart_amba_port, port);
1921
1922 while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
1923 barrier();
1924 writew(ch, uap->port.membase + UART01x_DR);
1925 }
1926
1927 static void
1928 pl011_console_write(struct console *co, const char *s, unsigned int count)
1929 {
1930 struct uart_amba_port *uap = amba_ports[co->index];
1931 unsigned int status, old_cr, new_cr;
1932 unsigned long flags;
1933 int locked = 1;
1934
1935 clk_enable(uap->clk);
1936
1937 local_irq_save(flags);
1938 if (uap->port.sysrq)
1939 locked = 0;
1940 else if (oops_in_progress)
1941 locked = spin_trylock(&uap->port.lock);
1942 else
1943 spin_lock(&uap->port.lock);
1944
1945 /*
1946 * First save the CR then disable the interrupts
1947 */
1948 old_cr = readw(uap->port.membase + UART011_CR);
1949 new_cr = old_cr & ~UART011_CR_CTSEN;
1950 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1951 writew(new_cr, uap->port.membase + UART011_CR);
1952
1953 uart_console_write(&uap->port, s, count, pl011_console_putchar);
1954
1955 /*
1956 * Finally, wait for transmitter to become empty
1957 * and restore the TCR
1958 */
1959 do {
1960 status = readw(uap->port.membase + UART01x_FR);
1961 } while (status & UART01x_FR_BUSY);
1962 writew(old_cr, uap->port.membase + UART011_CR);
1963
1964 if (locked)
1965 spin_unlock(&uap->port.lock);
1966 local_irq_restore(flags);
1967
1968 clk_disable(uap->clk);
1969 }
1970
1971 static void __init
1972 pl011_console_get_options(struct uart_amba_port *uap, int *baud,
1973 int *parity, int *bits)
1974 {
1975 if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
1976 unsigned int lcr_h, ibrd, fbrd;
1977
1978 lcr_h = readw(uap->port.membase + uap->lcrh_tx);
1979
1980 *parity = 'n';
1981 if (lcr_h & UART01x_LCRH_PEN) {
1982 if (lcr_h & UART01x_LCRH_EPS)
1983 *parity = 'e';
1984 else
1985 *parity = 'o';
1986 }
1987
1988 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
1989 *bits = 7;
1990 else
1991 *bits = 8;
1992
1993 ibrd = readw(uap->port.membase + UART011_IBRD);
1994 fbrd = readw(uap->port.membase + UART011_FBRD);
1995
1996 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
1997
1998 if (uap->vendor->oversampling) {
1999 if (readw(uap->port.membase + UART011_CR)
2000 & ST_UART011_CR_OVSFACT)
2001 *baud *= 2;
2002 }
2003 }
2004 }
2005
2006 static int __init pl011_console_setup(struct console *co, char *options)
2007 {
2008 struct uart_amba_port *uap;
2009 int baud = 38400;
2010 int bits = 8;
2011 int parity = 'n';
2012 int flow = 'n';
2013 int ret;
2014
2015 /*
2016 * Check whether an invalid uart number has been specified, and
2017 * if so, search for the first available port that does have
2018 * console support.
2019 */
2020 if (co->index >= UART_NR)
2021 co->index = 0;
2022 uap = amba_ports[co->index];
2023 if (!uap)
2024 return -ENODEV;
2025
2026 /* Allow pins to be muxed in and configured */
2027 pinctrl_pm_select_default_state(uap->port.dev);
2028
2029 ret = clk_prepare(uap->clk);
2030 if (ret)
2031 return ret;
2032
2033 if (dev_get_platdata(uap->port.dev)) {
2034 struct amba_pl011_data *plat;
2035
2036 plat = dev_get_platdata(uap->port.dev);
2037 if (plat->init)
2038 plat->init();
2039 }
2040
2041 uap->port.uartclk = clk_get_rate(uap->clk);
2042
2043 if (options)
2044 uart_parse_options(options, &baud, &parity, &bits, &flow);
2045 else
2046 pl011_console_get_options(uap, &baud, &parity, &bits);
2047
2048 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2049 }
2050
2051 static struct uart_driver amba_reg;
2052 static struct console amba_console = {
2053 .name = "ttyAMA",
2054 .write = pl011_console_write,
2055 .device = uart_console_device,
2056 .setup = pl011_console_setup,
2057 .flags = CON_PRINTBUFFER,
2058 .index = -1,
2059 .data = &amba_reg,
2060 };
2061
2062 #define AMBA_CONSOLE (&amba_console)
2063
2064 static void pl011_putc(struct uart_port *port, int c)
2065 {
2066 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2067 ;
2068 writeb(c, port->membase + UART01x_DR);
2069 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
2070 ;
2071 }
2072
2073 static void pl011_early_write(struct console *con, const char *s, unsigned n)
2074 {
2075 struct earlycon_device *dev = con->data;
2076
2077 uart_console_write(&dev->port, s, n, pl011_putc);
2078 }
2079
2080 static int __init pl011_early_console_setup(struct earlycon_device *device,
2081 const char *opt)
2082 {
2083 if (!device->port.membase)
2084 return -ENODEV;
2085
2086 device->con->write = pl011_early_write;
2087 return 0;
2088 }
2089 EARLYCON_DECLARE(pl011, pl011_early_console_setup);
2090 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
2091
2092 #else
2093 #define AMBA_CONSOLE NULL
2094 #endif
2095
2096 static struct uart_driver amba_reg = {
2097 .owner = THIS_MODULE,
2098 .driver_name = "ttyAMA",
2099 .dev_name = "ttyAMA",
2100 .major = SERIAL_AMBA_MAJOR,
2101 .minor = SERIAL_AMBA_MINOR,
2102 .nr = UART_NR,
2103 .cons = AMBA_CONSOLE,
2104 };
2105
2106 static int pl011_probe_dt_alias(int index, struct device *dev)
2107 {
2108 struct device_node *np;
2109 static bool seen_dev_with_alias = false;
2110 static bool seen_dev_without_alias = false;
2111 int ret = index;
2112
2113 if (!IS_ENABLED(CONFIG_OF))
2114 return ret;
2115
2116 np = dev->of_node;
2117 if (!np)
2118 return ret;
2119
2120 ret = of_alias_get_id(np, "serial");
2121 if (IS_ERR_VALUE(ret)) {
2122 seen_dev_without_alias = true;
2123 ret = index;
2124 } else {
2125 seen_dev_with_alias = true;
2126 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
2127 dev_warn(dev, "requested serial port %d not available.\n", ret);
2128 ret = index;
2129 }
2130 }
2131
2132 if (seen_dev_with_alias && seen_dev_without_alias)
2133 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2134
2135 return ret;
2136 }
2137
2138 static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2139 {
2140 struct uart_amba_port *uap;
2141 struct vendor_data *vendor = id->data;
2142 void __iomem *base;
2143 int i, ret;
2144
2145 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2146 if (amba_ports[i] == NULL)
2147 break;
2148
2149 if (i == ARRAY_SIZE(amba_ports))
2150 return -EBUSY;
2151
2152 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2153 GFP_KERNEL);
2154 if (uap == NULL)
2155 return -ENOMEM;
2156
2157 i = pl011_probe_dt_alias(i, &dev->dev);
2158
2159 base = devm_ioremap(&dev->dev, dev->res.start,
2160 resource_size(&dev->res));
2161 if (!base)
2162 return -ENOMEM;
2163
2164 uap->clk = devm_clk_get(&dev->dev, NULL);
2165 if (IS_ERR(uap->clk))
2166 return PTR_ERR(uap->clk);
2167
2168 uap->vendor = vendor;
2169 uap->lcrh_rx = vendor->lcrh_rx;
2170 uap->lcrh_tx = vendor->lcrh_tx;
2171 uap->old_cr = 0;
2172 uap->fifosize = vendor->get_fifosize(dev);
2173 uap->port.dev = &dev->dev;
2174 uap->port.mapbase = dev->res.start;
2175 uap->port.membase = base;
2176 uap->port.iotype = UPIO_MEM;
2177 uap->port.irq = dev->irq[0];
2178 uap->port.fifosize = uap->fifosize;
2179 uap->port.ops = &amba_pl011_pops;
2180 uap->port.flags = UPF_BOOT_AUTOCONF;
2181 uap->port.line = i;
2182
2183 /* Ensure interrupts from this UART are masked and cleared */
2184 writew(0, uap->port.membase + UART011_IMSC);
2185 writew(0xffff, uap->port.membase + UART011_ICR);
2186
2187 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2188
2189 amba_ports[i] = uap;
2190
2191 amba_set_drvdata(dev, uap);
2192
2193 if (!amba_reg.state) {
2194 ret = uart_register_driver(&amba_reg);
2195 if (ret < 0) {
2196 dev_err(&dev->dev,
2197 "Failed to register AMBA-PL011 driver\n");
2198 return ret;
2199 }
2200 }
2201
2202 ret = uart_add_one_port(&amba_reg, &uap->port);
2203 if (ret) {
2204 amba_ports[i] = NULL;
2205 uart_unregister_driver(&amba_reg);
2206 }
2207
2208 return ret;
2209 }
2210
2211 static int pl011_remove(struct amba_device *dev)
2212 {
2213 struct uart_amba_port *uap = amba_get_drvdata(dev);
2214 bool busy = false;
2215 int i;
2216
2217 uart_remove_one_port(&amba_reg, &uap->port);
2218
2219 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2220 if (amba_ports[i] == uap)
2221 amba_ports[i] = NULL;
2222 else if (amba_ports[i])
2223 busy = true;
2224
2225 pl011_dma_remove(uap);
2226 if (!busy)
2227 uart_unregister_driver(&amba_reg);
2228 return 0;
2229 }
2230
2231 #ifdef CONFIG_PM_SLEEP
2232 static int pl011_suspend(struct device *dev)
2233 {
2234 struct uart_amba_port *uap = dev_get_drvdata(dev);
2235
2236 if (!uap)
2237 return -EINVAL;
2238
2239 return uart_suspend_port(&amba_reg, &uap->port);
2240 }
2241
2242 static int pl011_resume(struct device *dev)
2243 {
2244 struct uart_amba_port *uap = dev_get_drvdata(dev);
2245
2246 if (!uap)
2247 return -EINVAL;
2248
2249 return uart_resume_port(&amba_reg, &uap->port);
2250 }
2251 #endif
2252
2253 static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume);
2254
2255 static struct amba_id pl011_ids[] = {
2256 {
2257 .id = 0x00041011,
2258 .mask = 0x000fffff,
2259 .data = &vendor_arm,
2260 },
2261 {
2262 .id = 0x00380802,
2263 .mask = 0x00ffffff,
2264 .data = &vendor_st,
2265 },
2266 { 0, 0 },
2267 };
2268
2269 MODULE_DEVICE_TABLE(amba, pl011_ids);
2270
2271 static struct amba_driver pl011_driver = {
2272 .drv = {
2273 .name = "uart-pl011",
2274 .pm = &pl011_dev_pm_ops,
2275 },
2276 .id_table = pl011_ids,
2277 .probe = pl011_probe,
2278 .remove = pl011_remove,
2279 };
2280
2281 static int __init pl011_init(void)
2282 {
2283 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2284
2285 return amba_driver_register(&pl011_driver);
2286 }
2287
2288 static void __exit pl011_exit(void)
2289 {
2290 amba_driver_unregister(&pl011_driver);
2291 }
2292
2293 /*
2294 * While this can be a module, if builtin it's most likely the console
2295 * So let's leave module_exit but move module_init to an earlier place
2296 */
2297 arch_initcall(pl011_init);
2298 module_exit(pl011_exit);
2299
2300 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2301 MODULE_DESCRIPTION("ARM AMBA serial port driver");
2302 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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