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Merge branch 'for-linus-4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/mason...
[deliverable/linux.git] / drivers / tty / serial / crisv10.c
1 /*
2 * Serial port driver for the ETRAX 100LX chip
3 *
4 * Copyright (C) 1998-2007 Axis Communications AB
5 *
6 * Many, many authors. Based once upon a time on serial.c for 16x50.
7 *
8 */
9
10 static char *serial_version = "$Revision: 1.25 $";
11
12 #include <linux/types.h>
13 #include <linux/errno.h>
14 #include <linux/signal.h>
15 #include <linux/sched.h>
16 #include <linux/timer.h>
17 #include <linux/interrupt.h>
18 #include <linux/tty.h>
19 #include <linux/tty_flip.h>
20 #include <linux/major.h>
21 #include <linux/string.h>
22 #include <linux/fcntl.h>
23 #include <linux/mm.h>
24 #include <linux/slab.h>
25 #include <linux/init.h>
26 #include <linux/kernel.h>
27 #include <linux/mutex.h>
28 #include <linux/bitops.h>
29 #include <linux/seq_file.h>
30 #include <linux/delay.h>
31 #include <linux/module.h>
32 #include <linux/uaccess.h>
33 #include <linux/io.h>
34
35 #include <asm/irq.h>
36 #include <asm/dma.h>
37
38 #include <arch/svinto.h>
39 #include <arch/system.h>
40
41 /* non-arch dependent serial structures are in linux/serial.h */
42 #include <linux/serial.h>
43 /* while we keep our own stuff (struct e100_serial) in a local .h file */
44 #include "crisv10.h"
45 #include <asm/fasttimer.h>
46 #include <arch/io_interface_mux.h>
47
48 #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
49 #ifndef CONFIG_ETRAX_FAST_TIMER
50 #error "Enable FAST_TIMER to use SERIAL_FAST_TIMER"
51 #endif
52 #endif
53
54 #if defined(CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS) && \
55 (CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS == 0)
56 #error "RX_TIMEOUT_TICKS == 0 not allowed, use 1"
57 #endif
58
59 /*
60 * All of the compatibilty code so we can compile serial.c against
61 * older kernels is hidden in serial_compat.h
62 */
63 #if defined(LOCAL_HEADERS)
64 #include "serial_compat.h"
65 #endif
66
67 struct tty_driver *serial_driver;
68
69 /* number of characters left in xmit buffer before we ask for more */
70 #define WAKEUP_CHARS 256
71
72 //#define SERIAL_DEBUG_INTR
73 //#define SERIAL_DEBUG_OPEN
74 //#define SERIAL_DEBUG_FLOW
75 //#define SERIAL_DEBUG_DATA
76 //#define SERIAL_DEBUG_THROTTLE
77 //#define SERIAL_DEBUG_IO /* Debug for Extra control and status pins */
78 //#define SERIAL_DEBUG_LINE 0 /* What serport we want to debug */
79
80 /* Enable this to use serial interrupts to handle when you
81 expect the first received event on the serial port to
82 be an error, break or similar. Used to be able to flash IRMA
83 from eLinux */
84 #define SERIAL_HANDLE_EARLY_ERRORS
85
86 /* Currently 16 descriptors x 128 bytes = 2048 bytes */
87 #define SERIAL_DESCR_BUF_SIZE 256
88
89 #define SERIAL_PRESCALE_BASE 3125000 /* 3.125MHz */
90 #define DEF_BAUD_BASE SERIAL_PRESCALE_BASE
91
92 /* We don't want to load the system with massive fast timer interrupt
93 * on high baudrates so limit it to 250 us (4kHz) */
94 #define MIN_FLUSH_TIME_USEC 250
95
96 /* Add an x here to log a lot of timer stuff */
97 #define TIMERD(x)
98 /* Debug details of interrupt handling */
99 #define DINTR1(x) /* irq on/off, errors */
100 #define DINTR2(x) /* tx and rx */
101 /* Debug flip buffer stuff */
102 #define DFLIP(x)
103 /* Debug flow control and overview of data flow */
104 #define DFLOW(x)
105 #define DBAUD(x)
106 #define DLOG_INT_TRIG(x)
107
108 //#define DEBUG_LOG_INCLUDED
109 #ifndef DEBUG_LOG_INCLUDED
110 #define DEBUG_LOG(line, string, value)
111 #else
112 struct debug_log_info
113 {
114 unsigned long time;
115 unsigned long timer_data;
116 // int line;
117 const char *string;
118 int value;
119 };
120 #define DEBUG_LOG_SIZE 4096
121
122 struct debug_log_info debug_log[DEBUG_LOG_SIZE];
123 int debug_log_pos = 0;
124
125 #define DEBUG_LOG(_line, _string, _value) do { \
126 if ((_line) == SERIAL_DEBUG_LINE) {\
127 debug_log_func(_line, _string, _value); \
128 }\
129 }while(0)
130
131 void debug_log_func(int line, const char *string, int value)
132 {
133 if (debug_log_pos < DEBUG_LOG_SIZE) {
134 debug_log[debug_log_pos].time = jiffies;
135 debug_log[debug_log_pos].timer_data = *R_TIMER_DATA;
136 // debug_log[debug_log_pos].line = line;
137 debug_log[debug_log_pos].string = string;
138 debug_log[debug_log_pos].value = value;
139 debug_log_pos++;
140 }
141 /*printk(string, value);*/
142 }
143 #endif
144
145 #ifndef CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS
146 /* Default number of timer ticks before flushing rx fifo
147 * When using "little data, low latency applications: use 0
148 * When using "much data applications (PPP)" use ~5
149 */
150 #define CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS 5
151 #endif
152
153 unsigned long timer_data_to_ns(unsigned long timer_data);
154
155 static void change_speed(struct e100_serial *info);
156 static void rs_throttle(struct tty_struct * tty);
157 static void rs_wait_until_sent(struct tty_struct *tty, int timeout);
158 static int rs_write(struct tty_struct *tty,
159 const unsigned char *buf, int count);
160 #ifdef CONFIG_ETRAX_RS485
161 static int e100_write_rs485(struct tty_struct *tty,
162 const unsigned char *buf, int count);
163 #endif
164 static int get_lsr_info(struct e100_serial *info, unsigned int *value);
165
166
167 #define DEF_BAUD 115200 /* 115.2 kbit/s */
168 #define DEF_RX 0x20 /* or SERIAL_CTRL_W >> 8 */
169 /* Default value of tx_ctrl register: has txd(bit 7)=1 (idle) as default */
170 #define DEF_TX 0x80 /* or SERIAL_CTRL_B */
171
172 /* offsets from R_SERIALx_CTRL */
173
174 #define REG_DATA 0
175 #define REG_DATA_STATUS32 0 /* this is the 32 bit register R_SERIALx_READ */
176 #define REG_TR_DATA 0
177 #define REG_STATUS 1
178 #define REG_TR_CTRL 1
179 #define REG_REC_CTRL 2
180 #define REG_BAUD 3
181 #define REG_XOFF 4 /* this is a 32 bit register */
182
183 /* The bitfields are the same for all serial ports */
184 #define SER_RXD_MASK IO_MASK(R_SERIAL0_STATUS, rxd)
185 #define SER_DATA_AVAIL_MASK IO_MASK(R_SERIAL0_STATUS, data_avail)
186 #define SER_FRAMING_ERR_MASK IO_MASK(R_SERIAL0_STATUS, framing_err)
187 #define SER_PAR_ERR_MASK IO_MASK(R_SERIAL0_STATUS, par_err)
188 #define SER_OVERRUN_MASK IO_MASK(R_SERIAL0_STATUS, overrun)
189
190 #define SER_ERROR_MASK (SER_OVERRUN_MASK | SER_PAR_ERR_MASK | SER_FRAMING_ERR_MASK)
191
192 /* Values for info->errorcode */
193 #define ERRCODE_SET_BREAK (TTY_BREAK)
194 #define ERRCODE_INSERT 0x100
195 #define ERRCODE_INSERT_BREAK (ERRCODE_INSERT | TTY_BREAK)
196
197 #define FORCE_EOP(info) *R_SET_EOP = 1U << info->iseteop;
198
199 /*
200 * General note regarding the use of IO_* macros in this file:
201 *
202 * We will use the bits defined for DMA channel 6 when using various
203 * IO_* macros (e.g. IO_STATE, IO_MASK, IO_EXTRACT) and _assume_ they are
204 * the same for all channels (which of course they are).
205 *
206 * We will also use the bits defined for serial port 0 when writing commands
207 * to the different ports, as these bits too are the same for all ports.
208 */
209
210
211 /* Mask for the irqs possibly enabled in R_IRQ_MASK1_RD etc. */
212 static const unsigned long e100_ser_int_mask = 0
213 #ifdef CONFIG_ETRAX_SERIAL_PORT0
214 | IO_MASK(R_IRQ_MASK1_RD, ser0_data) | IO_MASK(R_IRQ_MASK1_RD, ser0_ready)
215 #endif
216 #ifdef CONFIG_ETRAX_SERIAL_PORT1
217 | IO_MASK(R_IRQ_MASK1_RD, ser1_data) | IO_MASK(R_IRQ_MASK1_RD, ser1_ready)
218 #endif
219 #ifdef CONFIG_ETRAX_SERIAL_PORT2
220 | IO_MASK(R_IRQ_MASK1_RD, ser2_data) | IO_MASK(R_IRQ_MASK1_RD, ser2_ready)
221 #endif
222 #ifdef CONFIG_ETRAX_SERIAL_PORT3
223 | IO_MASK(R_IRQ_MASK1_RD, ser3_data) | IO_MASK(R_IRQ_MASK1_RD, ser3_ready)
224 #endif
225 ;
226 unsigned long r_alt_ser_baudrate_shadow = 0;
227
228 /* this is the data for the four serial ports in the etrax100 */
229 /* DMA2(ser2), DMA4(ser3), DMA6(ser0) or DMA8(ser1) */
230 /* R_DMA_CHx_CLR_INTR, R_DMA_CHx_FIRST, R_DMA_CHx_CMD */
231
232 static struct e100_serial rs_table[] = {
233 { .baud = DEF_BAUD,
234 .ioport = (unsigned char *)R_SERIAL0_CTRL,
235 .irq = 1U << 12, /* uses DMA 6 and 7 */
236 .oclrintradr = R_DMA_CH6_CLR_INTR,
237 .ofirstadr = R_DMA_CH6_FIRST,
238 .ocmdadr = R_DMA_CH6_CMD,
239 .ostatusadr = R_DMA_CH6_STATUS,
240 .iclrintradr = R_DMA_CH7_CLR_INTR,
241 .ifirstadr = R_DMA_CH7_FIRST,
242 .icmdadr = R_DMA_CH7_CMD,
243 .idescradr = R_DMA_CH7_DESCR,
244 .rx_ctrl = DEF_RX,
245 .tx_ctrl = DEF_TX,
246 .iseteop = 2,
247 .dma_owner = dma_ser0,
248 .io_if = if_serial_0,
249 #ifdef CONFIG_ETRAX_SERIAL_PORT0
250 .enabled = 1,
251 #ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA6_OUT
252 .dma_out_enabled = 1,
253 .dma_out_nbr = SER0_TX_DMA_NBR,
254 .dma_out_irq_nbr = SER0_DMA_TX_IRQ_NBR,
255 .dma_out_irq_flags = 0,
256 .dma_out_irq_description = "serial 0 dma tr",
257 #else
258 .dma_out_enabled = 0,
259 .dma_out_nbr = UINT_MAX,
260 .dma_out_irq_nbr = 0,
261 .dma_out_irq_flags = 0,
262 .dma_out_irq_description = NULL,
263 #endif
264 #ifdef CONFIG_ETRAX_SERIAL_PORT0_DMA7_IN
265 .dma_in_enabled = 1,
266 .dma_in_nbr = SER0_RX_DMA_NBR,
267 .dma_in_irq_nbr = SER0_DMA_RX_IRQ_NBR,
268 .dma_in_irq_flags = 0,
269 .dma_in_irq_description = "serial 0 dma rec",
270 #else
271 .dma_in_enabled = 0,
272 .dma_in_nbr = UINT_MAX,
273 .dma_in_irq_nbr = 0,
274 .dma_in_irq_flags = 0,
275 .dma_in_irq_description = NULL,
276 #endif
277 #else
278 .enabled = 0,
279 .io_if_description = NULL,
280 .dma_out_enabled = 0,
281 .dma_in_enabled = 0
282 #endif
283
284 }, /* ttyS0 */
285 { .baud = DEF_BAUD,
286 .ioport = (unsigned char *)R_SERIAL1_CTRL,
287 .irq = 1U << 16, /* uses DMA 8 and 9 */
288 .oclrintradr = R_DMA_CH8_CLR_INTR,
289 .ofirstadr = R_DMA_CH8_FIRST,
290 .ocmdadr = R_DMA_CH8_CMD,
291 .ostatusadr = R_DMA_CH8_STATUS,
292 .iclrintradr = R_DMA_CH9_CLR_INTR,
293 .ifirstadr = R_DMA_CH9_FIRST,
294 .icmdadr = R_DMA_CH9_CMD,
295 .idescradr = R_DMA_CH9_DESCR,
296 .rx_ctrl = DEF_RX,
297 .tx_ctrl = DEF_TX,
298 .iseteop = 3,
299 .dma_owner = dma_ser1,
300 .io_if = if_serial_1,
301 #ifdef CONFIG_ETRAX_SERIAL_PORT1
302 .enabled = 1,
303 .io_if_description = "ser1",
304 #ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA8_OUT
305 .dma_out_enabled = 1,
306 .dma_out_nbr = SER1_TX_DMA_NBR,
307 .dma_out_irq_nbr = SER1_DMA_TX_IRQ_NBR,
308 .dma_out_irq_flags = 0,
309 .dma_out_irq_description = "serial 1 dma tr",
310 #else
311 .dma_out_enabled = 0,
312 .dma_out_nbr = UINT_MAX,
313 .dma_out_irq_nbr = 0,
314 .dma_out_irq_flags = 0,
315 .dma_out_irq_description = NULL,
316 #endif
317 #ifdef CONFIG_ETRAX_SERIAL_PORT1_DMA9_IN
318 .dma_in_enabled = 1,
319 .dma_in_nbr = SER1_RX_DMA_NBR,
320 .dma_in_irq_nbr = SER1_DMA_RX_IRQ_NBR,
321 .dma_in_irq_flags = 0,
322 .dma_in_irq_description = "serial 1 dma rec",
323 #else
324 .dma_in_enabled = 0,
325 .dma_in_enabled = 0,
326 .dma_in_nbr = UINT_MAX,
327 .dma_in_irq_nbr = 0,
328 .dma_in_irq_flags = 0,
329 .dma_in_irq_description = NULL,
330 #endif
331 #else
332 .enabled = 0,
333 .io_if_description = NULL,
334 .dma_in_irq_nbr = 0,
335 .dma_out_enabled = 0,
336 .dma_in_enabled = 0
337 #endif
338 }, /* ttyS1 */
339
340 { .baud = DEF_BAUD,
341 .ioport = (unsigned char *)R_SERIAL2_CTRL,
342 .irq = 1U << 4, /* uses DMA 2 and 3 */
343 .oclrintradr = R_DMA_CH2_CLR_INTR,
344 .ofirstadr = R_DMA_CH2_FIRST,
345 .ocmdadr = R_DMA_CH2_CMD,
346 .ostatusadr = R_DMA_CH2_STATUS,
347 .iclrintradr = R_DMA_CH3_CLR_INTR,
348 .ifirstadr = R_DMA_CH3_FIRST,
349 .icmdadr = R_DMA_CH3_CMD,
350 .idescradr = R_DMA_CH3_DESCR,
351 .rx_ctrl = DEF_RX,
352 .tx_ctrl = DEF_TX,
353 .iseteop = 0,
354 .dma_owner = dma_ser2,
355 .io_if = if_serial_2,
356 #ifdef CONFIG_ETRAX_SERIAL_PORT2
357 .enabled = 1,
358 .io_if_description = "ser2",
359 #ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA2_OUT
360 .dma_out_enabled = 1,
361 .dma_out_nbr = SER2_TX_DMA_NBR,
362 .dma_out_irq_nbr = SER2_DMA_TX_IRQ_NBR,
363 .dma_out_irq_flags = 0,
364 .dma_out_irq_description = "serial 2 dma tr",
365 #else
366 .dma_out_enabled = 0,
367 .dma_out_nbr = UINT_MAX,
368 .dma_out_irq_nbr = 0,
369 .dma_out_irq_flags = 0,
370 .dma_out_irq_description = NULL,
371 #endif
372 #ifdef CONFIG_ETRAX_SERIAL_PORT2_DMA3_IN
373 .dma_in_enabled = 1,
374 .dma_in_nbr = SER2_RX_DMA_NBR,
375 .dma_in_irq_nbr = SER2_DMA_RX_IRQ_NBR,
376 .dma_in_irq_flags = 0,
377 .dma_in_irq_description = "serial 2 dma rec",
378 #else
379 .dma_in_enabled = 0,
380 .dma_in_nbr = UINT_MAX,
381 .dma_in_irq_nbr = 0,
382 .dma_in_irq_flags = 0,
383 .dma_in_irq_description = NULL,
384 #endif
385 #else
386 .enabled = 0,
387 .io_if_description = NULL,
388 .dma_out_enabled = 0,
389 .dma_in_enabled = 0
390 #endif
391 }, /* ttyS2 */
392
393 { .baud = DEF_BAUD,
394 .ioport = (unsigned char *)R_SERIAL3_CTRL,
395 .irq = 1U << 8, /* uses DMA 4 and 5 */
396 .oclrintradr = R_DMA_CH4_CLR_INTR,
397 .ofirstadr = R_DMA_CH4_FIRST,
398 .ocmdadr = R_DMA_CH4_CMD,
399 .ostatusadr = R_DMA_CH4_STATUS,
400 .iclrintradr = R_DMA_CH5_CLR_INTR,
401 .ifirstadr = R_DMA_CH5_FIRST,
402 .icmdadr = R_DMA_CH5_CMD,
403 .idescradr = R_DMA_CH5_DESCR,
404 .rx_ctrl = DEF_RX,
405 .tx_ctrl = DEF_TX,
406 .iseteop = 1,
407 .dma_owner = dma_ser3,
408 .io_if = if_serial_3,
409 #ifdef CONFIG_ETRAX_SERIAL_PORT3
410 .enabled = 1,
411 .io_if_description = "ser3",
412 #ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA4_OUT
413 .dma_out_enabled = 1,
414 .dma_out_nbr = SER3_TX_DMA_NBR,
415 .dma_out_irq_nbr = SER3_DMA_TX_IRQ_NBR,
416 .dma_out_irq_flags = 0,
417 .dma_out_irq_description = "serial 3 dma tr",
418 #else
419 .dma_out_enabled = 0,
420 .dma_out_nbr = UINT_MAX,
421 .dma_out_irq_nbr = 0,
422 .dma_out_irq_flags = 0,
423 .dma_out_irq_description = NULL,
424 #endif
425 #ifdef CONFIG_ETRAX_SERIAL_PORT3_DMA5_IN
426 .dma_in_enabled = 1,
427 .dma_in_nbr = SER3_RX_DMA_NBR,
428 .dma_in_irq_nbr = SER3_DMA_RX_IRQ_NBR,
429 .dma_in_irq_flags = 0,
430 .dma_in_irq_description = "serial 3 dma rec",
431 #else
432 .dma_in_enabled = 0,
433 .dma_in_nbr = UINT_MAX,
434 .dma_in_irq_nbr = 0,
435 .dma_in_irq_flags = 0,
436 .dma_in_irq_description = NULL
437 #endif
438 #else
439 .enabled = 0,
440 .io_if_description = NULL,
441 .dma_out_enabled = 0,
442 .dma_in_enabled = 0
443 #endif
444 } /* ttyS3 */
445 };
446
447
448 #define NR_PORTS (sizeof(rs_table)/sizeof(struct e100_serial))
449
450 #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
451 static struct fast_timer fast_timers[NR_PORTS];
452 #endif
453
454 /* RS-485 */
455 #if defined(CONFIG_ETRAX_RS485)
456 #ifdef CONFIG_ETRAX_FAST_TIMER
457 static struct fast_timer fast_timers_rs485[NR_PORTS];
458 #endif
459 #if defined(CONFIG_ETRAX_RS485_ON_PA)
460 static int rs485_pa_bit = CONFIG_ETRAX_RS485_ON_PA_BIT;
461 #endif
462 #endif
463
464 /* Info and macros needed for each ports extra control/status signals. */
465 #define E100_STRUCT_PORT(line, pinname) \
466 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
467 (R_PORT_PA_DATA): ( \
468 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
469 (R_PORT_PB_DATA):&dummy_ser[line]))
470
471 #define E100_STRUCT_SHADOW(line, pinname) \
472 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
473 (&port_pa_data_shadow): ( \
474 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
475 (&port_pb_data_shadow):&dummy_ser[line]))
476 #define E100_STRUCT_MASK(line, pinname) \
477 ((CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT >= 0)? \
478 (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PA_BIT): ( \
479 (CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT >= 0)? \
480 (1<<CONFIG_ETRAX_SER##line##_##pinname##_ON_PB_BIT):DUMMY_##pinname##_MASK))
481
482 #define DUMMY_DTR_MASK 1
483 #define DUMMY_RI_MASK 2
484 #define DUMMY_DSR_MASK 4
485 #define DUMMY_CD_MASK 8
486 static unsigned char dummy_ser[NR_PORTS] = {0xFF, 0xFF, 0xFF,0xFF};
487
488 /* If not all status pins are used or disabled, use mixed mode */
489 #ifdef CONFIG_ETRAX_SERIAL_PORT0
490
491 #define SER0_PA_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PA_BIT+CONFIG_ETRAX_SER0_RI_ON_PA_BIT+CONFIG_ETRAX_SER0_DSR_ON_PA_BIT+CONFIG_ETRAX_SER0_CD_ON_PA_BIT)
492
493 #if SER0_PA_BITSUM != -4
494 # if CONFIG_ETRAX_SER0_DTR_ON_PA_BIT == -1
495 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
496 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
497 # endif
498 # endif
499 # if CONFIG_ETRAX_SER0_RI_ON_PA_BIT == -1
500 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
501 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
502 # endif
503 # endif
504 # if CONFIG_ETRAX_SER0_DSR_ON_PA_BIT == -1
505 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
506 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
507 # endif
508 # endif
509 # if CONFIG_ETRAX_SER0_CD_ON_PA_BIT == -1
510 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
511 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
512 # endif
513 # endif
514 #endif
515
516 #define SER0_PB_BITSUM (CONFIG_ETRAX_SER0_DTR_ON_PB_BIT+CONFIG_ETRAX_SER0_RI_ON_PB_BIT+CONFIG_ETRAX_SER0_DSR_ON_PB_BIT+CONFIG_ETRAX_SER0_CD_ON_PB_BIT)
517
518 #if SER0_PB_BITSUM != -4
519 # if CONFIG_ETRAX_SER0_DTR_ON_PB_BIT == -1
520 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
521 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
522 # endif
523 # endif
524 # if CONFIG_ETRAX_SER0_RI_ON_PB_BIT == -1
525 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
526 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
527 # endif
528 # endif
529 # if CONFIG_ETRAX_SER0_DSR_ON_PB_BIT == -1
530 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
531 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
532 # endif
533 # endif
534 # if CONFIG_ETRAX_SER0_CD_ON_PB_BIT == -1
535 # ifndef CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED
536 # define CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED 1
537 # endif
538 # endif
539 #endif
540
541 #endif /* PORT0 */
542
543
544 #ifdef CONFIG_ETRAX_SERIAL_PORT1
545
546 #define SER1_PA_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PA_BIT+CONFIG_ETRAX_SER1_RI_ON_PA_BIT+CONFIG_ETRAX_SER1_DSR_ON_PA_BIT+CONFIG_ETRAX_SER1_CD_ON_PA_BIT)
547
548 #if SER1_PA_BITSUM != -4
549 # if CONFIG_ETRAX_SER1_DTR_ON_PA_BIT == -1
550 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
551 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
552 # endif
553 # endif
554 # if CONFIG_ETRAX_SER1_RI_ON_PA_BIT == -1
555 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
556 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
557 # endif
558 # endif
559 # if CONFIG_ETRAX_SER1_DSR_ON_PA_BIT == -1
560 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
561 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
562 # endif
563 # endif
564 # if CONFIG_ETRAX_SER1_CD_ON_PA_BIT == -1
565 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
566 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
567 # endif
568 # endif
569 #endif
570
571 #define SER1_PB_BITSUM (CONFIG_ETRAX_SER1_DTR_ON_PB_BIT+CONFIG_ETRAX_SER1_RI_ON_PB_BIT+CONFIG_ETRAX_SER1_DSR_ON_PB_BIT+CONFIG_ETRAX_SER1_CD_ON_PB_BIT)
572
573 #if SER1_PB_BITSUM != -4
574 # if CONFIG_ETRAX_SER1_DTR_ON_PB_BIT == -1
575 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
576 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
577 # endif
578 # endif
579 # if CONFIG_ETRAX_SER1_RI_ON_PB_BIT == -1
580 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
581 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
582 # endif
583 # endif
584 # if CONFIG_ETRAX_SER1_DSR_ON_PB_BIT == -1
585 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
586 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
587 # endif
588 # endif
589 # if CONFIG_ETRAX_SER1_CD_ON_PB_BIT == -1
590 # ifndef CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED
591 # define CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED 1
592 # endif
593 # endif
594 #endif
595
596 #endif /* PORT1 */
597
598 #ifdef CONFIG_ETRAX_SERIAL_PORT2
599
600 #define SER2_PA_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PA_BIT+CONFIG_ETRAX_SER2_RI_ON_PA_BIT+CONFIG_ETRAX_SER2_DSR_ON_PA_BIT+CONFIG_ETRAX_SER2_CD_ON_PA_BIT)
601
602 #if SER2_PA_BITSUM != -4
603 # if CONFIG_ETRAX_SER2_DTR_ON_PA_BIT == -1
604 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
605 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
606 # endif
607 # endif
608 # if CONFIG_ETRAX_SER2_RI_ON_PA_BIT == -1
609 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
610 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
611 # endif
612 # endif
613 # if CONFIG_ETRAX_SER2_DSR_ON_PA_BIT == -1
614 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
615 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
616 # endif
617 # endif
618 # if CONFIG_ETRAX_SER2_CD_ON_PA_BIT == -1
619 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
620 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
621 # endif
622 # endif
623 #endif
624
625 #define SER2_PB_BITSUM (CONFIG_ETRAX_SER2_DTR_ON_PB_BIT+CONFIG_ETRAX_SER2_RI_ON_PB_BIT+CONFIG_ETRAX_SER2_DSR_ON_PB_BIT+CONFIG_ETRAX_SER2_CD_ON_PB_BIT)
626
627 #if SER2_PB_BITSUM != -4
628 # if CONFIG_ETRAX_SER2_DTR_ON_PB_BIT == -1
629 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
630 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
631 # endif
632 # endif
633 # if CONFIG_ETRAX_SER2_RI_ON_PB_BIT == -1
634 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
635 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
636 # endif
637 # endif
638 # if CONFIG_ETRAX_SER2_DSR_ON_PB_BIT == -1
639 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
640 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
641 # endif
642 # endif
643 # if CONFIG_ETRAX_SER2_CD_ON_PB_BIT == -1
644 # ifndef CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED
645 # define CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED 1
646 # endif
647 # endif
648 #endif
649
650 #endif /* PORT2 */
651
652 #ifdef CONFIG_ETRAX_SERIAL_PORT3
653
654 #define SER3_PA_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PA_BIT+CONFIG_ETRAX_SER3_RI_ON_PA_BIT+CONFIG_ETRAX_SER3_DSR_ON_PA_BIT+CONFIG_ETRAX_SER3_CD_ON_PA_BIT)
655
656 #if SER3_PA_BITSUM != -4
657 # if CONFIG_ETRAX_SER3_DTR_ON_PA_BIT == -1
658 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
659 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
660 # endif
661 # endif
662 # if CONFIG_ETRAX_SER3_RI_ON_PA_BIT == -1
663 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
664 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
665 # endif
666 # endif
667 # if CONFIG_ETRAX_SER3_DSR_ON_PA_BIT == -1
668 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
669 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
670 # endif
671 # endif
672 # if CONFIG_ETRAX_SER3_CD_ON_PA_BIT == -1
673 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
674 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
675 # endif
676 # endif
677 #endif
678
679 #define SER3_PB_BITSUM (CONFIG_ETRAX_SER3_DTR_ON_PB_BIT+CONFIG_ETRAX_SER3_RI_ON_PB_BIT+CONFIG_ETRAX_SER3_DSR_ON_PB_BIT+CONFIG_ETRAX_SER3_CD_ON_PB_BIT)
680
681 #if SER3_PB_BITSUM != -4
682 # if CONFIG_ETRAX_SER3_DTR_ON_PB_BIT == -1
683 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
684 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
685 # endif
686 # endif
687 # if CONFIG_ETRAX_SER3_RI_ON_PB_BIT == -1
688 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
689 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
690 # endif
691 # endif
692 # if CONFIG_ETRAX_SER3_DSR_ON_PB_BIT == -1
693 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
694 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
695 # endif
696 # endif
697 # if CONFIG_ETRAX_SER3_CD_ON_PB_BIT == -1
698 # ifndef CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED
699 # define CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED 1
700 # endif
701 # endif
702 #endif
703
704 #endif /* PORT3 */
705
706
707 #if defined(CONFIG_ETRAX_SER0_DTR_RI_DSR_CD_MIXED) || \
708 defined(CONFIG_ETRAX_SER1_DTR_RI_DSR_CD_MIXED) || \
709 defined(CONFIG_ETRAX_SER2_DTR_RI_DSR_CD_MIXED) || \
710 defined(CONFIG_ETRAX_SER3_DTR_RI_DSR_CD_MIXED)
711 #define ETRAX_SERX_DTR_RI_DSR_CD_MIXED
712 #endif
713
714 #ifdef ETRAX_SERX_DTR_RI_DSR_CD_MIXED
715 /* The pins can be mixed on PA and PB */
716 #define CONTROL_PINS_PORT_NOT_USED(line) \
717 &dummy_ser[line], &dummy_ser[line], \
718 &dummy_ser[line], &dummy_ser[line], \
719 &dummy_ser[line], &dummy_ser[line], \
720 &dummy_ser[line], &dummy_ser[line], \
721 DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
722
723
724 struct control_pins
725 {
726 volatile unsigned char *dtr_port;
727 unsigned char *dtr_shadow;
728 volatile unsigned char *ri_port;
729 unsigned char *ri_shadow;
730 volatile unsigned char *dsr_port;
731 unsigned char *dsr_shadow;
732 volatile unsigned char *cd_port;
733 unsigned char *cd_shadow;
734
735 unsigned char dtr_mask;
736 unsigned char ri_mask;
737 unsigned char dsr_mask;
738 unsigned char cd_mask;
739 };
740
741 static const struct control_pins e100_modem_pins[NR_PORTS] =
742 {
743 /* Ser 0 */
744 {
745 #ifdef CONFIG_ETRAX_SERIAL_PORT0
746 E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
747 E100_STRUCT_PORT(0,RI), E100_STRUCT_SHADOW(0,RI),
748 E100_STRUCT_PORT(0,DSR), E100_STRUCT_SHADOW(0,DSR),
749 E100_STRUCT_PORT(0,CD), E100_STRUCT_SHADOW(0,CD),
750 E100_STRUCT_MASK(0,DTR),
751 E100_STRUCT_MASK(0,RI),
752 E100_STRUCT_MASK(0,DSR),
753 E100_STRUCT_MASK(0,CD)
754 #else
755 CONTROL_PINS_PORT_NOT_USED(0)
756 #endif
757 },
758
759 /* Ser 1 */
760 {
761 #ifdef CONFIG_ETRAX_SERIAL_PORT1
762 E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
763 E100_STRUCT_PORT(1,RI), E100_STRUCT_SHADOW(1,RI),
764 E100_STRUCT_PORT(1,DSR), E100_STRUCT_SHADOW(1,DSR),
765 E100_STRUCT_PORT(1,CD), E100_STRUCT_SHADOW(1,CD),
766 E100_STRUCT_MASK(1,DTR),
767 E100_STRUCT_MASK(1,RI),
768 E100_STRUCT_MASK(1,DSR),
769 E100_STRUCT_MASK(1,CD)
770 #else
771 CONTROL_PINS_PORT_NOT_USED(1)
772 #endif
773 },
774
775 /* Ser 2 */
776 {
777 #ifdef CONFIG_ETRAX_SERIAL_PORT2
778 E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
779 E100_STRUCT_PORT(2,RI), E100_STRUCT_SHADOW(2,RI),
780 E100_STRUCT_PORT(2,DSR), E100_STRUCT_SHADOW(2,DSR),
781 E100_STRUCT_PORT(2,CD), E100_STRUCT_SHADOW(2,CD),
782 E100_STRUCT_MASK(2,DTR),
783 E100_STRUCT_MASK(2,RI),
784 E100_STRUCT_MASK(2,DSR),
785 E100_STRUCT_MASK(2,CD)
786 #else
787 CONTROL_PINS_PORT_NOT_USED(2)
788 #endif
789 },
790
791 /* Ser 3 */
792 {
793 #ifdef CONFIG_ETRAX_SERIAL_PORT3
794 E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
795 E100_STRUCT_PORT(3,RI), E100_STRUCT_SHADOW(3,RI),
796 E100_STRUCT_PORT(3,DSR), E100_STRUCT_SHADOW(3,DSR),
797 E100_STRUCT_PORT(3,CD), E100_STRUCT_SHADOW(3,CD),
798 E100_STRUCT_MASK(3,DTR),
799 E100_STRUCT_MASK(3,RI),
800 E100_STRUCT_MASK(3,DSR),
801 E100_STRUCT_MASK(3,CD)
802 #else
803 CONTROL_PINS_PORT_NOT_USED(3)
804 #endif
805 }
806 };
807 #else /* ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
808
809 /* All pins are on either PA or PB for each serial port */
810 #define CONTROL_PINS_PORT_NOT_USED(line) \
811 &dummy_ser[line], &dummy_ser[line], \
812 DUMMY_DTR_MASK, DUMMY_RI_MASK, DUMMY_DSR_MASK, DUMMY_CD_MASK
813
814
815 struct control_pins
816 {
817 volatile unsigned char *port;
818 unsigned char *shadow;
819
820 unsigned char dtr_mask;
821 unsigned char ri_mask;
822 unsigned char dsr_mask;
823 unsigned char cd_mask;
824 };
825
826 #define dtr_port port
827 #define dtr_shadow shadow
828 #define ri_port port
829 #define ri_shadow shadow
830 #define dsr_port port
831 #define dsr_shadow shadow
832 #define cd_port port
833 #define cd_shadow shadow
834
835 static const struct control_pins e100_modem_pins[NR_PORTS] =
836 {
837 /* Ser 0 */
838 {
839 #ifdef CONFIG_ETRAX_SERIAL_PORT0
840 E100_STRUCT_PORT(0,DTR), E100_STRUCT_SHADOW(0,DTR),
841 E100_STRUCT_MASK(0,DTR),
842 E100_STRUCT_MASK(0,RI),
843 E100_STRUCT_MASK(0,DSR),
844 E100_STRUCT_MASK(0,CD)
845 #else
846 CONTROL_PINS_PORT_NOT_USED(0)
847 #endif
848 },
849
850 /* Ser 1 */
851 {
852 #ifdef CONFIG_ETRAX_SERIAL_PORT1
853 E100_STRUCT_PORT(1,DTR), E100_STRUCT_SHADOW(1,DTR),
854 E100_STRUCT_MASK(1,DTR),
855 E100_STRUCT_MASK(1,RI),
856 E100_STRUCT_MASK(1,DSR),
857 E100_STRUCT_MASK(1,CD)
858 #else
859 CONTROL_PINS_PORT_NOT_USED(1)
860 #endif
861 },
862
863 /* Ser 2 */
864 {
865 #ifdef CONFIG_ETRAX_SERIAL_PORT2
866 E100_STRUCT_PORT(2,DTR), E100_STRUCT_SHADOW(2,DTR),
867 E100_STRUCT_MASK(2,DTR),
868 E100_STRUCT_MASK(2,RI),
869 E100_STRUCT_MASK(2,DSR),
870 E100_STRUCT_MASK(2,CD)
871 #else
872 CONTROL_PINS_PORT_NOT_USED(2)
873 #endif
874 },
875
876 /* Ser 3 */
877 {
878 #ifdef CONFIG_ETRAX_SERIAL_PORT3
879 E100_STRUCT_PORT(3,DTR), E100_STRUCT_SHADOW(3,DTR),
880 E100_STRUCT_MASK(3,DTR),
881 E100_STRUCT_MASK(3,RI),
882 E100_STRUCT_MASK(3,DSR),
883 E100_STRUCT_MASK(3,CD)
884 #else
885 CONTROL_PINS_PORT_NOT_USED(3)
886 #endif
887 }
888 };
889 #endif /* !ETRAX_SERX_DTR_RI_DSR_CD_MIXED */
890
891 #define E100_RTS_MASK 0x20
892 #define E100_CTS_MASK 0x40
893
894 /* All serial port signals are active low:
895 * active = 0 -> 3.3V to RS-232 driver -> -12V on RS-232 level
896 * inactive = 1 -> 0V to RS-232 driver -> +12V on RS-232 level
897 *
898 * These macros returns the pin value: 0=0V, >=1 = 3.3V on ETRAX chip
899 */
900
901 /* Output */
902 #define E100_RTS_GET(info) ((info)->rx_ctrl & E100_RTS_MASK)
903 /* Input */
904 #define E100_CTS_GET(info) ((info)->ioport[REG_STATUS] & E100_CTS_MASK)
905
906 /* These are typically PA or PB and 0 means 0V, 1 means 3.3V */
907 /* Is an output */
908 #define E100_DTR_GET(info) ((*e100_modem_pins[(info)->line].dtr_shadow) & e100_modem_pins[(info)->line].dtr_mask)
909
910 /* Normally inputs */
911 #define E100_RI_GET(info) ((*e100_modem_pins[(info)->line].ri_port) & e100_modem_pins[(info)->line].ri_mask)
912 #define E100_CD_GET(info) ((*e100_modem_pins[(info)->line].cd_port) & e100_modem_pins[(info)->line].cd_mask)
913
914 /* Input */
915 #define E100_DSR_GET(info) ((*e100_modem_pins[(info)->line].dsr_port) & e100_modem_pins[(info)->line].dsr_mask)
916
917 /* Calculate the chartime depending on baudrate, numbor of bits etc. */
918 static void update_char_time(struct e100_serial * info)
919 {
920 tcflag_t cflags = info->port.tty->termios.c_cflag;
921 int bits;
922
923 /* calc. number of bits / data byte */
924 /* databits + startbit and 1 stopbit */
925 if ((cflags & CSIZE) == CS7)
926 bits = 9;
927 else
928 bits = 10;
929
930 if (cflags & CSTOPB) /* 2 stopbits ? */
931 bits++;
932
933 if (cflags & PARENB) /* parity bit ? */
934 bits++;
935
936 /* calc timeout */
937 info->char_time_usec = ((bits * 1000000) / info->baud) + 1;
938 info->flush_time_usec = 4*info->char_time_usec;
939 if (info->flush_time_usec < MIN_FLUSH_TIME_USEC)
940 info->flush_time_usec = MIN_FLUSH_TIME_USEC;
941
942 }
943
944 /*
945 * This function maps from the Bxxxx defines in asm/termbits.h into real
946 * baud rates.
947 */
948
949 static int
950 cflag_to_baud(unsigned int cflag)
951 {
952 static int baud_table[] = {
953 0, 50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400,
954 4800, 9600, 19200, 38400 };
955
956 static int ext_baud_table[] = {
957 0, 57600, 115200, 230400, 460800, 921600, 1843200, 6250000,
958 0, 0, 0, 0, 0, 0, 0, 0 };
959
960 if (cflag & CBAUDEX)
961 return ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
962 else
963 return baud_table[cflag & CBAUD];
964 }
965
966 /* and this maps to an etrax100 hardware baud constant */
967
968 static unsigned char
969 cflag_to_etrax_baud(unsigned int cflag)
970 {
971 char retval;
972
973 static char baud_table[] = {
974 -1, -1, -1, -1, -1, -1, -1, 0, 1, 2, -1, 3, 4, 5, 6, 7 };
975
976 static char ext_baud_table[] = {
977 -1, 8, 9, 10, 11, 12, 13, 14, -1, -1, -1, -1, -1, -1, -1, -1 };
978
979 if (cflag & CBAUDEX)
980 retval = ext_baud_table[(cflag & CBAUD) & ~CBAUDEX];
981 else
982 retval = baud_table[cflag & CBAUD];
983
984 if (retval < 0) {
985 printk(KERN_WARNING "serdriver tried setting invalid baud rate, flags %x.\n", cflag);
986 retval = 5; /* choose default 9600 instead */
987 }
988
989 return retval | (retval << 4); /* choose same for both TX and RX */
990 }
991
992
993 /* Various static support functions */
994
995 /* Functions to set or clear DTR/RTS on the requested line */
996 /* It is complicated by the fact that RTS is a serial port register, while
997 * DTR might not be implemented in the HW at all, and if it is, it can be on
998 * any general port.
999 */
1000
1001
1002 static inline void
1003 e100_dtr(struct e100_serial *info, int set)
1004 {
1005 unsigned char mask = e100_modem_pins[info->line].dtr_mask;
1006
1007 #ifdef SERIAL_DEBUG_IO
1008 printk("ser%i dtr %i mask: 0x%02X\n", info->line, set, mask);
1009 printk("ser%i shadow before 0x%02X get: %i\n",
1010 info->line, *e100_modem_pins[info->line].dtr_shadow,
1011 E100_DTR_GET(info));
1012 #endif
1013 /* DTR is active low */
1014 {
1015 unsigned long flags;
1016
1017 local_irq_save(flags);
1018 *e100_modem_pins[info->line].dtr_shadow &= ~mask;
1019 *e100_modem_pins[info->line].dtr_shadow |= (set ? 0 : mask);
1020 *e100_modem_pins[info->line].dtr_port = *e100_modem_pins[info->line].dtr_shadow;
1021 local_irq_restore(flags);
1022 }
1023
1024 #ifdef SERIAL_DEBUG_IO
1025 printk("ser%i shadow after 0x%02X get: %i\n",
1026 info->line, *e100_modem_pins[info->line].dtr_shadow,
1027 E100_DTR_GET(info));
1028 #endif
1029 }
1030
1031 /* set = 0 means 3.3V on the pin, bitvalue: 0=active, 1=inactive
1032 * 0=0V , 1=3.3V
1033 */
1034 static inline void
1035 e100_rts(struct e100_serial *info, int set)
1036 {
1037 unsigned long flags;
1038 local_irq_save(flags);
1039 info->rx_ctrl &= ~E100_RTS_MASK;
1040 info->rx_ctrl |= (set ? 0 : E100_RTS_MASK); /* RTS is active low */
1041 info->ioport[REG_REC_CTRL] = info->rx_ctrl;
1042 local_irq_restore(flags);
1043 #ifdef SERIAL_DEBUG_IO
1044 printk("ser%i rts %i\n", info->line, set);
1045 #endif
1046 }
1047
1048
1049 /* If this behaves as a modem, RI and CD is an output */
1050 static inline void
1051 e100_ri_out(struct e100_serial *info, int set)
1052 {
1053 /* RI is active low */
1054 {
1055 unsigned char mask = e100_modem_pins[info->line].ri_mask;
1056 unsigned long flags;
1057
1058 local_irq_save(flags);
1059 *e100_modem_pins[info->line].ri_shadow &= ~mask;
1060 *e100_modem_pins[info->line].ri_shadow |= (set ? 0 : mask);
1061 *e100_modem_pins[info->line].ri_port = *e100_modem_pins[info->line].ri_shadow;
1062 local_irq_restore(flags);
1063 }
1064 }
1065 static inline void
1066 e100_cd_out(struct e100_serial *info, int set)
1067 {
1068 /* CD is active low */
1069 {
1070 unsigned char mask = e100_modem_pins[info->line].cd_mask;
1071 unsigned long flags;
1072
1073 local_irq_save(flags);
1074 *e100_modem_pins[info->line].cd_shadow &= ~mask;
1075 *e100_modem_pins[info->line].cd_shadow |= (set ? 0 : mask);
1076 *e100_modem_pins[info->line].cd_port = *e100_modem_pins[info->line].cd_shadow;
1077 local_irq_restore(flags);
1078 }
1079 }
1080
1081 static inline void
1082 e100_disable_rx(struct e100_serial *info)
1083 {
1084 /* disable the receiver */
1085 info->ioport[REG_REC_CTRL] =
1086 (info->rx_ctrl &= ~IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
1087 }
1088
1089 static inline void
1090 e100_enable_rx(struct e100_serial *info)
1091 {
1092 /* enable the receiver */
1093 info->ioport[REG_REC_CTRL] =
1094 (info->rx_ctrl |= IO_MASK(R_SERIAL0_REC_CTRL, rec_enable));
1095 }
1096
1097 /* the rx DMA uses both the dma_descr and the dma_eop interrupts */
1098
1099 static inline void
1100 e100_disable_rxdma_irq(struct e100_serial *info)
1101 {
1102 #ifdef SERIAL_DEBUG_INTR
1103 printk("rxdma_irq(%d): 0\n",info->line);
1104 #endif
1105 DINTR1(DEBUG_LOG(info->line,"IRQ disable_rxdma_irq %i\n", info->line));
1106 *R_IRQ_MASK2_CLR = (info->irq << 2) | (info->irq << 3);
1107 }
1108
1109 static inline void
1110 e100_enable_rxdma_irq(struct e100_serial *info)
1111 {
1112 #ifdef SERIAL_DEBUG_INTR
1113 printk("rxdma_irq(%d): 1\n",info->line);
1114 #endif
1115 DINTR1(DEBUG_LOG(info->line,"IRQ enable_rxdma_irq %i\n", info->line));
1116 *R_IRQ_MASK2_SET = (info->irq << 2) | (info->irq << 3);
1117 }
1118
1119 /* the tx DMA uses only dma_descr interrupt */
1120
1121 static void e100_disable_txdma_irq(struct e100_serial *info)
1122 {
1123 #ifdef SERIAL_DEBUG_INTR
1124 printk("txdma_irq(%d): 0\n",info->line);
1125 #endif
1126 DINTR1(DEBUG_LOG(info->line,"IRQ disable_txdma_irq %i\n", info->line));
1127 *R_IRQ_MASK2_CLR = info->irq;
1128 }
1129
1130 static void e100_enable_txdma_irq(struct e100_serial *info)
1131 {
1132 #ifdef SERIAL_DEBUG_INTR
1133 printk("txdma_irq(%d): 1\n",info->line);
1134 #endif
1135 DINTR1(DEBUG_LOG(info->line,"IRQ enable_txdma_irq %i\n", info->line));
1136 *R_IRQ_MASK2_SET = info->irq;
1137 }
1138
1139 static void e100_disable_txdma_channel(struct e100_serial *info)
1140 {
1141 unsigned long flags;
1142
1143 /* Disable output DMA channel for the serial port in question
1144 * ( set to something other than serialX)
1145 */
1146 local_irq_save(flags);
1147 DFLOW(DEBUG_LOG(info->line, "disable_txdma_channel %i\n", info->line));
1148 if (info->line == 0) {
1149 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma6)) ==
1150 IO_STATE(R_GEN_CONFIG, dma6, serial0)) {
1151 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
1152 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, unused);
1153 }
1154 } else if (info->line == 1) {
1155 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma8)) ==
1156 IO_STATE(R_GEN_CONFIG, dma8, serial1)) {
1157 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
1158 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, usb);
1159 }
1160 } else if (info->line == 2) {
1161 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma2)) ==
1162 IO_STATE(R_GEN_CONFIG, dma2, serial2)) {
1163 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
1164 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, par0);
1165 }
1166 } else if (info->line == 3) {
1167 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma4)) ==
1168 IO_STATE(R_GEN_CONFIG, dma4, serial3)) {
1169 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
1170 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, par1);
1171 }
1172 }
1173 *R_GEN_CONFIG = genconfig_shadow;
1174 local_irq_restore(flags);
1175 }
1176
1177
1178 static void e100_enable_txdma_channel(struct e100_serial *info)
1179 {
1180 unsigned long flags;
1181
1182 local_irq_save(flags);
1183 DFLOW(DEBUG_LOG(info->line, "enable_txdma_channel %i\n", info->line));
1184 /* Enable output DMA channel for the serial port in question */
1185 if (info->line == 0) {
1186 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma6);
1187 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma6, serial0);
1188 } else if (info->line == 1) {
1189 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma8);
1190 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma8, serial1);
1191 } else if (info->line == 2) {
1192 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma2);
1193 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma2, serial2);
1194 } else if (info->line == 3) {
1195 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma4);
1196 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma4, serial3);
1197 }
1198 *R_GEN_CONFIG = genconfig_shadow;
1199 local_irq_restore(flags);
1200 }
1201
1202 static void e100_disable_rxdma_channel(struct e100_serial *info)
1203 {
1204 unsigned long flags;
1205
1206 /* Disable input DMA channel for the serial port in question
1207 * ( set to something other than serialX)
1208 */
1209 local_irq_save(flags);
1210 if (info->line == 0) {
1211 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma7)) ==
1212 IO_STATE(R_GEN_CONFIG, dma7, serial0)) {
1213 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
1214 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, unused);
1215 }
1216 } else if (info->line == 1) {
1217 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma9)) ==
1218 IO_STATE(R_GEN_CONFIG, dma9, serial1)) {
1219 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
1220 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, usb);
1221 }
1222 } else if (info->line == 2) {
1223 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma3)) ==
1224 IO_STATE(R_GEN_CONFIG, dma3, serial2)) {
1225 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
1226 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, par0);
1227 }
1228 } else if (info->line == 3) {
1229 if ((genconfig_shadow & IO_MASK(R_GEN_CONFIG, dma5)) ==
1230 IO_STATE(R_GEN_CONFIG, dma5, serial3)) {
1231 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
1232 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, par1);
1233 }
1234 }
1235 *R_GEN_CONFIG = genconfig_shadow;
1236 local_irq_restore(flags);
1237 }
1238
1239
1240 static void e100_enable_rxdma_channel(struct e100_serial *info)
1241 {
1242 unsigned long flags;
1243
1244 local_irq_save(flags);
1245 /* Enable input DMA channel for the serial port in question */
1246 if (info->line == 0) {
1247 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma7);
1248 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma7, serial0);
1249 } else if (info->line == 1) {
1250 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma9);
1251 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma9, serial1);
1252 } else if (info->line == 2) {
1253 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma3);
1254 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma3, serial2);
1255 } else if (info->line == 3) {
1256 genconfig_shadow &= ~IO_MASK(R_GEN_CONFIG, dma5);
1257 genconfig_shadow |= IO_STATE(R_GEN_CONFIG, dma5, serial3);
1258 }
1259 *R_GEN_CONFIG = genconfig_shadow;
1260 local_irq_restore(flags);
1261 }
1262
1263 #ifdef SERIAL_HANDLE_EARLY_ERRORS
1264 /* in order to detect and fix errors on the first byte
1265 we have to use the serial interrupts as well. */
1266
1267 static inline void
1268 e100_disable_serial_data_irq(struct e100_serial *info)
1269 {
1270 #ifdef SERIAL_DEBUG_INTR
1271 printk("ser_irq(%d): 0\n",info->line);
1272 #endif
1273 DINTR1(DEBUG_LOG(info->line,"IRQ disable data_irq %i\n", info->line));
1274 *R_IRQ_MASK1_CLR = (1U << (8+2*info->line));
1275 }
1276
1277 static inline void
1278 e100_enable_serial_data_irq(struct e100_serial *info)
1279 {
1280 #ifdef SERIAL_DEBUG_INTR
1281 printk("ser_irq(%d): 1\n",info->line);
1282 printk("**** %d = %d\n",
1283 (8+2*info->line),
1284 (1U << (8+2*info->line)));
1285 #endif
1286 DINTR1(DEBUG_LOG(info->line,"IRQ enable data_irq %i\n", info->line));
1287 *R_IRQ_MASK1_SET = (1U << (8+2*info->line));
1288 }
1289 #endif
1290
1291 static inline void
1292 e100_disable_serial_tx_ready_irq(struct e100_serial *info)
1293 {
1294 #ifdef SERIAL_DEBUG_INTR
1295 printk("ser_tx_irq(%d): 0\n",info->line);
1296 #endif
1297 DINTR1(DEBUG_LOG(info->line,"IRQ disable ready_irq %i\n", info->line));
1298 *R_IRQ_MASK1_CLR = (1U << (8+1+2*info->line));
1299 }
1300
1301 static inline void
1302 e100_enable_serial_tx_ready_irq(struct e100_serial *info)
1303 {
1304 #ifdef SERIAL_DEBUG_INTR
1305 printk("ser_tx_irq(%d): 1\n",info->line);
1306 printk("**** %d = %d\n",
1307 (8+1+2*info->line),
1308 (1U << (8+1+2*info->line)));
1309 #endif
1310 DINTR2(DEBUG_LOG(info->line,"IRQ enable ready_irq %i\n", info->line));
1311 *R_IRQ_MASK1_SET = (1U << (8+1+2*info->line));
1312 }
1313
1314 static inline void e100_enable_rx_irq(struct e100_serial *info)
1315 {
1316 if (info->uses_dma_in)
1317 e100_enable_rxdma_irq(info);
1318 else
1319 e100_enable_serial_data_irq(info);
1320 }
1321 static inline void e100_disable_rx_irq(struct e100_serial *info)
1322 {
1323 if (info->uses_dma_in)
1324 e100_disable_rxdma_irq(info);
1325 else
1326 e100_disable_serial_data_irq(info);
1327 }
1328
1329 #if defined(CONFIG_ETRAX_RS485)
1330 /* Enable RS-485 mode on selected port. This is UGLY. */
1331 static int
1332 e100_enable_rs485(struct tty_struct *tty, struct serial_rs485 *r)
1333 {
1334 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
1335
1336 #if defined(CONFIG_ETRAX_RS485_ON_PA)
1337 *R_PORT_PA_DATA = port_pa_data_shadow |= (1 << rs485_pa_bit);
1338 #endif
1339
1340 info->rs485 = *r;
1341
1342 /* Maximum delay before RTS equal to 1000 */
1343 if (info->rs485.delay_rts_before_send >= 1000)
1344 info->rs485.delay_rts_before_send = 1000;
1345
1346 /* printk("rts: on send = %i, after = %i, enabled = %i",
1347 info->rs485.rts_on_send,
1348 info->rs485.rts_after_sent,
1349 info->rs485.enabled
1350 );
1351 */
1352 return 0;
1353 }
1354
1355 static int
1356 e100_write_rs485(struct tty_struct *tty,
1357 const unsigned char *buf, int count)
1358 {
1359 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
1360 int old_value = (info->rs485.flags) & SER_RS485_ENABLED;
1361
1362 /* rs485 is always implicitly enabled if we're using the ioctl()
1363 * but it doesn't have to be set in the serial_rs485
1364 * (to be backward compatible with old apps)
1365 * So we store, set and restore it.
1366 */
1367 info->rs485.flags |= SER_RS485_ENABLED;
1368 /* rs_write now deals with RS485 if enabled */
1369 count = rs_write(tty, buf, count);
1370 if (!old_value)
1371 info->rs485.flags &= ~(SER_RS485_ENABLED);
1372 return count;
1373 }
1374
1375 #ifdef CONFIG_ETRAX_FAST_TIMER
1376 /* Timer function to toggle RTS when using FAST_TIMER */
1377 static void rs485_toggle_rts_timer_function(unsigned long data)
1378 {
1379 struct e100_serial *info = (struct e100_serial *)data;
1380
1381 fast_timers_rs485[info->line].function = NULL;
1382 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND));
1383 #if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
1384 e100_enable_rx(info);
1385 e100_enable_rx_irq(info);
1386 #endif
1387 }
1388 #endif
1389 #endif /* CONFIG_ETRAX_RS485 */
1390
1391 /*
1392 * ------------------------------------------------------------
1393 * rs_stop() and rs_start()
1394 *
1395 * This routines are called before setting or resetting tty->stopped.
1396 * They enable or disable transmitter using the XOFF registers, as necessary.
1397 * ------------------------------------------------------------
1398 */
1399
1400 static void
1401 rs_stop(struct tty_struct *tty)
1402 {
1403 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1404 if (info) {
1405 unsigned long flags;
1406 unsigned long xoff;
1407
1408 local_irq_save(flags);
1409 DFLOW(DEBUG_LOG(info->line, "XOFF rs_stop xmit %i\n",
1410 CIRC_CNT(info->xmit.head,
1411 info->xmit.tail,SERIAL_XMIT_SIZE)));
1412
1413 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char,
1414 STOP_CHAR(info->port.tty));
1415 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, stop);
1416 if (tty->termios.c_iflag & IXON ) {
1417 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1418 }
1419
1420 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
1421 local_irq_restore(flags);
1422 }
1423 }
1424
1425 static void
1426 rs_start(struct tty_struct *tty)
1427 {
1428 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
1429 if (info) {
1430 unsigned long flags;
1431 unsigned long xoff;
1432
1433 local_irq_save(flags);
1434 DFLOW(DEBUG_LOG(info->line, "XOFF rs_start xmit %i\n",
1435 CIRC_CNT(info->xmit.head,
1436 info->xmit.tail,SERIAL_XMIT_SIZE)));
1437 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(tty));
1438 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
1439 if (tty->termios.c_iflag & IXON ) {
1440 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
1441 }
1442
1443 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
1444 if (!info->uses_dma_out &&
1445 info->xmit.head != info->xmit.tail && info->xmit.buf)
1446 e100_enable_serial_tx_ready_irq(info);
1447
1448 local_irq_restore(flags);
1449 }
1450 }
1451
1452 /*
1453 * ----------------------------------------------------------------------
1454 *
1455 * Here starts the interrupt handling routines. All of the following
1456 * subroutines are declared as inline and are folded into
1457 * rs_interrupt(). They were separated out for readability's sake.
1458 *
1459 * Note: rs_interrupt() is a "fast" interrupt, which means that it
1460 * runs with interrupts turned off. People who may want to modify
1461 * rs_interrupt() should try to keep the interrupt handler as fast as
1462 * possible. After you are done making modifications, it is not a bad
1463 * idea to do:
1464 *
1465 * gcc -S -DKERNEL -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer serial.c
1466 *
1467 * and look at the resulting assemble code in serial.s.
1468 *
1469 * - Ted Ts'o (tytso@mit.edu), 7-Mar-93
1470 * -----------------------------------------------------------------------
1471 */
1472
1473 /*
1474 * This routine is used by the interrupt handler to schedule
1475 * processing in the software interrupt portion of the driver.
1476 */
1477 static void rs_sched_event(struct e100_serial *info, int event)
1478 {
1479 if (info->event & (1 << event))
1480 return;
1481 info->event |= 1 << event;
1482 schedule_work(&info->work);
1483 }
1484
1485 /* The output DMA channel is free - use it to send as many chars as possible
1486 * NOTES:
1487 * We don't pay attention to info->x_char, which means if the TTY wants to
1488 * use XON/XOFF it will set info->x_char but we won't send any X char!
1489 *
1490 * To implement this, we'd just start a DMA send of 1 byte pointing at a
1491 * buffer containing the X char, and skip updating xmit. We'd also have to
1492 * check if the last sent char was the X char when we enter this function
1493 * the next time, to avoid updating xmit with the sent X value.
1494 */
1495
1496 static void
1497 transmit_chars_dma(struct e100_serial *info)
1498 {
1499 unsigned int c, sentl;
1500 struct etrax_dma_descr *descr;
1501
1502 /* acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
1503 *info->oclrintradr =
1504 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
1505 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
1506
1507 #ifdef SERIAL_DEBUG_INTR
1508 if (info->line == SERIAL_DEBUG_LINE)
1509 printk("tc\n");
1510 #endif
1511 if (!info->tr_running) {
1512 /* weirdo... we shouldn't get here! */
1513 printk(KERN_WARNING "Achtung: transmit_chars_dma with !tr_running\n");
1514 return;
1515 }
1516
1517 descr = &info->tr_descr;
1518
1519 /* first get the amount of bytes sent during the last DMA transfer,
1520 and update xmit accordingly */
1521
1522 /* if the stop bit was not set, all data has been sent */
1523 if (!(descr->status & d_stop)) {
1524 sentl = descr->sw_len;
1525 } else
1526 /* otherwise we find the amount of data sent here */
1527 sentl = descr->hw_len;
1528
1529 DFLOW(DEBUG_LOG(info->line, "TX %i done\n", sentl));
1530
1531 /* update stats */
1532 info->icount.tx += sentl;
1533
1534 /* update xmit buffer */
1535 info->xmit.tail = (info->xmit.tail + sentl) & (SERIAL_XMIT_SIZE - 1);
1536
1537 /* if there is only a few chars left in the buf, wake up the blocked
1538 write if any */
1539 if (CIRC_CNT(info->xmit.head,
1540 info->xmit.tail,
1541 SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
1542 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
1543
1544 /* find out the largest amount of consecutive bytes we want to send now */
1545
1546 c = CIRC_CNT_TO_END(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
1547
1548 /* Don't send all in one DMA transfer - divide it so we wake up
1549 * application before all is sent
1550 */
1551
1552 if (c >= 4*WAKEUP_CHARS)
1553 c = c/2;
1554
1555 if (c <= 0) {
1556 /* our job here is done, don't schedule any new DMA transfer */
1557 info->tr_running = 0;
1558
1559 #if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
1560 if (info->rs485.flags & SER_RS485_ENABLED) {
1561 /* Set a short timer to toggle RTS */
1562 start_one_shot_timer(&fast_timers_rs485[info->line],
1563 rs485_toggle_rts_timer_function,
1564 (unsigned long)info,
1565 info->char_time_usec*2,
1566 "RS-485");
1567 }
1568 #endif /* RS485 */
1569 return;
1570 }
1571
1572 /* ok we can schedule a dma send of c chars starting at info->xmit.tail */
1573 /* set up the descriptor correctly for output */
1574 DFLOW(DEBUG_LOG(info->line, "TX %i\n", c));
1575 descr->ctrl = d_int | d_eol | d_wait; /* Wait needed for tty_wait_until_sent() */
1576 descr->sw_len = c;
1577 descr->buf = virt_to_phys(info->xmit.buf + info->xmit.tail);
1578 descr->status = 0;
1579
1580 *info->ofirstadr = virt_to_phys(descr); /* write to R_DMAx_FIRST */
1581 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
1582
1583 /* DMA is now running (hopefully) */
1584 } /* transmit_chars_dma */
1585
1586 static void
1587 start_transmit(struct e100_serial *info)
1588 {
1589 #if 0
1590 if (info->line == SERIAL_DEBUG_LINE)
1591 printk("x\n");
1592 #endif
1593
1594 info->tr_descr.sw_len = 0;
1595 info->tr_descr.hw_len = 0;
1596 info->tr_descr.status = 0;
1597 info->tr_running = 1;
1598 if (info->uses_dma_out)
1599 transmit_chars_dma(info);
1600 else
1601 e100_enable_serial_tx_ready_irq(info);
1602 } /* start_transmit */
1603
1604 #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
1605 static int serial_fast_timer_started = 0;
1606 static int serial_fast_timer_expired = 0;
1607 static void flush_timeout_function(unsigned long data);
1608 #define START_FLUSH_FAST_TIMER_TIME(info, string, usec) {\
1609 unsigned long timer_flags; \
1610 local_irq_save(timer_flags); \
1611 if (fast_timers[info->line].function == NULL) { \
1612 serial_fast_timer_started++; \
1613 TIMERD(DEBUG_LOG(info->line, "start_timer %i ", info->line)); \
1614 TIMERD(DEBUG_LOG(info->line, "num started: %i\n", serial_fast_timer_started)); \
1615 start_one_shot_timer(&fast_timers[info->line], \
1616 flush_timeout_function, \
1617 (unsigned long)info, \
1618 (usec), \
1619 string); \
1620 } \
1621 else { \
1622 TIMERD(DEBUG_LOG(info->line, "timer %i already running\n", info->line)); \
1623 } \
1624 local_irq_restore(timer_flags); \
1625 }
1626 #define START_FLUSH_FAST_TIMER(info, string) START_FLUSH_FAST_TIMER_TIME(info, string, info->flush_time_usec)
1627
1628 #else
1629 #define START_FLUSH_FAST_TIMER_TIME(info, string, usec)
1630 #define START_FLUSH_FAST_TIMER(info, string)
1631 #endif
1632
1633 static struct etrax_recv_buffer *
1634 alloc_recv_buffer(unsigned int size)
1635 {
1636 struct etrax_recv_buffer *buffer;
1637
1638 buffer = kmalloc(sizeof *buffer + size, GFP_ATOMIC);
1639 if (!buffer)
1640 return NULL;
1641
1642 buffer->next = NULL;
1643 buffer->length = 0;
1644 buffer->error = TTY_NORMAL;
1645
1646 return buffer;
1647 }
1648
1649 static void
1650 append_recv_buffer(struct e100_serial *info, struct etrax_recv_buffer *buffer)
1651 {
1652 unsigned long flags;
1653
1654 local_irq_save(flags);
1655
1656 if (!info->first_recv_buffer)
1657 info->first_recv_buffer = buffer;
1658 else
1659 info->last_recv_buffer->next = buffer;
1660
1661 info->last_recv_buffer = buffer;
1662
1663 info->recv_cnt += buffer->length;
1664 if (info->recv_cnt > info->max_recv_cnt)
1665 info->max_recv_cnt = info->recv_cnt;
1666
1667 local_irq_restore(flags);
1668 }
1669
1670 static int
1671 add_char_and_flag(struct e100_serial *info, unsigned char data, unsigned char flag)
1672 {
1673 struct etrax_recv_buffer *buffer;
1674 if (info->uses_dma_in) {
1675 buffer = alloc_recv_buffer(4);
1676 if (!buffer)
1677 return 0;
1678
1679 buffer->length = 1;
1680 buffer->error = flag;
1681 buffer->buffer[0] = data;
1682
1683 append_recv_buffer(info, buffer);
1684
1685 info->icount.rx++;
1686 } else {
1687 tty_insert_flip_char(&info->port, data, flag);
1688 info->icount.rx++;
1689 }
1690
1691 return 1;
1692 }
1693
1694 static unsigned int handle_descr_data(struct e100_serial *info,
1695 struct etrax_dma_descr *descr,
1696 unsigned int recvl)
1697 {
1698 struct etrax_recv_buffer *buffer = phys_to_virt(descr->buf) - sizeof *buffer;
1699
1700 if (info->recv_cnt + recvl > 65536) {
1701 printk(KERN_WARNING
1702 "%s: Too much pending incoming serial data! Dropping %u bytes.\n", __func__, recvl);
1703 return 0;
1704 }
1705
1706 buffer->length = recvl;
1707
1708 if (info->errorcode == ERRCODE_SET_BREAK)
1709 buffer->error = TTY_BREAK;
1710 info->errorcode = 0;
1711
1712 append_recv_buffer(info, buffer);
1713
1714 buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE);
1715 if (!buffer)
1716 panic("%s: Failed to allocate memory for receive buffer!\n", __func__);
1717
1718 descr->buf = virt_to_phys(buffer->buffer);
1719
1720 return recvl;
1721 }
1722
1723 static unsigned int handle_all_descr_data(struct e100_serial *info)
1724 {
1725 struct etrax_dma_descr *descr;
1726 unsigned int recvl;
1727 unsigned int ret = 0;
1728
1729 while (1)
1730 {
1731 descr = &info->rec_descr[info->cur_rec_descr];
1732
1733 if (descr == phys_to_virt(*info->idescradr))
1734 break;
1735
1736 if (++info->cur_rec_descr == SERIAL_RECV_DESCRIPTORS)
1737 info->cur_rec_descr = 0;
1738
1739 /* find out how many bytes were read */
1740
1741 /* if the eop bit was not set, all data has been received */
1742 if (!(descr->status & d_eop)) {
1743 recvl = descr->sw_len;
1744 } else {
1745 /* otherwise we find the amount of data received here */
1746 recvl = descr->hw_len;
1747 }
1748
1749 /* Reset the status information */
1750 descr->status = 0;
1751
1752 DFLOW( DEBUG_LOG(info->line, "RX %lu\n", recvl);
1753 if (info->port.tty->stopped) {
1754 unsigned char *buf = phys_to_virt(descr->buf);
1755 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[0]);
1756 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[1]);
1757 DEBUG_LOG(info->line, "rx 0x%02X\n", buf[2]);
1758 }
1759 );
1760
1761 /* update stats */
1762 info->icount.rx += recvl;
1763
1764 ret += handle_descr_data(info, descr, recvl);
1765 }
1766
1767 return ret;
1768 }
1769
1770 static void receive_chars_dma(struct e100_serial *info)
1771 {
1772 struct tty_struct *tty;
1773 unsigned char rstat;
1774
1775 /* Acknowledge both dma_descr and dma_eop irq in R_DMA_CHx_CLR_INTR */
1776 *info->iclrintradr =
1777 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
1778 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
1779
1780 tty = info->port.tty;
1781 if (!tty) /* Something wrong... */
1782 return;
1783
1784 #ifdef SERIAL_HANDLE_EARLY_ERRORS
1785 if (info->uses_dma_in)
1786 e100_enable_serial_data_irq(info);
1787 #endif
1788
1789 if (info->errorcode == ERRCODE_INSERT_BREAK)
1790 add_char_and_flag(info, '\0', TTY_BREAK);
1791
1792 handle_all_descr_data(info);
1793
1794 /* Read the status register to detect errors */
1795 rstat = info->ioport[REG_STATUS];
1796 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
1797 DFLOW(DEBUG_LOG(info->line, "XOFF detect stat %x\n", rstat));
1798 }
1799
1800 if (rstat & SER_ERROR_MASK) {
1801 /* If we got an error, we must reset it by reading the
1802 * data_in field
1803 */
1804 unsigned char data = info->ioport[REG_DATA];
1805
1806 DEBUG_LOG(info->line, "#dERR: s d 0x%04X\n",
1807 ((rstat & SER_ERROR_MASK) << 8) | data);
1808
1809 if (rstat & SER_PAR_ERR_MASK)
1810 add_char_and_flag(info, data, TTY_PARITY);
1811 else if (rstat & SER_OVERRUN_MASK)
1812 add_char_and_flag(info, data, TTY_OVERRUN);
1813 else if (rstat & SER_FRAMING_ERR_MASK)
1814 add_char_and_flag(info, data, TTY_FRAME);
1815 }
1816
1817 START_FLUSH_FAST_TIMER(info, "receive_chars");
1818
1819 /* Restart the receiving DMA */
1820 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart);
1821 }
1822
1823 static int start_recv_dma(struct e100_serial *info)
1824 {
1825 struct etrax_dma_descr *descr = info->rec_descr;
1826 struct etrax_recv_buffer *buffer;
1827 int i;
1828
1829 /* Set up the receiving descriptors */
1830 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++) {
1831 buffer = alloc_recv_buffer(SERIAL_DESCR_BUF_SIZE);
1832 if (!buffer)
1833 panic("%s: Failed to allocate memory for receive buffer!\n", __func__);
1834
1835 descr[i].ctrl = d_int;
1836 descr[i].buf = virt_to_phys(buffer->buffer);
1837 descr[i].sw_len = SERIAL_DESCR_BUF_SIZE;
1838 descr[i].hw_len = 0;
1839 descr[i].status = 0;
1840 descr[i].next = virt_to_phys(&descr[i+1]);
1841 }
1842
1843 /* Link the last descriptor to the first */
1844 descr[i-1].next = virt_to_phys(&descr[0]);
1845
1846 /* Start with the first descriptor in the list */
1847 info->cur_rec_descr = 0;
1848
1849 /* Start the DMA */
1850 *info->ifirstadr = virt_to_phys(&descr[info->cur_rec_descr]);
1851 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, start);
1852
1853 /* Input DMA should be running now */
1854 return 1;
1855 }
1856
1857 static void
1858 start_receive(struct e100_serial *info)
1859 {
1860 if (info->uses_dma_in) {
1861 /* reset the input dma channel to be sure it works */
1862
1863 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
1864 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) ==
1865 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
1866
1867 start_recv_dma(info);
1868 }
1869 }
1870
1871
1872 /* the bits in the MASK2 register are laid out like this:
1873 DMAI_EOP DMAI_DESCR DMAO_EOP DMAO_DESCR
1874 where I is the input channel and O is the output channel for the port.
1875 info->irq is the bit number for the DMAO_DESCR so to check the others we
1876 shift info->irq to the left.
1877 */
1878
1879 /* dma output channel interrupt handler
1880 this interrupt is called from DMA2(ser2), DMA4(ser3), DMA6(ser0) or
1881 DMA8(ser1) when they have finished a descriptor with the intr flag set.
1882 */
1883
1884 static irqreturn_t
1885 tr_interrupt(int irq, void *dev_id)
1886 {
1887 struct e100_serial *info;
1888 unsigned long ireg;
1889 int i;
1890 int handled = 0;
1891
1892 /* find out the line that caused this irq and get it from rs_table */
1893
1894 ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
1895
1896 for (i = 0; i < NR_PORTS; i++) {
1897 info = rs_table + i;
1898 if (!info->enabled || !info->uses_dma_out)
1899 continue;
1900 /* check for dma_descr (don't need to check for dma_eop in output dma for serial */
1901 if (ireg & info->irq) {
1902 handled = 1;
1903 /* we can send a new dma bunch. make it so. */
1904 DINTR2(DEBUG_LOG(info->line, "tr_interrupt %i\n", i));
1905 /* Read jiffies_usec first,
1906 * we want this time to be as late as possible
1907 */
1908 info->last_tx_active_usec = GET_JIFFIES_USEC();
1909 info->last_tx_active = jiffies;
1910 transmit_chars_dma(info);
1911 }
1912
1913 /* FIXME: here we should really check for a change in the
1914 status lines and if so call status_handle(info) */
1915 }
1916 return IRQ_RETVAL(handled);
1917 } /* tr_interrupt */
1918
1919 /* dma input channel interrupt handler */
1920
1921 static irqreturn_t
1922 rec_interrupt(int irq, void *dev_id)
1923 {
1924 struct e100_serial *info;
1925 unsigned long ireg;
1926 int i;
1927 int handled = 0;
1928
1929 /* find out the line that caused this irq and get it from rs_table */
1930
1931 ireg = *R_IRQ_MASK2_RD; /* get the active irq bits for the dma channels */
1932
1933 for (i = 0; i < NR_PORTS; i++) {
1934 info = rs_table + i;
1935 if (!info->enabled || !info->uses_dma_in)
1936 continue;
1937 /* check for both dma_eop and dma_descr for the input dma channel */
1938 if (ireg & ((info->irq << 2) | (info->irq << 3))) {
1939 handled = 1;
1940 /* we have received something */
1941 receive_chars_dma(info);
1942 }
1943
1944 /* FIXME: here we should really check for a change in the
1945 status lines and if so call status_handle(info) */
1946 }
1947 return IRQ_RETVAL(handled);
1948 } /* rec_interrupt */
1949
1950 static int force_eop_if_needed(struct e100_serial *info)
1951 {
1952 /* We check data_avail bit to determine if data has
1953 * arrived since last time
1954 */
1955 unsigned char rstat = info->ioport[REG_STATUS];
1956
1957 /* error or datavail? */
1958 if (rstat & SER_ERROR_MASK) {
1959 /* Some error has occurred. If there has been valid data, an
1960 * EOP interrupt will be made automatically. If no data, the
1961 * normal ser_interrupt should be enabled and handle it.
1962 * So do nothing!
1963 */
1964 DEBUG_LOG(info->line, "timeout err: rstat 0x%03X\n",
1965 rstat | (info->line << 8));
1966 return 0;
1967 }
1968
1969 if (rstat & SER_DATA_AVAIL_MASK) {
1970 /* Ok data, no error, count it */
1971 TIMERD(DEBUG_LOG(info->line, "timeout: rstat 0x%03X\n",
1972 rstat | (info->line << 8)));
1973 /* Read data to clear status flags */
1974 (void)info->ioport[REG_DATA];
1975
1976 info->forced_eop = 0;
1977 START_FLUSH_FAST_TIMER(info, "magic");
1978 return 0;
1979 }
1980
1981 /* hit the timeout, force an EOP for the input
1982 * dma channel if we haven't already
1983 */
1984 if (!info->forced_eop) {
1985 info->forced_eop = 1;
1986 TIMERD(DEBUG_LOG(info->line, "timeout EOP %i\n", info->line));
1987 FORCE_EOP(info);
1988 }
1989
1990 return 1;
1991 }
1992
1993 static void flush_to_flip_buffer(struct e100_serial *info)
1994 {
1995 struct etrax_recv_buffer *buffer;
1996 unsigned long flags;
1997
1998 local_irq_save(flags);
1999
2000 while ((buffer = info->first_recv_buffer) != NULL) {
2001 unsigned int count = buffer->length;
2002
2003 tty_insert_flip_string(&info->port, buffer->buffer, count);
2004 info->recv_cnt -= count;
2005
2006 if (count == buffer->length) {
2007 info->first_recv_buffer = buffer->next;
2008 kfree(buffer);
2009 } else {
2010 buffer->length -= count;
2011 memmove(buffer->buffer, buffer->buffer + count, buffer->length);
2012 buffer->error = TTY_NORMAL;
2013 }
2014 }
2015
2016 if (!info->first_recv_buffer)
2017 info->last_recv_buffer = NULL;
2018
2019 local_irq_restore(flags);
2020
2021 /* This includes a check for low-latency */
2022 tty_flip_buffer_push(&info->port);
2023 }
2024
2025 static void check_flush_timeout(struct e100_serial *info)
2026 {
2027 /* Flip what we've got (if we can) */
2028 flush_to_flip_buffer(info);
2029
2030 /* We might need to flip later, but not to fast
2031 * since the system is busy processing input... */
2032 if (info->first_recv_buffer)
2033 START_FLUSH_FAST_TIMER_TIME(info, "flip", 2000);
2034
2035 /* Force eop last, since data might have come while we're processing
2036 * and if we started the slow timer above, we won't start a fast
2037 * below.
2038 */
2039 force_eop_if_needed(info);
2040 }
2041
2042 #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
2043 static void flush_timeout_function(unsigned long data)
2044 {
2045 struct e100_serial *info = (struct e100_serial *)data;
2046
2047 fast_timers[info->line].function = NULL;
2048 serial_fast_timer_expired++;
2049 TIMERD(DEBUG_LOG(info->line, "flush_timeout %i ", info->line));
2050 TIMERD(DEBUG_LOG(info->line, "num expired: %i\n", serial_fast_timer_expired));
2051 check_flush_timeout(info);
2052 }
2053
2054 #else
2055
2056 /* dma fifo/buffer timeout handler
2057 forces an end-of-packet for the dma input channel if no chars
2058 have been received for CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS/100 s.
2059 */
2060
2061 static struct timer_list flush_timer;
2062
2063 static void
2064 timed_flush_handler(unsigned long ptr)
2065 {
2066 struct e100_serial *info;
2067 int i;
2068
2069 for (i = 0; i < NR_PORTS; i++) {
2070 info = rs_table + i;
2071 if (info->uses_dma_in)
2072 check_flush_timeout(info);
2073 }
2074
2075 /* restart flush timer */
2076 mod_timer(&flush_timer, jiffies + CONFIG_ETRAX_SERIAL_RX_TIMEOUT_TICKS);
2077 }
2078 #endif
2079
2080 #ifdef SERIAL_HANDLE_EARLY_ERRORS
2081
2082 /* If there is an error (ie break) when the DMA is running and
2083 * there are no bytes in the fifo the DMA is stopped and we get no
2084 * eop interrupt. Thus we have to monitor the first bytes on a DMA
2085 * transfer, and if it is without error we can turn the serial
2086 * interrupts off.
2087 */
2088
2089 /*
2090 BREAK handling on ETRAX 100:
2091 ETRAX will generate interrupt although there is no stop bit between the
2092 characters.
2093
2094 Depending on how long the break sequence is, the end of the breaksequence
2095 will look differently:
2096 | indicates start/end of a character.
2097
2098 B= Break character (0x00) with framing error.
2099 E= Error byte with parity error received after B characters.
2100 F= "Faked" valid byte received immediately after B characters.
2101 V= Valid byte
2102
2103 1.
2104 B BL ___________________________ V
2105 .._|__________|__________| |valid data |
2106
2107 Multiple frame errors with data == 0x00 (B),
2108 the timing matches up "perfectly" so no extra ending char is detected.
2109 The RXD pin is 1 in the last interrupt, in that case
2110 we set info->errorcode = ERRCODE_INSERT_BREAK, but we can't really
2111 know if another byte will come and this really is case 2. below
2112 (e.g F=0xFF or 0xFE)
2113 If RXD pin is 0 we can expect another character (see 2. below).
2114
2115
2116 2.
2117
2118 B B E or F__________________..__ V
2119 .._|__________|__________|______ | |valid data
2120 "valid" or
2121 parity error
2122
2123 Multiple frame errors with data == 0x00 (B),
2124 but the part of the break trigs is interpreted as a start bit (and possibly
2125 some 0 bits followed by a number of 1 bits and a stop bit).
2126 Depending on parity settings etc. this last character can be either
2127 a fake "valid" char (F) or have a parity error (E).
2128
2129 If the character is valid it will be put in the buffer,
2130 we set info->errorcode = ERRCODE_SET_BREAK so the receive interrupt
2131 will set the flags so the tty will handle it,
2132 if it's an error byte it will not be put in the buffer
2133 and we set info->errorcode = ERRCODE_INSERT_BREAK.
2134
2135 To distinguish a V byte in 1. from an F byte in 2. we keep a timestamp
2136 of the last faulty char (B) and compares it with the current time:
2137 If the time elapsed time is less then 2*char_time_usec we will assume
2138 it's a faked F char and not a Valid char and set
2139 info->errorcode = ERRCODE_SET_BREAK.
2140
2141 Flaws in the above solution:
2142 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
2143 We use the timer to distinguish a F character from a V character,
2144 if a V character is to close after the break we might make the wrong decision.
2145
2146 TODO: The break will be delayed until an F or V character is received.
2147
2148 */
2149
2150 static void handle_ser_rx_interrupt_no_dma(struct e100_serial *info)
2151 {
2152 unsigned long data_read;
2153
2154 /* Read data and status at the same time */
2155 data_read = *((unsigned long *)&info->ioport[REG_DATA_STATUS32]);
2156 more_data:
2157 if (data_read & IO_MASK(R_SERIAL0_READ, xoff_detect) ) {
2158 DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
2159 }
2160 DINTR2(DEBUG_LOG(info->line, "ser_rx %c\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read)));
2161
2162 if (data_read & ( IO_MASK(R_SERIAL0_READ, framing_err) |
2163 IO_MASK(R_SERIAL0_READ, par_err) |
2164 IO_MASK(R_SERIAL0_READ, overrun) )) {
2165 /* An error */
2166 info->last_rx_active_usec = GET_JIFFIES_USEC();
2167 info->last_rx_active = jiffies;
2168 DINTR1(DEBUG_LOG(info->line, "ser_rx err stat_data %04X\n", data_read));
2169 DLOG_INT_TRIG(
2170 if (!log_int_trig1_pos) {
2171 log_int_trig1_pos = log_int_pos;
2172 log_int(rdpc(), 0, 0);
2173 }
2174 );
2175
2176
2177 if ( ((data_read & IO_MASK(R_SERIAL0_READ, data_in)) == 0) &&
2178 (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) ) {
2179 /* Most likely a break, but we get interrupts over and
2180 * over again.
2181 */
2182
2183 if (!info->break_detected_cnt) {
2184 DEBUG_LOG(info->line, "#BRK start\n", 0);
2185 }
2186 if (data_read & IO_MASK(R_SERIAL0_READ, rxd)) {
2187 /* The RX pin is high now, so the break
2188 * must be over, but....
2189 * we can't really know if we will get another
2190 * last byte ending the break or not.
2191 * And we don't know if the byte (if any) will
2192 * have an error or look valid.
2193 */
2194 DEBUG_LOG(info->line, "# BL BRK\n", 0);
2195 info->errorcode = ERRCODE_INSERT_BREAK;
2196 }
2197 info->break_detected_cnt++;
2198 } else {
2199 /* The error does not look like a break, but could be
2200 * the end of one
2201 */
2202 if (info->break_detected_cnt) {
2203 DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
2204 info->errorcode = ERRCODE_INSERT_BREAK;
2205 } else {
2206 unsigned char data = IO_EXTRACT(R_SERIAL0_READ,
2207 data_in, data_read);
2208 char flag = TTY_NORMAL;
2209 if (info->errorcode == ERRCODE_INSERT_BREAK) {
2210 tty_insert_flip_char(&info->port, 0, flag);
2211 info->icount.rx++;
2212 }
2213
2214 if (data_read & IO_MASK(R_SERIAL0_READ, par_err)) {
2215 info->icount.parity++;
2216 flag = TTY_PARITY;
2217 } else if (data_read & IO_MASK(R_SERIAL0_READ, overrun)) {
2218 info->icount.overrun++;
2219 flag = TTY_OVERRUN;
2220 } else if (data_read & IO_MASK(R_SERIAL0_READ, framing_err)) {
2221 info->icount.frame++;
2222 flag = TTY_FRAME;
2223 }
2224 tty_insert_flip_char(&info->port, data, flag);
2225 info->errorcode = 0;
2226 }
2227 info->break_detected_cnt = 0;
2228 }
2229 } else if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
2230 /* No error */
2231 DLOG_INT_TRIG(
2232 if (!log_int_trig1_pos) {
2233 if (log_int_pos >= log_int_size) {
2234 log_int_pos = 0;
2235 }
2236 log_int_trig0_pos = log_int_pos;
2237 log_int(rdpc(), 0, 0);
2238 }
2239 );
2240 tty_insert_flip_char(&info->port,
2241 IO_EXTRACT(R_SERIAL0_READ, data_in, data_read),
2242 TTY_NORMAL);
2243 } else {
2244 DEBUG_LOG(info->line, "ser_rx int but no data_avail %08lX\n", data_read);
2245 }
2246
2247
2248 info->icount.rx++;
2249 data_read = *((unsigned long *)&info->ioport[REG_DATA_STATUS32]);
2250 if (data_read & IO_MASK(R_SERIAL0_READ, data_avail)) {
2251 DEBUG_LOG(info->line, "ser_rx %c in loop\n", IO_EXTRACT(R_SERIAL0_READ, data_in, data_read));
2252 goto more_data;
2253 }
2254
2255 tty_flip_buffer_push(&info->port);
2256 }
2257
2258 static void handle_ser_rx_interrupt(struct e100_serial *info)
2259 {
2260 unsigned char rstat;
2261
2262 #ifdef SERIAL_DEBUG_INTR
2263 printk("Interrupt from serport %d\n", i);
2264 #endif
2265 /* DEBUG_LOG(info->line, "ser_interrupt stat %03X\n", rstat | (i << 8)); */
2266 if (!info->uses_dma_in) {
2267 handle_ser_rx_interrupt_no_dma(info);
2268 return;
2269 }
2270 /* DMA is used */
2271 rstat = info->ioport[REG_STATUS];
2272 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect) ) {
2273 DFLOW(DEBUG_LOG(info->line, "XOFF detect\n", 0));
2274 }
2275
2276 if (rstat & SER_ERROR_MASK) {
2277 unsigned char data;
2278
2279 info->last_rx_active_usec = GET_JIFFIES_USEC();
2280 info->last_rx_active = jiffies;
2281 /* If we got an error, we must reset it by reading the
2282 * data_in field
2283 */
2284 data = info->ioport[REG_DATA];
2285 DINTR1(DEBUG_LOG(info->line, "ser_rx! %c\n", data));
2286 DINTR1(DEBUG_LOG(info->line, "ser_rx err stat %02X\n", rstat));
2287 if (!data && (rstat & SER_FRAMING_ERR_MASK)) {
2288 /* Most likely a break, but we get interrupts over and
2289 * over again.
2290 */
2291
2292 if (!info->break_detected_cnt) {
2293 DEBUG_LOG(info->line, "#BRK start\n", 0);
2294 }
2295 if (rstat & SER_RXD_MASK) {
2296 /* The RX pin is high now, so the break
2297 * must be over, but....
2298 * we can't really know if we will get another
2299 * last byte ending the break or not.
2300 * And we don't know if the byte (if any) will
2301 * have an error or look valid.
2302 */
2303 DEBUG_LOG(info->line, "# BL BRK\n", 0);
2304 info->errorcode = ERRCODE_INSERT_BREAK;
2305 }
2306 info->break_detected_cnt++;
2307 } else {
2308 /* The error does not look like a break, but could be
2309 * the end of one
2310 */
2311 if (info->break_detected_cnt) {
2312 DEBUG_LOG(info->line, "EBRK %i\n", info->break_detected_cnt);
2313 info->errorcode = ERRCODE_INSERT_BREAK;
2314 } else {
2315 if (info->errorcode == ERRCODE_INSERT_BREAK) {
2316 info->icount.brk++;
2317 add_char_and_flag(info, '\0', TTY_BREAK);
2318 }
2319
2320 if (rstat & SER_PAR_ERR_MASK) {
2321 info->icount.parity++;
2322 add_char_and_flag(info, data, TTY_PARITY);
2323 } else if (rstat & SER_OVERRUN_MASK) {
2324 info->icount.overrun++;
2325 add_char_and_flag(info, data, TTY_OVERRUN);
2326 } else if (rstat & SER_FRAMING_ERR_MASK) {
2327 info->icount.frame++;
2328 add_char_and_flag(info, data, TTY_FRAME);
2329 }
2330
2331 info->errorcode = 0;
2332 }
2333 info->break_detected_cnt = 0;
2334 DEBUG_LOG(info->line, "#iERR s d %04X\n",
2335 ((rstat & SER_ERROR_MASK) << 8) | data);
2336 }
2337 } else { /* It was a valid byte, now let the DMA do the rest */
2338 unsigned long curr_time_u = GET_JIFFIES_USEC();
2339 unsigned long curr_time = jiffies;
2340
2341 if (info->break_detected_cnt) {
2342 /* Detect if this character is a new valid char or the
2343 * last char in a break sequence: If LSBits are 0 and
2344 * MSBits are high AND the time is close to the
2345 * previous interrupt we should discard it.
2346 */
2347 long elapsed_usec =
2348 (curr_time - info->last_rx_active) * (1000000/HZ) +
2349 curr_time_u - info->last_rx_active_usec;
2350 if (elapsed_usec < 2*info->char_time_usec) {
2351 DEBUG_LOG(info->line, "FBRK %i\n", info->line);
2352 /* Report as BREAK (error) and let
2353 * receive_chars_dma() handle it
2354 */
2355 info->errorcode = ERRCODE_SET_BREAK;
2356 } else {
2357 DEBUG_LOG(info->line, "Not end of BRK (V)%i\n", info->line);
2358 }
2359 DEBUG_LOG(info->line, "num brk %i\n", info->break_detected_cnt);
2360 }
2361
2362 #ifdef SERIAL_DEBUG_INTR
2363 printk("** OK, disabling ser_interrupts\n");
2364 #endif
2365 e100_disable_serial_data_irq(info);
2366 DINTR2(DEBUG_LOG(info->line, "ser_rx OK %d\n", info->line));
2367 info->break_detected_cnt = 0;
2368
2369 }
2370 /* Restarting the DMA never hurts */
2371 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, restart);
2372 START_FLUSH_FAST_TIMER(info, "ser_int");
2373 } /* handle_ser_rx_interrupt */
2374
2375 static void handle_ser_tx_interrupt(struct e100_serial *info)
2376 {
2377 unsigned long flags;
2378
2379 if (info->x_char) {
2380 unsigned char rstat;
2381 DFLOW(DEBUG_LOG(info->line, "tx_int: xchar 0x%02X\n", info->x_char));
2382 local_irq_save(flags);
2383 rstat = info->ioport[REG_STATUS];
2384 DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat));
2385
2386 info->ioport[REG_TR_DATA] = info->x_char;
2387 info->icount.tx++;
2388 info->x_char = 0;
2389 /* We must enable since it is disabled in ser_interrupt */
2390 e100_enable_serial_tx_ready_irq(info);
2391 local_irq_restore(flags);
2392 return;
2393 }
2394 if (info->uses_dma_out) {
2395 unsigned char rstat;
2396 int i;
2397 /* We only use normal tx interrupt when sending x_char */
2398 DFLOW(DEBUG_LOG(info->line, "tx_int: xchar sent\n", 0));
2399 local_irq_save(flags);
2400 rstat = info->ioport[REG_STATUS];
2401 DFLOW(DEBUG_LOG(info->line, "stat %x\n", rstat));
2402 e100_disable_serial_tx_ready_irq(info);
2403 if (info->port.tty->stopped)
2404 rs_stop(info->port.tty);
2405 /* Enable the DMA channel and tell it to continue */
2406 e100_enable_txdma_channel(info);
2407 /* Wait 12 cycles before doing the DMA command */
2408 for(i = 6; i > 0; i--)
2409 nop();
2410
2411 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, continue);
2412 local_irq_restore(flags);
2413 return;
2414 }
2415 /* Normal char-by-char interrupt */
2416 if (info->xmit.head == info->xmit.tail
2417 || info->port.tty->stopped) {
2418 DFLOW(DEBUG_LOG(info->line, "tx_int: stopped %i\n",
2419 info->port.tty->stopped));
2420 e100_disable_serial_tx_ready_irq(info);
2421 info->tr_running = 0;
2422 return;
2423 }
2424 DINTR2(DEBUG_LOG(info->line, "tx_int %c\n", info->xmit.buf[info->xmit.tail]));
2425 /* Send a byte, rs485 timing is critical so turn of ints */
2426 local_irq_save(flags);
2427 info->ioport[REG_TR_DATA] = info->xmit.buf[info->xmit.tail];
2428 info->xmit.tail = (info->xmit.tail + 1) & (SERIAL_XMIT_SIZE-1);
2429 info->icount.tx++;
2430 if (info->xmit.head == info->xmit.tail) {
2431 #if defined(CONFIG_ETRAX_RS485) && defined(CONFIG_ETRAX_FAST_TIMER)
2432 if (info->rs485.flags & SER_RS485_ENABLED) {
2433 /* Set a short timer to toggle RTS */
2434 start_one_shot_timer(&fast_timers_rs485[info->line],
2435 rs485_toggle_rts_timer_function,
2436 (unsigned long)info,
2437 info->char_time_usec*2,
2438 "RS-485");
2439 }
2440 #endif /* RS485 */
2441 info->last_tx_active_usec = GET_JIFFIES_USEC();
2442 info->last_tx_active = jiffies;
2443 e100_disable_serial_tx_ready_irq(info);
2444 info->tr_running = 0;
2445 DFLOW(DEBUG_LOG(info->line, "tx_int: stop2\n", 0));
2446 } else {
2447 /* We must enable since it is disabled in ser_interrupt */
2448 e100_enable_serial_tx_ready_irq(info);
2449 }
2450 local_irq_restore(flags);
2451
2452 if (CIRC_CNT(info->xmit.head,
2453 info->xmit.tail,
2454 SERIAL_XMIT_SIZE) < WAKEUP_CHARS)
2455 rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
2456
2457 } /* handle_ser_tx_interrupt */
2458
2459 /* result of time measurements:
2460 * RX duration 54-60 us when doing something, otherwise 6-9 us
2461 * ser_int duration: just sending: 8-15 us normally, up to 73 us
2462 */
2463 static irqreturn_t
2464 ser_interrupt(int irq, void *dev_id)
2465 {
2466 static volatile int tx_started = 0;
2467 struct e100_serial *info;
2468 int i;
2469 unsigned long flags;
2470 unsigned long irq_mask1_rd;
2471 unsigned long data_mask = (1 << (8+2*0)); /* ser0 data_avail */
2472 int handled = 0;
2473 static volatile unsigned long reentered_ready_mask = 0;
2474
2475 local_irq_save(flags);
2476 irq_mask1_rd = *R_IRQ_MASK1_RD;
2477 /* First handle all rx interrupts with ints disabled */
2478 info = rs_table;
2479 irq_mask1_rd &= e100_ser_int_mask;
2480 for (i = 0; i < NR_PORTS; i++) {
2481 /* Which line caused the data irq? */
2482 if (irq_mask1_rd & data_mask) {
2483 handled = 1;
2484 handle_ser_rx_interrupt(info);
2485 }
2486 info += 1;
2487 data_mask <<= 2;
2488 }
2489 /* Handle tx interrupts with interrupts enabled so we
2490 * can take care of new data interrupts while transmitting
2491 * We protect the tx part with the tx_started flag.
2492 * We disable the tr_ready interrupts we are about to handle and
2493 * unblock the serial interrupt so new serial interrupts may come.
2494 *
2495 * If we get a new interrupt:
2496 * - it migth be due to synchronous serial ports.
2497 * - serial irq will be blocked by general irq handler.
2498 * - async data will be handled above (sync will be ignored).
2499 * - tx_started flag will prevent us from trying to send again and
2500 * we will exit fast - no need to unblock serial irq.
2501 * - Next (sync) serial interrupt handler will be runned with
2502 * disabled interrupt due to restore_flags() at end of function,
2503 * so sync handler will not be preempted or reentered.
2504 */
2505 if (!tx_started) {
2506 unsigned long ready_mask;
2507 unsigned long
2508 tx_started = 1;
2509 /* Only the tr_ready interrupts left */
2510 irq_mask1_rd &= (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |
2511 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |
2512 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |
2513 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));
2514 while (irq_mask1_rd) {
2515 /* Disable those we are about to handle */
2516 *R_IRQ_MASK1_CLR = irq_mask1_rd;
2517 /* Unblock the serial interrupt */
2518 *R_VECT_MASK_SET = IO_STATE(R_VECT_MASK_SET, serial, set);
2519
2520 local_irq_enable();
2521 ready_mask = (1 << (8+1+2*0)); /* ser0 tr_ready */
2522 info = rs_table;
2523 for (i = 0; i < NR_PORTS; i++) {
2524 /* Which line caused the ready irq? */
2525 if (irq_mask1_rd & ready_mask) {
2526 handled = 1;
2527 handle_ser_tx_interrupt(info);
2528 }
2529 info += 1;
2530 ready_mask <<= 2;
2531 }
2532 /* handle_ser_tx_interrupt enables tr_ready interrupts */
2533 local_irq_disable();
2534 /* Handle reentered TX interrupt */
2535 irq_mask1_rd = reentered_ready_mask;
2536 }
2537 local_irq_disable();
2538 tx_started = 0;
2539 } else {
2540 unsigned long ready_mask;
2541 ready_mask = irq_mask1_rd & (IO_MASK(R_IRQ_MASK1_RD, ser0_ready) |
2542 IO_MASK(R_IRQ_MASK1_RD, ser1_ready) |
2543 IO_MASK(R_IRQ_MASK1_RD, ser2_ready) |
2544 IO_MASK(R_IRQ_MASK1_RD, ser3_ready));
2545 if (ready_mask) {
2546 reentered_ready_mask |= ready_mask;
2547 /* Disable those we are about to handle */
2548 *R_IRQ_MASK1_CLR = ready_mask;
2549 DFLOW(DEBUG_LOG(SERIAL_DEBUG_LINE, "ser_int reentered with TX %X\n", ready_mask));
2550 }
2551 }
2552
2553 local_irq_restore(flags);
2554 return IRQ_RETVAL(handled);
2555 } /* ser_interrupt */
2556 #endif
2557
2558 /*
2559 * -------------------------------------------------------------------
2560 * Here ends the serial interrupt routines.
2561 * -------------------------------------------------------------------
2562 */
2563
2564 /*
2565 * This routine is used to handle the "bottom half" processing for the
2566 * serial driver, known also the "software interrupt" processing.
2567 * This processing is done at the kernel interrupt level, after the
2568 * rs_interrupt() has returned, BUT WITH INTERRUPTS TURNED ON. This
2569 * is where time-consuming activities which can not be done in the
2570 * interrupt driver proper are done; the interrupt driver schedules
2571 * them using rs_sched_event(), and they get done here.
2572 */
2573 static void
2574 do_softint(struct work_struct *work)
2575 {
2576 struct e100_serial *info;
2577 struct tty_struct *tty;
2578
2579 info = container_of(work, struct e100_serial, work);
2580
2581 tty = info->port.tty;
2582 if (!tty)
2583 return;
2584
2585 if (test_and_clear_bit(RS_EVENT_WRITE_WAKEUP, &info->event))
2586 tty_wakeup(tty);
2587 }
2588
2589 static int
2590 startup(struct e100_serial * info)
2591 {
2592 unsigned long flags;
2593 unsigned long xmit_page;
2594 int i;
2595
2596 xmit_page = get_zeroed_page(GFP_KERNEL);
2597 if (!xmit_page)
2598 return -ENOMEM;
2599
2600 local_irq_save(flags);
2601
2602 /* if it was already initialized, skip this */
2603
2604 if (info->port.flags & ASYNC_INITIALIZED) {
2605 local_irq_restore(flags);
2606 free_page(xmit_page);
2607 return 0;
2608 }
2609
2610 if (info->xmit.buf)
2611 free_page(xmit_page);
2612 else
2613 info->xmit.buf = (unsigned char *) xmit_page;
2614
2615 #ifdef SERIAL_DEBUG_OPEN
2616 printk("starting up ttyS%d (xmit_buf 0x%p)...\n", info->line, info->xmit.buf);
2617 #endif
2618
2619 /*
2620 * Clear the FIFO buffers and disable them
2621 * (they will be reenabled in change_speed())
2622 */
2623
2624 /*
2625 * Reset the DMA channels and make sure their interrupts are cleared
2626 */
2627
2628 if (info->dma_in_enabled) {
2629 info->uses_dma_in = 1;
2630 e100_enable_rxdma_channel(info);
2631
2632 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2633
2634 /* Wait until reset cycle is complete */
2635 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->icmdadr) ==
2636 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
2637
2638 /* Make sure the irqs are cleared */
2639 *info->iclrintradr =
2640 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
2641 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
2642 } else {
2643 e100_disable_rxdma_channel(info);
2644 }
2645
2646 if (info->dma_out_enabled) {
2647 info->uses_dma_out = 1;
2648 e100_enable_txdma_channel(info);
2649 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2650
2651 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) ==
2652 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, reset));
2653
2654 /* Make sure the irqs are cleared */
2655 *info->oclrintradr =
2656 IO_STATE(R_DMA_CH6_CLR_INTR, clr_descr, do) |
2657 IO_STATE(R_DMA_CH6_CLR_INTR, clr_eop, do);
2658 } else {
2659 e100_disable_txdma_channel(info);
2660 }
2661
2662 if (info->port.tty)
2663 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2664
2665 info->xmit.head = info->xmit.tail = 0;
2666 info->first_recv_buffer = info->last_recv_buffer = NULL;
2667 info->recv_cnt = info->max_recv_cnt = 0;
2668
2669 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2670 info->rec_descr[i].buf = 0;
2671
2672 /*
2673 * and set the speed and other flags of the serial port
2674 * this will start the rx/tx as well
2675 */
2676 #ifdef SERIAL_HANDLE_EARLY_ERRORS
2677 e100_enable_serial_data_irq(info);
2678 #endif
2679 change_speed(info);
2680
2681 /* dummy read to reset any serial errors */
2682
2683 (void)info->ioport[REG_DATA];
2684
2685 /* enable the interrupts */
2686 if (info->uses_dma_out)
2687 e100_enable_txdma_irq(info);
2688
2689 e100_enable_rx_irq(info);
2690
2691 info->tr_running = 0; /* to be sure we don't lock up the transmitter */
2692
2693 /* setup the dma input descriptor and start dma */
2694
2695 start_receive(info);
2696
2697 /* for safety, make sure the descriptors last result is 0 bytes written */
2698
2699 info->tr_descr.sw_len = 0;
2700 info->tr_descr.hw_len = 0;
2701 info->tr_descr.status = 0;
2702
2703 /* enable RTS/DTR last */
2704
2705 e100_rts(info, 1);
2706 e100_dtr(info, 1);
2707
2708 info->port.flags |= ASYNC_INITIALIZED;
2709
2710 local_irq_restore(flags);
2711 return 0;
2712 }
2713
2714 /*
2715 * This routine will shutdown a serial port; interrupts are disabled, and
2716 * DTR is dropped if the hangup on close termio flag is on.
2717 */
2718 static void
2719 shutdown(struct e100_serial * info)
2720 {
2721 unsigned long flags;
2722 struct etrax_dma_descr *descr = info->rec_descr;
2723 struct etrax_recv_buffer *buffer;
2724 int i;
2725
2726 /* shut down the transmitter and receiver */
2727 DFLOW(DEBUG_LOG(info->line, "shutdown %i\n", info->line));
2728 e100_disable_rx(info);
2729 info->ioport[REG_TR_CTRL] = (info->tx_ctrl &= ~0x40);
2730
2731 /* disable interrupts, reset dma channels */
2732 if (info->uses_dma_in) {
2733 e100_disable_rxdma_irq(info);
2734 *info->icmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2735 info->uses_dma_in = 0;
2736 } else {
2737 e100_disable_serial_data_irq(info);
2738 }
2739
2740 if (info->uses_dma_out) {
2741 e100_disable_txdma_irq(info);
2742 info->tr_running = 0;
2743 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, reset);
2744 info->uses_dma_out = 0;
2745 } else {
2746 e100_disable_serial_tx_ready_irq(info);
2747 info->tr_running = 0;
2748 }
2749
2750 if (!(info->port.flags & ASYNC_INITIALIZED))
2751 return;
2752
2753 #ifdef SERIAL_DEBUG_OPEN
2754 printk("Shutting down serial port %d (irq %d)....\n", info->line,
2755 info->irq);
2756 #endif
2757
2758 local_irq_save(flags);
2759
2760 if (info->xmit.buf) {
2761 free_page((unsigned long)info->xmit.buf);
2762 info->xmit.buf = NULL;
2763 }
2764
2765 for (i = 0; i < SERIAL_RECV_DESCRIPTORS; i++)
2766 if (descr[i].buf) {
2767 buffer = phys_to_virt(descr[i].buf) - sizeof *buffer;
2768 kfree(buffer);
2769 descr[i].buf = 0;
2770 }
2771
2772 if (!info->port.tty || (info->port.tty->termios.c_cflag & HUPCL)) {
2773 /* hang up DTR and RTS if HUPCL is enabled */
2774 e100_dtr(info, 0);
2775 e100_rts(info, 0); /* could check CRTSCTS before doing this */
2776 }
2777
2778 if (info->port.tty)
2779 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2780
2781 info->port.flags &= ~ASYNC_INITIALIZED;
2782 local_irq_restore(flags);
2783 }
2784
2785
2786 /* change baud rate and other assorted parameters */
2787
2788 static void
2789 change_speed(struct e100_serial *info)
2790 {
2791 unsigned int cflag;
2792 unsigned long xoff;
2793 unsigned long flags;
2794 /* first some safety checks */
2795
2796 if (!info->port.tty)
2797 return;
2798 if (!info->ioport)
2799 return;
2800
2801 cflag = info->port.tty->termios.c_cflag;
2802
2803 /* possibly, the tx/rx should be disabled first to do this safely */
2804
2805 /* change baud-rate and write it to the hardware */
2806 if ((info->port.flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST) {
2807 /* Special baudrate */
2808 u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */
2809 unsigned long alt_source =
2810 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) |
2811 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal);
2812 /* R_ALT_SER_BAUDRATE selects the source */
2813 DBAUD(printk("Custom baudrate: baud_base/divisor %lu/%i\n",
2814 (unsigned long)info->baud_base, info->custom_divisor));
2815 if (info->baud_base == SERIAL_PRESCALE_BASE) {
2816 /* 0, 2-65535 (0=65536) */
2817 u16 divisor = info->custom_divisor;
2818 /* R_SERIAL_PRESCALE (upper 16 bits of R_CLOCK_PRESCALE) */
2819 /* baudrate is 3.125MHz/custom_divisor */
2820 alt_source =
2821 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, prescale) |
2822 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, prescale);
2823 alt_source = 0x11;
2824 DBAUD(printk("Writing SERIAL_PRESCALE: divisor %i\n", divisor));
2825 *R_SERIAL_PRESCALE = divisor;
2826 info->baud = SERIAL_PRESCALE_BASE/divisor;
2827 }
2828 else
2829 {
2830 /* Bad baudbase, we don't support using timer0
2831 * for baudrate.
2832 */
2833 printk(KERN_WARNING "Bad baud_base/custom_divisor: %lu/%i\n",
2834 (unsigned long)info->baud_base, info->custom_divisor);
2835 }
2836 r_alt_ser_baudrate_shadow &= ~mask;
2837 r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8));
2838 *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow;
2839 } else {
2840 /* Normal baudrate */
2841 /* Make sure we use normal baudrate */
2842 u32 mask = 0xFF << (info->line*8); /* Each port has 8 bits */
2843 unsigned long alt_source =
2844 IO_STATE(R_ALT_SER_BAUDRATE, ser0_rec, normal) |
2845 IO_STATE(R_ALT_SER_BAUDRATE, ser0_tr, normal);
2846 r_alt_ser_baudrate_shadow &= ~mask;
2847 r_alt_ser_baudrate_shadow |= (alt_source << (info->line*8));
2848 *R_ALT_SER_BAUDRATE = r_alt_ser_baudrate_shadow;
2849
2850 info->baud = cflag_to_baud(cflag);
2851 info->ioport[REG_BAUD] = cflag_to_etrax_baud(cflag);
2852 }
2853
2854 /* start with default settings and then fill in changes */
2855 local_irq_save(flags);
2856 /* 8 bit, no/even parity */
2857 info->rx_ctrl &= ~(IO_MASK(R_SERIAL0_REC_CTRL, rec_bitnr) |
2858 IO_MASK(R_SERIAL0_REC_CTRL, rec_par_en) |
2859 IO_MASK(R_SERIAL0_REC_CTRL, rec_par));
2860
2861 /* 8 bit, no/even parity, 1 stop bit, no cts */
2862 info->tx_ctrl &= ~(IO_MASK(R_SERIAL0_TR_CTRL, tr_bitnr) |
2863 IO_MASK(R_SERIAL0_TR_CTRL, tr_par_en) |
2864 IO_MASK(R_SERIAL0_TR_CTRL, tr_par) |
2865 IO_MASK(R_SERIAL0_TR_CTRL, stop_bits) |
2866 IO_MASK(R_SERIAL0_TR_CTRL, auto_cts));
2867
2868 if ((cflag & CSIZE) == CS7) {
2869 /* set 7 bit mode */
2870 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_bitnr, tr_7bit);
2871 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_bitnr, rec_7bit);
2872 }
2873
2874 if (cflag & CSTOPB) {
2875 /* set 2 stop bit mode */
2876 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, stop_bits, two_bits);
2877 }
2878
2879 if (cflag & PARENB) {
2880 /* enable parity */
2881 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par_en, enable);
2882 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par_en, enable);
2883 }
2884
2885 if (cflag & CMSPAR) {
2886 /* enable stick parity, PARODD mean Mark which matches ETRAX */
2887 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_stick_par, stick);
2888 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_stick_par, stick);
2889 }
2890 if (cflag & PARODD) {
2891 /* set odd parity (or Mark if CMSPAR) */
2892 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_par, odd);
2893 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_par, odd);
2894 }
2895
2896 if (cflag & CRTSCTS) {
2897 /* enable automatic CTS handling */
2898 DFLOW(DEBUG_LOG(info->line, "FLOW auto_cts enabled\n", 0));
2899 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, auto_cts, active);
2900 }
2901
2902 /* make sure the tx and rx are enabled */
2903
2904 info->tx_ctrl |= IO_STATE(R_SERIAL0_TR_CTRL, tr_enable, enable);
2905 info->rx_ctrl |= IO_STATE(R_SERIAL0_REC_CTRL, rec_enable, enable);
2906
2907 /* actually write the control regs to the hardware */
2908
2909 info->ioport[REG_TR_CTRL] = info->tx_ctrl;
2910 info->ioport[REG_REC_CTRL] = info->rx_ctrl;
2911 xoff = IO_FIELD(R_SERIAL0_XOFF, xoff_char, STOP_CHAR(info->port.tty));
2912 xoff |= IO_STATE(R_SERIAL0_XOFF, tx_stop, enable);
2913 if (info->port.tty->termios.c_iflag & IXON ) {
2914 DFLOW(DEBUG_LOG(info->line, "FLOW XOFF enabled 0x%02X\n",
2915 STOP_CHAR(info->port.tty)));
2916 xoff |= IO_STATE(R_SERIAL0_XOFF, auto_xoff, enable);
2917 }
2918
2919 *((unsigned long *)&info->ioport[REG_XOFF]) = xoff;
2920 local_irq_restore(flags);
2921
2922 update_char_time(info);
2923
2924 } /* change_speed */
2925
2926 /* start transmitting chars NOW */
2927
2928 static void
2929 rs_flush_chars(struct tty_struct *tty)
2930 {
2931 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
2932 unsigned long flags;
2933
2934 if (info->tr_running ||
2935 info->xmit.head == info->xmit.tail ||
2936 tty->stopped ||
2937 !info->xmit.buf)
2938 return;
2939
2940 #ifdef SERIAL_DEBUG_FLOW
2941 printk("rs_flush_chars\n");
2942 #endif
2943
2944 /* this protection might not exactly be necessary here */
2945
2946 local_irq_save(flags);
2947 start_transmit(info);
2948 local_irq_restore(flags);
2949 }
2950
2951 static int rs_raw_write(struct tty_struct *tty,
2952 const unsigned char *buf, int count)
2953 {
2954 int c, ret = 0;
2955 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
2956 unsigned long flags;
2957
2958 /* first some sanity checks */
2959
2960 if (!info->xmit.buf)
2961 return 0;
2962
2963 #ifdef SERIAL_DEBUG_DATA
2964 if (info->line == SERIAL_DEBUG_LINE)
2965 printk("rs_raw_write (%d), status %d\n",
2966 count, info->ioport[REG_STATUS]);
2967 #endif
2968
2969 local_save_flags(flags);
2970 DFLOW(DEBUG_LOG(info->line, "write count %i ", count));
2971 DFLOW(DEBUG_LOG(info->line, "ldisc %i\n", tty->ldisc.chars_in_buffer(tty)));
2972
2973
2974 /* The local_irq_disable/restore_flags pairs below are needed
2975 * because the DMA interrupt handler moves the info->xmit values.
2976 * the memcpy needs to be in the critical region unfortunately,
2977 * because we need to read xmit values, memcpy, write xmit values
2978 * in one atomic operation... this could perhaps be avoided by
2979 * more clever design.
2980 */
2981 local_irq_disable();
2982 while (count) {
2983 c = CIRC_SPACE_TO_END(info->xmit.head,
2984 info->xmit.tail,
2985 SERIAL_XMIT_SIZE);
2986
2987 if (count < c)
2988 c = count;
2989 if (c <= 0)
2990 break;
2991
2992 memcpy(info->xmit.buf + info->xmit.head, buf, c);
2993 info->xmit.head = (info->xmit.head + c) &
2994 (SERIAL_XMIT_SIZE-1);
2995 buf += c;
2996 count -= c;
2997 ret += c;
2998 }
2999 local_irq_restore(flags);
3000
3001 /* enable transmitter if not running, unless the tty is stopped
3002 * this does not need IRQ protection since if tr_running == 0
3003 * the IRQ's are not running anyway for this port.
3004 */
3005 DFLOW(DEBUG_LOG(info->line, "write ret %i\n", ret));
3006
3007 if (info->xmit.head != info->xmit.tail &&
3008 !tty->stopped &&
3009 !info->tr_running) {
3010 start_transmit(info);
3011 }
3012
3013 return ret;
3014 } /* raw_raw_write() */
3015
3016 static int
3017 rs_write(struct tty_struct *tty,
3018 const unsigned char *buf, int count)
3019 {
3020 #if defined(CONFIG_ETRAX_RS485)
3021 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3022
3023 if (info->rs485.flags & SER_RS485_ENABLED)
3024 {
3025 /* If we are in RS-485 mode, we need to toggle RTS and disable
3026 * the receiver before initiating a DMA transfer
3027 */
3028 #ifdef CONFIG_ETRAX_FAST_TIMER
3029 /* Abort any started timer */
3030 fast_timers_rs485[info->line].function = NULL;
3031 del_fast_timer(&fast_timers_rs485[info->line]);
3032 #endif
3033 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_ON_SEND));
3034 #if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3035 e100_disable_rx(info);
3036 e100_enable_rx_irq(info);
3037 #endif
3038 if (info->rs485.delay_rts_before_send > 0)
3039 msleep(info->rs485.delay_rts_before_send);
3040 }
3041 #endif /* CONFIG_ETRAX_RS485 */
3042
3043 count = rs_raw_write(tty, buf, count);
3044
3045 #if defined(CONFIG_ETRAX_RS485)
3046 if (info->rs485.flags & SER_RS485_ENABLED)
3047 {
3048 unsigned int val;
3049 /* If we are in RS-485 mode the following has to be done:
3050 * wait until DMA is ready
3051 * wait on transmit shift register
3052 * toggle RTS
3053 * enable the receiver
3054 */
3055
3056 /* Sleep until all sent */
3057 tty_wait_until_sent(tty, 0);
3058 #ifdef CONFIG_ETRAX_FAST_TIMER
3059 /* Now sleep a little more so that shift register is empty */
3060 schedule_usleep(info->char_time_usec * 2);
3061 #endif
3062 /* wait on transmit shift register */
3063 do{
3064 get_lsr_info(info, &val);
3065 }while (!(val & TIOCSER_TEMT));
3066
3067 e100_rts(info, (info->rs485.flags & SER_RS485_RTS_AFTER_SEND));
3068
3069 #if defined(CONFIG_ETRAX_RS485_DISABLE_RECEIVER)
3070 e100_enable_rx(info);
3071 e100_enable_rxdma_irq(info);
3072 #endif
3073 }
3074 #endif /* CONFIG_ETRAX_RS485 */
3075
3076 return count;
3077 } /* rs_write */
3078
3079
3080 /* how much space is available in the xmit buffer? */
3081
3082 static int
3083 rs_write_room(struct tty_struct *tty)
3084 {
3085 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3086
3087 return CIRC_SPACE(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
3088 }
3089
3090 /* How many chars are in the xmit buffer?
3091 * This does not include any chars in the transmitter FIFO.
3092 * Use wait_until_sent for waiting for FIFO drain.
3093 */
3094
3095 static int
3096 rs_chars_in_buffer(struct tty_struct *tty)
3097 {
3098 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3099
3100 return CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
3101 }
3102
3103 /* discard everything in the xmit buffer */
3104
3105 static void
3106 rs_flush_buffer(struct tty_struct *tty)
3107 {
3108 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3109 unsigned long flags;
3110
3111 local_irq_save(flags);
3112 info->xmit.head = info->xmit.tail = 0;
3113 local_irq_restore(flags);
3114
3115 tty_wakeup(tty);
3116 }
3117
3118 /*
3119 * This function is used to send a high-priority XON/XOFF character to
3120 * the device
3121 *
3122 * Since we use DMA we don't check for info->x_char in transmit_chars_dma(),
3123 * but we do it in handle_ser_tx_interrupt().
3124 * We disable DMA channel and enable tx ready interrupt and write the
3125 * character when possible.
3126 */
3127 static void rs_send_xchar(struct tty_struct *tty, char ch)
3128 {
3129 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3130 unsigned long flags;
3131 local_irq_save(flags);
3132 if (info->uses_dma_out) {
3133 /* Put the DMA on hold and disable the channel */
3134 *info->ocmdadr = IO_STATE(R_DMA_CH6_CMD, cmd, hold);
3135 while (IO_EXTRACT(R_DMA_CH6_CMD, cmd, *info->ocmdadr) !=
3136 IO_STATE_VALUE(R_DMA_CH6_CMD, cmd, hold));
3137 e100_disable_txdma_channel(info);
3138 }
3139
3140 /* Must make sure transmitter is not stopped before we can transmit */
3141 if (tty->stopped)
3142 rs_start(tty);
3143
3144 /* Enable manual transmit interrupt and send from there */
3145 DFLOW(DEBUG_LOG(info->line, "rs_send_xchar 0x%02X\n", ch));
3146 info->x_char = ch;
3147 e100_enable_serial_tx_ready_irq(info);
3148 local_irq_restore(flags);
3149 }
3150
3151 /*
3152 * ------------------------------------------------------------
3153 * rs_throttle()
3154 *
3155 * This routine is called by the upper-layer tty layer to signal that
3156 * incoming characters should be throttled.
3157 * ------------------------------------------------------------
3158 */
3159 static void
3160 rs_throttle(struct tty_struct * tty)
3161 {
3162 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3163 #ifdef SERIAL_DEBUG_THROTTLE
3164 printk("throttle %s: %lu....\n", tty_name(tty),
3165 (unsigned long)tty->ldisc.chars_in_buffer(tty));
3166 #endif
3167 DFLOW(DEBUG_LOG(info->line,"rs_throttle %lu\n", tty->ldisc.chars_in_buffer(tty)));
3168
3169 /* Do RTS before XOFF since XOFF might take some time */
3170 if (tty->termios.c_cflag & CRTSCTS) {
3171 /* Turn off RTS line */
3172 e100_rts(info, 0);
3173 }
3174 if (I_IXOFF(tty))
3175 rs_send_xchar(tty, STOP_CHAR(tty));
3176
3177 }
3178
3179 static void
3180 rs_unthrottle(struct tty_struct * tty)
3181 {
3182 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3183 #ifdef SERIAL_DEBUG_THROTTLE
3184 printk("unthrottle %s: %lu....\n", tty_name(tty),
3185 (unsigned long)tty->ldisc.chars_in_buffer(tty));
3186 #endif
3187 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle ldisc %d\n", tty->ldisc.chars_in_buffer(tty)));
3188 DFLOW(DEBUG_LOG(info->line,"rs_unthrottle flip.count: %i\n", tty->flip.count));
3189 /* Do RTS before XOFF since XOFF might take some time */
3190 if (tty->termios.c_cflag & CRTSCTS) {
3191 /* Assert RTS line */
3192 e100_rts(info, 1);
3193 }
3194
3195 if (I_IXOFF(tty)) {
3196 if (info->x_char)
3197 info->x_char = 0;
3198 else
3199 rs_send_xchar(tty, START_CHAR(tty));
3200 }
3201
3202 }
3203
3204 /*
3205 * ------------------------------------------------------------
3206 * rs_ioctl() and friends
3207 * ------------------------------------------------------------
3208 */
3209
3210 static int
3211 get_serial_info(struct e100_serial * info,
3212 struct serial_struct * retinfo)
3213 {
3214 struct serial_struct tmp;
3215
3216 /* this is all probably wrong, there are a lot of fields
3217 * here that we don't have in e100_serial and maybe we
3218 * should set them to something else than 0.
3219 */
3220
3221 if (!retinfo)
3222 return -EFAULT;
3223 memset(&tmp, 0, sizeof(tmp));
3224 tmp.type = info->type;
3225 tmp.line = info->line;
3226 tmp.port = (int)info->ioport;
3227 tmp.irq = info->irq;
3228 tmp.flags = info->port.flags;
3229 tmp.baud_base = info->baud_base;
3230 tmp.close_delay = info->port.close_delay;
3231 tmp.closing_wait = info->port.closing_wait;
3232 tmp.custom_divisor = info->custom_divisor;
3233 if (copy_to_user(retinfo, &tmp, sizeof(*retinfo)))
3234 return -EFAULT;
3235 return 0;
3236 }
3237
3238 static int
3239 set_serial_info(struct e100_serial *info,
3240 struct serial_struct *new_info)
3241 {
3242 struct serial_struct new_serial;
3243 struct e100_serial old_info;
3244 int retval = 0;
3245
3246 if (copy_from_user(&new_serial, new_info, sizeof(new_serial)))
3247 return -EFAULT;
3248
3249 old_info = *info;
3250
3251 if (!capable(CAP_SYS_ADMIN)) {
3252 if ((new_serial.type != info->type) ||
3253 (new_serial.close_delay != info->port.close_delay) ||
3254 ((new_serial.flags & ~ASYNC_USR_MASK) !=
3255 (info->port.flags & ~ASYNC_USR_MASK)))
3256 return -EPERM;
3257 info->port.flags = ((info->port.flags & ~ASYNC_USR_MASK) |
3258 (new_serial.flags & ASYNC_USR_MASK));
3259 goto check_and_exit;
3260 }
3261
3262 if (info->port.count > 1)
3263 return -EBUSY;
3264
3265 /*
3266 * OK, past this point, all the error checking has been done.
3267 * At this point, we start making changes.....
3268 */
3269
3270 info->baud_base = new_serial.baud_base;
3271 info->port.flags = ((info->port.flags & ~ASYNC_FLAGS) |
3272 (new_serial.flags & ASYNC_FLAGS));
3273 info->custom_divisor = new_serial.custom_divisor;
3274 info->type = new_serial.type;
3275 info->port.close_delay = new_serial.close_delay;
3276 info->port.closing_wait = new_serial.closing_wait;
3277 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3278
3279 check_and_exit:
3280 if (info->port.flags & ASYNC_INITIALIZED) {
3281 change_speed(info);
3282 } else
3283 retval = startup(info);
3284 return retval;
3285 }
3286
3287 /*
3288 * get_lsr_info - get line status register info
3289 *
3290 * Purpose: Let user call ioctl() to get info when the UART physically
3291 * is emptied. On bus types like RS485, the transmitter must
3292 * release the bus after transmitting. This must be done when
3293 * the transmit shift register is empty, not be done when the
3294 * transmit holding register is empty. This functionality
3295 * allows an RS485 driver to be written in user space.
3296 */
3297 static int
3298 get_lsr_info(struct e100_serial * info, unsigned int *value)
3299 {
3300 unsigned int result = TIOCSER_TEMT;
3301 unsigned long curr_time = jiffies;
3302 unsigned long curr_time_usec = GET_JIFFIES_USEC();
3303 unsigned long elapsed_usec =
3304 (curr_time - info->last_tx_active) * 1000000/HZ +
3305 curr_time_usec - info->last_tx_active_usec;
3306
3307 if (info->xmit.head != info->xmit.tail ||
3308 elapsed_usec < 2*info->char_time_usec) {
3309 result = 0;
3310 }
3311
3312 if (copy_to_user(value, &result, sizeof(int)))
3313 return -EFAULT;
3314 return 0;
3315 }
3316
3317 #ifdef SERIAL_DEBUG_IO
3318 struct state_str
3319 {
3320 int state;
3321 const char *str;
3322 };
3323
3324 const struct state_str control_state_str[] = {
3325 {TIOCM_DTR, "DTR" },
3326 {TIOCM_RTS, "RTS"},
3327 {TIOCM_ST, "ST?" },
3328 {TIOCM_SR, "SR?" },
3329 {TIOCM_CTS, "CTS" },
3330 {TIOCM_CD, "CD" },
3331 {TIOCM_RI, "RI" },
3332 {TIOCM_DSR, "DSR" },
3333 {0, NULL }
3334 };
3335
3336 char *get_control_state_str(int MLines, char *s)
3337 {
3338 int i = 0;
3339
3340 s[0]='\0';
3341 while (control_state_str[i].str != NULL) {
3342 if (MLines & control_state_str[i].state) {
3343 if (s[0] != '\0') {
3344 strcat(s, ", ");
3345 }
3346 strcat(s, control_state_str[i].str);
3347 }
3348 i++;
3349 }
3350 return s;
3351 }
3352 #endif
3353
3354 static int
3355 rs_break(struct tty_struct *tty, int break_state)
3356 {
3357 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3358 unsigned long flags;
3359
3360 if (!info->ioport)
3361 return -EIO;
3362
3363 local_irq_save(flags);
3364 if (break_state == -1) {
3365 /* Go to manual mode and set the txd pin to 0 */
3366 /* Clear bit 7 (txd) and 6 (tr_enable) */
3367 info->tx_ctrl &= 0x3F;
3368 } else {
3369 /* Set bit 7 (txd) and 6 (tr_enable) */
3370 info->tx_ctrl |= (0x80 | 0x40);
3371 }
3372 info->ioport[REG_TR_CTRL] = info->tx_ctrl;
3373 local_irq_restore(flags);
3374 return 0;
3375 }
3376
3377 static int
3378 rs_tiocmset(struct tty_struct *tty, unsigned int set, unsigned int clear)
3379 {
3380 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3381 unsigned long flags;
3382
3383 local_irq_save(flags);
3384
3385 if (clear & TIOCM_RTS)
3386 e100_rts(info, 0);
3387 if (clear & TIOCM_DTR)
3388 e100_dtr(info, 0);
3389 /* Handle FEMALE behaviour */
3390 if (clear & TIOCM_RI)
3391 e100_ri_out(info, 0);
3392 if (clear & TIOCM_CD)
3393 e100_cd_out(info, 0);
3394
3395 if (set & TIOCM_RTS)
3396 e100_rts(info, 1);
3397 if (set & TIOCM_DTR)
3398 e100_dtr(info, 1);
3399 /* Handle FEMALE behaviour */
3400 if (set & TIOCM_RI)
3401 e100_ri_out(info, 1);
3402 if (set & TIOCM_CD)
3403 e100_cd_out(info, 1);
3404
3405 local_irq_restore(flags);
3406 return 0;
3407 }
3408
3409 static int
3410 rs_tiocmget(struct tty_struct *tty)
3411 {
3412 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3413 unsigned int result;
3414 unsigned long flags;
3415
3416 local_irq_save(flags);
3417
3418 result =
3419 (!E100_RTS_GET(info) ? TIOCM_RTS : 0)
3420 | (!E100_DTR_GET(info) ? TIOCM_DTR : 0)
3421 | (!E100_RI_GET(info) ? TIOCM_RNG : 0)
3422 | (!E100_DSR_GET(info) ? TIOCM_DSR : 0)
3423 | (!E100_CD_GET(info) ? TIOCM_CAR : 0)
3424 | (!E100_CTS_GET(info) ? TIOCM_CTS : 0);
3425
3426 local_irq_restore(flags);
3427
3428 #ifdef SERIAL_DEBUG_IO
3429 printk(KERN_DEBUG "ser%i: modem state: %i 0x%08X\n",
3430 info->line, result, result);
3431 {
3432 char s[100];
3433
3434 get_control_state_str(result, s);
3435 printk(KERN_DEBUG "state: %s\n", s);
3436 }
3437 #endif
3438 return result;
3439
3440 }
3441
3442
3443 static int
3444 rs_ioctl(struct tty_struct *tty,
3445 unsigned int cmd, unsigned long arg)
3446 {
3447 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3448
3449 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
3450 (cmd != TIOCSERCONFIG) && (cmd != TIOCSERGWILD) &&
3451 (cmd != TIOCSERSWILD) && (cmd != TIOCSERGSTRUCT)) {
3452 if (tty->flags & (1 << TTY_IO_ERROR))
3453 return -EIO;
3454 }
3455
3456 switch (cmd) {
3457 case TIOCGSERIAL:
3458 return get_serial_info(info,
3459 (struct serial_struct *) arg);
3460 case TIOCSSERIAL:
3461 return set_serial_info(info,
3462 (struct serial_struct *) arg);
3463 case TIOCSERGETLSR: /* Get line status register */
3464 return get_lsr_info(info, (unsigned int *) arg);
3465
3466 case TIOCSERGSTRUCT:
3467 if (copy_to_user((struct e100_serial *) arg,
3468 info, sizeof(struct e100_serial)))
3469 return -EFAULT;
3470 return 0;
3471
3472 #if defined(CONFIG_ETRAX_RS485)
3473 case TIOCSERSETRS485:
3474 {
3475 /* In this ioctl we still use the old structure
3476 * rs485_control for backward compatibility
3477 * (if we use serial_rs485, then old user-level code
3478 * wouldn't work anymore...).
3479 * The use of this ioctl is deprecated: use TIOCSRS485
3480 * instead.*/
3481 struct rs485_control rs485ctrl;
3482 struct serial_rs485 rs485data;
3483 printk(KERN_DEBUG "The use of this ioctl is deprecated. Use TIOCSRS485 instead\n");
3484 if (copy_from_user(&rs485ctrl, (struct rs485_control *)arg,
3485 sizeof(rs485ctrl)))
3486 return -EFAULT;
3487
3488 rs485data.delay_rts_before_send = rs485ctrl.delay_rts_before_send;
3489 rs485data.flags = 0;
3490
3491 if (rs485ctrl.enabled)
3492 rs485data.flags |= SER_RS485_ENABLED;
3493 else
3494 rs485data.flags &= ~(SER_RS485_ENABLED);
3495
3496 if (rs485ctrl.rts_on_send)
3497 rs485data.flags |= SER_RS485_RTS_ON_SEND;
3498 else
3499 rs485data.flags &= ~(SER_RS485_RTS_ON_SEND);
3500
3501 if (rs485ctrl.rts_after_sent)
3502 rs485data.flags |= SER_RS485_RTS_AFTER_SEND;
3503 else
3504 rs485data.flags &= ~(SER_RS485_RTS_AFTER_SEND);
3505
3506 return e100_enable_rs485(tty, &rs485data);
3507 }
3508
3509 case TIOCSRS485:
3510 {
3511 /* This is the new version of TIOCSRS485, with new
3512 * data structure serial_rs485 */
3513 struct serial_rs485 rs485data;
3514 if (copy_from_user(&rs485data, (struct rs485_control *)arg,
3515 sizeof(rs485data)))
3516 return -EFAULT;
3517
3518 return e100_enable_rs485(tty, &rs485data);
3519 }
3520
3521 case TIOCGRS485:
3522 {
3523 struct serial_rs485 *rs485data =
3524 &(((struct e100_serial *)tty->driver_data)->rs485);
3525 /* This is the ioctl to get RS485 data from user-space */
3526 if (copy_to_user((struct serial_rs485 *) arg,
3527 rs485data,
3528 sizeof(struct serial_rs485)))
3529 return -EFAULT;
3530 break;
3531 }
3532
3533 case TIOCSERWRRS485:
3534 {
3535 struct rs485_write rs485wr;
3536 if (copy_from_user(&rs485wr, (struct rs485_write *)arg,
3537 sizeof(rs485wr)))
3538 return -EFAULT;
3539
3540 return e100_write_rs485(tty, rs485wr.outc, rs485wr.outc_size);
3541 }
3542 #endif
3543
3544 default:
3545 return -ENOIOCTLCMD;
3546 }
3547 return 0;
3548 }
3549
3550 static void
3551 rs_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
3552 {
3553 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3554
3555 change_speed(info);
3556
3557 /* Handle turning off CRTSCTS */
3558 if ((old_termios->c_cflag & CRTSCTS) &&
3559 !(tty->termios.c_cflag & CRTSCTS))
3560 rs_start(tty);
3561
3562 }
3563
3564 /*
3565 * ------------------------------------------------------------
3566 * rs_close()
3567 *
3568 * This routine is called when the serial port gets closed. First, we
3569 * wait for the last remaining data to be sent. Then, we unlink its
3570 * S structure from the interrupt chain if necessary, and we free
3571 * that IRQ if nothing is left in the chain.
3572 * ------------------------------------------------------------
3573 */
3574 static void
3575 rs_close(struct tty_struct *tty, struct file * filp)
3576 {
3577 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3578 unsigned long flags;
3579
3580 if (!info)
3581 return;
3582
3583 /* interrupts are disabled for this entire function */
3584
3585 local_irq_save(flags);
3586
3587 if (tty_hung_up_p(filp)) {
3588 local_irq_restore(flags);
3589 return;
3590 }
3591
3592 #ifdef SERIAL_DEBUG_OPEN
3593 printk("[%d] rs_close ttyS%d, count = %d\n", current->pid,
3594 info->line, info->count);
3595 #endif
3596 if ((tty->count == 1) && (info->port.count != 1)) {
3597 /*
3598 * Uh, oh. tty->count is 1, which means that the tty
3599 * structure will be freed. Info->count should always
3600 * be one in these conditions. If it's greater than
3601 * one, we've got real problems, since it means the
3602 * serial port won't be shutdown.
3603 */
3604 printk(KERN_ERR
3605 "rs_close: bad serial port count; tty->count is 1, "
3606 "info->count is %d\n", info->port.count);
3607 info->port.count = 1;
3608 }
3609 if (--info->port.count < 0) {
3610 printk(KERN_ERR "rs_close: bad serial port count for ttyS%d: %d\n",
3611 info->line, info->port.count);
3612 info->port.count = 0;
3613 }
3614 if (info->port.count) {
3615 local_irq_restore(flags);
3616 return;
3617 }
3618 info->port.flags |= ASYNC_CLOSING;
3619 /*
3620 * Now we wait for the transmit buffer to clear; and we notify
3621 * the line discipline to only process XON/XOFF characters.
3622 */
3623 tty->closing = 1;
3624 if (info->port.closing_wait != ASYNC_CLOSING_WAIT_NONE)
3625 tty_wait_until_sent(tty, info->port.closing_wait);
3626 /*
3627 * At this point we stop accepting input. To do this, we
3628 * disable the serial receiver and the DMA receive interrupt.
3629 */
3630 #ifdef SERIAL_HANDLE_EARLY_ERRORS
3631 e100_disable_serial_data_irq(info);
3632 #endif
3633
3634 e100_disable_rx(info);
3635 e100_disable_rx_irq(info);
3636
3637 if (info->port.flags & ASYNC_INITIALIZED) {
3638 /*
3639 * Before we drop DTR, make sure the UART transmitter
3640 * has completely drained; this is especially
3641 * important as we have a transmit FIFO!
3642 */
3643 rs_wait_until_sent(tty, HZ);
3644 }
3645
3646 shutdown(info);
3647 rs_flush_buffer(tty);
3648 tty_ldisc_flush(tty);
3649 tty->closing = 0;
3650 info->event = 0;
3651 info->port.tty = NULL;
3652 if (info->port.blocked_open) {
3653 if (info->port.close_delay)
3654 schedule_timeout_interruptible(info->port.close_delay);
3655 wake_up_interruptible(&info->port.open_wait);
3656 }
3657 info->port.flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
3658 local_irq_restore(flags);
3659
3660 /* port closed */
3661
3662 #if defined(CONFIG_ETRAX_RS485)
3663 if (info->rs485.flags & SER_RS485_ENABLED) {
3664 info->rs485.flags &= ~(SER_RS485_ENABLED);
3665 #if defined(CONFIG_ETRAX_RS485_ON_PA)
3666 *R_PORT_PA_DATA = port_pa_data_shadow &= ~(1 << rs485_pa_bit);
3667 #endif
3668 }
3669 #endif
3670
3671 /*
3672 * Release any allocated DMA irq's.
3673 */
3674 if (info->dma_in_enabled) {
3675 free_irq(info->dma_in_irq_nbr, info);
3676 cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description);
3677 info->uses_dma_in = 0;
3678 #ifdef SERIAL_DEBUG_OPEN
3679 printk(KERN_DEBUG "DMA irq '%s' freed\n",
3680 info->dma_in_irq_description);
3681 #endif
3682 }
3683 if (info->dma_out_enabled) {
3684 free_irq(info->dma_out_irq_nbr, info);
3685 cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description);
3686 info->uses_dma_out = 0;
3687 #ifdef SERIAL_DEBUG_OPEN
3688 printk(KERN_DEBUG "DMA irq '%s' freed\n",
3689 info->dma_out_irq_description);
3690 #endif
3691 }
3692 }
3693
3694 /*
3695 * rs_wait_until_sent() --- wait until the transmitter is empty
3696 */
3697 static void rs_wait_until_sent(struct tty_struct *tty, int timeout)
3698 {
3699 unsigned long orig_jiffies;
3700 struct e100_serial *info = (struct e100_serial *)tty->driver_data;
3701 unsigned long curr_time = jiffies;
3702 unsigned long curr_time_usec = GET_JIFFIES_USEC();
3703 long elapsed_usec =
3704 (curr_time - info->last_tx_active) * (1000000/HZ) +
3705 curr_time_usec - info->last_tx_active_usec;
3706
3707 /*
3708 * Check R_DMA_CHx_STATUS bit 0-6=number of available bytes in FIFO
3709 * R_DMA_CHx_HWSW bit 31-16=nbr of bytes left in DMA buffer (0=64k)
3710 */
3711 orig_jiffies = jiffies;
3712 while (info->xmit.head != info->xmit.tail || /* More in send queue */
3713 (*info->ostatusadr & 0x007f) || /* more in FIFO */
3714 (elapsed_usec < 2*info->char_time_usec)) {
3715 schedule_timeout_interruptible(1);
3716 if (signal_pending(current))
3717 break;
3718 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3719 break;
3720 curr_time = jiffies;
3721 curr_time_usec = GET_JIFFIES_USEC();
3722 elapsed_usec =
3723 (curr_time - info->last_tx_active) * (1000000/HZ) +
3724 curr_time_usec - info->last_tx_active_usec;
3725 }
3726 set_current_state(TASK_RUNNING);
3727 }
3728
3729 /*
3730 * rs_hangup() --- called by tty_hangup() when a hangup is signaled.
3731 */
3732 void
3733 rs_hangup(struct tty_struct *tty)
3734 {
3735 struct e100_serial * info = (struct e100_serial *)tty->driver_data;
3736
3737 rs_flush_buffer(tty);
3738 shutdown(info);
3739 info->event = 0;
3740 info->port.count = 0;
3741 info->port.flags &= ~ASYNC_NORMAL_ACTIVE;
3742 info->port.tty = NULL;
3743 wake_up_interruptible(&info->port.open_wait);
3744 }
3745
3746 /*
3747 * ------------------------------------------------------------
3748 * rs_open() and friends
3749 * ------------------------------------------------------------
3750 */
3751 static int
3752 block_til_ready(struct tty_struct *tty, struct file * filp,
3753 struct e100_serial *info)
3754 {
3755 DECLARE_WAITQUEUE(wait, current);
3756 unsigned long flags;
3757 int retval;
3758 int do_clocal = 0;
3759
3760 /*
3761 * If non-blocking mode is set, or the port is not enabled,
3762 * then make the check up front and then exit.
3763 */
3764 if ((filp->f_flags & O_NONBLOCK) ||
3765 (tty->flags & (1 << TTY_IO_ERROR))) {
3766 info->port.flags |= ASYNC_NORMAL_ACTIVE;
3767 return 0;
3768 }
3769
3770 if (tty->termios.c_cflag & CLOCAL) {
3771 do_clocal = 1;
3772 }
3773
3774 /*
3775 * Block waiting for the carrier detect and the line to become
3776 * free (i.e., not in use by the callout). While we are in
3777 * this loop, info->port.count is dropped by one, so that
3778 * rs_close() knows when to free things. We restore it upon
3779 * exit, either normal or abnormal.
3780 */
3781 retval = 0;
3782 add_wait_queue(&info->port.open_wait, &wait);
3783 #ifdef SERIAL_DEBUG_OPEN
3784 printk("block_til_ready before block: ttyS%d, count = %d\n",
3785 info->line, info->port.count);
3786 #endif
3787 local_irq_save(flags);
3788 info->port.count--;
3789 local_irq_restore(flags);
3790 info->port.blocked_open++;
3791 while (1) {
3792 local_irq_save(flags);
3793 /* assert RTS and DTR */
3794 e100_rts(info, 1);
3795 e100_dtr(info, 1);
3796 local_irq_restore(flags);
3797 set_current_state(TASK_INTERRUPTIBLE);
3798 if (tty_hung_up_p(filp) ||
3799 !(info->port.flags & ASYNC_INITIALIZED)) {
3800 #ifdef SERIAL_DO_RESTART
3801 if (info->port.flags & ASYNC_HUP_NOTIFY)
3802 retval = -EAGAIN;
3803 else
3804 retval = -ERESTARTSYS;
3805 #else
3806 retval = -EAGAIN;
3807 #endif
3808 break;
3809 }
3810 if (do_clocal)
3811 /* && (do_clocal || DCD_IS_ASSERTED) */
3812 break;
3813 if (signal_pending(current)) {
3814 retval = -ERESTARTSYS;
3815 break;
3816 }
3817 #ifdef SERIAL_DEBUG_OPEN
3818 printk("block_til_ready blocking: ttyS%d, count = %d\n",
3819 info->line, info->port.count);
3820 #endif
3821 tty_unlock(tty);
3822 schedule();
3823 tty_lock(tty);
3824 }
3825 set_current_state(TASK_RUNNING);
3826 remove_wait_queue(&info->port.open_wait, &wait);
3827 if (!tty_hung_up_p(filp))
3828 info->port.count++;
3829 info->port.blocked_open--;
3830 #ifdef SERIAL_DEBUG_OPEN
3831 printk("block_til_ready after blocking: ttyS%d, count = %d\n",
3832 info->line, info->port.count);
3833 #endif
3834 if (retval)
3835 return retval;
3836 info->port.flags |= ASYNC_NORMAL_ACTIVE;
3837 return 0;
3838 }
3839
3840 static void
3841 deinit_port(struct e100_serial *info)
3842 {
3843 if (info->dma_out_enabled) {
3844 cris_free_dma(info->dma_out_nbr, info->dma_out_irq_description);
3845 free_irq(info->dma_out_irq_nbr, info);
3846 }
3847 if (info->dma_in_enabled) {
3848 cris_free_dma(info->dma_in_nbr, info->dma_in_irq_description);
3849 free_irq(info->dma_in_irq_nbr, info);
3850 }
3851 }
3852
3853 /*
3854 * This routine is called whenever a serial port is opened.
3855 * It performs the serial-specific initialization for the tty structure.
3856 */
3857 static int
3858 rs_open(struct tty_struct *tty, struct file * filp)
3859 {
3860 struct e100_serial *info;
3861 int retval;
3862 int allocated_resources = 0;
3863
3864 info = rs_table + tty->index;
3865 if (!info->enabled)
3866 return -ENODEV;
3867
3868 #ifdef SERIAL_DEBUG_OPEN
3869 printk("[%d] rs_open %s, count = %d\n", current->pid, tty->name,
3870 info->port.count);
3871 #endif
3872
3873 info->port.count++;
3874 tty->driver_data = info;
3875 info->port.tty = tty;
3876
3877 info->port.low_latency = !!(info->port.flags & ASYNC_LOW_LATENCY);
3878
3879 /*
3880 * If DMA is enabled try to allocate the irq's.
3881 */
3882 if (info->port.count == 1) {
3883 allocated_resources = 1;
3884 if (info->dma_in_enabled) {
3885 if (request_irq(info->dma_in_irq_nbr,
3886 rec_interrupt,
3887 info->dma_in_irq_flags,
3888 info->dma_in_irq_description,
3889 info)) {
3890 printk(KERN_WARNING "DMA irq '%s' busy; "
3891 "falling back to non-DMA mode\n",
3892 info->dma_in_irq_description);
3893 /* Make sure we never try to use DMA in */
3894 /* for the port again. */
3895 info->dma_in_enabled = 0;
3896 } else if (cris_request_dma(info->dma_in_nbr,
3897 info->dma_in_irq_description,
3898 DMA_VERBOSE_ON_ERROR,
3899 info->dma_owner)) {
3900 free_irq(info->dma_in_irq_nbr, info);
3901 printk(KERN_WARNING "DMA '%s' busy; "
3902 "falling back to non-DMA mode\n",
3903 info->dma_in_irq_description);
3904 /* Make sure we never try to use DMA in */
3905 /* for the port again. */
3906 info->dma_in_enabled = 0;
3907 }
3908 #ifdef SERIAL_DEBUG_OPEN
3909 else
3910 printk(KERN_DEBUG "DMA irq '%s' allocated\n",
3911 info->dma_in_irq_description);
3912 #endif
3913 }
3914 if (info->dma_out_enabled) {
3915 if (request_irq(info->dma_out_irq_nbr,
3916 tr_interrupt,
3917 info->dma_out_irq_flags,
3918 info->dma_out_irq_description,
3919 info)) {
3920 printk(KERN_WARNING "DMA irq '%s' busy; "
3921 "falling back to non-DMA mode\n",
3922 info->dma_out_irq_description);
3923 /* Make sure we never try to use DMA out */
3924 /* for the port again. */
3925 info->dma_out_enabled = 0;
3926 } else if (cris_request_dma(info->dma_out_nbr,
3927 info->dma_out_irq_description,
3928 DMA_VERBOSE_ON_ERROR,
3929 info->dma_owner)) {
3930 free_irq(info->dma_out_irq_nbr, info);
3931 printk(KERN_WARNING "DMA '%s' busy; "
3932 "falling back to non-DMA mode\n",
3933 info->dma_out_irq_description);
3934 /* Make sure we never try to use DMA out */
3935 /* for the port again. */
3936 info->dma_out_enabled = 0;
3937 }
3938 #ifdef SERIAL_DEBUG_OPEN
3939 else
3940 printk(KERN_DEBUG "DMA irq '%s' allocated\n",
3941 info->dma_out_irq_description);
3942 #endif
3943 }
3944 }
3945
3946 /*
3947 * Start up the serial port
3948 */
3949
3950 retval = startup(info);
3951 if (retval) {
3952 if (allocated_resources)
3953 deinit_port(info);
3954
3955 /* FIXME Decrease count info->port.count here too? */
3956 return retval;
3957 }
3958
3959
3960 retval = block_til_ready(tty, filp, info);
3961 if (retval) {
3962 #ifdef SERIAL_DEBUG_OPEN
3963 printk("rs_open returning after block_til_ready with %d\n",
3964 retval);
3965 #endif
3966 if (allocated_resources)
3967 deinit_port(info);
3968
3969 return retval;
3970 }
3971
3972 #ifdef SERIAL_DEBUG_OPEN
3973 printk("rs_open ttyS%d successful...\n", info->line);
3974 #endif
3975 DLOG_INT_TRIG( log_int_pos = 0);
3976
3977 DFLIP( if (info->line == SERIAL_DEBUG_LINE) {
3978 info->icount.rx = 0;
3979 } );
3980
3981 return 0;
3982 }
3983
3984 #ifdef CONFIG_PROC_FS
3985 /*
3986 * /proc fs routines....
3987 */
3988
3989 static void seq_line_info(struct seq_file *m, struct e100_serial *info)
3990 {
3991 unsigned long tmp;
3992
3993 seq_printf(m, "%d: uart:E100 port:%lX irq:%d",
3994 info->line, (unsigned long)info->ioport, info->irq);
3995
3996 if (!info->ioport || (info->type == PORT_UNKNOWN)) {
3997 seq_printf(m, "\n");
3998 return;
3999 }
4000
4001 seq_printf(m, " baud:%d", info->baud);
4002 seq_printf(m, " tx:%lu rx:%lu",
4003 (unsigned long)info->icount.tx,
4004 (unsigned long)info->icount.rx);
4005 tmp = CIRC_CNT(info->xmit.head, info->xmit.tail, SERIAL_XMIT_SIZE);
4006 if (tmp)
4007 seq_printf(m, " tx_pend:%lu/%lu",
4008 (unsigned long)tmp,
4009 (unsigned long)SERIAL_XMIT_SIZE);
4010
4011 seq_printf(m, " rx_pend:%lu/%lu",
4012 (unsigned long)info->recv_cnt,
4013 (unsigned long)info->max_recv_cnt);
4014
4015 #if 1
4016 if (info->port.tty) {
4017 if (info->port.tty->stopped)
4018 seq_printf(m, " stopped:%i",
4019 (int)info->port.tty->stopped);
4020 }
4021
4022 {
4023 unsigned char rstat = info->ioport[REG_STATUS];
4024 if (rstat & IO_MASK(R_SERIAL0_STATUS, xoff_detect))
4025 seq_printf(m, " xoff_detect:1");
4026 }
4027
4028 #endif
4029
4030 if (info->icount.frame)
4031 seq_printf(m, " fe:%lu", (unsigned long)info->icount.frame);
4032
4033 if (info->icount.parity)
4034 seq_printf(m, " pe:%lu", (unsigned long)info->icount.parity);
4035
4036 if (info->icount.brk)
4037 seq_printf(m, " brk:%lu", (unsigned long)info->icount.brk);
4038
4039 if (info->icount.overrun)
4040 seq_printf(m, " oe:%lu", (unsigned long)info->icount.overrun);
4041
4042 /*
4043 * Last thing is the RS-232 status lines
4044 */
4045 if (!E100_RTS_GET(info))
4046 seq_puts(m, "|RTS");
4047 if (!E100_CTS_GET(info))
4048 seq_puts(m, "|CTS");
4049 if (!E100_DTR_GET(info))
4050 seq_puts(m, "|DTR");
4051 if (!E100_DSR_GET(info))
4052 seq_puts(m, "|DSR");
4053 if (!E100_CD_GET(info))
4054 seq_puts(m, "|CD");
4055 if (!E100_RI_GET(info))
4056 seq_puts(m, "|RI");
4057 seq_puts(m, "\n");
4058 }
4059
4060
4061 static int crisv10_proc_show(struct seq_file *m, void *v)
4062 {
4063 int i;
4064
4065 seq_printf(m, "serinfo:1.0 driver:%s\n", serial_version);
4066
4067 for (i = 0; i < NR_PORTS; i++) {
4068 if (!rs_table[i].enabled)
4069 continue;
4070 seq_line_info(m, &rs_table[i]);
4071 }
4072 #ifdef DEBUG_LOG_INCLUDED
4073 for (i = 0; i < debug_log_pos; i++) {
4074 seq_printf(m, "%-4i %lu.%lu ",
4075 i, debug_log[i].time,
4076 timer_data_to_ns(debug_log[i].timer_data));
4077 seq_printf(m, debug_log[i].string, debug_log[i].value);
4078 }
4079 seq_printf(m, "debug_log %i/%i\n", i, DEBUG_LOG_SIZE);
4080 debug_log_pos = 0;
4081 #endif
4082 return 0;
4083 }
4084
4085 static int crisv10_proc_open(struct inode *inode, struct file *file)
4086 {
4087 return single_open(file, crisv10_proc_show, NULL);
4088 }
4089
4090 static const struct file_operations crisv10_proc_fops = {
4091 .owner = THIS_MODULE,
4092 .open = crisv10_proc_open,
4093 .read = seq_read,
4094 .llseek = seq_lseek,
4095 .release = single_release,
4096 };
4097 #endif
4098
4099
4100 /* Finally, routines used to initialize the serial driver. */
4101
4102 static void show_serial_version(void)
4103 {
4104 printk(KERN_INFO
4105 "ETRAX 100LX serial-driver %s, "
4106 "(c) 2000-2004 Axis Communications AB\r\n",
4107 &serial_version[11]); /* "$Revision: x.yy" */
4108 }
4109
4110 /* rs_init inits the driver at boot (using the module_init chain) */
4111
4112 static const struct tty_operations rs_ops = {
4113 .open = rs_open,
4114 .close = rs_close,
4115 .write = rs_write,
4116 .flush_chars = rs_flush_chars,
4117 .write_room = rs_write_room,
4118 .chars_in_buffer = rs_chars_in_buffer,
4119 .flush_buffer = rs_flush_buffer,
4120 .ioctl = rs_ioctl,
4121 .throttle = rs_throttle,
4122 .unthrottle = rs_unthrottle,
4123 .set_termios = rs_set_termios,
4124 .stop = rs_stop,
4125 .start = rs_start,
4126 .hangup = rs_hangup,
4127 .break_ctl = rs_break,
4128 .send_xchar = rs_send_xchar,
4129 .wait_until_sent = rs_wait_until_sent,
4130 .tiocmget = rs_tiocmget,
4131 .tiocmset = rs_tiocmset,
4132 #ifdef CONFIG_PROC_FS
4133 .proc_fops = &crisv10_proc_fops,
4134 #endif
4135 };
4136
4137 static int __init rs_init(void)
4138 {
4139 int i;
4140 struct e100_serial *info;
4141 struct tty_driver *driver = alloc_tty_driver(NR_PORTS);
4142
4143 if (!driver)
4144 return -ENOMEM;
4145
4146 show_serial_version();
4147
4148 /* Setup the timed flush handler system */
4149
4150 #if !defined(CONFIG_ETRAX_SERIAL_FAST_TIMER)
4151 setup_timer(&flush_timer, timed_flush_handler, 0);
4152 mod_timer(&flush_timer, jiffies + 5);
4153 #endif
4154
4155 #if defined(CONFIG_ETRAX_RS485)
4156 #if defined(CONFIG_ETRAX_RS485_ON_PA)
4157 if (cris_io_interface_allocate_pins(if_serial_0, 'a', rs485_pa_bit,
4158 rs485_pa_bit)) {
4159 printk(KERN_ERR "ETRAX100LX serial: Could not allocate "
4160 "RS485 pin\n");
4161 put_tty_driver(driver);
4162 return -EBUSY;
4163 }
4164 #endif
4165 #endif
4166
4167 /* Initialize the tty_driver structure */
4168
4169 driver->driver_name = "serial";
4170 driver->name = "ttyS";
4171 driver->major = TTY_MAJOR;
4172 driver->minor_start = 64;
4173 driver->type = TTY_DRIVER_TYPE_SERIAL;
4174 driver->subtype = SERIAL_TYPE_NORMAL;
4175 driver->init_termios = tty_std_termios;
4176 driver->init_termios.c_cflag =
4177 B115200 | CS8 | CREAD | HUPCL | CLOCAL; /* is normally B9600 default... */
4178 driver->init_termios.c_ispeed = 115200;
4179 driver->init_termios.c_ospeed = 115200;
4180 driver->flags = TTY_DRIVER_REAL_RAW;
4181
4182 tty_set_operations(driver, &rs_ops);
4183 serial_driver = driver;
4184
4185 /* do some initializing for the separate ports */
4186 for (i = 0, info = rs_table; i < NR_PORTS; i++,info++) {
4187 if (info->enabled) {
4188 if (cris_request_io_interface(info->io_if,
4189 info->io_if_description)) {
4190 printk(KERN_ERR "ETRAX100LX async serial: "
4191 "Could not allocate IO pins for "
4192 "%s, port %d\n",
4193 info->io_if_description, i);
4194 info->enabled = 0;
4195 }
4196 }
4197 tty_port_init(&info->port);
4198 info->uses_dma_in = 0;
4199 info->uses_dma_out = 0;
4200 info->line = i;
4201 info->port.tty = NULL;
4202 info->type = PORT_ETRAX;
4203 info->tr_running = 0;
4204 info->forced_eop = 0;
4205 info->baud_base = DEF_BAUD_BASE;
4206 info->custom_divisor = 0;
4207 info->x_char = 0;
4208 info->event = 0;
4209 info->xmit.buf = NULL;
4210 info->xmit.tail = info->xmit.head = 0;
4211 info->first_recv_buffer = info->last_recv_buffer = NULL;
4212 info->recv_cnt = info->max_recv_cnt = 0;
4213 info->last_tx_active_usec = 0;
4214 info->last_tx_active = 0;
4215
4216 #if defined(CONFIG_ETRAX_RS485)
4217 /* Set sane defaults */
4218 info->rs485.flags &= ~(SER_RS485_RTS_ON_SEND);
4219 info->rs485.flags |= SER_RS485_RTS_AFTER_SEND;
4220 info->rs485.delay_rts_before_send = 0;
4221 info->rs485.flags &= ~(SER_RS485_ENABLED);
4222 #endif
4223 INIT_WORK(&info->work, do_softint);
4224
4225 if (info->enabled) {
4226 printk(KERN_INFO "%s%d at %p is a builtin UART with DMA\n",
4227 serial_driver->name, info->line, info->ioport);
4228 }
4229 tty_port_link_device(&info->port, driver, i);
4230 }
4231
4232 if (tty_register_driver(driver))
4233 panic("Couldn't register serial driver\n");
4234
4235 #ifdef CONFIG_ETRAX_FAST_TIMER
4236 #ifdef CONFIG_ETRAX_SERIAL_FAST_TIMER
4237 memset(fast_timers, 0, sizeof(fast_timers));
4238 #endif
4239 #ifdef CONFIG_ETRAX_RS485
4240 memset(fast_timers_rs485, 0, sizeof(fast_timers_rs485));
4241 #endif
4242 fast_timer_init();
4243 #endif
4244
4245 #ifndef CONFIG_ETRAX_KGDB
4246 /* Not needed in simulator. May only complicate stuff. */
4247 /* hook the irq's for DMA channel 6 and 7, serial output and input, and some more... */
4248
4249 if (request_irq(SERIAL_IRQ_NBR, ser_interrupt,
4250 IRQF_SHARED, "serial ", driver))
4251 panic("%s: Failed to request irq8", __func__);
4252
4253 #endif
4254
4255 return 0;
4256 }
4257
4258 /* this makes sure that rs_init is called during kernel boot */
4259
4260 module_init(rs_init);
Linux kernel - Deliverables
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