2 * Freescale lpuart serial port driver
4 * Copyright 2012-2014 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
16 #include <linux/clk.h>
17 #include <linux/console.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/dmaengine.h>
20 #include <linux/dmapool.h>
22 #include <linux/irq.h>
23 #include <linux/module.h>
25 #include <linux/of_device.h>
26 #include <linux/of_dma.h>
27 #include <linux/serial_core.h>
28 #include <linux/slab.h>
29 #include <linux/tty_flip.h>
31 /* All registers are 8-bit width */
41 #define UARTMODEM 0x0d
42 #define UARTPFIFO 0x10
43 #define UARTCFIFO 0x11
44 #define UARTSFIFO 0x12
45 #define UARTTWFIFO 0x13
46 #define UARTTCFIFO 0x14
47 #define UARTRWFIFO 0x15
49 #define UARTBDH_LBKDIE 0x80
50 #define UARTBDH_RXEDGIE 0x40
51 #define UARTBDH_SBR_MASK 0x1f
53 #define UARTCR1_LOOPS 0x80
54 #define UARTCR1_RSRC 0x20
55 #define UARTCR1_M 0x10
56 #define UARTCR1_WAKE 0x08
57 #define UARTCR1_ILT 0x04
58 #define UARTCR1_PE 0x02
59 #define UARTCR1_PT 0x01
61 #define UARTCR2_TIE 0x80
62 #define UARTCR2_TCIE 0x40
63 #define UARTCR2_RIE 0x20
64 #define UARTCR2_ILIE 0x10
65 #define UARTCR2_TE 0x08
66 #define UARTCR2_RE 0x04
67 #define UARTCR2_RWU 0x02
68 #define UARTCR2_SBK 0x01
70 #define UARTSR1_TDRE 0x80
71 #define UARTSR1_TC 0x40
72 #define UARTSR1_RDRF 0x20
73 #define UARTSR1_IDLE 0x10
74 #define UARTSR1_OR 0x08
75 #define UARTSR1_NF 0x04
76 #define UARTSR1_FE 0x02
77 #define UARTSR1_PE 0x01
79 #define UARTCR3_R8 0x80
80 #define UARTCR3_T8 0x40
81 #define UARTCR3_TXDIR 0x20
82 #define UARTCR3_TXINV 0x10
83 #define UARTCR3_ORIE 0x08
84 #define UARTCR3_NEIE 0x04
85 #define UARTCR3_FEIE 0x02
86 #define UARTCR3_PEIE 0x01
88 #define UARTCR4_MAEN1 0x80
89 #define UARTCR4_MAEN2 0x40
90 #define UARTCR4_M10 0x20
91 #define UARTCR4_BRFA_MASK 0x1f
92 #define UARTCR4_BRFA_OFF 0
94 #define UARTCR5_TDMAS 0x80
95 #define UARTCR5_RDMAS 0x20
97 #define UARTMODEM_RXRTSE 0x08
98 #define UARTMODEM_TXRTSPOL 0x04
99 #define UARTMODEM_TXRTSE 0x02
100 #define UARTMODEM_TXCTSE 0x01
102 #define UARTPFIFO_TXFE 0x80
103 #define UARTPFIFO_FIFOSIZE_MASK 0x7
104 #define UARTPFIFO_TXSIZE_OFF 4
105 #define UARTPFIFO_RXFE 0x08
106 #define UARTPFIFO_RXSIZE_OFF 0
108 #define UARTCFIFO_TXFLUSH 0x80
109 #define UARTCFIFO_RXFLUSH 0x40
110 #define UARTCFIFO_RXOFE 0x04
111 #define UARTCFIFO_TXOFE 0x02
112 #define UARTCFIFO_RXUFE 0x01
114 #define UARTSFIFO_TXEMPT 0x80
115 #define UARTSFIFO_RXEMPT 0x40
116 #define UARTSFIFO_RXOF 0x04
117 #define UARTSFIFO_TXOF 0x02
118 #define UARTSFIFO_RXUF 0x01
120 /* 32-bit register defination */
121 #define UARTBAUD 0x00
122 #define UARTSTAT 0x04
123 #define UARTCTRL 0x08
124 #define UARTDATA 0x0C
125 #define UARTMATCH 0x10
126 #define UARTMODIR 0x14
127 #define UARTFIFO 0x18
128 #define UARTWATER 0x1c
130 #define UARTBAUD_MAEN1 0x80000000
131 #define UARTBAUD_MAEN2 0x40000000
132 #define UARTBAUD_M10 0x20000000
133 #define UARTBAUD_TDMAE 0x00800000
134 #define UARTBAUD_RDMAE 0x00200000
135 #define UARTBAUD_MATCFG 0x00400000
136 #define UARTBAUD_BOTHEDGE 0x00020000
137 #define UARTBAUD_RESYNCDIS 0x00010000
138 #define UARTBAUD_LBKDIE 0x00008000
139 #define UARTBAUD_RXEDGIE 0x00004000
140 #define UARTBAUD_SBNS 0x00002000
141 #define UARTBAUD_SBR 0x00000000
142 #define UARTBAUD_SBR_MASK 0x1fff
144 #define UARTSTAT_LBKDIF 0x80000000
145 #define UARTSTAT_RXEDGIF 0x40000000
146 #define UARTSTAT_MSBF 0x20000000
147 #define UARTSTAT_RXINV 0x10000000
148 #define UARTSTAT_RWUID 0x08000000
149 #define UARTSTAT_BRK13 0x04000000
150 #define UARTSTAT_LBKDE 0x02000000
151 #define UARTSTAT_RAF 0x01000000
152 #define UARTSTAT_TDRE 0x00800000
153 #define UARTSTAT_TC 0x00400000
154 #define UARTSTAT_RDRF 0x00200000
155 #define UARTSTAT_IDLE 0x00100000
156 #define UARTSTAT_OR 0x00080000
157 #define UARTSTAT_NF 0x00040000
158 #define UARTSTAT_FE 0x00020000
159 #define UARTSTAT_PE 0x00010000
160 #define UARTSTAT_MA1F 0x00008000
161 #define UARTSTAT_M21F 0x00004000
163 #define UARTCTRL_R8T9 0x80000000
164 #define UARTCTRL_R9T8 0x40000000
165 #define UARTCTRL_TXDIR 0x20000000
166 #define UARTCTRL_TXINV 0x10000000
167 #define UARTCTRL_ORIE 0x08000000
168 #define UARTCTRL_NEIE 0x04000000
169 #define UARTCTRL_FEIE 0x02000000
170 #define UARTCTRL_PEIE 0x01000000
171 #define UARTCTRL_TIE 0x00800000
172 #define UARTCTRL_TCIE 0x00400000
173 #define UARTCTRL_RIE 0x00200000
174 #define UARTCTRL_ILIE 0x00100000
175 #define UARTCTRL_TE 0x00080000
176 #define UARTCTRL_RE 0x00040000
177 #define UARTCTRL_RWU 0x00020000
178 #define UARTCTRL_SBK 0x00010000
179 #define UARTCTRL_MA1IE 0x00008000
180 #define UARTCTRL_MA2IE 0x00004000
181 #define UARTCTRL_IDLECFG 0x00000100
182 #define UARTCTRL_LOOPS 0x00000080
183 #define UARTCTRL_DOZEEN 0x00000040
184 #define UARTCTRL_RSRC 0x00000020
185 #define UARTCTRL_M 0x00000010
186 #define UARTCTRL_WAKE 0x00000008
187 #define UARTCTRL_ILT 0x00000004
188 #define UARTCTRL_PE 0x00000002
189 #define UARTCTRL_PT 0x00000001
191 #define UARTDATA_NOISY 0x00008000
192 #define UARTDATA_PARITYE 0x00004000
193 #define UARTDATA_FRETSC 0x00002000
194 #define UARTDATA_RXEMPT 0x00001000
195 #define UARTDATA_IDLINE 0x00000800
196 #define UARTDATA_MASK 0x3ff
198 #define UARTMODIR_IREN 0x00020000
199 #define UARTMODIR_TXCTSSRC 0x00000020
200 #define UARTMODIR_TXCTSC 0x00000010
201 #define UARTMODIR_RXRTSE 0x00000008
202 #define UARTMODIR_TXRTSPOL 0x00000004
203 #define UARTMODIR_TXRTSE 0x00000002
204 #define UARTMODIR_TXCTSE 0x00000001
206 #define UARTFIFO_TXEMPT 0x00800000
207 #define UARTFIFO_RXEMPT 0x00400000
208 #define UARTFIFO_TXOF 0x00020000
209 #define UARTFIFO_RXUF 0x00010000
210 #define UARTFIFO_TXFLUSH 0x00008000
211 #define UARTFIFO_RXFLUSH 0x00004000
212 #define UARTFIFO_TXOFE 0x00000200
213 #define UARTFIFO_RXUFE 0x00000100
214 #define UARTFIFO_TXFE 0x00000080
215 #define UARTFIFO_FIFOSIZE_MASK 0x7
216 #define UARTFIFO_TXSIZE_OFF 4
217 #define UARTFIFO_RXFE 0x00000008
218 #define UARTFIFO_RXSIZE_OFF 0
220 #define UARTWATER_COUNT_MASK 0xff
221 #define UARTWATER_TXCNT_OFF 8
222 #define UARTWATER_RXCNT_OFF 24
223 #define UARTWATER_WATER_MASK 0xff
224 #define UARTWATER_TXWATER_OFF 0
225 #define UARTWATER_RXWATER_OFF 16
227 #define FSL_UART_RX_DMA_BUFFER_SIZE 64
229 #define DRIVER_NAME "fsl-lpuart"
230 #define DEV_NAME "ttyLP"
234 struct uart_port port
;
236 unsigned int txfifo_size
;
237 unsigned int rxfifo_size
;
240 bool lpuart_dma_tx_use
;
241 bool lpuart_dma_rx_use
;
242 struct dma_chan
*dma_tx_chan
;
243 struct dma_chan
*dma_rx_chan
;
244 struct dma_async_tx_descriptor
*dma_tx_desc
;
245 struct dma_async_tx_descriptor
*dma_rx_desc
;
246 dma_addr_t dma_tx_buf_bus
;
247 dma_addr_t dma_rx_buf_bus
;
248 dma_cookie_t dma_tx_cookie
;
249 dma_cookie_t dma_rx_cookie
;
250 unsigned char *dma_tx_buf_virt
;
251 unsigned char *dma_rx_buf_virt
;
252 unsigned int dma_tx_bytes
;
253 unsigned int dma_rx_bytes
;
254 int dma_tx_in_progress
;
255 int dma_rx_in_progress
;
256 unsigned int dma_rx_timeout
;
257 struct timer_list lpuart_timer
;
260 static struct of_device_id lpuart_dt_ids
[] = {
262 .compatible
= "fsl,vf610-lpuart",
265 .compatible
= "fsl,ls1021a-lpuart",
269 MODULE_DEVICE_TABLE(of
, lpuart_dt_ids
);
271 /* Forward declare this for the dma callbacks*/
272 static void lpuart_dma_tx_complete(void *arg
);
273 static void lpuart_dma_rx_complete(void *arg
);
275 static u32
lpuart32_read(void __iomem
*addr
)
277 return ioread32be(addr
);
280 static void lpuart32_write(u32 val
, void __iomem
*addr
)
282 iowrite32be(val
, addr
);
285 static void lpuart_stop_tx(struct uart_port
*port
)
289 temp
= readb(port
->membase
+ UARTCR2
);
290 temp
&= ~(UARTCR2_TIE
| UARTCR2_TCIE
);
291 writeb(temp
, port
->membase
+ UARTCR2
);
294 static void lpuart32_stop_tx(struct uart_port
*port
)
298 temp
= lpuart32_read(port
->membase
+ UARTCTRL
);
299 temp
&= ~(UARTCTRL_TIE
| UARTCTRL_TCIE
);
300 lpuart32_write(temp
, port
->membase
+ UARTCTRL
);
303 static void lpuart_stop_rx(struct uart_port
*port
)
307 temp
= readb(port
->membase
+ UARTCR2
);
308 writeb(temp
& ~UARTCR2_RE
, port
->membase
+ UARTCR2
);
311 static void lpuart32_stop_rx(struct uart_port
*port
)
315 temp
= lpuart32_read(port
->membase
+ UARTCTRL
);
316 lpuart32_write(temp
& ~UARTCTRL_RE
, port
->membase
+ UARTCTRL
);
319 static void lpuart_copy_rx_to_tty(struct lpuart_port
*sport
,
320 struct tty_port
*tty
, int count
)
324 sport
->port
.icount
.rx
+= count
;
327 dev_err(sport
->port
.dev
, "No tty port\n");
331 dma_sync_single_for_cpu(sport
->port
.dev
, sport
->dma_rx_buf_bus
,
332 FSL_UART_RX_DMA_BUFFER_SIZE
, DMA_FROM_DEVICE
);
333 copied
= tty_insert_flip_string(tty
,
334 ((unsigned char *)(sport
->dma_rx_buf_virt
)), count
);
336 if (copied
!= count
) {
338 dev_err(sport
->port
.dev
, "RxData copy to tty layer failed\n");
341 dma_sync_single_for_device(sport
->port
.dev
, sport
->dma_rx_buf_bus
,
342 FSL_UART_RX_DMA_BUFFER_SIZE
, DMA_TO_DEVICE
);
345 static void lpuart_pio_tx(struct lpuart_port
*sport
)
347 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
350 spin_lock_irqsave(&sport
->port
.lock
, flags
);
352 while (!uart_circ_empty(xmit
) &&
353 readb(sport
->port
.membase
+ UARTTCFIFO
) < sport
->txfifo_size
) {
354 writeb(xmit
->buf
[xmit
->tail
], sport
->port
.membase
+ UARTDR
);
355 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
356 sport
->port
.icount
.tx
++;
359 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
360 uart_write_wakeup(&sport
->port
);
362 if (uart_circ_empty(xmit
))
363 writeb(readb(sport
->port
.membase
+ UARTCR5
) | UARTCR5_TDMAS
,
364 sport
->port
.membase
+ UARTCR5
);
366 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
369 static int lpuart_dma_tx(struct lpuart_port
*sport
, unsigned long count
)
371 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
372 dma_addr_t tx_bus_addr
;
374 dma_sync_single_for_device(sport
->port
.dev
, sport
->dma_tx_buf_bus
,
375 UART_XMIT_SIZE
, DMA_TO_DEVICE
);
376 sport
->dma_tx_bytes
= count
& ~(sport
->txfifo_size
- 1);
377 tx_bus_addr
= sport
->dma_tx_buf_bus
+ xmit
->tail
;
378 sport
->dma_tx_desc
= dmaengine_prep_slave_single(sport
->dma_tx_chan
,
379 tx_bus_addr
, sport
->dma_tx_bytes
,
380 DMA_MEM_TO_DEV
, DMA_PREP_INTERRUPT
);
382 if (!sport
->dma_tx_desc
) {
383 dev_err(sport
->port
.dev
, "Not able to get desc for tx\n");
387 sport
->dma_tx_desc
->callback
= lpuart_dma_tx_complete
;
388 sport
->dma_tx_desc
->callback_param
= sport
;
389 sport
->dma_tx_in_progress
= 1;
390 sport
->dma_tx_cookie
= dmaengine_submit(sport
->dma_tx_desc
);
391 dma_async_issue_pending(sport
->dma_tx_chan
);
396 static void lpuart_prepare_tx(struct lpuart_port
*sport
)
398 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
399 unsigned long count
= CIRC_CNT_TO_END(xmit
->head
,
400 xmit
->tail
, UART_XMIT_SIZE
);
405 if (count
< sport
->txfifo_size
)
406 writeb(readb(sport
->port
.membase
+ UARTCR5
) & ~UARTCR5_TDMAS
,
407 sport
->port
.membase
+ UARTCR5
);
409 writeb(readb(sport
->port
.membase
+ UARTCR5
) | UARTCR5_TDMAS
,
410 sport
->port
.membase
+ UARTCR5
);
411 lpuart_dma_tx(sport
, count
);
415 static void lpuart_dma_tx_complete(void *arg
)
417 struct lpuart_port
*sport
= arg
;
418 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
421 async_tx_ack(sport
->dma_tx_desc
);
423 spin_lock_irqsave(&sport
->port
.lock
, flags
);
425 xmit
->tail
= (xmit
->tail
+ sport
->dma_tx_bytes
) & (UART_XMIT_SIZE
- 1);
426 sport
->dma_tx_in_progress
= 0;
428 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
429 uart_write_wakeup(&sport
->port
);
431 lpuart_prepare_tx(sport
);
433 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
436 static int lpuart_dma_rx(struct lpuart_port
*sport
)
438 dma_sync_single_for_device(sport
->port
.dev
, sport
->dma_rx_buf_bus
,
439 FSL_UART_RX_DMA_BUFFER_SIZE
, DMA_TO_DEVICE
);
440 sport
->dma_rx_desc
= dmaengine_prep_slave_single(sport
->dma_rx_chan
,
441 sport
->dma_rx_buf_bus
, FSL_UART_RX_DMA_BUFFER_SIZE
,
442 DMA_DEV_TO_MEM
, DMA_PREP_INTERRUPT
);
444 if (!sport
->dma_rx_desc
) {
445 dev_err(sport
->port
.dev
, "Not able to get desc for rx\n");
449 sport
->dma_rx_desc
->callback
= lpuart_dma_rx_complete
;
450 sport
->dma_rx_desc
->callback_param
= sport
;
451 sport
->dma_rx_in_progress
= 1;
452 sport
->dma_rx_cookie
= dmaengine_submit(sport
->dma_rx_desc
);
453 dma_async_issue_pending(sport
->dma_rx_chan
);
458 static void lpuart_dma_rx_complete(void *arg
)
460 struct lpuart_port
*sport
= arg
;
461 struct tty_port
*port
= &sport
->port
.state
->port
;
464 async_tx_ack(sport
->dma_rx_desc
);
465 mod_timer(&sport
->lpuart_timer
, jiffies
+ sport
->dma_rx_timeout
);
467 spin_lock_irqsave(&sport
->port
.lock
, flags
);
469 sport
->dma_rx_in_progress
= 0;
470 lpuart_copy_rx_to_tty(sport
, port
, FSL_UART_RX_DMA_BUFFER_SIZE
);
471 tty_flip_buffer_push(port
);
472 lpuart_dma_rx(sport
);
474 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
477 static void lpuart_timer_func(unsigned long data
)
479 struct lpuart_port
*sport
= (struct lpuart_port
*)data
;
480 struct tty_port
*port
= &sport
->port
.state
->port
;
481 struct dma_tx_state state
;
486 del_timer(&sport
->lpuart_timer
);
487 dmaengine_pause(sport
->dma_rx_chan
);
488 dmaengine_tx_status(sport
->dma_rx_chan
, sport
->dma_rx_cookie
, &state
);
489 dmaengine_terminate_all(sport
->dma_rx_chan
);
490 count
= FSL_UART_RX_DMA_BUFFER_SIZE
- state
.residue
;
491 async_tx_ack(sport
->dma_rx_desc
);
493 spin_lock_irqsave(&sport
->port
.lock
, flags
);
495 sport
->dma_rx_in_progress
= 0;
496 lpuart_copy_rx_to_tty(sport
, port
, count
);
497 tty_flip_buffer_push(port
);
498 temp
= readb(sport
->port
.membase
+ UARTCR5
);
499 writeb(temp
& ~UARTCR5_RDMAS
, sport
->port
.membase
+ UARTCR5
);
501 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
504 static inline void lpuart_prepare_rx(struct lpuart_port
*sport
)
509 spin_lock_irqsave(&sport
->port
.lock
, flags
);
511 sport
->lpuart_timer
.expires
= jiffies
+ sport
->dma_rx_timeout
;
512 add_timer(&sport
->lpuart_timer
);
514 lpuart_dma_rx(sport
);
515 temp
= readb(sport
->port
.membase
+ UARTCR5
);
516 writeb(temp
| UARTCR5_RDMAS
, sport
->port
.membase
+ UARTCR5
);
518 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
521 static inline void lpuart_transmit_buffer(struct lpuart_port
*sport
)
523 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
525 while (!uart_circ_empty(xmit
) &&
526 (readb(sport
->port
.membase
+ UARTTCFIFO
) < sport
->txfifo_size
)) {
527 writeb(xmit
->buf
[xmit
->tail
], sport
->port
.membase
+ UARTDR
);
528 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
529 sport
->port
.icount
.tx
++;
532 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
533 uart_write_wakeup(&sport
->port
);
535 if (uart_circ_empty(xmit
))
536 lpuart_stop_tx(&sport
->port
);
539 static inline void lpuart32_transmit_buffer(struct lpuart_port
*sport
)
541 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
544 txcnt
= lpuart32_read(sport
->port
.membase
+ UARTWATER
);
545 txcnt
= txcnt
>> UARTWATER_TXCNT_OFF
;
546 txcnt
&= UARTWATER_COUNT_MASK
;
547 while (!uart_circ_empty(xmit
) && (txcnt
< sport
->txfifo_size
)) {
548 lpuart32_write(xmit
->buf
[xmit
->tail
], sport
->port
.membase
+ UARTDATA
);
549 xmit
->tail
= (xmit
->tail
+ 1) & (UART_XMIT_SIZE
- 1);
550 sport
->port
.icount
.tx
++;
551 txcnt
= lpuart32_read(sport
->port
.membase
+ UARTWATER
);
552 txcnt
= txcnt
>> UARTWATER_TXCNT_OFF
;
553 txcnt
&= UARTWATER_COUNT_MASK
;
556 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
557 uart_write_wakeup(&sport
->port
);
559 if (uart_circ_empty(xmit
))
560 lpuart32_stop_tx(&sport
->port
);
563 static void lpuart_start_tx(struct uart_port
*port
)
565 struct lpuart_port
*sport
= container_of(port
,
566 struct lpuart_port
, port
);
567 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
570 temp
= readb(port
->membase
+ UARTCR2
);
571 writeb(temp
| UARTCR2_TIE
, port
->membase
+ UARTCR2
);
573 if (sport
->lpuart_dma_tx_use
) {
574 if (!uart_circ_empty(xmit
) && !sport
->dma_tx_in_progress
)
575 lpuart_prepare_tx(sport
);
577 if (readb(port
->membase
+ UARTSR1
) & UARTSR1_TDRE
)
578 lpuart_transmit_buffer(sport
);
582 static void lpuart32_start_tx(struct uart_port
*port
)
584 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
587 temp
= lpuart32_read(port
->membase
+ UARTCTRL
);
588 lpuart32_write(temp
| UARTCTRL_TIE
, port
->membase
+ UARTCTRL
);
590 if (lpuart32_read(port
->membase
+ UARTSTAT
) & UARTSTAT_TDRE
)
591 lpuart32_transmit_buffer(sport
);
594 static irqreturn_t
lpuart_txint(int irq
, void *dev_id
)
596 struct lpuart_port
*sport
= dev_id
;
597 struct circ_buf
*xmit
= &sport
->port
.state
->xmit
;
600 spin_lock_irqsave(&sport
->port
.lock
, flags
);
601 if (sport
->port
.x_char
) {
603 lpuart32_write(sport
->port
.x_char
, sport
->port
.membase
+ UARTDATA
);
605 writeb(sport
->port
.x_char
, sport
->port
.membase
+ UARTDR
);
609 if (uart_circ_empty(xmit
) || uart_tx_stopped(&sport
->port
)) {
611 lpuart32_stop_tx(&sport
->port
);
613 lpuart_stop_tx(&sport
->port
);
618 lpuart32_transmit_buffer(sport
);
620 lpuart_transmit_buffer(sport
);
622 if (uart_circ_chars_pending(xmit
) < WAKEUP_CHARS
)
623 uart_write_wakeup(&sport
->port
);
626 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
630 static irqreturn_t
lpuart_rxint(int irq
, void *dev_id
)
632 struct lpuart_port
*sport
= dev_id
;
633 unsigned int flg
, ignored
= 0;
634 struct tty_port
*port
= &sport
->port
.state
->port
;
636 unsigned char rx
, sr
;
638 spin_lock_irqsave(&sport
->port
.lock
, flags
);
640 while (!(readb(sport
->port
.membase
+ UARTSFIFO
) & UARTSFIFO_RXEMPT
)) {
642 sport
->port
.icount
.rx
++;
644 * to clear the FE, OR, NF, FE, PE flags,
645 * read SR1 then read DR
647 sr
= readb(sport
->port
.membase
+ UARTSR1
);
648 rx
= readb(sport
->port
.membase
+ UARTDR
);
650 if (uart_handle_sysrq_char(&sport
->port
, (unsigned char)rx
))
653 if (sr
& (UARTSR1_PE
| UARTSR1_OR
| UARTSR1_FE
)) {
655 sport
->port
.icount
.parity
++;
656 else if (sr
& UARTSR1_FE
)
657 sport
->port
.icount
.frame
++;
660 sport
->port
.icount
.overrun
++;
662 if (sr
& sport
->port
.ignore_status_mask
) {
668 sr
&= sport
->port
.read_status_mask
;
672 else if (sr
& UARTSR1_FE
)
679 sport
->port
.sysrq
= 0;
683 tty_insert_flip_char(port
, rx
, flg
);
687 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
689 tty_flip_buffer_push(port
);
693 static irqreturn_t
lpuart32_rxint(int irq
, void *dev_id
)
695 struct lpuart_port
*sport
= dev_id
;
696 unsigned int flg
, ignored
= 0;
697 struct tty_port
*port
= &sport
->port
.state
->port
;
699 unsigned long rx
, sr
;
701 spin_lock_irqsave(&sport
->port
.lock
, flags
);
703 while (!(lpuart32_read(sport
->port
.membase
+ UARTFIFO
) & UARTFIFO_RXEMPT
)) {
705 sport
->port
.icount
.rx
++;
707 * to clear the FE, OR, NF, FE, PE flags,
708 * read STAT then read DATA reg
710 sr
= lpuart32_read(sport
->port
.membase
+ UARTSTAT
);
711 rx
= lpuart32_read(sport
->port
.membase
+ UARTDATA
);
714 if (uart_handle_sysrq_char(&sport
->port
, (unsigned char)rx
))
717 if (sr
& (UARTSTAT_PE
| UARTSTAT_OR
| UARTSTAT_FE
)) {
718 if (sr
& UARTSTAT_PE
)
719 sport
->port
.icount
.parity
++;
720 else if (sr
& UARTSTAT_FE
)
721 sport
->port
.icount
.frame
++;
723 if (sr
& UARTSTAT_OR
)
724 sport
->port
.icount
.overrun
++;
726 if (sr
& sport
->port
.ignore_status_mask
) {
732 sr
&= sport
->port
.read_status_mask
;
734 if (sr
& UARTSTAT_PE
)
736 else if (sr
& UARTSTAT_FE
)
739 if (sr
& UARTSTAT_OR
)
743 sport
->port
.sysrq
= 0;
747 tty_insert_flip_char(port
, rx
, flg
);
751 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
753 tty_flip_buffer_push(port
);
757 static irqreturn_t
lpuart_int(int irq
, void *dev_id
)
759 struct lpuart_port
*sport
= dev_id
;
760 unsigned char sts
, crdma
;
762 sts
= readb(sport
->port
.membase
+ UARTSR1
);
763 crdma
= readb(sport
->port
.membase
+ UARTCR5
);
765 if (sts
& UARTSR1_RDRF
&& !(crdma
& UARTCR5_RDMAS
)) {
766 if (sport
->lpuart_dma_rx_use
)
767 lpuart_prepare_rx(sport
);
769 lpuart_rxint(irq
, dev_id
);
771 if (sts
& UARTSR1_TDRE
&& !(crdma
& UARTCR5_TDMAS
)) {
772 if (sport
->lpuart_dma_tx_use
)
773 lpuart_pio_tx(sport
);
775 lpuart_txint(irq
, dev_id
);
781 static irqreturn_t
lpuart32_int(int irq
, void *dev_id
)
783 struct lpuart_port
*sport
= dev_id
;
784 unsigned long sts
, rxcount
;
786 sts
= lpuart32_read(sport
->port
.membase
+ UARTSTAT
);
787 rxcount
= lpuart32_read(sport
->port
.membase
+ UARTWATER
);
788 rxcount
= rxcount
>> UARTWATER_RXCNT_OFF
;
790 if (sts
& UARTSTAT_RDRF
|| rxcount
> 0)
791 lpuart32_rxint(irq
, dev_id
);
793 if ((sts
& UARTSTAT_TDRE
) &&
794 !(lpuart32_read(sport
->port
.membase
+ UARTBAUD
) & UARTBAUD_TDMAE
))
795 lpuart_txint(irq
, dev_id
);
797 lpuart32_write(sts
, sport
->port
.membase
+ UARTSTAT
);
801 /* return TIOCSER_TEMT when transmitter is not busy */
802 static unsigned int lpuart_tx_empty(struct uart_port
*port
)
804 return (readb(port
->membase
+ UARTSR1
) & UARTSR1_TC
) ?
808 static unsigned int lpuart32_tx_empty(struct uart_port
*port
)
810 return (lpuart32_read(port
->membase
+ UARTSTAT
) & UARTSTAT_TC
) ?
814 static unsigned int lpuart_get_mctrl(struct uart_port
*port
)
816 unsigned int temp
= 0;
819 reg
= readb(port
->membase
+ UARTMODEM
);
820 if (reg
& UARTMODEM_TXCTSE
)
823 if (reg
& UARTMODEM_RXRTSE
)
829 static unsigned int lpuart32_get_mctrl(struct uart_port
*port
)
831 unsigned int temp
= 0;
834 reg
= lpuart32_read(port
->membase
+ UARTMODIR
);
835 if (reg
& UARTMODIR_TXCTSE
)
838 if (reg
& UARTMODIR_RXRTSE
)
844 static void lpuart_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
848 temp
= readb(port
->membase
+ UARTMODEM
) &
849 ~(UARTMODEM_RXRTSE
| UARTMODEM_TXCTSE
);
851 if (mctrl
& TIOCM_RTS
)
852 temp
|= UARTMODEM_RXRTSE
;
854 if (mctrl
& TIOCM_CTS
)
855 temp
|= UARTMODEM_TXCTSE
;
857 writeb(temp
, port
->membase
+ UARTMODEM
);
860 static void lpuart32_set_mctrl(struct uart_port
*port
, unsigned int mctrl
)
864 temp
= lpuart32_read(port
->membase
+ UARTMODIR
) &
865 ~(UARTMODIR_RXRTSE
| UARTMODIR_TXCTSE
);
867 if (mctrl
& TIOCM_RTS
)
868 temp
|= UARTMODIR_RXRTSE
;
870 if (mctrl
& TIOCM_CTS
)
871 temp
|= UARTMODIR_TXCTSE
;
873 lpuart32_write(temp
, port
->membase
+ UARTMODIR
);
876 static void lpuart_break_ctl(struct uart_port
*port
, int break_state
)
880 temp
= readb(port
->membase
+ UARTCR2
) & ~UARTCR2_SBK
;
882 if (break_state
!= 0)
885 writeb(temp
, port
->membase
+ UARTCR2
);
888 static void lpuart32_break_ctl(struct uart_port
*port
, int break_state
)
892 temp
= lpuart32_read(port
->membase
+ UARTCTRL
) & ~UARTCTRL_SBK
;
894 if (break_state
!= 0)
895 temp
|= UARTCTRL_SBK
;
897 lpuart32_write(temp
, port
->membase
+ UARTCTRL
);
900 static void lpuart_setup_watermark(struct lpuart_port
*sport
)
902 unsigned char val
, cr2
;
903 unsigned char cr2_saved
;
905 cr2
= readb(sport
->port
.membase
+ UARTCR2
);
907 cr2
&= ~(UARTCR2_TIE
| UARTCR2_TCIE
| UARTCR2_TE
|
908 UARTCR2_RIE
| UARTCR2_RE
);
909 writeb(cr2
, sport
->port
.membase
+ UARTCR2
);
911 val
= readb(sport
->port
.membase
+ UARTPFIFO
);
912 writeb(val
| UARTPFIFO_TXFE
| UARTPFIFO_RXFE
,
913 sport
->port
.membase
+ UARTPFIFO
);
915 /* flush Tx and Rx FIFO */
916 writeb(UARTCFIFO_TXFLUSH
| UARTCFIFO_RXFLUSH
,
917 sport
->port
.membase
+ UARTCFIFO
);
919 writeb(0, sport
->port
.membase
+ UARTTWFIFO
);
920 writeb(1, sport
->port
.membase
+ UARTRWFIFO
);
923 writeb(cr2_saved
, sport
->port
.membase
+ UARTCR2
);
926 static void lpuart32_setup_watermark(struct lpuart_port
*sport
)
928 unsigned long val
, ctrl
;
929 unsigned long ctrl_saved
;
931 ctrl
= lpuart32_read(sport
->port
.membase
+ UARTCTRL
);
933 ctrl
&= ~(UARTCTRL_TIE
| UARTCTRL_TCIE
| UARTCTRL_TE
|
934 UARTCTRL_RIE
| UARTCTRL_RE
);
935 lpuart32_write(ctrl
, sport
->port
.membase
+ UARTCTRL
);
937 /* enable FIFO mode */
938 val
= lpuart32_read(sport
->port
.membase
+ UARTFIFO
);
939 val
|= UARTFIFO_TXFE
| UARTFIFO_RXFE
;
940 val
|= UARTFIFO_TXFLUSH
| UARTFIFO_RXFLUSH
;
941 lpuart32_write(val
, sport
->port
.membase
+ UARTFIFO
);
943 /* set the watermark */
944 val
= (0x1 << UARTWATER_RXWATER_OFF
) | (0x0 << UARTWATER_TXWATER_OFF
);
945 lpuart32_write(val
, sport
->port
.membase
+ UARTWATER
);
948 lpuart32_write(ctrl_saved
, sport
->port
.membase
+ UARTCTRL
);
951 static int lpuart_dma_tx_request(struct uart_port
*port
)
953 struct lpuart_port
*sport
= container_of(port
,
954 struct lpuart_port
, port
);
955 struct dma_slave_config dma_tx_sconfig
;
957 unsigned char *dma_buf
;
960 dma_bus
= dma_map_single(sport
->dma_tx_chan
->device
->dev
,
961 sport
->port
.state
->xmit
.buf
,
962 UART_XMIT_SIZE
, DMA_TO_DEVICE
);
964 if (dma_mapping_error(sport
->dma_tx_chan
->device
->dev
, dma_bus
)) {
965 dev_err(sport
->port
.dev
, "dma_map_single tx failed\n");
969 dma_buf
= sport
->port
.state
->xmit
.buf
;
970 dma_tx_sconfig
.dst_addr
= sport
->port
.mapbase
+ UARTDR
;
971 dma_tx_sconfig
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
972 dma_tx_sconfig
.dst_maxburst
= sport
->txfifo_size
;
973 dma_tx_sconfig
.direction
= DMA_MEM_TO_DEV
;
974 ret
= dmaengine_slave_config(sport
->dma_tx_chan
, &dma_tx_sconfig
);
977 dev_err(sport
->port
.dev
,
978 "Dma slave config failed, err = %d\n", ret
);
982 sport
->dma_tx_buf_virt
= dma_buf
;
983 sport
->dma_tx_buf_bus
= dma_bus
;
984 sport
->dma_tx_in_progress
= 0;
989 static int lpuart_dma_rx_request(struct uart_port
*port
)
991 struct lpuart_port
*sport
= container_of(port
,
992 struct lpuart_port
, port
);
993 struct dma_slave_config dma_rx_sconfig
;
995 unsigned char *dma_buf
;
998 dma_buf
= devm_kzalloc(sport
->port
.dev
,
999 FSL_UART_RX_DMA_BUFFER_SIZE
, GFP_KERNEL
);
1002 dev_err(sport
->port
.dev
, "Dma rx alloc failed\n");
1006 dma_bus
= dma_map_single(sport
->dma_rx_chan
->device
->dev
, dma_buf
,
1007 FSL_UART_RX_DMA_BUFFER_SIZE
, DMA_FROM_DEVICE
);
1009 if (dma_mapping_error(sport
->dma_rx_chan
->device
->dev
, dma_bus
)) {
1010 dev_err(sport
->port
.dev
, "dma_map_single rx failed\n");
1014 dma_rx_sconfig
.src_addr
= sport
->port
.mapbase
+ UARTDR
;
1015 dma_rx_sconfig
.src_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
1016 dma_rx_sconfig
.src_maxburst
= 1;
1017 dma_rx_sconfig
.direction
= DMA_DEV_TO_MEM
;
1018 ret
= dmaengine_slave_config(sport
->dma_rx_chan
, &dma_rx_sconfig
);
1021 dev_err(sport
->port
.dev
,
1022 "Dma slave config failed, err = %d\n", ret
);
1026 sport
->dma_rx_buf_virt
= dma_buf
;
1027 sport
->dma_rx_buf_bus
= dma_bus
;
1028 sport
->dma_rx_in_progress
= 0;
1033 static void lpuart_dma_tx_free(struct uart_port
*port
)
1035 struct lpuart_port
*sport
= container_of(port
,
1036 struct lpuart_port
, port
);
1038 dma_unmap_single(sport
->port
.dev
, sport
->dma_tx_buf_bus
,
1039 UART_XMIT_SIZE
, DMA_TO_DEVICE
);
1041 sport
->dma_tx_buf_bus
= 0;
1042 sport
->dma_tx_buf_virt
= NULL
;
1045 static void lpuart_dma_rx_free(struct uart_port
*port
)
1047 struct lpuart_port
*sport
= container_of(port
,
1048 struct lpuart_port
, port
);
1050 dma_unmap_single(sport
->port
.dev
, sport
->dma_rx_buf_bus
,
1051 FSL_UART_RX_DMA_BUFFER_SIZE
, DMA_FROM_DEVICE
);
1053 sport
->dma_rx_buf_bus
= 0;
1054 sport
->dma_rx_buf_virt
= NULL
;
1057 static int lpuart_startup(struct uart_port
*port
)
1059 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
1061 unsigned long flags
;
1064 /* determine FIFO size and enable FIFO mode */
1065 temp
= readb(sport
->port
.membase
+ UARTPFIFO
);
1067 sport
->txfifo_size
= 0x1 << (((temp
>> UARTPFIFO_TXSIZE_OFF
) &
1068 UARTPFIFO_FIFOSIZE_MASK
) + 1);
1070 sport
->rxfifo_size
= 0x1 << (((temp
>> UARTPFIFO_RXSIZE_OFF
) &
1071 UARTPFIFO_FIFOSIZE_MASK
) + 1);
1073 if (sport
->dma_rx_chan
&& !lpuart_dma_rx_request(port
)) {
1074 sport
->lpuart_dma_rx_use
= true;
1075 setup_timer(&sport
->lpuart_timer
, lpuart_timer_func
,
1076 (unsigned long)sport
);
1078 sport
->lpuart_dma_rx_use
= false;
1081 if (sport
->dma_tx_chan
&& !lpuart_dma_tx_request(port
)) {
1082 sport
->lpuart_dma_tx_use
= true;
1083 temp
= readb(port
->membase
+ UARTCR5
);
1084 temp
&= ~UARTCR5_RDMAS
;
1085 writeb(temp
| UARTCR5_TDMAS
, port
->membase
+ UARTCR5
);
1087 sport
->lpuart_dma_tx_use
= false;
1089 ret
= devm_request_irq(port
->dev
, port
->irq
, lpuart_int
, 0,
1090 DRIVER_NAME
, sport
);
1094 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1096 lpuart_setup_watermark(sport
);
1098 temp
= readb(sport
->port
.membase
+ UARTCR2
);
1099 temp
|= (UARTCR2_RIE
| UARTCR2_TIE
| UARTCR2_RE
| UARTCR2_TE
);
1100 writeb(temp
, sport
->port
.membase
+ UARTCR2
);
1102 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1106 static int lpuart32_startup(struct uart_port
*port
)
1108 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
1110 unsigned long flags
;
1113 /* determine FIFO size */
1114 temp
= lpuart32_read(sport
->port
.membase
+ UARTFIFO
);
1116 sport
->txfifo_size
= 0x1 << (((temp
>> UARTFIFO_TXSIZE_OFF
) &
1117 UARTFIFO_FIFOSIZE_MASK
) - 1);
1119 sport
->rxfifo_size
= 0x1 << (((temp
>> UARTFIFO_RXSIZE_OFF
) &
1120 UARTFIFO_FIFOSIZE_MASK
) - 1);
1122 ret
= devm_request_irq(port
->dev
, port
->irq
, lpuart32_int
, 0,
1123 DRIVER_NAME
, sport
);
1127 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1129 lpuart32_setup_watermark(sport
);
1131 temp
= lpuart32_read(sport
->port
.membase
+ UARTCTRL
);
1132 temp
|= (UARTCTRL_RIE
| UARTCTRL_TIE
| UARTCTRL_RE
| UARTCTRL_TE
);
1133 temp
|= UARTCTRL_ILIE
;
1134 lpuart32_write(temp
, sport
->port
.membase
+ UARTCTRL
);
1136 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1140 static void lpuart_shutdown(struct uart_port
*port
)
1142 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
1144 unsigned long flags
;
1146 spin_lock_irqsave(&port
->lock
, flags
);
1148 /* disable Rx/Tx and interrupts */
1149 temp
= readb(port
->membase
+ UARTCR2
);
1150 temp
&= ~(UARTCR2_TE
| UARTCR2_RE
|
1151 UARTCR2_TIE
| UARTCR2_TCIE
| UARTCR2_RIE
);
1152 writeb(temp
, port
->membase
+ UARTCR2
);
1154 spin_unlock_irqrestore(&port
->lock
, flags
);
1156 devm_free_irq(port
->dev
, port
->irq
, sport
);
1158 if (sport
->lpuart_dma_rx_use
) {
1159 lpuart_dma_rx_free(&sport
->port
);
1160 del_timer_sync(&sport
->lpuart_timer
);
1163 if (sport
->lpuart_dma_tx_use
)
1164 lpuart_dma_tx_free(&sport
->port
);
1167 static void lpuart32_shutdown(struct uart_port
*port
)
1169 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
1171 unsigned long flags
;
1173 spin_lock_irqsave(&port
->lock
, flags
);
1175 /* disable Rx/Tx and interrupts */
1176 temp
= lpuart32_read(port
->membase
+ UARTCTRL
);
1177 temp
&= ~(UARTCTRL_TE
| UARTCTRL_RE
|
1178 UARTCTRL_TIE
| UARTCTRL_TCIE
| UARTCTRL_RIE
);
1179 lpuart32_write(temp
, port
->membase
+ UARTCTRL
);
1181 spin_unlock_irqrestore(&port
->lock
, flags
);
1183 devm_free_irq(port
->dev
, port
->irq
, sport
);
1187 lpuart_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
1188 struct ktermios
*old
)
1190 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
1191 unsigned long flags
;
1192 unsigned char cr1
, old_cr1
, old_cr2
, cr4
, bdh
, modem
;
1194 unsigned int old_csize
= old
? old
->c_cflag
& CSIZE
: CS8
;
1195 unsigned int sbr
, brfa
;
1197 cr1
= old_cr1
= readb(sport
->port
.membase
+ UARTCR1
);
1198 old_cr2
= readb(sport
->port
.membase
+ UARTCR2
);
1199 cr4
= readb(sport
->port
.membase
+ UARTCR4
);
1200 bdh
= readb(sport
->port
.membase
+ UARTBDH
);
1201 modem
= readb(sport
->port
.membase
+ UARTMODEM
);
1203 * only support CS8 and CS7, and for CS7 must enable PE.
1210 while ((termios
->c_cflag
& CSIZE
) != CS8
&&
1211 (termios
->c_cflag
& CSIZE
) != CS7
) {
1212 termios
->c_cflag
&= ~CSIZE
;
1213 termios
->c_cflag
|= old_csize
;
1217 if ((termios
->c_cflag
& CSIZE
) == CS8
||
1218 (termios
->c_cflag
& CSIZE
) == CS7
)
1219 cr1
= old_cr1
& ~UARTCR1_M
;
1221 if (termios
->c_cflag
& CMSPAR
) {
1222 if ((termios
->c_cflag
& CSIZE
) != CS8
) {
1223 termios
->c_cflag
&= ~CSIZE
;
1224 termios
->c_cflag
|= CS8
;
1229 if (termios
->c_cflag
& CRTSCTS
) {
1230 modem
|= (UARTMODEM_RXRTSE
| UARTMODEM_TXCTSE
);
1232 termios
->c_cflag
&= ~CRTSCTS
;
1233 modem
&= ~(UARTMODEM_RXRTSE
| UARTMODEM_TXCTSE
);
1236 if (termios
->c_cflag
& CSTOPB
)
1237 termios
->c_cflag
&= ~CSTOPB
;
1239 /* parity must be enabled when CS7 to match 8-bits format */
1240 if ((termios
->c_cflag
& CSIZE
) == CS7
)
1241 termios
->c_cflag
|= PARENB
;
1243 if ((termios
->c_cflag
& PARENB
)) {
1244 if (termios
->c_cflag
& CMSPAR
) {
1249 if ((termios
->c_cflag
& CSIZE
) == CS8
)
1251 if (termios
->c_cflag
& PARODD
)
1258 /* ask the core to calculate the divisor */
1259 baud
= uart_get_baud_rate(port
, termios
, old
, 50, port
->uartclk
/ 16);
1261 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1263 sport
->port
.read_status_mask
= 0;
1264 if (termios
->c_iflag
& INPCK
)
1265 sport
->port
.read_status_mask
|= (UARTSR1_FE
| UARTSR1_PE
);
1266 if (termios
->c_iflag
& (IGNBRK
| BRKINT
| PARMRK
))
1267 sport
->port
.read_status_mask
|= UARTSR1_FE
;
1269 /* characters to ignore */
1270 sport
->port
.ignore_status_mask
= 0;
1271 if (termios
->c_iflag
& IGNPAR
)
1272 sport
->port
.ignore_status_mask
|= UARTSR1_PE
;
1273 if (termios
->c_iflag
& IGNBRK
) {
1274 sport
->port
.ignore_status_mask
|= UARTSR1_FE
;
1276 * if we're ignoring parity and break indicators,
1277 * ignore overruns too (for real raw support).
1279 if (termios
->c_iflag
& IGNPAR
)
1280 sport
->port
.ignore_status_mask
|= UARTSR1_OR
;
1283 /* update the per-port timeout */
1284 uart_update_timeout(port
, termios
->c_cflag
, baud
);
1286 if (sport
->lpuart_dma_rx_use
) {
1287 /* Calculate delay for 1.5 DMA buffers */
1288 sport
->dma_rx_timeout
= (sport
->port
.timeout
- HZ
/ 50) *
1289 FSL_UART_RX_DMA_BUFFER_SIZE
* 3 /
1290 sport
->rxfifo_size
/ 2;
1291 dev_dbg(port
->dev
, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1292 sport
->dma_rx_timeout
* 1000 / HZ
, sport
->port
.timeout
);
1293 if (sport
->dma_rx_timeout
< msecs_to_jiffies(20))
1294 sport
->dma_rx_timeout
= msecs_to_jiffies(20);
1297 /* wait transmit engin complete */
1298 while (!(readb(sport
->port
.membase
+ UARTSR1
) & UARTSR1_TC
))
1301 /* disable transmit and receive */
1302 writeb(old_cr2
& ~(UARTCR2_TE
| UARTCR2_RE
),
1303 sport
->port
.membase
+ UARTCR2
);
1305 sbr
= sport
->port
.uartclk
/ (16 * baud
);
1306 brfa
= ((sport
->port
.uartclk
- (16 * sbr
* baud
)) * 2) / baud
;
1307 bdh
&= ~UARTBDH_SBR_MASK
;
1308 bdh
|= (sbr
>> 8) & 0x1F;
1309 cr4
&= ~UARTCR4_BRFA_MASK
;
1310 brfa
&= UARTCR4_BRFA_MASK
;
1311 writeb(cr4
| brfa
, sport
->port
.membase
+ UARTCR4
);
1312 writeb(bdh
, sport
->port
.membase
+ UARTBDH
);
1313 writeb(sbr
& 0xFF, sport
->port
.membase
+ UARTBDL
);
1314 writeb(cr1
, sport
->port
.membase
+ UARTCR1
);
1315 writeb(modem
, sport
->port
.membase
+ UARTMODEM
);
1317 /* restore control register */
1318 writeb(old_cr2
, sport
->port
.membase
+ UARTCR2
);
1320 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1324 lpuart32_set_termios(struct uart_port
*port
, struct ktermios
*termios
,
1325 struct ktermios
*old
)
1327 struct lpuart_port
*sport
= container_of(port
, struct lpuart_port
, port
);
1328 unsigned long flags
;
1329 unsigned long ctrl
, old_ctrl
, bd
, modem
;
1331 unsigned int old_csize
= old
? old
->c_cflag
& CSIZE
: CS8
;
1334 ctrl
= old_ctrl
= lpuart32_read(sport
->port
.membase
+ UARTCTRL
);
1335 bd
= lpuart32_read(sport
->port
.membase
+ UARTBAUD
);
1336 modem
= lpuart32_read(sport
->port
.membase
+ UARTMODIR
);
1338 * only support CS8 and CS7, and for CS7 must enable PE.
1345 while ((termios
->c_cflag
& CSIZE
) != CS8
&&
1346 (termios
->c_cflag
& CSIZE
) != CS7
) {
1347 termios
->c_cflag
&= ~CSIZE
;
1348 termios
->c_cflag
|= old_csize
;
1352 if ((termios
->c_cflag
& CSIZE
) == CS8
||
1353 (termios
->c_cflag
& CSIZE
) == CS7
)
1354 ctrl
= old_ctrl
& ~UARTCTRL_M
;
1356 if (termios
->c_cflag
& CMSPAR
) {
1357 if ((termios
->c_cflag
& CSIZE
) != CS8
) {
1358 termios
->c_cflag
&= ~CSIZE
;
1359 termios
->c_cflag
|= CS8
;
1364 if (termios
->c_cflag
& CRTSCTS
) {
1365 modem
|= (UARTMODEM_RXRTSE
| UARTMODEM_TXCTSE
);
1367 termios
->c_cflag
&= ~CRTSCTS
;
1368 modem
&= ~(UARTMODEM_RXRTSE
| UARTMODEM_TXCTSE
);
1371 if (termios
->c_cflag
& CSTOPB
)
1372 termios
->c_cflag
&= ~CSTOPB
;
1374 /* parity must be enabled when CS7 to match 8-bits format */
1375 if ((termios
->c_cflag
& CSIZE
) == CS7
)
1376 termios
->c_cflag
|= PARENB
;
1378 if ((termios
->c_cflag
& PARENB
)) {
1379 if (termios
->c_cflag
& CMSPAR
) {
1380 ctrl
&= ~UARTCTRL_PE
;
1384 if ((termios
->c_cflag
& CSIZE
) == CS8
)
1386 if (termios
->c_cflag
& PARODD
)
1387 ctrl
|= UARTCTRL_PT
;
1389 ctrl
&= ~UARTCTRL_PT
;
1393 /* ask the core to calculate the divisor */
1394 baud
= uart_get_baud_rate(port
, termios
, old
, 50, port
->uartclk
/ 16);
1396 spin_lock_irqsave(&sport
->port
.lock
, flags
);
1398 sport
->port
.read_status_mask
= 0;
1399 if (termios
->c_iflag
& INPCK
)
1400 sport
->port
.read_status_mask
|= (UARTSTAT_FE
| UARTSTAT_PE
);
1401 if (termios
->c_iflag
& (IGNBRK
| BRKINT
| PARMRK
))
1402 sport
->port
.read_status_mask
|= UARTSTAT_FE
;
1404 /* characters to ignore */
1405 sport
->port
.ignore_status_mask
= 0;
1406 if (termios
->c_iflag
& IGNPAR
)
1407 sport
->port
.ignore_status_mask
|= UARTSTAT_PE
;
1408 if (termios
->c_iflag
& IGNBRK
) {
1409 sport
->port
.ignore_status_mask
|= UARTSTAT_FE
;
1411 * if we're ignoring parity and break indicators,
1412 * ignore overruns too (for real raw support).
1414 if (termios
->c_iflag
& IGNPAR
)
1415 sport
->port
.ignore_status_mask
|= UARTSTAT_OR
;
1418 /* update the per-port timeout */
1419 uart_update_timeout(port
, termios
->c_cflag
, baud
);
1421 /* wait transmit engin complete */
1422 while (!(lpuart32_read(sport
->port
.membase
+ UARTSTAT
) & UARTSTAT_TC
))
1425 /* disable transmit and receive */
1426 lpuart32_write(old_ctrl
& ~(UARTCTRL_TE
| UARTCTRL_RE
),
1427 sport
->port
.membase
+ UARTCTRL
);
1429 sbr
= sport
->port
.uartclk
/ (16 * baud
);
1430 bd
&= ~UARTBAUD_SBR_MASK
;
1431 bd
|= sbr
& UARTBAUD_SBR_MASK
;
1432 bd
|= UARTBAUD_BOTHEDGE
;
1433 bd
&= ~(UARTBAUD_TDMAE
| UARTBAUD_RDMAE
);
1434 lpuart32_write(bd
, sport
->port
.membase
+ UARTBAUD
);
1435 lpuart32_write(modem
, sport
->port
.membase
+ UARTMODIR
);
1436 lpuart32_write(ctrl
, sport
->port
.membase
+ UARTCTRL
);
1437 /* restore control register */
1439 spin_unlock_irqrestore(&sport
->port
.lock
, flags
);
1442 static const char *lpuart_type(struct uart_port
*port
)
1444 return "FSL_LPUART";
1447 static void lpuart_release_port(struct uart_port
*port
)
1452 static int lpuart_request_port(struct uart_port
*port
)
1457 /* configure/autoconfigure the port */
1458 static void lpuart_config_port(struct uart_port
*port
, int flags
)
1460 if (flags
& UART_CONFIG_TYPE
)
1461 port
->type
= PORT_LPUART
;
1464 static int lpuart_verify_port(struct uart_port
*port
, struct serial_struct
*ser
)
1468 if (ser
->type
!= PORT_UNKNOWN
&& ser
->type
!= PORT_LPUART
)
1470 if (port
->irq
!= ser
->irq
)
1472 if (ser
->io_type
!= UPIO_MEM
)
1474 if (port
->uartclk
/ 16 != ser
->baud_base
)
1476 if (port
->iobase
!= ser
->port
)
1483 static struct uart_ops lpuart_pops
= {
1484 .tx_empty
= lpuart_tx_empty
,
1485 .set_mctrl
= lpuart_set_mctrl
,
1486 .get_mctrl
= lpuart_get_mctrl
,
1487 .stop_tx
= lpuart_stop_tx
,
1488 .start_tx
= lpuart_start_tx
,
1489 .stop_rx
= lpuart_stop_rx
,
1490 .break_ctl
= lpuart_break_ctl
,
1491 .startup
= lpuart_startup
,
1492 .shutdown
= lpuart_shutdown
,
1493 .set_termios
= lpuart_set_termios
,
1494 .type
= lpuart_type
,
1495 .request_port
= lpuart_request_port
,
1496 .release_port
= lpuart_release_port
,
1497 .config_port
= lpuart_config_port
,
1498 .verify_port
= lpuart_verify_port
,
1501 static struct uart_ops lpuart32_pops
= {
1502 .tx_empty
= lpuart32_tx_empty
,
1503 .set_mctrl
= lpuart32_set_mctrl
,
1504 .get_mctrl
= lpuart32_get_mctrl
,
1505 .stop_tx
= lpuart32_stop_tx
,
1506 .start_tx
= lpuart32_start_tx
,
1507 .stop_rx
= lpuart32_stop_rx
,
1508 .break_ctl
= lpuart32_break_ctl
,
1509 .startup
= lpuart32_startup
,
1510 .shutdown
= lpuart32_shutdown
,
1511 .set_termios
= lpuart32_set_termios
,
1512 .type
= lpuart_type
,
1513 .request_port
= lpuart_request_port
,
1514 .release_port
= lpuart_release_port
,
1515 .config_port
= lpuart_config_port
,
1516 .verify_port
= lpuart_verify_port
,
1519 static struct lpuart_port
*lpuart_ports
[UART_NR
];
1521 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
1522 static void lpuart_console_putchar(struct uart_port
*port
, int ch
)
1524 while (!(readb(port
->membase
+ UARTSR1
) & UARTSR1_TDRE
))
1527 writeb(ch
, port
->membase
+ UARTDR
);
1530 static void lpuart32_console_putchar(struct uart_port
*port
, int ch
)
1532 while (!(lpuart32_read(port
->membase
+ UARTSTAT
) & UARTSTAT_TDRE
))
1535 lpuart32_write(ch
, port
->membase
+ UARTDATA
);
1539 lpuart_console_write(struct console
*co
, const char *s
, unsigned int count
)
1541 struct lpuart_port
*sport
= lpuart_ports
[co
->index
];
1542 unsigned char old_cr2
, cr2
;
1544 /* first save CR2 and then disable interrupts */
1545 cr2
= old_cr2
= readb(sport
->port
.membase
+ UARTCR2
);
1546 cr2
|= (UARTCR2_TE
| UARTCR2_RE
);
1547 cr2
&= ~(UARTCR2_TIE
| UARTCR2_TCIE
| UARTCR2_RIE
);
1548 writeb(cr2
, sport
->port
.membase
+ UARTCR2
);
1550 uart_console_write(&sport
->port
, s
, count
, lpuart_console_putchar
);
1552 /* wait for transmitter finish complete and restore CR2 */
1553 while (!(readb(sport
->port
.membase
+ UARTSR1
) & UARTSR1_TC
))
1556 writeb(old_cr2
, sport
->port
.membase
+ UARTCR2
);
1560 lpuart32_console_write(struct console
*co
, const char *s
, unsigned int count
)
1562 struct lpuart_port
*sport
= lpuart_ports
[co
->index
];
1563 unsigned long old_cr
, cr
;
1565 /* first save CR2 and then disable interrupts */
1566 cr
= old_cr
= lpuart32_read(sport
->port
.membase
+ UARTCTRL
);
1567 cr
|= (UARTCTRL_TE
| UARTCTRL_RE
);
1568 cr
&= ~(UARTCTRL_TIE
| UARTCTRL_TCIE
| UARTCTRL_RIE
);
1569 lpuart32_write(cr
, sport
->port
.membase
+ UARTCTRL
);
1571 uart_console_write(&sport
->port
, s
, count
, lpuart32_console_putchar
);
1573 /* wait for transmitter finish complete and restore CR2 */
1574 while (!(lpuart32_read(sport
->port
.membase
+ UARTSTAT
) & UARTSTAT_TC
))
1577 lpuart32_write(old_cr
, sport
->port
.membase
+ UARTCTRL
);
1581 * if the port was already initialised (eg, by a boot loader),
1582 * try to determine the current setup.
1585 lpuart_console_get_options(struct lpuart_port
*sport
, int *baud
,
1586 int *parity
, int *bits
)
1588 unsigned char cr
, bdh
, bdl
, brfa
;
1589 unsigned int sbr
, uartclk
, baud_raw
;
1591 cr
= readb(sport
->port
.membase
+ UARTCR2
);
1592 cr
&= UARTCR2_TE
| UARTCR2_RE
;
1596 /* ok, the port was enabled */
1598 cr
= readb(sport
->port
.membase
+ UARTCR1
);
1601 if (cr
& UARTCR1_PE
) {
1602 if (cr
& UARTCR1_PT
)
1613 bdh
= readb(sport
->port
.membase
+ UARTBDH
);
1614 bdh
&= UARTBDH_SBR_MASK
;
1615 bdl
= readb(sport
->port
.membase
+ UARTBDL
);
1619 brfa
= readb(sport
->port
.membase
+ UARTCR4
);
1620 brfa
&= UARTCR4_BRFA_MASK
;
1622 uartclk
= clk_get_rate(sport
->clk
);
1624 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1626 baud_raw
= uartclk
/ (16 * (sbr
+ brfa
/ 32));
1628 if (*baud
!= baud_raw
)
1629 printk(KERN_INFO
"Serial: Console lpuart rounded baud rate"
1630 "from %d to %d\n", baud_raw
, *baud
);
1634 lpuart32_console_get_options(struct lpuart_port
*sport
, int *baud
,
1635 int *parity
, int *bits
)
1637 unsigned long cr
, bd
;
1638 unsigned int sbr
, uartclk
, baud_raw
;
1640 cr
= lpuart32_read(sport
->port
.membase
+ UARTCTRL
);
1641 cr
&= UARTCTRL_TE
| UARTCTRL_RE
;
1645 /* ok, the port was enabled */
1647 cr
= lpuart32_read(sport
->port
.membase
+ UARTCTRL
);
1650 if (cr
& UARTCTRL_PE
) {
1651 if (cr
& UARTCTRL_PT
)
1657 if (cr
& UARTCTRL_M
)
1662 bd
= lpuart32_read(sport
->port
.membase
+ UARTBAUD
);
1663 bd
&= UARTBAUD_SBR_MASK
;
1665 uartclk
= clk_get_rate(sport
->clk
);
1667 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1669 baud_raw
= uartclk
/ (16 * sbr
);
1671 if (*baud
!= baud_raw
)
1672 printk(KERN_INFO
"Serial: Console lpuart rounded baud rate"
1673 "from %d to %d\n", baud_raw
, *baud
);
1676 static int __init
lpuart_console_setup(struct console
*co
, char *options
)
1678 struct lpuart_port
*sport
;
1685 * check whether an invalid uart number has been specified, and
1686 * if so, search for the first available port that does have
1689 if (co
->index
== -1 || co
->index
>= ARRAY_SIZE(lpuart_ports
))
1692 sport
= lpuart_ports
[co
->index
];
1697 uart_parse_options(options
, &baud
, &parity
, &bits
, &flow
);
1699 if (sport
->lpuart32
)
1700 lpuart32_console_get_options(sport
, &baud
, &parity
, &bits
);
1702 lpuart_console_get_options(sport
, &baud
, &parity
, &bits
);
1704 if (sport
->lpuart32
)
1705 lpuart32_setup_watermark(sport
);
1707 lpuart_setup_watermark(sport
);
1709 return uart_set_options(&sport
->port
, co
, baud
, parity
, bits
, flow
);
1712 static struct uart_driver lpuart_reg
;
1713 static struct console lpuart_console
= {
1715 .write
= lpuart_console_write
,
1716 .device
= uart_console_device
,
1717 .setup
= lpuart_console_setup
,
1718 .flags
= CON_PRINTBUFFER
,
1720 .data
= &lpuart_reg
,
1723 static struct console lpuart32_console
= {
1725 .write
= lpuart32_console_write
,
1726 .device
= uart_console_device
,
1727 .setup
= lpuart_console_setup
,
1728 .flags
= CON_PRINTBUFFER
,
1730 .data
= &lpuart_reg
,
1733 #define LPUART_CONSOLE (&lpuart_console)
1734 #define LPUART32_CONSOLE (&lpuart32_console)
1736 #define LPUART_CONSOLE NULL
1737 #define LPUART32_CONSOLE NULL
1740 static struct uart_driver lpuart_reg
= {
1741 .owner
= THIS_MODULE
,
1742 .driver_name
= DRIVER_NAME
,
1743 .dev_name
= DEV_NAME
,
1744 .nr
= ARRAY_SIZE(lpuart_ports
),
1745 .cons
= LPUART_CONSOLE
,
1748 static int lpuart_probe(struct platform_device
*pdev
)
1750 struct device_node
*np
= pdev
->dev
.of_node
;
1751 struct lpuart_port
*sport
;
1752 struct resource
*res
;
1755 sport
= devm_kzalloc(&pdev
->dev
, sizeof(*sport
), GFP_KERNEL
);
1759 pdev
->dev
.coherent_dma_mask
= 0;
1761 ret
= of_alias_get_id(np
, "serial");
1763 dev_err(&pdev
->dev
, "failed to get alias id, errno %d\n", ret
);
1766 sport
->port
.line
= ret
;
1767 sport
->lpuart32
= of_device_is_compatible(np
, "fsl,ls1021a-lpuart");
1769 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1770 sport
->port
.membase
= devm_ioremap_resource(&pdev
->dev
, res
);
1771 if (IS_ERR(sport
->port
.membase
))
1772 return PTR_ERR(sport
->port
.membase
);
1774 sport
->port
.mapbase
= res
->start
;
1775 sport
->port
.dev
= &pdev
->dev
;
1776 sport
->port
.type
= PORT_LPUART
;
1777 sport
->port
.iotype
= UPIO_MEM
;
1778 sport
->port
.irq
= platform_get_irq(pdev
, 0);
1779 if (sport
->lpuart32
)
1780 sport
->port
.ops
= &lpuart32_pops
;
1782 sport
->port
.ops
= &lpuart_pops
;
1783 sport
->port
.flags
= UPF_BOOT_AUTOCONF
;
1785 sport
->clk
= devm_clk_get(&pdev
->dev
, "ipg");
1786 if (IS_ERR(sport
->clk
)) {
1787 ret
= PTR_ERR(sport
->clk
);
1788 dev_err(&pdev
->dev
, "failed to get uart clk: %d\n", ret
);
1792 ret
= clk_prepare_enable(sport
->clk
);
1794 dev_err(&pdev
->dev
, "failed to enable uart clk: %d\n", ret
);
1798 sport
->port
.uartclk
= clk_get_rate(sport
->clk
);
1800 lpuart_ports
[sport
->port
.line
] = sport
;
1802 platform_set_drvdata(pdev
, &sport
->port
);
1804 if (sport
->lpuart32
)
1805 lpuart_reg
.cons
= LPUART32_CONSOLE
;
1807 lpuart_reg
.cons
= LPUART_CONSOLE
;
1809 ret
= uart_add_one_port(&lpuart_reg
, &sport
->port
);
1811 clk_disable_unprepare(sport
->clk
);
1815 sport
->dma_tx_chan
= dma_request_slave_channel(sport
->port
.dev
, "tx");
1816 if (!sport
->dma_tx_chan
)
1817 dev_info(sport
->port
.dev
, "DMA tx channel request failed, "
1818 "operating without tx DMA\n");
1820 sport
->dma_rx_chan
= dma_request_slave_channel(sport
->port
.dev
, "rx");
1821 if (!sport
->dma_rx_chan
)
1822 dev_info(sport
->port
.dev
, "DMA rx channel request failed, "
1823 "operating without rx DMA\n");
1828 static int lpuart_remove(struct platform_device
*pdev
)
1830 struct lpuart_port
*sport
= platform_get_drvdata(pdev
);
1832 uart_remove_one_port(&lpuart_reg
, &sport
->port
);
1834 clk_disable_unprepare(sport
->clk
);
1836 if (sport
->dma_tx_chan
)
1837 dma_release_channel(sport
->dma_tx_chan
);
1839 if (sport
->dma_rx_chan
)
1840 dma_release_channel(sport
->dma_rx_chan
);
1845 #ifdef CONFIG_PM_SLEEP
1846 static int lpuart_suspend(struct device
*dev
)
1848 struct lpuart_port
*sport
= dev_get_drvdata(dev
);
1850 uart_suspend_port(&lpuart_reg
, &sport
->port
);
1855 static int lpuart_resume(struct device
*dev
)
1857 struct lpuart_port
*sport
= dev_get_drvdata(dev
);
1860 if (sport
->lpuart32
) {
1861 lpuart32_setup_watermark(sport
);
1862 temp
= lpuart32_read(sport
->port
.membase
+ UARTCTRL
);
1863 temp
|= (UARTCTRL_RIE
| UARTCTRL_TIE
| UARTCTRL_RE
|
1864 UARTCTRL_TE
| UARTCTRL_ILIE
);
1865 lpuart32_write(temp
, sport
->port
.membase
+ UARTCTRL
);
1867 lpuart_setup_watermark(sport
);
1868 temp
= readb(sport
->port
.membase
+ UARTCR2
);
1869 temp
|= (UARTCR2_RIE
| UARTCR2_TIE
| UARTCR2_RE
| UARTCR2_TE
);
1870 writeb(temp
, sport
->port
.membase
+ UARTCR2
);
1873 uart_resume_port(&lpuart_reg
, &sport
->port
);
1879 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops
, lpuart_suspend
, lpuart_resume
);
1881 static struct platform_driver lpuart_driver
= {
1882 .probe
= lpuart_probe
,
1883 .remove
= lpuart_remove
,
1885 .name
= "fsl-lpuart",
1886 .of_match_table
= lpuart_dt_ids
,
1887 .pm
= &lpuart_pm_ops
,
1891 static int __init
lpuart_serial_init(void)
1893 int ret
= uart_register_driver(&lpuart_reg
);
1898 ret
= platform_driver_register(&lpuart_driver
);
1900 uart_unregister_driver(&lpuart_reg
);
1905 static void __exit
lpuart_serial_exit(void)
1907 platform_driver_unregister(&lpuart_driver
);
1908 uart_unregister_driver(&lpuart_reg
);
1911 module_init(lpuart_serial_init
);
1912 module_exit(lpuart_serial_exit
);
1914 MODULE_DESCRIPTION("Freescale lpuart serial port driver");
1915 MODULE_LICENSE("GPL v2");