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ASoC: cs4265: Convert to params_width()
[deliverable/linux.git] / drivers / tty / serial / fsl_lpuart.c
1 /*
2 * Freescale lpuart serial port driver
3 *
4 * Copyright 2012-2013 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12 #if defined(CONFIG_SERIAL_FSL_LPUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
13 #define SUPPORT_SYSRQ
14 #endif
15
16 #include <linux/clk.h>
17 #include <linux/console.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/dmaengine.h>
20 #include <linux/dmapool.h>
21 #include <linux/io.h>
22 #include <linux/irq.h>
23 #include <linux/module.h>
24 #include <linux/of.h>
25 #include <linux/of_device.h>
26 #include <linux/of_dma.h>
27 #include <linux/serial_core.h>
28 #include <linux/slab.h>
29 #include <linux/tty_flip.h>
30
31 /* All registers are 8-bit width */
32 #define UARTBDH 0x00
33 #define UARTBDL 0x01
34 #define UARTCR1 0x02
35 #define UARTCR2 0x03
36 #define UARTSR1 0x04
37 #define UARTCR3 0x06
38 #define UARTDR 0x07
39 #define UARTCR4 0x0a
40 #define UARTCR5 0x0b
41 #define UARTMODEM 0x0d
42 #define UARTPFIFO 0x10
43 #define UARTCFIFO 0x11
44 #define UARTSFIFO 0x12
45 #define UARTTWFIFO 0x13
46 #define UARTTCFIFO 0x14
47 #define UARTRWFIFO 0x15
48
49 #define UARTBDH_LBKDIE 0x80
50 #define UARTBDH_RXEDGIE 0x40
51 #define UARTBDH_SBR_MASK 0x1f
52
53 #define UARTCR1_LOOPS 0x80
54 #define UARTCR1_RSRC 0x20
55 #define UARTCR1_M 0x10
56 #define UARTCR1_WAKE 0x08
57 #define UARTCR1_ILT 0x04
58 #define UARTCR1_PE 0x02
59 #define UARTCR1_PT 0x01
60
61 #define UARTCR2_TIE 0x80
62 #define UARTCR2_TCIE 0x40
63 #define UARTCR2_RIE 0x20
64 #define UARTCR2_ILIE 0x10
65 #define UARTCR2_TE 0x08
66 #define UARTCR2_RE 0x04
67 #define UARTCR2_RWU 0x02
68 #define UARTCR2_SBK 0x01
69
70 #define UARTSR1_TDRE 0x80
71 #define UARTSR1_TC 0x40
72 #define UARTSR1_RDRF 0x20
73 #define UARTSR1_IDLE 0x10
74 #define UARTSR1_OR 0x08
75 #define UARTSR1_NF 0x04
76 #define UARTSR1_FE 0x02
77 #define UARTSR1_PE 0x01
78
79 #define UARTCR3_R8 0x80
80 #define UARTCR3_T8 0x40
81 #define UARTCR3_TXDIR 0x20
82 #define UARTCR3_TXINV 0x10
83 #define UARTCR3_ORIE 0x08
84 #define UARTCR3_NEIE 0x04
85 #define UARTCR3_FEIE 0x02
86 #define UARTCR3_PEIE 0x01
87
88 #define UARTCR4_MAEN1 0x80
89 #define UARTCR4_MAEN2 0x40
90 #define UARTCR4_M10 0x20
91 #define UARTCR4_BRFA_MASK 0x1f
92 #define UARTCR4_BRFA_OFF 0
93
94 #define UARTCR5_TDMAS 0x80
95 #define UARTCR5_RDMAS 0x20
96
97 #define UARTMODEM_RXRTSE 0x08
98 #define UARTMODEM_TXRTSPOL 0x04
99 #define UARTMODEM_TXRTSE 0x02
100 #define UARTMODEM_TXCTSE 0x01
101
102 #define UARTPFIFO_TXFE 0x80
103 #define UARTPFIFO_FIFOSIZE_MASK 0x7
104 #define UARTPFIFO_TXSIZE_OFF 4
105 #define UARTPFIFO_RXFE 0x08
106 #define UARTPFIFO_RXSIZE_OFF 0
107
108 #define UARTCFIFO_TXFLUSH 0x80
109 #define UARTCFIFO_RXFLUSH 0x40
110 #define UARTCFIFO_RXOFE 0x04
111 #define UARTCFIFO_TXOFE 0x02
112 #define UARTCFIFO_RXUFE 0x01
113
114 #define UARTSFIFO_TXEMPT 0x80
115 #define UARTSFIFO_RXEMPT 0x40
116 #define UARTSFIFO_RXOF 0x04
117 #define UARTSFIFO_TXOF 0x02
118 #define UARTSFIFO_RXUF 0x01
119
120 #define DMA_MAXBURST 16
121 #define DMA_MAXBURST_MASK (DMA_MAXBURST - 1)
122 #define FSL_UART_RX_DMA_BUFFER_SIZE 64
123
124 #define DRIVER_NAME "fsl-lpuart"
125 #define DEV_NAME "ttyLP"
126 #define UART_NR 6
127
128 struct lpuart_port {
129 struct uart_port port;
130 struct clk *clk;
131 unsigned int txfifo_size;
132 unsigned int rxfifo_size;
133
134 bool lpuart_dma_use;
135 struct dma_chan *dma_tx_chan;
136 struct dma_chan *dma_rx_chan;
137 struct dma_async_tx_descriptor *dma_tx_desc;
138 struct dma_async_tx_descriptor *dma_rx_desc;
139 dma_addr_t dma_tx_buf_bus;
140 dma_addr_t dma_rx_buf_bus;
141 dma_cookie_t dma_tx_cookie;
142 dma_cookie_t dma_rx_cookie;
143 unsigned char *dma_tx_buf_virt;
144 unsigned char *dma_rx_buf_virt;
145 unsigned int dma_tx_bytes;
146 unsigned int dma_rx_bytes;
147 int dma_tx_in_progress;
148 int dma_rx_in_progress;
149 unsigned int dma_rx_timeout;
150 struct timer_list lpuart_timer;
151 };
152
153 static struct of_device_id lpuart_dt_ids[] = {
154 {
155 .compatible = "fsl,vf610-lpuart",
156 },
157 { /* sentinel */ }
158 };
159 MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
160
161 /* Forward declare this for the dma callbacks*/
162 static void lpuart_dma_tx_complete(void *arg);
163 static void lpuart_dma_rx_complete(void *arg);
164
165 static void lpuart_stop_tx(struct uart_port *port)
166 {
167 unsigned char temp;
168
169 temp = readb(port->membase + UARTCR2);
170 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
171 writeb(temp, port->membase + UARTCR2);
172 }
173
174 static void lpuart_stop_rx(struct uart_port *port)
175 {
176 unsigned char temp;
177
178 temp = readb(port->membase + UARTCR2);
179 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
180 }
181
182 static void lpuart_enable_ms(struct uart_port *port)
183 {
184 }
185
186 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport,
187 struct tty_port *tty, int count)
188 {
189 int copied;
190
191 sport->port.icount.rx += count;
192
193 if (!tty) {
194 dev_err(sport->port.dev, "No tty port\n");
195 return;
196 }
197
198 dma_sync_single_for_cpu(sport->port.dev, sport->dma_rx_buf_bus,
199 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
200 copied = tty_insert_flip_string(tty,
201 ((unsigned char *)(sport->dma_rx_buf_virt)), count);
202
203 if (copied != count) {
204 WARN_ON(1);
205 dev_err(sport->port.dev, "RxData copy to tty layer failed\n");
206 }
207
208 dma_sync_single_for_device(sport->port.dev, sport->dma_rx_buf_bus,
209 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
210 }
211
212 static void lpuart_pio_tx(struct lpuart_port *sport)
213 {
214 struct circ_buf *xmit = &sport->port.state->xmit;
215 unsigned long flags;
216
217 spin_lock_irqsave(&sport->port.lock, flags);
218
219 while (!uart_circ_empty(xmit) &&
220 readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size) {
221 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
222 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
223 sport->port.icount.tx++;
224 }
225
226 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
227 uart_write_wakeup(&sport->port);
228
229 if (uart_circ_empty(xmit))
230 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS,
231 sport->port.membase + UARTCR5);
232
233 spin_unlock_irqrestore(&sport->port.lock, flags);
234 }
235
236 static int lpuart_dma_tx(struct lpuart_port *sport, unsigned long count)
237 {
238 struct circ_buf *xmit = &sport->port.state->xmit;
239 dma_addr_t tx_bus_addr;
240
241 dma_sync_single_for_device(sport->port.dev, sport->dma_tx_buf_bus,
242 UART_XMIT_SIZE, DMA_TO_DEVICE);
243 sport->dma_tx_bytes = count & ~(DMA_MAXBURST_MASK);
244 tx_bus_addr = sport->dma_tx_buf_bus + xmit->tail;
245 sport->dma_tx_desc = dmaengine_prep_slave_single(sport->dma_tx_chan,
246 tx_bus_addr, sport->dma_tx_bytes,
247 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
248
249 if (!sport->dma_tx_desc) {
250 dev_err(sport->port.dev, "Not able to get desc for tx\n");
251 return -EIO;
252 }
253
254 sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
255 sport->dma_tx_desc->callback_param = sport;
256 sport->dma_tx_in_progress = 1;
257 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
258 dma_async_issue_pending(sport->dma_tx_chan);
259
260 return 0;
261 }
262
263 static void lpuart_prepare_tx(struct lpuart_port *sport)
264 {
265 struct circ_buf *xmit = &sport->port.state->xmit;
266 unsigned long count = CIRC_CNT_TO_END(xmit->head,
267 xmit->tail, UART_XMIT_SIZE);
268
269 if (!count)
270 return;
271
272 if (count < DMA_MAXBURST)
273 writeb(readb(sport->port.membase + UARTCR5) & ~UARTCR5_TDMAS,
274 sport->port.membase + UARTCR5);
275 else {
276 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_TDMAS,
277 sport->port.membase + UARTCR5);
278 lpuart_dma_tx(sport, count);
279 }
280 }
281
282 static void lpuart_dma_tx_complete(void *arg)
283 {
284 struct lpuart_port *sport = arg;
285 struct circ_buf *xmit = &sport->port.state->xmit;
286 unsigned long flags;
287
288 async_tx_ack(sport->dma_tx_desc);
289
290 spin_lock_irqsave(&sport->port.lock, flags);
291
292 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
293 sport->dma_tx_in_progress = 0;
294
295 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
296 uart_write_wakeup(&sport->port);
297
298 lpuart_prepare_tx(sport);
299
300 spin_unlock_irqrestore(&sport->port.lock, flags);
301 }
302
303 static int lpuart_dma_rx(struct lpuart_port *sport)
304 {
305 dma_sync_single_for_device(sport->port.dev, sport->dma_rx_buf_bus,
306 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_TO_DEVICE);
307 sport->dma_rx_desc = dmaengine_prep_slave_single(sport->dma_rx_chan,
308 sport->dma_rx_buf_bus, FSL_UART_RX_DMA_BUFFER_SIZE,
309 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
310
311 if (!sport->dma_rx_desc) {
312 dev_err(sport->port.dev, "Not able to get desc for rx\n");
313 return -EIO;
314 }
315
316 sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
317 sport->dma_rx_desc->callback_param = sport;
318 sport->dma_rx_in_progress = 1;
319 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
320 dma_async_issue_pending(sport->dma_rx_chan);
321
322 return 0;
323 }
324
325 static void lpuart_dma_rx_complete(void *arg)
326 {
327 struct lpuart_port *sport = arg;
328 struct tty_port *port = &sport->port.state->port;
329 unsigned long flags;
330
331 async_tx_ack(sport->dma_rx_desc);
332
333 spin_lock_irqsave(&sport->port.lock, flags);
334
335 sport->dma_rx_in_progress = 0;
336 lpuart_copy_rx_to_tty(sport, port, FSL_UART_RX_DMA_BUFFER_SIZE);
337 tty_flip_buffer_push(port);
338 lpuart_dma_rx(sport);
339
340 spin_unlock_irqrestore(&sport->port.lock, flags);
341 }
342
343 static void lpuart_timer_func(unsigned long data)
344 {
345 struct lpuart_port *sport = (struct lpuart_port *)data;
346 struct tty_port *port = &sport->port.state->port;
347 struct dma_tx_state state;
348 unsigned long flags;
349 unsigned char temp;
350 int count;
351
352 del_timer(&sport->lpuart_timer);
353 dmaengine_pause(sport->dma_rx_chan);
354 dmaengine_tx_status(sport->dma_rx_chan, sport->dma_rx_cookie, &state);
355 dmaengine_terminate_all(sport->dma_rx_chan);
356 count = FSL_UART_RX_DMA_BUFFER_SIZE - state.residue;
357 async_tx_ack(sport->dma_rx_desc);
358
359 spin_lock_irqsave(&sport->port.lock, flags);
360
361 sport->dma_rx_in_progress = 0;
362 lpuart_copy_rx_to_tty(sport, port, count);
363 tty_flip_buffer_push(port);
364 temp = readb(sport->port.membase + UARTCR5);
365 writeb(temp & ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
366
367 spin_unlock_irqrestore(&sport->port.lock, flags);
368 }
369
370 static inline void lpuart_prepare_rx(struct lpuart_port *sport)
371 {
372 unsigned long flags;
373 unsigned char temp;
374
375 spin_lock_irqsave(&sport->port.lock, flags);
376
377 init_timer(&sport->lpuart_timer);
378 sport->lpuart_timer.function = lpuart_timer_func;
379 sport->lpuart_timer.data = (unsigned long)sport;
380 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
381 add_timer(&sport->lpuart_timer);
382
383 lpuart_dma_rx(sport);
384 temp = readb(sport->port.membase + UARTCR5);
385 writeb(temp | UARTCR5_RDMAS, sport->port.membase + UARTCR5);
386
387 spin_unlock_irqrestore(&sport->port.lock, flags);
388 }
389
390 static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
391 {
392 struct circ_buf *xmit = &sport->port.state->xmit;
393
394 while (!uart_circ_empty(xmit) &&
395 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
396 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
397 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
398 sport->port.icount.tx++;
399 }
400
401 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
402 uart_write_wakeup(&sport->port);
403
404 if (uart_circ_empty(xmit))
405 lpuart_stop_tx(&sport->port);
406 }
407
408 static void lpuart_start_tx(struct uart_port *port)
409 {
410 struct lpuart_port *sport = container_of(port,
411 struct lpuart_port, port);
412 struct circ_buf *xmit = &sport->port.state->xmit;
413 unsigned char temp;
414
415 temp = readb(port->membase + UARTCR2);
416 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
417
418 if (sport->lpuart_dma_use) {
419 if (!uart_circ_empty(xmit) && !sport->dma_tx_in_progress)
420 lpuart_prepare_tx(sport);
421 } else {
422 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
423 lpuart_transmit_buffer(sport);
424 }
425 }
426
427 static irqreturn_t lpuart_txint(int irq, void *dev_id)
428 {
429 struct lpuart_port *sport = dev_id;
430 struct circ_buf *xmit = &sport->port.state->xmit;
431 unsigned long flags;
432
433 spin_lock_irqsave(&sport->port.lock, flags);
434 if (sport->port.x_char) {
435 writeb(sport->port.x_char, sport->port.membase + UARTDR);
436 goto out;
437 }
438
439 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
440 lpuart_stop_tx(&sport->port);
441 goto out;
442 }
443
444 lpuart_transmit_buffer(sport);
445
446 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
447 uart_write_wakeup(&sport->port);
448
449 out:
450 spin_unlock_irqrestore(&sport->port.lock, flags);
451 return IRQ_HANDLED;
452 }
453
454 static irqreturn_t lpuart_rxint(int irq, void *dev_id)
455 {
456 struct lpuart_port *sport = dev_id;
457 unsigned int flg, ignored = 0;
458 struct tty_port *port = &sport->port.state->port;
459 unsigned long flags;
460 unsigned char rx, sr;
461
462 spin_lock_irqsave(&sport->port.lock, flags);
463
464 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
465 flg = TTY_NORMAL;
466 sport->port.icount.rx++;
467 /*
468 * to clear the FE, OR, NF, FE, PE flags,
469 * read SR1 then read DR
470 */
471 sr = readb(sport->port.membase + UARTSR1);
472 rx = readb(sport->port.membase + UARTDR);
473
474 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
475 continue;
476
477 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
478 if (sr & UARTSR1_PE)
479 sport->port.icount.parity++;
480 else if (sr & UARTSR1_FE)
481 sport->port.icount.frame++;
482
483 if (sr & UARTSR1_OR)
484 sport->port.icount.overrun++;
485
486 if (sr & sport->port.ignore_status_mask) {
487 if (++ignored > 100)
488 goto out;
489 continue;
490 }
491
492 sr &= sport->port.read_status_mask;
493
494 if (sr & UARTSR1_PE)
495 flg = TTY_PARITY;
496 else if (sr & UARTSR1_FE)
497 flg = TTY_FRAME;
498
499 if (sr & UARTSR1_OR)
500 flg = TTY_OVERRUN;
501
502 #ifdef SUPPORT_SYSRQ
503 sport->port.sysrq = 0;
504 #endif
505 }
506
507 tty_insert_flip_char(port, rx, flg);
508 }
509
510 out:
511 spin_unlock_irqrestore(&sport->port.lock, flags);
512
513 tty_flip_buffer_push(port);
514 return IRQ_HANDLED;
515 }
516
517 static irqreturn_t lpuart_int(int irq, void *dev_id)
518 {
519 struct lpuart_port *sport = dev_id;
520 unsigned char sts;
521
522 sts = readb(sport->port.membase + UARTSR1);
523
524 if (sts & UARTSR1_RDRF) {
525 if (sport->lpuart_dma_use)
526 lpuart_prepare_rx(sport);
527 else
528 lpuart_rxint(irq, dev_id);
529 }
530 if (sts & UARTSR1_TDRE &&
531 !(readb(sport->port.membase + UARTCR5) & UARTCR5_TDMAS)) {
532 if (sport->lpuart_dma_use)
533 lpuart_pio_tx(sport);
534 else
535 lpuart_txint(irq, dev_id);
536 }
537
538 return IRQ_HANDLED;
539 }
540
541 /* return TIOCSER_TEMT when transmitter is not busy */
542 static unsigned int lpuart_tx_empty(struct uart_port *port)
543 {
544 return (readb(port->membase + UARTSR1) & UARTSR1_TC) ?
545 TIOCSER_TEMT : 0;
546 }
547
548 static unsigned int lpuart_get_mctrl(struct uart_port *port)
549 {
550 unsigned int temp = 0;
551 unsigned char reg;
552
553 reg = readb(port->membase + UARTMODEM);
554 if (reg & UARTMODEM_TXCTSE)
555 temp |= TIOCM_CTS;
556
557 if (reg & UARTMODEM_RXRTSE)
558 temp |= TIOCM_RTS;
559
560 return temp;
561 }
562
563 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
564 {
565 unsigned char temp;
566
567 temp = readb(port->membase + UARTMODEM) &
568 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
569
570 if (mctrl & TIOCM_RTS)
571 temp |= UARTMODEM_RXRTSE;
572
573 if (mctrl & TIOCM_CTS)
574 temp |= UARTMODEM_TXCTSE;
575
576 writeb(temp, port->membase + UARTMODEM);
577 }
578
579 static void lpuart_break_ctl(struct uart_port *port, int break_state)
580 {
581 unsigned char temp;
582
583 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
584
585 if (break_state != 0)
586 temp |= UARTCR2_SBK;
587
588 writeb(temp, port->membase + UARTCR2);
589 }
590
591 static void lpuart_setup_watermark(struct lpuart_port *sport)
592 {
593 unsigned char val, cr2;
594 unsigned char cr2_saved;
595
596 cr2 = readb(sport->port.membase + UARTCR2);
597 cr2_saved = cr2;
598 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
599 UARTCR2_RIE | UARTCR2_RE);
600 writeb(cr2, sport->port.membase + UARTCR2);
601
602 /* determine FIFO size and enable FIFO mode */
603 val = readb(sport->port.membase + UARTPFIFO);
604
605 sport->txfifo_size = 0x1 << (((val >> UARTPFIFO_TXSIZE_OFF) &
606 UARTPFIFO_FIFOSIZE_MASK) + 1);
607
608 sport->rxfifo_size = 0x1 << (((val >> UARTPFIFO_RXSIZE_OFF) &
609 UARTPFIFO_FIFOSIZE_MASK) + 1);
610
611 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
612 sport->port.membase + UARTPFIFO);
613
614 /* flush Tx and Rx FIFO */
615 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
616 sport->port.membase + UARTCFIFO);
617
618 writeb(0, sport->port.membase + UARTTWFIFO);
619 writeb(1, sport->port.membase + UARTRWFIFO);
620
621 /* Restore cr2 */
622 writeb(cr2_saved, sport->port.membase + UARTCR2);
623 }
624
625 static int lpuart_dma_tx_request(struct uart_port *port)
626 {
627 struct lpuart_port *sport = container_of(port,
628 struct lpuart_port, port);
629 struct dma_chan *tx_chan;
630 struct dma_slave_config dma_tx_sconfig;
631 dma_addr_t dma_bus;
632 unsigned char *dma_buf;
633 int ret;
634
635 tx_chan = dma_request_slave_channel(sport->port.dev, "tx");
636
637 if (!tx_chan) {
638 dev_err(sport->port.dev, "Dma tx channel request failed!\n");
639 return -ENODEV;
640 }
641
642 dma_bus = dma_map_single(tx_chan->device->dev,
643 sport->port.state->xmit.buf,
644 UART_XMIT_SIZE, DMA_TO_DEVICE);
645
646 if (dma_mapping_error(tx_chan->device->dev, dma_bus)) {
647 dev_err(sport->port.dev, "dma_map_single tx failed\n");
648 dma_release_channel(tx_chan);
649 return -ENOMEM;
650 }
651
652 dma_buf = sport->port.state->xmit.buf;
653 dma_tx_sconfig.dst_addr = sport->port.mapbase + UARTDR;
654 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
655 dma_tx_sconfig.dst_maxburst = DMA_MAXBURST;
656 dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
657 ret = dmaengine_slave_config(tx_chan, &dma_tx_sconfig);
658
659 if (ret < 0) {
660 dev_err(sport->port.dev,
661 "Dma slave config failed, err = %d\n", ret);
662 dma_release_channel(tx_chan);
663 return ret;
664 }
665
666 sport->dma_tx_chan = tx_chan;
667 sport->dma_tx_buf_virt = dma_buf;
668 sport->dma_tx_buf_bus = dma_bus;
669 sport->dma_tx_in_progress = 0;
670
671 return 0;
672 }
673
674 static int lpuart_dma_rx_request(struct uart_port *port)
675 {
676 struct lpuart_port *sport = container_of(port,
677 struct lpuart_port, port);
678 struct dma_chan *rx_chan;
679 struct dma_slave_config dma_rx_sconfig;
680 dma_addr_t dma_bus;
681 unsigned char *dma_buf;
682 int ret;
683
684 rx_chan = dma_request_slave_channel(sport->port.dev, "rx");
685
686 if (!rx_chan) {
687 dev_err(sport->port.dev, "Dma rx channel request failed!\n");
688 return -ENODEV;
689 }
690
691 dma_buf = devm_kzalloc(sport->port.dev,
692 FSL_UART_RX_DMA_BUFFER_SIZE, GFP_KERNEL);
693
694 if (!dma_buf) {
695 dev_err(sport->port.dev, "Dma rx alloc failed\n");
696 dma_release_channel(rx_chan);
697 return -ENOMEM;
698 }
699
700 dma_bus = dma_map_single(rx_chan->device->dev, dma_buf,
701 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
702
703 if (dma_mapping_error(rx_chan->device->dev, dma_bus)) {
704 dev_err(sport->port.dev, "dma_map_single rx failed\n");
705 dma_release_channel(rx_chan);
706 return -ENOMEM;
707 }
708
709 dma_rx_sconfig.src_addr = sport->port.mapbase + UARTDR;
710 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
711 dma_rx_sconfig.src_maxburst = 1;
712 dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
713 ret = dmaengine_slave_config(rx_chan, &dma_rx_sconfig);
714
715 if (ret < 0) {
716 dev_err(sport->port.dev,
717 "Dma slave config failed, err = %d\n", ret);
718 dma_release_channel(rx_chan);
719 return ret;
720 }
721
722 sport->dma_rx_chan = rx_chan;
723 sport->dma_rx_buf_virt = dma_buf;
724 sport->dma_rx_buf_bus = dma_bus;
725 sport->dma_rx_in_progress = 0;
726
727 sport->dma_rx_timeout = (sport->port.timeout - HZ / 50) *
728 FSL_UART_RX_DMA_BUFFER_SIZE * 3 /
729 sport->rxfifo_size / 2;
730
731 if (sport->dma_rx_timeout < msecs_to_jiffies(20))
732 sport->dma_rx_timeout = msecs_to_jiffies(20);
733
734 return 0;
735 }
736
737 static void lpuart_dma_tx_free(struct uart_port *port)
738 {
739 struct lpuart_port *sport = container_of(port,
740 struct lpuart_port, port);
741 struct dma_chan *dma_chan;
742
743 dma_unmap_single(sport->port.dev, sport->dma_tx_buf_bus,
744 UART_XMIT_SIZE, DMA_TO_DEVICE);
745 dma_chan = sport->dma_tx_chan;
746 sport->dma_tx_chan = NULL;
747 sport->dma_tx_buf_bus = 0;
748 sport->dma_tx_buf_virt = NULL;
749 dma_release_channel(dma_chan);
750 }
751
752 static void lpuart_dma_rx_free(struct uart_port *port)
753 {
754 struct lpuart_port *sport = container_of(port,
755 struct lpuart_port, port);
756 struct dma_chan *dma_chan;
757
758 dma_unmap_single(sport->port.dev, sport->dma_rx_buf_bus,
759 FSL_UART_RX_DMA_BUFFER_SIZE, DMA_FROM_DEVICE);
760
761 dma_chan = sport->dma_rx_chan;
762 sport->dma_rx_chan = NULL;
763 sport->dma_rx_buf_bus = 0;
764 sport->dma_rx_buf_virt = NULL;
765 dma_release_channel(dma_chan);
766 }
767
768 static int lpuart_startup(struct uart_port *port)
769 {
770 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
771 int ret;
772 unsigned long flags;
773 unsigned char temp;
774
775 /*whether use dma support by dma request results*/
776 if (lpuart_dma_tx_request(port) || lpuart_dma_rx_request(port)) {
777 sport->lpuart_dma_use = false;
778 } else {
779 sport->lpuart_dma_use = true;
780 temp = readb(port->membase + UARTCR5);
781 writeb(temp | UARTCR5_TDMAS, port->membase + UARTCR5);
782 }
783
784 ret = devm_request_irq(port->dev, port->irq, lpuart_int, 0,
785 DRIVER_NAME, sport);
786 if (ret)
787 return ret;
788
789 spin_lock_irqsave(&sport->port.lock, flags);
790
791 lpuart_setup_watermark(sport);
792
793 temp = readb(sport->port.membase + UARTCR2);
794 temp |= (UARTCR2_RIE | UARTCR2_TIE | UARTCR2_RE | UARTCR2_TE);
795 writeb(temp, sport->port.membase + UARTCR2);
796
797 spin_unlock_irqrestore(&sport->port.lock, flags);
798 return 0;
799 }
800
801 static void lpuart_shutdown(struct uart_port *port)
802 {
803 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
804 unsigned char temp;
805 unsigned long flags;
806
807 spin_lock_irqsave(&port->lock, flags);
808
809 /* disable Rx/Tx and interrupts */
810 temp = readb(port->membase + UARTCR2);
811 temp &= ~(UARTCR2_TE | UARTCR2_RE |
812 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
813 writeb(temp, port->membase + UARTCR2);
814
815 spin_unlock_irqrestore(&port->lock, flags);
816
817 devm_free_irq(port->dev, port->irq, sport);
818
819 if (sport->lpuart_dma_use) {
820 lpuart_dma_tx_free(port);
821 lpuart_dma_rx_free(port);
822 }
823 }
824
825 static void
826 lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
827 struct ktermios *old)
828 {
829 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
830 unsigned long flags;
831 unsigned char cr1, old_cr1, old_cr2, cr4, bdh, modem;
832 unsigned int baud;
833 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
834 unsigned int sbr, brfa;
835
836 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
837 old_cr2 = readb(sport->port.membase + UARTCR2);
838 cr4 = readb(sport->port.membase + UARTCR4);
839 bdh = readb(sport->port.membase + UARTBDH);
840 modem = readb(sport->port.membase + UARTMODEM);
841 /*
842 * only support CS8 and CS7, and for CS7 must enable PE.
843 * supported mode:
844 * - (7,e/o,1)
845 * - (8,n,1)
846 * - (8,m/s,1)
847 * - (8,e/o,1)
848 */
849 while ((termios->c_cflag & CSIZE) != CS8 &&
850 (termios->c_cflag & CSIZE) != CS7) {
851 termios->c_cflag &= ~CSIZE;
852 termios->c_cflag |= old_csize;
853 old_csize = CS8;
854 }
855
856 if ((termios->c_cflag & CSIZE) == CS8 ||
857 (termios->c_cflag & CSIZE) == CS7)
858 cr1 = old_cr1 & ~UARTCR1_M;
859
860 if (termios->c_cflag & CMSPAR) {
861 if ((termios->c_cflag & CSIZE) != CS8) {
862 termios->c_cflag &= ~CSIZE;
863 termios->c_cflag |= CS8;
864 }
865 cr1 |= UARTCR1_M;
866 }
867
868 if (termios->c_cflag & CRTSCTS) {
869 modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
870 } else {
871 termios->c_cflag &= ~CRTSCTS;
872 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
873 }
874
875 if (termios->c_cflag & CSTOPB)
876 termios->c_cflag &= ~CSTOPB;
877
878 /* parity must be enabled when CS7 to match 8-bits format */
879 if ((termios->c_cflag & CSIZE) == CS7)
880 termios->c_cflag |= PARENB;
881
882 if ((termios->c_cflag & PARENB)) {
883 if (termios->c_cflag & CMSPAR) {
884 cr1 &= ~UARTCR1_PE;
885 cr1 |= UARTCR1_M;
886 } else {
887 cr1 |= UARTCR1_PE;
888 if ((termios->c_cflag & CSIZE) == CS8)
889 cr1 |= UARTCR1_M;
890 if (termios->c_cflag & PARODD)
891 cr1 |= UARTCR1_PT;
892 else
893 cr1 &= ~UARTCR1_PT;
894 }
895 }
896
897 /* ask the core to calculate the divisor */
898 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
899
900 spin_lock_irqsave(&sport->port.lock, flags);
901
902 sport->port.read_status_mask = 0;
903 if (termios->c_iflag & INPCK)
904 sport->port.read_status_mask |= (UARTSR1_FE | UARTSR1_PE);
905 if (termios->c_iflag & (BRKINT | PARMRK))
906 sport->port.read_status_mask |= UARTSR1_FE;
907
908 /* characters to ignore */
909 sport->port.ignore_status_mask = 0;
910 if (termios->c_iflag & IGNPAR)
911 sport->port.ignore_status_mask |= UARTSR1_PE;
912 if (termios->c_iflag & IGNBRK) {
913 sport->port.ignore_status_mask |= UARTSR1_FE;
914 /*
915 * if we're ignoring parity and break indicators,
916 * ignore overruns too (for real raw support).
917 */
918 if (termios->c_iflag & IGNPAR)
919 sport->port.ignore_status_mask |= UARTSR1_OR;
920 }
921
922 /* update the per-port timeout */
923 uart_update_timeout(port, termios->c_cflag, baud);
924
925 /* wait transmit engin complete */
926 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
927 barrier();
928
929 /* disable transmit and receive */
930 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
931 sport->port.membase + UARTCR2);
932
933 sbr = sport->port.uartclk / (16 * baud);
934 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
935 bdh &= ~UARTBDH_SBR_MASK;
936 bdh |= (sbr >> 8) & 0x1F;
937 cr4 &= ~UARTCR4_BRFA_MASK;
938 brfa &= UARTCR4_BRFA_MASK;
939 writeb(cr4 | brfa, sport->port.membase + UARTCR4);
940 writeb(bdh, sport->port.membase + UARTBDH);
941 writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
942 writeb(cr1, sport->port.membase + UARTCR1);
943 writeb(modem, sport->port.membase + UARTMODEM);
944
945 /* restore control register */
946 writeb(old_cr2, sport->port.membase + UARTCR2);
947
948 spin_unlock_irqrestore(&sport->port.lock, flags);
949 }
950
951 static const char *lpuart_type(struct uart_port *port)
952 {
953 return "FSL_LPUART";
954 }
955
956 static void lpuart_release_port(struct uart_port *port)
957 {
958 /* nothing to do */
959 }
960
961 static int lpuart_request_port(struct uart_port *port)
962 {
963 return 0;
964 }
965
966 /* configure/autoconfigure the port */
967 static void lpuart_config_port(struct uart_port *port, int flags)
968 {
969 if (flags & UART_CONFIG_TYPE)
970 port->type = PORT_LPUART;
971 }
972
973 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
974 {
975 int ret = 0;
976
977 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
978 ret = -EINVAL;
979 if (port->irq != ser->irq)
980 ret = -EINVAL;
981 if (ser->io_type != UPIO_MEM)
982 ret = -EINVAL;
983 if (port->uartclk / 16 != ser->baud_base)
984 ret = -EINVAL;
985 if (port->iobase != ser->port)
986 ret = -EINVAL;
987 if (ser->hub6 != 0)
988 ret = -EINVAL;
989 return ret;
990 }
991
992 static struct uart_ops lpuart_pops = {
993 .tx_empty = lpuart_tx_empty,
994 .set_mctrl = lpuart_set_mctrl,
995 .get_mctrl = lpuart_get_mctrl,
996 .stop_tx = lpuart_stop_tx,
997 .start_tx = lpuart_start_tx,
998 .stop_rx = lpuart_stop_rx,
999 .enable_ms = lpuart_enable_ms,
1000 .break_ctl = lpuart_break_ctl,
1001 .startup = lpuart_startup,
1002 .shutdown = lpuart_shutdown,
1003 .set_termios = lpuart_set_termios,
1004 .type = lpuart_type,
1005 .request_port = lpuart_request_port,
1006 .release_port = lpuart_release_port,
1007 .config_port = lpuart_config_port,
1008 .verify_port = lpuart_verify_port,
1009 };
1010
1011 static struct lpuart_port *lpuart_ports[UART_NR];
1012
1013 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
1014 static void lpuart_console_putchar(struct uart_port *port, int ch)
1015 {
1016 while (!(readb(port->membase + UARTSR1) & UARTSR1_TDRE))
1017 barrier();
1018
1019 writeb(ch, port->membase + UARTDR);
1020 }
1021
1022 static void
1023 lpuart_console_write(struct console *co, const char *s, unsigned int count)
1024 {
1025 struct lpuart_port *sport = lpuart_ports[co->index];
1026 unsigned char old_cr2, cr2;
1027
1028 /* first save CR2 and then disable interrupts */
1029 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
1030 cr2 |= (UARTCR2_TE | UARTCR2_RE);
1031 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1032 writeb(cr2, sport->port.membase + UARTCR2);
1033
1034 uart_console_write(&sport->port, s, count, lpuart_console_putchar);
1035
1036 /* wait for transmitter finish complete and restore CR2 */
1037 while (!(readb(sport->port.membase + UARTSR1) & UARTSR1_TC))
1038 barrier();
1039
1040 writeb(old_cr2, sport->port.membase + UARTCR2);
1041 }
1042
1043 /*
1044 * if the port was already initialised (eg, by a boot loader),
1045 * try to determine the current setup.
1046 */
1047 static void __init
1048 lpuart_console_get_options(struct lpuart_port *sport, int *baud,
1049 int *parity, int *bits)
1050 {
1051 unsigned char cr, bdh, bdl, brfa;
1052 unsigned int sbr, uartclk, baud_raw;
1053
1054 cr = readb(sport->port.membase + UARTCR2);
1055 cr &= UARTCR2_TE | UARTCR2_RE;
1056 if (!cr)
1057 return;
1058
1059 /* ok, the port was enabled */
1060
1061 cr = readb(sport->port.membase + UARTCR1);
1062
1063 *parity = 'n';
1064 if (cr & UARTCR1_PE) {
1065 if (cr & UARTCR1_PT)
1066 *parity = 'o';
1067 else
1068 *parity = 'e';
1069 }
1070
1071 if (cr & UARTCR1_M)
1072 *bits = 9;
1073 else
1074 *bits = 8;
1075
1076 bdh = readb(sport->port.membase + UARTBDH);
1077 bdh &= UARTBDH_SBR_MASK;
1078 bdl = readb(sport->port.membase + UARTBDL);
1079 sbr = bdh;
1080 sbr <<= 8;
1081 sbr |= bdl;
1082 brfa = readb(sport->port.membase + UARTCR4);
1083 brfa &= UARTCR4_BRFA_MASK;
1084
1085 uartclk = clk_get_rate(sport->clk);
1086 /*
1087 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
1088 */
1089 baud_raw = uartclk / (16 * (sbr + brfa / 32));
1090
1091 if (*baud != baud_raw)
1092 printk(KERN_INFO "Serial: Console lpuart rounded baud rate"
1093 "from %d to %d\n", baud_raw, *baud);
1094 }
1095
1096 static int __init lpuart_console_setup(struct console *co, char *options)
1097 {
1098 struct lpuart_port *sport;
1099 int baud = 115200;
1100 int bits = 8;
1101 int parity = 'n';
1102 int flow = 'n';
1103
1104 /*
1105 * check whether an invalid uart number has been specified, and
1106 * if so, search for the first available port that does have
1107 * console support.
1108 */
1109 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
1110 co->index = 0;
1111
1112 sport = lpuart_ports[co->index];
1113 if (sport == NULL)
1114 return -ENODEV;
1115
1116 if (options)
1117 uart_parse_options(options, &baud, &parity, &bits, &flow);
1118 else
1119 lpuart_console_get_options(sport, &baud, &parity, &bits);
1120
1121 lpuart_setup_watermark(sport);
1122
1123 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
1124 }
1125
1126 static struct uart_driver lpuart_reg;
1127 static struct console lpuart_console = {
1128 .name = DEV_NAME,
1129 .write = lpuart_console_write,
1130 .device = uart_console_device,
1131 .setup = lpuart_console_setup,
1132 .flags = CON_PRINTBUFFER,
1133 .index = -1,
1134 .data = &lpuart_reg,
1135 };
1136
1137 #define LPUART_CONSOLE (&lpuart_console)
1138 #else
1139 #define LPUART_CONSOLE NULL
1140 #endif
1141
1142 static struct uart_driver lpuart_reg = {
1143 .owner = THIS_MODULE,
1144 .driver_name = DRIVER_NAME,
1145 .dev_name = DEV_NAME,
1146 .nr = ARRAY_SIZE(lpuart_ports),
1147 .cons = LPUART_CONSOLE,
1148 };
1149
1150 static int lpuart_probe(struct platform_device *pdev)
1151 {
1152 struct device_node *np = pdev->dev.of_node;
1153 struct lpuart_port *sport;
1154 struct resource *res;
1155 int ret;
1156
1157 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1158 if (!sport)
1159 return -ENOMEM;
1160
1161 pdev->dev.coherent_dma_mask = 0;
1162
1163 ret = of_alias_get_id(np, "serial");
1164 if (ret < 0) {
1165 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1166 return ret;
1167 }
1168 sport->port.line = ret;
1169
1170 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1171 if (!res)
1172 return -ENODEV;
1173
1174 sport->port.mapbase = res->start;
1175 sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
1176 if (IS_ERR(sport->port.membase))
1177 return PTR_ERR(sport->port.membase);
1178
1179 sport->port.dev = &pdev->dev;
1180 sport->port.type = PORT_LPUART;
1181 sport->port.iotype = UPIO_MEM;
1182 sport->port.irq = platform_get_irq(pdev, 0);
1183 sport->port.ops = &lpuart_pops;
1184 sport->port.flags = UPF_BOOT_AUTOCONF;
1185
1186 sport->clk = devm_clk_get(&pdev->dev, "ipg");
1187 if (IS_ERR(sport->clk)) {
1188 ret = PTR_ERR(sport->clk);
1189 dev_err(&pdev->dev, "failed to get uart clk: %d\n", ret);
1190 return ret;
1191 }
1192
1193 ret = clk_prepare_enable(sport->clk);
1194 if (ret) {
1195 dev_err(&pdev->dev, "failed to enable uart clk: %d\n", ret);
1196 return ret;
1197 }
1198
1199 sport->port.uartclk = clk_get_rate(sport->clk);
1200
1201 lpuart_ports[sport->port.line] = sport;
1202
1203 platform_set_drvdata(pdev, &sport->port);
1204
1205 ret = uart_add_one_port(&lpuart_reg, &sport->port);
1206 if (ret) {
1207 clk_disable_unprepare(sport->clk);
1208 return ret;
1209 }
1210
1211 return 0;
1212 }
1213
1214 static int lpuart_remove(struct platform_device *pdev)
1215 {
1216 struct lpuart_port *sport = platform_get_drvdata(pdev);
1217
1218 uart_remove_one_port(&lpuart_reg, &sport->port);
1219
1220 clk_disable_unprepare(sport->clk);
1221
1222 return 0;
1223 }
1224
1225 #ifdef CONFIG_PM_SLEEP
1226 static int lpuart_suspend(struct device *dev)
1227 {
1228 struct lpuart_port *sport = dev_get_drvdata(dev);
1229
1230 uart_suspend_port(&lpuart_reg, &sport->port);
1231
1232 return 0;
1233 }
1234
1235 static int lpuart_resume(struct device *dev)
1236 {
1237 struct lpuart_port *sport = dev_get_drvdata(dev);
1238
1239 uart_resume_port(&lpuart_reg, &sport->port);
1240
1241 return 0;
1242 }
1243 #endif
1244
1245 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
1246
1247 static struct platform_driver lpuart_driver = {
1248 .probe = lpuart_probe,
1249 .remove = lpuart_remove,
1250 .driver = {
1251 .name = "fsl-lpuart",
1252 .owner = THIS_MODULE,
1253 .of_match_table = lpuart_dt_ids,
1254 .pm = &lpuart_pm_ops,
1255 },
1256 };
1257
1258 static int __init lpuart_serial_init(void)
1259 {
1260 int ret;
1261
1262 pr_info("serial: Freescale lpuart driver\n");
1263
1264 ret = uart_register_driver(&lpuart_reg);
1265 if (ret)
1266 return ret;
1267
1268 ret = platform_driver_register(&lpuart_driver);
1269 if (ret)
1270 uart_unregister_driver(&lpuart_reg);
1271
1272 return ret;
1273 }
1274
1275 static void __exit lpuart_serial_exit(void)
1276 {
1277 platform_driver_unregister(&lpuart_driver);
1278 uart_unregister_driver(&lpuart_reg);
1279 }
1280
1281 module_init(lpuart_serial_init);
1282 module_exit(lpuart_serial_exit);
1283
1284 MODULE_DESCRIPTION("Freescale lpuart serial port driver");
1285 MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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