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Merge tag 'for-linus-4.4-rc2-tag' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / drivers / tty / serial / imx.c
1 /*
2 * Driver for Motorola/Freescale IMX serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21 #define SUPPORT_SYSRQ
22 #endif
23
24 #include <linux/module.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/platform_device.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial_core.h>
33 #include <linux/serial.h>
34 #include <linux/clk.h>
35 #include <linux/delay.h>
36 #include <linux/rational.h>
37 #include <linux/slab.h>
38 #include <linux/of.h>
39 #include <linux/of_device.h>
40 #include <linux/io.h>
41 #include <linux/dma-mapping.h>
42
43 #include <asm/irq.h>
44 #include <linux/platform_data/serial-imx.h>
45 #include <linux/platform_data/dma-imx.h>
46
47 /* Register definitions */
48 #define URXD0 0x0 /* Receiver Register */
49 #define URTX0 0x40 /* Transmitter Register */
50 #define UCR1 0x80 /* Control Register 1 */
51 #define UCR2 0x84 /* Control Register 2 */
52 #define UCR3 0x88 /* Control Register 3 */
53 #define UCR4 0x8c /* Control Register 4 */
54 #define UFCR 0x90 /* FIFO Control Register */
55 #define USR1 0x94 /* Status Register 1 */
56 #define USR2 0x98 /* Status Register 2 */
57 #define UESC 0x9c /* Escape Character Register */
58 #define UTIM 0xa0 /* Escape Timer Register */
59 #define UBIR 0xa4 /* BRM Incremental Register */
60 #define UBMR 0xa8 /* BRM Modulator Register */
61 #define UBRC 0xac /* Baud Rate Count Register */
62 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
63 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
64 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
65
66 /* UART Control Register Bit Fields.*/
67 #define URXD_DUMMY_READ (1<<16)
68 #define URXD_CHARRDY (1<<15)
69 #define URXD_ERR (1<<14)
70 #define URXD_OVRRUN (1<<13)
71 #define URXD_FRMERR (1<<12)
72 #define URXD_BRK (1<<11)
73 #define URXD_PRERR (1<<10)
74 #define URXD_RX_DATA (0xFF<<0)
75 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
76 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
77 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
78 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
79 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
80 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
81 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
82 #define UCR1_IREN (1<<7) /* Infrared interface enable */
83 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
84 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
85 #define UCR1_SNDBRK (1<<4) /* Send break */
86 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
87 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
88 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
89 #define UCR1_DOZE (1<<1) /* Doze */
90 #define UCR1_UARTEN (1<<0) /* UART enabled */
91 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
92 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
93 #define UCR2_CTSC (1<<13) /* CTS pin control */
94 #define UCR2_CTS (1<<12) /* Clear to send */
95 #define UCR2_ESCEN (1<<11) /* Escape enable */
96 #define UCR2_PREN (1<<8) /* Parity enable */
97 #define UCR2_PROE (1<<7) /* Parity odd/even */
98 #define UCR2_STPB (1<<6) /* Stop */
99 #define UCR2_WS (1<<5) /* Word size */
100 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
101 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
102 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
103 #define UCR2_RXEN (1<<1) /* Receiver enabled */
104 #define UCR2_SRST (1<<0) /* SW reset */
105 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
106 #define UCR3_PARERREN (1<<12) /* Parity enable */
107 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
108 #define UCR3_DSR (1<<10) /* Data set ready */
109 #define UCR3_DCD (1<<9) /* Data carrier detect */
110 #define UCR3_RI (1<<8) /* Ring indicator */
111 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
112 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
113 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
114 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
115 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
116 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
117 #define UCR3_BPEN (1<<0) /* Preset registers enable */
118 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
119 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
120 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
121 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
122 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
123 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
124 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
125 #define UCR4_IRSC (1<<5) /* IR special case */
126 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
127 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
128 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
129 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
130 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
131 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
132 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
133 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
134 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
135 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
136 #define USR1_RTSS (1<<14) /* RTS pin status */
137 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
138 #define USR1_RTSD (1<<12) /* RTS delta */
139 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
140 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
141 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
142 #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
143 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
144 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
145 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
146 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
147 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
148 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
149 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
150 #define USR2_IDLE (1<<12) /* Idle condition */
151 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
152 #define USR2_WAKE (1<<7) /* Wake */
153 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
154 #define USR2_TXDC (1<<3) /* Transmitter complete */
155 #define USR2_BRCD (1<<2) /* Break condition */
156 #define USR2_ORE (1<<1) /* Overrun error */
157 #define USR2_RDR (1<<0) /* Recv data ready */
158 #define UTS_FRCPERR (1<<13) /* Force parity error */
159 #define UTS_LOOP (1<<12) /* Loop tx and rx */
160 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
161 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
162 #define UTS_TXFULL (1<<4) /* TxFIFO full */
163 #define UTS_RXFULL (1<<3) /* RxFIFO full */
164 #define UTS_SOFTRST (1<<0) /* Software reset */
165
166 /* We've been assigned a range on the "Low-density serial ports" major */
167 #define SERIAL_IMX_MAJOR 207
168 #define MINOR_START 16
169 #define DEV_NAME "ttymxc"
170
171 /*
172 * This determines how often we check the modem status signals
173 * for any change. They generally aren't connected to an IRQ
174 * so we have to poll them. We also check immediately before
175 * filling the TX fifo incase CTS has been dropped.
176 */
177 #define MCTRL_TIMEOUT (250*HZ/1000)
178
179 #define DRIVER_NAME "IMX-uart"
180
181 #define UART_NR 8
182
183 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
184 enum imx_uart_type {
185 IMX1_UART,
186 IMX21_UART,
187 IMX6Q_UART,
188 };
189
190 /* device type dependent stuff */
191 struct imx_uart_data {
192 unsigned uts_reg;
193 enum imx_uart_type devtype;
194 };
195
196 struct imx_port {
197 struct uart_port port;
198 struct timer_list timer;
199 unsigned int old_status;
200 unsigned int have_rtscts:1;
201 unsigned int dte_mode:1;
202 unsigned int irda_inv_rx:1;
203 unsigned int irda_inv_tx:1;
204 unsigned short trcv_delay; /* transceiver delay */
205 struct clk *clk_ipg;
206 struct clk *clk_per;
207 const struct imx_uart_data *devdata;
208
209 /* DMA fields */
210 unsigned int dma_is_inited:1;
211 unsigned int dma_is_enabled:1;
212 unsigned int dma_is_rxing:1;
213 unsigned int dma_is_txing:1;
214 struct dma_chan *dma_chan_rx, *dma_chan_tx;
215 struct scatterlist rx_sgl, tx_sgl[2];
216 void *rx_buf;
217 unsigned int tx_bytes;
218 unsigned int dma_tx_nents;
219 wait_queue_head_t dma_wait;
220 unsigned int saved_reg[10];
221 bool context_saved;
222 };
223
224 struct imx_port_ucrs {
225 unsigned int ucr1;
226 unsigned int ucr2;
227 unsigned int ucr3;
228 };
229
230 static struct imx_uart_data imx_uart_devdata[] = {
231 [IMX1_UART] = {
232 .uts_reg = IMX1_UTS,
233 .devtype = IMX1_UART,
234 },
235 [IMX21_UART] = {
236 .uts_reg = IMX21_UTS,
237 .devtype = IMX21_UART,
238 },
239 [IMX6Q_UART] = {
240 .uts_reg = IMX21_UTS,
241 .devtype = IMX6Q_UART,
242 },
243 };
244
245 static const struct platform_device_id imx_uart_devtype[] = {
246 {
247 .name = "imx1-uart",
248 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
249 }, {
250 .name = "imx21-uart",
251 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
252 }, {
253 .name = "imx6q-uart",
254 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
255 }, {
256 /* sentinel */
257 }
258 };
259 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
260
261 static const struct of_device_id imx_uart_dt_ids[] = {
262 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
263 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
264 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
265 { /* sentinel */ }
266 };
267 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
268
269 static inline unsigned uts_reg(struct imx_port *sport)
270 {
271 return sport->devdata->uts_reg;
272 }
273
274 static inline int is_imx1_uart(struct imx_port *sport)
275 {
276 return sport->devdata->devtype == IMX1_UART;
277 }
278
279 static inline int is_imx21_uart(struct imx_port *sport)
280 {
281 return sport->devdata->devtype == IMX21_UART;
282 }
283
284 static inline int is_imx6q_uart(struct imx_port *sport)
285 {
286 return sport->devdata->devtype == IMX6Q_UART;
287 }
288 /*
289 * Save and restore functions for UCR1, UCR2 and UCR3 registers
290 */
291 #if defined(CONFIG_SERIAL_IMX_CONSOLE)
292 static void imx_port_ucrs_save(struct uart_port *port,
293 struct imx_port_ucrs *ucr)
294 {
295 /* save control registers */
296 ucr->ucr1 = readl(port->membase + UCR1);
297 ucr->ucr2 = readl(port->membase + UCR2);
298 ucr->ucr3 = readl(port->membase + UCR3);
299 }
300
301 static void imx_port_ucrs_restore(struct uart_port *port,
302 struct imx_port_ucrs *ucr)
303 {
304 /* restore control registers */
305 writel(ucr->ucr1, port->membase + UCR1);
306 writel(ucr->ucr2, port->membase + UCR2);
307 writel(ucr->ucr3, port->membase + UCR3);
308 }
309 #endif
310
311 /*
312 * Handle any change of modem status signal since we were last called.
313 */
314 static void imx_mctrl_check(struct imx_port *sport)
315 {
316 unsigned int status, changed;
317
318 status = sport->port.ops->get_mctrl(&sport->port);
319 changed = status ^ sport->old_status;
320
321 if (changed == 0)
322 return;
323
324 sport->old_status = status;
325
326 if (changed & TIOCM_RI)
327 sport->port.icount.rng++;
328 if (changed & TIOCM_DSR)
329 sport->port.icount.dsr++;
330 if (changed & TIOCM_CAR)
331 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
332 if (changed & TIOCM_CTS)
333 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
334
335 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
336 }
337
338 /*
339 * This is our per-port timeout handler, for checking the
340 * modem status signals.
341 */
342 static void imx_timeout(unsigned long data)
343 {
344 struct imx_port *sport = (struct imx_port *)data;
345 unsigned long flags;
346
347 if (sport->port.state) {
348 spin_lock_irqsave(&sport->port.lock, flags);
349 imx_mctrl_check(sport);
350 spin_unlock_irqrestore(&sport->port.lock, flags);
351
352 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
353 }
354 }
355
356 /*
357 * interrupts disabled on entry
358 */
359 static void imx_stop_tx(struct uart_port *port)
360 {
361 struct imx_port *sport = (struct imx_port *)port;
362 unsigned long temp;
363
364 /*
365 * We are maybe in the SMP context, so if the DMA TX thread is running
366 * on other cpu, we have to wait for it to finish.
367 */
368 if (sport->dma_is_enabled && sport->dma_is_txing)
369 return;
370
371 temp = readl(port->membase + UCR1);
372 writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1);
373
374 /* in rs485 mode disable transmitter if shifter is empty */
375 if (port->rs485.flags & SER_RS485_ENABLED &&
376 readl(port->membase + USR2) & USR2_TXDC) {
377 temp = readl(port->membase + UCR2);
378 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
379 temp &= ~UCR2_CTS;
380 else
381 temp |= UCR2_CTS;
382 writel(temp, port->membase + UCR2);
383
384 temp = readl(port->membase + UCR4);
385 temp &= ~UCR4_TCEN;
386 writel(temp, port->membase + UCR4);
387 }
388 }
389
390 /*
391 * interrupts disabled on entry
392 */
393 static void imx_stop_rx(struct uart_port *port)
394 {
395 struct imx_port *sport = (struct imx_port *)port;
396 unsigned long temp;
397
398 if (sport->dma_is_enabled && sport->dma_is_rxing) {
399 if (sport->port.suspended) {
400 dmaengine_terminate_all(sport->dma_chan_rx);
401 sport->dma_is_rxing = 0;
402 } else {
403 return;
404 }
405 }
406
407 temp = readl(sport->port.membase + UCR2);
408 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
409
410 /* disable the `Receiver Ready Interrrupt` */
411 temp = readl(sport->port.membase + UCR1);
412 writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);
413 }
414
415 /*
416 * Set the modem control timer to fire immediately.
417 */
418 static void imx_enable_ms(struct uart_port *port)
419 {
420 struct imx_port *sport = (struct imx_port *)port;
421
422 mod_timer(&sport->timer, jiffies);
423 }
424
425 static void imx_dma_tx(struct imx_port *sport);
426 static inline void imx_transmit_buffer(struct imx_port *sport)
427 {
428 struct circ_buf *xmit = &sport->port.state->xmit;
429 unsigned long temp;
430
431 if (sport->port.x_char) {
432 /* Send next char */
433 writel(sport->port.x_char, sport->port.membase + URTX0);
434 sport->port.icount.tx++;
435 sport->port.x_char = 0;
436 return;
437 }
438
439 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
440 imx_stop_tx(&sport->port);
441 return;
442 }
443
444 if (sport->dma_is_enabled) {
445 /*
446 * We've just sent a X-char Ensure the TX DMA is enabled
447 * and the TX IRQ is disabled.
448 **/
449 temp = readl(sport->port.membase + UCR1);
450 temp &= ~UCR1_TXMPTYEN;
451 if (sport->dma_is_txing) {
452 temp |= UCR1_TDMAEN;
453 writel(temp, sport->port.membase + UCR1);
454 } else {
455 writel(temp, sport->port.membase + UCR1);
456 imx_dma_tx(sport);
457 }
458 }
459
460 while (!uart_circ_empty(xmit) &&
461 !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) {
462 /* send xmit->buf[xmit->tail]
463 * out the port here */
464 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
465 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
466 sport->port.icount.tx++;
467 }
468
469 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
470 uart_write_wakeup(&sport->port);
471
472 if (uart_circ_empty(xmit))
473 imx_stop_tx(&sport->port);
474 }
475
476 static void dma_tx_callback(void *data)
477 {
478 struct imx_port *sport = data;
479 struct scatterlist *sgl = &sport->tx_sgl[0];
480 struct circ_buf *xmit = &sport->port.state->xmit;
481 unsigned long flags;
482 unsigned long temp;
483
484 spin_lock_irqsave(&sport->port.lock, flags);
485
486 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
487
488 temp = readl(sport->port.membase + UCR1);
489 temp &= ~UCR1_TDMAEN;
490 writel(temp, sport->port.membase + UCR1);
491
492 /* update the stat */
493 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
494 sport->port.icount.tx += sport->tx_bytes;
495
496 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
497
498 sport->dma_is_txing = 0;
499
500 spin_unlock_irqrestore(&sport->port.lock, flags);
501
502 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
503 uart_write_wakeup(&sport->port);
504
505 if (waitqueue_active(&sport->dma_wait)) {
506 wake_up(&sport->dma_wait);
507 dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
508 return;
509 }
510
511 spin_lock_irqsave(&sport->port.lock, flags);
512 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
513 imx_dma_tx(sport);
514 spin_unlock_irqrestore(&sport->port.lock, flags);
515 }
516
517 static void imx_dma_tx(struct imx_port *sport)
518 {
519 struct circ_buf *xmit = &sport->port.state->xmit;
520 struct scatterlist *sgl = sport->tx_sgl;
521 struct dma_async_tx_descriptor *desc;
522 struct dma_chan *chan = sport->dma_chan_tx;
523 struct device *dev = sport->port.dev;
524 unsigned long temp;
525 int ret;
526
527 if (sport->dma_is_txing)
528 return;
529
530 sport->tx_bytes = uart_circ_chars_pending(xmit);
531
532 if (xmit->tail < xmit->head) {
533 sport->dma_tx_nents = 1;
534 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
535 } else {
536 sport->dma_tx_nents = 2;
537 sg_init_table(sgl, 2);
538 sg_set_buf(sgl, xmit->buf + xmit->tail,
539 UART_XMIT_SIZE - xmit->tail);
540 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
541 }
542
543 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
544 if (ret == 0) {
545 dev_err(dev, "DMA mapping error for TX.\n");
546 return;
547 }
548 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
549 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
550 if (!desc) {
551 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
552 DMA_TO_DEVICE);
553 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
554 return;
555 }
556 desc->callback = dma_tx_callback;
557 desc->callback_param = sport;
558
559 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
560 uart_circ_chars_pending(xmit));
561
562 temp = readl(sport->port.membase + UCR1);
563 temp |= UCR1_TDMAEN;
564 writel(temp, sport->port.membase + UCR1);
565
566 /* fire it */
567 sport->dma_is_txing = 1;
568 dmaengine_submit(desc);
569 dma_async_issue_pending(chan);
570 return;
571 }
572
573 /*
574 * interrupts disabled on entry
575 */
576 static void imx_start_tx(struct uart_port *port)
577 {
578 struct imx_port *sport = (struct imx_port *)port;
579 unsigned long temp;
580
581 if (port->rs485.flags & SER_RS485_ENABLED) {
582 /* enable transmitter and shifter empty irq */
583 temp = readl(port->membase + UCR2);
584 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
585 temp &= ~UCR2_CTS;
586 else
587 temp |= UCR2_CTS;
588 writel(temp, port->membase + UCR2);
589
590 temp = readl(port->membase + UCR4);
591 temp |= UCR4_TCEN;
592 writel(temp, port->membase + UCR4);
593 }
594
595 if (!sport->dma_is_enabled) {
596 temp = readl(sport->port.membase + UCR1);
597 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
598 }
599
600 if (sport->dma_is_enabled) {
601 if (sport->port.x_char) {
602 /* We have X-char to send, so enable TX IRQ and
603 * disable TX DMA to let TX interrupt to send X-char */
604 temp = readl(sport->port.membase + UCR1);
605 temp &= ~UCR1_TDMAEN;
606 temp |= UCR1_TXMPTYEN;
607 writel(temp, sport->port.membase + UCR1);
608 return;
609 }
610
611 if (!uart_circ_empty(&port->state->xmit) &&
612 !uart_tx_stopped(port))
613 imx_dma_tx(sport);
614 return;
615 }
616 }
617
618 static irqreturn_t imx_rtsint(int irq, void *dev_id)
619 {
620 struct imx_port *sport = dev_id;
621 unsigned int val;
622 unsigned long flags;
623
624 spin_lock_irqsave(&sport->port.lock, flags);
625
626 writel(USR1_RTSD, sport->port.membase + USR1);
627 val = readl(sport->port.membase + USR1) & USR1_RTSS;
628 uart_handle_cts_change(&sport->port, !!val);
629 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
630
631 spin_unlock_irqrestore(&sport->port.lock, flags);
632 return IRQ_HANDLED;
633 }
634
635 static irqreturn_t imx_txint(int irq, void *dev_id)
636 {
637 struct imx_port *sport = dev_id;
638 unsigned long flags;
639
640 spin_lock_irqsave(&sport->port.lock, flags);
641 imx_transmit_buffer(sport);
642 spin_unlock_irqrestore(&sport->port.lock, flags);
643 return IRQ_HANDLED;
644 }
645
646 static irqreturn_t imx_rxint(int irq, void *dev_id)
647 {
648 struct imx_port *sport = dev_id;
649 unsigned int rx, flg, ignored = 0;
650 struct tty_port *port = &sport->port.state->port;
651 unsigned long flags, temp;
652
653 spin_lock_irqsave(&sport->port.lock, flags);
654
655 while (readl(sport->port.membase + USR2) & USR2_RDR) {
656 flg = TTY_NORMAL;
657 sport->port.icount.rx++;
658
659 rx = readl(sport->port.membase + URXD0);
660
661 temp = readl(sport->port.membase + USR2);
662 if (temp & USR2_BRCD) {
663 writel(USR2_BRCD, sport->port.membase + USR2);
664 if (uart_handle_break(&sport->port))
665 continue;
666 }
667
668 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
669 continue;
670
671 if (unlikely(rx & URXD_ERR)) {
672 if (rx & URXD_BRK)
673 sport->port.icount.brk++;
674 else if (rx & URXD_PRERR)
675 sport->port.icount.parity++;
676 else if (rx & URXD_FRMERR)
677 sport->port.icount.frame++;
678 if (rx & URXD_OVRRUN)
679 sport->port.icount.overrun++;
680
681 if (rx & sport->port.ignore_status_mask) {
682 if (++ignored > 100)
683 goto out;
684 continue;
685 }
686
687 rx &= (sport->port.read_status_mask | 0xFF);
688
689 if (rx & URXD_BRK)
690 flg = TTY_BREAK;
691 else if (rx & URXD_PRERR)
692 flg = TTY_PARITY;
693 else if (rx & URXD_FRMERR)
694 flg = TTY_FRAME;
695 if (rx & URXD_OVRRUN)
696 flg = TTY_OVERRUN;
697
698 #ifdef SUPPORT_SYSRQ
699 sport->port.sysrq = 0;
700 #endif
701 }
702
703 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
704 goto out;
705
706 if (tty_insert_flip_char(port, rx, flg) == 0)
707 sport->port.icount.buf_overrun++;
708 }
709
710 out:
711 spin_unlock_irqrestore(&sport->port.lock, flags);
712 tty_flip_buffer_push(port);
713 return IRQ_HANDLED;
714 }
715
716 static int start_rx_dma(struct imx_port *sport);
717 /*
718 * If the RXFIFO is filled with some data, and then we
719 * arise a DMA operation to receive them.
720 */
721 static void imx_dma_rxint(struct imx_port *sport)
722 {
723 unsigned long temp;
724 unsigned long flags;
725
726 spin_lock_irqsave(&sport->port.lock, flags);
727
728 temp = readl(sport->port.membase + USR2);
729 if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
730 sport->dma_is_rxing = 1;
731
732 /* disable the receiver ready and aging timer interrupts */
733 temp = readl(sport->port.membase + UCR1);
734 temp &= ~(UCR1_RRDYEN);
735 writel(temp, sport->port.membase + UCR1);
736
737 temp = readl(sport->port.membase + UCR2);
738 temp &= ~(UCR2_ATEN);
739 writel(temp, sport->port.membase + UCR2);
740
741 /* tell the DMA to receive the data. */
742 start_rx_dma(sport);
743 }
744
745 spin_unlock_irqrestore(&sport->port.lock, flags);
746 }
747
748 static irqreturn_t imx_int(int irq, void *dev_id)
749 {
750 struct imx_port *sport = dev_id;
751 unsigned int sts;
752 unsigned int sts2;
753
754 sts = readl(sport->port.membase + USR1);
755 sts2 = readl(sport->port.membase + USR2);
756
757 if (sts & (USR1_RRDY | USR1_AGTIM)) {
758 if (sport->dma_is_enabled)
759 imx_dma_rxint(sport);
760 else
761 imx_rxint(irq, dev_id);
762 }
763
764 if ((sts & USR1_TRDY &&
765 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) ||
766 (sts2 & USR2_TXDC &&
767 readl(sport->port.membase + UCR4) & UCR4_TCEN))
768 imx_txint(irq, dev_id);
769
770 if (sts & USR1_RTSD)
771 imx_rtsint(irq, dev_id);
772
773 if (sts & USR1_AWAKE)
774 writel(USR1_AWAKE, sport->port.membase + USR1);
775
776 if (sts2 & USR2_ORE) {
777 sport->port.icount.overrun++;
778 writel(USR2_ORE, sport->port.membase + USR2);
779 }
780
781 return IRQ_HANDLED;
782 }
783
784 /*
785 * Return TIOCSER_TEMT when transmitter is not busy.
786 */
787 static unsigned int imx_tx_empty(struct uart_port *port)
788 {
789 struct imx_port *sport = (struct imx_port *)port;
790 unsigned int ret;
791
792 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
793
794 /* If the TX DMA is working, return 0. */
795 if (sport->dma_is_enabled && sport->dma_is_txing)
796 ret = 0;
797
798 return ret;
799 }
800
801 /*
802 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
803 */
804 static unsigned int imx_get_mctrl(struct uart_port *port)
805 {
806 struct imx_port *sport = (struct imx_port *)port;
807 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
808
809 if (readl(sport->port.membase + USR1) & USR1_RTSS)
810 tmp |= TIOCM_CTS;
811
812 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
813 tmp |= TIOCM_RTS;
814
815 if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP)
816 tmp |= TIOCM_LOOP;
817
818 return tmp;
819 }
820
821 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
822 {
823 struct imx_port *sport = (struct imx_port *)port;
824 unsigned long temp;
825
826 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
827 temp = readl(sport->port.membase + UCR2);
828 temp &= ~(UCR2_CTS | UCR2_CTSC);
829 if (mctrl & TIOCM_RTS)
830 temp |= UCR2_CTS | UCR2_CTSC;
831 writel(temp, sport->port.membase + UCR2);
832 }
833
834 temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
835 if (mctrl & TIOCM_LOOP)
836 temp |= UTS_LOOP;
837 writel(temp, sport->port.membase + uts_reg(sport));
838 }
839
840 /*
841 * Interrupts always disabled.
842 */
843 static void imx_break_ctl(struct uart_port *port, int break_state)
844 {
845 struct imx_port *sport = (struct imx_port *)port;
846 unsigned long flags, temp;
847
848 spin_lock_irqsave(&sport->port.lock, flags);
849
850 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
851
852 if (break_state != 0)
853 temp |= UCR1_SNDBRK;
854
855 writel(temp, sport->port.membase + UCR1);
856
857 spin_unlock_irqrestore(&sport->port.lock, flags);
858 }
859
860 #define RX_BUF_SIZE (PAGE_SIZE)
861 static void imx_rx_dma_done(struct imx_port *sport)
862 {
863 unsigned long temp;
864 unsigned long flags;
865
866 spin_lock_irqsave(&sport->port.lock, flags);
867
868 /* re-enable interrupts to get notified when new symbols are incoming */
869 temp = readl(sport->port.membase + UCR1);
870 temp |= UCR1_RRDYEN;
871 writel(temp, sport->port.membase + UCR1);
872
873 temp = readl(sport->port.membase + UCR2);
874 temp |= UCR2_ATEN;
875 writel(temp, sport->port.membase + UCR2);
876
877 sport->dma_is_rxing = 0;
878
879 /* Is the shutdown waiting for us? */
880 if (waitqueue_active(&sport->dma_wait))
881 wake_up(&sport->dma_wait);
882
883 spin_unlock_irqrestore(&sport->port.lock, flags);
884 }
885
886 /*
887 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
888 * [1] the RX DMA buffer is full.
889 * [2] the aging timer expires
890 *
891 * Condition [2] is triggered when a character has been sitting in the FIFO
892 * for at least 8 byte durations.
893 */
894 static void dma_rx_callback(void *data)
895 {
896 struct imx_port *sport = data;
897 struct dma_chan *chan = sport->dma_chan_rx;
898 struct scatterlist *sgl = &sport->rx_sgl;
899 struct tty_port *port = &sport->port.state->port;
900 struct dma_tx_state state;
901 enum dma_status status;
902 unsigned int count;
903
904 /* unmap it first */
905 dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE);
906
907 status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
908 count = RX_BUF_SIZE - state.residue;
909
910 dev_dbg(sport->port.dev, "We get %d bytes.\n", count);
911
912 if (count) {
913 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
914 int bytes = tty_insert_flip_string(port, sport->rx_buf,
915 count);
916
917 if (bytes != count)
918 sport->port.icount.buf_overrun++;
919 }
920 tty_flip_buffer_push(port);
921 sport->port.icount.rx += count;
922 }
923
924 /*
925 * Restart RX DMA directly if more data is available in order to skip
926 * the roundtrip through the IRQ handler. If there is some data already
927 * in the FIFO, DMA needs to be restarted soon anyways.
928 *
929 * Otherwise stop the DMA and reactivate FIFO IRQs to restart DMA once
930 * data starts to arrive again.
931 */
932 if (readl(sport->port.membase + USR2) & USR2_RDR)
933 start_rx_dma(sport);
934 else
935 imx_rx_dma_done(sport);
936 }
937
938 static int start_rx_dma(struct imx_port *sport)
939 {
940 struct scatterlist *sgl = &sport->rx_sgl;
941 struct dma_chan *chan = sport->dma_chan_rx;
942 struct device *dev = sport->port.dev;
943 struct dma_async_tx_descriptor *desc;
944 int ret;
945
946 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
947 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
948 if (ret == 0) {
949 dev_err(dev, "DMA mapping error for RX.\n");
950 return -EINVAL;
951 }
952 desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM,
953 DMA_PREP_INTERRUPT);
954 if (!desc) {
955 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
956 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
957 return -EINVAL;
958 }
959 desc->callback = dma_rx_callback;
960 desc->callback_param = sport;
961
962 dev_dbg(dev, "RX: prepare for the DMA.\n");
963 dmaengine_submit(desc);
964 dma_async_issue_pending(chan);
965 return 0;
966 }
967
968 #define TXTL_DEFAULT 2 /* reset default */
969 #define RXTL_DEFAULT 1 /* reset default */
970 #define TXTL_DMA 8 /* DMA burst setting */
971 #define RXTL_DMA 9 /* DMA burst setting */
972
973 static void imx_setup_ufcr(struct imx_port *sport,
974 unsigned char txwl, unsigned char rxwl)
975 {
976 unsigned int val;
977
978 /* set receiver / transmitter trigger level */
979 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
980 val |= txwl << UFCR_TXTL_SHF | rxwl;
981 writel(val, sport->port.membase + UFCR);
982 }
983
984 static void imx_uart_dma_exit(struct imx_port *sport)
985 {
986 if (sport->dma_chan_rx) {
987 dma_release_channel(sport->dma_chan_rx);
988 sport->dma_chan_rx = NULL;
989
990 kfree(sport->rx_buf);
991 sport->rx_buf = NULL;
992 }
993
994 if (sport->dma_chan_tx) {
995 dma_release_channel(sport->dma_chan_tx);
996 sport->dma_chan_tx = NULL;
997 }
998
999 sport->dma_is_inited = 0;
1000 }
1001
1002 static int imx_uart_dma_init(struct imx_port *sport)
1003 {
1004 struct dma_slave_config slave_config = {};
1005 struct device *dev = sport->port.dev;
1006 int ret;
1007
1008 /* Prepare for RX : */
1009 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1010 if (!sport->dma_chan_rx) {
1011 dev_dbg(dev, "cannot get the DMA channel.\n");
1012 ret = -EINVAL;
1013 goto err;
1014 }
1015
1016 slave_config.direction = DMA_DEV_TO_MEM;
1017 slave_config.src_addr = sport->port.mapbase + URXD0;
1018 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1019 /* one byte less than the watermark level to enable the aging timer */
1020 slave_config.src_maxburst = RXTL_DMA - 1;
1021 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1022 if (ret) {
1023 dev_err(dev, "error in RX dma configuration.\n");
1024 goto err;
1025 }
1026
1027 sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
1028 if (!sport->rx_buf) {
1029 ret = -ENOMEM;
1030 goto err;
1031 }
1032
1033 /* Prepare for TX : */
1034 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1035 if (!sport->dma_chan_tx) {
1036 dev_err(dev, "cannot get the TX DMA channel!\n");
1037 ret = -EINVAL;
1038 goto err;
1039 }
1040
1041 slave_config.direction = DMA_MEM_TO_DEV;
1042 slave_config.dst_addr = sport->port.mapbase + URTX0;
1043 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1044 slave_config.dst_maxburst = TXTL_DMA;
1045 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1046 if (ret) {
1047 dev_err(dev, "error in TX dma configuration.");
1048 goto err;
1049 }
1050
1051 sport->dma_is_inited = 1;
1052
1053 return 0;
1054 err:
1055 imx_uart_dma_exit(sport);
1056 return ret;
1057 }
1058
1059 static void imx_enable_dma(struct imx_port *sport)
1060 {
1061 unsigned long temp;
1062
1063 init_waitqueue_head(&sport->dma_wait);
1064
1065 /* set UCR1 */
1066 temp = readl(sport->port.membase + UCR1);
1067 temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN;
1068 writel(temp, sport->port.membase + UCR1);
1069
1070 temp = readl(sport->port.membase + UCR2);
1071 temp |= UCR2_ATEN;
1072 writel(temp, sport->port.membase + UCR2);
1073
1074 imx_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1075
1076 sport->dma_is_enabled = 1;
1077 }
1078
1079 static void imx_disable_dma(struct imx_port *sport)
1080 {
1081 unsigned long temp;
1082
1083 /* clear UCR1 */
1084 temp = readl(sport->port.membase + UCR1);
1085 temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1086 writel(temp, sport->port.membase + UCR1);
1087
1088 /* clear UCR2 */
1089 temp = readl(sport->port.membase + UCR2);
1090 temp &= ~(UCR2_CTSC | UCR2_CTS | UCR2_ATEN);
1091 writel(temp, sport->port.membase + UCR2);
1092
1093 imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1094
1095 sport->dma_is_enabled = 0;
1096 }
1097
1098 /* half the RX buffer size */
1099 #define CTSTL 16
1100
1101 static int imx_startup(struct uart_port *port)
1102 {
1103 struct imx_port *sport = (struct imx_port *)port;
1104 int retval, i;
1105 unsigned long flags, temp;
1106
1107 retval = clk_prepare_enable(sport->clk_per);
1108 if (retval)
1109 return retval;
1110 retval = clk_prepare_enable(sport->clk_ipg);
1111 if (retval) {
1112 clk_disable_unprepare(sport->clk_per);
1113 return retval;
1114 }
1115
1116 imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1117
1118 /* disable the DREN bit (Data Ready interrupt enable) before
1119 * requesting IRQs
1120 */
1121 temp = readl(sport->port.membase + UCR4);
1122
1123 /* set the trigger level for CTS */
1124 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1125 temp |= CTSTL << UCR4_CTSTL_SHF;
1126
1127 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1128
1129 /* Can we enable the DMA support? */
1130 if (is_imx6q_uart(sport) && !uart_console(port) &&
1131 !sport->dma_is_inited)
1132 imx_uart_dma_init(sport);
1133
1134 spin_lock_irqsave(&sport->port.lock, flags);
1135 /* Reset fifo's and state machines */
1136 i = 100;
1137
1138 temp = readl(sport->port.membase + UCR2);
1139 temp &= ~UCR2_SRST;
1140 writel(temp, sport->port.membase + UCR2);
1141
1142 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1143 udelay(1);
1144
1145 /*
1146 * Finally, clear and enable interrupts
1147 */
1148 writel(USR1_RTSD, sport->port.membase + USR1);
1149 writel(USR2_ORE, sport->port.membase + USR2);
1150
1151 if (sport->dma_is_inited && !sport->dma_is_enabled)
1152 imx_enable_dma(sport);
1153
1154 temp = readl(sport->port.membase + UCR1);
1155 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
1156
1157 writel(temp, sport->port.membase + UCR1);
1158
1159 temp = readl(sport->port.membase + UCR4);
1160 temp |= UCR4_OREN;
1161 writel(temp, sport->port.membase + UCR4);
1162
1163 temp = readl(sport->port.membase + UCR2);
1164 temp |= (UCR2_RXEN | UCR2_TXEN);
1165 if (!sport->have_rtscts)
1166 temp |= UCR2_IRTS;
1167 writel(temp, sport->port.membase + UCR2);
1168
1169 if (!is_imx1_uart(sport)) {
1170 temp = readl(sport->port.membase + UCR3);
1171 temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
1172 writel(temp, sport->port.membase + UCR3);
1173 }
1174
1175 /*
1176 * Enable modem status interrupts
1177 */
1178 imx_enable_ms(&sport->port);
1179 spin_unlock_irqrestore(&sport->port.lock, flags);
1180
1181 return 0;
1182 }
1183
1184 static void imx_shutdown(struct uart_port *port)
1185 {
1186 struct imx_port *sport = (struct imx_port *)port;
1187 unsigned long temp;
1188 unsigned long flags;
1189
1190 if (sport->dma_is_enabled) {
1191 int ret;
1192
1193 /* We have to wait for the DMA to finish. */
1194 ret = wait_event_interruptible(sport->dma_wait,
1195 !sport->dma_is_rxing && !sport->dma_is_txing);
1196 if (ret != 0) {
1197 sport->dma_is_rxing = 0;
1198 sport->dma_is_txing = 0;
1199 dmaengine_terminate_all(sport->dma_chan_tx);
1200 dmaengine_terminate_all(sport->dma_chan_rx);
1201 }
1202 spin_lock_irqsave(&sport->port.lock, flags);
1203 imx_stop_tx(port);
1204 imx_stop_rx(port);
1205 imx_disable_dma(sport);
1206 spin_unlock_irqrestore(&sport->port.lock, flags);
1207 imx_uart_dma_exit(sport);
1208 }
1209
1210 spin_lock_irqsave(&sport->port.lock, flags);
1211 temp = readl(sport->port.membase + UCR2);
1212 temp &= ~(UCR2_TXEN);
1213 writel(temp, sport->port.membase + UCR2);
1214 spin_unlock_irqrestore(&sport->port.lock, flags);
1215
1216 /*
1217 * Stop our timer.
1218 */
1219 del_timer_sync(&sport->timer);
1220
1221 /*
1222 * Disable all interrupts, port and break condition.
1223 */
1224
1225 spin_lock_irqsave(&sport->port.lock, flags);
1226 temp = readl(sport->port.membase + UCR1);
1227 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
1228
1229 writel(temp, sport->port.membase + UCR1);
1230 spin_unlock_irqrestore(&sport->port.lock, flags);
1231
1232 clk_disable_unprepare(sport->clk_per);
1233 clk_disable_unprepare(sport->clk_ipg);
1234 }
1235
1236 static void imx_flush_buffer(struct uart_port *port)
1237 {
1238 struct imx_port *sport = (struct imx_port *)port;
1239 struct scatterlist *sgl = &sport->tx_sgl[0];
1240 unsigned long temp;
1241 int i = 100, ubir, ubmr, uts;
1242
1243 if (!sport->dma_chan_tx)
1244 return;
1245
1246 sport->tx_bytes = 0;
1247 dmaengine_terminate_all(sport->dma_chan_tx);
1248 if (sport->dma_is_txing) {
1249 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1250 DMA_TO_DEVICE);
1251 temp = readl(sport->port.membase + UCR1);
1252 temp &= ~UCR1_TDMAEN;
1253 writel(temp, sport->port.membase + UCR1);
1254 sport->dma_is_txing = false;
1255 }
1256
1257 /*
1258 * According to the Reference Manual description of the UART SRST bit:
1259 * "Reset the transmit and receive state machines,
1260 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1261 * and UTS[6-3]". As we don't need to restore the old values from
1262 * USR1, USR2, URXD, UTXD, only save/restore the other four registers
1263 */
1264 ubir = readl(sport->port.membase + UBIR);
1265 ubmr = readl(sport->port.membase + UBMR);
1266 uts = readl(sport->port.membase + IMX21_UTS);
1267
1268 temp = readl(sport->port.membase + UCR2);
1269 temp &= ~UCR2_SRST;
1270 writel(temp, sport->port.membase + UCR2);
1271
1272 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1273 udelay(1);
1274
1275 /* Restore the registers */
1276 writel(ubir, sport->port.membase + UBIR);
1277 writel(ubmr, sport->port.membase + UBMR);
1278 writel(uts, sport->port.membase + IMX21_UTS);
1279 }
1280
1281 static void
1282 imx_set_termios(struct uart_port *port, struct ktermios *termios,
1283 struct ktermios *old)
1284 {
1285 struct imx_port *sport = (struct imx_port *)port;
1286 unsigned long flags;
1287 unsigned int ucr2, old_ucr1, old_ucr2, baud, quot;
1288 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1289 unsigned int div, ufcr;
1290 unsigned long num, denom;
1291 uint64_t tdiv64;
1292
1293 /*
1294 * We only support CS7 and CS8.
1295 */
1296 while ((termios->c_cflag & CSIZE) != CS7 &&
1297 (termios->c_cflag & CSIZE) != CS8) {
1298 termios->c_cflag &= ~CSIZE;
1299 termios->c_cflag |= old_csize;
1300 old_csize = CS8;
1301 }
1302
1303 if ((termios->c_cflag & CSIZE) == CS8)
1304 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1305 else
1306 ucr2 = UCR2_SRST | UCR2_IRTS;
1307
1308 if (termios->c_cflag & CRTSCTS) {
1309 if (sport->have_rtscts) {
1310 ucr2 &= ~UCR2_IRTS;
1311
1312 if (port->rs485.flags & SER_RS485_ENABLED) {
1313 /*
1314 * RTS is mandatory for rs485 operation, so keep
1315 * it under manual control and keep transmitter
1316 * disabled.
1317 */
1318 if (!(port->rs485.flags &
1319 SER_RS485_RTS_AFTER_SEND))
1320 ucr2 |= UCR2_CTS;
1321 } else {
1322 ucr2 |= UCR2_CTSC;
1323 }
1324 } else {
1325 termios->c_cflag &= ~CRTSCTS;
1326 }
1327 } else if (port->rs485.flags & SER_RS485_ENABLED)
1328 /* disable transmitter */
1329 if (!(port->rs485.flags & SER_RS485_RTS_AFTER_SEND))
1330 ucr2 |= UCR2_CTS;
1331
1332 if (termios->c_cflag & CSTOPB)
1333 ucr2 |= UCR2_STPB;
1334 if (termios->c_cflag & PARENB) {
1335 ucr2 |= UCR2_PREN;
1336 if (termios->c_cflag & PARODD)
1337 ucr2 |= UCR2_PROE;
1338 }
1339
1340 del_timer_sync(&sport->timer);
1341
1342 /*
1343 * Ask the core to calculate the divisor for us.
1344 */
1345 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1346 quot = uart_get_divisor(port, baud);
1347
1348 spin_lock_irqsave(&sport->port.lock, flags);
1349
1350 sport->port.read_status_mask = 0;
1351 if (termios->c_iflag & INPCK)
1352 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1353 if (termios->c_iflag & (BRKINT | PARMRK))
1354 sport->port.read_status_mask |= URXD_BRK;
1355
1356 /*
1357 * Characters to ignore
1358 */
1359 sport->port.ignore_status_mask = 0;
1360 if (termios->c_iflag & IGNPAR)
1361 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1362 if (termios->c_iflag & IGNBRK) {
1363 sport->port.ignore_status_mask |= URXD_BRK;
1364 /*
1365 * If we're ignoring parity and break indicators,
1366 * ignore overruns too (for real raw support).
1367 */
1368 if (termios->c_iflag & IGNPAR)
1369 sport->port.ignore_status_mask |= URXD_OVRRUN;
1370 }
1371
1372 if ((termios->c_cflag & CREAD) == 0)
1373 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1374
1375 /*
1376 * Update the per-port timeout.
1377 */
1378 uart_update_timeout(port, termios->c_cflag, baud);
1379
1380 /*
1381 * disable interrupts and drain transmitter
1382 */
1383 old_ucr1 = readl(sport->port.membase + UCR1);
1384 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1385 sport->port.membase + UCR1);
1386
1387 while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1388 barrier();
1389
1390 /* then, disable everything */
1391 old_ucr2 = readl(sport->port.membase + UCR2);
1392 writel(old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN),
1393 sport->port.membase + UCR2);
1394 old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN);
1395
1396 /* custom-baudrate handling */
1397 div = sport->port.uartclk / (baud * 16);
1398 if (baud == 38400 && quot != div)
1399 baud = sport->port.uartclk / (quot * 16);
1400
1401 div = sport->port.uartclk / (baud * 16);
1402 if (div > 7)
1403 div = 7;
1404 if (!div)
1405 div = 1;
1406
1407 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1408 1 << 16, 1 << 16, &num, &denom);
1409
1410 tdiv64 = sport->port.uartclk;
1411 tdiv64 *= num;
1412 do_div(tdiv64, denom * 16 * div);
1413 tty_termios_encode_baud_rate(termios,
1414 (speed_t)tdiv64, (speed_t)tdiv64);
1415
1416 num -= 1;
1417 denom -= 1;
1418
1419 ufcr = readl(sport->port.membase + UFCR);
1420 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1421 if (sport->dte_mode)
1422 ufcr |= UFCR_DCEDTE;
1423 writel(ufcr, sport->port.membase + UFCR);
1424
1425 writel(num, sport->port.membase + UBIR);
1426 writel(denom, sport->port.membase + UBMR);
1427
1428 if (!is_imx1_uart(sport))
1429 writel(sport->port.uartclk / div / 1000,
1430 sport->port.membase + IMX21_ONEMS);
1431
1432 writel(old_ucr1, sport->port.membase + UCR1);
1433
1434 /* set the parity, stop bits and data size */
1435 writel(ucr2 | old_ucr2, sport->port.membase + UCR2);
1436
1437 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1438 imx_enable_ms(&sport->port);
1439
1440 spin_unlock_irqrestore(&sport->port.lock, flags);
1441 }
1442
1443 static const char *imx_type(struct uart_port *port)
1444 {
1445 struct imx_port *sport = (struct imx_port *)port;
1446
1447 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1448 }
1449
1450 /*
1451 * Configure/autoconfigure the port.
1452 */
1453 static void imx_config_port(struct uart_port *port, int flags)
1454 {
1455 struct imx_port *sport = (struct imx_port *)port;
1456
1457 if (flags & UART_CONFIG_TYPE)
1458 sport->port.type = PORT_IMX;
1459 }
1460
1461 /*
1462 * Verify the new serial_struct (for TIOCSSERIAL).
1463 * The only change we allow are to the flags and type, and
1464 * even then only between PORT_IMX and PORT_UNKNOWN
1465 */
1466 static int
1467 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1468 {
1469 struct imx_port *sport = (struct imx_port *)port;
1470 int ret = 0;
1471
1472 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1473 ret = -EINVAL;
1474 if (sport->port.irq != ser->irq)
1475 ret = -EINVAL;
1476 if (ser->io_type != UPIO_MEM)
1477 ret = -EINVAL;
1478 if (sport->port.uartclk / 16 != ser->baud_base)
1479 ret = -EINVAL;
1480 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1481 ret = -EINVAL;
1482 if (sport->port.iobase != ser->port)
1483 ret = -EINVAL;
1484 if (ser->hub6 != 0)
1485 ret = -EINVAL;
1486 return ret;
1487 }
1488
1489 #if defined(CONFIG_CONSOLE_POLL)
1490
1491 static int imx_poll_init(struct uart_port *port)
1492 {
1493 struct imx_port *sport = (struct imx_port *)port;
1494 unsigned long flags;
1495 unsigned long temp;
1496 int retval;
1497
1498 retval = clk_prepare_enable(sport->clk_ipg);
1499 if (retval)
1500 return retval;
1501 retval = clk_prepare_enable(sport->clk_per);
1502 if (retval)
1503 clk_disable_unprepare(sport->clk_ipg);
1504
1505 imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1506
1507 spin_lock_irqsave(&sport->port.lock, flags);
1508
1509 temp = readl(sport->port.membase + UCR1);
1510 if (is_imx1_uart(sport))
1511 temp |= IMX1_UCR1_UARTCLKEN;
1512 temp |= UCR1_UARTEN | UCR1_RRDYEN;
1513 temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN);
1514 writel(temp, sport->port.membase + UCR1);
1515
1516 temp = readl(sport->port.membase + UCR2);
1517 temp |= UCR2_RXEN;
1518 writel(temp, sport->port.membase + UCR2);
1519
1520 spin_unlock_irqrestore(&sport->port.lock, flags);
1521
1522 return 0;
1523 }
1524
1525 static int imx_poll_get_char(struct uart_port *port)
1526 {
1527 if (!(readl_relaxed(port->membase + USR2) & USR2_RDR))
1528 return NO_POLL_CHAR;
1529
1530 return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA;
1531 }
1532
1533 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1534 {
1535 unsigned int status;
1536
1537 /* drain */
1538 do {
1539 status = readl_relaxed(port->membase + USR1);
1540 } while (~status & USR1_TRDY);
1541
1542 /* write */
1543 writel_relaxed(c, port->membase + URTX0);
1544
1545 /* flush */
1546 do {
1547 status = readl_relaxed(port->membase + USR2);
1548 } while (~status & USR2_TXDC);
1549 }
1550 #endif
1551
1552 static int imx_rs485_config(struct uart_port *port,
1553 struct serial_rs485 *rs485conf)
1554 {
1555 struct imx_port *sport = (struct imx_port *)port;
1556
1557 /* unimplemented */
1558 rs485conf->delay_rts_before_send = 0;
1559 rs485conf->delay_rts_after_send = 0;
1560 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1561
1562 /* RTS is required to control the transmitter */
1563 if (!sport->have_rtscts)
1564 rs485conf->flags &= ~SER_RS485_ENABLED;
1565
1566 if (rs485conf->flags & SER_RS485_ENABLED) {
1567 unsigned long temp;
1568
1569 /* disable transmitter */
1570 temp = readl(sport->port.membase + UCR2);
1571 temp &= ~UCR2_CTSC;
1572 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1573 temp &= ~UCR2_CTS;
1574 else
1575 temp |= UCR2_CTS;
1576 writel(temp, sport->port.membase + UCR2);
1577 }
1578
1579 port->rs485 = *rs485conf;
1580
1581 return 0;
1582 }
1583
1584 static struct uart_ops imx_pops = {
1585 .tx_empty = imx_tx_empty,
1586 .set_mctrl = imx_set_mctrl,
1587 .get_mctrl = imx_get_mctrl,
1588 .stop_tx = imx_stop_tx,
1589 .start_tx = imx_start_tx,
1590 .stop_rx = imx_stop_rx,
1591 .enable_ms = imx_enable_ms,
1592 .break_ctl = imx_break_ctl,
1593 .startup = imx_startup,
1594 .shutdown = imx_shutdown,
1595 .flush_buffer = imx_flush_buffer,
1596 .set_termios = imx_set_termios,
1597 .type = imx_type,
1598 .config_port = imx_config_port,
1599 .verify_port = imx_verify_port,
1600 #if defined(CONFIG_CONSOLE_POLL)
1601 .poll_init = imx_poll_init,
1602 .poll_get_char = imx_poll_get_char,
1603 .poll_put_char = imx_poll_put_char,
1604 #endif
1605 };
1606
1607 static struct imx_port *imx_ports[UART_NR];
1608
1609 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1610 static void imx_console_putchar(struct uart_port *port, int ch)
1611 {
1612 struct imx_port *sport = (struct imx_port *)port;
1613
1614 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1615 barrier();
1616
1617 writel(ch, sport->port.membase + URTX0);
1618 }
1619
1620 /*
1621 * Interrupts are disabled on entering
1622 */
1623 static void
1624 imx_console_write(struct console *co, const char *s, unsigned int count)
1625 {
1626 struct imx_port *sport = imx_ports[co->index];
1627 struct imx_port_ucrs old_ucr;
1628 unsigned int ucr1;
1629 unsigned long flags = 0;
1630 int locked = 1;
1631 int retval;
1632
1633 retval = clk_enable(sport->clk_per);
1634 if (retval)
1635 return;
1636 retval = clk_enable(sport->clk_ipg);
1637 if (retval) {
1638 clk_disable(sport->clk_per);
1639 return;
1640 }
1641
1642 if (sport->port.sysrq)
1643 locked = 0;
1644 else if (oops_in_progress)
1645 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1646 else
1647 spin_lock_irqsave(&sport->port.lock, flags);
1648
1649 /*
1650 * First, save UCR1/2/3 and then disable interrupts
1651 */
1652 imx_port_ucrs_save(&sport->port, &old_ucr);
1653 ucr1 = old_ucr.ucr1;
1654
1655 if (is_imx1_uart(sport))
1656 ucr1 |= IMX1_UCR1_UARTCLKEN;
1657 ucr1 |= UCR1_UARTEN;
1658 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1659
1660 writel(ucr1, sport->port.membase + UCR1);
1661
1662 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1663
1664 uart_console_write(&sport->port, s, count, imx_console_putchar);
1665
1666 /*
1667 * Finally, wait for transmitter to become empty
1668 * and restore UCR1/2/3
1669 */
1670 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1671
1672 imx_port_ucrs_restore(&sport->port, &old_ucr);
1673
1674 if (locked)
1675 spin_unlock_irqrestore(&sport->port.lock, flags);
1676
1677 clk_disable(sport->clk_ipg);
1678 clk_disable(sport->clk_per);
1679 }
1680
1681 /*
1682 * If the port was already initialised (eg, by a boot loader),
1683 * try to determine the current setup.
1684 */
1685 static void __init
1686 imx_console_get_options(struct imx_port *sport, int *baud,
1687 int *parity, int *bits)
1688 {
1689
1690 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1691 /* ok, the port was enabled */
1692 unsigned int ucr2, ubir, ubmr, uartclk;
1693 unsigned int baud_raw;
1694 unsigned int ucfr_rfdiv;
1695
1696 ucr2 = readl(sport->port.membase + UCR2);
1697
1698 *parity = 'n';
1699 if (ucr2 & UCR2_PREN) {
1700 if (ucr2 & UCR2_PROE)
1701 *parity = 'o';
1702 else
1703 *parity = 'e';
1704 }
1705
1706 if (ucr2 & UCR2_WS)
1707 *bits = 8;
1708 else
1709 *bits = 7;
1710
1711 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1712 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1713
1714 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1715 if (ucfr_rfdiv == 6)
1716 ucfr_rfdiv = 7;
1717 else
1718 ucfr_rfdiv = 6 - ucfr_rfdiv;
1719
1720 uartclk = clk_get_rate(sport->clk_per);
1721 uartclk /= ucfr_rfdiv;
1722
1723 { /*
1724 * The next code provides exact computation of
1725 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1726 * without need of float support or long long division,
1727 * which would be required to prevent 32bit arithmetic overflow
1728 */
1729 unsigned int mul = ubir + 1;
1730 unsigned int div = 16 * (ubmr + 1);
1731 unsigned int rem = uartclk % div;
1732
1733 baud_raw = (uartclk / div) * mul;
1734 baud_raw += (rem * mul + div / 2) / div;
1735 *baud = (baud_raw + 50) / 100 * 100;
1736 }
1737
1738 if (*baud != baud_raw)
1739 pr_info("Console IMX rounded baud rate from %d to %d\n",
1740 baud_raw, *baud);
1741 }
1742 }
1743
1744 static int __init
1745 imx_console_setup(struct console *co, char *options)
1746 {
1747 struct imx_port *sport;
1748 int baud = 9600;
1749 int bits = 8;
1750 int parity = 'n';
1751 int flow = 'n';
1752 int retval;
1753
1754 /*
1755 * Check whether an invalid uart number has been specified, and
1756 * if so, search for the first available port that does have
1757 * console support.
1758 */
1759 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1760 co->index = 0;
1761 sport = imx_ports[co->index];
1762 if (sport == NULL)
1763 return -ENODEV;
1764
1765 /* For setting the registers, we only need to enable the ipg clock. */
1766 retval = clk_prepare_enable(sport->clk_ipg);
1767 if (retval)
1768 goto error_console;
1769
1770 if (options)
1771 uart_parse_options(options, &baud, &parity, &bits, &flow);
1772 else
1773 imx_console_get_options(sport, &baud, &parity, &bits);
1774
1775 imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1776
1777 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1778
1779 clk_disable(sport->clk_ipg);
1780 if (retval) {
1781 clk_unprepare(sport->clk_ipg);
1782 goto error_console;
1783 }
1784
1785 retval = clk_prepare(sport->clk_per);
1786 if (retval)
1787 clk_disable_unprepare(sport->clk_ipg);
1788
1789 error_console:
1790 return retval;
1791 }
1792
1793 static struct uart_driver imx_reg;
1794 static struct console imx_console = {
1795 .name = DEV_NAME,
1796 .write = imx_console_write,
1797 .device = uart_console_device,
1798 .setup = imx_console_setup,
1799 .flags = CON_PRINTBUFFER,
1800 .index = -1,
1801 .data = &imx_reg,
1802 };
1803
1804 #define IMX_CONSOLE &imx_console
1805
1806 #ifdef CONFIG_OF
1807 static void imx_console_early_putchar(struct uart_port *port, int ch)
1808 {
1809 while (readl_relaxed(port->membase + IMX21_UTS) & UTS_TXFULL)
1810 cpu_relax();
1811
1812 writel_relaxed(ch, port->membase + URTX0);
1813 }
1814
1815 static void imx_console_early_write(struct console *con, const char *s,
1816 unsigned count)
1817 {
1818 struct earlycon_device *dev = con->data;
1819
1820 uart_console_write(&dev->port, s, count, imx_console_early_putchar);
1821 }
1822
1823 static int __init
1824 imx_console_early_setup(struct earlycon_device *dev, const char *opt)
1825 {
1826 if (!dev->port.membase)
1827 return -ENODEV;
1828
1829 dev->con->write = imx_console_early_write;
1830
1831 return 0;
1832 }
1833 OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup);
1834 OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup);
1835 #endif
1836
1837 #else
1838 #define IMX_CONSOLE NULL
1839 #endif
1840
1841 static struct uart_driver imx_reg = {
1842 .owner = THIS_MODULE,
1843 .driver_name = DRIVER_NAME,
1844 .dev_name = DEV_NAME,
1845 .major = SERIAL_IMX_MAJOR,
1846 .minor = MINOR_START,
1847 .nr = ARRAY_SIZE(imx_ports),
1848 .cons = IMX_CONSOLE,
1849 };
1850
1851 #ifdef CONFIG_OF
1852 /*
1853 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1854 * could successfully get all information from dt or a negative errno.
1855 */
1856 static int serial_imx_probe_dt(struct imx_port *sport,
1857 struct platform_device *pdev)
1858 {
1859 struct device_node *np = pdev->dev.of_node;
1860 const struct of_device_id *of_id =
1861 of_match_device(imx_uart_dt_ids, &pdev->dev);
1862 int ret;
1863
1864 if (!np)
1865 /* no device tree device */
1866 return 1;
1867
1868 ret = of_alias_get_id(np, "serial");
1869 if (ret < 0) {
1870 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1871 return ret;
1872 }
1873 sport->port.line = ret;
1874
1875 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1876 sport->have_rtscts = 1;
1877
1878 if (of_get_property(np, "fsl,dte-mode", NULL))
1879 sport->dte_mode = 1;
1880
1881 sport->devdata = of_id->data;
1882
1883 return 0;
1884 }
1885 #else
1886 static inline int serial_imx_probe_dt(struct imx_port *sport,
1887 struct platform_device *pdev)
1888 {
1889 return 1;
1890 }
1891 #endif
1892
1893 static void serial_imx_probe_pdata(struct imx_port *sport,
1894 struct platform_device *pdev)
1895 {
1896 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
1897
1898 sport->port.line = pdev->id;
1899 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1900
1901 if (!pdata)
1902 return;
1903
1904 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1905 sport->have_rtscts = 1;
1906 }
1907
1908 static int serial_imx_probe(struct platform_device *pdev)
1909 {
1910 struct imx_port *sport;
1911 void __iomem *base;
1912 int ret = 0, reg;
1913 struct resource *res;
1914 int txirq, rxirq, rtsirq;
1915
1916 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1917 if (!sport)
1918 return -ENOMEM;
1919
1920 ret = serial_imx_probe_dt(sport, pdev);
1921 if (ret > 0)
1922 serial_imx_probe_pdata(sport, pdev);
1923 else if (ret < 0)
1924 return ret;
1925
1926 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1927 base = devm_ioremap_resource(&pdev->dev, res);
1928 if (IS_ERR(base))
1929 return PTR_ERR(base);
1930
1931 rxirq = platform_get_irq(pdev, 0);
1932 txirq = platform_get_irq(pdev, 1);
1933 rtsirq = platform_get_irq(pdev, 2);
1934
1935 sport->port.dev = &pdev->dev;
1936 sport->port.mapbase = res->start;
1937 sport->port.membase = base;
1938 sport->port.type = PORT_IMX,
1939 sport->port.iotype = UPIO_MEM;
1940 sport->port.irq = rxirq;
1941 sport->port.fifosize = 32;
1942 sport->port.ops = &imx_pops;
1943 sport->port.rs485_config = imx_rs485_config;
1944 sport->port.rs485.flags =
1945 SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX;
1946 sport->port.flags = UPF_BOOT_AUTOCONF;
1947 init_timer(&sport->timer);
1948 sport->timer.function = imx_timeout;
1949 sport->timer.data = (unsigned long)sport;
1950
1951 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1952 if (IS_ERR(sport->clk_ipg)) {
1953 ret = PTR_ERR(sport->clk_ipg);
1954 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
1955 return ret;
1956 }
1957
1958 sport->clk_per = devm_clk_get(&pdev->dev, "per");
1959 if (IS_ERR(sport->clk_per)) {
1960 ret = PTR_ERR(sport->clk_per);
1961 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
1962 return ret;
1963 }
1964
1965 sport->port.uartclk = clk_get_rate(sport->clk_per);
1966
1967 /* For register access, we only need to enable the ipg clock. */
1968 ret = clk_prepare_enable(sport->clk_ipg);
1969 if (ret)
1970 return ret;
1971
1972 /* Disable interrupts before requesting them */
1973 reg = readl_relaxed(sport->port.membase + UCR1);
1974 reg &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN |
1975 UCR1_TXMPTYEN | UCR1_RTSDEN);
1976 writel_relaxed(reg, sport->port.membase + UCR1);
1977
1978 clk_disable_unprepare(sport->clk_ipg);
1979
1980 /*
1981 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
1982 * chips only have one interrupt.
1983 */
1984 if (txirq > 0) {
1985 ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0,
1986 dev_name(&pdev->dev), sport);
1987 if (ret)
1988 return ret;
1989
1990 ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0,
1991 dev_name(&pdev->dev), sport);
1992 if (ret)
1993 return ret;
1994 } else {
1995 ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0,
1996 dev_name(&pdev->dev), sport);
1997 if (ret)
1998 return ret;
1999 }
2000
2001 imx_ports[sport->port.line] = sport;
2002
2003 platform_set_drvdata(pdev, sport);
2004
2005 return uart_add_one_port(&imx_reg, &sport->port);
2006 }
2007
2008 static int serial_imx_remove(struct platform_device *pdev)
2009 {
2010 struct imx_port *sport = platform_get_drvdata(pdev);
2011
2012 return uart_remove_one_port(&imx_reg, &sport->port);
2013 }
2014
2015 static void serial_imx_restore_context(struct imx_port *sport)
2016 {
2017 if (!sport->context_saved)
2018 return;
2019
2020 writel(sport->saved_reg[4], sport->port.membase + UFCR);
2021 writel(sport->saved_reg[5], sport->port.membase + UESC);
2022 writel(sport->saved_reg[6], sport->port.membase + UTIM);
2023 writel(sport->saved_reg[7], sport->port.membase + UBIR);
2024 writel(sport->saved_reg[8], sport->port.membase + UBMR);
2025 writel(sport->saved_reg[9], sport->port.membase + IMX21_UTS);
2026 writel(sport->saved_reg[0], sport->port.membase + UCR1);
2027 writel(sport->saved_reg[1] | UCR2_SRST, sport->port.membase + UCR2);
2028 writel(sport->saved_reg[2], sport->port.membase + UCR3);
2029 writel(sport->saved_reg[3], sport->port.membase + UCR4);
2030 sport->context_saved = false;
2031 }
2032
2033 static void serial_imx_save_context(struct imx_port *sport)
2034 {
2035 /* Save necessary regs */
2036 sport->saved_reg[0] = readl(sport->port.membase + UCR1);
2037 sport->saved_reg[1] = readl(sport->port.membase + UCR2);
2038 sport->saved_reg[2] = readl(sport->port.membase + UCR3);
2039 sport->saved_reg[3] = readl(sport->port.membase + UCR4);
2040 sport->saved_reg[4] = readl(sport->port.membase + UFCR);
2041 sport->saved_reg[5] = readl(sport->port.membase + UESC);
2042 sport->saved_reg[6] = readl(sport->port.membase + UTIM);
2043 sport->saved_reg[7] = readl(sport->port.membase + UBIR);
2044 sport->saved_reg[8] = readl(sport->port.membase + UBMR);
2045 sport->saved_reg[9] = readl(sport->port.membase + IMX21_UTS);
2046 sport->context_saved = true;
2047 }
2048
2049 static void serial_imx_enable_wakeup(struct imx_port *sport, bool on)
2050 {
2051 unsigned int val;
2052
2053 val = readl(sport->port.membase + UCR3);
2054 if (on)
2055 val |= UCR3_AWAKEN;
2056 else
2057 val &= ~UCR3_AWAKEN;
2058 writel(val, sport->port.membase + UCR3);
2059
2060 val = readl(sport->port.membase + UCR1);
2061 if (on)
2062 val |= UCR1_RTSDEN;
2063 else
2064 val &= ~UCR1_RTSDEN;
2065 writel(val, sport->port.membase + UCR1);
2066 }
2067
2068 static int imx_serial_port_suspend_noirq(struct device *dev)
2069 {
2070 struct platform_device *pdev = to_platform_device(dev);
2071 struct imx_port *sport = platform_get_drvdata(pdev);
2072 int ret;
2073
2074 ret = clk_enable(sport->clk_ipg);
2075 if (ret)
2076 return ret;
2077
2078 serial_imx_save_context(sport);
2079
2080 clk_disable(sport->clk_ipg);
2081
2082 return 0;
2083 }
2084
2085 static int imx_serial_port_resume_noirq(struct device *dev)
2086 {
2087 struct platform_device *pdev = to_platform_device(dev);
2088 struct imx_port *sport = platform_get_drvdata(pdev);
2089 int ret;
2090
2091 ret = clk_enable(sport->clk_ipg);
2092 if (ret)
2093 return ret;
2094
2095 serial_imx_restore_context(sport);
2096
2097 clk_disable(sport->clk_ipg);
2098
2099 return 0;
2100 }
2101
2102 static int imx_serial_port_suspend(struct device *dev)
2103 {
2104 struct platform_device *pdev = to_platform_device(dev);
2105 struct imx_port *sport = platform_get_drvdata(pdev);
2106
2107 /* enable wakeup from i.MX UART */
2108 serial_imx_enable_wakeup(sport, true);
2109
2110 uart_suspend_port(&imx_reg, &sport->port);
2111
2112 return 0;
2113 }
2114
2115 static int imx_serial_port_resume(struct device *dev)
2116 {
2117 struct platform_device *pdev = to_platform_device(dev);
2118 struct imx_port *sport = platform_get_drvdata(pdev);
2119
2120 /* disable wakeup from i.MX UART */
2121 serial_imx_enable_wakeup(sport, false);
2122
2123 uart_resume_port(&imx_reg, &sport->port);
2124
2125 return 0;
2126 }
2127
2128 static const struct dev_pm_ops imx_serial_port_pm_ops = {
2129 .suspend_noirq = imx_serial_port_suspend_noirq,
2130 .resume_noirq = imx_serial_port_resume_noirq,
2131 .suspend = imx_serial_port_suspend,
2132 .resume = imx_serial_port_resume,
2133 };
2134
2135 static struct platform_driver serial_imx_driver = {
2136 .probe = serial_imx_probe,
2137 .remove = serial_imx_remove,
2138
2139 .id_table = imx_uart_devtype,
2140 .driver = {
2141 .name = "imx-uart",
2142 .of_match_table = imx_uart_dt_ids,
2143 .pm = &imx_serial_port_pm_ops,
2144 },
2145 };
2146
2147 static int __init imx_serial_init(void)
2148 {
2149 int ret = uart_register_driver(&imx_reg);
2150
2151 if (ret)
2152 return ret;
2153
2154 ret = platform_driver_register(&serial_imx_driver);
2155 if (ret != 0)
2156 uart_unregister_driver(&imx_reg);
2157
2158 return ret;
2159 }
2160
2161 static void __exit imx_serial_exit(void)
2162 {
2163 platform_driver_unregister(&serial_imx_driver);
2164 uart_unregister_driver(&imx_reg);
2165 }
2166
2167 module_init(imx_serial_init);
2168 module_exit(imx_serial_exit);
2169
2170 MODULE_AUTHOR("Sascha Hauer");
2171 MODULE_DESCRIPTION("IMX generic serial port driver");
2172 MODULE_LICENSE("GPL");
2173 MODULE_ALIAS("platform:imx-uart");
Linux kernel - Deliverables
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