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73158d96822a0269a5a2d523f369783e3c8edfd7
[deliverable/linux.git] / drivers / tty / serial / imx.c
1 /*
2 * Driver for Motorola IMX serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
8 *
9 * Copyright (C) 2009 emlix GmbH
10 * Author: Fabian Godehardt (added IrDA support for iMX)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * [29-Mar-2005] Mike Lee
27 * Added hardware handshake
28 */
29
30 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31 #define SUPPORT_SYSRQ
32 #endif
33
34 #include <linux/module.h>
35 #include <linux/ioport.h>
36 #include <linux/init.h>
37 #include <linux/console.h>
38 #include <linux/sysrq.h>
39 #include <linux/platform_device.h>
40 #include <linux/tty.h>
41 #include <linux/tty_flip.h>
42 #include <linux/serial_core.h>
43 #include <linux/serial.h>
44 #include <linux/clk.h>
45 #include <linux/delay.h>
46 #include <linux/rational.h>
47 #include <linux/slab.h>
48 #include <linux/of.h>
49 #include <linux/of_device.h>
50 #include <linux/io.h>
51 #include <linux/dma-mapping.h>
52
53 #include <asm/irq.h>
54 #include <linux/platform_data/serial-imx.h>
55 #include <linux/platform_data/dma-imx.h>
56
57 /* Register definitions */
58 #define URXD0 0x0 /* Receiver Register */
59 #define URTX0 0x40 /* Transmitter Register */
60 #define UCR1 0x80 /* Control Register 1 */
61 #define UCR2 0x84 /* Control Register 2 */
62 #define UCR3 0x88 /* Control Register 3 */
63 #define UCR4 0x8c /* Control Register 4 */
64 #define UFCR 0x90 /* FIFO Control Register */
65 #define USR1 0x94 /* Status Register 1 */
66 #define USR2 0x98 /* Status Register 2 */
67 #define UESC 0x9c /* Escape Character Register */
68 #define UTIM 0xa0 /* Escape Timer Register */
69 #define UBIR 0xa4 /* BRM Incremental Register */
70 #define UBMR 0xa8 /* BRM Modulator Register */
71 #define UBRC 0xac /* Baud Rate Count Register */
72 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
73 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
74 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
75
76 /* UART Control Register Bit Fields.*/
77 #define URXD_DUMMY_READ (1<<16)
78 #define URXD_CHARRDY (1<<15)
79 #define URXD_ERR (1<<14)
80 #define URXD_OVRRUN (1<<13)
81 #define URXD_FRMERR (1<<12)
82 #define URXD_BRK (1<<11)
83 #define URXD_PRERR (1<<10)
84 #define URXD_RX_DATA (0xFF<<0)
85 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
86 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
87 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
88 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
89 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
90 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
91 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
92 #define UCR1_IREN (1<<7) /* Infrared interface enable */
93 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
94 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
95 #define UCR1_SNDBRK (1<<4) /* Send break */
96 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
97 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
98 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
99 #define UCR1_DOZE (1<<1) /* Doze */
100 #define UCR1_UARTEN (1<<0) /* UART enabled */
101 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
102 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
103 #define UCR2_CTSC (1<<13) /* CTS pin control */
104 #define UCR2_CTS (1<<12) /* Clear to send */
105 #define UCR2_ESCEN (1<<11) /* Escape enable */
106 #define UCR2_PREN (1<<8) /* Parity enable */
107 #define UCR2_PROE (1<<7) /* Parity odd/even */
108 #define UCR2_STPB (1<<6) /* Stop */
109 #define UCR2_WS (1<<5) /* Word size */
110 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
111 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
112 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
113 #define UCR2_RXEN (1<<1) /* Receiver enabled */
114 #define UCR2_SRST (1<<0) /* SW reset */
115 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
116 #define UCR3_PARERREN (1<<12) /* Parity enable */
117 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
118 #define UCR3_DSR (1<<10) /* Data set ready */
119 #define UCR3_DCD (1<<9) /* Data carrier detect */
120 #define UCR3_RI (1<<8) /* Ring indicator */
121 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
122 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
123 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
124 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
125 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
126 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
127 #define UCR3_BPEN (1<<0) /* Preset registers enable */
128 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
129 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
130 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
131 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
132 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
133 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
134 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
135 #define UCR4_IRSC (1<<5) /* IR special case */
136 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
137 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
138 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
139 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
140 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
141 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
142 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
143 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
144 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
145 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
146 #define USR1_RTSS (1<<14) /* RTS pin status */
147 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
148 #define USR1_RTSD (1<<12) /* RTS delta */
149 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
150 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
151 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
152 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
153 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
154 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
155 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
156 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
157 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
158 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
159 #define USR2_IDLE (1<<12) /* Idle condition */
160 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
161 #define USR2_WAKE (1<<7) /* Wake */
162 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
163 #define USR2_TXDC (1<<3) /* Transmitter complete */
164 #define USR2_BRCD (1<<2) /* Break condition */
165 #define USR2_ORE (1<<1) /* Overrun error */
166 #define USR2_RDR (1<<0) /* Recv data ready */
167 #define UTS_FRCPERR (1<<13) /* Force parity error */
168 #define UTS_LOOP (1<<12) /* Loop tx and rx */
169 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
170 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
171 #define UTS_TXFULL (1<<4) /* TxFIFO full */
172 #define UTS_RXFULL (1<<3) /* RxFIFO full */
173 #define UTS_SOFTRST (1<<0) /* Software reset */
174
175 /* We've been assigned a range on the "Low-density serial ports" major */
176 #define SERIAL_IMX_MAJOR 207
177 #define MINOR_START 16
178 #define DEV_NAME "ttymxc"
179
180 /*
181 * This determines how often we check the modem status signals
182 * for any change. They generally aren't connected to an IRQ
183 * so we have to poll them. We also check immediately before
184 * filling the TX fifo incase CTS has been dropped.
185 */
186 #define MCTRL_TIMEOUT (250*HZ/1000)
187
188 #define DRIVER_NAME "IMX-uart"
189
190 #define UART_NR 8
191
192 /* i.mx21 type uart runs on all i.mx except i.mx1 */
193 enum imx_uart_type {
194 IMX1_UART,
195 IMX21_UART,
196 IMX6Q_UART,
197 };
198
199 /* device type dependent stuff */
200 struct imx_uart_data {
201 unsigned uts_reg;
202 enum imx_uart_type devtype;
203 };
204
205 struct imx_port {
206 struct uart_port port;
207 struct timer_list timer;
208 unsigned int old_status;
209 int txirq, rxirq, rtsirq;
210 unsigned int have_rtscts:1;
211 unsigned int dte_mode:1;
212 unsigned int use_irda:1;
213 unsigned int irda_inv_rx:1;
214 unsigned int irda_inv_tx:1;
215 unsigned short trcv_delay; /* transceiver delay */
216 struct clk *clk_ipg;
217 struct clk *clk_per;
218 const struct imx_uart_data *devdata;
219
220 /* DMA fields */
221 unsigned int dma_is_inited:1;
222 unsigned int dma_is_enabled:1;
223 unsigned int dma_is_rxing:1;
224 unsigned int dma_is_txing:1;
225 struct dma_chan *dma_chan_rx, *dma_chan_tx;
226 struct scatterlist rx_sgl, tx_sgl[2];
227 void *rx_buf;
228 unsigned int tx_bytes;
229 unsigned int dma_tx_nents;
230 wait_queue_head_t dma_wait;
231 };
232
233 struct imx_port_ucrs {
234 unsigned int ucr1;
235 unsigned int ucr2;
236 unsigned int ucr3;
237 };
238
239 #ifdef CONFIG_IRDA
240 #define USE_IRDA(sport) ((sport)->use_irda)
241 #else
242 #define USE_IRDA(sport) (0)
243 #endif
244
245 static struct imx_uart_data imx_uart_devdata[] = {
246 [IMX1_UART] = {
247 .uts_reg = IMX1_UTS,
248 .devtype = IMX1_UART,
249 },
250 [IMX21_UART] = {
251 .uts_reg = IMX21_UTS,
252 .devtype = IMX21_UART,
253 },
254 [IMX6Q_UART] = {
255 .uts_reg = IMX21_UTS,
256 .devtype = IMX6Q_UART,
257 },
258 };
259
260 static struct platform_device_id imx_uart_devtype[] = {
261 {
262 .name = "imx1-uart",
263 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
264 }, {
265 .name = "imx21-uart",
266 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
267 }, {
268 .name = "imx6q-uart",
269 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
270 }, {
271 /* sentinel */
272 }
273 };
274 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
275
276 static struct of_device_id imx_uart_dt_ids[] = {
277 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
278 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
279 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
280 { /* sentinel */ }
281 };
282 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
283
284 static inline unsigned uts_reg(struct imx_port *sport)
285 {
286 return sport->devdata->uts_reg;
287 }
288
289 static inline int is_imx1_uart(struct imx_port *sport)
290 {
291 return sport->devdata->devtype == IMX1_UART;
292 }
293
294 static inline int is_imx21_uart(struct imx_port *sport)
295 {
296 return sport->devdata->devtype == IMX21_UART;
297 }
298
299 static inline int is_imx6q_uart(struct imx_port *sport)
300 {
301 return sport->devdata->devtype == IMX6Q_UART;
302 }
303 /*
304 * Save and restore functions for UCR1, UCR2 and UCR3 registers
305 */
306 #if defined(CONFIG_SERIAL_IMX_CONSOLE)
307 static void imx_port_ucrs_save(struct uart_port *port,
308 struct imx_port_ucrs *ucr)
309 {
310 /* save control registers */
311 ucr->ucr1 = readl(port->membase + UCR1);
312 ucr->ucr2 = readl(port->membase + UCR2);
313 ucr->ucr3 = readl(port->membase + UCR3);
314 }
315
316 static void imx_port_ucrs_restore(struct uart_port *port,
317 struct imx_port_ucrs *ucr)
318 {
319 /* restore control registers */
320 writel(ucr->ucr1, port->membase + UCR1);
321 writel(ucr->ucr2, port->membase + UCR2);
322 writel(ucr->ucr3, port->membase + UCR3);
323 }
324 #endif
325
326 /*
327 * Handle any change of modem status signal since we were last called.
328 */
329 static void imx_mctrl_check(struct imx_port *sport)
330 {
331 unsigned int status, changed;
332
333 status = sport->port.ops->get_mctrl(&sport->port);
334 changed = status ^ sport->old_status;
335
336 if (changed == 0)
337 return;
338
339 sport->old_status = status;
340
341 if (changed & TIOCM_RI)
342 sport->port.icount.rng++;
343 if (changed & TIOCM_DSR)
344 sport->port.icount.dsr++;
345 if (changed & TIOCM_CAR)
346 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
347 if (changed & TIOCM_CTS)
348 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
349
350 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
351 }
352
353 /*
354 * This is our per-port timeout handler, for checking the
355 * modem status signals.
356 */
357 static void imx_timeout(unsigned long data)
358 {
359 struct imx_port *sport = (struct imx_port *)data;
360 unsigned long flags;
361
362 if (sport->port.state) {
363 spin_lock_irqsave(&sport->port.lock, flags);
364 imx_mctrl_check(sport);
365 spin_unlock_irqrestore(&sport->port.lock, flags);
366
367 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
368 }
369 }
370
371 /*
372 * interrupts disabled on entry
373 */
374 static void imx_stop_tx(struct uart_port *port)
375 {
376 struct imx_port *sport = (struct imx_port *)port;
377 unsigned long temp;
378
379 if (USE_IRDA(sport)) {
380 /* half duplex - wait for end of transmission */
381 int n = 256;
382 while ((--n > 0) &&
383 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
384 udelay(5);
385 barrier();
386 }
387 /*
388 * irda transceiver - wait a bit more to avoid
389 * cutoff, hardware dependent
390 */
391 udelay(sport->trcv_delay);
392
393 /*
394 * half duplex - reactivate receive mode,
395 * flush receive pipe echo crap
396 */
397 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
398 temp = readl(sport->port.membase + UCR1);
399 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
400 writel(temp, sport->port.membase + UCR1);
401
402 temp = readl(sport->port.membase + UCR4);
403 temp &= ~(UCR4_TCEN);
404 writel(temp, sport->port.membase + UCR4);
405
406 while (readl(sport->port.membase + URXD0) &
407 URXD_CHARRDY)
408 barrier();
409
410 temp = readl(sport->port.membase + UCR1);
411 temp |= UCR1_RRDYEN;
412 writel(temp, sport->port.membase + UCR1);
413
414 temp = readl(sport->port.membase + UCR4);
415 temp |= UCR4_DREN;
416 writel(temp, sport->port.membase + UCR4);
417 }
418 return;
419 }
420
421 /*
422 * We are maybe in the SMP context, so if the DMA TX thread is running
423 * on other cpu, we have to wait for it to finish.
424 */
425 if (sport->dma_is_enabled && sport->dma_is_txing)
426 return;
427
428 temp = readl(sport->port.membase + UCR1);
429 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
430 }
431
432 /*
433 * interrupts disabled on entry
434 */
435 static void imx_stop_rx(struct uart_port *port)
436 {
437 struct imx_port *sport = (struct imx_port *)port;
438 unsigned long temp;
439
440 if (sport->dma_is_enabled && sport->dma_is_rxing) {
441 if (sport->port.suspended) {
442 dmaengine_terminate_all(sport->dma_chan_rx);
443 sport->dma_is_rxing = 0;
444 } else {
445 return;
446 }
447 }
448
449 temp = readl(sport->port.membase + UCR2);
450 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
451
452 /* disable the `Receiver Ready Interrrupt` */
453 temp = readl(sport->port.membase + UCR1);
454 writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);
455 }
456
457 /*
458 * Set the modem control timer to fire immediately.
459 */
460 static void imx_enable_ms(struct uart_port *port)
461 {
462 struct imx_port *sport = (struct imx_port *)port;
463
464 mod_timer(&sport->timer, jiffies);
465 }
466
467 static inline void imx_transmit_buffer(struct imx_port *sport)
468 {
469 struct circ_buf *xmit = &sport->port.state->xmit;
470
471 if (sport->port.x_char) {
472 /* Send next char */
473 writel(sport->port.x_char, sport->port.membase + URTX0);
474 return;
475 }
476
477 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
478 imx_stop_tx(&sport->port);
479 return;
480 }
481
482 while (!uart_circ_empty(xmit) &&
483 !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) {
484 /* send xmit->buf[xmit->tail]
485 * out the port here */
486 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
487 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
488 sport->port.icount.tx++;
489 }
490
491 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
492 uart_write_wakeup(&sport->port);
493
494 if (uart_circ_empty(xmit))
495 imx_stop_tx(&sport->port);
496 }
497
498 static void dma_tx_callback(void *data)
499 {
500 struct imx_port *sport = data;
501 struct scatterlist *sgl = &sport->tx_sgl[0];
502 struct circ_buf *xmit = &sport->port.state->xmit;
503 unsigned long flags;
504
505 spin_lock_irqsave(&sport->port.lock, flags);
506
507 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
508
509 /* update the stat */
510 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
511 sport->port.icount.tx += sport->tx_bytes;
512
513 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
514
515 sport->dma_is_txing = 0;
516
517 spin_unlock_irqrestore(&sport->port.lock, flags);
518
519 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
520 uart_write_wakeup(&sport->port);
521
522 if (waitqueue_active(&sport->dma_wait)) {
523 wake_up(&sport->dma_wait);
524 dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
525 return;
526 }
527 }
528
529 static void imx_dma_tx(struct imx_port *sport)
530 {
531 struct circ_buf *xmit = &sport->port.state->xmit;
532 struct scatterlist *sgl = sport->tx_sgl;
533 struct dma_async_tx_descriptor *desc;
534 struct dma_chan *chan = sport->dma_chan_tx;
535 struct device *dev = sport->port.dev;
536 int ret;
537
538 if (sport->dma_is_txing)
539 return;
540
541 sport->tx_bytes = uart_circ_chars_pending(xmit);
542
543 if (xmit->tail < xmit->head) {
544 sport->dma_tx_nents = 1;
545 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
546 } else {
547 sport->dma_tx_nents = 2;
548 sg_init_table(sgl, 2);
549 sg_set_buf(sgl, xmit->buf + xmit->tail,
550 UART_XMIT_SIZE - xmit->tail);
551 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
552 }
553
554 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
555 if (ret == 0) {
556 dev_err(dev, "DMA mapping error for TX.\n");
557 return;
558 }
559 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
560 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
561 if (!desc) {
562 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
563 DMA_TO_DEVICE);
564 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
565 return;
566 }
567 desc->callback = dma_tx_callback;
568 desc->callback_param = sport;
569
570 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
571 uart_circ_chars_pending(xmit));
572 /* fire it */
573 sport->dma_is_txing = 1;
574 dmaengine_submit(desc);
575 dma_async_issue_pending(chan);
576 return;
577 }
578
579 /*
580 * interrupts disabled on entry
581 */
582 static void imx_start_tx(struct uart_port *port)
583 {
584 struct imx_port *sport = (struct imx_port *)port;
585 unsigned long temp;
586
587 if (USE_IRDA(sport)) {
588 /* half duplex in IrDA mode; have to disable receive mode */
589 temp = readl(sport->port.membase + UCR4);
590 temp &= ~(UCR4_DREN);
591 writel(temp, sport->port.membase + UCR4);
592
593 temp = readl(sport->port.membase + UCR1);
594 temp &= ~(UCR1_RRDYEN);
595 writel(temp, sport->port.membase + UCR1);
596 }
597 /* Clear any pending ORE flag before enabling interrupt */
598 temp = readl(sport->port.membase + USR2);
599 writel(temp | USR2_ORE, sport->port.membase + USR2);
600
601 temp = readl(sport->port.membase + UCR4);
602 temp |= UCR4_OREN;
603 writel(temp, sport->port.membase + UCR4);
604
605 if (!sport->dma_is_enabled) {
606 temp = readl(sport->port.membase + UCR1);
607 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
608 }
609
610 if (USE_IRDA(sport)) {
611 temp = readl(sport->port.membase + UCR1);
612 temp |= UCR1_TRDYEN;
613 writel(temp, sport->port.membase + UCR1);
614
615 temp = readl(sport->port.membase + UCR4);
616 temp |= UCR4_TCEN;
617 writel(temp, sport->port.membase + UCR4);
618 }
619
620 if (sport->dma_is_enabled) {
621 /* FIXME: port->x_char must be transmitted if != 0 */
622 if (!uart_circ_empty(&port->state->xmit) &&
623 !uart_tx_stopped(port))
624 imx_dma_tx(sport);
625 return;
626 }
627 }
628
629 static irqreturn_t imx_rtsint(int irq, void *dev_id)
630 {
631 struct imx_port *sport = dev_id;
632 unsigned int val;
633 unsigned long flags;
634
635 spin_lock_irqsave(&sport->port.lock, flags);
636
637 writel(USR1_RTSD, sport->port.membase + USR1);
638 val = readl(sport->port.membase + USR1) & USR1_RTSS;
639 uart_handle_cts_change(&sport->port, !!val);
640 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
641
642 spin_unlock_irqrestore(&sport->port.lock, flags);
643 return IRQ_HANDLED;
644 }
645
646 static irqreturn_t imx_txint(int irq, void *dev_id)
647 {
648 struct imx_port *sport = dev_id;
649 unsigned long flags;
650
651 spin_lock_irqsave(&sport->port.lock, flags);
652 imx_transmit_buffer(sport);
653 spin_unlock_irqrestore(&sport->port.lock, flags);
654 return IRQ_HANDLED;
655 }
656
657 static irqreturn_t imx_rxint(int irq, void *dev_id)
658 {
659 struct imx_port *sport = dev_id;
660 unsigned int rx, flg, ignored = 0;
661 struct tty_port *port = &sport->port.state->port;
662 unsigned long flags, temp;
663
664 spin_lock_irqsave(&sport->port.lock, flags);
665
666 while (readl(sport->port.membase + USR2) & USR2_RDR) {
667 flg = TTY_NORMAL;
668 sport->port.icount.rx++;
669
670 rx = readl(sport->port.membase + URXD0);
671
672 temp = readl(sport->port.membase + USR2);
673 if (temp & USR2_BRCD) {
674 writel(USR2_BRCD, sport->port.membase + USR2);
675 if (uart_handle_break(&sport->port))
676 continue;
677 }
678
679 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
680 continue;
681
682 if (unlikely(rx & URXD_ERR)) {
683 if (rx & URXD_BRK)
684 sport->port.icount.brk++;
685 else if (rx & URXD_PRERR)
686 sport->port.icount.parity++;
687 else if (rx & URXD_FRMERR)
688 sport->port.icount.frame++;
689 if (rx & URXD_OVRRUN)
690 sport->port.icount.overrun++;
691
692 if (rx & sport->port.ignore_status_mask) {
693 if (++ignored > 100)
694 goto out;
695 continue;
696 }
697
698 rx &= sport->port.read_status_mask;
699
700 if (rx & URXD_BRK)
701 flg = TTY_BREAK;
702 else if (rx & URXD_PRERR)
703 flg = TTY_PARITY;
704 else if (rx & URXD_FRMERR)
705 flg = TTY_FRAME;
706 if (rx & URXD_OVRRUN)
707 flg = TTY_OVERRUN;
708
709 #ifdef SUPPORT_SYSRQ
710 sport->port.sysrq = 0;
711 #endif
712 }
713
714 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
715 goto out;
716
717 tty_insert_flip_char(port, rx, flg);
718 }
719
720 out:
721 spin_unlock_irqrestore(&sport->port.lock, flags);
722 tty_flip_buffer_push(port);
723 return IRQ_HANDLED;
724 }
725
726 static int start_rx_dma(struct imx_port *sport);
727 /*
728 * If the RXFIFO is filled with some data, and then we
729 * arise a DMA operation to receive them.
730 */
731 static void imx_dma_rxint(struct imx_port *sport)
732 {
733 unsigned long temp;
734 unsigned long flags;
735
736 spin_lock_irqsave(&sport->port.lock, flags);
737
738 temp = readl(sport->port.membase + USR2);
739 if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
740 sport->dma_is_rxing = 1;
741
742 /* disable the `Recerver Ready Interrrupt` */
743 temp = readl(sport->port.membase + UCR1);
744 temp &= ~(UCR1_RRDYEN);
745 writel(temp, sport->port.membase + UCR1);
746
747 /* tell the DMA to receive the data. */
748 start_rx_dma(sport);
749 }
750
751 spin_unlock_irqrestore(&sport->port.lock, flags);
752 }
753
754 static irqreturn_t imx_int(int irq, void *dev_id)
755 {
756 struct imx_port *sport = dev_id;
757 unsigned int sts;
758 unsigned int sts2;
759
760 sts = readl(sport->port.membase + USR1);
761
762 if (sts & USR1_RRDY) {
763 if (sport->dma_is_enabled)
764 imx_dma_rxint(sport);
765 else
766 imx_rxint(irq, dev_id);
767 }
768
769 if (sts & USR1_TRDY &&
770 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
771 imx_txint(irq, dev_id);
772
773 if (sts & USR1_RTSD)
774 imx_rtsint(irq, dev_id);
775
776 if (sts & USR1_AWAKE)
777 writel(USR1_AWAKE, sport->port.membase + USR1);
778
779 sts2 = readl(sport->port.membase + USR2);
780 if (sts2 & USR2_ORE) {
781 dev_err(sport->port.dev, "Rx FIFO overrun\n");
782 sport->port.icount.overrun++;
783 writel(sts2 | USR2_ORE, sport->port.membase + USR2);
784 }
785
786 return IRQ_HANDLED;
787 }
788
789 /*
790 * Return TIOCSER_TEMT when transmitter is not busy.
791 */
792 static unsigned int imx_tx_empty(struct uart_port *port)
793 {
794 struct imx_port *sport = (struct imx_port *)port;
795 unsigned int ret;
796
797 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
798
799 /* If the TX DMA is working, return 0. */
800 if (sport->dma_is_enabled && sport->dma_is_txing)
801 ret = 0;
802
803 return ret;
804 }
805
806 /*
807 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
808 */
809 static unsigned int imx_get_mctrl(struct uart_port *port)
810 {
811 struct imx_port *sport = (struct imx_port *)port;
812 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
813
814 if (readl(sport->port.membase + USR1) & USR1_RTSS)
815 tmp |= TIOCM_CTS;
816
817 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
818 tmp |= TIOCM_RTS;
819
820 if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP)
821 tmp |= TIOCM_LOOP;
822
823 return tmp;
824 }
825
826 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
827 {
828 struct imx_port *sport = (struct imx_port *)port;
829 unsigned long temp;
830
831 temp = readl(sport->port.membase + UCR2) & ~(UCR2_CTS | UCR2_CTSC);
832 if (mctrl & TIOCM_RTS)
833 temp |= UCR2_CTS | UCR2_CTSC;
834
835 writel(temp, sport->port.membase + UCR2);
836
837 temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
838 if (mctrl & TIOCM_LOOP)
839 temp |= UTS_LOOP;
840 writel(temp, sport->port.membase + uts_reg(sport));
841 }
842
843 /*
844 * Interrupts always disabled.
845 */
846 static void imx_break_ctl(struct uart_port *port, int break_state)
847 {
848 struct imx_port *sport = (struct imx_port *)port;
849 unsigned long flags, temp;
850
851 spin_lock_irqsave(&sport->port.lock, flags);
852
853 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
854
855 if (break_state != 0)
856 temp |= UCR1_SNDBRK;
857
858 writel(temp, sport->port.membase + UCR1);
859
860 spin_unlock_irqrestore(&sport->port.lock, flags);
861 }
862
863 #define TXTL 2 /* reset default */
864 #define RXTL 1 /* reset default */
865
866 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
867 {
868 unsigned int val;
869
870 /* set receiver / transmitter trigger level */
871 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
872 val |= TXTL << UFCR_TXTL_SHF | RXTL;
873 writel(val, sport->port.membase + UFCR);
874 return 0;
875 }
876
877 #define RX_BUF_SIZE (PAGE_SIZE)
878 static void imx_rx_dma_done(struct imx_port *sport)
879 {
880 unsigned long temp;
881 unsigned long flags;
882
883 spin_lock_irqsave(&sport->port.lock, flags);
884
885 /* Enable this interrupt when the RXFIFO is empty. */
886 temp = readl(sport->port.membase + UCR1);
887 temp |= UCR1_RRDYEN;
888 writel(temp, sport->port.membase + UCR1);
889
890 sport->dma_is_rxing = 0;
891
892 /* Is the shutdown waiting for us? */
893 if (waitqueue_active(&sport->dma_wait))
894 wake_up(&sport->dma_wait);
895
896 spin_unlock_irqrestore(&sport->port.lock, flags);
897 }
898
899 /*
900 * There are three kinds of RX DMA interrupts(such as in the MX6Q):
901 * [1] the RX DMA buffer is full.
902 * [2] the Aging timer expires(wait for 8 bytes long)
903 * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN).
904 *
905 * The [2] is trigger when a character was been sitting in the FIFO
906 * meanwhile [3] can wait for 32 bytes long when the RX line is
907 * on IDLE state and RxFIFO is empty.
908 */
909 static void dma_rx_callback(void *data)
910 {
911 struct imx_port *sport = data;
912 struct dma_chan *chan = sport->dma_chan_rx;
913 struct scatterlist *sgl = &sport->rx_sgl;
914 struct tty_port *port = &sport->port.state->port;
915 struct dma_tx_state state;
916 enum dma_status status;
917 unsigned int count;
918
919 /* unmap it first */
920 dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE);
921
922 status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
923 count = RX_BUF_SIZE - state.residue;
924 dev_dbg(sport->port.dev, "We get %d bytes.\n", count);
925
926 if (count) {
927 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ))
928 tty_insert_flip_string(port, sport->rx_buf, count);
929 tty_flip_buffer_push(port);
930
931 start_rx_dma(sport);
932 } else
933 imx_rx_dma_done(sport);
934 }
935
936 static int start_rx_dma(struct imx_port *sport)
937 {
938 struct scatterlist *sgl = &sport->rx_sgl;
939 struct dma_chan *chan = sport->dma_chan_rx;
940 struct device *dev = sport->port.dev;
941 struct dma_async_tx_descriptor *desc;
942 int ret;
943
944 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
945 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
946 if (ret == 0) {
947 dev_err(dev, "DMA mapping error for RX.\n");
948 return -EINVAL;
949 }
950 desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM,
951 DMA_PREP_INTERRUPT);
952 if (!desc) {
953 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
954 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
955 return -EINVAL;
956 }
957 desc->callback = dma_rx_callback;
958 desc->callback_param = sport;
959
960 dev_dbg(dev, "RX: prepare for the DMA.\n");
961 dmaengine_submit(desc);
962 dma_async_issue_pending(chan);
963 return 0;
964 }
965
966 static void imx_uart_dma_exit(struct imx_port *sport)
967 {
968 if (sport->dma_chan_rx) {
969 dma_release_channel(sport->dma_chan_rx);
970 sport->dma_chan_rx = NULL;
971
972 kfree(sport->rx_buf);
973 sport->rx_buf = NULL;
974 }
975
976 if (sport->dma_chan_tx) {
977 dma_release_channel(sport->dma_chan_tx);
978 sport->dma_chan_tx = NULL;
979 }
980
981 sport->dma_is_inited = 0;
982 }
983
984 static int imx_uart_dma_init(struct imx_port *sport)
985 {
986 struct dma_slave_config slave_config = {};
987 struct device *dev = sport->port.dev;
988 int ret;
989
990 /* Prepare for RX : */
991 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
992 if (!sport->dma_chan_rx) {
993 dev_dbg(dev, "cannot get the DMA channel.\n");
994 ret = -EINVAL;
995 goto err;
996 }
997
998 slave_config.direction = DMA_DEV_TO_MEM;
999 slave_config.src_addr = sport->port.mapbase + URXD0;
1000 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1001 slave_config.src_maxburst = RXTL;
1002 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1003 if (ret) {
1004 dev_err(dev, "error in RX dma configuration.\n");
1005 goto err;
1006 }
1007
1008 sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
1009 if (!sport->rx_buf) {
1010 ret = -ENOMEM;
1011 goto err;
1012 }
1013
1014 /* Prepare for TX : */
1015 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1016 if (!sport->dma_chan_tx) {
1017 dev_err(dev, "cannot get the TX DMA channel!\n");
1018 ret = -EINVAL;
1019 goto err;
1020 }
1021
1022 slave_config.direction = DMA_MEM_TO_DEV;
1023 slave_config.dst_addr = sport->port.mapbase + URTX0;
1024 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1025 slave_config.dst_maxburst = TXTL;
1026 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1027 if (ret) {
1028 dev_err(dev, "error in TX dma configuration.");
1029 goto err;
1030 }
1031
1032 sport->dma_is_inited = 1;
1033
1034 return 0;
1035 err:
1036 imx_uart_dma_exit(sport);
1037 return ret;
1038 }
1039
1040 static void imx_enable_dma(struct imx_port *sport)
1041 {
1042 unsigned long temp;
1043
1044 init_waitqueue_head(&sport->dma_wait);
1045
1046 /* set UCR1 */
1047 temp = readl(sport->port.membase + UCR1);
1048 temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN |
1049 /* wait for 32 idle frames for IDDMA interrupt */
1050 UCR1_ICD_REG(3);
1051 writel(temp, sport->port.membase + UCR1);
1052
1053 /* set UCR4 */
1054 temp = readl(sport->port.membase + UCR4);
1055 temp |= UCR4_IDDMAEN;
1056 writel(temp, sport->port.membase + UCR4);
1057
1058 sport->dma_is_enabled = 1;
1059 }
1060
1061 static void imx_disable_dma(struct imx_port *sport)
1062 {
1063 unsigned long temp;
1064
1065 /* clear UCR1 */
1066 temp = readl(sport->port.membase + UCR1);
1067 temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1068 writel(temp, sport->port.membase + UCR1);
1069
1070 /* clear UCR2 */
1071 temp = readl(sport->port.membase + UCR2);
1072 temp &= ~(UCR2_CTSC | UCR2_CTS);
1073 writel(temp, sport->port.membase + UCR2);
1074
1075 /* clear UCR4 */
1076 temp = readl(sport->port.membase + UCR4);
1077 temp &= ~UCR4_IDDMAEN;
1078 writel(temp, sport->port.membase + UCR4);
1079
1080 sport->dma_is_enabled = 0;
1081 }
1082
1083 /* half the RX buffer size */
1084 #define CTSTL 16
1085
1086 static int imx_startup(struct uart_port *port)
1087 {
1088 struct imx_port *sport = (struct imx_port *)port;
1089 int retval, i;
1090 unsigned long flags, temp;
1091
1092 retval = clk_prepare_enable(sport->clk_per);
1093 if (retval)
1094 return retval;
1095 retval = clk_prepare_enable(sport->clk_ipg);
1096 if (retval) {
1097 clk_disable_unprepare(sport->clk_per);
1098 return retval;
1099 }
1100
1101 imx_setup_ufcr(sport, 0);
1102
1103 /* disable the DREN bit (Data Ready interrupt enable) before
1104 * requesting IRQs
1105 */
1106 temp = readl(sport->port.membase + UCR4);
1107
1108 if (USE_IRDA(sport))
1109 temp |= UCR4_IRSC;
1110
1111 /* set the trigger level for CTS */
1112 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1113 temp |= CTSTL << UCR4_CTSTL_SHF;
1114
1115 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1116
1117 /* Reset fifo's and state machines */
1118 i = 100;
1119
1120 temp = readl(sport->port.membase + UCR2);
1121 temp &= ~UCR2_SRST;
1122 writel(temp, sport->port.membase + UCR2);
1123
1124 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1125 udelay(1);
1126
1127 spin_lock_irqsave(&sport->port.lock, flags);
1128 /*
1129 * Finally, clear and enable interrupts
1130 */
1131 writel(USR1_RTSD, sport->port.membase + USR1);
1132
1133 temp = readl(sport->port.membase + UCR1);
1134 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
1135
1136 if (USE_IRDA(sport)) {
1137 temp |= UCR1_IREN;
1138 temp &= ~(UCR1_RTSDEN);
1139 }
1140
1141 writel(temp, sport->port.membase + UCR1);
1142
1143 temp = readl(sport->port.membase + UCR2);
1144 temp |= (UCR2_RXEN | UCR2_TXEN);
1145 if (!sport->have_rtscts)
1146 temp |= UCR2_IRTS;
1147 writel(temp, sport->port.membase + UCR2);
1148
1149 if (!is_imx1_uart(sport)) {
1150 temp = readl(sport->port.membase + UCR3);
1151 temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
1152 writel(temp, sport->port.membase + UCR3);
1153 }
1154
1155 if (USE_IRDA(sport)) {
1156 temp = readl(sport->port.membase + UCR4);
1157 if (sport->irda_inv_rx)
1158 temp |= UCR4_INVR;
1159 else
1160 temp &= ~(UCR4_INVR);
1161 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
1162
1163 temp = readl(sport->port.membase + UCR3);
1164 if (sport->irda_inv_tx)
1165 temp |= UCR3_INVT;
1166 else
1167 temp &= ~(UCR3_INVT);
1168 writel(temp, sport->port.membase + UCR3);
1169 }
1170
1171 /*
1172 * Enable modem status interrupts
1173 */
1174 imx_enable_ms(&sport->port);
1175 spin_unlock_irqrestore(&sport->port.lock, flags);
1176
1177 if (USE_IRDA(sport)) {
1178 struct imxuart_platform_data *pdata;
1179 pdata = dev_get_platdata(sport->port.dev);
1180 sport->irda_inv_rx = pdata->irda_inv_rx;
1181 sport->irda_inv_tx = pdata->irda_inv_tx;
1182 sport->trcv_delay = pdata->transceiver_delay;
1183 if (pdata->irda_enable)
1184 pdata->irda_enable(1);
1185 }
1186
1187 return 0;
1188 }
1189
1190 static void imx_shutdown(struct uart_port *port)
1191 {
1192 struct imx_port *sport = (struct imx_port *)port;
1193 unsigned long temp;
1194 unsigned long flags;
1195
1196 if (sport->dma_is_enabled) {
1197 int ret;
1198
1199 /* We have to wait for the DMA to finish. */
1200 ret = wait_event_interruptible(sport->dma_wait,
1201 !sport->dma_is_rxing && !sport->dma_is_txing);
1202 if (ret != 0) {
1203 sport->dma_is_rxing = 0;
1204 sport->dma_is_txing = 0;
1205 dmaengine_terminate_all(sport->dma_chan_tx);
1206 dmaengine_terminate_all(sport->dma_chan_rx);
1207 }
1208 spin_lock_irqsave(&sport->port.lock, flags);
1209 imx_stop_tx(port);
1210 imx_stop_rx(port);
1211 imx_disable_dma(sport);
1212 spin_unlock_irqrestore(&sport->port.lock, flags);
1213 imx_uart_dma_exit(sport);
1214 }
1215
1216 spin_lock_irqsave(&sport->port.lock, flags);
1217 temp = readl(sport->port.membase + UCR2);
1218 temp &= ~(UCR2_TXEN);
1219 writel(temp, sport->port.membase + UCR2);
1220 spin_unlock_irqrestore(&sport->port.lock, flags);
1221
1222 if (USE_IRDA(sport)) {
1223 struct imxuart_platform_data *pdata;
1224 pdata = dev_get_platdata(sport->port.dev);
1225 if (pdata->irda_enable)
1226 pdata->irda_enable(0);
1227 }
1228
1229 /*
1230 * Stop our timer.
1231 */
1232 del_timer_sync(&sport->timer);
1233
1234 /*
1235 * Disable all interrupts, port and break condition.
1236 */
1237
1238 spin_lock_irqsave(&sport->port.lock, flags);
1239 temp = readl(sport->port.membase + UCR1);
1240 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
1241 if (USE_IRDA(sport))
1242 temp &= ~(UCR1_IREN);
1243
1244 writel(temp, sport->port.membase + UCR1);
1245 spin_unlock_irqrestore(&sport->port.lock, flags);
1246
1247 clk_disable_unprepare(sport->clk_per);
1248 clk_disable_unprepare(sport->clk_ipg);
1249 }
1250
1251 static void imx_flush_buffer(struct uart_port *port)
1252 {
1253 struct imx_port *sport = (struct imx_port *)port;
1254 struct scatterlist *sgl = &sport->tx_sgl[0];
1255
1256 if (!sport->dma_chan_tx)
1257 return;
1258
1259 sport->tx_bytes = 0;
1260 dmaengine_terminate_all(sport->dma_chan_tx);
1261 if (sport->dma_is_txing) {
1262 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1263 DMA_TO_DEVICE);
1264 sport->dma_is_txing = false;
1265 }
1266 }
1267
1268 static void
1269 imx_set_termios(struct uart_port *port, struct ktermios *termios,
1270 struct ktermios *old)
1271 {
1272 struct imx_port *sport = (struct imx_port *)port;
1273 unsigned long flags;
1274 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
1275 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1276 unsigned int div, ufcr;
1277 unsigned long num, denom;
1278 uint64_t tdiv64;
1279
1280 /*
1281 * If we don't support modem control lines, don't allow
1282 * these to be set.
1283 */
1284 if (0) {
1285 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
1286 termios->c_cflag |= CLOCAL;
1287 }
1288
1289 /*
1290 * We only support CS7 and CS8.
1291 */
1292 while ((termios->c_cflag & CSIZE) != CS7 &&
1293 (termios->c_cflag & CSIZE) != CS8) {
1294 termios->c_cflag &= ~CSIZE;
1295 termios->c_cflag |= old_csize;
1296 old_csize = CS8;
1297 }
1298
1299 if ((termios->c_cflag & CSIZE) == CS8)
1300 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1301 else
1302 ucr2 = UCR2_SRST | UCR2_IRTS;
1303
1304 if (termios->c_cflag & CRTSCTS) {
1305 if (sport->have_rtscts) {
1306 ucr2 &= ~UCR2_IRTS;
1307 ucr2 |= UCR2_CTSC;
1308
1309 /* Can we enable the DMA support? */
1310 if (is_imx6q_uart(sport) && !uart_console(port)
1311 && !sport->dma_is_inited)
1312 imx_uart_dma_init(sport);
1313 } else {
1314 termios->c_cflag &= ~CRTSCTS;
1315 }
1316 }
1317
1318 if (termios->c_cflag & CSTOPB)
1319 ucr2 |= UCR2_STPB;
1320 if (termios->c_cflag & PARENB) {
1321 ucr2 |= UCR2_PREN;
1322 if (termios->c_cflag & PARODD)
1323 ucr2 |= UCR2_PROE;
1324 }
1325
1326 del_timer_sync(&sport->timer);
1327
1328 /*
1329 * Ask the core to calculate the divisor for us.
1330 */
1331 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1332 quot = uart_get_divisor(port, baud);
1333
1334 spin_lock_irqsave(&sport->port.lock, flags);
1335
1336 sport->port.read_status_mask = 0;
1337 if (termios->c_iflag & INPCK)
1338 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1339 if (termios->c_iflag & (BRKINT | PARMRK))
1340 sport->port.read_status_mask |= URXD_BRK;
1341
1342 /*
1343 * Characters to ignore
1344 */
1345 sport->port.ignore_status_mask = 0;
1346 if (termios->c_iflag & IGNPAR)
1347 sport->port.ignore_status_mask |= URXD_PRERR;
1348 if (termios->c_iflag & IGNBRK) {
1349 sport->port.ignore_status_mask |= URXD_BRK;
1350 /*
1351 * If we're ignoring parity and break indicators,
1352 * ignore overruns too (for real raw support).
1353 */
1354 if (termios->c_iflag & IGNPAR)
1355 sport->port.ignore_status_mask |= URXD_OVRRUN;
1356 }
1357
1358 if ((termios->c_cflag & CREAD) == 0)
1359 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1360
1361 /*
1362 * Update the per-port timeout.
1363 */
1364 uart_update_timeout(port, termios->c_cflag, baud);
1365
1366 /*
1367 * disable interrupts and drain transmitter
1368 */
1369 old_ucr1 = readl(sport->port.membase + UCR1);
1370 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1371 sport->port.membase + UCR1);
1372
1373 while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1374 barrier();
1375
1376 /* then, disable everything */
1377 old_txrxen = readl(sport->port.membase + UCR2);
1378 writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN),
1379 sport->port.membase + UCR2);
1380 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
1381
1382 if (USE_IRDA(sport)) {
1383 /*
1384 * use maximum available submodule frequency to
1385 * avoid missing short pulses due to low sampling rate
1386 */
1387 div = 1;
1388 } else {
1389 /* custom-baudrate handling */
1390 div = sport->port.uartclk / (baud * 16);
1391 if (baud == 38400 && quot != div)
1392 baud = sport->port.uartclk / (quot * 16);
1393
1394 div = sport->port.uartclk / (baud * 16);
1395 if (div > 7)
1396 div = 7;
1397 if (!div)
1398 div = 1;
1399 }
1400
1401 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1402 1 << 16, 1 << 16, &num, &denom);
1403
1404 tdiv64 = sport->port.uartclk;
1405 tdiv64 *= num;
1406 do_div(tdiv64, denom * 16 * div);
1407 tty_termios_encode_baud_rate(termios,
1408 (speed_t)tdiv64, (speed_t)tdiv64);
1409
1410 num -= 1;
1411 denom -= 1;
1412
1413 ufcr = readl(sport->port.membase + UFCR);
1414 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1415 if (sport->dte_mode)
1416 ufcr |= UFCR_DCEDTE;
1417 writel(ufcr, sport->port.membase + UFCR);
1418
1419 writel(num, sport->port.membase + UBIR);
1420 writel(denom, sport->port.membase + UBMR);
1421
1422 if (!is_imx1_uart(sport))
1423 writel(sport->port.uartclk / div / 1000,
1424 sport->port.membase + IMX21_ONEMS);
1425
1426 writel(old_ucr1, sport->port.membase + UCR1);
1427
1428 /* set the parity, stop bits and data size */
1429 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
1430
1431 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1432 imx_enable_ms(&sport->port);
1433
1434 if (sport->dma_is_inited && !sport->dma_is_enabled)
1435 imx_enable_dma(sport);
1436 spin_unlock_irqrestore(&sport->port.lock, flags);
1437 }
1438
1439 static const char *imx_type(struct uart_port *port)
1440 {
1441 struct imx_port *sport = (struct imx_port *)port;
1442
1443 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1444 }
1445
1446 /*
1447 * Configure/autoconfigure the port.
1448 */
1449 static void imx_config_port(struct uart_port *port, int flags)
1450 {
1451 struct imx_port *sport = (struct imx_port *)port;
1452
1453 if (flags & UART_CONFIG_TYPE)
1454 sport->port.type = PORT_IMX;
1455 }
1456
1457 /*
1458 * Verify the new serial_struct (for TIOCSSERIAL).
1459 * The only change we allow are to the flags and type, and
1460 * even then only between PORT_IMX and PORT_UNKNOWN
1461 */
1462 static int
1463 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1464 {
1465 struct imx_port *sport = (struct imx_port *)port;
1466 int ret = 0;
1467
1468 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1469 ret = -EINVAL;
1470 if (sport->port.irq != ser->irq)
1471 ret = -EINVAL;
1472 if (ser->io_type != UPIO_MEM)
1473 ret = -EINVAL;
1474 if (sport->port.uartclk / 16 != ser->baud_base)
1475 ret = -EINVAL;
1476 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1477 ret = -EINVAL;
1478 if (sport->port.iobase != ser->port)
1479 ret = -EINVAL;
1480 if (ser->hub6 != 0)
1481 ret = -EINVAL;
1482 return ret;
1483 }
1484
1485 #if defined(CONFIG_CONSOLE_POLL)
1486
1487 static int imx_poll_init(struct uart_port *port)
1488 {
1489 struct imx_port *sport = (struct imx_port *)port;
1490 unsigned long flags;
1491 unsigned long temp;
1492 int retval;
1493
1494 retval = clk_prepare_enable(sport->clk_ipg);
1495 if (retval)
1496 return retval;
1497 retval = clk_prepare_enable(sport->clk_per);
1498 if (retval)
1499 clk_disable_unprepare(sport->clk_ipg);
1500
1501 imx_setup_ufcr(sport, 0);
1502
1503 spin_lock_irqsave(&sport->port.lock, flags);
1504
1505 temp = readl(sport->port.membase + UCR1);
1506 if (is_imx1_uart(sport))
1507 temp |= IMX1_UCR1_UARTCLKEN;
1508 temp |= UCR1_UARTEN | UCR1_RRDYEN;
1509 temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN);
1510 writel(temp, sport->port.membase + UCR1);
1511
1512 temp = readl(sport->port.membase + UCR2);
1513 temp |= UCR2_RXEN;
1514 writel(temp, sport->port.membase + UCR2);
1515
1516 spin_unlock_irqrestore(&sport->port.lock, flags);
1517
1518 return 0;
1519 }
1520
1521 static int imx_poll_get_char(struct uart_port *port)
1522 {
1523 if (!(readl_relaxed(port->membase + USR2) & USR2_RDR))
1524 return NO_POLL_CHAR;
1525
1526 return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA;
1527 }
1528
1529 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1530 {
1531 unsigned int status;
1532
1533 /* drain */
1534 do {
1535 status = readl_relaxed(port->membase + USR1);
1536 } while (~status & USR1_TRDY);
1537
1538 /* write */
1539 writel_relaxed(c, port->membase + URTX0);
1540
1541 /* flush */
1542 do {
1543 status = readl_relaxed(port->membase + USR2);
1544 } while (~status & USR2_TXDC);
1545 }
1546 #endif
1547
1548 static struct uart_ops imx_pops = {
1549 .tx_empty = imx_tx_empty,
1550 .set_mctrl = imx_set_mctrl,
1551 .get_mctrl = imx_get_mctrl,
1552 .stop_tx = imx_stop_tx,
1553 .start_tx = imx_start_tx,
1554 .stop_rx = imx_stop_rx,
1555 .enable_ms = imx_enable_ms,
1556 .break_ctl = imx_break_ctl,
1557 .startup = imx_startup,
1558 .shutdown = imx_shutdown,
1559 .flush_buffer = imx_flush_buffer,
1560 .set_termios = imx_set_termios,
1561 .type = imx_type,
1562 .config_port = imx_config_port,
1563 .verify_port = imx_verify_port,
1564 #if defined(CONFIG_CONSOLE_POLL)
1565 .poll_init = imx_poll_init,
1566 .poll_get_char = imx_poll_get_char,
1567 .poll_put_char = imx_poll_put_char,
1568 #endif
1569 };
1570
1571 static struct imx_port *imx_ports[UART_NR];
1572
1573 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1574 static void imx_console_putchar(struct uart_port *port, int ch)
1575 {
1576 struct imx_port *sport = (struct imx_port *)port;
1577
1578 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1579 barrier();
1580
1581 writel(ch, sport->port.membase + URTX0);
1582 }
1583
1584 /*
1585 * Interrupts are disabled on entering
1586 */
1587 static void
1588 imx_console_write(struct console *co, const char *s, unsigned int count)
1589 {
1590 struct imx_port *sport = imx_ports[co->index];
1591 struct imx_port_ucrs old_ucr;
1592 unsigned int ucr1;
1593 unsigned long flags = 0;
1594 int locked = 1;
1595 int retval;
1596
1597 retval = clk_enable(sport->clk_per);
1598 if (retval)
1599 return;
1600 retval = clk_enable(sport->clk_ipg);
1601 if (retval) {
1602 clk_disable(sport->clk_per);
1603 return;
1604 }
1605
1606 if (sport->port.sysrq)
1607 locked = 0;
1608 else if (oops_in_progress)
1609 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1610 else
1611 spin_lock_irqsave(&sport->port.lock, flags);
1612
1613 /*
1614 * First, save UCR1/2/3 and then disable interrupts
1615 */
1616 imx_port_ucrs_save(&sport->port, &old_ucr);
1617 ucr1 = old_ucr.ucr1;
1618
1619 if (is_imx1_uart(sport))
1620 ucr1 |= IMX1_UCR1_UARTCLKEN;
1621 ucr1 |= UCR1_UARTEN;
1622 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1623
1624 writel(ucr1, sport->port.membase + UCR1);
1625
1626 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1627
1628 uart_console_write(&sport->port, s, count, imx_console_putchar);
1629
1630 /*
1631 * Finally, wait for transmitter to become empty
1632 * and restore UCR1/2/3
1633 */
1634 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1635
1636 imx_port_ucrs_restore(&sport->port, &old_ucr);
1637
1638 if (locked)
1639 spin_unlock_irqrestore(&sport->port.lock, flags);
1640
1641 clk_disable(sport->clk_ipg);
1642 clk_disable(sport->clk_per);
1643 }
1644
1645 /*
1646 * If the port was already initialised (eg, by a boot loader),
1647 * try to determine the current setup.
1648 */
1649 static void __init
1650 imx_console_get_options(struct imx_port *sport, int *baud,
1651 int *parity, int *bits)
1652 {
1653
1654 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1655 /* ok, the port was enabled */
1656 unsigned int ucr2, ubir, ubmr, uartclk;
1657 unsigned int baud_raw;
1658 unsigned int ucfr_rfdiv;
1659
1660 ucr2 = readl(sport->port.membase + UCR2);
1661
1662 *parity = 'n';
1663 if (ucr2 & UCR2_PREN) {
1664 if (ucr2 & UCR2_PROE)
1665 *parity = 'o';
1666 else
1667 *parity = 'e';
1668 }
1669
1670 if (ucr2 & UCR2_WS)
1671 *bits = 8;
1672 else
1673 *bits = 7;
1674
1675 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1676 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1677
1678 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1679 if (ucfr_rfdiv == 6)
1680 ucfr_rfdiv = 7;
1681 else
1682 ucfr_rfdiv = 6 - ucfr_rfdiv;
1683
1684 uartclk = clk_get_rate(sport->clk_per);
1685 uartclk /= ucfr_rfdiv;
1686
1687 { /*
1688 * The next code provides exact computation of
1689 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1690 * without need of float support or long long division,
1691 * which would be required to prevent 32bit arithmetic overflow
1692 */
1693 unsigned int mul = ubir + 1;
1694 unsigned int div = 16 * (ubmr + 1);
1695 unsigned int rem = uartclk % div;
1696
1697 baud_raw = (uartclk / div) * mul;
1698 baud_raw += (rem * mul + div / 2) / div;
1699 *baud = (baud_raw + 50) / 100 * 100;
1700 }
1701
1702 if (*baud != baud_raw)
1703 pr_info("Console IMX rounded baud rate from %d to %d\n",
1704 baud_raw, *baud);
1705 }
1706 }
1707
1708 static int __init
1709 imx_console_setup(struct console *co, char *options)
1710 {
1711 struct imx_port *sport;
1712 int baud = 9600;
1713 int bits = 8;
1714 int parity = 'n';
1715 int flow = 'n';
1716 int retval;
1717
1718 /*
1719 * Check whether an invalid uart number has been specified, and
1720 * if so, search for the first available port that does have
1721 * console support.
1722 */
1723 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1724 co->index = 0;
1725 sport = imx_ports[co->index];
1726 if (sport == NULL)
1727 return -ENODEV;
1728
1729 /* For setting the registers, we only need to enable the ipg clock. */
1730 retval = clk_prepare_enable(sport->clk_ipg);
1731 if (retval)
1732 goto error_console;
1733
1734 if (options)
1735 uart_parse_options(options, &baud, &parity, &bits, &flow);
1736 else
1737 imx_console_get_options(sport, &baud, &parity, &bits);
1738
1739 imx_setup_ufcr(sport, 0);
1740
1741 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1742
1743 clk_disable(sport->clk_ipg);
1744 if (retval) {
1745 clk_unprepare(sport->clk_ipg);
1746 goto error_console;
1747 }
1748
1749 retval = clk_prepare(sport->clk_per);
1750 if (retval)
1751 clk_disable_unprepare(sport->clk_ipg);
1752
1753 error_console:
1754 return retval;
1755 }
1756
1757 static struct uart_driver imx_reg;
1758 static struct console imx_console = {
1759 .name = DEV_NAME,
1760 .write = imx_console_write,
1761 .device = uart_console_device,
1762 .setup = imx_console_setup,
1763 .flags = CON_PRINTBUFFER,
1764 .index = -1,
1765 .data = &imx_reg,
1766 };
1767
1768 #define IMX_CONSOLE &imx_console
1769 #else
1770 #define IMX_CONSOLE NULL
1771 #endif
1772
1773 static struct uart_driver imx_reg = {
1774 .owner = THIS_MODULE,
1775 .driver_name = DRIVER_NAME,
1776 .dev_name = DEV_NAME,
1777 .major = SERIAL_IMX_MAJOR,
1778 .minor = MINOR_START,
1779 .nr = ARRAY_SIZE(imx_ports),
1780 .cons = IMX_CONSOLE,
1781 };
1782
1783 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1784 {
1785 struct imx_port *sport = platform_get_drvdata(dev);
1786 unsigned int val;
1787
1788 /* enable wakeup from i.MX UART */
1789 val = readl(sport->port.membase + UCR3);
1790 val |= UCR3_AWAKEN;
1791 writel(val, sport->port.membase + UCR3);
1792
1793 uart_suspend_port(&imx_reg, &sport->port);
1794
1795 return 0;
1796 }
1797
1798 static int serial_imx_resume(struct platform_device *dev)
1799 {
1800 struct imx_port *sport = platform_get_drvdata(dev);
1801 unsigned int val;
1802
1803 /* disable wakeup from i.MX UART */
1804 val = readl(sport->port.membase + UCR3);
1805 val &= ~UCR3_AWAKEN;
1806 writel(val, sport->port.membase + UCR3);
1807
1808 uart_resume_port(&imx_reg, &sport->port);
1809
1810 return 0;
1811 }
1812
1813 #ifdef CONFIG_OF
1814 /*
1815 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1816 * could successfully get all information from dt or a negative errno.
1817 */
1818 static int serial_imx_probe_dt(struct imx_port *sport,
1819 struct platform_device *pdev)
1820 {
1821 struct device_node *np = pdev->dev.of_node;
1822 const struct of_device_id *of_id =
1823 of_match_device(imx_uart_dt_ids, &pdev->dev);
1824 int ret;
1825
1826 if (!np)
1827 /* no device tree device */
1828 return 1;
1829
1830 ret = of_alias_get_id(np, "serial");
1831 if (ret < 0) {
1832 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1833 return ret;
1834 }
1835 sport->port.line = ret;
1836
1837 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1838 sport->have_rtscts = 1;
1839
1840 if (of_get_property(np, "fsl,irda-mode", NULL))
1841 sport->use_irda = 1;
1842
1843 if (of_get_property(np, "fsl,dte-mode", NULL))
1844 sport->dte_mode = 1;
1845
1846 sport->devdata = of_id->data;
1847
1848 return 0;
1849 }
1850 #else
1851 static inline int serial_imx_probe_dt(struct imx_port *sport,
1852 struct platform_device *pdev)
1853 {
1854 return 1;
1855 }
1856 #endif
1857
1858 static void serial_imx_probe_pdata(struct imx_port *sport,
1859 struct platform_device *pdev)
1860 {
1861 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
1862
1863 sport->port.line = pdev->id;
1864 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1865
1866 if (!pdata)
1867 return;
1868
1869 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1870 sport->have_rtscts = 1;
1871
1872 if (pdata->flags & IMXUART_IRDA)
1873 sport->use_irda = 1;
1874 }
1875
1876 static int serial_imx_probe(struct platform_device *pdev)
1877 {
1878 struct imx_port *sport;
1879 void __iomem *base;
1880 int ret = 0;
1881 struct resource *res;
1882
1883 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1884 if (!sport)
1885 return -ENOMEM;
1886
1887 ret = serial_imx_probe_dt(sport, pdev);
1888 if (ret > 0)
1889 serial_imx_probe_pdata(sport, pdev);
1890 else if (ret < 0)
1891 return ret;
1892
1893 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1894 base = devm_ioremap_resource(&pdev->dev, res);
1895 if (IS_ERR(base))
1896 return PTR_ERR(base);
1897
1898 sport->port.dev = &pdev->dev;
1899 sport->port.mapbase = res->start;
1900 sport->port.membase = base;
1901 sport->port.type = PORT_IMX,
1902 sport->port.iotype = UPIO_MEM;
1903 sport->port.irq = platform_get_irq(pdev, 0);
1904 sport->rxirq = platform_get_irq(pdev, 0);
1905 sport->txirq = platform_get_irq(pdev, 1);
1906 sport->rtsirq = platform_get_irq(pdev, 2);
1907 sport->port.fifosize = 32;
1908 sport->port.ops = &imx_pops;
1909 sport->port.flags = UPF_BOOT_AUTOCONF;
1910 init_timer(&sport->timer);
1911 sport->timer.function = imx_timeout;
1912 sport->timer.data = (unsigned long)sport;
1913
1914 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1915 if (IS_ERR(sport->clk_ipg)) {
1916 ret = PTR_ERR(sport->clk_ipg);
1917 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
1918 return ret;
1919 }
1920
1921 sport->clk_per = devm_clk_get(&pdev->dev, "per");
1922 if (IS_ERR(sport->clk_per)) {
1923 ret = PTR_ERR(sport->clk_per);
1924 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
1925 return ret;
1926 }
1927
1928 sport->port.uartclk = clk_get_rate(sport->clk_per);
1929
1930 /*
1931 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
1932 * chips only have one interrupt.
1933 */
1934 if (sport->txirq > 0) {
1935 ret = devm_request_irq(&pdev->dev, sport->rxirq, imx_rxint, 0,
1936 dev_name(&pdev->dev), sport);
1937 if (ret)
1938 return ret;
1939
1940 ret = devm_request_irq(&pdev->dev, sport->txirq, imx_txint, 0,
1941 dev_name(&pdev->dev), sport);
1942 if (ret)
1943 return ret;
1944
1945 /* do not use RTS IRQ on IrDA */
1946 if (!USE_IRDA(sport)) {
1947 ret = devm_request_irq(&pdev->dev, sport->rtsirq,
1948 imx_rtsint, 0,
1949 dev_name(&pdev->dev), sport);
1950 if (ret)
1951 return ret;
1952 }
1953 } else {
1954 ret = devm_request_irq(&pdev->dev, sport->port.irq, imx_int, 0,
1955 dev_name(&pdev->dev), sport);
1956 if (ret)
1957 return ret;
1958 }
1959
1960 imx_ports[sport->port.line] = sport;
1961
1962 platform_set_drvdata(pdev, sport);
1963
1964 return uart_add_one_port(&imx_reg, &sport->port);
1965 }
1966
1967 static int serial_imx_remove(struct platform_device *pdev)
1968 {
1969 struct imx_port *sport = platform_get_drvdata(pdev);
1970
1971 return uart_remove_one_port(&imx_reg, &sport->port);
1972 }
1973
1974 static struct platform_driver serial_imx_driver = {
1975 .probe = serial_imx_probe,
1976 .remove = serial_imx_remove,
1977
1978 .suspend = serial_imx_suspend,
1979 .resume = serial_imx_resume,
1980 .id_table = imx_uart_devtype,
1981 .driver = {
1982 .name = "imx-uart",
1983 .of_match_table = imx_uart_dt_ids,
1984 },
1985 };
1986
1987 static int __init imx_serial_init(void)
1988 {
1989 int ret = uart_register_driver(&imx_reg);
1990
1991 if (ret)
1992 return ret;
1993
1994 ret = platform_driver_register(&serial_imx_driver);
1995 if (ret != 0)
1996 uart_unregister_driver(&imx_reg);
1997
1998 return ret;
1999 }
2000
2001 static void __exit imx_serial_exit(void)
2002 {
2003 platform_driver_unregister(&serial_imx_driver);
2004 uart_unregister_driver(&imx_reg);
2005 }
2006
2007 module_init(imx_serial_init);
2008 module_exit(imx_serial_exit);
2009
2010 MODULE_AUTHOR("Sascha Hauer");
2011 MODULE_DESCRIPTION("IMX generic serial port driver");
2012 MODULE_LICENSE("GPL");
2013 MODULE_ALIAS("platform:imx-uart");
Linux kernel - Deliverables
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