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952730ab90671b9e9cabea6c30d9d19310f589dc
[deliverable/linux.git] / drivers / tty / serial / imx.c
1 /*
2 * Driver for Motorola IMX serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
8 *
9 * Copyright (C) 2009 emlix GmbH
10 * Author: Fabian Godehardt (added IrDA support for iMX)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * [29-Mar-2005] Mike Lee
27 * Added hardware handshake
28 */
29
30 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31 #define SUPPORT_SYSRQ
32 #endif
33
34 #include <linux/module.h>
35 #include <linux/ioport.h>
36 #include <linux/init.h>
37 #include <linux/console.h>
38 #include <linux/sysrq.h>
39 #include <linux/platform_device.h>
40 #include <linux/tty.h>
41 #include <linux/tty_flip.h>
42 #include <linux/serial_core.h>
43 #include <linux/serial.h>
44 #include <linux/clk.h>
45 #include <linux/delay.h>
46 #include <linux/rational.h>
47 #include <linux/slab.h>
48 #include <linux/of.h>
49 #include <linux/of_device.h>
50 #include <linux/io.h>
51 #include <linux/dma-mapping.h>
52
53 #include <asm/irq.h>
54 #include <linux/platform_data/serial-imx.h>
55 #include <linux/platform_data/dma-imx.h>
56
57 /* Register definitions */
58 #define URXD0 0x0 /* Receiver Register */
59 #define URTX0 0x40 /* Transmitter Register */
60 #define UCR1 0x80 /* Control Register 1 */
61 #define UCR2 0x84 /* Control Register 2 */
62 #define UCR3 0x88 /* Control Register 3 */
63 #define UCR4 0x8c /* Control Register 4 */
64 #define UFCR 0x90 /* FIFO Control Register */
65 #define USR1 0x94 /* Status Register 1 */
66 #define USR2 0x98 /* Status Register 2 */
67 #define UESC 0x9c /* Escape Character Register */
68 #define UTIM 0xa0 /* Escape Timer Register */
69 #define UBIR 0xa4 /* BRM Incremental Register */
70 #define UBMR 0xa8 /* BRM Modulator Register */
71 #define UBRC 0xac /* Baud Rate Count Register */
72 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
73 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
74 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
75
76 /* UART Control Register Bit Fields.*/
77 #define URXD_DUMMY_READ (1<<16)
78 #define URXD_CHARRDY (1<<15)
79 #define URXD_ERR (1<<14)
80 #define URXD_OVRRUN (1<<13)
81 #define URXD_FRMERR (1<<12)
82 #define URXD_BRK (1<<11)
83 #define URXD_PRERR (1<<10)
84 #define URXD_RX_DATA (0xFF<<0)
85 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
86 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
87 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
88 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
89 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
90 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
91 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
92 #define UCR1_IREN (1<<7) /* Infrared interface enable */
93 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
94 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
95 #define UCR1_SNDBRK (1<<4) /* Send break */
96 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
97 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
98 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
99 #define UCR1_DOZE (1<<1) /* Doze */
100 #define UCR1_UARTEN (1<<0) /* UART enabled */
101 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
102 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
103 #define UCR2_CTSC (1<<13) /* CTS pin control */
104 #define UCR2_CTS (1<<12) /* Clear to send */
105 #define UCR2_ESCEN (1<<11) /* Escape enable */
106 #define UCR2_PREN (1<<8) /* Parity enable */
107 #define UCR2_PROE (1<<7) /* Parity odd/even */
108 #define UCR2_STPB (1<<6) /* Stop */
109 #define UCR2_WS (1<<5) /* Word size */
110 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
111 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
112 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
113 #define UCR2_RXEN (1<<1) /* Receiver enabled */
114 #define UCR2_SRST (1<<0) /* SW reset */
115 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
116 #define UCR3_PARERREN (1<<12) /* Parity enable */
117 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
118 #define UCR3_DSR (1<<10) /* Data set ready */
119 #define UCR3_DCD (1<<9) /* Data carrier detect */
120 #define UCR3_RI (1<<8) /* Ring indicator */
121 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
122 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
123 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
124 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
125 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
126 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
127 #define UCR3_BPEN (1<<0) /* Preset registers enable */
128 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
129 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
130 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
131 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
132 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
133 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
134 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
135 #define UCR4_IRSC (1<<5) /* IR special case */
136 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
137 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
138 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
139 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
140 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
141 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
142 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
143 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
144 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
145 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
146 #define USR1_RTSS (1<<14) /* RTS pin status */
147 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
148 #define USR1_RTSD (1<<12) /* RTS delta */
149 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
150 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
151 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
152 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
153 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
154 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
155 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
156 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
157 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
158 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
159 #define USR2_IDLE (1<<12) /* Idle condition */
160 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
161 #define USR2_WAKE (1<<7) /* Wake */
162 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
163 #define USR2_TXDC (1<<3) /* Transmitter complete */
164 #define USR2_BRCD (1<<2) /* Break condition */
165 #define USR2_ORE (1<<1) /* Overrun error */
166 #define USR2_RDR (1<<0) /* Recv data ready */
167 #define UTS_FRCPERR (1<<13) /* Force parity error */
168 #define UTS_LOOP (1<<12) /* Loop tx and rx */
169 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
170 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
171 #define UTS_TXFULL (1<<4) /* TxFIFO full */
172 #define UTS_RXFULL (1<<3) /* RxFIFO full */
173 #define UTS_SOFTRST (1<<0) /* Software reset */
174
175 /* We've been assigned a range on the "Low-density serial ports" major */
176 #define SERIAL_IMX_MAJOR 207
177 #define MINOR_START 16
178 #define DEV_NAME "ttymxc"
179
180 /*
181 * This determines how often we check the modem status signals
182 * for any change. They generally aren't connected to an IRQ
183 * so we have to poll them. We also check immediately before
184 * filling the TX fifo incase CTS has been dropped.
185 */
186 #define MCTRL_TIMEOUT (250*HZ/1000)
187
188 #define DRIVER_NAME "IMX-uart"
189
190 #define UART_NR 8
191
192 /* i.mx21 type uart runs on all i.mx except i.mx1 */
193 enum imx_uart_type {
194 IMX1_UART,
195 IMX21_UART,
196 IMX6Q_UART,
197 };
198
199 /* device type dependent stuff */
200 struct imx_uart_data {
201 unsigned uts_reg;
202 enum imx_uart_type devtype;
203 };
204
205 struct imx_port {
206 struct uart_port port;
207 struct timer_list timer;
208 unsigned int old_status;
209 int txirq, rxirq, rtsirq;
210 unsigned int have_rtscts:1;
211 unsigned int dte_mode:1;
212 unsigned int use_irda:1;
213 unsigned int irda_inv_rx:1;
214 unsigned int irda_inv_tx:1;
215 unsigned short trcv_delay; /* transceiver delay */
216 struct clk *clk_ipg;
217 struct clk *clk_per;
218 const struct imx_uart_data *devdata;
219
220 /* DMA fields */
221 unsigned int dma_is_inited:1;
222 unsigned int dma_is_enabled:1;
223 unsigned int dma_is_rxing:1;
224 unsigned int dma_is_txing:1;
225 struct dma_chan *dma_chan_rx, *dma_chan_tx;
226 struct scatterlist rx_sgl, tx_sgl[2];
227 void *rx_buf;
228 unsigned int tx_bytes;
229 unsigned int dma_tx_nents;
230 wait_queue_head_t dma_wait;
231 };
232
233 struct imx_port_ucrs {
234 unsigned int ucr1;
235 unsigned int ucr2;
236 unsigned int ucr3;
237 };
238
239 #ifdef CONFIG_IRDA
240 #define USE_IRDA(sport) ((sport)->use_irda)
241 #else
242 #define USE_IRDA(sport) (0)
243 #endif
244
245 static struct imx_uart_data imx_uart_devdata[] = {
246 [IMX1_UART] = {
247 .uts_reg = IMX1_UTS,
248 .devtype = IMX1_UART,
249 },
250 [IMX21_UART] = {
251 .uts_reg = IMX21_UTS,
252 .devtype = IMX21_UART,
253 },
254 [IMX6Q_UART] = {
255 .uts_reg = IMX21_UTS,
256 .devtype = IMX6Q_UART,
257 },
258 };
259
260 static struct platform_device_id imx_uart_devtype[] = {
261 {
262 .name = "imx1-uart",
263 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
264 }, {
265 .name = "imx21-uart",
266 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
267 }, {
268 .name = "imx6q-uart",
269 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
270 }, {
271 /* sentinel */
272 }
273 };
274 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
275
276 static struct of_device_id imx_uart_dt_ids[] = {
277 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
278 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
279 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
280 { /* sentinel */ }
281 };
282 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
283
284 static inline unsigned uts_reg(struct imx_port *sport)
285 {
286 return sport->devdata->uts_reg;
287 }
288
289 static inline int is_imx1_uart(struct imx_port *sport)
290 {
291 return sport->devdata->devtype == IMX1_UART;
292 }
293
294 static inline int is_imx21_uart(struct imx_port *sport)
295 {
296 return sport->devdata->devtype == IMX21_UART;
297 }
298
299 static inline int is_imx6q_uart(struct imx_port *sport)
300 {
301 return sport->devdata->devtype == IMX6Q_UART;
302 }
303 /*
304 * Save and restore functions for UCR1, UCR2 and UCR3 registers
305 */
306 #if defined(CONFIG_SERIAL_IMX_CONSOLE)
307 static void imx_port_ucrs_save(struct uart_port *port,
308 struct imx_port_ucrs *ucr)
309 {
310 /* save control registers */
311 ucr->ucr1 = readl(port->membase + UCR1);
312 ucr->ucr2 = readl(port->membase + UCR2);
313 ucr->ucr3 = readl(port->membase + UCR3);
314 }
315
316 static void imx_port_ucrs_restore(struct uart_port *port,
317 struct imx_port_ucrs *ucr)
318 {
319 /* restore control registers */
320 writel(ucr->ucr1, port->membase + UCR1);
321 writel(ucr->ucr2, port->membase + UCR2);
322 writel(ucr->ucr3, port->membase + UCR3);
323 }
324 #endif
325
326 /*
327 * Handle any change of modem status signal since we were last called.
328 */
329 static void imx_mctrl_check(struct imx_port *sport)
330 {
331 unsigned int status, changed;
332
333 status = sport->port.ops->get_mctrl(&sport->port);
334 changed = status ^ sport->old_status;
335
336 if (changed == 0)
337 return;
338
339 sport->old_status = status;
340
341 if (changed & TIOCM_RI)
342 sport->port.icount.rng++;
343 if (changed & TIOCM_DSR)
344 sport->port.icount.dsr++;
345 if (changed & TIOCM_CAR)
346 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
347 if (changed & TIOCM_CTS)
348 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
349
350 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
351 }
352
353 /*
354 * This is our per-port timeout handler, for checking the
355 * modem status signals.
356 */
357 static void imx_timeout(unsigned long data)
358 {
359 struct imx_port *sport = (struct imx_port *)data;
360 unsigned long flags;
361
362 if (sport->port.state) {
363 spin_lock_irqsave(&sport->port.lock, flags);
364 imx_mctrl_check(sport);
365 spin_unlock_irqrestore(&sport->port.lock, flags);
366
367 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
368 }
369 }
370
371 /*
372 * interrupts disabled on entry
373 */
374 static void imx_stop_tx(struct uart_port *port)
375 {
376 struct imx_port *sport = (struct imx_port *)port;
377 unsigned long temp;
378
379 if (USE_IRDA(sport)) {
380 /* half duplex - wait for end of transmission */
381 int n = 256;
382 while ((--n > 0) &&
383 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
384 udelay(5);
385 barrier();
386 }
387 /*
388 * irda transceiver - wait a bit more to avoid
389 * cutoff, hardware dependent
390 */
391 udelay(sport->trcv_delay);
392
393 /*
394 * half duplex - reactivate receive mode,
395 * flush receive pipe echo crap
396 */
397 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
398 temp = readl(sport->port.membase + UCR1);
399 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
400 writel(temp, sport->port.membase + UCR1);
401
402 temp = readl(sport->port.membase + UCR4);
403 temp &= ~(UCR4_TCEN);
404 writel(temp, sport->port.membase + UCR4);
405
406 while (readl(sport->port.membase + URXD0) &
407 URXD_CHARRDY)
408 barrier();
409
410 temp = readl(sport->port.membase + UCR1);
411 temp |= UCR1_RRDYEN;
412 writel(temp, sport->port.membase + UCR1);
413
414 temp = readl(sport->port.membase + UCR4);
415 temp |= UCR4_DREN;
416 writel(temp, sport->port.membase + UCR4);
417 }
418 return;
419 }
420
421 /*
422 * We are maybe in the SMP context, so if the DMA TX thread is running
423 * on other cpu, we have to wait for it to finish.
424 */
425 if (sport->dma_is_enabled && sport->dma_is_txing)
426 return;
427
428 temp = readl(sport->port.membase + UCR1);
429 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
430 }
431
432 /*
433 * interrupts disabled on entry
434 */
435 static void imx_stop_rx(struct uart_port *port)
436 {
437 struct imx_port *sport = (struct imx_port *)port;
438 unsigned long temp;
439
440 if (sport->dma_is_enabled && sport->dma_is_rxing) {
441 if (sport->port.suspended) {
442 dmaengine_terminate_all(sport->dma_chan_rx);
443 sport->dma_is_rxing = 0;
444 } else {
445 return;
446 }
447 }
448
449 temp = readl(sport->port.membase + UCR2);
450 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
451
452 /* disable the `Receiver Ready Interrrupt` */
453 temp = readl(sport->port.membase + UCR1);
454 writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);
455 }
456
457 /*
458 * Set the modem control timer to fire immediately.
459 */
460 static void imx_enable_ms(struct uart_port *port)
461 {
462 struct imx_port *sport = (struct imx_port *)port;
463
464 mod_timer(&sport->timer, jiffies);
465 }
466
467 static inline void imx_transmit_buffer(struct imx_port *sport)
468 {
469 struct circ_buf *xmit = &sport->port.state->xmit;
470
471 if (sport->port.x_char) {
472 /* Send next char */
473 writel(sport->port.x_char, sport->port.membase + URTX0);
474 return;
475 }
476
477 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
478 imx_stop_tx(&sport->port);
479 return;
480 }
481
482 while (!uart_circ_empty(xmit) &&
483 !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) {
484 /* send xmit->buf[xmit->tail]
485 * out the port here */
486 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
487 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
488 sport->port.icount.tx++;
489 }
490
491 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
492 uart_write_wakeup(&sport->port);
493
494 if (uart_circ_empty(xmit))
495 imx_stop_tx(&sport->port);
496 }
497
498 static void dma_tx_callback(void *data)
499 {
500 struct imx_port *sport = data;
501 struct scatterlist *sgl = &sport->tx_sgl[0];
502 struct circ_buf *xmit = &sport->port.state->xmit;
503 unsigned long flags;
504
505 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
506
507 sport->dma_is_txing = 0;
508
509 /* update the stat */
510 spin_lock_irqsave(&sport->port.lock, flags);
511 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
512 sport->port.icount.tx += sport->tx_bytes;
513 spin_unlock_irqrestore(&sport->port.lock, flags);
514
515 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
516
517 uart_write_wakeup(&sport->port);
518
519 if (waitqueue_active(&sport->dma_wait)) {
520 wake_up(&sport->dma_wait);
521 dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
522 return;
523 }
524 }
525
526 static void imx_dma_tx(struct imx_port *sport)
527 {
528 struct circ_buf *xmit = &sport->port.state->xmit;
529 struct scatterlist *sgl = sport->tx_sgl;
530 struct dma_async_tx_descriptor *desc;
531 struct dma_chan *chan = sport->dma_chan_tx;
532 struct device *dev = sport->port.dev;
533 enum dma_status status;
534 int ret;
535
536 status = dmaengine_tx_status(chan, (dma_cookie_t)0, NULL);
537 if (DMA_IN_PROGRESS == status)
538 return;
539
540 sport->tx_bytes = uart_circ_chars_pending(xmit);
541
542 if (xmit->tail < xmit->head) {
543 sport->dma_tx_nents = 1;
544 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
545 } else {
546 sport->dma_tx_nents = 2;
547 sg_init_table(sgl, 2);
548 sg_set_buf(sgl, xmit->buf + xmit->tail,
549 UART_XMIT_SIZE - xmit->tail);
550 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
551 }
552
553 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
554 if (ret == 0) {
555 dev_err(dev, "DMA mapping error for TX.\n");
556 return;
557 }
558 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
559 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
560 if (!desc) {
561 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
562 DMA_TO_DEVICE);
563 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
564 return;
565 }
566 desc->callback = dma_tx_callback;
567 desc->callback_param = sport;
568
569 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
570 uart_circ_chars_pending(xmit));
571 /* fire it */
572 sport->dma_is_txing = 1;
573 dmaengine_submit(desc);
574 dma_async_issue_pending(chan);
575 return;
576 }
577
578 /*
579 * interrupts disabled on entry
580 */
581 static void imx_start_tx(struct uart_port *port)
582 {
583 struct imx_port *sport = (struct imx_port *)port;
584 unsigned long temp;
585
586 if (USE_IRDA(sport)) {
587 /* half duplex in IrDA mode; have to disable receive mode */
588 temp = readl(sport->port.membase + UCR4);
589 temp &= ~(UCR4_DREN);
590 writel(temp, sport->port.membase + UCR4);
591
592 temp = readl(sport->port.membase + UCR1);
593 temp &= ~(UCR1_RRDYEN);
594 writel(temp, sport->port.membase + UCR1);
595 }
596 /* Clear any pending ORE flag before enabling interrupt */
597 temp = readl(sport->port.membase + USR2);
598 writel(temp | USR2_ORE, sport->port.membase + USR2);
599
600 temp = readl(sport->port.membase + UCR4);
601 temp |= UCR4_OREN;
602 writel(temp, sport->port.membase + UCR4);
603
604 if (!sport->dma_is_enabled) {
605 temp = readl(sport->port.membase + UCR1);
606 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
607 }
608
609 if (USE_IRDA(sport)) {
610 temp = readl(sport->port.membase + UCR1);
611 temp |= UCR1_TRDYEN;
612 writel(temp, sport->port.membase + UCR1);
613
614 temp = readl(sport->port.membase + UCR4);
615 temp |= UCR4_TCEN;
616 writel(temp, sport->port.membase + UCR4);
617 }
618
619 if (sport->dma_is_enabled) {
620 /* FIXME: port->x_char must be transmitted if != 0 */
621 if (!uart_circ_empty(&port->state->xmit) &&
622 !uart_tx_stopped(port))
623 imx_dma_tx(sport);
624 return;
625 }
626 }
627
628 static irqreturn_t imx_rtsint(int irq, void *dev_id)
629 {
630 struct imx_port *sport = dev_id;
631 unsigned int val;
632 unsigned long flags;
633
634 spin_lock_irqsave(&sport->port.lock, flags);
635
636 writel(USR1_RTSD, sport->port.membase + USR1);
637 val = readl(sport->port.membase + USR1) & USR1_RTSS;
638 uart_handle_cts_change(&sport->port, !!val);
639 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
640
641 spin_unlock_irqrestore(&sport->port.lock, flags);
642 return IRQ_HANDLED;
643 }
644
645 static irqreturn_t imx_txint(int irq, void *dev_id)
646 {
647 struct imx_port *sport = dev_id;
648 unsigned long flags;
649
650 spin_lock_irqsave(&sport->port.lock, flags);
651 imx_transmit_buffer(sport);
652 spin_unlock_irqrestore(&sport->port.lock, flags);
653 return IRQ_HANDLED;
654 }
655
656 static irqreturn_t imx_rxint(int irq, void *dev_id)
657 {
658 struct imx_port *sport = dev_id;
659 unsigned int rx, flg, ignored = 0;
660 struct tty_port *port = &sport->port.state->port;
661 unsigned long flags, temp;
662
663 spin_lock_irqsave(&sport->port.lock, flags);
664
665 while (readl(sport->port.membase + USR2) & USR2_RDR) {
666 flg = TTY_NORMAL;
667 sport->port.icount.rx++;
668
669 rx = readl(sport->port.membase + URXD0);
670
671 temp = readl(sport->port.membase + USR2);
672 if (temp & USR2_BRCD) {
673 writel(USR2_BRCD, sport->port.membase + USR2);
674 if (uart_handle_break(&sport->port))
675 continue;
676 }
677
678 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
679 continue;
680
681 if (unlikely(rx & URXD_ERR)) {
682 if (rx & URXD_BRK)
683 sport->port.icount.brk++;
684 else if (rx & URXD_PRERR)
685 sport->port.icount.parity++;
686 else if (rx & URXD_FRMERR)
687 sport->port.icount.frame++;
688 if (rx & URXD_OVRRUN)
689 sport->port.icount.overrun++;
690
691 if (rx & sport->port.ignore_status_mask) {
692 if (++ignored > 100)
693 goto out;
694 continue;
695 }
696
697 rx &= sport->port.read_status_mask;
698
699 if (rx & URXD_BRK)
700 flg = TTY_BREAK;
701 else if (rx & URXD_PRERR)
702 flg = TTY_PARITY;
703 else if (rx & URXD_FRMERR)
704 flg = TTY_FRAME;
705 if (rx & URXD_OVRRUN)
706 flg = TTY_OVERRUN;
707
708 #ifdef SUPPORT_SYSRQ
709 sport->port.sysrq = 0;
710 #endif
711 }
712
713 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
714 goto out;
715
716 tty_insert_flip_char(port, rx, flg);
717 }
718
719 out:
720 spin_unlock_irqrestore(&sport->port.lock, flags);
721 tty_flip_buffer_push(port);
722 return IRQ_HANDLED;
723 }
724
725 static int start_rx_dma(struct imx_port *sport);
726 /*
727 * If the RXFIFO is filled with some data, and then we
728 * arise a DMA operation to receive them.
729 */
730 static void imx_dma_rxint(struct imx_port *sport)
731 {
732 unsigned long temp;
733 unsigned long flags;
734
735 spin_lock_irqsave(&sport->port.lock, flags);
736
737 temp = readl(sport->port.membase + USR2);
738 if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
739 sport->dma_is_rxing = 1;
740
741 /* disable the `Recerver Ready Interrrupt` */
742 temp = readl(sport->port.membase + UCR1);
743 temp &= ~(UCR1_RRDYEN);
744 writel(temp, sport->port.membase + UCR1);
745
746 /* tell the DMA to receive the data. */
747 start_rx_dma(sport);
748 }
749
750 spin_unlock_irqrestore(&sport->port.lock, flags);
751 }
752
753 static irqreturn_t imx_int(int irq, void *dev_id)
754 {
755 struct imx_port *sport = dev_id;
756 unsigned int sts;
757 unsigned int sts2;
758
759 sts = readl(sport->port.membase + USR1);
760
761 if (sts & USR1_RRDY) {
762 if (sport->dma_is_enabled)
763 imx_dma_rxint(sport);
764 else
765 imx_rxint(irq, dev_id);
766 }
767
768 if (sts & USR1_TRDY &&
769 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
770 imx_txint(irq, dev_id);
771
772 if (sts & USR1_RTSD)
773 imx_rtsint(irq, dev_id);
774
775 if (sts & USR1_AWAKE)
776 writel(USR1_AWAKE, sport->port.membase + USR1);
777
778 sts2 = readl(sport->port.membase + USR2);
779 if (sts2 & USR2_ORE) {
780 dev_err(sport->port.dev, "Rx FIFO overrun\n");
781 sport->port.icount.overrun++;
782 writel(sts2 | USR2_ORE, sport->port.membase + USR2);
783 }
784
785 return IRQ_HANDLED;
786 }
787
788 /*
789 * Return TIOCSER_TEMT when transmitter is not busy.
790 */
791 static unsigned int imx_tx_empty(struct uart_port *port)
792 {
793 struct imx_port *sport = (struct imx_port *)port;
794 unsigned int ret;
795
796 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
797
798 /* If the TX DMA is working, return 0. */
799 if (sport->dma_is_enabled && sport->dma_is_txing)
800 ret = 0;
801
802 return ret;
803 }
804
805 /*
806 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
807 */
808 static unsigned int imx_get_mctrl(struct uart_port *port)
809 {
810 struct imx_port *sport = (struct imx_port *)port;
811 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
812
813 if (readl(sport->port.membase + USR1) & USR1_RTSS)
814 tmp |= TIOCM_CTS;
815
816 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
817 tmp |= TIOCM_RTS;
818
819 if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP)
820 tmp |= TIOCM_LOOP;
821
822 return tmp;
823 }
824
825 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
826 {
827 struct imx_port *sport = (struct imx_port *)port;
828 unsigned long temp;
829
830 temp = readl(sport->port.membase + UCR2) & ~(UCR2_CTS | UCR2_CTSC);
831 if (mctrl & TIOCM_RTS)
832 temp |= UCR2_CTS | UCR2_CTSC;
833
834 writel(temp, sport->port.membase + UCR2);
835
836 temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
837 if (mctrl & TIOCM_LOOP)
838 temp |= UTS_LOOP;
839 writel(temp, sport->port.membase + uts_reg(sport));
840 }
841
842 /*
843 * Interrupts always disabled.
844 */
845 static void imx_break_ctl(struct uart_port *port, int break_state)
846 {
847 struct imx_port *sport = (struct imx_port *)port;
848 unsigned long flags, temp;
849
850 spin_lock_irqsave(&sport->port.lock, flags);
851
852 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
853
854 if (break_state != 0)
855 temp |= UCR1_SNDBRK;
856
857 writel(temp, sport->port.membase + UCR1);
858
859 spin_unlock_irqrestore(&sport->port.lock, flags);
860 }
861
862 #define TXTL 2 /* reset default */
863 #define RXTL 1 /* reset default */
864
865 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
866 {
867 unsigned int val;
868
869 /* set receiver / transmitter trigger level */
870 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
871 val |= TXTL << UFCR_TXTL_SHF | RXTL;
872 writel(val, sport->port.membase + UFCR);
873 return 0;
874 }
875
876 #define RX_BUF_SIZE (PAGE_SIZE)
877 static void imx_rx_dma_done(struct imx_port *sport)
878 {
879 unsigned long temp;
880 unsigned long flags;
881
882 spin_lock_irqsave(&sport->port.lock, flags);
883
884 /* Enable this interrupt when the RXFIFO is empty. */
885 temp = readl(sport->port.membase + UCR1);
886 temp |= UCR1_RRDYEN;
887 writel(temp, sport->port.membase + UCR1);
888
889 sport->dma_is_rxing = 0;
890
891 /* Is the shutdown waiting for us? */
892 if (waitqueue_active(&sport->dma_wait))
893 wake_up(&sport->dma_wait);
894
895 spin_unlock_irqrestore(&sport->port.lock, flags);
896 }
897
898 /*
899 * There are three kinds of RX DMA interrupts(such as in the MX6Q):
900 * [1] the RX DMA buffer is full.
901 * [2] the Aging timer expires(wait for 8 bytes long)
902 * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN).
903 *
904 * The [2] is trigger when a character was been sitting in the FIFO
905 * meanwhile [3] can wait for 32 bytes long when the RX line is
906 * on IDLE state and RxFIFO is empty.
907 */
908 static void dma_rx_callback(void *data)
909 {
910 struct imx_port *sport = data;
911 struct dma_chan *chan = sport->dma_chan_rx;
912 struct scatterlist *sgl = &sport->rx_sgl;
913 struct tty_port *port = &sport->port.state->port;
914 struct dma_tx_state state;
915 enum dma_status status;
916 unsigned int count;
917
918 /* unmap it first */
919 dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE);
920
921 status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
922 count = RX_BUF_SIZE - state.residue;
923 dev_dbg(sport->port.dev, "We get %d bytes.\n", count);
924
925 if (count) {
926 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ))
927 tty_insert_flip_string(port, sport->rx_buf, count);
928 tty_flip_buffer_push(port);
929
930 start_rx_dma(sport);
931 } else
932 imx_rx_dma_done(sport);
933 }
934
935 static int start_rx_dma(struct imx_port *sport)
936 {
937 struct scatterlist *sgl = &sport->rx_sgl;
938 struct dma_chan *chan = sport->dma_chan_rx;
939 struct device *dev = sport->port.dev;
940 struct dma_async_tx_descriptor *desc;
941 int ret;
942
943 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
944 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
945 if (ret == 0) {
946 dev_err(dev, "DMA mapping error for RX.\n");
947 return -EINVAL;
948 }
949 desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM,
950 DMA_PREP_INTERRUPT);
951 if (!desc) {
952 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
953 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
954 return -EINVAL;
955 }
956 desc->callback = dma_rx_callback;
957 desc->callback_param = sport;
958
959 dev_dbg(dev, "RX: prepare for the DMA.\n");
960 dmaengine_submit(desc);
961 dma_async_issue_pending(chan);
962 return 0;
963 }
964
965 static void imx_uart_dma_exit(struct imx_port *sport)
966 {
967 if (sport->dma_chan_rx) {
968 dma_release_channel(sport->dma_chan_rx);
969 sport->dma_chan_rx = NULL;
970
971 kfree(sport->rx_buf);
972 sport->rx_buf = NULL;
973 }
974
975 if (sport->dma_chan_tx) {
976 dma_release_channel(sport->dma_chan_tx);
977 sport->dma_chan_tx = NULL;
978 }
979
980 sport->dma_is_inited = 0;
981 }
982
983 static int imx_uart_dma_init(struct imx_port *sport)
984 {
985 struct dma_slave_config slave_config = {};
986 struct device *dev = sport->port.dev;
987 int ret;
988
989 /* Prepare for RX : */
990 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
991 if (!sport->dma_chan_rx) {
992 dev_dbg(dev, "cannot get the DMA channel.\n");
993 ret = -EINVAL;
994 goto err;
995 }
996
997 slave_config.direction = DMA_DEV_TO_MEM;
998 slave_config.src_addr = sport->port.mapbase + URXD0;
999 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1000 slave_config.src_maxburst = RXTL;
1001 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1002 if (ret) {
1003 dev_err(dev, "error in RX dma configuration.\n");
1004 goto err;
1005 }
1006
1007 sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
1008 if (!sport->rx_buf) {
1009 ret = -ENOMEM;
1010 goto err;
1011 }
1012
1013 /* Prepare for TX : */
1014 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1015 if (!sport->dma_chan_tx) {
1016 dev_err(dev, "cannot get the TX DMA channel!\n");
1017 ret = -EINVAL;
1018 goto err;
1019 }
1020
1021 slave_config.direction = DMA_MEM_TO_DEV;
1022 slave_config.dst_addr = sport->port.mapbase + URTX0;
1023 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1024 slave_config.dst_maxburst = TXTL;
1025 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1026 if (ret) {
1027 dev_err(dev, "error in TX dma configuration.");
1028 goto err;
1029 }
1030
1031 sport->dma_is_inited = 1;
1032
1033 return 0;
1034 err:
1035 imx_uart_dma_exit(sport);
1036 return ret;
1037 }
1038
1039 static void imx_enable_dma(struct imx_port *sport)
1040 {
1041 unsigned long temp;
1042
1043 init_waitqueue_head(&sport->dma_wait);
1044
1045 /* set UCR1 */
1046 temp = readl(sport->port.membase + UCR1);
1047 temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN |
1048 /* wait for 32 idle frames for IDDMA interrupt */
1049 UCR1_ICD_REG(3);
1050 writel(temp, sport->port.membase + UCR1);
1051
1052 /* set UCR4 */
1053 temp = readl(sport->port.membase + UCR4);
1054 temp |= UCR4_IDDMAEN;
1055 writel(temp, sport->port.membase + UCR4);
1056
1057 sport->dma_is_enabled = 1;
1058 }
1059
1060 static void imx_disable_dma(struct imx_port *sport)
1061 {
1062 unsigned long temp;
1063
1064 /* clear UCR1 */
1065 temp = readl(sport->port.membase + UCR1);
1066 temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1067 writel(temp, sport->port.membase + UCR1);
1068
1069 /* clear UCR2 */
1070 temp = readl(sport->port.membase + UCR2);
1071 temp &= ~(UCR2_CTSC | UCR2_CTS);
1072 writel(temp, sport->port.membase + UCR2);
1073
1074 /* clear UCR4 */
1075 temp = readl(sport->port.membase + UCR4);
1076 temp &= ~UCR4_IDDMAEN;
1077 writel(temp, sport->port.membase + UCR4);
1078
1079 sport->dma_is_enabled = 0;
1080 }
1081
1082 /* half the RX buffer size */
1083 #define CTSTL 16
1084
1085 static int imx_startup(struct uart_port *port)
1086 {
1087 struct imx_port *sport = (struct imx_port *)port;
1088 int retval, i;
1089 unsigned long flags, temp;
1090
1091 retval = clk_prepare_enable(sport->clk_per);
1092 if (retval)
1093 return retval;
1094 retval = clk_prepare_enable(sport->clk_ipg);
1095 if (retval) {
1096 clk_disable_unprepare(sport->clk_per);
1097 return retval;
1098 }
1099
1100 imx_setup_ufcr(sport, 0);
1101
1102 /* disable the DREN bit (Data Ready interrupt enable) before
1103 * requesting IRQs
1104 */
1105 temp = readl(sport->port.membase + UCR4);
1106
1107 if (USE_IRDA(sport))
1108 temp |= UCR4_IRSC;
1109
1110 /* set the trigger level for CTS */
1111 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1112 temp |= CTSTL << UCR4_CTSTL_SHF;
1113
1114 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1115
1116 /* Reset fifo's and state machines */
1117 i = 100;
1118
1119 temp = readl(sport->port.membase + UCR2);
1120 temp &= ~UCR2_SRST;
1121 writel(temp, sport->port.membase + UCR2);
1122
1123 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1124 udelay(1);
1125
1126 spin_lock_irqsave(&sport->port.lock, flags);
1127 /*
1128 * Finally, clear and enable interrupts
1129 */
1130 writel(USR1_RTSD, sport->port.membase + USR1);
1131
1132 temp = readl(sport->port.membase + UCR1);
1133 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
1134
1135 if (USE_IRDA(sport)) {
1136 temp |= UCR1_IREN;
1137 temp &= ~(UCR1_RTSDEN);
1138 }
1139
1140 writel(temp, sport->port.membase + UCR1);
1141
1142 temp = readl(sport->port.membase + UCR2);
1143 temp |= (UCR2_RXEN | UCR2_TXEN);
1144 if (!sport->have_rtscts)
1145 temp |= UCR2_IRTS;
1146 writel(temp, sport->port.membase + UCR2);
1147
1148 if (!is_imx1_uart(sport)) {
1149 temp = readl(sport->port.membase + UCR3);
1150 temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
1151 writel(temp, sport->port.membase + UCR3);
1152 }
1153
1154 if (USE_IRDA(sport)) {
1155 temp = readl(sport->port.membase + UCR4);
1156 if (sport->irda_inv_rx)
1157 temp |= UCR4_INVR;
1158 else
1159 temp &= ~(UCR4_INVR);
1160 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
1161
1162 temp = readl(sport->port.membase + UCR3);
1163 if (sport->irda_inv_tx)
1164 temp |= UCR3_INVT;
1165 else
1166 temp &= ~(UCR3_INVT);
1167 writel(temp, sport->port.membase + UCR3);
1168 }
1169
1170 /*
1171 * Enable modem status interrupts
1172 */
1173 imx_enable_ms(&sport->port);
1174 spin_unlock_irqrestore(&sport->port.lock, flags);
1175
1176 if (USE_IRDA(sport)) {
1177 struct imxuart_platform_data *pdata;
1178 pdata = dev_get_platdata(sport->port.dev);
1179 sport->irda_inv_rx = pdata->irda_inv_rx;
1180 sport->irda_inv_tx = pdata->irda_inv_tx;
1181 sport->trcv_delay = pdata->transceiver_delay;
1182 if (pdata->irda_enable)
1183 pdata->irda_enable(1);
1184 }
1185
1186 return 0;
1187 }
1188
1189 static void imx_shutdown(struct uart_port *port)
1190 {
1191 struct imx_port *sport = (struct imx_port *)port;
1192 unsigned long temp;
1193 unsigned long flags;
1194
1195 if (sport->dma_is_enabled) {
1196 int ret;
1197
1198 /* We have to wait for the DMA to finish. */
1199 ret = wait_event_interruptible(sport->dma_wait,
1200 !sport->dma_is_rxing && !sport->dma_is_txing);
1201 if (ret != 0) {
1202 sport->dma_is_rxing = 0;
1203 sport->dma_is_txing = 0;
1204 dmaengine_terminate_all(sport->dma_chan_tx);
1205 dmaengine_terminate_all(sport->dma_chan_rx);
1206 }
1207 spin_lock_irqsave(&sport->port.lock, flags);
1208 imx_stop_tx(port);
1209 imx_stop_rx(port);
1210 imx_disable_dma(sport);
1211 spin_unlock_irqrestore(&sport->port.lock, flags);
1212 imx_uart_dma_exit(sport);
1213 }
1214
1215 spin_lock_irqsave(&sport->port.lock, flags);
1216 temp = readl(sport->port.membase + UCR2);
1217 temp &= ~(UCR2_TXEN);
1218 writel(temp, sport->port.membase + UCR2);
1219 spin_unlock_irqrestore(&sport->port.lock, flags);
1220
1221 if (USE_IRDA(sport)) {
1222 struct imxuart_platform_data *pdata;
1223 pdata = dev_get_platdata(sport->port.dev);
1224 if (pdata->irda_enable)
1225 pdata->irda_enable(0);
1226 }
1227
1228 /*
1229 * Stop our timer.
1230 */
1231 del_timer_sync(&sport->timer);
1232
1233 /*
1234 * Disable all interrupts, port and break condition.
1235 */
1236
1237 spin_lock_irqsave(&sport->port.lock, flags);
1238 temp = readl(sport->port.membase + UCR1);
1239 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
1240 if (USE_IRDA(sport))
1241 temp &= ~(UCR1_IREN);
1242
1243 writel(temp, sport->port.membase + UCR1);
1244 spin_unlock_irqrestore(&sport->port.lock, flags);
1245
1246 clk_disable_unprepare(sport->clk_per);
1247 clk_disable_unprepare(sport->clk_ipg);
1248 }
1249
1250 static void imx_flush_buffer(struct uart_port *port)
1251 {
1252 struct imx_port *sport = (struct imx_port *)port;
1253 struct scatterlist *sgl = &sport->tx_sgl[0];
1254
1255 if (!sport->dma_chan_tx)
1256 return;
1257
1258 sport->tx_bytes = 0;
1259 dmaengine_terminate_all(sport->dma_chan_tx);
1260 if (sport->dma_is_txing) {
1261 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1262 DMA_TO_DEVICE);
1263 sport->dma_is_txing = false;
1264 }
1265 }
1266
1267 static void
1268 imx_set_termios(struct uart_port *port, struct ktermios *termios,
1269 struct ktermios *old)
1270 {
1271 struct imx_port *sport = (struct imx_port *)port;
1272 unsigned long flags;
1273 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
1274 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1275 unsigned int div, ufcr;
1276 unsigned long num, denom;
1277 uint64_t tdiv64;
1278
1279 /*
1280 * If we don't support modem control lines, don't allow
1281 * these to be set.
1282 */
1283 if (0) {
1284 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
1285 termios->c_cflag |= CLOCAL;
1286 }
1287
1288 /*
1289 * We only support CS7 and CS8.
1290 */
1291 while ((termios->c_cflag & CSIZE) != CS7 &&
1292 (termios->c_cflag & CSIZE) != CS8) {
1293 termios->c_cflag &= ~CSIZE;
1294 termios->c_cflag |= old_csize;
1295 old_csize = CS8;
1296 }
1297
1298 if ((termios->c_cflag & CSIZE) == CS8)
1299 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1300 else
1301 ucr2 = UCR2_SRST | UCR2_IRTS;
1302
1303 if (termios->c_cflag & CRTSCTS) {
1304 if (sport->have_rtscts) {
1305 ucr2 &= ~UCR2_IRTS;
1306 ucr2 |= UCR2_CTSC;
1307
1308 /* Can we enable the DMA support? */
1309 if (is_imx6q_uart(sport) && !uart_console(port)
1310 && !sport->dma_is_inited)
1311 imx_uart_dma_init(sport);
1312 } else {
1313 termios->c_cflag &= ~CRTSCTS;
1314 }
1315 }
1316
1317 if (termios->c_cflag & CSTOPB)
1318 ucr2 |= UCR2_STPB;
1319 if (termios->c_cflag & PARENB) {
1320 ucr2 |= UCR2_PREN;
1321 if (termios->c_cflag & PARODD)
1322 ucr2 |= UCR2_PROE;
1323 }
1324
1325 del_timer_sync(&sport->timer);
1326
1327 /*
1328 * Ask the core to calculate the divisor for us.
1329 */
1330 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1331 quot = uart_get_divisor(port, baud);
1332
1333 spin_lock_irqsave(&sport->port.lock, flags);
1334
1335 sport->port.read_status_mask = 0;
1336 if (termios->c_iflag & INPCK)
1337 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1338 if (termios->c_iflag & (BRKINT | PARMRK))
1339 sport->port.read_status_mask |= URXD_BRK;
1340
1341 /*
1342 * Characters to ignore
1343 */
1344 sport->port.ignore_status_mask = 0;
1345 if (termios->c_iflag & IGNPAR)
1346 sport->port.ignore_status_mask |= URXD_PRERR;
1347 if (termios->c_iflag & IGNBRK) {
1348 sport->port.ignore_status_mask |= URXD_BRK;
1349 /*
1350 * If we're ignoring parity and break indicators,
1351 * ignore overruns too (for real raw support).
1352 */
1353 if (termios->c_iflag & IGNPAR)
1354 sport->port.ignore_status_mask |= URXD_OVRRUN;
1355 }
1356
1357 if ((termios->c_cflag & CREAD) == 0)
1358 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1359
1360 /*
1361 * Update the per-port timeout.
1362 */
1363 uart_update_timeout(port, termios->c_cflag, baud);
1364
1365 /*
1366 * disable interrupts and drain transmitter
1367 */
1368 old_ucr1 = readl(sport->port.membase + UCR1);
1369 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1370 sport->port.membase + UCR1);
1371
1372 while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1373 barrier();
1374
1375 /* then, disable everything */
1376 old_txrxen = readl(sport->port.membase + UCR2);
1377 writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN),
1378 sport->port.membase + UCR2);
1379 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
1380
1381 if (USE_IRDA(sport)) {
1382 /*
1383 * use maximum available submodule frequency to
1384 * avoid missing short pulses due to low sampling rate
1385 */
1386 div = 1;
1387 } else {
1388 /* custom-baudrate handling */
1389 div = sport->port.uartclk / (baud * 16);
1390 if (baud == 38400 && quot != div)
1391 baud = sport->port.uartclk / (quot * 16);
1392
1393 div = sport->port.uartclk / (baud * 16);
1394 if (div > 7)
1395 div = 7;
1396 if (!div)
1397 div = 1;
1398 }
1399
1400 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1401 1 << 16, 1 << 16, &num, &denom);
1402
1403 tdiv64 = sport->port.uartclk;
1404 tdiv64 *= num;
1405 do_div(tdiv64, denom * 16 * div);
1406 tty_termios_encode_baud_rate(termios,
1407 (speed_t)tdiv64, (speed_t)tdiv64);
1408
1409 num -= 1;
1410 denom -= 1;
1411
1412 ufcr = readl(sport->port.membase + UFCR);
1413 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1414 if (sport->dte_mode)
1415 ufcr |= UFCR_DCEDTE;
1416 writel(ufcr, sport->port.membase + UFCR);
1417
1418 writel(num, sport->port.membase + UBIR);
1419 writel(denom, sport->port.membase + UBMR);
1420
1421 if (!is_imx1_uart(sport))
1422 writel(sport->port.uartclk / div / 1000,
1423 sport->port.membase + IMX21_ONEMS);
1424
1425 writel(old_ucr1, sport->port.membase + UCR1);
1426
1427 /* set the parity, stop bits and data size */
1428 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
1429
1430 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1431 imx_enable_ms(&sport->port);
1432
1433 if (sport->dma_is_inited && !sport->dma_is_enabled)
1434 imx_enable_dma(sport);
1435 spin_unlock_irqrestore(&sport->port.lock, flags);
1436 }
1437
1438 static const char *imx_type(struct uart_port *port)
1439 {
1440 struct imx_port *sport = (struct imx_port *)port;
1441
1442 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1443 }
1444
1445 /*
1446 * Configure/autoconfigure the port.
1447 */
1448 static void imx_config_port(struct uart_port *port, int flags)
1449 {
1450 struct imx_port *sport = (struct imx_port *)port;
1451
1452 if (flags & UART_CONFIG_TYPE)
1453 sport->port.type = PORT_IMX;
1454 }
1455
1456 /*
1457 * Verify the new serial_struct (for TIOCSSERIAL).
1458 * The only change we allow are to the flags and type, and
1459 * even then only between PORT_IMX and PORT_UNKNOWN
1460 */
1461 static int
1462 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1463 {
1464 struct imx_port *sport = (struct imx_port *)port;
1465 int ret = 0;
1466
1467 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1468 ret = -EINVAL;
1469 if (sport->port.irq != ser->irq)
1470 ret = -EINVAL;
1471 if (ser->io_type != UPIO_MEM)
1472 ret = -EINVAL;
1473 if (sport->port.uartclk / 16 != ser->baud_base)
1474 ret = -EINVAL;
1475 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1476 ret = -EINVAL;
1477 if (sport->port.iobase != ser->port)
1478 ret = -EINVAL;
1479 if (ser->hub6 != 0)
1480 ret = -EINVAL;
1481 return ret;
1482 }
1483
1484 #if defined(CONFIG_CONSOLE_POLL)
1485
1486 static int imx_poll_init(struct uart_port *port)
1487 {
1488 struct imx_port *sport = (struct imx_port *)port;
1489 unsigned long flags;
1490 unsigned long temp;
1491 int retval;
1492
1493 retval = clk_prepare_enable(sport->clk_ipg);
1494 if (retval)
1495 return retval;
1496 retval = clk_prepare_enable(sport->clk_per);
1497 if (retval)
1498 clk_disable_unprepare(sport->clk_ipg);
1499
1500 imx_setup_ufcr(sport, 0);
1501
1502 spin_lock_irqsave(&sport->port.lock, flags);
1503
1504 temp = readl(sport->port.membase + UCR1);
1505 if (is_imx1_uart(sport))
1506 temp |= IMX1_UCR1_UARTCLKEN;
1507 temp |= UCR1_UARTEN | UCR1_RRDYEN;
1508 temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN);
1509 writel(temp, sport->port.membase + UCR1);
1510
1511 temp = readl(sport->port.membase + UCR2);
1512 temp |= UCR2_RXEN;
1513 writel(temp, sport->port.membase + UCR2);
1514
1515 spin_unlock_irqrestore(&sport->port.lock, flags);
1516
1517 return 0;
1518 }
1519
1520 static int imx_poll_get_char(struct uart_port *port)
1521 {
1522 if (!(readl_relaxed(port->membase + USR2) & USR2_RDR))
1523 return NO_POLL_CHAR;
1524
1525 return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA;
1526 }
1527
1528 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1529 {
1530 unsigned int status;
1531
1532 /* drain */
1533 do {
1534 status = readl_relaxed(port->membase + USR1);
1535 } while (~status & USR1_TRDY);
1536
1537 /* write */
1538 writel_relaxed(c, port->membase + URTX0);
1539
1540 /* flush */
1541 do {
1542 status = readl_relaxed(port->membase + USR2);
1543 } while (~status & USR2_TXDC);
1544 }
1545 #endif
1546
1547 static struct uart_ops imx_pops = {
1548 .tx_empty = imx_tx_empty,
1549 .set_mctrl = imx_set_mctrl,
1550 .get_mctrl = imx_get_mctrl,
1551 .stop_tx = imx_stop_tx,
1552 .start_tx = imx_start_tx,
1553 .stop_rx = imx_stop_rx,
1554 .enable_ms = imx_enable_ms,
1555 .break_ctl = imx_break_ctl,
1556 .startup = imx_startup,
1557 .shutdown = imx_shutdown,
1558 .flush_buffer = imx_flush_buffer,
1559 .set_termios = imx_set_termios,
1560 .type = imx_type,
1561 .config_port = imx_config_port,
1562 .verify_port = imx_verify_port,
1563 #if defined(CONFIG_CONSOLE_POLL)
1564 .poll_init = imx_poll_init,
1565 .poll_get_char = imx_poll_get_char,
1566 .poll_put_char = imx_poll_put_char,
1567 #endif
1568 };
1569
1570 static struct imx_port *imx_ports[UART_NR];
1571
1572 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1573 static void imx_console_putchar(struct uart_port *port, int ch)
1574 {
1575 struct imx_port *sport = (struct imx_port *)port;
1576
1577 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1578 barrier();
1579
1580 writel(ch, sport->port.membase + URTX0);
1581 }
1582
1583 /*
1584 * Interrupts are disabled on entering
1585 */
1586 static void
1587 imx_console_write(struct console *co, const char *s, unsigned int count)
1588 {
1589 struct imx_port *sport = imx_ports[co->index];
1590 struct imx_port_ucrs old_ucr;
1591 unsigned int ucr1;
1592 unsigned long flags = 0;
1593 int locked = 1;
1594 int retval;
1595
1596 retval = clk_enable(sport->clk_per);
1597 if (retval)
1598 return;
1599 retval = clk_enable(sport->clk_ipg);
1600 if (retval) {
1601 clk_disable(sport->clk_per);
1602 return;
1603 }
1604
1605 if (sport->port.sysrq)
1606 locked = 0;
1607 else if (oops_in_progress)
1608 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1609 else
1610 spin_lock_irqsave(&sport->port.lock, flags);
1611
1612 /*
1613 * First, save UCR1/2/3 and then disable interrupts
1614 */
1615 imx_port_ucrs_save(&sport->port, &old_ucr);
1616 ucr1 = old_ucr.ucr1;
1617
1618 if (is_imx1_uart(sport))
1619 ucr1 |= IMX1_UCR1_UARTCLKEN;
1620 ucr1 |= UCR1_UARTEN;
1621 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1622
1623 writel(ucr1, sport->port.membase + UCR1);
1624
1625 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1626
1627 uart_console_write(&sport->port, s, count, imx_console_putchar);
1628
1629 /*
1630 * Finally, wait for transmitter to become empty
1631 * and restore UCR1/2/3
1632 */
1633 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1634
1635 imx_port_ucrs_restore(&sport->port, &old_ucr);
1636
1637 if (locked)
1638 spin_unlock_irqrestore(&sport->port.lock, flags);
1639
1640 clk_disable(sport->clk_ipg);
1641 clk_disable(sport->clk_per);
1642 }
1643
1644 /*
1645 * If the port was already initialised (eg, by a boot loader),
1646 * try to determine the current setup.
1647 */
1648 static void __init
1649 imx_console_get_options(struct imx_port *sport, int *baud,
1650 int *parity, int *bits)
1651 {
1652
1653 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1654 /* ok, the port was enabled */
1655 unsigned int ucr2, ubir, ubmr, uartclk;
1656 unsigned int baud_raw;
1657 unsigned int ucfr_rfdiv;
1658
1659 ucr2 = readl(sport->port.membase + UCR2);
1660
1661 *parity = 'n';
1662 if (ucr2 & UCR2_PREN) {
1663 if (ucr2 & UCR2_PROE)
1664 *parity = 'o';
1665 else
1666 *parity = 'e';
1667 }
1668
1669 if (ucr2 & UCR2_WS)
1670 *bits = 8;
1671 else
1672 *bits = 7;
1673
1674 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1675 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1676
1677 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1678 if (ucfr_rfdiv == 6)
1679 ucfr_rfdiv = 7;
1680 else
1681 ucfr_rfdiv = 6 - ucfr_rfdiv;
1682
1683 uartclk = clk_get_rate(sport->clk_per);
1684 uartclk /= ucfr_rfdiv;
1685
1686 { /*
1687 * The next code provides exact computation of
1688 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1689 * without need of float support or long long division,
1690 * which would be required to prevent 32bit arithmetic overflow
1691 */
1692 unsigned int mul = ubir + 1;
1693 unsigned int div = 16 * (ubmr + 1);
1694 unsigned int rem = uartclk % div;
1695
1696 baud_raw = (uartclk / div) * mul;
1697 baud_raw += (rem * mul + div / 2) / div;
1698 *baud = (baud_raw + 50) / 100 * 100;
1699 }
1700
1701 if (*baud != baud_raw)
1702 pr_info("Console IMX rounded baud rate from %d to %d\n",
1703 baud_raw, *baud);
1704 }
1705 }
1706
1707 static int __init
1708 imx_console_setup(struct console *co, char *options)
1709 {
1710 struct imx_port *sport;
1711 int baud = 9600;
1712 int bits = 8;
1713 int parity = 'n';
1714 int flow = 'n';
1715 int retval;
1716
1717 /*
1718 * Check whether an invalid uart number has been specified, and
1719 * if so, search for the first available port that does have
1720 * console support.
1721 */
1722 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1723 co->index = 0;
1724 sport = imx_ports[co->index];
1725 if (sport == NULL)
1726 return -ENODEV;
1727
1728 /* For setting the registers, we only need to enable the ipg clock. */
1729 retval = clk_prepare_enable(sport->clk_ipg);
1730 if (retval)
1731 goto error_console;
1732
1733 if (options)
1734 uart_parse_options(options, &baud, &parity, &bits, &flow);
1735 else
1736 imx_console_get_options(sport, &baud, &parity, &bits);
1737
1738 imx_setup_ufcr(sport, 0);
1739
1740 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1741
1742 clk_disable(sport->clk_ipg);
1743 if (retval) {
1744 clk_unprepare(sport->clk_ipg);
1745 goto error_console;
1746 }
1747
1748 retval = clk_prepare(sport->clk_per);
1749 if (retval)
1750 clk_disable_unprepare(sport->clk_ipg);
1751
1752 error_console:
1753 return retval;
1754 }
1755
1756 static struct uart_driver imx_reg;
1757 static struct console imx_console = {
1758 .name = DEV_NAME,
1759 .write = imx_console_write,
1760 .device = uart_console_device,
1761 .setup = imx_console_setup,
1762 .flags = CON_PRINTBUFFER,
1763 .index = -1,
1764 .data = &imx_reg,
1765 };
1766
1767 #define IMX_CONSOLE &imx_console
1768 #else
1769 #define IMX_CONSOLE NULL
1770 #endif
1771
1772 static struct uart_driver imx_reg = {
1773 .owner = THIS_MODULE,
1774 .driver_name = DRIVER_NAME,
1775 .dev_name = DEV_NAME,
1776 .major = SERIAL_IMX_MAJOR,
1777 .minor = MINOR_START,
1778 .nr = ARRAY_SIZE(imx_ports),
1779 .cons = IMX_CONSOLE,
1780 };
1781
1782 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1783 {
1784 struct imx_port *sport = platform_get_drvdata(dev);
1785 unsigned int val;
1786
1787 /* enable wakeup from i.MX UART */
1788 val = readl(sport->port.membase + UCR3);
1789 val |= UCR3_AWAKEN;
1790 writel(val, sport->port.membase + UCR3);
1791
1792 uart_suspend_port(&imx_reg, &sport->port);
1793
1794 return 0;
1795 }
1796
1797 static int serial_imx_resume(struct platform_device *dev)
1798 {
1799 struct imx_port *sport = platform_get_drvdata(dev);
1800 unsigned int val;
1801
1802 /* disable wakeup from i.MX UART */
1803 val = readl(sport->port.membase + UCR3);
1804 val &= ~UCR3_AWAKEN;
1805 writel(val, sport->port.membase + UCR3);
1806
1807 uart_resume_port(&imx_reg, &sport->port);
1808
1809 return 0;
1810 }
1811
1812 #ifdef CONFIG_OF
1813 /*
1814 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1815 * could successfully get all information from dt or a negative errno.
1816 */
1817 static int serial_imx_probe_dt(struct imx_port *sport,
1818 struct platform_device *pdev)
1819 {
1820 struct device_node *np = pdev->dev.of_node;
1821 const struct of_device_id *of_id =
1822 of_match_device(imx_uart_dt_ids, &pdev->dev);
1823 int ret;
1824
1825 if (!np)
1826 /* no device tree device */
1827 return 1;
1828
1829 ret = of_alias_get_id(np, "serial");
1830 if (ret < 0) {
1831 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1832 return ret;
1833 }
1834 sport->port.line = ret;
1835
1836 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1837 sport->have_rtscts = 1;
1838
1839 if (of_get_property(np, "fsl,irda-mode", NULL))
1840 sport->use_irda = 1;
1841
1842 if (of_get_property(np, "fsl,dte-mode", NULL))
1843 sport->dte_mode = 1;
1844
1845 sport->devdata = of_id->data;
1846
1847 return 0;
1848 }
1849 #else
1850 static inline int serial_imx_probe_dt(struct imx_port *sport,
1851 struct platform_device *pdev)
1852 {
1853 return 1;
1854 }
1855 #endif
1856
1857 static void serial_imx_probe_pdata(struct imx_port *sport,
1858 struct platform_device *pdev)
1859 {
1860 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
1861
1862 sport->port.line = pdev->id;
1863 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1864
1865 if (!pdata)
1866 return;
1867
1868 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1869 sport->have_rtscts = 1;
1870
1871 if (pdata->flags & IMXUART_IRDA)
1872 sport->use_irda = 1;
1873 }
1874
1875 static int serial_imx_probe(struct platform_device *pdev)
1876 {
1877 struct imx_port *sport;
1878 void __iomem *base;
1879 int ret = 0;
1880 struct resource *res;
1881
1882 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1883 if (!sport)
1884 return -ENOMEM;
1885
1886 ret = serial_imx_probe_dt(sport, pdev);
1887 if (ret > 0)
1888 serial_imx_probe_pdata(sport, pdev);
1889 else if (ret < 0)
1890 return ret;
1891
1892 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1893 base = devm_ioremap_resource(&pdev->dev, res);
1894 if (IS_ERR(base))
1895 return PTR_ERR(base);
1896
1897 sport->port.dev = &pdev->dev;
1898 sport->port.mapbase = res->start;
1899 sport->port.membase = base;
1900 sport->port.type = PORT_IMX,
1901 sport->port.iotype = UPIO_MEM;
1902 sport->port.irq = platform_get_irq(pdev, 0);
1903 sport->rxirq = platform_get_irq(pdev, 0);
1904 sport->txirq = platform_get_irq(pdev, 1);
1905 sport->rtsirq = platform_get_irq(pdev, 2);
1906 sport->port.fifosize = 32;
1907 sport->port.ops = &imx_pops;
1908 sport->port.flags = UPF_BOOT_AUTOCONF;
1909 init_timer(&sport->timer);
1910 sport->timer.function = imx_timeout;
1911 sport->timer.data = (unsigned long)sport;
1912
1913 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1914 if (IS_ERR(sport->clk_ipg)) {
1915 ret = PTR_ERR(sport->clk_ipg);
1916 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
1917 return ret;
1918 }
1919
1920 sport->clk_per = devm_clk_get(&pdev->dev, "per");
1921 if (IS_ERR(sport->clk_per)) {
1922 ret = PTR_ERR(sport->clk_per);
1923 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
1924 return ret;
1925 }
1926
1927 sport->port.uartclk = clk_get_rate(sport->clk_per);
1928
1929 /*
1930 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
1931 * chips only have one interrupt.
1932 */
1933 if (sport->txirq > 0) {
1934 ret = devm_request_irq(&pdev->dev, sport->rxirq, imx_rxint, 0,
1935 dev_name(&pdev->dev), sport);
1936 if (ret)
1937 return ret;
1938
1939 ret = devm_request_irq(&pdev->dev, sport->txirq, imx_txint, 0,
1940 dev_name(&pdev->dev), sport);
1941 if (ret)
1942 return ret;
1943
1944 /* do not use RTS IRQ on IrDA */
1945 if (!USE_IRDA(sport)) {
1946 ret = devm_request_irq(&pdev->dev, sport->rtsirq,
1947 imx_rtsint, 0,
1948 dev_name(&pdev->dev), sport);
1949 if (ret)
1950 return ret;
1951 }
1952 } else {
1953 ret = devm_request_irq(&pdev->dev, sport->port.irq, imx_int, 0,
1954 dev_name(&pdev->dev), sport);
1955 if (ret)
1956 return ret;
1957 }
1958
1959 imx_ports[sport->port.line] = sport;
1960
1961 platform_set_drvdata(pdev, sport);
1962
1963 return uart_add_one_port(&imx_reg, &sport->port);
1964 }
1965
1966 static int serial_imx_remove(struct platform_device *pdev)
1967 {
1968 struct imx_port *sport = platform_get_drvdata(pdev);
1969
1970 return uart_remove_one_port(&imx_reg, &sport->port);
1971 }
1972
1973 static struct platform_driver serial_imx_driver = {
1974 .probe = serial_imx_probe,
1975 .remove = serial_imx_remove,
1976
1977 .suspend = serial_imx_suspend,
1978 .resume = serial_imx_resume,
1979 .id_table = imx_uart_devtype,
1980 .driver = {
1981 .name = "imx-uart",
1982 .of_match_table = imx_uart_dt_ids,
1983 },
1984 };
1985
1986 static int __init imx_serial_init(void)
1987 {
1988 int ret = uart_register_driver(&imx_reg);
1989
1990 if (ret)
1991 return ret;
1992
1993 ret = platform_driver_register(&serial_imx_driver);
1994 if (ret != 0)
1995 uart_unregister_driver(&imx_reg);
1996
1997 return ret;
1998 }
1999
2000 static void __exit imx_serial_exit(void)
2001 {
2002 platform_driver_unregister(&serial_imx_driver);
2003 uart_unregister_driver(&imx_reg);
2004 }
2005
2006 module_init(imx_serial_init);
2007 module_exit(imx_serial_exit);
2008
2009 MODULE_AUTHOR("Sascha Hauer");
2010 MODULE_DESCRIPTION("IMX generic serial port driver");
2011 MODULE_LICENSE("GPL");
2012 MODULE_ALIAS("platform:imx-uart");
Linux kernel - Deliverables
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